# SPARC T3

The SPARC T3 microprocessor (previously known as UltraSPARC T3, codenamed Rainbow Falls, and also known as UltraSPARC KT or Niagara-3 during development) is a multithreading, multi-core CPU produced by Oracle Corporation (previously Sun Microsystems). Officially launched on 20 September 2010, it is a member of the SPARC family, and the successor to the UltraSPARC T2.

## Performance

Overall single socket and multi-socket throughput increased with the T3 processor in systems, providing superior throughput with half the CPU socket requirements to its predecessor.
The throughput (SPEC CINT2006 rate) increased in single a socket T3-1 platform in comparison to its predecessor T2+ processor in a dual-socket T5240 platform.
Under simulated web serving workloads, dual-socket based SPARC T3 systems benchmarked better performance than quad-socket (previous generation) UltraSPARC T2+ systems (as well as competing dual and quad socket contemporary systems).

## History

Online IT publication The Register incorrectly reported in June 2008 that the microprocessor would have 16 cores, each with 16 threads. In September 2009 they published a roadmap that instead showed 8 threads per core. During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads. According to the ISSCC 2010 presentation:
   "A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to maximize throughput. The 6 MB L2 cache of 461 GB/s and the 308-pin SerDes I/O of 2.4 Tb/s support the required bandwidth. Six clock and four voltage domains, as well as power management and circuit techniques, optimize performance, power, variability and yield trade-offs across the 377mm$^2$ die."
Support for the UltraSPARC T3 was confirmed on July 16, 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris.
During Oracle OpenWorld in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" (dropping the "Ultra" prefix in its name), accompanied by new systems and new reported benchmarks claiming world-record performance. Varied real-world application benchmarks were released with full system disclosures. Internationally recognized SPEC benchmarks were also released with full system disclosures. Oracle disclosed that SPARC T3 was built with a 40 nm process.

## Features

SPARC T3 features include:
* 8 or 16 CPU cores
* 8 hardware threads per core
* 6 MB Level 2 cache
* 2 embedded coherency controllers
* 6 coherence links
* 14 unidirectional lanes per coherence link
* SMP to 4 sockets without glue circuitry
* 4 DDR3 SDRAM memory channels
* Embedded PCI Express I/O interfaces
* Security co-processor on each core. Supports DES, 3DES, AES, RC4, SHA-1, SHA-256/384/512, Kasumi, Galois Field, MD5, RSA with up to 2048 key, ECC, CRC.
* Hardware random number generator
* 2 embedded 1GigE/10GigE interfaces
* 2.4 Tbit/s aggregate throughput per socket

## Systems

With the release of the SPARC T3 chip, the new brand of Oracle SPARC T-series servers was introduced to the market, effectively replacing CMT (UltraSPARC T2/T2 Plus) machines from the previous SPARC Enterprise product line. Fewer physical products from the former server line were refreshed with the T3 chip, reducing the total number of servers respectively to four:
* One Socket SPARC T3-1 2U Rack Server
* One Socket SPARC T3-1B Blade Server
* Two Socket SPARC T3-2 Server
* Four Socket SPARC T3-4 Server

## Virtualization

Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Oracle VM Server for SPARC domains (a feature formerly known as Logical Domains).

## Performance improvement versus T2 and T2+

The SPARC T3 processor is effectively two T2+ processors on a single die. The T3 has:
* Double the cores (16) of a T2 or T2+
* Double the 10Gig Ethernet ports (2) over a T2+
* Double the crypto accelerator cores (16) over a T2 or T2+
* Crypto engines support more algorithms than the T2 or T2+ including: DES, Triple DES, AES, RC4, SHA-1, SHA256/384/512, Kasumi, Galois Field, MD5, RSA to 2048 key, ECC, CRC32
* Over 1.9x Cryptography Performance Throughput Increase
* Faster DDR3 RAM interface over the T2 or T2+ DDR2 interface
* Double the throughput
* Double the memory capacity
* Quadruple the I/O throughput
* Two PCIe 2.0 eight lane interfaces vs one PCIe former generation eight lane interface