# Intel Quark

Intel Quark is a line of 32-bit x86 SoCs and microcontrollers by Intel, designed for small size and low power consumption, and targeted at new markets including wearable devices. The line was introduced at Intel Developer Forum in 2013, and discontinued in January 2019.
Quark processors, while slower than Atom processors, are much smaller and consume less power. They lack support for SIMD instruction sets (such as MMX and SSE) and only support embedded operating systems.
Quark powers the (now discontinued) Intel Galileo developer microcontroller board. In 2016 Arduino released the Arduino 101 board that includes an Intel Quark SoC. The CPU instruction set is, for most models, the same as a Pentium (P54C/i586) CPU.

## History

The first product in the Quark line is the single-core 32 nm X1000 SoC with a clock rate of up to 400 MHz. The system includes several interfaces, including PCI Express, serial UART, I²C, Fast Ethernet, USB 2.0, SDIO, power management controller, and GPIO. There are 16 kB of on-chip embedded SRAM and an integrated DDR3 memory controller.
A second Intel product that includes Quark core, the Intel Edison microcomputer, was presented in January 2014. It has a form factor close to the size of an SD card, and is capable of wireless networking using Wi-Fi or Bluetooth.
In January 2015, Intel announced the sub-miniature Intel Curie module for wearable applications, based on a Quark SE core with 80 kB SRAM and 384 kB flash. At the size of a button, it also features a 6-axis accelerometer, a DSP sensor hub, a Bluetooth LE unit and a battery charge controller.
Intel announced the end-of-life of its Quark products in January 2019, with orders accepted until July 2019 and final shipments set for July 2022.

## List of processors
### "Lakemont" (32 nm)

The name Lakemont has been used in reference to the processor core in multiple Quark-series processors.$^{:4}$$^{:42}$

#### "Clanton"

Source:
* All models support i586 instruction set, with x87 FPU and NX bit
* Temperature range: -40 °C to +85 °C for X10x1 models, 0 °C to +70 °C, for X10x0 models
* Secure boot supported on X102x models
* DDR3 controller with one 16-bit channel
* Two PCI-Express 2.0 controllers, with 1 lane each.
* USB Controller with two USB 2.0 Host ports and one USB 2.0 device port
* Two 10/100 MBit Ethernet controllers
* Integrated memory card reader supporting SDIO 3.0, eMMC 4.41 and SD 3.0
* Serial I/O supporting SPI, UART (serial port) and I2C
(The L2 cache column shows the size of the L1 cache.)
| Model | sSpec number | Cores | Clock rate | GPU frequency | L2 cache | I/O bus | Memory | Voltage | TDP | Socket | Release date | Part number(s) | Release price (USD) |
| Quark X1000 | SR1BY (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q4'13 | DH8066101538300 | $9.63 |
| Quark X1001 | SR1VB (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q2'14 | DHQ1ET | $11.77 |
| Quark X1010 | SR1BZ (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 (ECC) | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q1'14 | DH8066101555100 | $10.16 |
| Quark X1011 | SR1VC (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 (ECC) | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q2'14 | DHQ1ECCET | $12.31 |
| Quark X1020 | SR1VW (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 (ECC) | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q2'14 | DHQ1ECCSECCTS1 | $11.45 |
| Quark X1020D | SR1BX (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 (ECC) | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q1'14 | DH8066101531900 | $10.70 |
| Quark X1021 | SR1WH (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 (ECC) | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q2'14 | DHQ1ECCSECETS1 | $13.39 |
| Quark X1021D | SR1VA (A0) | 1 | 400 MHz | — | 16 KB | PCIe | DDR3-800 (ECC) | 0.95–1.1 V | 2.2 W | FC-BGA11E | Q2'14 | DHQ1ECCSECET | $12.85 |

#### "Silver Butte"

* Implements only a limited subset of the 32-bit x86 instruction set (e.g. segmentation, BCD/string instructions, AF/PF flags, XCHG are not supported)
| Model | sSpec number | Cores | Clock rate | GPU frequency | L2 cache | I/O bus | Memory | Voltage | TDP | Socket | Release date | Part number(s) | Release price (USD) |
| Quark D1000 | SLKMJ (B1) | 1 | 32 MHz | — | | AHB-Lite, APB$^{:30}$ | eSRAM | 1.62–3.63 V | 0.025 W | QFN40 | Q3'15 | DMNIAD01SLVBT | $2.54 |

#### "Mint Valley"

* Supports i586 instruction set, without x87.
| Model | sSpec number | Cores | Clock rate | GPU frequency | L2 cache | I/O bus | Memory | Voltage | TDP | Socket | Release date | Part number(s) | Release price (USD) |
| Quark D2000 | SR2KF (A0) | 1 | 32 MHz | — | | AHB-Lite,$^{:72}$APB$^{:96}$ | eSRAM | 1.62–3.63 V | 0.025 W | QFN40 | Q3'15 | FND2000 | $2.54 |

#### "Atlas Peak"

* Supports i586 instruction set, without x87.
| Model | sSpec number | Cores | Clock rate | GPU frequency | L2 cache | I/O bus | Memory | Voltage | TDP | Socket | Release date | Part number(s) | Release price (USD) |
| Quark SE C1000 | SR2T6 (A0) SR2TJ (A1) | 1 | 32 MHz | — | 8 KB | AHB-Lite, APB | eSRAM | 1.8–3.3 V | 0.025 W | VFBGA144 | Q4'15 | LMCQ1000 | $10.32 |

## Segfault bug

Intel Quark SoC X1000 contains a bug (#71538) that "under specific circumstances" results in a type of crash known as a segfault. The workaround implemented by Intel is to omit LOCK prefixes (not required on single-threaded processors) in the compiled code. While source-based embedded systems like those built using the Yocto Project can incorporate this workaround at compile time, general purpose Linux distributions such as Debian are deeply affected by the bug. Such a workaround is not easy to implement in binaries meant to support multithreading too as they require LOCK prefixes to function properly.