# NetBurst

The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of central processing units (CPUs) made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2001, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.
NetBurst was replaced with the Core microarchitecture based on P6, released in July 2006.

## Technology

The NetBurst microarchitecture includes features such as Hyper-threading, Hyper Pipelined Technology, Rapid Execution Engine, Execution Trace Cache, and replay system which all were introduced for the first time in this particular microarchitecture, and some never appeared again afterwards.

### Hyper-threading

Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 processors. Intel introduced it with NetBurst processors in 2002. Later Intel reintroduced it in the Nehalem microarchitecture after its absence in the Core 2.

### Quad-Pumped Front-Side Bus

The Northwood and Willamette cores feature an external Front Side Bus (FSB) that runs at 100 MHz which transfers four bits per clock cycle, thus having an effective speed of 400 MHz. Later revisions of the Northwood core, along with the Prescott core (and derivatives) have an effective 800 MHz front-side bus (200 MHz quad pumped).

### Hyper-Pipelined Technology

The Willamette and Northwood cores contain a 20-stage instruction pipeline. This is a significant increase in the number of stages compared to the Pentium III, which had only 10 stages in its pipeline. The Prescott core increased the length of the pipeline to 31 stages. A drawback of longer pipelines is the increase in the number of stages that need to be traced back in the event of a branch misprediction, increasing the penalty of said misprediction. To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reduces branch mispredictions by 33% over Pentium III. In reality, the longer pipeline resulted in reduced efficiency through a lower number of instructions per clock (IPC) executed as high enough clock speeds were not able to be reached to offset lost performance due to larger than expected increase in power consumption and heat.

### Rapid Execution Engine

With this technology, the two arithmetic logic units (ALUs) in the core of the CPU are double-pumped, meaning that they actually operate at twice the core clock frequency. For example, in a 3.8 GHz processor, the ALUs will effectively be operating at 7.6 GHz. The reason behind this is to generally make up for the low IPC count; additionally this considerably enhances the integer performance of the CPU. Intel also replaced the high-speed barrel shifter with a shift/rotate execution unit that operates at the same frequency as the CPU core. The downside is that certain instructions are now much slower (relatively and absolutely) than before, making optimization for multiple target CPUs difficult. An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the i386, including the main competitor processor, Athlon.

### Execution Trace Cache

Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache. It stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving considerable time. Moreover, the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution. Intel later introduced a similar but simpler concept with Sandy Bridge called micro-operation cache (UOP cache).

### Replay system

The replay system is a subsystem within the Intel Pentium 4 processor to catch operations that have been mistakenly sent for execution by the processor's scheduler. Operations caught by the replay system are then re-executed in a loop until the conditions necessary for their proper execution have been fulfilled.

### Branch prediction hints

The Intel NetBurst architecture allows branch prediction hints to be inserted into the code to tell whether the static prediction should be taken or not taken, while this feature was abandoned in later Intel processors. According to Intel, NetBurst's branch prediction algorithm is 33% better than the one in P6.

## Scaling-up issues

Despite these enhancements, the NetBurst architecture created obstacles for engineers trying to scale up its performance. With this microarchitecture, Intel planned to attain clock speeds of 10 GHz, but because of rising clock speeds, Intel faced increasing problems with keeping power dissipation within acceptable limits. Intel reached a speed barrier of 3.8 GHz in November 2004 but encountered problems trying to achieve even that. Intel abandoned NetBurst in 2006 after the heat problems became unacceptable and then developed the Core microarchitecture, inspired by the P6 Core of the Pentium Pro to the Tualatin Pentium III-S, and most directly the Pentium M.

## Revisions

| Revision | Processor Brand(s) | Pipeline stages |
| Willamette (180 nm) | Celeron, Pentium 4, Xeon | 20 |
| Northwood (130 nm) | Celeron, Pentium 4, Pentium 4 HT, Pentium 4 HT Extreme Edition, Xeon | 20 |
| Prescott (90 nm) | Celeron D, Pentium 4, Pentium 4 HT, Pentium 4 HT Extreme Edition, Xeon | 31 |
| Cedar Mill (65 nm) | Celeron D, Pentium 4 HT | 31 |
| Smithfield (90 nm) | Pentium D, Xeon | 31 |
| Presler (65 nm) | Pentium D, Xeon | 31 |
Intel replaced the original Willamette core with a redesigned version of the NetBurst microarchitecture called Northwood in January 2002. The Northwood design combined an increased cache size, a smaller 130 nm fabrication process, and Hyper-threading (although initially all models but the 3.06 GHz model had this feature disabled) to produce a more modern, higher-performing version of the NetBurst microarchitecture.
In February 2004, Intel introduced Prescott, a more radical revision of the microarchitecture. The Prescott core was produced on a 90 nm process, and included several major design changes, including the addition of an even larger cache (from 512 KB in the Northwood to 1 MB, and 2 MB in Prescott 2M), a much deeper instruction pipeline (31 stages as compared to 20 in the Northwood), a heavily improved branch predictor, the introduction of the SSE3 instructions, and later, the implementation of Intel Extended Memory 64 Technology (EM64T), Intel's branding for their compatible implementation of the x86-64 64-bit version of the x86 microarchitecture (as with hyper-threading, all Prescott chips branded Pentium 4 HT have hardware to support this feature, but it was initially only enabled on the high-end Xeon processors, before being officially introduced in processors with the Pentium trademark). Power consumption and heat dissipation also became major issues with Prescott, which quickly became the hottest-running, and most power-hungry, of Intel's single-core x86 and x86-64 processors. Power and heat concerns prevented Intel from releasing a Prescott clocked above 3.8 GHz, along with a mobile version of the core clocked above 3.46 GHz.
Intel also released a dual-core processor based on the NetBurst microarchitecture branded Pentium D. The first Pentium D core was codenamed Smithfield, which is actually two Prescott cores in a single die, and later Presler, which consists of two Cedar Mill cores on two separate dies (Cedar Mill being the 65 nm die-shrink of Prescott).

## Roadmap

vteIntel CPU core roadmaps from P6 to Panther Lake :
Atom (ULV)
Node name
Pentium/Core
Microarch.
Step
Microarch.
Step
600 nm
P6
Pentium Pro (133 MHz)
500 nm
Pentium Pro (150 MHz)
350 nm
Pentium Pro (166–200 MHz)
Klamath
250 nm
Deschutes
Katmai
NetBurst
180 nm
Coppermine
Willamette
130 nm
Tualatin
Northwood
Pentium M
Banias
NetBurst(HT)
NetBurst(×2)
90 nm
Dothan
Prescott
Prescott‑2M
Smithfield
Tejas
Cedarmill (Tejas)
65 nm
Yonah
Nehalem (NetBurst)
Cedar Mill
Presler
Core
Merom
4 cores on mainstream desktop, DDR3 introduced
Bonnell
Bonnell
45 nm
Penryn
Nehalem
Nehalem
HT reintroduced, integrated MC, PCH L3-cache introduced, 256KB L2-cache/core
Saltwell
32 nm
Westmere
Introduced GPU on same package and AES-NI
Sandy Bridge
Sandy Bridge
On-die ring bus, no more non-UEFI motherboards
Silvermont
Silvermont
22 nm
Ivy Bridge
Haswell
Haswell
Fully integrated voltage regulator
Airmont
14 nm
Broadwell
Skylake
Skylake
DDR4 introduced on mainstream desktop
Goldmont
Goldmont
Kaby Lake
Coffee Lake
6 cores on mainstream desktop
Amber Lake
Mobile-only
Goldmont Plus
Goldmont Plus
Whiskey Lake
Mobile-only
Coffee Lake Refresh
8 cores on mainstream desktop
Comet Lake
10 cores on mainstream desktop
Sunny Cove
Cypress Cove (Rocket Lake)
Backported Sunny Cove microarchitecture for 14nm
Tremont
Tremont
10 nm
Skylake
Palm Cove (Cannon Lake)
Mobile-only
Sunny Cove
Sunny Cove (Ice Lake)
512 KB L2-cache/core
Willow Cove (Tiger Lake)
X$^e$ graphics engine
Gracemont
Gracemont
Intel 7 (10nm ESF)
Golden Cove
Golden Cove (Alder Lake)
Hybrid, DDR5, PCIe 5.0
Raptor Cove (Raptor Lake)
Crestmont
Crestmont
Intel 4
Redwood Cove
Meteor Lake
Mobile-only NPU, chiplet architecture
Skymont
Skymont
N3B (TSMC)
Lion Cove
Lunar Lake
Low power mobile only (9-30W)
Arrow Lake
Darkmont
Darkmont
18A
Cougar Cove
Panther Lake
Strike-through indicates cancelled processors
Bold names are microarchitectures
Italic names are future processors :

## Successor

Intel had NetBurst-based successors in development called Tejas and Jayhawk with between 40 and 50 pipeline stages, but ultimately decided to replace NetBurst with the Core microarchitecture, released in July 2006; these successors were more directly derived from the Pentium Pro (P6 microarchitecture). August 8, 2008 marked the end of Intel NetBurst-based processors. The reason for NetBurst's abandonment was the severe heat problems caused by high clock speeds. While some Core- and Nehalem-based processors have higher TDPs, most processors are multi-core, so each core gives off a fraction of the maximum TDP, and the highest-clocked Core-based single-core processors give off a maximum of 27 W of heat. The fastest-clocked desktop Pentium 4 processors (single-core) had TDPs of 115 W, compared to 88 W for the fastest clocked mobile versions. Although, with the introduction of new steppings, TDPs for some models were eventually lowered.
The Nehalem microarchitecture, the successor to the Core microarchitecture, was supposed to be an evolution of NetBurst according to Intel roadmaps dating back to 2000. Nehalem reimplements certain features of NetBurst, including the Hyper-Threading technology first introduced in the 3.06 GHz Northwood core, and L3 cache, first implemented on a consumer processor in the Gallatin core used in the Pentium 4 Extreme Edition.

## NetBurst-based chips

* Celeron (NetBurst)
* Celeron D
* Pentium 4
* Pentium 4 Extreme Edition
* Pentium D
* Pentium Extreme Edition
* Xeon, from 2001 through 2006