# PX5 RTOS

PX5 RTOS is a real-time operating system (RTOS) designed for embedded systems. It is implemented using the ANSI C programming language.

## Overview

The PX5 RTOS, created by William Lamie, is an embedded real-time operating system (RTOS) that was launched in January 2023. Lamie, who also developed other RTOSes such as Nucleus RTX, Nucleus PLUS, and ThreadX (acquired by Microsoft), currently serves as the President and CEO of PX5, an embedded software company headquartered in San Diego, California, United States. Among these RTOSes, approximately 10 billion devices are operated by the ThreadX RTOS, while the Nucleus RTOS is used in around 3 billion devices.
The name PX5 is an abbreviation where P stands for POSIX threads, X stands for thread switching, and 5 represents fifth generation RTOS. Written in ANSI C, the PX5 RTOS is compatible with various embedded microcontroller unit (MCU) and memory protection unit (MPU) architectures. It has minimal resource requirements, needing less than 1KB of FLASH and 1KB of RAM for basic operations on microcontrollers.
One of the notable features of the PX5 RTOS is its native support for POSIX Threads (pthreads), which is an industry-standard API often absent in many other RTOS solutions. Additionally, it offers real-time extensions such as event flags, fast queues, tick timers, and memory management.
The PX5 RTOS executes most API calls and context switches in less than a microsecond on typical 32-bit microcontrollers. It is also deterministic – ensuring predictable processing for each API and context switch regardless of the number of active threads.
The PX5 RTOS incorporates Pointer/Data Verification (PDV) technology, which verifies function return addresses, function pointers, system objects, global data, memory pools, and more.
In November 2023, PX5 introduced PX5 NET adding TCP/IP networking to the PX5 RTOS. Like PX5 RTOS, PX5 NET has a small minimal footprint (under 6KB) and leverages PDV for run-time safety and security.

## Supported platforms

PX5 RTOS supports most of the embedded MCU and MPU architectures, including ARM's Cortex-M, Cortex-R, Cortex-A, and RISC-V architecture families. It supports both 32-bit and 64-bit architectures, and provides support for both asymmetric multiprocessing (AMP) and symmetric multiprocessing (SMP) configurations.

## Technology

The PX5 RTOS uses a microkernel which enhances device security by integrating with Arm TrustZone technology, specifically designed for Cortex-M23 and Cortex-M33 microcontrollers. As a fifth-generation RTOS, PX5 is tailored for industrial-grade applications, enabling the separation of secure and non-secure MCU functions at the hardware level.
To further strengthen security measures, PX5 RTOS incorporates a technology called Pointer/Data Verification (PDV). This technology identifies and prevents computer program errors, including buffer errors. In addition, the operating system is constructed using industry-standard POSIX pthreads APIs, facilitating the development of multi-threaded programs in C/C++. This allows for the execution of multiple tasks simultaneously across different operating systems.
The POSIX pthreads APIs in PX5 RTOS offer support for various mechanisms, such as signals, condition variables, semaphore, mutex, and message queues. Furthermore, extensions like event flags, fast queues, tick timers, and memory management are also included. PX5 RTOS maintains a small footprint and exhibits rapid scalability. Its installation process involves a 3-step procedure, aided by two accessible source files: px5.c and px5_binding.s. Additionally, the operating system automatically promotes one "main" file to the first system thread.
PX5 RTOS accommodates read-only memory (ROM) Flash, ranging from a minimum of 1KB to a maximum of less than 40KB. The solution also ensures portability through its support for portable ANSI C for system programming. Moreover, PX5 RTOS has been verified by C-STAT static analysis and adheres to MISRA compliance standards.

## Partnerships

In January 2023, PX5 and Clarinox have joined forces to facilitate wireless connectivity in resource-constrained embedded systems. They integrated ClarinoxBlue and ClarinoxWiFi protocol stack software with the PX5 RTOS.
On 25 January 2023, Cypherbridge made an announcement regarding the integration of its SDKPac and uLoadXL IoT software with PX5 RTOS.
In March 2023, Percepio AB entered into a partnership agreement with PX5. The PX5 integrated the Percepio Tracealyzer trace recorder and Percepio supported the RTOS PX5 in a commercially available version.