# Elbrus-2S+

Elbrus-2S+ (Russian: Эльбрус-2С+) is a multi-core microprocessor based on the Elbrus 2000 architecture developed by Moscow Center of SPARC Technologies (MCST). There are multiple reports regarding the evolution of this technology for the purpose of import substitution in Russia, which was raised by several ministries in July 2014, due to economic sanctions in response to 2014 pro-Russian unrest in Ukraine. In December 2014, it was announced that Mikron Group started pilot production of a dual-core variant of this microprocessor called Elbrus-2SM (Russian: Эльбрус-2СМ) using a 90 nanometer CMOS manufacturing process in Zelenograd, Russia.

## Technology

The Elbrus-4S CPU uses a VLIW instruction set where it can perform up to 23 instructions per clock cycle and is reported to have support for Intel x86 emulation through a virtual machine. When programs are built for Elbrus 2000 native mode, the compiler determines how the different operations shall be distributed over the 23 computing units before saving the final program. This means that no dynamic scheduling is needed during runtime, thus reducing the amount of work the CPU has to perform every time a program is executed. Because static scheduling only needs to be performed one time when the program is built, more advanced algorithms for finding the optimal distribution of work can be employed.

## Specifications

| | Elbrus-2S+ | Elbrus-2SМ | Elbrus-4S |
| Russian designation | 1891ВМ7Я | 1891ВМ9Я | 1891ВМ8Я |
| Produced | 2011 | 2014 | 2014 |
| Process | CMOS 90 nm | CMOS 90 nm | CMOS 65 nm |
| Clock rate | 500 MHz | 300 MHz | 800 MHz |
| Elbrus 2000 CPU cores Elcore-09 DSP cores | 2 4 | 2 0 | 4 0 |
| Peak performance (CPU + DSP) 64-bit 64-bit 32-bit 32-bit 16-bit | 20 + 2 GIPS 8 + 0 GFlops 33 + 16 GIPS 16 + 12 GFlops 43 + 48 GIPS | 12 GIPS 4.8 GFlops 19.8 GIPS 9.6 GFlops | 25 GFlops 107 GIPS 50 GFlops |
| L1 instruction cache (per core) | 64 KB | 64 KB | 128 KB |
| L1 data cache (per core) | 64 KB | 64 KB | 64 KB |
| L2 cache (per core) | 1 MB | 1 MB | 8 MB |
| DSP cache (per DSP core) | 128 KB | | |
| Data transfer rate to cache | 16 GB/s | | |
| Data transfer rate to main memory | 12.8 GB/s | | 38.4 GB/s |
| Communications number of channels for interprocessor communications channel bandwidth for interprocessor communications number of input-output channels channel bandwidth for input-output | 3 4 GB/s 2 2 GB/s | | 3 12 GB/s 1 4 GB/s |
| Crystal area | 289 sq. mm | | 380 sq. mm |
| Transistors | 368 million | >300 million | 986 million |
| Connection layers | 9 | | 9 |
| Packing/pins | HFCBGA/1296 | | HFCBGA/1600 |
| Package size | 37.5×37.5×2.5 mm | | 42.5×42.5×3.2 mm |
| Voltage | 1.0/1.8/2.5 V | 1.2/1.8/ 2.5 V | 1.1/1.5/2.5/3.3 V |
| Power consumption | ~25 W | | ~45 W |
| Producer | TSMC Taiwan | Mikron Russia | Mikron Russia |

## South Bridge

The south bridge for the Elbrus 2000 chipset, which connects peripherals and bus to the CPU is developed by MCST. It is also compatible with the MCST-R1000.
| | KPI 1991VG1YA 1026A010 |
| Produced | 2010 |
| Process | CMOS 0.13 μm |
| Clock rate | 250 MHz |
| serial bus for communication with the microprocessor | 1 GB/s – receiving, 1 GB/s – transmission |
| PCI Express controller, revision 1.0a | 8 lines |
| PCI controller, version 2.3 | 32/64-bit at clock frequencies of 33/66 MHz |
| Ethernet controller, 1 GB/s | 1 port |
| SATA 2.0 controller | 4 ports |
| IDE controller, PATA-100 | 2 ports for 2 devices |
| USB 2.0 controller | 2 ports |
| audio interface controller, AC-97 | 2-channel stereo |
| Serial controller, RS-232 and RS-485 | 2 ports |
| Parallel interface controller, IEEE-1284 with DMA support | 1 port |
| Programmable universal input-output (GPIO) controller | 16 signals |
| I²C interface | Channel 4 |
| SPI Interface | Supports for 4 devices |
| Interrupt control subsystems | 2 PIC + 1 IOAPIC |
| Timers | System timer and watchdog timer. |
| Crystal area | 112 sq. mm |
| Transistors | 30 million |
| Packing/pins | HFCBGA/1156 |
| Package size | 35×35×3.2 mm |
| Voltage | 1.2/3.3 V |
| Power consumption | ~6 W |

## Applications

In December 2012, Kraftway announced that it will deliver an Elbrus based PC together with its partner MCST.
In August 2013, Kuyan, Gusev, Kozlov, Kaimuldenov and Kravtsunov from MCST has published an article based on their experience with building and deployment of Debian Linux for the Elbrus computer architecture. It was done using a hybrid compiler toolchain (cross and native), for Elbrus-2S+ and Intel Core 2 Duo.
In December 2014, an implementation of the OpenGL 3.3 standard was demonstrated by running the game Doom 3 BFG Edition on an Elbrus-4S, clocked at 720 MHz, using a Radeon graphics card with 2 gigabytes of video memory.
In April 2015, MCST announced two new products based on the Elbrus-4S CPU: One 19-inch rack server with four CPUs (16 cores) and one personal computer.
In December 2015, the first shipment of PCs based on VLIW CPU Elbrus-4s was made in Russia.
In June 2024, the “Elbrus-2S3 (Эльбрус-2С3) microprocessor” has resurfaced on the Russian market. This is a nona-core("CPU-core×2" + "3D・GPU-core×1" + "2D・GPU-core×2" + "VPU-core×4") CPU manufactured with a 16nm process. This is the cut down version of the 16-core Elbrus-16S, which might also resurface at some point if there's enough market demand for this to make sense.
In September 2024, The MCST company presented “Elbrus-2S3 (Эльбрус-2С3) microprocessor” at the 10th anniversary Russian forum "Microelectronics 2024".