# AN/FSQ-32

The AN/FSQ-32 SAGE Solid State Computer (AN/FSQ-7A before December 1958,$^{:27}$ colloq. "Q-32") was a planned military computer of the United States Air Force. It was central for deployment to Super Combat Centers in nuclear bunkers and to some above-ground military installations. In 1958, Air Defense Command planned to acquire 13 Q-32 centrals for several Air Divisions/Sectors.

## Background

In 1956, Air Research and Development Command sponsored "development of a transistorized, or solid-state, computer" by IBM and when announced in June 1958, the planned "SAGE Solid State Computer...was estimated to have a computing capability of seven times" the AN/FSQ-7. ADC's November 1958 plan to field—by April 1964—the 13 solid state AN/FSQ-7A was for each to network "a maximum of 20 long-range radar inputs [40 LRI telephone lines] and a maximum dimension of just over 1000 miles in both north-south and east-west directions." "Low rate Teletype data" could be accepted on 32 telephone lines (e.g., from "Alert Network Number 1"). On 17 November 1958, CINCNORAD "decided to request the solid state computer and hardened facilities", and the remaining vacuum-tube AN/FSQ-8 centrals for combat centers were cancelled (one was retrofitted to function as an AN/FSQ-7).
"Each AN/FSQ-32 computer would be" used:$^{:21}$
    1. for "a combat center" (as with the vacuum-tube AN/FSQ-8),
    2. to accept "radar and weapons connections" for weapons direction as with the AN/FSQ-7--e.g., for backup CIM-10 Bomarc guidance or manned interceptor GCI if above-ground Direction Center(s) could not function, and
    3. for "air traffic control functions".$^{:21}$
"Air Defense and Air Traffic Control Integration" was planned for airways modernization after the USAF, CAA, and AMB agreed on August 22, 1958, to "collocate air route traffic control centers and air defense facilities"$^{:24}$ (e.g., jointly use some Air Route Surveillance Radars at SAGE radar stations). The May 22, 1959, agreement between the USAF, DoD, and FAA designated emplacement of ATC facilities "in the hardened structure of the nine U. S. SCC's",$^{:24}$ and SAGE Air Defense Sectors and FAA regions were to have coincident boundaries in a June 19, 1959, air defense plan used to create a new SAGE Implementation Schedule on July 1, 1959.$^{:20}$
On December 21, 1959, the Office of Defense Research and Engineering informed NORAD a stop order had been placed on AN/FSQ-32 production and in January 1960, the Office of the Secretary of Defense recommended the SCC program be cancelled. The AN/FSQ-32, as part of the SCC Program, was cancelled by March 18, 1960, and the SAGE Air Traffic Integration (SATIN) was similarly cancelled by the DoD. Back-Up Interceptor Control eventually with smaller solid-state computers at above-ground SAGE radar stations was instead implemented for survivability.
Planned deployment was for Ottawa, St Louis, San Antonio, Raleigh, Syracuse, Chicago, Spokane, Minot, Portland, Phoenix, Miami (above-ground), Albuquerque (above-ground), and Shreveport (above-ground). (During 1959 SAGE/FAA "boundary alignments", the total was reduced to 12.)

## Prototype

The prototype of the AN/FSQ-32 was the largest transistor (solid state) computer ever made. Initial weight: 66.5 short tons; 60.3 metric tons (132,960 lb), expanded (18 tape drives, 10 storage units): 90.8 short tons; 82.4 metric tons (181,560 lb).
The Q-32 prototype was installed at System Development Corporation (SDC) headquarters in Santa Monica, California, and SDC developed the prototype software using JOVIAL. The mainframe occupied nearly an entire floor of a large office building (refrigeration units were also in the building). The prototype used batch processing of the military data.

### ARPA research

In the early 1960s, the AN/FSQ-32 prototype was taken over by the Advanced Research Projects Agency and remained in Santa Monica. This action set the stage for ARPA's Information Processing Techniques Office. SDC's research included ways to permit the prototype to handle multiple batch tasks simultaneously ("time-sharing") and to simultaneously process data multiple geographically-separated computer users.
On April 23, 1963, Dr. J. C. R. Licklider, ARPA Director of Behavioral Sciences Command & Control Research, identified early challenges in establishing a time-sharing network of computers with the software of the era. An early remote user of the prototype was the Augmentation Research Center at the Stanford Research Institute.

#### Time-sharing

By June 1963 the Time-Sharing System (TSS) Model Zero was demonstrated after magnetic drums were added to the time-sharing. Each user was given a priority-based time slice, measured in milliseconds, when the user's program was written from the magnetic drums into much higher speed memory, processed, and then written back to the magnetic drums with any computational changes that had occurred. It was influenced by early experiments at Bolt, Beranek, and Newman, and the CTSS project at MIT. Terminals included several Teletype Model 33 ASRs.

#### Computer network

After the SAGE Sector Warning Network for the 1st operational SAGE direction center used the 1st operational computer network (cf. the experimental networks for Bomarc test launches and SAGE compatibility tests), in October 1965 Lincoln Labs' used a TX-2 solid-state computer tied to the Q-32 prototype for the first telecommunication of time packets.

### Description

The prototype was an IBM 4020 Military Computer that included a central processing unit, memory, High-Speed Input/Output, Low-Speed Input/Output, and for both computer operations and maintenance, an Operations Console. The AN/FSQ-32 central would have included additional equipment such as display and console equipment for use by Air Defense Command, Army Air Defense Command, Federal Aviation Administration, and other personnel (e.g., at SCC/DCs, weapons direction consoles for dispatching/guiding manned interceptors, launching/guiding CIM-10 Bomarcs, and launching Nike surface-to-air missiles).

#### Central processing unit

The Instruction set used a fixed length of one word providing 24 bits for the operation and 24 bits for the address. The address consisted of 18 bits (3 bytes) for the memory address, with other bits used for the specification of index registers and indirect addressing. The operation field provided the operation code and a variety of modifiers. Some modifiers allowed instructions to operate only on specific bytes of a word or on specific bits of a byte without separate masking operations. Other modifiers allowed the single 48-bit ALU to operate on a pair of 24-bit operands to facilitate vector operations. CPU controls included sense switches to control various software functions, a run/halt switch, and a switch, amplifier, and speaker assembly, to provide audio feedback or even play music, by connecting one of four bits in the main accumulator which could then be toggled under software control at an appropriate rate to produce whatever tones one wanted.

#### Memory

Memory was addressed by words, which were 48 bits long. Each word was divided into eight 6-bit bytes. A 6-bit byte, as opposed to the 8-bit byte in common use today, was common in IBM and other scientific computers of the time. The address space provided a maximum of 256K words. The prototype was equipped with 128k words (48 bits plus two parity bits) of memory that was oil and water cooled. Also considered as part of the memory subsystem in that they were addressed via fixed reserved memory addresses, were 4 48 position switch banks, in which a short program could be inserted, and a plug panel, similar to the one used in IBM Unit-Record equipment, that had the capacity of 32 words, so longer bootstrap or diagnostic programs could be installed in plug panels which could then be inserted into the receptacle and used as a primitive ROM. The memory had a cycle time of 2.5 microseconds, and the lack of memory management was a limitation in the computer.

#### Input/Output

High-Speed Input/Output provided interfaces to the Drum Memory system, which consisted of a control system, and two vertical drum memory devices. Each drum read and wrote 50 bits at a time in parallel so transferring data could be done quickly. The drums were organized as 17 fields with 8192 words per field for a total capacity of 139264 words. The motors that rotated the drums required 208 VAC at 45 Hz so a motor generator unit was required to change the frequency from 60 Hz. This added to the noise level in the computer room. The other connection to/from the HSIO was to the SACCS EDTCC, which then interfaced to the rest of the SACCS.
Low-Speed Input/Output interfaced to several different devices:
* Communications Multiplexor
* Tape Controllers 1 and 2, connected to 16 IBM 729-V Tape Drives
* Disk File Controller, which was a modified Tape Controller, connected to a Bryant Disk File, which had 25 disks that were 39" in diameter, 125 read/write heads that were hydraulically actuated, and had a total capacity of 26 megabytes
* IBM 1401, which controlled data transfers from unit-record equipment: IBM 1402 Card Reader/Punch, IBM 1403 Line Printer, & 2 IBM 729-V Tape Drives
* 2 IBM Selectric Typewriters, (I/O Typewriters) one of which was used for operational messages and the other for diagnostic messages and maintenance activities.