# XScale

XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM architecture (version 5) instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE (see more below), with some later models designed as system-on-a-chip (SoC). Intel sold the PXA family to Marvell Technology Group in June 2006. Marvell then extended the brand to include processors with other microarchitectures, like Arm's Cortex.
The XScale architecture is based on the ARMv5TE ISA without the floating-point instructions. XScale uses a seven-stage integer and an eight-stage memory super-pipelined microarchitecture. It is the successor to the Intel StrongARM line of microprocessors and microcontrollers, which Intel acquired from DEC's Digital Semiconductor division as part of a settlement of a lawsuit between the two companies. Intel used the StrongARM to replace its ailing line of outdated RISC processors, the i860 and i960.
All the generations of XScale are 32-bit ARMv5TE processors manufactured with a 0.18 μm or 0.13 μm (as in IXP43x parts) process and have a 32 KB data cache and a 32 KB instruction cache. First- and second-generation XScale multi-core processors also have a 2 KB mini data cache (claimed it "avoids 'thrashing' of the D-Cache for frequently changing data streams"). Products based on the third-generation XScale have up to 512 KB unified L2 cache.

## Processor families

The XScale core is used in a number of microcontroller families manufactured by Intel and Marvell:
* Application processors (with the prefix PXA). There are four generations of XScale application processors, described below: PXA210/PXA25x, PXA26x, PXA27x, and PXA3xx.
* I/O processors (with the prefix IOP).
* Network processors (with the prefix IXP).
* Control plane processors (with the prefix IXC).
* Consumer electronics processors (with the prefix CE).
There are also standalone processors: the 80200 and 80219 (targeted primarily at PCI applications).

### PXA

PXA System on a Chip (SoC) products were designed in Austin, Texas. The code-names for this product line are small towns in Texas, primarily near deer hunting leases frequented by the Intel XScale core and mobile phone SoC marketing team. PXA System on a Chip products were popular on smartphones and PDAs (with Windows Mobile, Symbian OS, Palm OS) during 2000 to 2006.
| | Released date | Code name | ARM type | Fab | Size | Pin count | Clock speeds |
| PXA21x and PXA26x ||||||||
| PXA210 | February 2002 | - | ARMv5 XScale1 core | | 13x13mm | 255 pin T-PBGA | 133 MHz and 200 MHz |
| PXA250 | February 2002 | Cotulla | ARMv5 XScale1 core | | 17x17mm | 256-pin PBGA | 200 MHz, 300 MHz and 400 MHz |
| PXA255 | March 2003 | Cotulla | ARMv5 XScale1 core | | 17x17mm | 256-pin PBGA | 200 MHz, 300 MHz and 400 MHz |
| PXA26x ||||||||
| PXA260 | March 2003 | Dalhart | ARMv5 XScale1 core | | | | 200 MHz, 300 MHz and 400 MHz |
| PXA261 | March 2003 | Dalhart | ARMv5 XScale1 core | | | | 200 MHz, 300 MHz and 400 MHz |
| PXA263 | March 2003 | Dalhart | ARMv5 XScale1 core | | | | 200 MHz, 300 MHz and 400 MHz |
| PXA27x ||||||||
| PXA270 | April 2004 | Bulverde | ARMv5 XScale2 core | | | | 312 MHz, 416 MHz, 520 MHz and 624 MHz |
| PXA271 | April 2004 | Bulverde | ARMv5 XScale2 core | | | | 13, 104, 208 MHz or 416 MHz |
| PXA272 | April 2004 | Bulverde | ARMv5 XScale2 core | | | | 312 MHz, 416 MHz or 520 MHz |
| PXA3xx ||||||||
| PXA300 | August 2005 | Monahans | ARMv5 XScale3 core | | | | 208 MHz, 624 MHz |
| PXA310 | August 2005 | Monahans | ARMv5 XScale3 core | | | | 624 MHz |
| PXA320 | August 2005 | Monahans | ARMv5 XScale3 core | | | | 806 MHz |
| PXA90x ||||||||
| PXA90x | | | | 130 nm | | | |
| PXA93x ||||||||
| PXA930 | | Tavor | ARMv5 XScale3 core | 65 nm | | | 624 MHz, 1000 MHz |
| PXA935 | | Tavor | ARMv5 XScale3 core | 45 nm | | | |
| PXA95x ||||||||
| PXA955 | | | ARMv7 | | | | |

#### PXA210/PXA25x

The PXA210 was Intel's entry-level XScale targeted at mobile phone applications. It was released with the PXA250 in February 2002 and comes clocked at 133 MHz and 200 MHz.
The PXA25x family (code-named Cotulla) consists of the PXA250 and PXA255. The PXA250 was Intel's first generation of XScale processors. There was a choice of three clock speeds: 200 MHz, 300 MHz and 400 MHz. It came out in February 2002. In March 2003, the revision C0 of the PXA250 was renamed to PXA255. The main differences were a doubled internal bus speed (100 MHz to 200 MHz) for faster data transfer, lower core voltage (only 1.3 V at 400 MHz) for lower power consumption and writeback functionality for the data cache, the lack of which had severely impaired performance on the PXA250.
Intel XScale Core Features :
* ARMv5TE
* ARM Thumb
* ARM DSP
* L1 32-KByte data and instruction cache

#### PXA26x

The PXA26x family (code-named Dalhart) consists of the PXA260 and PXA261-PXA263. The PXA260 is a stand-alone processor clocked at the same frequency as the PXA25x, but features a TPBGA package which is about 53% smaller than the PXA25x's PBGA package. The PXA261-PXA263 are the same as the PXA260 but have Intel StrataFlash memory stacked on top of the processor in the same package; 16 MB of 16-bit memory in the PXA261, 32 MB of 16-bit memory in the PXA262 and 32 MB of 32-bit memory in the PXA263. The PXA26x family was released in March 2003.

#### PXA27x

The PXA27x family (code-named Bulverde) consists of the PXA270 and PXA271-PXA272 processors. This revision is a huge update to the XScale family of processors. The PXA270 is clocked in four different speeds: 312 MHz, 416 MHz, 520 MHz and 624 MHz and is a stand-alone processor with no packaged memory. The PXA271 can be clocked to 13, 104, 208 MHz or 416 MHz and has 32 MB of 16-bit stacked StrataFlash memory and 32 MB of 16-bit SDRAM in the same package. The PXA272 can be clocked to 312 MHz, 416 MHz or 520 MHz and has 64 MB of 32-bit stacked StrataFlash memory.
Intel also added many new technologies to the PXA27x family such as:
* SpeedStep: the operating system can clock the processor down based on load to save power.
* Wireless MMX (code-named Concan; "iwMMXt"): 43 new SIMD instructions containing the full MMX instruction set and the integer instructions from Intel's SSE instruction set along with some instructions unique to the XScale. Wireless MMX provides 16 extra 64-bit registers that can be treated as an array of two 32-bit words, four 16-bit halfwords or eight 8-bit bytes. The XScale core can then perform up to eight adds or four MACs in parallel in a single cycle. This capability is used to boost speed in decoding and encoding of multimedia and in playing games.
* Additional peripherals, such as a USB-Host interface and a camera interface.
* Internal 256 KB SRAM to reduce power consumption and latency.
The PXA27x family was released in April 2004. Along with the PXA27x family Intel released the 2700G embedded graphics co-processor(code-named Marathon).

#### PXA3xx

In August 2005 Intel announced the successor to Bulverde, codenamed Monahans.
They demonstrated it showing its capability to play back high definition encoded video on a PDA screen.
The new processor was shown clocked at 1.25 GHz but Intel said it only offered a 25% increase in performance (800 MIPS for the 624 MHz PXA270 processor vs. 1000 MIPS for 1.25 GHz Monahans). An announced successor to the 2700G graphics processor, code named Stanwood, has since been canceled. sd features of Stanwood are integrated into Monahans. For extra graphics capabilities, Intel recommends third-party chips like the Nvidia GoForce chip family.
In November 2006, Marvell Semiconductor officially introduced the Monahans family as Marvell PXA320, PXA300, and PXA310. PXA320 is currently shipping in high volume, and is scalable up to 806 MHz. PXA300 and PXA310 deliver performance "scalable to 624 MHz", and are software-compatible with PXA320.

#### PXA800F

Codenamed Manitoba, Intel PXA800F was a SoC introduced by Intel in 2003 for use in GSM- and GPRS-enabled mobile phones. The chip was built around an XScale processor core, the likes of which had been used in PDAs, clocked at 312 MHz and manufactured with a 0.13 μm process, with 4 MB of integrated flash memory and a digital signal processor.
A prototype board with the chip was demoed during the Intel Developer Forum. Intel noted it was in talks with leading mobile phone manufacturers, such as Nokia, Motorola, Samsung, Siemens and Sony Ericsson, about incorporating Manitoba into their phones.
O2 XM, released in 2005, was the only mobile phone with a documented use of the Manitoba chip. An Intel executive stated that the chip version used in the phone was reworked to be less expensive than the initial one.

#### PXA90x

The PXA90x, codenamed Hermon, was a successor to Manitoba with 3G support. The PXA90x is built using a 130 nm process. The SoC continued being marketed by Marvell as they acquired Intel's XScale business.

#### PXA16x

PXA16x is a processor designed by Marvell, combining the earlier Intel designed PXA SoC components with a new ARMv5TE CPU core named Mohawk or PJ1 from Marvell's Sheeva family instead of using wdc Xscale or ARM design. The CPU core is derived from the Feroceon core used in Marvell's embedded Kirkwood product line, but extended for instruction level compatibility with the XScale IWMMX.
The PXA16x delivers strong performance at a mass market price point for cost sensitive consumer and embedded markets such as digital picture frames, E Readers, multifunction printer user interface (UI) displays, interactive VoIP phones, IP surveillance cameras, and home control gadgets.

#### PXA930/935

The PXA930 and PXA935 processor series were again built using the Sheeva microarchitecture developed by Marvell but upgraded to ARMv7 instruction set compatibility. This core is a so-called Tri-core architecture codenamed Tavor; Tri-core means it supports the ARMv5TE, ARMv6 and ARMv7 instruction sets. This new architecture was a significant leap from the old Xscale architecture. The PXA930 uses 65 nm technology while the PXA935 is built using the 45 nm process.
The PXA930 is used in the BlackBerry Bold 9700.

#### PXA940

Little is known about the PXA940, although it is known to be ARM Cortex-A8 compliant. It is utilized in the BlackBerry Torch 9800 and is built using 45 nm technology.

#### PXA986/PXA988

After XScale and Sheeva, the PXA98x uses the third CPU core design, this time licensed directly from ARM, in form of dual core Cortex A9 application processors utilized by devices like Samsung Galaxy Tab 3 7.0.

#### PXA1088

It is a quad core Cortex A7 application processor with Vivante GPU.

### IXC
#### IXC1100

The IXC1100 processor features clock speeds at 266, 400, and 533 MHz, a 133 MHz bus, 32 KB of instruction cache, 32 KB of data cache, and 2 KB of mini-data cache. It is also designed for low power consumption, using 2.4 W at 533 MHz. The chip comes in the 35 mm PBGA package.

### IOP

The IOP line of processors is designed to allow computers and storage devices to transfer data and increase performance by offloading I/O functionality from the main CPU of the device. The IOP3XX processors are based on the XScale architecture and designed to replace the older 80219 sd and i960 family of chips. There are ten different IOP processors currently available: IOP303, IOP310, IOP315, IOP321, IOP331, IOP332, IOP333, IOP341, IOP342 and IOP348. Clock speeds range from 100 MHz to 1.2 GHz. The processors also differ in PCI bus type, PCI bus speed, memory type, maximum memory allowable, and the number of processor cores.

### IXP network processor

The XScale core is utilized in the second generation of Intel's IXP network processor line, while the first generation used StrongARM cores. The IXP network processor family ranges from solutions aimed at small/medium office network applications, IXP4XX, to high performance network processors such as the IXP2850, capable of sustaining up to OC-192 line rates. In IXP4XX devices the XScale core is used as both a control and data plane processor, providing both system control and data processing. The task of the XScale in the IXP2XXX devices is typically to provide control plane functionality only, with data processing performed by the microengines, examples of such control plane tasks include routing table updates, microengine control, and memory management.

### CE

In April 2007, Intel announced an XScale-based processor targeting consumer electronics markets, the Intel CE 2110 (codenamed Olo River).

## Applications

XScale microprocessors were used in RIM's BlackBerry handheld, the Dell Axim family of Pocket PCs, most of the Zire, Treo and Tungsten Handheld lines by Palm, later versions of the Sharp Zaurus, the Motorola A780, the Acer n50, the Compaq iPaq 3900 series, and in other PDAs. It was the CPU in the Iyonix PC desktop computer running RISC OS, and the NSLU2 (Slug) running Linux. XScale is also used in devices such as PVPs (Portable Video Players), PMCs (Portable Media Centres), including the Creative Zen Portable Media Player and Amazon Kindle E-Book reader, and in industrial embedded systems.
At the other end of the market, the XScale IOP33x Storage I/O processors are used in some Intel Xeon-based server platforms.

## Sale of PXA processor line

On June 27, 2006, the sale of Intel's XScale PXA mobile processor assets was announced. Intel agreed to sell the XScale PXA business to Marvell Technology Group for an estimated $600 million in cash and the assumption of unspecified liabilities. The move was intended to permit Intel to focus its resources on its core x86 and server businesses. Marvell holds a full architecture license for ARM, allowing it to design chips to implement the ARM instruction set, not just license a processor core.
The acquisition was completed on November 9, 2006. Intel was expected to continue manufacturing XScale processors until Marvell secures other manufacturing facilities, and would continue manufacturing and selling the IXP and IOP processors, as they were not part of the deal.
The XScale effort at Intel was initiated by the purchase of the StrongARM division from Digital Equipment Corporation in 1998. Intel still holds an ARM license even after the sale of XScale; this license is at the architectural level.