# Unicore

Unicore is a computer instruction set architecture designed by the Microprocessor Research and Development Center (MPRC) of Peking University in the PRC. The computer built on this architecture is called the Unity-863. The CPU is integrated into a fully functional SoC to make a PC-like system.
The processor is very similar to the ARM architecture, but uses a different instruction set.
It is supported by the Linux kernel as of version 2.6.39. Support will be removed in Linux kernel version 5.9 as nobody seems to maintain it and the code is falling behind the rest of the kernel code and compiler requirements.

## Instruction set

The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits. Likewise, the immediate format is 9 bits rotated by a 5-bit amount (rather than 8 bit rotated by 4), the load/store offset sizes are 14 bits for byte/word and 10 bits for signed byte or half-word. Conditional moves are provided by encoding the condition in the (unused by ARM) second source register field Rn for MOV and MVN instructions.
Unicore32 instruction set overview :
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Description |
| 0 | 0 | 0 | opcode | opcode | opcode | opcode | S | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | shift | shift | shift | shift | shift | 0 | Sh | Sh | 0 | Rm | Rm | Rm | Rm | Rm | ALU operation, Rd = Rn op Rm shift #shift |
| 0 | 0 | 0 | opcode | opcode | opcode | opcode | S | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | Rs | Rs | Rs | Rs | Rs | 0 | Sh | Sh | 1 | Rm | Rm | Rm | Rm | Rm | ALU operation, Rd = Rn op Rm shift Rs |
| 0 | 0 | 1 | opcode | opcode | opcode | opcode | S | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | shift | shift | shift | shift | shift | imm9 | imm9 | imm9 | imm9 | imm9 | imm9 | imm9 | imm9 | imm9 | ALU operation, Rd = Rn op #imm9 ROTL #shift |
| 0 | 1 | 0 | P | U | B | W | L | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | shift | shift | shift | shift | shift | 0 | Sh | Sh | 0 | Rm | Rm | Rm | Rm | Rm | Load/store Rd to address Rn ± Rm shift #shift |
| 0 | 1 | 1 | P | U | B | W | L | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | offset14 | Load/store Rd to address Rn ± offset14 |
| 1 | 0 | 0 | P | U | S | W | L | Rn | Rn | Rn | Rn | Rn | Bitmap high | Bitmap high | Bitmap high | Bitmap high | Bitmap high | Bitmap high | Bitmap high | Bitmap high | Bitmap high | Bitmap high | 0 | 0 | H | Bitmap low | Bitmap low | Bitmap low | Bitmap low | Bitmap low | Bitmap low | Load/store multiple registers |
| 1 | 0 | 1 | cond | cond | cond | cond | L | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | offset24 | Branch (and link) if condition true |
| 1 | 1 | 0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coprocessor (FPU) instructions |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Trap number | Software interrupt |
| 0 | 0 | 0 | 0 | 0 | 0 | A | S | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | Rs | Rs | Rs | Rs | Rs | 1 | 0 | 0 | 1 | Rm | Rm | Rm | Rm | Rm | Multiply, Rd = Rm * Rs (+ Rn) |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | L | 11111 | 11111 | 11111 | 11111 | 11111 | 11111 | 11111 | 11111 | 11111 | 11111 | 00000 | 00000 | 00000 | 00000 | 00000 | 1 | 0 | 0 | 1 | Rm | Rm | Rm | Rm | Rm | Branch and exchange (BX, BLX) |
| 0 | 1 | 0 | P | U | 0 | W | L | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | 00000 | 00000 | 00000 | 00000 | 00000 | 1 | S | H | 1 | Rm | Rm | Rm | Rm | Rm | Load/store Rd to address Rn ± Rm (16-bit) |
| 0 | 1 | 0 | P | U | 1 | W | L | Rn | Rn | Rn | Rn | Rn | Rd | Rd | Rd | Rd | Rd | imm_hi | imm_hi | imm_hi | imm_hi | imm_hi | 1 | S | H | 1 | imm_lo | imm_lo | imm_lo | imm_lo | imm_lo | Load/store Rd to address Rn ± #imm10 (16-bit) |
The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set. The load/store multiple instruction can only access half of the register set, depending on the H bit. If H=0, the 16 bits indicate R0–R15; if H=1, R16–R31.