# Four-valued logic

In logic, a four-valued logic is any logic with four truth values. Several types of four-valued logic have been advanced.

## Belnap

Nuel Belnap considered the challenge of question answering by computer in 1975. Noting human fallibility, he was concerned with the case where two contradictory facts were loaded into memory, and then a query was made. "We all know about the fecundity of contradictions in two-valued logic: contradictions are never isolated, infecting as they do the whole system." Belnap proposed a four-valued logic as a means of containing contradiction.
He called the table of values A4: Its possible values are true, false, both (true and false), and neither (true nor false). Belnap's logic is designed to cope with multiple information sources such that if only true is found then true is assigned, if only false is found then false is assigned, if some sources say true and others say false then both is assigned, and if no information is given by any information source then neither is assigned. These four values correspond to the elements of the power set based on {T, F}.
T is the supremum and F the infimum in the logical lattice where None and Both are in the wings. Belnap has this interpretation: "The worst thing is to be told something is false simpliciter. You are better off (it is one of your hopes) in either being told nothing about it, or being told both that it is true and also that it is false; while of course best of all is to be told that it is true." Belnap notes that "paradoxes of implication" (A&~A)→B and A→(B∨~B) are avoided in his 4-valued system.

### Logical connectives

Belnap addressed the challenge of extending logical connectives to A4. Since it is the power set on {T, F}, the elements of A4 are ordered by inclusion making it a lattice with Both at the supremum and None at the infimum, and T and F on the wings. Referring to Dana Scott, he assumes the connectives are Scott-continuous or monotonic functions. First he expands negation by deducing that ¬Both = Both and ¬None = None. To expand And and Or the monotonicity goes only so far. Belnap uses equivalence (a&b = a iff avb = b) to fill out the tables for these connectives. He finds None & Both = F while None v Both = T.
| & | N | F | T | B |
| N | N | F | N | F |
| F | F | F | F | F |
| T | N | F | T | B |
| B | F | F | B | B |
| v | N | F | T | B |
| N | N | N | T | T |
| F | N | F | T | B |
| T | T | T | T | T |
| B | T | B | T | B |
The result is a second lattice L4 called the "logical lattice", where A4 is the "approximation lattice" determining Scott continuity.

## Implementation using two bits

Let one bit be assigned for each truth value: 01=T and 10=F with 00=N and 11=B.
Then the subset relation in the power set on {T, F} corresponds to order ab<cd iff a<c and b<d in two-bit representation. Belnap calls the lattice associated with this order the "approximation lattice".
The logic associated with two-bit variables can be incorporated into computer hardware.

## Matrix transitions

As a discrete system, the four-valued logic illustrates a set of states subject to transitions by logical matrices to form a transition system. An input of two bits transitions to an output of two bits through matrix multiplication.
There are sixteen logical matrices that are 2x2, and four logical vectors that act as inputs and outputs of the matrix transitions:
    X = {A, B, C, D } = {(0,1), (1, 0), (0, 0), (1, 1) }.
When C is input, the output is always C. Four of the sixteen have zero in one corner only, so the output of vector-matrix multiplication with Boolean arithmetic is always D, except for C input.
Nine further logical matrices need description to fill out the labelled transition system where the matrices label the transitions. Excluding C, inputs A, B, and D are considered in order and the output in X expressed as a triple, for example ABD for ${\begin{pmatrix}1&0\\0&1\end{pmatrix}},$ commonly known as the identity matrix.
The asymmetric matrices differ in their action on row versus column vectors. The row convention is used here:
    ${\begin{pmatrix}1&0\\1&0\end{pmatrix}}$ has code BBB, ${\begin{pmatrix}0&1\\0&1\end{pmatrix}}$ code AAA
    ${\begin{pmatrix}1&1\\0&0\end{pmatrix}}$ has code CDB, ${\begin{pmatrix}0&0\\1&1\end{pmatrix}}$ code DCA.
The remaining operations on X are expressed with matrices with three zeros, so outputs include C for a third of the inputs. The codes are CAA, BCA, ACA, and CBB in these cases.

## Applications

A four-valued logic was established by IEEE with the standard IEEE 1364: It models signal values in digital circuits. The four values are 1, 0, Z and X. 1 and 0 stand for Boolean true and false, Z stands for high impedance or open circuit and X stands for don't care (e.g., the value has no effect). This logic is itself a subset of the 9-valued logic standard called IEEE 1164 and implemented in Very High Speed Integrated Circuit Hardware Description Language, VHDL's std_logic.
One should not confuse four-valued mathematical logic (using operators, truth tables, syllogisms, propositional calculus, theorems and so on) with communication protocols built using binary logic and displaying responses with four possible states implemented with Boolean-like type of values : for instance, the SAE J1939 standard, used for CAN data transmission in heavy road vehicles, which has four logical (Boolean) values: False, True, Error Condition, and Not installed (represented by values 0–3). Error Condition means there is a technical problem obstructing data acquisition. The logics for that is for example True and Error Condition=Error Condition. Not installed is used for a feature that does not exist in this vehicle, and should be disregarded for logical calculation. On CAN, usually fixed data messages are sent containing many signal values each, so a signal representing a not-installed feature will be sent anyway.

### Split bit proposed gate

Creation of carbon nanotubes for logical gates has used carbon nanotube field-effect transistors (CNFETs). An anticipated demand for data storage in the Internet of Things (IoT) provides a motivation. A proposal has been made for 32 nm process application using a split bit-gate: "By using CNFET technology in 32 nm node by the proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered."