# 3 GB barrier

In computing, the term 3 GB barrier refers to a limitation of some 32-bit operating systems running on x86 microprocessors. It prevents the operating systems from using all of 4 GiB (4 × 1024$^3$ bytes) of main memory. The exact barrier varies by motherboard and I/O device configuration, particularly the size of video RAM; it may be in the range of 2.75 GB to 3.5 GB. The barrier is not present with a 64-bit processor and 64-bit operating system, or with certain x86 hardware and an operating system such as Linux or certain versions of Windows Server and macOS that allow use of Physical Address Extension (PAE) mode on x86 to access more than 4 GiB of RAM.
Whatever the actual position of the "barrier", there is no code in operating system software nor any hardware architectural limit that directly imposes it. Rather, the "barrier" is the result of interactions between several aspects of both.

## Physical address limits

Many 32-bit computers have 32 physical address bits and are thus limited to 4 GiB (2$^{32}$ words) of memory. x86 processors prior to the Pentium Pro have 32 or fewer physical address bits; however, most x86 processors since the Pentium Pro, which was first sold in 1995, have the Physical Address Extension (PAE) mechanism, which allows addressing up to 64 GiB (2$^{36}$ words) of memory. PAE is a modification of the protected mode address translation scheme which allows virtual or linear addresses to be translated to 36-bit physical addresses, instead of the 32-bit addresses available without PAE. The CPU pinouts likewise provide 36 bits of physical address lines to the motherboard.
Many x86 operating systems, including any version of Linux with a PAE kernel and some versions of Windows Server and macOS, can use PAE to address up to 64 GiB of memory on an x86 system.
There are other factors that may limit this ability to use up to 64 GiB of memory, and lead to the "3 GB barrier" under certain circumstances, even on processors that implement PAE. These are described in the following sections.

## Chipset and other motherboard issues

Although, as noted above, most x86 processors from the Pentium Pro onward are able to generate physical addresses up to 64 GiB, the rest of the motherboard must participate in allowing RAM above the 4 GiB point to be addressed by the CPU. Chipsets and motherboards allowing more than 4 GiB of RAM with x86 processors do exist, but in the past, most of those intended for other than the high-end server market could access only 4 GiB of RAM.
This, however, is not sufficient to explain the "3 GB barrier" that appears even when running some x86 versions of Microsoft Windows on platforms that can access more than 4 GiB of RAM.

## Memory-mapped I/O and disabled RAM

Modern personal computers are built around a set of standards that depend on, among other things, the characteristics of the original PCI bus. The original PCI bus implemented 32-bit physical addresses and 32-bit-wide data transfers. PCI (and PCI Express and AGP) devices present at least some, if not all, of their host control interfaces via a set of memory-mapped I/O locations (MMIO). The address space in which these MMIO locations appear is the same address space as that used by RAM, and while RAM can exist and be addressable above the 4 GiB point, these MMIO locations decoded by I/O devices cannot be. They are limited by PCI bus specifications to addresses of 0xFFFFFFFF (2$^{32}$ − 1) and below. With 4 GiB or more of RAM installed, and with RAM occupying a contiguous range of addresses starting at 0, some of the MMIO locations will overlap with RAM addresses. On machines with large amounts of video memory, MMIO locations have been found to occupy as much as 1.8 GB of the 32-bit address space. Other locations that might overlap with RAM addresses might include those for the APIC, SMRAM and iGPU.
The BIOS and chipset are responsible for detecting these address conflicts and disabling access to the RAM at those locations. Due to the way bus address ranges are determined on the PCI bus, this disabling is often at a relatively large granularity, resulting in relatively large amounts of RAM being disabled.

## Address remapping

x86 chipsets that can address more than 4 GiB of RAM typically also allow memory remapping (referred to in some BIOS setup screens as "memory hole remapping"). In this scheme, the BIOS detects the memory address conflict and in effect relocates the interfering RAM so that it may be addressed by the processor at a new physical address that does not conflict with MMIO. On the Intel side, this feature once was limited to server chipsets; however, newer desktop chipsets like the Intel 955X and 965 and later have it as well (see "Memory Reclaiming" in the chipset datasheet). On the AMD side, the AMD K8 and later processors' built-in memory controller had it from the beginning.
As the new physical addresses are above the 4 GiB point, addressing this RAM does require that the operating system be able to use physical addresses larger than 2$^{32}$. This capability is provided by PAE. Note that there is not necessarily a requirement for the operating system to support more than 4 GiB total of RAM, as the total RAM might be only 4 GiB; it is just that a portion of it appears to the CPU at addresses in the range from 4 GiB and up.
This form of the 3 GB barrier affects one generation of MacBooks, lasting 1 year (Core2Duo (Merom) – November 2006 to October 2007): the prior generation was limited to 2 GiB, while later generations (November 2007 – October 2009) allowed 4 GiB through the use of PAE and memory-hole remapping, and subsequent generations (late 2009 onwards) use 64-bit processors and therefore can address over 4 GiB.

## Windows version dependencies

The "non-server", or "client", x86 SKUs of Windows XP and later operate x86 processors in PAE mode by default when the CPU present implements the NX bit. Nevertheless, these operating systems do not permit addressing of physical memory above the 4 GiB address boundary. This is not an architectural limit; it is a limit imposed by Microsoft as a workaround for device driver compatibility issues that were discovered during testing.
Thus, the "3 GB barrier" under x86 Windows "client" operating systems can therefore arise in two slightly different scenarios. In both, RAM near the 4 GiB point conflicts with memory-mapped I/O space. Either the BIOS simply disables the conflicting RAM; or, the BIOS remaps the conflicting RAM to physical addresses above the 4 GiB point, but x86 Windows client editions refuse to use physical addresses higher than that, even though they are running with PAE enabled. The conflicting RAM is therefore unavailable to the operating system whether it is remapped or not.