# Pascal (microarchitecture)

Pascal is the codename for a GPU microarchitecture developed by Nvidia, as the successor to the Maxwell architecture. The architecture was first introduced in April 2016 with the release of the Tesla P100 (GP100) on April 5, 2016, and is primarily used in the GeForce 10 series, starting with the GeForce GTX 1080 and GTX 1070 (both using the GP104 GPU), which were released on May 27, 2016, and June 10, 2016, respectively. Pascal was manufactured using TSMC's 16 nm FinFET process, and later Samsung's 14 nm FinFET process.
The architecture is named after the 17th century French mathematician and physicist, Blaise Pascal.
In April 2019, Nvidia enabled a software implementation of DirectX Raytracing on Pascal-based cards starting with the GTX 1060 6 GB, and in the 16 series cards, a feature reserved to the Turing-based RTX series up to that point.

## Details

In March 2014, Nvidia announced that the successor to Maxwell would be the Pascal microarchitecture; announced on May 6, 2016, and released on May 27 of the same year. The Tesla P100 (GP100 chip) has a different version of the Pascal architecture compared to the GTX GPUs (GP104 chip). The shader units in GP104 have a Maxwell-like design.
Architectural improvements of the GP100 architecture include the following:
* In Pascal, a SM (streaming multiprocessor) consists of between 64-128 CUDA cores, depending on if it is GP100 or GP104. Maxwell contained 128 CUDA cores per SM; Kepler had 192, Fermi 32 and Tesla 8. The GP100 SM is partitioned into two processing blocks, each having 32 single-precision CUDA cores, an instruction buffer, a warp scheduler, 2 texture mapping units and 2 dispatch units.
* CUDA Compute Capability 6.0.
* High Bandwidth Memory 2 — some cards feature 16 GiB HBM2 in four stacks with a total bus width of 4096 bits and a memory bandwidth of 720 GB/s.
* Unified memory — a memory architecture where the CPU and GPU can access both main system memory and memory on the graphics card with the help of a technology called "Page Migration Engine".
* NVLink — a high-bandwidth bus between the CPU and GPU, and between multiple GPUs. Allows much higher transfer speeds than those achievable by using PCI Express; estimated to provide between 80 and 200 GB/s.
* 16-bit (FP16) floating-point operations (colloquially "half precision") can be executed at twice the rate of 32-bit floating-point operations ("single precision") and 64-bit floating-point operations (colloquially "double precision") executed at half the rate of 32-bit floating point operations.
* More registers — twice the amount of registers per CUDA core compared to Maxwell.
* More shared memory.
* Dynamic load balancing scheduling system. This allows the scheduler to dynamically adjust the amount of the GPU assigned to multiple tasks, ensuring that the GPU remains saturated with work except when there is no more work that can safely be distributed to distribute. Nvidia therefore has safely enabled asynchronous compute in Pascal's driver.
* Instruction-level and thread-level preemption.
Architectural improvements of the GP104 architecture include the following:
* CUDA Compute Capability 6.1.
* GDDR5X — new memory standard supporting 10Gbit/s data rates, updated memory controller.
* Simultaneous Multi-Projection - generating multiple projections of a single geometry stream, as it enters the SMP engine from upstream shader stages.
* DisplayPort 1.4, HDMI 2.0b.
* Fourth generation Delta Color Compression.
* Enhanced SLI Interface — SLI interface with higher bandwidth compared to the previous versions.
* PureVideo Feature Set H hardware video decoding HEVC Main10 (10-bit), Main12 (12-bit) and VP9 hardware decoding.
* HDCP 2.2 support for 4K DRM protected content playback and streaming (Maxwell GM200 and GM204 lack HDCP 2.2 support, GM206 supports HDCP 2.2).
* NVENC HEVC Main10 10bit hardware encoding.
* GPU Boost 3.0.
* Instruction-level preemption. In graphics tasks, the driver restricts preemption to the pixel-level, because pixel tasks typically finish quickly and the overhead costs of doing pixel-level preemption are lower than instruction-level preemption (which is expensive). Compute tasks get thread-level or instruction-level preemption, because they can take longer times to finish and there are no guarantees on when a compute task finishes. Therefore the driver enables the expensive instruction-level preemption for these tasks.

## Overview
### Graphics Processor Cluster

A chip is partitioned into Graphics Processor Clusters (GPCs). For the GP104 chips, a GPC encompasses 5 SMs.

### Streaming Multiprocessor "Pascal"

A "Streaming Multiprocessor" is analogous to AMD's Compute Unit. An SM encompasses 128 single-precision ALUs ("CUDA cores") on GP104 chips and 64 single-precision ALUs on GP100 chips. While all CU versions consist of 64 shader processors (i.e. 4 SIMD Vector Units, each 16 lanes wide), Nvidia experimented with very different numbers of CUDA cores:
* On Tesla, 1 SM combines 8 single-precision (FP32) shader processors
* On Fermi, 1 SM combines 32 single-precision (FP32) shader processors
* On Kepler, 1 SM combines 192 single-precision (FP32) shader processors and 64 double-precision (FP64) units (on GK110 GPUs)
* On Maxwell, 1 SM combines 128 single-precision (FP32) shader processors
* On Pascal, it depends:
** On GP100, 1 SM combines 64 single-precision (FP32) shader processors and also 32 double-precision (FP64) providing a 2:1 ratio of single- to double-precision throughput. The GP100 uses more flexible FP32 cores that are able to process one single-precision or two half-precision numbers in a two-element vector. This is intended to better serve machine learning tasks.
** On GP104, 1 SM combines 128 single-precision ALUs, 4 double-precision ALUs (providing a 32:1 ratio), and one half-precision ALU which contains a vector of two half-precision floats which can execute the same instruction on both floats, providing a 64:1 ratio if the same instruction is used on both elements.

### Polymorph-Engine 4.0

The Polymorph Engine version 4.0 is the unit responsible for Tessellation. It corresponds functionally with AMD's Geometric Processor. It has been moved from the shader module to the TPC to allow one Polymorph engine to feed multiple SMs within the TPC.

### Chips

* GP100: Nvidia's Tesla P100 GPU accelerator is targeted at GPGPU applications such as FP64 double precision compute and deep learning training that uses FP16. It uses HBM2 memory. Quadro GP100 also uses the GP100 GPU.
* GP102: This GPU is used in the Titan Xp, Titan X Pascal and the GeForce GTX 1080 Ti. It is also used in the Quadro P6000 & Tesla P40.
* GP104: This GPU is used in the GeForce GTX 1070, GTX 1070 Ti, GTX 1080, and some GTX 1060 6 GB's. The GTX 1070 has 15/20 and the GTX 1070 Ti has 19/20 of its SMs enabled; both utilize GDDR5 memory. The GTX 1080 is a fully unlocked chip and uses GDDR5X memory. Some GTX 1060 6 GB's use GP104 with 10/20 SMs enabled and GDDR5X memory. It is also used in the Quadro P5000, Quadro P4000, Quadro P3200 (mobile applications) and Tesla P4.
* GP106: This GPU is used in the GeForce GTX 1060 with GDDR5 memory. It is also used in the Quadro P2000.
* GP107: This GPU is used in the GeForce GTX 1050 and 1050 Ti. It is also used in the Quadro P1000, Quadro P600, Quadro P620 & Quadro P400.
* GP108: This GPU is used in the GeForce GT 1010 and GeForce GT 1030.
Comparison table of some Kepler, Maxwell, and Pascal chips :
| | GK104 | GK110 | GM204 (GTX 970) | GM204 (GTX 980) | GM200 | GP104 | GP100 |
| Dedicated texture cache per SM | 48 KiB | — | — | — | — | — | — |
| Texture (graphics or compute) or read-only data (compute only) cache per SM | — | 48 KiB | — | — | — | — | — |
| Programmer-selectable shared memory/L1 partitions per SM | 48 KiB shared memory + 16 KiB L1 cache (default) | 48 KiB shared memory + 16 KiB L1 cache (default) | — | — | — | — | — |
| Programmer-selectable shared memory/L1 partitions per SM | 32 KiB shared memory + 32 KiB L1 cache | 32 KiB shared memory + 32 KiB L1 cache | — | — | — | — | — |
| Programmer-selectable shared memory/L1 partitions per SM | 16 KiB shared memory + 48 KiB L1 cache | 16 KiB shared memory + 48 KiB L1 cache | — | — | — | — | — |
| Unified L1 cache/texture cache per SM | — | — | 48 KiB | 48 KiB | 48 KiB | 48 KiB | 24 KiB |
| Dedicated shared memory per SM | — | — | 96 KiB | 96 KiB | 96 KiB | 96 KiB | 64 KiB |
| L2 cache per chip | 512 KiB | 1536 KiB | 1792 KiB | 2048 KiB | 3072 KiB | 2048 KiB | 4096 KiB |

## Performance

The theoretical single-precision processing power of a Pascal GPU in GFLOPS is computed as 2 × operations per FMA instruction per CUDA core per cycle × number of CUDA cores × core clock speed (in GHz).
The theoretical double-precision processing power of a Pascal GPU is 1/2 of the single precision performance on Nvidia GP100, and 1/32 of Nvidia GP102, GP104, GP106, GP107 & GP108.
The theoretical half-precision processing power of a Pascal GPU is 2× of the single precision performance on GP100 and 1/64 on GP104, GP106, GP107 & GP108.

## Successor

The Pascal architecture was succeeded in 2017 by Volta in the HPC, cloud computing, and self-driving car markets, and in 2018 by Turing in the consumer and business market.

## P100 accelerator and DGX-1

Comparison of accelerators used in DGX:
| Model | Architecture | Socket | FP32 CUDA cores | FP64 cores (excl. tensor) | Mixed INT32/FP32 cores | INT32 cores | Boost clock | Memory clock | Memory bus width | Memory bandwidth | VRAM | Single precision (FP32) | Double precision (FP64) | INT8 (non-tensor) | INT8 dense tensor | INT32 | FP4 dense tensor | FP16 | FP16 dense tensor | bfloat16 dense tensor | TensorFloat-32 (TF32) dense tensor | FP64 dense tensor | Interconnect (NVLink) | GPU | L1 Cache | L2 Cache | TDP | Die size | Transistor count | Process | Launched |
| B200 | Blackwell | SXM6 | N/A | N/A | N/A | N/A | N/A | 8 Gbit/s HBM3e | 8192-bit | 8 TB/sec | 192 GB HBM3e | N/A | N/A | N/A | 4.5 POPS | N/A | 9 PFLOPS | N/A | 2.25 PFLOPS | 2.25 PFLOPS | 1.2 PFLOPS | 40 TFLOPS | 1.8 TB/sec | GB100 | N/A | N/A | 1000 W | N/A | 208 B | TSMC 4NP | Q4 2024 (expected) |
| B100 | Blackwell | SXM6 | N/A | N/A | N/A | N/A | N/A | 8 Gbit/s HBM3e | 8192-bit | 8 TB/sec | 192 GB HBM3e | N/A | N/A | N/A | 3.5 POPS | N/A | 7 PFLOPS | N/A | 1.98 PFLOPS | 1.98 PFLOPS | 989 TFLOPS | 30 TFLOPS | 1.8 TB/sec | GB100 | N/A | N/A | 700 W | N/A | 208 B | TSMC 4NP | Q4 2024 (expected) |
| H200 | Hopper | SXM5 | 16896 | 4608 | 16896 | N/A | 1980 MHz | 6.3 Gbit/s HBM3e | 6144-bit | 4.8 TB/sec | 141 GB HBM3e | 67 TFLOPS | 34 TFLOPS | N/A | 1.98 POPS | N/A | N/A | N/A | 990 TFLOPS | 990 TFLOPS | 495 TFLOPS | 67 TFLOPS | 900 GB/sec | GH100 | 25344 KB (192 KB × 132) | 51200 KB | 1000 W | 814 mm$^2$ | 80 B | TSMC 4N | Q3 2023 |
| H100 | Hopper | SXM5 | 16896 | 4608 | 16896 | N/A | 1980 MHz | 5.2 Gbit/s HBM3 | 5120-bit | 3.35 TB/sec | 80 GB HBM3 | 67 TFLOPS | 34 TFLOPS | N/A | 1.98 POPS | N/A | N/A | N/A | 990 TFLOPS | 990 TFLOPS | 495 TFLOPS | 67 TFLOPS | 900 GB/sec | GH100 | 25344 KB (192 KB × 132) | 51200 KB | 700 W | 814 mm$^2$ | 80 B | TSMC 4N | Q3 2022 |
| A100 80GB | Ampere | SXM4 | 6912 | 3456 | 6912 | N/A | 1410 MHz | 3.2 Gbit/s HBM2e | 5120-bit | 1.52 TB/sec | 80 GB HBM2e | 19.5 TFLOPS | 9.7 TFLOPS | N/A | 624 TOPS | 19.5 TOPS | N/A | 78 TFLOPS | 312 TFLOPS | 312 TFLOPS | 156 TFLOPS | 19.5 TFLOPS | 600 GB/sec | GA100 | 20736 KB (192 KB × 108) | 40960 KB | 400 W | 826 mm$^2$ | 54.2 B | TSMC N7 | Q1 2020 |
| A100 40GB | Ampere | SXM4 | 6912 | 3456 | 6912 | N/A | 1410 MHz | 2.4 Gbit/s HBM2 | 5120-bit | 1.52 TB/sec | 40 GB HBM2 | 19.5 TFLOPS | 9.7 TFLOPS | N/A | 624 TOPS | 19.5 TOPS | N/A | 78 TFLOPS | 312 TFLOPS | 312 TFLOPS | 156 TFLOPS | 19.5 TFLOPS | 600 GB/sec | GA100 | 20736 KB (192 KB × 108) | 40960 KB | 400 W | 826 mm$^2$ | 54.2 B | TSMC N7 | Q1 2020 |
| V100 32GB | Volta | SXM3 | 5120 | 2560 | N/A | 5120 | 1530 MHz | 1.75 Gbit/s HBM2 | 4096-bit | 900 GB/sec | 32 GB HBM2 | 15.7 TFLOPS | 7.8 TFLOPS | 62 TOPS | N/A | 15.7 TOPS | N/A | 31.4 TFLOPS | 125 TFLOPS | N/A | N/A | N/A | 300 GB/sec | GV100 | 10240 KB (128 KB × 80) | 6144 KB | 350 W | 815 mm$^2$ | 21.1 B | TSMC 12FFN | Q3 2017 |
| V100 16GB | Volta | SXM2 | 5120 | 2560 | N/A | 5120 | 1530 MHz | 1.75 Gbit/s HBM2 | 4096-bit | 900 GB/sec | 16 GB HBM2 | 15.7 TFLOPS | 7.8 TFLOPS | 62 TOPS | N/A | 15.7 TOPS | N/A | 31.4 TFLOPS | 125 TFLOPS | N/A | N/A | N/A | 300 GB/sec | GV100 | 10240 KB (128 KB × 80) | 6144 KB | 300 W | 815 mm$^2$ | 21.1 B | TSMC 12FFN | Q3 2017 |
| P100 | Pascal | SXM/SXM2 | N/A | 1792 | 3584 | N/A | 1480 MHz | 1.4 Gbit/s HBM2 | 4096-bit | 720 GB/sec | 16 GB HBM2 | 10.6 TFLOPS | 5.3 TFLOPS | N/A | N/A | N/A | N/A | 21.2 TFLOPS | N/A | N/A | N/A | N/A | 160 GB/sec | GP100 | 1344 KB (24 KB × 56) | 4096 KB | 300 W | 610 mm$^2$ | 15.3 B | TSMC 16FF+ | Q2 2016 |