# UNIVAC III

The UNIVAC III, designed as an improved transistorized replacement for the vacuum tube UNIVAC I and UNIVAC II computers. The project was started by the Philadelphia division of Remington Rand UNIVAC in 1958 with the initial announcement of the system been made in the Spring of 1960, however as this division was heavily focused on the UNIVAC LARC project the shipment of the system was delayed until June 1962, with Westinghouse agreeing to furnish system programing and marketing on June 1, 1962. It was designed to be compatible for all data formats. However the word size and instruction set were completely different; this presented significant difficulty as all programs had to be rewritten, so many customers switched to different vendors instead of upgrading existing UNIVACs.
The UNIVAC III weighed about 27,225 pounds (13.6 short tons; 12.3 t).
The system was engineered to use as little core memory as possible, as it was a very expensive item. The memory system was 25 bits wide and could be configured with from 8,192 words to 32,768 words of memory. Memory was built in stacks of 29 planes of 4,096 cores: 25 for the data word, two for "modulo-3 check" bits, and two for spares. Each memory cabinet held up to four stacks (16,384 words).
It supported the following data formats:
* 25-bit signed binary numbers
* excess-3 binary-coded decimal with four bits per digit, allowing six-digit signed decimal numbers
* alphanumerics with six bits per character, allowing four-character signed alphanumeric values
| 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| s | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) | binary value (ones complement) |
| s | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) | digit (XS-3) |
| s | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character | character |
Instructions were 25 bits long.
| 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| i/a | x | x | x | x | op (opcode) | op (opcode) | op (opcode) | op (opcode) | op (opcode) | op (opcode) | ar/xo | ar/xo | ar/xo | ar/xo | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) |
The CPU had four accumulators, a four-bit field (ar) allowed selection of any combination of the accumulators for operations on data from one to four words in length. For backward compatibility with the UNIVAC I and UNIVAC II data, two accumulators were needed to store a 12-digit decimal number and three accumulators were needed to store a 12-character alphanumeric value. When accumulators were combined in an instruction, the sign bit of the Most Significant Accumulator was used and the others ignored.
The CPU had 15 index registers, a four-bit field (x) allowed selection of one index register as the base register. Operand addresses were determined by adding the contents of the selected base register and the 10-bit displacement field (m). Instructions that modified or stored index registers used a four-bit field (xo) to select that index register.
Indirect addressing or field selection was selected if the one-bit field (i/a) was set. Both indirect addressing and a base register could be selected in the indirect address in memory. Only a base register could be selected in the field selector in memory.
| 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| i/a | x | x | x | x | 0 | 0 | 0 | spare | spare | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) | l (address) |
| 0 | x | x | x | x | left bit (1..24 XS-3) | left bit (1..24 XS-3) | left bit (1..24 XS-3) | left bit (1..24 XS-3) | left bit (1..24 XS-3) | right bit (1..24 XS-3) | right bit (1..24 XS-3) | right bit (1..24 XS-3) | right bit (1..24 XS-3) | right bit (1..24 XS-3) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) | m (address) |
Sperry Rand began shipment in June 1962 and produced 96 UNIVAC III systems.
The operating systems(s) which were developed for the UNIVAC III's were called CHIEF, and BOSS.The assembly language was SALT. The majority of UNIVAC III systems were equipped with tape drives; tapes contained images of the system data at the head of any tape, followed by data. The OS could handle jobs at this time, so some tapes had data relating to job control, and others had data. UNIVAC III systems could have up to 32 tape drives.
Some systems were equipped at a later time with a random-access FASTRAND drum.