# Universal synchronous and asynchronous receiver-transmitter

A universal synchronous and asynchronous receiver-transmitter (USART, programmable communications interface or PCI) is a type of a serial interface device that can be programmed to communicate asynchronously or synchronously. See universal asynchronous receiver-transmitter (UART) for a discussion of the asynchronous capabilities of these devices.

## Purpose and history

The USART's synchronous capabilities were primarily intended to support synchronous protocols like IBM's synchronous transmit-receive (STR), binary synchronous communications (BSC), synchronous data link control (SDLC), and the ISO-standard high-level data link control (HDLC) synchronous link-layer protocols, which were used with synchronous voice-frequency modems. These protocols were designed to make the best use of bandwidth when modems were analog devices. In those times, the fastest asynchronous voice-band modem could achieve at most speeds of 300 bit/s using frequency-shift keying (FSK) modulation, while synchronous modems could run at speeds up to 9600 bit/s using phase-shift keying (PSK). Synchronous transmission used only slightly over 80% of the bandwidth of the now more-familiar asynchronous transmission, since start and stop bits were unnecessary. Those modems are obsolete, having been replaced by modems which convert asynchronous data to synchronous forms, but similar synchronous telecommunications protocols survive in numerous block-oriented technologies such as the widely used IEEE 802.2 (Ethernet) link-level protocol. USARTs are still sometimes integrated with MCUs. USARTs are still used in routers that connect to external CSU/DSU devices, and they often use either Cisco's proprietary HDLC implementation or the IETF standard point-to-point protocol (PPP) in HDLC-like framing as defined in RFC 1662.

## Operation

The operation of a USART is intimately related to the various protocols; refer to those pages for details. This section only provides a few general notes.
* USARTs in synchronous mode transmits data in frames. In synchronous operation, characters must be provided on time until a frame is complete; if the controlling processor does not do so, this is an "underrun error," and transmission of the frame is aborted.
* USARTs operating as synchronous devices used either character-oriented or bit-oriented mode. In character (STR and BSC) modes, the device relied on particular characters to define frame boundaries; in bit (HDLC and SDLC) modes earlier devices relied on physical-layer signals, while later devices took over the physical-layer recognition of bit patterns.
* A synchronous line is never silent; when the modem is transmitting, data is flowing. When the physical layer indicates that the modem is active, a USART will send a steady stream of padding, either characters or bits as appropriate to the device and protocol.

## Devices

| Manufacturer | Device | Description | Device data |
| Intel | 8251A$^{:396}$ | Programmable communications interface | Intel 8251A data sheet |
| Signetics / Philips | 2651 | Programmable communications interface | Philips Semiconductors SCN2651 data sheet |
| Zilog | "SIO" Z8440–4/Z84C40–4 | Serial input/output controller | Zilog #ps0183, Z8440/1/2/3/4 and Z84C40/1/2/3/4 data sheet |
| Zilog | "SCC" Z8530/Z85C30; Z85230/Z80230/Z8523L/Z85233 | Enhanced serial communications controller | IXYS web page |