# Backside Power Delivery

Backside Power Delivery (BPD) advanced semiconductor technology that relocates the power delivery network from the frontside to the backside of a silicon wafer. This technique aims to improve power efficiency, performance, and design flexibility in integrated circuits (ICs).

## Overview

Traditionally, power and signal interconnects are both placed on the frontside of the silicon wafer. BPD separates these functions by placing power delivery interconnects on the backside of the wafer, thereby freeing up more space for signal interconnects on the frontside. This separation can lead to improved power integrity, reduced signal interference, and enhanced performance.

## Development and Adoption
### Intel's PowerVia Technology

Intel has been a pioneer in BPD with its PowerVia technology, scheduled for introduction in its 20A process node in 2024. PowerVia has demonstrated significant benefits, including a 6% increase in operating frequency, 30% reduction in power loss, and more compact designs with improved density.
PowerVia involves constructing transistors on the frontside of the silicon wafer while routing power interconnects on the backside. This process requires drilling deep, narrow through-silicon vias (TSVs) to connect the power interconnects to the transistors. Intel has developed methods to ensure that these TSVs do not compromise the reliability or thermal management of the chip. Intel's Blue Sky Creek test chip demonstrated the benefits of this approach, showing over 90% cell utilization and potential cost reduction.

### TSMC's N2 and A16 Nodes

Taiwan Semiconductor Manufacturing Company (TSMC) has explored BPD, initially planning to introduce it in their N2P process node. However, TSMC decided to delay the incorporation of BPD due to cost and complexity considerations. Instead, they will focus on other enhancements, such as the NanoFlex technology, which allows for greater optimization of performance, power, and area (PPA) through flexible cell design.
TSMC's A16 process node, set to debut in 2025, integrates the Super PowerRail architecture along with nanosheet transistors. This combination aims to enhance computational efficiency and reduce energy consumption. The A16 process is designed to alleviate IR drop, simplify power distribution, and allow for tighter chip packaging. TSMC claims that A16 can achieve a 10% higher clock speed or a 15% to 20% decrease in power consumption compared to the N2P node, while also increasing chip density by up to 10%.

### Samsung's SF1.4 Process

Samsung is another major competitor in the BPD arena, planning to implement its Backside Power Delivery Network in the 1.4-nanometer process by 2027. Samsung's approach aims to reduce wafer area consumption by 14.8% and wiring length by 9.2%, leading to lower power consumption and improved power transmission conditions.

## Technical Benefits
### Improved Power Integrity

By moving the power delivery network to the backside, BPD reduces the voltage droop experienced by transistors. This is because the power interconnects can be made larger and less resistive, providing a more stable power supply. This stability allows transistors to operate at higher frequencies with less risk of performance degradation.

### Enhanced Signal Routing

With power interconnects relocated, the frontside has more space for signal routing. This reduces congestion and parasitic capacitance, leading to faster and more efficient signal transmission. The reduction in signal congestion allows for denser packing of logic cells, further enhancing the performance and efficiency of the chip.

### Thermal Management

BPD presents new challenges and opportunities for thermal management. The relocation of power interconnects can lead to higher thermal densities, requiring innovative cooling solutions. However, it also allows for more efficient heat dissipation paths, potentially improving overall thermal performance if managed correctly.

## Challenges
### Design Complexity

Implementing BPD requires significant changes to traditional design methodologies. Engineers must adapt to new design rules and tools that account for the backside routing of power. This includes ensuring that thermal management and mechanical stresses are properly addressed, as these can impact the reliability and performance of the IC.

### Manufacturing Costs

The process of creating BPD-enabled chips involves additional steps, such as the creation of TSVs and the handling of wafers with interconnects on both sides. These steps can increase manufacturing costs, although companies like Intel have developed methods to offset these costs by optimizing other aspects of the chip design process.

## Future Prospects

Intel plans to integrate BPD with its RibbonFET transistors in upcoming process nodes, targeting production readiness in the first half of 2024. TSMC, while delaying BPD in its N2P node due to cost and complexity, will introduce it in the A16 node by 2025. Samsung aims to apply BPD to its 1.4-nanometer process by 2027, focusing on reducing wafer area consumption and improving power transmission.