# Silici d'Apple

El silici d'Apple és una sèrie de processadors sistema en xip (SoC) i sistema en paquet (SiP) dissenyats per Apple Inc., utilitzant principalment l'arquitectura ARM. És la base de la majoria d'ordinadors Mac nous, així com de l'iPhone, l'iPad, l'iPod Touch, l'Apple TV i l'Apple Watch, i de productes com els AirPods, HomePod i el seu successor HomePod Mini i AirTag.
Apple va anunciar el seu pla per canviar els ordinadors Mac dels processadors Intel a Apple silici a la WWDC 2020 el 22 de juny de 2020. Els primers Mac construïts amb el processador Apple M1 es van presentar el 10 de novembre de 2020. El 2022, els models de Mac més nous s'han construït amb silici d'Apple; només els models més antics del Mac Mini i el Mac Pro encara utilitzen processadors Intel Core i Xeon respectivament.
Apple externalitza la fabricació dels xips, però controla totalment la seva integració amb el maquinari i el programari de l'empresa. Johny Srouji és el responsable del disseny de silici d'Apple.
Llista de processadors:
| General | General | General | Imatge | Tecnologia | Tecnologia | Tecnologia | Tecnologia | Arquitectura | Arquitectura | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | GPU | GPU | GPU |
| Nom | Renom | Part No. | Imatge | Node | Fabricant | Transistors nº | Mida Dau | CPU ISA | Bit width | Prestacions Nucli | Prestacions Nucli | Prestacions Nucli | Eficiència | Eficiència | Eficiència | Overall cores | Cache | Cache | Cache | Cache | Vendor | Cores | EU count | ALU count | Frequency | FLOPS |
| Nom | Renom | Part No. | Imatge | Node | Fabricant | Transistors nº | Mida Dau | CPU ISA | Bit width | Nucli nom | Nuclis | Velocitat nucli | Core name | Cores | Core speed | Overall cores | L1 | L2 | L3 | SLC | Vendor | Cores | EU count | ALU count | Frequency | FLOPS |
| | APL0098 | S5L8900 | | 90 nm | Samsung | | 72 mm² | ARMv6 | 32-bit | ARM11 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | L1i: 16 KB L1d: 16 KB | rowspan=16 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=30 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Overall cores | PowerVR MBX Lite | 1 | 1 | 8 | 60 MHz - 103 MHz |
| | APL0278 | S5L8720 | | 65 nm | Samsung | | 36 mm² | ARMv6 | 32-bit | ARM11 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | L1i: 16 KB L1d: 16 KB | rowspan=16 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=30 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 533 MHz | PowerVR MBX Lite | 1 | 1 | 8 | 103 MHz - 133 MHz | 1.64 GFLOPs - 2.12 GFLOPS |
| | APL0298 | S5L8920 | | 65 nm | Samsung | | 71.8 mm² | ARMv7 | 32-bit | Cortex-A8 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | 600 MHz | L1i: 32 KB L1d: 32 KB | 256 KB | PowerVR SGX535 | 1 | 2 | 16 | 200 MHz | 6.4 GFLOPS |
| | APL2298 | S5L8922 | | 45 nm | Samsung | | 41.6 mm² | ARMv7 | 32-bit | Cortex-A8 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | 600 MHz | L1i: 32 KB L1d: 32 KB | 256 KB | PowerVR SGX535 | 1 | 2 | 16 | 200 MHz | 6.4 GFLOPS |
| A4 | APL0398 | S5L8930 | | 45 nm | Samsung | | 53.3 mm² | ARMv7 | 32-bit | Cortex-A8 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | 800 MHz | L1i: 32 KB L1d: 32 KB | 512 KB | PowerVR SGX535 | 1 | 2 | 16 | 200 MHz - 250 MHz | 6.4 GFLOPS - 8.0 GFLOPS |
| A4 | APL0398 | S5L8930 | | 45 nm | Samsung | | 53.3 mm² | ARMv7 | 32-bit | Cortex-A8 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | 1.0 GHz | L1i: 32 KB L1d: 32 KB | 512 KB | PowerVR SGX535 | 1 | 2 | 16 | 200 MHz - 250 MHz | 6.4 GFLOPS - 8.0 GFLOPS |
| A4 | APL0398 | S5L8930 | | 45 nm | Samsung | | 53.3 mm² | ARMv7 | 32-bit | Cortex-A8 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | Single-core | 800 MHz | L1i: 32 KB L1d: 32 KB | 512 KB | PowerVR SGX535 | 1 | 2 | 16 | 200 MHz - 250 MHz | 6.4 GFLOPS - 8.0 GFLOPS |
| A5 | APL0498 | S5L8940 | | 45 nm | Samsung | | 122.2 mm² | ARMv7 | 32-bit | Cortex-A9 | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 800 MHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 2 | 4 | 32 | 200 MHz | 12.8 GFLOPS |
| A5 | APL0498 | S5L8940 | | 45 nm | Samsung | | 122.2 mm² | ARMv7 | 32-bit | Cortex-A9 | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.0 GHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 2 | 4 | 32 | 200 MHz | 12.8 GFLOPS |
| A5 | APL2498 | S5L8942 | | 32 nmHκ MG | Samsung | | 69.6 mm² | ARMv7 | 32-bit | Cortex-A9 | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 800 MHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 2 | 4 | 32 | 200 MHz | 12.8 GFLOPS |
| A5 | APL2498 | S5L8942 | | 32 nmHκ MG | Samsung | | 69.6 mm² | ARMv7 | 32-bit | Cortex-A9 | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.0 GHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 2 | 4 | 32 | 200 MHz | 12.8 GFLOPS |
| A5 | APL2498 | S5L8942 | | 32 nmHκ MG | Samsung | | 69.6 mm² | ARMv7 | 32-bit | Cortex-A9 | 2 (One core locked) | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.0 GHz | Dual-coreSingle-core in actual | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 2 | 4 | 32 | 200 MHz | 12.8 GFLOPS |
| A5 | APL7498 | S5L8947 | | 32 nmHκ MG | Samsung | | 37.8 mm² | ARMv7 | 32-bit | Cortex-A9 | 1 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.0 GHz | Single-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 2 | 4 | 32 | 200 MHz | 12.8 GFLOPS |
| A5X | APL5498 | S5L8945 | | 45 nm | Samsung | | 165 mm² | ARMv7 | 32-bit | Cortex-A9 | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.0 GHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 4 | 8 | 64 | 200 MHz | 25.6 GFLOPS |
| A6 | APL0598 | S5L8950 | | 32 nmHκ MG | Samsung | | 96.71 mm² | ARMv7s | 32-bit | Swift | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.3 GHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX543 | 3 | 6 | 48 | 266 MHz | 68.0 GFLOPS |
| A6X | APL5598 | S5L8955 | | 32 nmHκ MG | Samsung | | 123 mm² | ARMv7s | 32-bit | Swift | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.4 GHz | Dual-core | L1i: 32 KB L1d: 32 KB | 1 MB | PowerVR SGX554 | 4 | 16 | 128 | 300 MHz | 76.8 GFLOPS |
| A7 | APL0698 | S5L8960 | | 28 nm Hκ MG | Samsung | 1 billion | 102 mm² | ARMv8.0-A | 64-bit | Cyclone | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.3 GHz | Dual-core | L1i: 64 KB L1d: 64 KB | 1 MB | 4 MB (Inclusive) | 4 | 16 | 128 | PowerVR G6430 | 450 MHz | 115.2 GFLOPS |
| A7 | APL5698 | S5L8965 | | 28 nm Hκ MG | Samsung | 1 billion | 102 mm² | ARMv8.0-A | 64-bit | Cyclone | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.4 GHz | Dual-core | L1i: 64 KB L1d: 64 KB | 1 MB | 4 MB (Inclusive) | 4 | 16 | 128 | PowerVR G6430 | 450 MHz | 115.2 GFLOPS |
| A8 | APL1011 | T7000 | | 20 nm Hκ MG | TSMC | 2 billion | 89 mm² | ARMv8.0-A | 64-bit | Typhoon | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.1 GHz | Dual-core | L1i: 64 KB L1d: 64 KB | 1 MB | 4 MB (Inclusive) | 4 | 16 | 128 | PowerVR GX6450 | 533 MHz | 136.4 GFLOPS |
| A8 | APL1011 | T7000 | | 20 nm Hκ MG | TSMC | 2 billion | 89 mm² | ARMv8.0-A | 64-bit | Typhoon | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.4 GHz | Dual-core | L1i: 64 KB L1d: 64 KB | 1 MB | 4 MB (Inclusive) | 4 | 16 | 128 | PowerVR GX6450 | 533 MHz | 136.4 GFLOPS |
| A8 | APL1011 | T7000 | | 20 nm Hκ MG | TSMC | 2 billion | 89 mm² | ARMv8.0-A | 64-bit | Typhoon | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 1.4 GHz | Dual-core | L1i: 64 KB L1d: 64 KB | 1 MB | 4 MB (Inclusive) | 4 | 16 | 128 | PowerVR GX6450 | 533 MHz | 136.4 GFLOPS | 1.5 GHz |
| A8 | APL1011 | T7000 | | 20 nm Hκ MG | TSMC | 2 billion | 89 mm² | ARMv8.0-A | 64-bit | Typhoon | 2 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | A8X | Dual-core | L1i: 64 KB L1d: 64 KB | 1 MB | 4 MB (Inclusive) | 4 | 16 | 128 | PowerVR GX6450 | 533 MHz | 136.4 GFLOPS | APL1021 | T7001 | | 3 billion | 128 mm² | 3 | 1.5 GHz | 3-core | 2 MB | PowerVR GX6850 | 8 | 32 | 256 | 450 MHz | 230.4 GFLOPS |
| A9 | APL0898 | S8000 | | 20 nm Hκ MG | TSMC | 14 nmFinFET | Samsung | ARMv8.0-A | 64-bit | Typhoon | ≥ 2 billion | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 96 mm² | Twister | L1i: 64 KB L1d: 64 KB | 2 | 4 MB (Inclusive) | 1.85 GHz | Dual-core | 3 MB | 4 MB (Victim) | PowerVR GT7600 | 6 | 24 | 192 | 650 MHz | 249.6 GFLOPS |
| A9 | APL1022 | S8003 | | 16 nm FinFET | TSMC | 104.5 mm² | | ARMv8.0-A | 64-bit | | ≥ 2 billion | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | | Twister | L1i: 64 KB L1d: 64 KB | 2 | | 1.85 GHz | Dual-core | 3 MB | 4 MB (Victim) | PowerVR GT7600 | 6 | 24 | 192 | 650 MHz | 249.6 GFLOPS |
| A9X | APL1021 | S8001 | | 16 nm FinFET | TSMC | ≥ 3 billion | 143.9 mm² | ARMv8.0-A | 64-bit | N/D | PowerVR GT7850 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 12 | Twister | L1i: 64 KB L1d: 64 KB | 2 | 48 | 384 | Dual-core | 3 MB | 650 MHz | 499.2 GFLOPS |
| A9X | APL1021 | S8001 | | 16 nm FinFET | TSMC | ≥ 3 billion | 143.9 mm² | ARMv8.0-A | 64-bit | N/D | PowerVR GT7850 | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 12 | Twister | L1i: 64 KB L1d: 64 KB | 2 | 48 | 384 | Dual-core | 3 MB | 650 MHz | 499.2 GFLOPS | 2.26 GHz |
| A10 Fusion | APL1W24 | T8010 | | 16 nm FinFET | TSMC | 3.3 billion | 125 mm² | ARMv8.0-A | 64-bit | ARMv8.1-A | Hurricane | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D|rowspan=27 style="background: #ececec; color: grey; vertical-align: middle; text-align: center; " class="table-na" | N/D | 2 | 1.64 GHz | L1i: 64 KB L1d: 64 KB | Zephyr | 2 | 1.09 GHz | Quad-core(Only 2 cores performed at a same time) | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 3 MB E-core: 1 MB | 4 MB | PowerVR GT7600 Plus | 6 | 24 | 192 | 900 MHz | 345.6 GFLOPS |
| A10 Fusion | APL1W24 | T8010 | | 16 nm FinFET | TSMC | 3.3 billion | 125 mm² | 2.34 GHz | 64-bit | ARMv8.1-A | Hurricane | | 2 | | | Zephyr | 2 | 1.09 GHz | Quad-core(Only 2 cores performed at a same time) | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 3 MB E-core: 1 MB | 4 MB | PowerVR GT7600 Plus | 6 | 24 | 192 | 900 MHz | 345.6 GFLOPS |
| A10 Fusion | APL1W24 | T8010 | | 16 nm FinFET | TSMC | 3.3 billion | 125 mm² | 2.34 GHz | 64-bit | ARMv8.1-A | Hurricane | A10X Fusion | 2 | APL1071 | T8011 | Zephyr | 2 | 1.09 GHz | Quad-core(Only 2 cores performed at a same time) | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 3 MB E-core: 1 MB | 4 MB | PowerVR GT7600 Plus | 6 | 24 | 192 | 900 MHz | 345.6 GFLOPS | | 10 nmFinFET | ≥ 4 billion | 96.4 mm² | 3 | 2.38 GHz | 3 | 1.30 GHz | 6-core(Only 3 cores performed at a same time) | P-core: 8 MB E-core: 1 MB | N/D | 4 MB | 12 | 48 | 384 | 1000 MHz | 768.0 GFLOPS |
| A11Bionic | APL1W72 | T8015 | | 4.3 billion | TSMC | 87.66 mm² | ARMv8.2-A | Monsoon | 64-bit | ARMv8.1-A | Hurricane | A10X Fusion | 2 | APL1071 | T8011 | Zephyr | 2.39 GHz | Mistral | 4 | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | 1.19 GHz | 6-core | PowerVR GT7600 Plus | First generation Apple-designed | 3 | 24 | 192 | 1066 MHz | | 10 nmFinFET | ≥ 4 billion | 96.4 mm² | 3 | 2.38 GHz | 3 | 1.30 GHz | 6-core(Only 3 cores performed at a same time) | P-core: 8 MB E-core: 1 MB | N/D | 4 MB | 12 | 48 | 384 | 1000 MHz | 768.0 GFLOPS | 409.3 GFLOPS |
| A11Bionic | APL1W72 | T8015 | | 4.3 billion | TSMC | 87.66 mm² | ARMv8.2-A | Monsoon | 64-bit | ARMv8.1-A | Hurricane | A12Bionic | 2 | APL1W81 | T8020 | Zephyr | 2.39 GHz | Mistral | 4 | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | 1.19 GHz | 6-core | PowerVR GT7600 Plus | First generation Apple-designed | 3 | 24 | 192 | 1066 MHz | | 10 nmFinFET | 7 nm (N7) FinFET | 6.9 billion | 83.27 mm² | ARMv8.3-A | Vortex | 2.49 GHz | Tempest | P-core: 8 MB E-core: 1 MB | N/D | 4 MB | 1.59 GHz | P-core: L1i: 128 KB L1d: 128 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 8 MB E-core: 2 MB | 8 MB | Second generation Apple-designed | 409.3 GFLOPS | 4 | 32 | 256 | 1125 MHz | 576.0 GFLOPS |
| A12X Bionic | APL1083 | T8027 | | 10 billion | TSMC | 135 mm² | 4 | 8-core | 64-bit | 7 | 56 | A12Bionic | 2 | APL1W81 | T8020 | 448 | 1340 MHz | 1.20 TFLOPS | 4 | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | | 6-core | | | | | | | | 10 nmFinFET | 7 nm (N7) FinFET | 6.9 billion | 83.27 mm² | ARMv8.3-A | Vortex | 2.49 GHz | Tempest | P-core: 8 MB E-core: 1 MB | N/D | 4 MB | 1.59 GHz | P-core: L1i: 128 KB L1d: 128 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 8 MB E-core: 2 MB | 8 MB | Second generation Apple-designed | | 4 | 32 | 256 | 1125 MHz | 576.0 GFLOPS |
| A12X Bionic | APL1083 | T8027 | | 10 billion | TSMC | 135 mm² | 4 | 8-core | 64-bit | 7 | 56 | A12Z Bionic | 2 | | 8 | 448 | 1340 MHz | 1.20 TFLOPS | 4 | P-core: L1i: 64 KB L1d: 64 KB E-core: L1i: 32 KB L1d: 32KB | 64 | 6-core | 512 | 1.37 TFLOPS | | | | | | | 7 nm (N7) FinFET | | | ARMv8.3-A | Vortex | 2.49 GHz | Tempest | | N/D | | 1.59 GHz | P-core: L1i: 128 KB L1d: 128 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 8 MB E-core: 2 MB | 8 MB | Second generation Apple-designed |
| A13Bionic | APL1083 | T8027 | APL1W85 | 10 billion | TSMC | 135 mm² | 4 | 8-core | 64-bit | T8030 | | A12Z Bionic | 7 nm (N7P) FinFET | | 8 | 8.5 billion | 1340 MHz | 98.48 mm² | 4 | ARMv8.4-A | 64 | Lightning | 512 | 1.37 TFLOPS | 2 | 2.65 GHz | Thunder | 1.72 GHz | 6-core | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 96 KB L1d: 48 KB | 7 nm (N7) FinFET | P-core: 8 MB E-core: 4 MB | 16 MB | ARMv8.3-A | Vortex | 2.49 GHz | Tempest | Third generation Apple-designed | N/D | 4 | 1.59 GHz | P-core: L1i: 128 KB L1d: 128 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 8 MB E-core: 2 MB | 8 MB | Second generation Apple-designed | 32 | 256 | 1350 MHz | 691.2 GFLOPS |
| A13Bionic | APL1083 | T8027 | APL1W85 | 10 billion | TSMC | 135 mm² | 4 | 8-core | 64-bit | T8030 | | A14Bionic | 7 nm (N7P) FinFET | APL1W01 | T8101 | 8.5 billion | 1340 MHz | 98.48 mm² | 4 | ARMv8.4-A | | Lightning | 5 nm (N5) FinFET | 11.8 billion | 2 | 2.65 GHz | Thunder | 1.72 GHz | 6-core | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 96 KB L1d: 48 KB | 7 nm (N7) FinFET | P-core: 8 MB E-core: 4 MB | 16 MB | ARMv8.3-A | Vortex | 2.49 GHz | Tempest | Third generation Apple-designed | N/D | 4 | 1.59 GHz | P-core: L1i: 128 KB L1d: 128 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 8 MB E-core: 2 MB | 8 MB | Second generation Apple-designed | 32 | 256 | 1350 MHz | 691.2 GFLOPS | 88 mm² | ARMv8.5-A | Firestorm | 3.09 GHz | Icestorm | 1.82 GHz | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 128 KB L1d: 64 KB | Fourth generation Apple-designed | 64 | 512 | 1000 MHz | 1.0 TFLOPS |
| A15Bionic | APL1W07 | T8110 | | 5 nm (N5P) FinFET | TSMC | 15 billion | 107.68 mm² | Avalanche | 64-bit | 3.23 GHz | Blizzard | A14Bionic | 2.02 GHz | APL1W01 | T8101 | P-core: 12 MB E-core: 4 MB | 32 MB | Fifth generation Apple-designed | 4 | 128 | | 1024 | 5 nm (N5) FinFET | 11.8 billion | 2 | 600 MHz | 1.2 TFLOPS | | 6-core | | 7 nm (N7) FinFET | P-core: 8 MB E-core: 4 MB | 16 MB | ARMv8.3-A | Vortex | 2.49 GHz | Tempest | | N/D | 4 | 1.59 GHz | P-core: L1i: 128 KB L1d: 128 KB E-core: L1i: 32 KB L1d: 32KB | P-core: 8 MB E-core: 2 MB | 8 MB | Second generation Apple-designed | | | | | 88 mm² | ARMv8.5-A | Firestorm | 3.09 GHz | Icestorm | 1.82 GHz | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 128 KB L1d: 64 KB | Fourth generation Apple-designed | 64 | 512 | 1000 MHz | 1.0 TFLOPS |
| A15Bionic | APL1W07 | T8110 | | 5 nm (N5P) FinFET | TSMC | 15 billion | 107.68 mm² | Avalanche | 64-bit | 2.93 GHz | Blizzard | 5 | 2.02 GHz | 160 | 1280 | P-core: 12 MB E-core: 4 MB | 32 MB | Fifth generation Apple-designed | 4 | 1.5 TFLOPS | | | | | 2 | 600 MHz | | | 6-core | | | P-core: 8 MB E-core: 4 MB | 16 MB | | | | | | N/D | 4 | | | | | | | | | | | ARMv8.5-A | | | | | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 128 KB L1d: 64 KB |
| A15Bionic | APL1W07 | T8110 | | 5 nm (N5P) FinFET | TSMC | 15 billion | 107.68 mm² | Avalanche | 64-bit | 3.23 GHz | Blizzard | 5 | 2.02 GHz | 160 | 1280 | P-core: 12 MB E-core: 4 MB | 32 MB | Fifth generation Apple-designed | 4 | 1.5 TFLOPS | | | | | 2 | 600 MHz | | | 6-core | | | | | | | | | | N/D | 4 | | | | | | | | | | | ARMv8.5-A | | | | | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 128 KB L1d: 64 KB |
| A16Bionic | APL1W10 | T8120 | | 5 nm (N4) - marketed as "4nm" FinFET | TSMC | 16 billion | | ARMv9 | 64-bit | Everest | 3.46 GHz | 5 | 2.02 GHz | Sawtooth | Sixth generation Apple-designed | P-core: 12 MB E-core: 4 MB | 32 MB | 160 | 4 | 1280 | 700 MHz | 2.0 TFLOPS (FP32 Single Precision) | | | 2 | | | | 6-core | | | | | | | | | | N/D | | | | | | | | | | | | ARMv8.5-A | | | | | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 128 KB L1d: 64 KB |
| Nom | Renom | Part No. | Imatge | Node | TSMC | Fabricant | Transistors nº | Mida Dau | 64-bit | CPU ISA | Bits | Core name | Cores | Core speed | Core name | Cores | Core speed | Overall cores | 4 | L1 | L2 | L3 | SLC | Vendor | 2 | Cores | | | 6-core | | | | | | | | | | N/D | | | | | | | | | | | | | | | | | P-core: L1i: 192 KB L1d: 128 KB E-core: L1i: 128 KB L1d: 64 KB |
| Nom | Renom | Part No. | Imatge | Node | TSMC | Fabricant | Transistors nº | Mida Dau | 64-bit | CPU ISA | Bits | Performance core | Performance core | Performance core | Efficiency core | Efficiency core | Efficiency core | Overall cores | 4 | Cache | Cache | Cache | Cache | | | | Vendor | 2 | Cores | | | 6-core | | | | | | | | | | N/D |
| General | General | General | Imatge | Tecnologia | Tecnologia | Tecnologia | Tecnologia | Arquitectura | Arquitectura | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | CPU | GPU | GPU | GPU | GPU | GPU | GPU | | | | | | | | | | | | | | | | | | N/D |

## Referències

* ↑ Error en sol·licitar la Plantilla:cite press release: El paràmetre title ha d'estar especificat.
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* ↑ Shimpi, Anand Lal. «The iPhone 5s Review: The Move to 64-bit». AnandTech, 17-09-2013. Arxivat de l'original el 21 setembre 2013. [Consulta: 18 setembre 2013].
* 1 2 Shimpi, Anand Lal. «The iPhone 5s Review: After Swift Comes Cyclone». AnandTech, 17-09-2013. Arxivat de l'original el 21 setembre 2013. [Consulta: 18 setembre 2013].
* 1 2 «The iPhone 6 Review: A8's CPU: What Comes After Cyclone?». AnandTech, 30-09-2014. Arxivat de l'original el 15 maig 2015. [Consulta: 30 setembre 2014].
* 1 2 3 «Correcting Apple's A9 SoC L3 Cache Size: A 4MB Victim Cache». AnandTech, 30-11-2015. Arxivat de l'original el 1 desembre 2015. [Consulta: 1r desembre 2015].
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* ↑ Shimpi, Anand Lal. «The iPhone 5s Review: GPU Architecture». AnandTech, 17-09-2013. Arxivat de l'original el 21 setembre 2013. [Consulta: 18 setembre 2013].
* ↑ «The iPhone 6 Review: A8: Apple's First 20nm SoC». AnandTech, 30-09-2014. Arxivat de l'original el 1 octubre 2014. [Consulta: 30 setembre 2014].
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* 1 2 3 «Apple A8X's GPU - GXA6850, Even Better Than I Thought». Anandtech, 11-11-2014. Arxivat de l'original el 30 novembre 2014. [Consulta: 12 novembre 2014].
* 1 2 «Imagination PowerVR GXA6850 - NotebookCheck.net Tech». NotebookCheck.net, 26-11-2014. Arxivat de l'original el 29 novembre 2014. [Consulta: 26 novembre 2014].
* 1 2 3 4 5 Kanter, David. «A Look Inside Apple's Custom GPU for the iPhone» (en anglès americà). Arxivat de l'original el 27 agost 2019. [Consulta: 27 agost 2019].
* ↑ «Chipworks Disassembles Apple's A8 SoC: GX6450, 4MB L3 Cache & More». AnandTech, 23-09-2014. Arxivat de l'original el 23 setembre 2014. [Consulta: 23 setembre 2014].
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* ↑ Ho, Joshua. «Apple Announces the iPhone 6s and iPhone 6s Plus», 09-09-2015. Arxivat de l'original el 10 setembre 2015. [Consulta: 10 setembre 2015].
* 1 2 3 «Apple's A9 SoC Is Dual Sourced From Samsung & TSMC». Anandtech, 28-09-2015. Arxivat de l'original el 30 setembre 2015. [Consulta: 29 setembre 2015].
* ↑ «iPhone 6s customer receives her device early, benchmarks show a marked increase in power». iDownloadBlog, 21-09-2015. Arxivat de l'original el 24 setembre 2015. [Consulta: 25 setembre 2015].
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* 1 2 3 4 «More on Apple's A9X SoC: 147mm2@TSMC, 12 GPU Cores, No L3 Cache». AnandTech, 30-11-2015. Arxivat de l'original el 1 desembre 2015. [Consulta: 1r desembre 2015].
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* 1 2 3 Wei, Andy. «10 nm Process Rollout Marching Right Along». TechInsights, 29-06-2017. Arxivat de l'original el 3 agost 2017. [Consulta: 30 juny 2017].
* ↑ «Intel Core i5-8250U vs Apple A10 Fusion». Arxivat de l'original el 27 desembre 2019. [Consulta: 27 desembre 2019].
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* ↑ Smith, Ryan. «TechInsights Confirms Apple's A10X SoC Is TSMC 10nm FF; 96.4mm2 Die Size». AnandTech, 29-06-2017. Arxivat de l'original el 2 juliol 2017. [Consulta: 30 juny 2017].
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* ↑ «Apple iPhone 8 Plus Teardown». TechInsights, 27-09-2017. Arxivat de l'original el 27 setembre 2017. [Consulta: 28 setembre 2017].
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* ↑ «A13 has ARMv8.4, apparently (LLVM project sources, thanks, @Longhorn)». Jonathan Levin, @Morpheus, 13-03-2020. Arxivat de l'original el 10 març 2020. [Consulta: 13 març 2020].
* 1 2 Cross, Jason. «A14 Bionic FAQ: What you need to know about Apple's 5nm processor» (en anglès americà), 14-10-2020. [Consulta: 2 abril 2021].
* ↑ Patel, Dylan. «Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims» (en anglès americà), 27-10-2020. Arxivat de l'original el 12 de desembre 2020. [Consulta: 29 octubre 2020].
* ↑ Frumusanu, Andrei. «The iPhone 12 & 12 Pro Review: New Design and Diminishing Returns» (en anglès americà), 30-11-2020. [Consulta: 2 abril 2021].
* ↑ «All-new iPad Air with advanced A14 Bionic chip available to order starting today» (en anglès americà), 16-10-2020.
* ↑ Frumusanu, Andrei. «Apple Announces new 8th gen iPad with A12, iPad Air with 5nm A14 Chip» (en anglès americà), 15-09-2020. [Consulta: 7 abril 2021].
* 1 2 «Apple iPhone 13 Pro Teardown | TechInsights».
* ↑ Sohail, Omar. «iPhone 13 With 4-Core GPU Scores Significantly Less Than iPhone 13 Pro; Only 15 Percent Higher Than iPhone 12 Pro» (en anglès americà), 16-09-2021. [Consulta: 17 setembre 2021].
* ↑ Roberts, Dave. «Discover advances in Metal for A15 Bionic» (en anglès americà), 18-09-2021. [Consulta: 12 novembre 2021].
* ↑ Sohail, Omar. «iPhone 13 Pro With 5-Core GPU Obtains a Remarkable 55 Percent Performance Increase Over iPhone 12 Pro» (en anglès americà), 15-09-2021. [Consulta: 19 setembre 2021].
* 1 2 3 «Apple A15 (4 GPU Cores)» (en anglès). [Consulta: 16 setembre 2022].
* 1 2 3 «Apple A15 (5 GPU Cores)» (en anglès). [Consulta: 16 setembre 2022].
* ↑ «Iphone 14 pro teardown ! Iphone 14 pro disassembly ! Iphone 14 teardown ! Iphone 14 pro max teardown» (en anglès). [Consulta: 16 setembre 2022].
* ↑ «Logic Technology», 08-09-2022. Arxivat de l'original el 2022-09-08. [Consulta: 18 setembre 2022].
* ↑ Schor, David. «TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node» (en anglès americà), 26-10-2021. [Consulta: 8 setembre 2022].
* ↑ «N3E Replaces N3; Comes In Many Flavors» (en anglès americà), 04-09-2022. [Consulta: 10 setembre 2022].
* ↑ «Apple A16 Bionic: All you need to know about the new chip» (en anglès), 07-09-2022. [Consulta: 11 setembre 2022].
* ↑ «Apple A16 Bionic Benchmark, Test and specs» (en anglès). [Consulta: 11 setembre 2022].
* 1 2 «The codename of the CPU core of A16 for iPhone14 Pro is revealed-posted by leaker» (en anglès americà). [Consulta: 13 setembre 2022].
* 1 2 Buckner, Sanjay. «Apple's A16 Bionic Gets New Cores, Now Codenamed After Mountains» (en anglès americà), 13-09-2022. Arxivat de l'original el 2022-09-13. [Consulta: 13 setembre 2022].
* 1 2 3 4 «Apple A16 (5 GPU Cores)» (en anglès). [Consulta: 16 setembre 2022].