windowsでiverilog その162

# 概要　
windowsでiverilogやってみた。
cpu見つけたので、勝手にマシン語、作ってみた。
アセンブラ書いてみた。
verilogで、cpu書いてみた。

# 参考にしたページ

https://qiita.com/KajizukaTaichi/items/2da92161db1355466b5c

# サンプルコード

```


module cpu72(input clk, input rst);
	parameter N = 32;
	integer i,
			j,
			ipc;
	real v,
		pc,
		ar,
		dr,
		cr,
		ba,
		sp,
		ra,
		va;
	reg [71:0] rom[32:0];
	reg [71:0] ram[32:0];
	reg [71:0] stack[0:N - 1];
	reg jpflg;
	wire [71:0] code;
	wire [4:0] op;
	wire [2:0] rg;
	wire [63:0] opland;
	task push;
		begin
			for (i = 1; i < N; i = i + 1)
				stack[i] <= stack[i - 1];
		end
	endtask
	task pop;
		begin
			for (i = 0; i < N - 1; i = i + 1)
				stack[i] <= stack[i + 1];
		end
	endtask
	assign code = rom[ipc];
	assign op = code[71:67];
	assign rg = code[66:64];
	assign opland = code[63:0];
	always @(posedge clk)
	begin
		if (rst)
		begin
// main  psh  5       
	rom[0] <= 72'hB84014000000000000;
//   psh  8
	rom[1] <= 72'hB84020000000000000;
//   psh  2
	rom[2] <= 72'hB84000000000000000;
//   cal  sum     
	rom[3] <= 72'h884022000000000000;
//   pop  ar      
	rom[4] <= 72'hB10000000000000000;
//   mov  ba  8   
	rom[5] <= 72'h0C4020000000000000;
//   sta  ba  ar  
	rom[6] <= 72'hC40000000000000000;
//   mov  va  ar
	rom[7] <= 72'h0E0000000000000000;
//   hlt         
	rom[8] <= 72'hF80000000000000000;
// sum  mov  ar  0           
	rom[9] <= 72'h090000000000000000;
// loop_start  mov  cr  sp
	rom[10] <= 72'h4B0000000000000000;
//   nor  cr  cr          
	rom[11] <= 72'h430000000000000000;
//   jmp  cr  loop_end    
	rom[12] <= 72'h834030000000000000;
// loop_body  pop  dr              
	rom[13] <= 72'hB20000000000000000;
//   add  ar  dr          
	rom[14] <= 72'h110000000000000000;
//   jmp  1  loop_start   
	rom[15] <= 72'h814024000000000000;
// loop_end  psh  ar              
	rom[16] <= 72'hA80000000000000000;
//   ret
	rom[17] <= 72'h900000000000000000;
			for (i = 0; i < N; i = i + 1)
				stack[i] <= 0;
			jpflg <= 0;
			ipc <= 0;
			ra <= 0;
			pc <= 0;
			ar <= 0;
			dr <= 0;
			cr <= 0;
			ba <= 0;
			sp <= 0;
			va <= 0;
			ram[0] <= 0;
			ram[1] <= 0;
			ram[2] <= 0;
			ram[8] <= 0;
		end
		else
		begin
			case (op)
			5'h00://nop
			begin
			end
			5'h01://mov
			begin
				case (rg)
				3'h1://ar
				begin
					v = $bitstoreal(opland);
					ar <= v;
				end
				3'h3://cr
				begin
					cr <= sp;
				end
				3'h4://ba
				begin
					v = $bitstoreal(opland);
					ba <= v;
				end
				3'h6://va
				begin
					va <= ar;
				end
				endcase
			end
			5'h02://add
			begin
				ar <= ar + dr;
			end
			5'h08://nor
			begin
				case (rg)
				3'h3://cr
				begin
					if (cr == 0)
					begin
						cr <= 1;
					end
					else
					begin
						cr <= 0;
					end
				end
				endcase
			end
			5'h09://mov
			begin
				cr <= sp;
			end
			5'h10://jmp
			begin
				case (rg)
				3'h1://1
				begin
					jpflg = 1;
					v = $bitstoreal(opland);
					pc = v;
					ipc = pc;
				end
				3'h3://cr
				begin
					if (cr != 0)
					begin
						jpflg = 1;
						v = $bitstoreal(opland);
						pc = v;
						ipc = pc;
					end
				end
				endcase
			end
			5'h11://cal
			begin
				j = ipc + 1;
				ra = j;
				jpflg = 1;
				v = $bitstoreal(opland);
				pc = v;
				ipc = pc;
			end
			5'h12://ret
			begin
				jpflg = 1;
				pc = ra;
				ipc = pc;
			end
			5'h13://lda
			begin
			end
			5'h14://sta
			begin
			end
			5'h15://psh reg
			begin
				push;
				stack[0] <= ar;
				sp <= sp + 1;
			end
			5'h16://pop
			begin
				case (rg)
				3'h1://ar
				begin
					ar <= stack[0];
					pop;
					sp <= sp - 1;
				end
				3'h2://dr
				begin
					dr <= stack[0];
					pop;
					sp <= sp - 1;
				end
				endcase
			end
			5'h17://psh opland
			begin
				push;
				v = $bitstoreal(opland);
				stack[0] = v;
				sp = sp + 1;
			end
			5'h18://sta
			begin
				j = ba;
				ram[j] <= ar;
			end
			5'h1f://hlt
			begin
				pc <= pc - 1;
			end
			endcase
			if (jpflg == 0)
			begin
				pc = pc + 1;
				ipc = pc;
			end
			else
			begin
				jpflg <= 0;
			end
		end
	end
	initial
	begin
		$display("ipc,   code,                op,  rg,  ar,  cr,  dr,  ba,   sp,  va,  stack0,    stack1,    stack2, ram[8]");
		$monitor(" %d    %h     %h    %d     %d    %d    %d    %d    %d    %d   %f   %f   %f   %f", pc, code, op, rg, ar, cr, dr, ba, sp, va, stack[0], stack[1], stack[2], ram[8]);
	end
endmodule


module test;
	reg clk,
		rst;
	cpu72 u(.clk(clk), .rst(rst));
	initial
	begin
		clk = 0;
		rst = 0;
		#1
			rst = 1;
		#1
			rst = 0;
		#100
			$finish;
	end
	always
		#1
			clk = ~clk;
endmodule





```

# 実行結果

```
>vvp a.out
ipc,   code,                op,  rg,  ar,  cr,  dr,  ba,   sp,  va,  stack0,    stack1,    stack2, ram[8]
 0    xxxxxxxxxxxxxxxxxx     xx    x     0    0    0    0    0    0   0.000000   0.000000   0.000000   0.000000
 0    b84014000000000000     17    0     0    0    0    0    0    0   0.000000   0.000000   0.000000   0.000000
 1    b84020000000000000     17    0     0    0    0    0    1    0   5.000000   0.000000   0.000000   0.000000
 2    b84000000000000000     17    0     0    0    0    0    2    0   8.000000   5.000000   0.000000   0.000000
 3    884022000000000000     11    0     0    0    0    0    3    0   2.000000   8.000000   5.000000   0.000000
 9    090000000000000000     01    1     0    0    0    0    3    0   2.000000   8.000000   5.000000   0.000000
 10    4b0000000000000000     09    3     0    0    0    0    3    0   2.000000   8.000000   5.000000   0.000000
 11    430000000000000000     08    3     0    3    0    0    3    0   2.000000   8.000000   5.000000   0.000000
 12    834030000000000000     10    3     0    0    0    0    3    0   2.000000   8.000000   5.000000   0.000000
 13    b20000000000000000     16    2     0    0    0    0    3    0   2.000000   8.000000   5.000000   0.000000
 14    110000000000000000     02    1     0    0    2    0    2    0   8.000000   5.000000   0.000000   0.000000
 15    814024000000000000     10    1     2    0    2    0    2    0   8.000000   5.000000   0.000000   0.000000
 10    4b0000000000000000     09    3     2    0    2    0    2    0   8.000000   5.000000   0.000000   0.000000
 11    430000000000000000     08    3     2    2    2    0    2    0   8.000000   5.000000   0.000000   0.000000
 12    834030000000000000     10    3     2    0    2    0    2    0   8.000000   5.000000   0.000000   0.000000
 13    b20000000000000000     16    2     2    0    2    0    2    0   8.000000   5.000000   0.000000   0.000000
 14    110000000000000000     02    1     2    0    8    0    1    0   5.000000   0.000000   0.000000   0.000000
 15    814024000000000000     10    1     10    0    8    0    1    0   5.000000   0.000000   0.000000   0.000000
 10    4b0000000000000000     09    3     10    0    8    0    1    0   5.000000   0.000000   0.000000   0.000000
 11    430000000000000000     08    3     10    1    8    0    1    0   5.000000   0.000000   0.000000   0.000000
 12    834030000000000000     10    3     10    0    8    0    1    0   5.000000   0.000000   0.000000   0.000000
 13    b20000000000000000     16    2     10    0    8    0    1    0   5.000000   0.000000   0.000000   0.000000
 14    110000000000000000     02    1     10    0    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 15    814024000000000000     10    1     15    0    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 10    4b0000000000000000     09    3     15    0    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 11    430000000000000000     08    3     15    0    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 12    834030000000000000     10    3     15    1    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 16    a80000000000000000     15    0     15    1    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 17    900000000000000000     12    0     15    1    5    0    1    0   15.000000   0.000000   0.000000   0.000000
 4    b10000000000000000     16    1     15    1    5    0    1    0   15.000000   0.000000   0.000000   0.000000
 5    0c4020000000000000     01    4     15    1    5    0    0    0   0.000000   0.000000   0.000000   0.000000
 6    c40000000000000000     18    4     15    1    5    8    0    0   0.000000   0.000000   0.000000   0.000000
 7    0e0000000000000000     01    6     15    1    5    8    0    0   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     15    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     15    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 7    090000000000000000     01    1     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
 8    f80000000000000000     1f    0     0    1    5    8    0    15   0.000000   0.000000   0.000000   15.000000
ruka.v:266: $finish called at 102 (1s)

```


以上。