半導体工学その5



## ■ Analog IC Layout Design: Workflow and Key Considerations

Analog IC layout design is a critical phase in chip development where the physical implementation of the circuit is realized. Unlike digital design, analog layout demands high precision due to the sensitivity of circuit performance to parasitic effects, thermal gradients, symmetry, and matching. This stage directly affects **IC functionality, cost, yield, and reliability**.

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### ◉ General Workflow of Analog IC Layout

1. **Pin Assignment Planning**

   * Optimize for PCB trace routing and application-level accessibility.
   * Avoid signal interference, minimize solder bridging, and ensure mechanical robustness.

2. **Floor Planning**

   * Arrange functional blocks logically within the chip outline.
   * Consider symmetry, thermal distribution, power/ground routing, and area efficiency.

3. **Cell, Block, and Top-Level Layout**

   * Begin with individual cells (e.g., differential pairs, current mirrors), then build blocks and the full chip layout hierarchically.
   * Ensure alignment and regularity to facilitate matching and minimize variation.

4. **Routing and Pattern Generation**

   * Connect devices according to schematic.
   * Optimize trace widths, spacing, and current density; consider parasitic reduction.

5. **Layout Verification**

   * Run DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), and RC extraction.

6. **Post-Layout Simulation**

   * Use extracted parasitic values to verify performance under real-world physical effects.

7. **Mask Data Preparation and Design Review**

   * Generate GDSII files for mask fabrication after passing all verification steps.

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### ◉ Essential Layout Verification Techniques

* **DRC (Design Rule Check)**: Verifies geometric rules (e.g., minimum width, spacing).
* **LVS (Layout vs. Schematic)**: Confirms that the layout matches the schematic netlist.
* **ERC (Electrical Rule Check)**: Detects shorts, opens, floating nodes, and drive/load mismatches.
* **LPE/RCX (Parasitic Extraction)**: Outputs netlists with extracted parasitic resistances and capacitances for accurate simulation.

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### ◉ Manual Review Is Still Essential

Despite modern CAD tools, **manual inspection (visual layout review)** is indispensable, especially for analog circuits where automated tools may not detect:

* Mismatched device symmetry
* Improper shielding from thermal or mechanical stress
* Gate oxide damage from antenna effects
* Inadequate ESD protection or latch-up susceptibility
* Poor matching due to layout-induced parasitic variation

Cross-review by other designers (e.g., a junior designer reviewing a senior’s layout or vice versa) enhances error detection and spreads layout know-how.

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### ◉ Best Practices and Layout Techniques

#### 1. **Temperature-Aware Layout**

* Components susceptible to thermal mismatch (e.g., differential pairs) should be placed on **iso-thermal lines** to reduce drift due to temperature gradients.

#### 2. **Symmetry and Matching**

* Use **common-centroid layout** for matched pairs like MOSFETs or resistors to cancel out gradient-induced variations and lithographic distortion.

#### 3. **Dummy Elements**

* Add dummy devices around matched structures to ensure uniform etching and stress distribution, improving pattern fidelity and electrical matching.

#### 4. **Parasitic-Aware Routing**

* Optimize wire lengths and layer transitions to control resistance, capacitance, and inductive coupling. Avoid long signal traces near sensitive analog nodes.

#### 5. **ESD Protection**

* Include robust ESD clamps (diodes, SCRs, etc.) near bond pads. MOS input stages are especially vulnerable due to high input impedance.

#### 6. **Latch-Up Mitigation**

* Break parasitic SCR paths by minimizing substrate resistance, adding guard rings, and spacing out n+/p+ regions. Ensure low gain in parasitic transistors.

#### 7. **Antenna Effect Prevention**

* Prevent charge accumulation on floating metal lines by segmenting interconnects or adding discharge paths (e.g., diodes) during fabrication steps involving plasma.

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### ◉ Why Layout Quality Reflects Designer Expertise

In analog ICs, circuit performance can degrade drastically due to poor layout—even when the schematic is flawless. Key layout decisions directly influence:

* Functional correctness (e.g., matching, symmetry)
* Chip area and yield (e.g., cost optimization)
* Reliability and robustness (e.g., ESD, latch-up)
* Electrical noise immunity (e.g., shielding, isolation)

Experienced layout engineers balance design rules, circuit behavior, and physical constraints with skill, much like traditional craftsmanship. Well-designed analog layouts not only function as intended but also optimize size, yield, and long-term reliability.

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