multi core processor wiki reference check

There are some differences at English wiki and Japanese wiki.
References are quite different.
I should check the references on multi core processor wiki in English and Japanese,
After this, i will chekc the papers about multi core in arXiv.
Multi core include multi core fiber, processor and other meanings.

# wiki 
Multi-core_processor
https://en.wikipedia.org/wiki/Multi-core_processor
## 1
 Rouse, Margaret (March 27, 2007). "Definition: multi-core processor". TechTarget. Archived from the original on August 5, 2010. Retrieved March 6, 2013.
https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html 
## 2
 Schauer, Bryan. "Multicore Processors – A Necessity" (PDF). Archived from the original (PDF) on 2011-11-25.
https://web.archive.org/web/20111125035151/http://www.csa.com/discoveryguides/multicore/review.pdf
## 3
 Smith, Ryan. "NVIDIA Announces the GeForce RTX 30 Series: Ampere For Gaming, Starting With RTX 3080 & RTX 3090". www.anandtech.com. Retrieved 2020-09-15.
https://www.anandtech.com/show/16057/nvidia-announces-the-geforce-rtx-30-series-ampere-for-gaming-starting-with-rtx-3080-rtx-3090
## 4
 "Sunway TaihuLight - Sunway MPP, Sunway SW26010 260C 1.45GHz, Sunway | TOP500". www.top500.org. Retrieved 2020-09-15.
https://www.top500.org/system/178764/
## 5
Suleman, Aater (May 20, 2011). "What makes parallel programming hard?". FutureChips. Archived from the original on May 29, 2011. Retrieved March 6, 2013.
https://web.archive.org/web/20110529133159/http://www.futurechips.org/tips-for-power-coders/parallel-programming.html
## 6
 Duran, A (2011). "Ompss: a proposal for programming heterogeneous multi-core architectures". Parallel Processing Letters. 21 (2): 173–193. doi:10.1142/S0129626411000151.　https://www.worldscientific.com/doi/epdf/10.1142/S0129626411000151
https://www.researchgate.net/publication/220439810_Ompss_a_Proposal_for_Programming_Heterogeneous_Multi-Core_Architectures
## 7
"Definition of dual core". PCMAG. Retrieved 2023-10-27.
## 8
 "Intel taking its six-core processors mainstream in 2018 with Coffee Lake family". ZDNET. Retrieved 2023-10-27.
## 
 Alan Dexter (2022-04-05). "Six-core CPUs are now more popular than quad-core chips on Steam". PC Gamer. Retrieved 2024-05-22.
## 
 Schor, David (November 2017). "The 2,048-core PEZY-SC2 sets a Green500 record". WikiChip.
## 
 Vajda, András (2011-06-10). Programming Many-Core Chips. Springer. p. 3. ISBN 978-1-4419-9739-5.
## 
 Shrout, Ryan (December 2, 2009). "Intel Shows 48-core x86 Processor as Single-chip Cloud Computer". Archived from the original on January 5, 2016. Retrieved May 17, 2015.
## 
 "Intel unveils 48-core cloud computing silicon chip". BBC. December 3, 2009. Archived from the original on December 6, 2012. Retrieved March 6, 2013.
 ## 
 Patterson, David A. "Future of computer architecture." Berkeley EECS Annual Research Symposium (BEARS), College of Engineering, UC Berkeley, US. 2006.
## 
 Suleman, Aater (May 19, 2011). "Q & A: Do multicores save energy? Not really". Archived from the original on December 16, 2012. Retrieved March 6, 2013.
## 
 Clark, Jack. "Intel: Why a 1,000-core chip is feasible". ZDNet. Archived from the original on 6 August 2015. Retrieved 6 August 2015.
## 
 Kudikala, Chakri (Aug 27, 2016). "These 5 Myths About the Octa-Core Phones Are Actually True". Giz Bot.
## 
 "MediaTek Launches MT6592 True Octa-Core Mobile Platform" (Press release). MediaTek. November 20, 2013. Archived from the original on October 29, 2020.
## 
 "What is an Octa-core processor". Samsung. Archived from the original on January 17, 2022. Galaxy smartphones run on either Octa-core (2.3GHz Quad + 1.6GHz Quad) or Quad-core (2.15GHz + 1.6GHz Dual) processors
## 
 Merritt, Rick (February 6, 2008). "CPU designers debate multi-core future". EE Times. Retrieved October 21, 2023.
 "Multicore Packet Processing Forum". Archived from the original on 2009-12-21.
## 
 John Darlinton; Moustafa Ghanem; Yike Guo; Hing Wing To (1996). "Guided Resource Organisation in Heterogeneous Parallel Computing". Journal of High Performance Computing. 4 (1): 13–23. CiteSeerX 10.1.1.37.4309.
## 
 Bright, Peter (4 December 2015). "Windows Server 2016 moving to per core, not per socket, licensing". Ars Technica. Condé Nast. Archived from the original on 4 December 2015. Retrieved 5 December 2015.
## 
 Compare: "The Licensing Of Oracle Technology Products". OMT-CO Operations Management Technology Consulting GmbH. Archived from the original on 2014-03-21. Retrieved 2014-03-04.
## 
 "6WINDGATE Software: Network Optimization Software – SDN Software – Control Plane Software | 6WIND".
## 
 "Sempron™ 3850 APU with Radeon™ R3 Series | AMD". AMD. Archived from the original on 4 May 2019. Retrieved 5 May 2019.
## 
 "Intel® Atom™ Processor C Series Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 "Intel® Atom™ Processor Z Series Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 "Intel Preps Dual-Core Celeron Processors". 11 October 2007. Archived from the original on 4 November 2007. Retrieved 12 November 2007.
## 
 "Intel® Celeron® Processor J Series Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 "Products formerly Yonah". ark.intel.com. Retrieved 2019-05-04.
## 
 "Products formerly Conroe". ark.intel.com. Retrieved 2019-05-04.
## 
 "Products formerly Kentsfield". ark.intel.com. Retrieved 2019-05-04.
## 
 "Intel® Core™ X-series Processors Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 "Intel® Itanium® Processor Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 "Intel® Pentium® Processor D Series Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 Zazaian, Mike (September 26, 2006). "Intel: 80 Cores by 2011". Archived from the original on 2006-11-09. Retrieved 2006-09-28.
## 
 Kowaliski, Cyril (February 18, 2014). "Intel releases 15-core Xeon E7 v2 processor". Archived from the original on 2014-10-11.
## 
 "Intel Xeon Processor E7 v3 Family". Intel. Archived from the original on 2015-07-07.
## 
 "Intel Xeon Processor E7 v2 Family". Intel. Archived from the original on 2015-07-07.
## 
 "Intel Xeon Processor E3 v2 Family". Intel. Archived from the original on 2015-07-07.
## 
 "Intel shows off Xeon Platinum CPU with up to 56 cores and 112 threads". TechSpot. 2 
 ## 
April 2019. Retrieved 2019-05-04. PDF, Download. "2nd Gen Intel® Xeon® Scalable Processors Brief". Intel. Retrieved 2019-05-04.
## 
 "Intel® Xeon Phi™ x100 Product Family Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 "Intel® Xeon Phi™ 72x5 Processor Family Product Specifications". ark.intel.com. Retrieved 2019-05-04.
## 
 Cole, Bernard (September 24, 2008). "40-core processor with Forth-based IDE tools unveiled".
## 
 Hammond, Lance; et al. (1999). The Stanford Hydra CMP (PDF). Hot Chips. Retrieved 27 June 2023.
## 
 Chacos, Brad (June 20, 2016). "Meet KiloCore, a 1,000-core processor so efficient it could run on a AA battery". PC World. Archived from the original on June 23, 2016.
## "COSMIC:Statistical Multiprocessor Benchmark Suite".
 
# Wiki マルチコア
https://ja.wikipedia.org/wiki/マルチコア

## J1
インテル、メニーコア化への取り組みなど、研究活動に関する説明会を開催[リンク切れ], マイコミジャーナル, 2005年11月09日
~~https://news.mynavi.jp/news/2005/11/09/003.html~~

### intel many core 検索


+IntelのMany-core構想とCellの相違
https://pc.watch.impress.co.jp/docs/2005/1110/kaigai_1.pdf

## J2 
Univac® 1108 multiprocessor system
doi:10.1145/1465482.1465493

-> https://dl.acm.org/doi/pdf/10.1145/1465482.1465493

## J3
FACOM230-60（1968年） : 富士通2024年9月4日閲覧
https://www.fujitsu.com/jp/about/plus/museum/products/computer/mainframe/facom230-60.html

## J4
FACOM 230-60 - コンピュータ博物館2024年9月4日閲覧

## J5
 日立評論1974年1月号:電子計算機および計測2024年9月4日閲覧

## J6
HITAC 8800, 8700 - コンピュータ博物館2024年9月4日閲覧

## J7
TOSBAC-5600/10, 30, 50 - コンピュータ博物館2024年9月4日閲覧

## J8
技術の系統化調査報告「コンピュータ開発史概要と資料保存状況について -第3世代と第3.5世代コンピュータおよびスーパーコンピュータについて-」2024年9月4日閲覧、p. 28から引用「TOSBAC-5600は1970年に発表された汎用大型コンピュータで、密結合マルチプロセシングを前提に設計され、」

## 9
ACOSシリーズ77 システム600, 700 - コンピュータ博物館2024年9月4日閲覧

## 10
SXシリーズ 進化の軌跡 | NEC2024年9月4日閲覧、SX-3の項目に、引用「国産初の共有メモリ・マルチプロセッサによる並列処理や、」とある

## 11
SX-3シリーズ - コンピュータ博物館2024年9月4日閲覧

## 12
VPP500（1992年） : 富士通2024年9月4日閲覧

## 13
FUJITSU VPP500, VX/VPP300/VPP700シリーズ - コンピュータ博物館2024年9月4日閲覧
#3 14
日立評論1993年5月号:スーパーコンピュータシステムの動向2024年9月4日閲覧
## 15
HITAC S-3000シリーズ - コンピュータ博物館2024年9月4日閲覧（Descriptionメタタグに、日立：4台のマルチプロセッサ構成で32GFLOPSのベクトル演算性能を有する並列ベクトル型スーパーコンピュータS-3800/3600を発表、とある）
## 16
コンピュータグラフィックスシステムLINKS-1 - コンピュータ博物館2024年9月5日閲覧
## 17
並列画像生成システムLINKS - 2のアーキテクチャ（ http://id.nii.ac.jp/1001/00015340/ ）
## 18
つくる並列処理コンピュータ - 東京電機大学出版局2024年9月5日閲覧
## 19
486SXでも可かどうかはよくわからない。
## 20
デュアルソケット・ザ・ワールド　8086 Multiprocessing Features2024年9月5日閲覧
## 21
企画課：特別企画 第2回 PC-98シリーズと CPU：第 5世代 CPU編2024年9月5日閲覧
## 22
企画課：特別企画 第2回 PC-98シリーズと CPU：第 6世代 CPU2024年9月5日閲覧、Pentium II ODPの解説の最後を参照。
## 23
設計上は9コアが存在するが、うち1コアは歩留まり向上のための予備であり、出荷前に無効化されている。
## 24
Energy Aware Scheduling — The Linux Kernel documentation
## 25
ローカル・キャッシュを共有し合う機構とは、コアローカルなL2キャッシュとダイ共有のL3キャッシュの関係で、通常はスヌープしてローカルなL2キャッシュ間のコヒーレンシを確保する仕組みである。自分のコアのL2でmissして他のコアのL2にあれば、L3ではなく他のコアのL2をアクセスする仕組みを指す。コア数が増えるとダイ共有のL3では対応し切れなくなるためと推測される[独自研究?]。
## 26製品仕様 インテル® Xeon Phi™ プロセッサー

# arXiv
multi core, 5693
"multi core", 1110

Multi-core anti-resonant hollow core fibre
https://arxiv.org/pdf/2409.14555

Accelerating Image-based Pest Detection on a Heterogeneous Multi-core Microcontroller
https://arxiv.org/pdf/2408.15911

An Asynchronous Multi-core Accelerator for SNN inference
https://arxiv.org/pdf/2407.20947

High Spectral-Efficiency, Ultra-low MIMO SDM Transmission over a Field-Deployed Multi-Core OAM Fiber
https://arxiv.org/pdf/2407.01552

D&A: Resource Optimisation in Personalised PageRank Computations Using Multi-Core Machines
https://arxiv.org/pdf/2407.00068

Fast Switching Serial and Parallel Paradigms of SNN Inference on Multi-core Heterogeneous Neuromorphic Platform SpiNNaker2
https://arxiv.org/pdf/2406.17049

ONNXim: A Fast, Cycle-level Multi-core NPU Simulator
https://arxiv.org/pdf/2406.08051

A multi-core periphery perspective: Ranking via relative centrality
https://arxiv.org/pdf/2406.04487

Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures
https://arxiv.org/pdf/2405.16275

MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-core Processor
https://arxiv.org/pdf/2404.19180

Revisiting the Mapping of Quantum Circuits: Entering the Multi-Core Era
https://arxiv.org/pdf/2403.17205

Design-Space Exploration of SNN Models using Application-Specific Multi-Core Architectures
https://arxiv.org/pdf/2403.12061

Globalized distributionally robust optimization with multi core sets
https://arxiv.org/pdf/2403.08169

ARGO: An Auto-Tuning Runtime System for Scalable GNN Training on Multi-Core Processor
https://arxiv.org/pdf/2402.03671

Circuit Partitioning for Multi-Core Quantum Architectures with Deep Reinforcement Learning
https://arxiv.org/pdf/2401.17976

Modeling Online Paging in Multi-Core Systems
https://arxiv.org/pdf/2401.05834

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures
https://arxiv.org/pdf/2312.13000

Calibration-free quantitative phase imaging in multi-core fiber endoscopes using end-to-end deep learning
https://arxiv.org/pdf/2312.07102

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor
https://arxiv.org/pdf/2311.07493

CloverLeaf on Intel Multi-Core CPUs: A Case Study in Write-Allocate Evasion
https://arxiv.org/pdf/2311.04797

PT-symmetry enabled stable modes in multi-core fiber
https://arxiv.org/pdf/2310.08814

Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not?
https://arxiv.org/pdf/2310.02959

DYNAP-SE2: a scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor
https://arxiv.org/pdf/2310.00564

Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures
https://arxiv.org/pdf/2309.12182

Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU
https://arxiv.org/pdf/2309.09131

Interconnect Fabrics for Multi-Core Quantum Processors: A Context Analysis
https://arxiv.org/pdf/2309.07313

Mapping of CNNs on multi-core RRAM-based CIM architectures
https://arxiv.org/pdf/2309.03805

Algebraic Temporal Blocking for Sparse Iterative Solvers on Multi-Core CPUs
https://arxiv.org/pdf/2309.02228

Core interface optimization for multi-core neuromorphic processors
https://arxiv.org/pdf/2308.04171

PODTherm-GP: A Physics-based Data-Driven Approach for Effective Architecture-Level Thermal Simulation of Multi-Core CPUs
https://arxiv.org/pdf/2305.01911

HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package
https://arxiv.org/pdf/2305.00039

Performance Study of Partitioned Caches in Asymmetric Multi-Core Processors
https://arxiv.org/pdf/2304.05442