windowsでiverilog その147

# 概要　
windowsでiverilogやってみた。
verilog見つけたので、やってみた。

# 参考にしたページ

https://qiita.com/RotaryKer/items/d8f6d218962c213b0577

# サンプルコード

```

`default_nettype 	none
`define FIFO_D 		4
`timescale 			1ps/1ps

module FIFO(input wire clk, input wire n_rst, input wire [DATA_WIDTH - 1:0] din, input wire rd_en, input wire wr_en, output reg empty, output reg full, output reg [DATA_WIDTH - 1:0] dout);
	parameter DATA_WIDTH = 8;
	parameter FIFO_DEPTH = 4;
	reg [0:2**FIFO_DEPTH] rd_addr;
	reg [0:2**FIFO_DEPTH] wr_addr;
	reg [DATA_WIDTH - 1:0] data[0:2**FIFO_DEPTH - 1];
	always @(posedge clk)
	begin
		if (wr_en & !full)
			data[wr_addr] <= din;
		if (rd_en & !empty)
			dout <= data[rd_addr];
	end
	always @(posedge clk or posedge n_rst)
	begin
		if (n_rst)
		begin
			wr_addr <= 0;
		end
		else
		begin
			if (wr_en == 1'b1 & full == 1'b0)
			begin
				if (wr_addr == `FIFO_D'b1111)
				begin
					wr_addr <= 0;
				end
				else
				begin
					wr_addr <= wr_addr + 1'b1;
				end
			end
		end
	end
	always @(posedge clk or posedge n_rst)
	begin
		if (n_rst)
		begin
			rd_addr <= 0;
		end
		else
		begin
			if (rd_en)
			begin
				if (rd_addr == `FIFO_D'b1111)
				begin
					rd_addr <= 0;
				end
				else
				begin
					rd_addr <= rd_addr + 1'b1;
				end
			end
		end
	end
	always @(posedge clk or posedge n_rst)
	begin
		if (n_rst)
		begin
			full <= 0;
		end
		else
		begin
			if (wr_addr == `FIFO_D'b1111 & wr_en == 1 & rd_en == 0)
			begin
				full <= 1;
			end
			else
			if (full == 1 &rd_en == 1)
			begin
				full <= 0;
			end
		end
	end
	always @(posedge clk or posedge n_rst)
	begin
		if (n_rst)
		begin
			empty <= 1;
		end
		else
		begin
			if (wr_en)
			begin
				empty <= 0;
			end
		end
	end
endmodule

module FIFO_bench();
	parameter DATA_WIDTH = 8;
	parameter FIFO_DEPTH = 4;
	reg clk,
		n_rst,
		rd_en,
		wr_en;
	reg [DATA_WIDTH - 1:0] din;
	wire [DATA_WIDTH - 1:0] dout;
	FIFO #(.FIFO_DEPTH(FIFO_DEPTH)) u0(.clk(clk), .n_rst(n_rst), .rd_en(rd_en), .wr_en(wr_en), .din(din), .dout(dout));
	initial
	begin
		n_rst = 1;
		#10 n_rst = ~n_rst;
	end
	initial
	begin
		clk = 0;
		rd_en = 0;
		forever #10 clk = ~clk;
	end
	initial
	begin
		#10 wr_en = 1;
			din = 1;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 2;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 3;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 4;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 5;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 6;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 7;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 8;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 9;
		#10 wr_en = ~wr_en;
		#10 wr_en = 1;
			din = 10;
		#10 wr_en = ~wr_en;
		#10 rd_en = 1'b1;
		#10 rd_en = ~rd_en;
		#10 rd_en = 1'b1;
		#10 rd_en = ~rd_en;
		#10 rd_en = 1'b1;
		#10 rd_en = ~rd_en;
		#10 rd_en = 1'b1;
		#10 rd_en = ~rd_en;
		#10 rd_en = 1'b1;
		#10 rd_en = ~rd_en;
	end
	initial
	begin
		#500 $finish();
	end
	integer i;
 	initial
	begin
		$dumpfile("FIFO.vcd");
		$dumpvars(0, FIFO_bench);
		for(i = 0; i < 2 ** FIFO_DEPTH; i++)
			$dumpvars(1, u0.data[i]);
		$monitor ("%t: clk = %b r_data = %b", $time, clk,dout);
	end
endmodule



```

# 実行結果

```
>vvp a.out
VCD info: dumpfile FIFO.vcd opened for output.
VCD warning: array word FIFO_bench.u0.data[0] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[1] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[2] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[3] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[4] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[5] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[6] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[7] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[8] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[9] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[10] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[11] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[12] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[13] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[14] will conflict with an escaped identifier.
VCD warning: array word FIFO_bench.u0.data[15] will conflict with an escaped identifier.
                   0: clk = 0 r_data = xxxxxxxx
                  10: clk = 1 r_data = xxxxxxxx
                  20: clk = 0 r_data = xxxxxxxx
                  30: clk = 1 r_data = xxxxxxxx
                  40: clk = 0 r_data = xxxxxxxx
                  50: clk = 1 r_data = xxxxxxxx
                  60: clk = 0 r_data = xxxxxxxx
                  70: clk = 1 r_data = xxxxxxxx
                  80: clk = 0 r_data = xxxxxxxx
                  90: clk = 1 r_data = xxxxxxxx
                 100: clk = 0 r_data = xxxxxxxx
                 110: clk = 1 r_data = xxxxxxxx
                 120: clk = 0 r_data = xxxxxxxx
                 130: clk = 1 r_data = xxxxxxxx
                 140: clk = 0 r_data = xxxxxxxx
                 150: clk = 1 r_data = xxxxxxxx
                 160: clk = 0 r_data = xxxxxxxx
                 170: clk = 1 r_data = xxxxxxxx
                 180: clk = 0 r_data = xxxxxxxx
                 190: clk = 1 r_data = xxxxxxxx
                 200: clk = 0 r_data = xxxxxxxx
                 210: clk = 1 r_data = 00000001
                 220: clk = 0 r_data = 00000001
                 230: clk = 1 r_data = 00000010
                 240: clk = 0 r_data = 00000010
                 250: clk = 1 r_data = 00000011
                 260: clk = 0 r_data = 00000011
                 270: clk = 1 r_data = 00000100
                 280: clk = 0 r_data = 00000100
                 290: clk = 1 r_data = 00000101
                 300: clk = 0 r_data = 00000101
                 310: clk = 1 r_data = 00000101
                 320: clk = 0 r_data = 00000101
                 330: clk = 1 r_data = 00000101
                 340: clk = 0 r_data = 00000101
                 350: clk = 1 r_data = 00000101
                 360: clk = 0 r_data = 00000101
                 370: clk = 1 r_data = 00000101
                 380: clk = 0 r_data = 00000101
                 390: clk = 1 r_data = 00000101
                 400: clk = 0 r_data = 00000101
                 410: clk = 1 r_data = 00000101
                 420: clk = 0 r_data = 00000101
                 430: clk = 1 r_data = 00000101
                 440: clk = 0 r_data = 00000101
                 450: clk = 1 r_data = 00000101
                 460: clk = 0 r_data = 00000101
                 470: clk = 1 r_data = 00000101
                 480: clk = 0 r_data = 00000101
                 490: clk = 1 r_data = 00000101
fifo0.v:163: $finish called at 500 (1ps)
                 500: clk = 0 r_data = 00000101

```

# 写真

![image.png](https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/18104/ec2df2f0-3fb2-61ce-78ea-e03c34288891.png)

以上。