windowsでiverilog その149

# 概要　
windowsでiverilogやってみた。
verilog見つけたので、やってみた。

# 参考にしたページ

https://qiita.com/namikitakeo/items/4bb03f4bf007b65e4d61

# サンプルコード

```

`timescale 1ns/1ps

module prescaler #(parameter RATIO = 2) (input wire quick_clock, output reg slow_clock);
	reg [31:0] counter;

	wire [31:0] next_counter;
	wire inv;
	wire next_slow_clock;

	assign next_slow_clock = inv ? ~slow_clock : slow_clock;
	assign inv = (counter == (RATIO / 2 - 1));
	assign next_counter = inv ? 32'd0 : counter + 32'd1;

	always @(posedge quick_clock)
		counter <= next_counter;
	always @(posedge quick_clock)
		slow_clock <= next_slow_clock;
endmodule

module td4(input wire CLOCK,input wire RESET,input wire [3:0] IN,output reg [3:0] reg_out);
	reg [3:0] reg_a,
		reg_b;
	reg [3:0] pc = 4'b0;
	reg cflag = 1'b1;
	reg [7:0] rom[0:15];

	wire [7:0] opcode;
	wire [3:0] next_pc;
	wire [1:0] alu_sel, load_sel;
	wire jmp;
	wire [3:0] im; 
	// IMMEDIATE
	wire load_a, load_b, load_out, load_pc;
	wire [3:0] alu_in;
	wire [3:0] alu_out;
	wire nextcflag;

	assign alu_sel = (opcode[7:6] == 2'b11) ? 2'b11 : opcode[5:4];
	assign load_sel = opcode[7:6];
	assign jmp = opcode[4];
	assign im = opcode[3:0];
	assign alu_in = (alu_sel == 2'b00) ? reg_a : 
					// from A
					(alu_sel == 2'b01) ? reg_b : 
					// from B
					(alu_sel == 2'b10) ? IN : 
					// from input port
					4'b0000; 
					// zero
	assign {nextcflag, alu_out} = alu_in + im;
	assign alu_data = alu_out;
	assign opcode = rom[pc];
	assign op = opcode;
	assign load_a = (load_sel == 2'b00) ? 1'b0 : 1'b1; 
	// negative logic
	assign load_b = (load_sel == 2'b01) ? 1'b0 : 1'b1; 
	// negative logic
	assign load_out = (load_sel == 2'b10) ? 1'b0 : 1'b1; 
	// negative logic
	assign load_pc = (load_sel == 2'b11 && (jmp == 1'b1 || cflag)) ? 1'b0 : 1'b1; 
	// negative logic
	assign next_pc = (load_pc == 1'b0) ? alu_out : pc + 1;

	initial
	begin
		rom[0] = 8'b10110111; // OUT 0111	 # LED
		rom[1] = 8'b00000001; // ADD A,0001
		rom[2] = 8'b11100001; // JNC 0001	 # loop 16 times
		rom[3] = 8'b00000001; // ADD A,0001
		rom[4] = 8'b11100011; // JNC 0011	 # loop 16 times
		rom[5] = 8'b10110110; // OUT 0110	 # LED
		rom[6] = 8'b00000001; // ADD A,0001
		rom[7] = 8'b11100110; // JNC 0110	 # loop 16 times
		rom[8] = 8'b00000001; // ADD A,0001
		rom[9] = 8'b11101000; // JNC 1000	# loop 16 times
		rom[10] = 8'b10110000; // OUT 0000	 # LED
		rom[11] = 8'b10110100; // OUT 0100	 # LED
		rom[12] = 8'b00000001; // ADD A,0001
		rom[13] = 8'b11101010; // JNC 1010	 # loop 16 times
		rom[14] = 8'b10111000; // OUT 1000	 # LED
		rom[15] = 8'b11111111; // JMP 1111
	end
	always @(posedge CLOCK or negedge RESET)
	begin
		if (!RESET)
		begin
			reg_a <= 4'b0;
			reg_b <= 4'b0;
			reg_out <= 4'b0;
			cflag <= 1'b1;
			pc <= 4'b0;
		end
		else
		begin
			reg_a <= #1 (load_a == 1'b0) ? alu_out : reg_a;
			reg_b <= #1 (load_b == 1'b0) ? alu_out : reg_b;
			reg_out <= #1 (load_out == 1'b0) ? alu_out : reg_out;
			cflag <= #1 ~nextcflag; 
			// negative logic carry
			pc <= #1 next_pc;
		end
	end
endmodule

module top_td4(input CLOCK, input RESET, input [3:0] IN, output [3:0] OUT);
	wire td4_CLOCK;
	prescaler #(.RATIO(10_000_000)) prescaler(.quick_clock(CLOCK), .slow_clock(td4_CLOCK));
	td4 td4_0(td4_CLOCK, ~RESET, IN, OUT);
endmodule

module test_td4;
	reg clock = 1'b0;
	reg reset_n = 1'b0;
	reg [3:0] reg_in = 4'b0000;
	wire [3:0] pc_out;
	td4 td4_1(clock, reset_n, reg_in, pc_out);
	initial
	begin
		$dumpfile("test.vcd");
		$dumpvars(0, test_td4);
		$monitor("%t: in_port = %h, out_port = %h", $time, reg_in, pc_out);
	end
	initial
	begin
		clock = 1'b0;
		forever begin
			#1 clock = ~clock;
		end
	end
	initial
	begin
		reset_n = 1'b0;
		#1 reset_n = 1'b1;
		#10000 $finish;
	end
endmodule



```

# 実行結果

```
>vvp a.out
VCD info: dumpfile test.vcd opened for output.
                   0: in_port = 0, out_port = 0
                2000: in_port = 0, out_port = 7
              132000: in_port = 0, out_port = 6
              262000: in_port = 0, out_port = 0
              264000: in_port = 0, out_port = 4
              270000: in_port = 0, out_port = 0
              272000: in_port = 0, out_port = 4
              278000: in_port = 0, out_port = 0
              280000: in_port = 0, out_port = 4
              286000: in_port = 0, out_port = 0
              288000: in_port = 0, out_port = 4
              294000: in_port = 0, out_port = 0
              296000: in_port = 0, out_port = 4
              302000: in_port = 0, out_port = 0
              304000: in_port = 0, out_port = 4
              310000: in_port = 0, out_port = 0
              312000: in_port = 0, out_port = 4
              318000: in_port = 0, out_port = 0
              320000: in_port = 0, out_port = 4
              326000: in_port = 0, out_port = 0
              328000: in_port = 0, out_port = 4
              334000: in_port = 0, out_port = 0
              336000: in_port = 0, out_port = 4
              342000: in_port = 0, out_port = 0
              344000: in_port = 0, out_port = 4
              350000: in_port = 0, out_port = 0
              352000: in_port = 0, out_port = 4
              358000: in_port = 0, out_port = 0
              360000: in_port = 0, out_port = 4
              366000: in_port = 0, out_port = 0
              368000: in_port = 0, out_port = 4
              374000: in_port = 0, out_port = 0
              376000: in_port = 0, out_port = 4
              382000: in_port = 0, out_port = 0
              384000: in_port = 0, out_port = 4
              390000: in_port = 0, out_port = 8
td4.v:136: $finish called at 10001000 (1ps)

```

# 写真

![image.png](https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/18104/579b237c-abbd-81ed-40ea-af366f75d280.png)


以上。