paiza.ioでelixir その118

# 概要
paiza.ioでelixirやってみた。
FPGAの高位合成書いてみた。
ニューラルネットワークのxor判定器をコンパイルしてみた。

# 参考にしたページ

https://github.com/Archfx/XOR-FPGA


# 高位合成て何
FPGAを記述する、HDL言語を生成するコンパイラ
下のコードから下の下のコードを生成する。

```
w100 = 47
w101 = -61
w110 = -35
w111 = -46
w120 = 55
w121 = -37
w20 = 75
w21 = -44
w22 = -66
b10 = -23
b11 = 7
b12 = 13
b2 = 33
```

```
module sigmoid(input [7:0] in, output reg [7:0] out);
	always @ *
	begin
	case (in)
	-8'sd 127: out<= 8'sd 0;
	-8'sd 126: out<= 8'sd 0;
	-8'sd 125: out<= 8'sd 0;
	-8'sd 124: out<= 8'sd 0;
	-8'sd 123: out<= 8'sd 0;
	-8'sd 122: out<= 8'sd 0;
	-8'sd 121: out<= 8'sd 0;
	-8'sd 120: out<= 8'sd 0;
	-8'sd 119: out<= 8'sd 0;
	-8'sd 118: out<= 8'sd 0;
	-8'sd 117: out<= 8'sd 0;
	-8'sd 116: out<= 8'sd 0;
	-8'sd 115: out<= 8'sd 0;
	-8'sd 114: out<= 8'sd 0;
	-8'sd 113: out<= 8'sd 0;
	-8'sd 112: out<= 8'sd 0;
	-8'sd 111: out<= 8'sd 0;
	-8'sd 110: out<= 8'sd 0;
	-8'sd 109: out<= 8'sd 0;
	-8'sd 108: out<= 8'sd 0;
	-8'sd 107: out<= 8'sd 0;
	-8'sd 106: out<= 8'sd 0;
	-8'sd 105: out<= 8'sd 0;
	-8'sd 104: out<= 8'sd 0;
	-8'sd 103: out<= 8'sd 0;
	-8'sd 102: out<= 8'sd 0;
	-8'sd 101: out<= 8'sd 0;
	-8'sd 100: out<= 8'sd 0;
	-8'sd 99: out<= 8'sd 0;
	-8'sd 98: out<= 8'sd 0;
	-8'sd 97: out<= 8'sd 0;
	-8'sd 96: out<= 8'sd 0;
	-8'sd 95: out<= 8'sd 0;
	-8'sd 94: out<= 8'sd 0;
	-8'sd 93: out<= 8'sd 0;
	-8'sd 92: out<= 8'sd 0;
	-8'sd 91: out<= 8'sd 0;
	-8'sd 90: out<= 8'sd 0;
	-8'sd 89: out<= 8'sd 0;
	-8'sd 88: out<= 8'sd 0;
	-8'sd 87: out<= 8'sd 0;
	-8'sd 86: out<= 8'sd 0;
	-8'sd 85: out<= 8'sd 0;
	-8'sd 84: out<= 8'sd 0;
	-8'sd 83: out<= 8'sd 0;
	-8'sd 82: out<= 8'sd 0;
	-8'sd 81: out<= 8'sd 0;
	-8'sd 80: out<= 8'sd 0;
	-8'sd 79: out<= 8'sd 0;
	-8'sd 78: out<= 8'sd 0;
	-8'sd 77: out<= 8'sd 0;
	-8'sd 76: out<= 8'sd 0;
	-8'sd 75: out<= 8'sd 0;
	-8'sd 74: out<= 8'sd 0;
	-8'sd 73: out<= 8'sd 0;
	-8'sd 72: out<= 8'sd 0;
	-8'sd 71: out<= 8'sd 0;
	-8'sd 70: out<= 8'sd 0;
	-8'sd 69: out<= 8'sd 0;
	-8'sd 68: out<= 8'sd 0;
	-8'sd 67: out<= 8'sd 0;
	-8'sd 66: out<= 8'sd 0;
	-8'sd 65: out<= 8'sd 0;
	-8'sd 64: out<= 8'sd 0;
	-8'sd 63: out<= 8'sd 0;
	-8'sd 62: out<= 8'sd 0;
	-8'sd 61: out<= 8'sd 0;
	-8'sd 60: out<= 8'sd 0;
	-8'sd 59: out<= 8'sd 0;
	-8'sd 58: out<= 8'sd 0;
	-8'sd 57: out<= 8'sd 0;
	-8'sd 56: out<= 8'sd 0;
	-8'sd 55: out<= 8'sd 0;
	-8'sd 54: out<= 8'sd 0;
	-8'sd 53: out<= 8'sd 0;
	-8'sd 52: out<= 8'sd 0;
	-8'sd 51: out<= 8'sd 0;
	-8'sd 50: out<= 8'sd 0;
	-8'sd 49: out<= 8'sd 0;
	-8'sd 48: out<= 8'sd 0;
	-8'sd 47: out<= 8'sd 0;
	-8'sd 46: out<= 8'sd 0;
	-8'sd 45: out<= 8'sd 1;
	-8'sd 44: out<= 8'sd 1;
	-8'sd 43: out<= 8'sd 1;
	-8'sd 42: out<= 8'sd 1;
	-8'sd 41: out<= 8'sd 1;
	-8'sd 40: out<= 8'sd 1;
	-8'sd 39: out<= 8'sd 1;
	-8'sd 38: out<= 8'sd 2;
	-8'sd 37: out<= 8'sd 2;
	-8'sd 36: out<= 8'sd 2;
	-8'sd 35: out<= 8'sd 2;
	-8'sd 34: out<= 8'sd 3;
	-8'sd 33: out<= 8'sd 3;
	-8'sd 32: out<= 8'sd 3;
	-8'sd 31: out<= 8'sd 4;
	-8'sd 30: out<= 8'sd 4;
	-8'sd 29: out<= 8'sd 5;
	-8'sd 28: out<= 8'sd 5;
	-8'sd 27: out<= 8'sd 6;
	-8'sd 26: out<= 8'sd 6;
	-8'sd 25: out<= 8'sd 7;
	-8'sd 24: out<= 8'sd 8;
	-8'sd 23: out<= 8'sd 9;
	-8'sd 22: out<= 8'sd 9;
	-8'sd 21: out<= 8'sd 10;
	-8'sd 20: out<= 8'sd 11;
	-8'sd 19: out<= 8'sd 13;
	-8'sd 18: out<= 8'sd 14;
	-8'sd 17: out<= 8'sd 15;
	-8'sd 16: out<= 8'sd 16;
	-8'sd 15: out<= 8'sd 18;
	-8'sd 14: out<= 8'sd 19;
	-8'sd 13: out<= 8'sd 21;
	-8'sd 12: out<= 8'sd 23;
	-8'sd 11: out<= 8'sd 24;
	-8'sd 10: out<= 8'sd 26;
	-8'sd 9: out<= 8'sd 28;
	-8'sd 8: out<= 8'sd 31;
	-8'sd 7: out<= 8'sd 33;
	-8'sd 6: out<= 8'sd 35;
	-8'sd 5: out<= 8'sd 37;
	-8'sd 4: out<= 8'sd 40;
	-8'sd 3: out<= 8'sd 42;
	-8'sd 2: out<= 8'sd 45;
	-8'sd 1: out<= 8'sd 47;
	8'sd 0: out<= 8'sd 50;
	8'sd 1: out<= 8'sd 52;
	8'sd 2: out<= 8'sd 54;
	8'sd 3: out<= 8'sd 57;
	8'sd 4: out<= 8'sd 59;
	8'sd 5: out<= 8'sd 62;
	8'sd 6: out<= 8'sd 64;
	8'sd 7: out<= 8'sd 66;
	8'sd 8: out<= 8'sd 68;
	8'sd 9: out<= 8'sd 71;
	8'sd 10: out<= 8'sd 73;
	8'sd 11: out<= 8'sd 75;
	8'sd 12: out<= 8'sd 76;
	8'sd 13: out<= 8'sd 78;
	8'sd 14: out<= 8'sd 80;
	8'sd 15: out<= 8'sd 81;
	8'sd 16: out<= 8'sd 83;
	8'sd 17: out<= 8'sd 84;
	8'sd 18: out<= 8'sd 85;
	8'sd 19: out<= 8'sd 86;
	8'sd 20: out<= 8'sd 88;
	8'sd 21: out<= 8'sd 89;
	8'sd 22: out<= 8'sd 90;
	8'sd 23: out<= 8'sd 90;
	8'sd 24: out<= 8'sd 91;
	8'sd 25: out<= 8'sd 92;
	8'sd 26: out<= 8'sd 93;
	8'sd 27: out<= 8'sd 93;
	8'sd 28: out<= 8'sd 94;
	8'sd 29: out<= 8'sd 94;
	8'sd 30: out<= 8'sd 95;
	8'sd 31: out<= 8'sd 95;
	8'sd 32: out<= 8'sd 96;
	8'sd 33: out<= 8'sd 96;
	8'sd 34: out<= 8'sd 96;
	8'sd 35: out<= 8'sd 97;
	8'sd 36: out<= 8'sd 97;
	8'sd 37: out<= 8'sd 97;
	8'sd 38: out<= 8'sd 97;
	8'sd 39: out<= 8'sd 98;
	8'sd 40: out<= 8'sd 98;
	8'sd 41: out<= 8'sd 98;
	8'sd 42: out<= 8'sd 98;
	8'sd 43: out<= 8'sd 98;
	8'sd 44: out<= 8'sd 98;
	8'sd 45: out<= 8'sd 98;
	8'sd 46: out<= 8'sd 99;
	8'sd 47: out<= 8'sd 99;
	8'sd 48: out<= 8'sd 99;
	8'sd 49: out<= 8'sd 99;
	8'sd 50: out<= 8'sd 99;
	8'sd 51: out<= 8'sd 99;
	8'sd 52: out<= 8'sd 99;
	8'sd 53: out<= 8'sd 99;
	8'sd 54: out<= 8'sd 99;
	8'sd 55: out<= 8'sd 99;
	8'sd 56: out<= 8'sd 99;
	8'sd 57: out<= 8'sd 99;
	8'sd 58: out<= 8'sd 99;
	8'sd 59: out<= 8'sd 99;
	8'sd 60: out<= 8'sd 99;
	8'sd 61: out<= 8'sd 99;
	8'sd 62: out<= 8'sd 99;
	8'sd 63: out<= 8'sd 99;
	8'sd 64: out<= 8'sd 99;
	8'sd 65: out<= 8'sd 99;
	8'sd 66: out<= 8'sd 99;
	8'sd 67: out<= 8'sd 99;
	8'sd 68: out<= 8'sd 99;
	8'sd 69: out<= 8'sd 99;
	8'sd 70: out<= 8'sd 99;
	8'sd 71: out<= 8'sd 99;
	8'sd 72: out<= 8'sd 99;
	8'sd 73: out<= 8'sd 99;
	8'sd 74: out<= 8'sd 99;
	8'sd 75: out<= 8'sd 99;
	8'sd 76: out<= 8'sd 99;
	8'sd 77: out<= 8'sd 99;
	8'sd 78: out<= 8'sd 99;
	8'sd 79: out<= 8'sd 99;
	8'sd 80: out<= 8'sd 99;
	8'sd 81: out<= 8'sd 99;
	8'sd 82: out<= 8'sd 99;
	8'sd 83: out<= 8'sd 99;
	8'sd 84: out<= 8'sd 99;
	8'sd 85: out<= 8'sd 99;
	8'sd 86: out<= 8'sd 99;
	8'sd 87: out<= 8'sd 99;
	8'sd 88: out<= 8'sd 99;
	8'sd 89: out<= 8'sd 99;
	8'sd 90: out<= 8'sd 99;
	8'sd 91: out<= 8'sd 99;
	8'sd 92: out<= 8'sd 99;
	8'sd 93: out<= 8'sd 99;
	8'sd 94: out<= 8'sd 99;
	8'sd 95: out<= 8'sd 99;
	8'sd 96: out<= 8'sd 99;
	8'sd 97: out<= 8'sd 99;
	8'sd 98: out<= 8'sd 99;
	8'sd 99: out<= 8'sd 99;
	8'sd 100: out<= 8'sd 99;
	8'sd 101: out<= 8'sd 99;
	8'sd 102: out<= 8'sd 99;
	8'sd 103: out<= 8'sd 99;
	8'sd 104: out<= 8'sd 99;
	8'sd 105: out<= 8'sd 99;
	8'sd 106: out<= 8'sd 99;
	8'sd 107: out<= 8'sd 99;
	8'sd 108: out<= 8'sd 99;
	8'sd 109: out<= 8'sd 99;
	8'sd 110: out<= 8'sd 99;
	8'sd 111: out<= 8'sd 99;
	8'sd 112: out<= 8'sd 99;
	8'sd 113: out<= 8'sd 99;
	8'sd 114: out<= 8'sd 99;
	8'sd 115: out<= 8'sd 99;
	8'sd 116: out<= 8'sd 99;
	8'sd 117: out<= 8'sd 99;
	8'sd 118: out<= 8'sd 99;
	8'sd 119: out<= 8'sd 99;
	8'sd 120: out<= 8'sd 99;
	8'sd 121: out<= 8'sd 99;
	8'sd 122: out<= 8'sd 99;
	8'sd 123: out<= 8'sd 99;
	8'sd 124: out<= 8'sd 99;
	8'sd 125: out<= 8'sd 99;
	8'sd 126: out<= 8'sd 99;
	8'sd 127: out<= 8'sd 99;
	endcase
	end
endmodule

module XOR_NN(input [1:0] x, input predict, input clock, output reg signed [7:0] a3);
	reg [7:0] X [0:3][0:1];
	reg y [0:3];
	reg signed [7:0] x_0;
	reg signed [7:0] x_1;
	reg signed [7:0] W1 [0:2][0:1];
	reg signed [7:0] W2 [0:2];
	reg signed [7:0] B1 [0:2];
	reg signed [7:0] B2;
	reg signed [7:0] z2 [0:2];
	reg signed [7:0] z3 = 8'd0;
	reg signed [16:0] z3_temp_1;
	reg signed [16:0] z3_temp_2;
	reg signed [7:0] a2 [0:2];
	reg en_Hidden;
	reg en_Hidden_sigmoid;
	reg en_Output;
	reg en_Output_sigmoid;
	reg en_Display;
	reg [7:0] pc;
	wire [7:0] z2_0;
	wire [7:0] z2_1;
	wire [7:0] z2_2;
	wire [7:0] a2_0;
	wire [7:0] a2_1;
	wire [7:0] a2_2;
	wire [7:0] z3_wire;
	wire [7:0] a3_wire;
	assign z2_0 = z2[0];
	assign z2_1 = z2[1];
	assign z2_2 = z2[2];
	assign z3_wire = z3;
	sigmoid Hidden_0(.in(z2_0), .out(a2_0));
	sigmoid Hidden_1(.in(z2_1), .out(a2_1));
	sigmoid Hidden_2(.in(z2_2), .out(a2_2));
	sigmoid Output(.in(z3_wire), .out(a3_wire));
	initial
	begin
		x_0 = 8'd0;
		x_1 = 8'd0;
		X[0][0] = 8'sd0;
		X[0][1] = 8'sd1;
		X[1][0] = 8'sd1;
		X[1][1] = 8'sd0;
		X[2][0] = 8'sd0;
		X[2][1] = 8'sd0;
		X[3][0] = 8'sd1;
		X[3][1] = 8'sd1;
		y[0] = 1;
		y[1] = 1;
		y[2] = 0;
		y[3] = 0;

                W1[0][0] = 47;
                W1[0][1] = -61;
                W1[1][0] = -35;
                W1[1][1] = -46;
                W1[2][0] = 55;
                W1[2][1] = -37;
                W2[0] = 75;
                W2[1] = -44;
                W2[2] = -66;
                B1[0] = -23;
                B1[1] = 7;
                B1[2] = 13;
                B2 = 33;

	end
	always @ *
	begin
		x_0[0:0] = x[0:0];
		x_1[0:0] = x[1:1];
	end
	always @ (posedge clock, posedge predict)
	begin
		if (predict)
		begin
			en_Hidden = 1;
			en_Output = 0;
			en_Hidden_sigmoid = 0;
			en_Output_sigmoid = 0;
			en_Display = 0;
			$display("x %b", x);
			pc <= 10;
		end
		else
		begin
			case(pc)
			10:
			begin
				z2[0] <= (W1[0][0] * x_0) + (W1[0][1] * x_1) + (B1[0]);
				z2[1] <= (W1[1][0] * x_0) + (W1[1][1] * x_1) + (B1[1]);
				z2[2] <= (W1[2][0] * x_0) + (W1[2][1] * x_1) + (B1[2]);
				en_Hidden_sigmoid <= 1;
				en_Hidden <= 0;
				pc <= 20;
			end
			20:
			begin
				a2[0][7:0] <= a2_0;
				a2[1][7:0] <= a2_1;
				a2[2][7:0] <= a2_2;
				en_Output <= 1;
				en_Hidden_sigmoid <= 0;
				$display("z20 %d", z2_0);
				$display("z21 %d", z2_1);
				$display("z22 %d", z2_2);
				pc <= 30;
			end
			30:
			begin
				z3 <= (W2[0] * a2[0] / 17'sd128) + (W2[1] * a2[1] / 17'sd128) + (W2[2] * a2[2] / 17'sd128) + B2;
				en_Output <= 0;
				en_Output_sigmoid <= 1;
				$display("a2_0 %d", a2[0]);
				$display("a2_1 %d", a2[1]);
				$display("a2_2 %d", a2[2]);
				pc <= 40;
			end
			40:
			begin
				a3 <= a3_wire;
				$display("z3 %d", z3);
				en_Output_sigmoid = 0;
				en_Display = 1;
				pc <= 50;
			end
			50:
			begin
				en_Display = 0;
				$display("Final prediction percentage for 1: %d", a3_wire);
				pc <= 60;
			end
			60:
			begin
				pc <= 60;
			end
			endcase
		end
	end
endmodule

module test;
	reg [1:0] x;
	reg clock;
	reg predict;
	wire [7:0] a3;
	XOR_NN uut(.x(x), .predict(predict), .clock(clock), .a3(a3));
	initial
	begin
		x = 2'b00;
		clock = 0;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		x = 2'b01;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		x = 2'b10;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		x = 2'b11;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		$finish;
	end
	initial
	begin
		forever
		begin
			#5 clock = ~clock;
		end
	end
endmodule

```

# シミュレーション結果

```
>vvp a.out
x 00
x 00
z20 233
z21   7
z22  13
a2_0   9
a2_1  66
a2_2  78
z3  -24
Final prediction percentage for 1:   8
x 01
x 01
z20  24
z21 228
z22  68
a2_0  91
a2_1   5
a2_2  99
z3   34
Final prediction percentage for 1:  96
x 10
x 10
z20 172
z21 217
z22 232
a2_0   0
a2_1   1
a2_2   8
z3   29
Final prediction percentage for 1:  94
x 11
x 11
z20 219
z21 182
z22  31
a2_0   2
a2_1   0
a2_2  95
z3  -14
Final prediction percentage for 1:  19


```

# サンプルコード

```

defmodule Main do
	def run(str) do
	    IO.puts """
module sigmoid(input [7:0] in, output reg [7:0] out);
	always @ *
	begin
	case (in)
	-8'sd 127: out<= 8'sd 0;
	-8'sd 126: out<= 8'sd 0;
	-8'sd 125: out<= 8'sd 0;
	-8'sd 124: out<= 8'sd 0;
	-8'sd 123: out<= 8'sd 0;
	-8'sd 122: out<= 8'sd 0;
	-8'sd 121: out<= 8'sd 0;
	-8'sd 120: out<= 8'sd 0;
	-8'sd 119: out<= 8'sd 0;
	-8'sd 118: out<= 8'sd 0;
	-8'sd 117: out<= 8'sd 0;
	-8'sd 116: out<= 8'sd 0;
	-8'sd 115: out<= 8'sd 0;
	-8'sd 114: out<= 8'sd 0;
	-8'sd 113: out<= 8'sd 0;
	-8'sd 112: out<= 8'sd 0;
	-8'sd 111: out<= 8'sd 0;
	-8'sd 110: out<= 8'sd 0;
	-8'sd 109: out<= 8'sd 0;
	-8'sd 108: out<= 8'sd 0;
	-8'sd 107: out<= 8'sd 0;
	-8'sd 106: out<= 8'sd 0;
	-8'sd 105: out<= 8'sd 0;
	-8'sd 104: out<= 8'sd 0;
	-8'sd 103: out<= 8'sd 0;
	-8'sd 102: out<= 8'sd 0;
	-8'sd 101: out<= 8'sd 0;
	-8'sd 100: out<= 8'sd 0;
	-8'sd 99: out<= 8'sd 0;
	-8'sd 98: out<= 8'sd 0;
	-8'sd 97: out<= 8'sd 0;
	-8'sd 96: out<= 8'sd 0;
	-8'sd 95: out<= 8'sd 0;
	-8'sd 94: out<= 8'sd 0;
	-8'sd 93: out<= 8'sd 0;
	-8'sd 92: out<= 8'sd 0;
	-8'sd 91: out<= 8'sd 0;
	-8'sd 90: out<= 8'sd 0;
	-8'sd 89: out<= 8'sd 0;
	-8'sd 88: out<= 8'sd 0;
	-8'sd 87: out<= 8'sd 0;
	-8'sd 86: out<= 8'sd 0;
	-8'sd 85: out<= 8'sd 0;
	-8'sd 84: out<= 8'sd 0;
	-8'sd 83: out<= 8'sd 0;
	-8'sd 82: out<= 8'sd 0;
	-8'sd 81: out<= 8'sd 0;
	-8'sd 80: out<= 8'sd 0;
	-8'sd 79: out<= 8'sd 0;
	-8'sd 78: out<= 8'sd 0;
	-8'sd 77: out<= 8'sd 0;
	-8'sd 76: out<= 8'sd 0;
	-8'sd 75: out<= 8'sd 0;
	-8'sd 74: out<= 8'sd 0;
	-8'sd 73: out<= 8'sd 0;
	-8'sd 72: out<= 8'sd 0;
	-8'sd 71: out<= 8'sd 0;
	-8'sd 70: out<= 8'sd 0;
	-8'sd 69: out<= 8'sd 0;
	-8'sd 68: out<= 8'sd 0;
	-8'sd 67: out<= 8'sd 0;
	-8'sd 66: out<= 8'sd 0;
	-8'sd 65: out<= 8'sd 0;
	-8'sd 64: out<= 8'sd 0;
	-8'sd 63: out<= 8'sd 0;
	-8'sd 62: out<= 8'sd 0;
	-8'sd 61: out<= 8'sd 0;
	-8'sd 60: out<= 8'sd 0;
	-8'sd 59: out<= 8'sd 0;
	-8'sd 58: out<= 8'sd 0;
	-8'sd 57: out<= 8'sd 0;
	-8'sd 56: out<= 8'sd 0;
	-8'sd 55: out<= 8'sd 0;
	-8'sd 54: out<= 8'sd 0;
	-8'sd 53: out<= 8'sd 0;
	-8'sd 52: out<= 8'sd 0;
	-8'sd 51: out<= 8'sd 0;
	-8'sd 50: out<= 8'sd 0;
	-8'sd 49: out<= 8'sd 0;
	-8'sd 48: out<= 8'sd 0;
	-8'sd 47: out<= 8'sd 0;
	-8'sd 46: out<= 8'sd 0;
	-8'sd 45: out<= 8'sd 1;
	-8'sd 44: out<= 8'sd 1;
	-8'sd 43: out<= 8'sd 1;
	-8'sd 42: out<= 8'sd 1;
	-8'sd 41: out<= 8'sd 1;
	-8'sd 40: out<= 8'sd 1;
	-8'sd 39: out<= 8'sd 1;
	-8'sd 38: out<= 8'sd 2;
	-8'sd 37: out<= 8'sd 2;
	-8'sd 36: out<= 8'sd 2;
	-8'sd 35: out<= 8'sd 2;
	-8'sd 34: out<= 8'sd 3;
	-8'sd 33: out<= 8'sd 3;
	-8'sd 32: out<= 8'sd 3;
	-8'sd 31: out<= 8'sd 4;
	-8'sd 30: out<= 8'sd 4;
	-8'sd 29: out<= 8'sd 5;
	-8'sd 28: out<= 8'sd 5;
	-8'sd 27: out<= 8'sd 6;
	-8'sd 26: out<= 8'sd 6;
	-8'sd 25: out<= 8'sd 7;
	-8'sd 24: out<= 8'sd 8;
	-8'sd 23: out<= 8'sd 9;
	-8'sd 22: out<= 8'sd 9;
	-8'sd 21: out<= 8'sd 10;
	-8'sd 20: out<= 8'sd 11;
	-8'sd 19: out<= 8'sd 13;
	-8'sd 18: out<= 8'sd 14;
	-8'sd 17: out<= 8'sd 15;
	-8'sd 16: out<= 8'sd 16;
	-8'sd 15: out<= 8'sd 18;
	-8'sd 14: out<= 8'sd 19;
	-8'sd 13: out<= 8'sd 21;
	-8'sd 12: out<= 8'sd 23;
	-8'sd 11: out<= 8'sd 24;
	-8'sd 10: out<= 8'sd 26;
	-8'sd 9: out<= 8'sd 28;
	-8'sd 8: out<= 8'sd 31;
	-8'sd 7: out<= 8'sd 33;
	-8'sd 6: out<= 8'sd 35;
	-8'sd 5: out<= 8'sd 37;
	-8'sd 4: out<= 8'sd 40;
	-8'sd 3: out<= 8'sd 42;
	-8'sd 2: out<= 8'sd 45;
	-8'sd 1: out<= 8'sd 47;
	8'sd 0: out<= 8'sd 50;
	8'sd 1: out<= 8'sd 52;
	8'sd 2: out<= 8'sd 54;
	8'sd 3: out<= 8'sd 57;
	8'sd 4: out<= 8'sd 59;
	8'sd 5: out<= 8'sd 62;
	8'sd 6: out<= 8'sd 64;
	8'sd 7: out<= 8'sd 66;
	8'sd 8: out<= 8'sd 68;
	8'sd 9: out<= 8'sd 71;
	8'sd 10: out<= 8'sd 73;
	8'sd 11: out<= 8'sd 75;
	8'sd 12: out<= 8'sd 76;
	8'sd 13: out<= 8'sd 78;
	8'sd 14: out<= 8'sd 80;
	8'sd 15: out<= 8'sd 81;
	8'sd 16: out<= 8'sd 83;
	8'sd 17: out<= 8'sd 84;
	8'sd 18: out<= 8'sd 85;
	8'sd 19: out<= 8'sd 86;
	8'sd 20: out<= 8'sd 88;
	8'sd 21: out<= 8'sd 89;
	8'sd 22: out<= 8'sd 90;
	8'sd 23: out<= 8'sd 90;
	8'sd 24: out<= 8'sd 91;
	8'sd 25: out<= 8'sd 92;
	8'sd 26: out<= 8'sd 93;
	8'sd 27: out<= 8'sd 93;
	8'sd 28: out<= 8'sd 94;
	8'sd 29: out<= 8'sd 94;
	8'sd 30: out<= 8'sd 95;
	8'sd 31: out<= 8'sd 95;
	8'sd 32: out<= 8'sd 96;
	8'sd 33: out<= 8'sd 96;
	8'sd 34: out<= 8'sd 96;
	8'sd 35: out<= 8'sd 97;
	8'sd 36: out<= 8'sd 97;
	8'sd 37: out<= 8'sd 97;
	8'sd 38: out<= 8'sd 97;
	8'sd 39: out<= 8'sd 98;
	8'sd 40: out<= 8'sd 98;
	8'sd 41: out<= 8'sd 98;
	8'sd 42: out<= 8'sd 98;
	8'sd 43: out<= 8'sd 98;
	8'sd 44: out<= 8'sd 98;
	8'sd 45: out<= 8'sd 98;
	8'sd 46: out<= 8'sd 99;
	8'sd 47: out<= 8'sd 99;
	8'sd 48: out<= 8'sd 99;
	8'sd 49: out<= 8'sd 99;
	8'sd 50: out<= 8'sd 99;
	8'sd 51: out<= 8'sd 99;
	8'sd 52: out<= 8'sd 99;
	8'sd 53: out<= 8'sd 99;
	8'sd 54: out<= 8'sd 99;
	8'sd 55: out<= 8'sd 99;
	8'sd 56: out<= 8'sd 99;
	8'sd 57: out<= 8'sd 99;
	8'sd 58: out<= 8'sd 99;
	8'sd 59: out<= 8'sd 99;
	8'sd 60: out<= 8'sd 99;
	8'sd 61: out<= 8'sd 99;
	8'sd 62: out<= 8'sd 99;
	8'sd 63: out<= 8'sd 99;
	8'sd 64: out<= 8'sd 99;
	8'sd 65: out<= 8'sd 99;
	8'sd 66: out<= 8'sd 99;
	8'sd 67: out<= 8'sd 99;
	8'sd 68: out<= 8'sd 99;
	8'sd 69: out<= 8'sd 99;
	8'sd 70: out<= 8'sd 99;
	8'sd 71: out<= 8'sd 99;
	8'sd 72: out<= 8'sd 99;
	8'sd 73: out<= 8'sd 99;
	8'sd 74: out<= 8'sd 99;
	8'sd 75: out<= 8'sd 99;
	8'sd 76: out<= 8'sd 99;
	8'sd 77: out<= 8'sd 99;
	8'sd 78: out<= 8'sd 99;
	8'sd 79: out<= 8'sd 99;
	8'sd 80: out<= 8'sd 99;
	8'sd 81: out<= 8'sd 99;
	8'sd 82: out<= 8'sd 99;
	8'sd 83: out<= 8'sd 99;
	8'sd 84: out<= 8'sd 99;
	8'sd 85: out<= 8'sd 99;
	8'sd 86: out<= 8'sd 99;
	8'sd 87: out<= 8'sd 99;
	8'sd 88: out<= 8'sd 99;
	8'sd 89: out<= 8'sd 99;
	8'sd 90: out<= 8'sd 99;
	8'sd 91: out<= 8'sd 99;
	8'sd 92: out<= 8'sd 99;
	8'sd 93: out<= 8'sd 99;
	8'sd 94: out<= 8'sd 99;
	8'sd 95: out<= 8'sd 99;
	8'sd 96: out<= 8'sd 99;
	8'sd 97: out<= 8'sd 99;
	8'sd 98: out<= 8'sd 99;
	8'sd 99: out<= 8'sd 99;
	8'sd 100: out<= 8'sd 99;
	8'sd 101: out<= 8'sd 99;
	8'sd 102: out<= 8'sd 99;
	8'sd 103: out<= 8'sd 99;
	8'sd 104: out<= 8'sd 99;
	8'sd 105: out<= 8'sd 99;
	8'sd 106: out<= 8'sd 99;
	8'sd 107: out<= 8'sd 99;
	8'sd 108: out<= 8'sd 99;
	8'sd 109: out<= 8'sd 99;
	8'sd 110: out<= 8'sd 99;
	8'sd 111: out<= 8'sd 99;
	8'sd 112: out<= 8'sd 99;
	8'sd 113: out<= 8'sd 99;
	8'sd 114: out<= 8'sd 99;
	8'sd 115: out<= 8'sd 99;
	8'sd 116: out<= 8'sd 99;
	8'sd 117: out<= 8'sd 99;
	8'sd 118: out<= 8'sd 99;
	8'sd 119: out<= 8'sd 99;
	8'sd 120: out<= 8'sd 99;
	8'sd 121: out<= 8'sd 99;
	8'sd 122: out<= 8'sd 99;
	8'sd 123: out<= 8'sd 99;
	8'sd 124: out<= 8'sd 99;
	8'sd 125: out<= 8'sd 99;
	8'sd 126: out<= 8'sd 99;
	8'sd 127: out<= 8'sd 99;
	endcase
	end
endmodule

module XOR_NN(input [1:0] x, input predict, input clock, output reg signed [7:0] a3);
	reg [7:0] X [0:3][0:1];
	reg y [0:3];
	reg signed [7:0] x_0;
	reg signed [7:0] x_1;
	reg signed [7:0] W1 [0:2][0:1];
	reg signed [7:0] W2 [0:2];
	reg signed [7:0] B1 [0:2];
	reg signed [7:0] B2;
	reg signed [7:0] z2 [0:2];
	reg signed [7:0] z3 = 8'd0;
	reg signed [16:0] z3_temp_1;
	reg signed [16:0] z3_temp_2;
	reg signed [7:0] a2 [0:2];
	reg en_Hidden;
	reg en_Hidden_sigmoid;
	reg en_Output;
	reg en_Output_sigmoid;
	reg en_Display;
	reg [7:0] pc;
	wire [7:0] z2_0;
	wire [7:0] z2_1;
	wire [7:0] z2_2;
	wire [7:0] a2_0;
	wire [7:0] a2_1;
	wire [7:0] a2_2;
	wire [7:0] z3_wire;
	wire [7:0] a3_wire;
	assign z2_0 = z2[0];
	assign z2_1 = z2[1];
	assign z2_2 = z2[2];
	assign z3_wire = z3;
	sigmoid Hidden_0(.in(z2_0), .out(a2_0));
	sigmoid Hidden_1(.in(z2_1), .out(a2_1));
	sigmoid Hidden_2(.in(z2_2), .out(a2_2));
	sigmoid Output(.in(z3_wire), .out(a3_wire));
	initial
	begin
		x_0 = 8'd0;
		x_1 = 8'd0;
		X[0][0] = 8'sd0;
		X[0][1] = 8'sd1;
		X[1][0] = 8'sd1;
		X[1][1] = 8'sd0;
		X[2][0] = 8'sd0;
		X[2][1] = 8'sd0;
		X[3][0] = 8'sd1;
		X[3][1] = 8'sd1;
		y[0] = 1;
		y[1] = 1;
		y[2] = 0;
		y[3] = 0;
"""
    	Enum.map(String.split(str, "\n"), fn l ->
		    s = String.split(l, " = ")
		    cond do
			Enum.at(s, 0) == "w100" ->
				IO.puts("                W1[0][0] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w101" ->
				IO.puts("                W1[0][1] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w110" ->
				IO.puts("                W1[1][0] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w111" ->
				IO.puts("                W1[1][1] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w120" ->
				IO.puts("                W1[2][0] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w121" ->
				IO.puts("                W1[2][1] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w20" ->
				IO.puts("                W2[0] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w21" ->
				IO.puts("                W2[1] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "w22" ->
				IO.puts("                W2[2] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "b10" ->
				IO.puts("                B1[0] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "b11" ->
				IO.puts("                B1[1] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "b12" ->
				IO.puts("                B1[2] = #{Enum.at(s, 1)};")
			Enum.at(s, 0) == "b2" ->
				IO.puts("                B2 = #{Enum.at(s, 1)};")
			true ->
				IO.puts ""
			end
	    end)
	    IO.puts """
	end
	always @ *
	begin
		x_0[0:0] = x[0:0];
		x_1[0:0] = x[1:1];
	end
	always @ (posedge clock, posedge predict)
	begin
		if (predict)
		begin
			en_Hidden = 1;
			en_Output = 0;
			en_Hidden_sigmoid = 0;
			en_Output_sigmoid = 0;
			en_Display = 0;
			$display("x %b", x);
			pc <= 10;
		end
		else
		begin
			case(pc)
			10:
			begin
				z2[0] <= (W1[0][0] * x_0) + (W1[0][1] * x_1) + (B1[0]);
				z2[1] <= (W1[1][0] * x_0) + (W1[1][1] * x_1) + (B1[1]);
				z2[2] <= (W1[2][0] * x_0) + (W1[2][1] * x_1) + (B1[2]);
				en_Hidden_sigmoid <= 1;
				en_Hidden <= 0;
				pc <= 20;
			end
			20:
			begin
				a2[0][7:0] <= a2_0;
				a2[1][7:0] <= a2_1;
				a2[2][7:0] <= a2_2;
				en_Output <= 1;
				en_Hidden_sigmoid <= 0;
				$display("z20 %d", z2_0);
				$display("z21 %d", z2_1);
				$display("z22 %d", z2_2);
				pc <= 30;
			end
			30:
			begin
				z3 <= (W2[0] * a2[0] / 17'sd128) + (W2[1] * a2[1] / 17'sd128) + (W2[2] * a2[2] / 17'sd128) + B2;
				en_Output <= 0;
				en_Output_sigmoid <= 1;
				$display("a2_0 %d", a2[0]);
				$display("a2_1 %d", a2[1]);
				$display("a2_2 %d", a2[2]);
				pc <= 40;
			end
			40:
			begin
				a3 <= a3_wire;
				$display("z3 %d", z3);
				en_Output_sigmoid = 0;
				en_Display = 1;
				pc <= 50;
			end
			50:
			begin
				en_Display = 0;
				$display("Final prediction percentage for 1: %d", a3_wire);
				pc <= 60;
			end
			60:
			begin
				pc <= 60;
			end
			endcase
		end
	end
endmodule

module test;
	reg [1:0] x;
	reg clock;
	reg predict;
	wire [7:0] a3;
	XOR_NN uut(.x(x), .predict(predict), .clock(clock), .a3(a3));
	initial
	begin
		x = 2'b00;
		clock = 0;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		x = 2'b01;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		x = 2'b10;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		x = 2'b11;
		predict = 0;
	#100
		predict = 0;
	#10
		predict = 1;
	#10
		predict = 0;
	#100
		$finish;
	end
	initial
	begin
		forever
		begin
			#5 clock = ~clock;
		end
	end
endmodule
"""
	end
end

Main.run("""
w100 = 47
w101 = -61
w110 = -35
w111 = -46
w120 = 55
w121 = -37
w20 = 75
w21 = -44
w22 = -66
b10 = -23
b11 = 7
b12 = 13
b2 = 33
""")

```

# 成果物

https://paiza.io/projects/4ZzqbFOwxzWbwSsT8w7crw?language=elixir


以上。