paiza.ioでelixir その110

# 概要
paiza.ioでelixirやってみた。
FPGAの高位合成書いてみた。
パルス書いてみた。

# 高位合成て何
FPGAを記述する、HDL言語を生成するコンパイラ
下のコードから下の下のコードを生成する。

```
111111111000
```

```
module loop(input clk, input rst, output reg a);
	reg [4:0] state;
	always @(posedge clk or negedge rst)
	begin
		if (!rst)
		begin
			a <= 0;
			state <= 0;
		end
		else
			begin
			case (state)

			0 :
			begin
			    a <= 0;
			    state <= 1;
			end
			1:
                        begin
                           a <= 1;
                           state <= 2;
			end
			2 :
			begin
			    a <= 0;
			    state <= 3;
			end
			3:
                        begin
                           a <= 1;
                           state <= 4;
			end
			4 :
			begin
			    a <= 0;
			    state <= 5;
			end
			5:
                        begin
                           a <= 1;
                           state <= 6;
			end
			6 :
			begin
			    a <= 0;
			    state <= 7;
			end
			7:
                        begin
                           a <= 1;
                           state <= 8;
			end
			8 :
			begin
			    a <= 0;
			    state <= 9;
			end
			9:
                        begin
                           a <= 1;
                           state <= 10;
			end
			10 :
			begin
			    a <= 0;
			    state <= 11;
			end
			11:
                        begin
                           a <= 1;
                           state <= 12;
			end
			12 :
			begin
			    a <= 0;
			    state <= 13;
			end
			13:
                        begin
                           a <= 1;
                           state <= 14;
			end
			14 :
			begin
			    a <= 0;
			    state <= 15;
			end
			15:
                        begin
                           a <= 1;
                           state <= 16;
			end
			16 :
			begin
			    a <= 0;
			    state <= 17;
			end
			17:
                        begin
                           a <= 1;
                           state <= 18;
			end
			18 :
			begin
			    a <= 0;
			    state <= 19;
			end
			19:
                        begin
                           a <= 0;
                           state <= 20;
			end
			20 :
			begin
			    a <= 0;
			    state <= 21;
			end
			21:
                        begin
                           a <= 0;
                           state <= 22;
			end
			22 :
			begin
			    a <= 0;
			    state <= 23;
			end
			23:
                        begin
                           a <= 0;
                           state <= 0;
			end
			endcase
		end
	end
endmodule
module test;
	reg clk,
			rst;
	loop u(.clk(clk), .rst(rst), .a(a));
	initial
	begin
		clk = 0;
		rst = 1;
		#2
			rst = 0;
		#2
			rst = 1;
		#150
			$finish;
	end
	always
		#1
			clk = ~clk;
	initial
	begin
		$dumpfile("test.vcd");
		$dumpvars(0, test);
	end
endmodule

```

# シミュレーション結果

![image.png](https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/18104/c7f4cb5d-182b-739e-5818-f12a063d5bfd.png)

# サンプルコード

```
IO.puts """
module loop(input clk, input rst, output reg a);
	reg [4:0] state;
	always @(posedge clk or negedge rst)
	begin
		if (!rst)
		begin
			a <= 0;
			state <= 0;
		end
		else
			begin
			case (state)
"""
str = "111111111000"
l = String.length(str) * 2 - 2
Enum.reduce(String.split(str, "", trim: true), 0, fn x, n ->
    IO.puts "			#{n} :"
    IO.puts "			begin"
    IO.puts "			    a <= 0;"
    IO.puts "			    state <= #{n + 1};"
    IO.puts "			end"
    IO.puts "			#{n + 1}:"
    IO.puts "                        begin"
    IO.puts "                           a <= #{x};"
    cond do
    n == l ->
        IO.puts "                           state <= 0;"
    true ->
        IO.puts "                           state <= #{n + 2};"
    end
    IO.puts "			end"
    n + 2
end)
IO.puts """
			endcase
		end
	end
endmodule
module test;
	reg clk,
			rst;
	loop u(.clk(clk), .rst(rst), .a(a));
	initial
	begin
		clk = 0;
		rst = 1;
		#2
			rst = 0;
		#2
			rst = 1;
		#150
			$finish;
	end
	always
		#1
			clk = ~clk;
	initial
	begin
		$dumpfile("test.vcd");
		$dumpvars(0, test);
	end
endmodule
"""




```

# 成果物

https://paiza.io/projects/gXWtwXnLQtvFM79BGcorPQ


以上。