windowsでiverilog その83

#概要　

windowsでiverilogやってみた。
4bitのcpu書いた。
3個、繋げて見た。

#サンプルコード


```

module server(input clk, input rst, input [3:0] inport, output reg [3:0] outport);
	reg [3:0] a,
		b,
		pc;
	reg [7:0] mem[14:0];
	wire [7:0] code;
	wire [3:0] op;
	wire [3:0] opland;
	assign code = mem[pc];
	assign op = code[7:4];
	assign opland = code[3:0];
	always @(posedge clk, negedge rst)
	begin
		if (!rst)
		begin
			mem[0] <= 8'h51;//out 1
			mem[1] <= 8'h52;//out 2
			mem[2] <= 8'h54;//out 4
			mem[3] <= 8'h58;//out 8
			mem[4] <= 8'h66;//ifajmp 6
			mem[5] <= 8'h2f;//jmp f
			mem[6] <= 8'h54;//out 4
			mem[7] <= 8'h52;//out 2
			mem[8] <= 8'h51;//out 1
			mem[9] <= 8'h41;//ifbjmp 1
			mem[10] <= 8'h00;//add 0
			mem[11] <= 8'h00;//add 0
			mem[12] <= 8'h00;//add 0
			mem[13] <= 8'h00;//add 0
			mem[14] <= 8'h00;//add 0
			a <= 4'h0;
			b <= 4'h0;
			pc <= 4'h0;
		end
		else
		begin
			case (op)
			4'h0://add
			begin
				a <= a + opland;
				pc <= pc + 1;
			end
			4'h1://lda
			begin
				a <= opland;
				pc <= pc + 1;
			end
			4'h2://jmp
			begin
				pc <= opland;
			end
			4'h3://ldb
			begin
				b <= opland;
				pc <= pc + 1;
			end
			4'h4://ifbjmp
			begin
				if (inport[1] == 1)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			4'h5://out
			begin
				outport <= opland;
				pc <= pc + 1;
			end
			4'h6://ifajmp
			begin
				if (inport[0] == 1)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			4'h7://eqjmp
			begin
				if (a == b)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			endcase
		end
	end
	initial
	begin
		//$monitor("%h  %h  %h  %h", pc, op, opland, inport);
	end
endmodule

module clientA(input clk, input rst, input [3:0] inport, output reg [3:0] outport);
	reg [3:0] a,
		b,
		pc;
	reg [7:0] mem[14:0];
	wire [7:0] code;
	wire [3:0] op;
	wire [3:0] opland;
	assign code = mem[pc];
	assign op = code[7:4];
	assign opland = code[3:0];
	always @(posedge clk, negedge rst)
	begin
		if (!rst)
		begin
			mem[0] <= 8'h00;//add 0
			mem[1] <= 8'h00;//
			mem[2] <= 8'h00;//
			mem[3] <= 8'h60;//ifaout
			mem[4] <= 8'h60;//
			mem[5] <= 8'h00;//
			mem[6] <= 8'h00;//
			mem[7] <= 8'h00;//
			mem[8] <= 8'h00;//
			mem[9] <= 8'h00;//
			mem[10] <= 8'h00;//add 0
			mem[11] <= 8'h00;//add 0
			mem[12] <= 8'h00;//add 0
			mem[13] <= 8'h00;//add 0
			mem[14] <= 8'h00;//add 0
			a <= 4'h0;
			b <= 4'h0;
			pc <= 4'h0;
			outport <= 4'h0;
		end
		else
		begin
			case (op)
			4'h0://add
			begin
				a <= a + opland;
				pc <= pc + 1;
			end
			4'h1://lda
			begin
				a <= opland;
				pc <= pc + 1;
			end
			4'h2://jmp
			begin
				pc <= opland;
			end
			4'h3://ldb
			begin
				b <= opland;
				pc <= pc + 1;
			end
			4'h4://ifbjmp
			begin
				if (inport[1] == 1)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			4'h5://out
			begin
				outport <= opland;
				pc <= pc + 1;
			end
			4'h6://ifaout
			begin
				if (inport[2] == 1)
					outport <= 4'h1;
				pc <= pc + 1;
			end
			4'h7://eqjmp
			begin
				if (a == b)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			endcase
		end
	end
	initial
	begin
		//$monitor("%h  %h  %h  %h", pc, op, opland, inport);
	end
endmodule

module clientB(input clk, input rst, input [3:0] inport, output reg [3:0] outport);
	reg [3:0] a,
		b,
		pc;
	reg [7:0] mem[14:0];
	wire [7:0] code;
	wire [3:0] op;
	wire [3:0] opland;
	assign code = mem[pc];
	assign op = code[7:4];
	assign opland = code[3:0];
	always @(posedge clk, negedge rst)
	begin
		if (!rst)
		begin
			mem[0] <= 8'h00;//add 0
			mem[1] <= 8'h00;//
			mem[2] <= 8'h00;//
			mem[3] <= 8'h00;//
			mem[4] <= 8'h00;//
			mem[5] <= 8'h00;//
			mem[6] <= 8'h00;//
			mem[7] <= 8'h40;//ifbout
			mem[8] <= 8'h40;//ifbout
			mem[9] <= 8'h00;//
			mem[10] <= 8'h00;//add 0
			mem[11] <= 8'h00;//add 0
			mem[12] <= 8'h00;//add 0
			mem[13] <= 8'h00;//add 0
			mem[14] <= 8'h00;//add 0
			a <= 4'h0;
			b <= 4'h0;
			pc <= 4'h0;
			outport <= 4'h0;
		end
		else
		begin
			case (op)
			4'h0://add
			begin
				a <= a + opland;
				pc <= pc + 1;
			end
			4'h1://lda
			begin
				a <= opland;
				pc <= pc + 1;
			end
			4'h2://jmp
			begin
				pc <= opland;
			end
			4'h3://ldb
			begin
				b <= opland;
				pc <= pc + 1;
			end
			4'h4://ifbout
			begin
				if (inport[1] == 1)
					outport <= 4'h2;
				pc <= pc + 1;
			end
			4'h5://out
			begin
				outport <= opland;
				pc <= pc + 1;
			end
			4'h6://ifajmp
			begin
				if (inport[2] == 1)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			4'h7://eqjmp
			begin
				if (a == b)
					pc <= opland;
				else
					pc <= pc + 1;
			end
			endcase
		end
	end
	initial
	begin
		//$monitor("%h  %h  %h  %h", pc, op, opland, inport);
	end
endmodule

module test;
	reg clk,
		rst;
	wire [3:0] inport;
	wire [3:0] outport;
	wire [3:0] outporta;
	wire [3:0] outportb;
	server u(.clk(clk), .rst(rst), .inport(inport), .outport(outport));
	clientA a(.clk(clk), .rst(rst), .inport(outport), .outport(outporta));
	clientB b(.clk(clk), .rst(rst), .inport(outport), .outport(outportb));
	assign inport = {1'b0, 1'b0, outportb[1], outporta[0]};
	initial
	begin
		//$monitor("%b  %b  %b %b", outporta, outport, outportb, inport);
		$monitor("%b   %b   %b", outporta, outport, outportb);
		clk = 0;
		rst = 1;
		#2
			rst = 0;
		#2
			rst = 1;
		#30
			$finish;
	end
	always
		#1
			clk = ~clk;
endmodule





```

#実行結果

```


xxxx   xxxx   xxxx
0000   xxxx   0000
0000   0001   0000
0000   0010   0000
0000   0100   0000
0001   1000   0000
0001   0100   0000
0001   0010   0000
0001   0001   0010
0001   0010   0010
0001   0100   0010
0001   1000   0010
0001   0100   0010
0001   0010   0010


```


以上。