windowsでiverilog その87

#概要　

windowsでiverilogやってみた。
avrのcpu書いてみる。
構想編。

#cpu仕様

レジスタマシン
8bit CPU（汎用レジスタが8bit 32本）
メモリーは、rom16語8bit, ram16語8bit
マシン語は8bit, 2byte固定長
命令は、転送命令、ビット操作命令、算術命令、分岐命令の４種類
プログラムカウンタ(12bit)
スタック(8bit), 深さ８
入出力は8bit
レジスタは、r0からr31の32個
命令長は、2バイト。rjmpとrcallは、相対アドレス
ｘｙｚレジスタは、r26:r27, r28:r29, r30:r31
r0からr15は、ldi, cpiできない
sramにプログラムは、置けない。
フラグは、z, c, n, s, h, t, v, i
r31をportaへ、出力する。

#アセンブラの説明

|アセンブリ|	機械語|	動作|
|:--|:--|:--|
|MOV Rd, Rr  |001011xxxxxxxxxx|      Rd = Rr
MOVW Rd, Rr  ||   Rd1 : Rd = Rr1 : Rr, r, d even
LDI Rd, K8   |1110xxxxxxxxxxxx|   Rd = K8
LDS Rd, k    ||   Rd = (k)
LD Rd, X     ||   Rd = (X)
LD Rd, X+    ||   Rd = (X), X = X + 1
LD Rd, -X    ||   X = X - 1, Rd = (X)
LD Rd, Y    ||    Rd = (Y)
LD Rd, Y+   ||    Rd = (Y), Y = Y + 1
LD Rd, -Y   ||    Y = Y - 1, Rd = (Y)
LDD Rd, Y+q ||    Rd = (Y + q)
LD Rd, Z    ||    Rd = (Z)
LD Rd, Z+   ||    Rd = (Z), Z = Z + 1
LD Rd, -Z   ||    Z = Z - 1, Rd = (Z)
LDD Rd, Z+q ||    Rd = (Z + q)
STS k, Rr   ||    (k) = Rr
ST X, Rr    ||    (X) = Rr
ST X+, Rr   ||    (X) = Rr, X = X + 1
ST -X, Rr   ||    X = X - 1, (X) = Rr
ST Y, Rr    ||    (Y) = Rr
ST Y+, Rr   ||    (Y) = Rr, Y = Y + 1
ST -Y, Rr   ||    Y = Y - 1, (Y) = Rr
ST Y+q, Rr  ||    (Y + q) = Rr
ST Z, Rr    ||    (Z) = Rr
ST Z+, Rr   ||    (Z) = Rr, Z = Z + 1
ST -Z, Rr   ||    Z = Z - 1, (Z) = Rr
ST Z+q, Rr  ||    (Z + q) = Rr
LPM         ||    R0 = (Z)
LPM Rd, Z   ||    Rd = (Z)
LPM Rd, Z+  ||    Rd = (Z), Z = Z + 1
ELPM        ||    R0 = (RAMPZ : Z)
ELPM Rd, Z  ||    Rd = (RAMPZ : Z)
ELPM Rd, Z+ ||    Rd = (RAMPZ : Z),  Z = Z + 1
SPM         ||    (Z) = R1 : R0
ESPM        ||    (RAMPZ : Z) = R1 : R0
IN Rd, P    ||    Rd = P
OUT P, Rr   ||    P = Rr
PUSH Rr     ||    STACK = Rr
POP Rd      ||    Rd = STACK
LSL Rd    ||      Rd(n + 1) = Rd(n),  Rd(0) = 0, C = Rd(7)
LSR Rd    |1001010xxxxx0110|      Rd(n) = Rd(n + 1), Rd(7) = 0, C = Rd(0)
ROL Rd    ||      Rd(0) = C, Rd(n + 1) = Rd(n), C = Rd(7)
ROR Rd    ||      Rd(7) = C, Rd(n) = Rd(n + 1), C = Rd(0)
ASR Rd    ||      Rd(n) = Rd(n + 1),  n = 0, ..., 6
SWAP      ||      Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0)
BSET s    ||      SREG(s) = 1
BCLR s    ||      SREG(s) = 0
SBI P, b   ||     I/O(P, b) = 1
CBI P, b   ||     I/O(P, b) = 0
BST Rr, b  ||     T = Rr(b)
BLD Rd, b  ||     Rd(b) = T
SEC        ||     C = 1
CLC        ||     C = 0
SEN        ||     N = 1
CLN        ||     N = 0
SEZ        ||     Z = 1
CLZ        ||     Z = 0
SEI        ||     I = 1
CLI        ||     I = 0
SES        ||     S = 1
CLN        ||     S = 0
SEV        ||     V = 1
CLV        ||     V = 0
SET        ||     T = 1
CLT        ||     T = 0
SEH        ||     H = 1
CLH         ||    H = 0
NOP         ||    No operation
SLEEP       ||    Sleep
WDR         ||    Watchdog
BREAK       ||    Execution Break
ADD Rd, Rr  |000011xxxxxxxxxx|    Rd = Rd + Rr 
ADC Rd, Rr  |000111xxxxxxxxxx|    Rd = Rd + Rr + C
ADIW Rd, K  ||    Rd + 1 : Rd, K
SUB Rd, Rr  |000110xxxxxxxxxx|    Rd = Rd - Rr
SUBI Rd, K8  |0101xxxxxxxxxxxx|   Rd = Rd - K8
SBC Rd, Rr   |000010xxxxxxxxxx|   Rd = Rd - Rr - C
SBCI Rd, K8  ||   Rd = Rd - K8 - C
AND Rd, Rr   |001000xxxxxxxxxx|   Rd = Rd · Rr
ANDI Rd, K8  ||   Rd = Rd · K8
OR Rd, Rr    |001010xxxxxxxxxx|   Rd = Rd V Rr
ORI Rd, K8   ||   Rd = Rd V K8
EOR Rd, Rr   |001001xxxxxxxxxx|   Rd = Rd EOR Rr
COM Rd       ||   Rd = $FF - Rd
NEG Rd       ||   Rd = $00 - Rd
SBR Rd, k8   ||   Rd = Rd V K8
CBR Rd, k8   ||   Rd = Rd · ($FF - K8)
INC Rd       ||   Rd = Rd + 1
DEC Rd       ||   Rd = Rd - 1
TST Rd       ||   Rd = Rd · Rd
CLR Rd       ||   Rd = 0
SER Rd       ||   Rd = $FF
SBIW Rdl, K6 ||   Rdh : Rdl = Rdh : Rdl - K6
MUL Rd, Rr   ||   R1 : R0 = Rd * Rr
MULS Rd, Rr  ||   R1 : R0 = Rd * Rr
MULSU Rd, Rr ||   R1 : R0 = Rd * Rr
FMUL Rd, Rr  ||   R1 : R0 = (Rd * Rr) << 1
FMULS Rd, Rr  ||  R1 : R0 = (Rd * Rr) << 1
FMULSU Rd, Rr ||  R1 : R0 = (Rd * Rr) << 1
RJMP k    ||      PC = PC + k + 1
IJMP       ||     PC = Z
EIJMP      ||     STACK = PC + 1,  PC(15 : 0) = Z,  PC(21 : 16) = EIND
JMP k      ||     PC = k
RCALL k    ||     STACK = PC + 1,  PC = PC + k + 1
ICALL      ||     STACK = PC + 1,  PC = Z 
EICALL     ||     STACK = PC + 1,  PC(15 : 0) = Z,  PC(21 : 16) = EIND
CALL k     ||     STACK = PC + 2,  PC = k
RET         ||    PC = STACK
RETI        ||    PC = STACK
CPSE Rd, Rr  ||   if (Rd == Rr) PC = PC 2 or 3
CP Rd, Rr    |000101xxxxxxxxxx|   Rd - Rr
CPC Rd, Rr   ||   Rd - Rr - C
CPI Rd, K8   ||   Rd - K
SBRC Rr, b   ||   if (Rr(b) == 0) PC = PC + 2 or 3
SBRS Rr, b   ||   if (Rr(b) == 1) PC = PC + 2 or 3
SBIC P, b    ||   if (I/O(P, b) == 0) PC = PC + 2 or 3
SBIS P, b    ||   if (I/O(P, b) == 1) PC = PC + 2 or 3
BRBC s, k    ||   if (SREG(s) == 0) PC = PC + k + 1
BRBS s, k    ||   if (SREG(s) == 1) PC = PC + k + 1
BREQ k       |111100xxxxxxx001|   if (Z == 1) PC = PC + k + 1
BRNE k       |111101xxxxxxx001|   if (Z == 0) PC = PC + k + 1
BRCS k       |111100xxxxxxx000|   if (C == 1) PC = PC + k + 1
BRCC k       |111101xxxxxxx000|   if (C == 0) PC = PC + k + 1
BRSH k       ||   if (C == 0) PC = PC + k + 1
BRLO k       ||   if (C == 1) PC = PC + k + 1
BRMI k       ||   if (N == 1) PC = PC + k + 1
BRPL k       ||   if (N == 0) PC = PC + k + 1
BRGE k       ||   if (S == 0) PC = PC + k + 1
BRLT k       ||   if (S == 1) PC = PC + k + 1
BRHS k       ||   if (H == 1) PC = PC + k + 1
BRHC k       ||   if (H == 0) PC = PC + k + 1
BRTS k       ||   if (T == 1) PC = PC + k + 1
BRTC k       ||   if (T == 0) PC = PC + k + 1
BRVS k       ||   if (V == 1) PC = PC + k + 1
BRVC k       ||   if (V == 0) PC = PC + k + 1
BRIE k       ||   if (I == 1) PC = PC + k + 1
BRID k       ||   if (I == 0) PC = PC + k + 1