windowsでiverilog その62

#概要　

windowsでiverilogやってみた。
浮動小数点の加算やってみる。

#使用したライブラリー

https://github.com/suhasr1991/5-Stage-Pipelined-IEEE-Single-Precision-Floating-Point-Adder-Design

#サンプルコード


```
`timescale 1ns/1ps

module IEEE_SP_FP_ADDER(input clk, input reset, input [31:0] Number1, input [31:0] Number2, output [31:0] Result);
	reg [31:0] Num_shift_80;
	reg [7:0] Larger_exp_80,
		Final_expo_80;
	reg [22:0] Small_exp_mantissa_80,
		S_mantissa_80,
		L_mantissa_80,
		Large_mantissa_80,
		Final_mant_80;
	reg [23:0] Add_mant_80,
		Add1_mant_80;
	reg [7:0] e1_80,
		e2_80;
	reg [22:0] m1_80,
		m2_80;
	reg s1_80,
		s2_80,
		Final_sign_80;
	reg [3:0] renorm_shift_80;
	integer signed renorm_exp_80;
	reg [31:0] Result_80;
	assign Result = Result_80;
	always @(*)
	begin
		e1_80 = Number1[30:23];
		e2_80 = Number2[30:23];
		m1_80 = Number1[22:0];
		m2_80 = Number2[22:0];
		s1_80 = Number1[31];
		s2_80 = Number2[31];
		if (e1_80 > e2_80)
		begin
			Num_shift_80 = e1_80 - e2_80;
			Larger_exp_80 = e1_80;
			Small_exp_mantissa_80 = m2_80;
			Large_mantissa_80 = m1_80;
		end
		else
		begin
			Num_shift_80 = e2_80 - e1_80;
			Larger_exp_80 = e2_80;
			Small_exp_mantissa_80 = m1_80;
			Large_mantissa_80 = m2_80;
		end
		if (e1_80 == 0 | e2_80 == 0)
		begin
			Num_shift_80 = 0;
		end
		else
		begin
			Num_shift_80 = Num_shift_80;
		end
		if (e1_80 != 0)
		begin
			Small_exp_mantissa_80 = {1'b1, Small_exp_mantissa_80[22:1]};
			Small_exp_mantissa_80 = (Small_exp_mantissa_80 >> Num_shift_80);
		end
		else
		begin
			Small_exp_mantissa_80 = Small_exp_mantissa_80;
		end
		if (e2_80 != 0)
		begin
			Large_mantissa_80 = {1'b1, Large_mantissa_80[22:1]};
		end
		else
		begin
			Large_mantissa_80 = Large_mantissa_80;
		end
		if (Small_exp_mantissa_80 < Large_mantissa_80)
		begin
			S_mantissa_80 = Small_exp_mantissa_80;
			L_mantissa_80 = Large_mantissa_80;
		end
		else
		begin
			S_mantissa_80 = Large_mantissa_80;
			L_mantissa_80 = Small_exp_mantissa_80;
		end
		if (e1_80 != 0 & e2_80 != 0)
		begin
			if (s1_80 == s2_80)
			begin
				Add_mant_80 = S_mantissa_80 + L_mantissa_80;
			end
			else
			begin
				Add_mant_80 = L_mantissa_80 - S_mantissa_80;
			end
		end
		else
		begin
			Add_mant_80 = L_mantissa_80;
		end
		if (Add_mant_80[23])
		begin
			renorm_shift_80 = 4'd1;
			renorm_exp_80 = 4'd1;
		end
		else if (Add_mant_80[22])
		begin
			renorm_shift_80 = 4'd2;
			renorm_exp_80 = 0;
		end
		else if (Add_mant_80[21])
		begin
			renorm_shift_80 = 4'd3;
			renorm_exp_80 = -1;
		end
		else if (Add_mant_80[20])
		begin
			renorm_shift_80 = 4'd4;
			renorm_exp_80 = -2;
		end
		else if (Add_mant_80[19])
		begin
			renorm_shift_80 = 4'd5;
			renorm_exp_80 = -3;
		end
		Final_expo_80 = Larger_exp_80 + renorm_exp_80;
		Add1_mant_80 = Add_mant_80 << renorm_shift_80;
		Final_mant_80 = Add1_mant_80[23:1];
		if (s1_80 == s2_80)
		begin
			Final_sign_80 = s1_80;
		end
		if (e1_80 > e2_80)
		begin
			Final_sign_80 = s1_80;
		end
		else if (e2_80 > e1_80)
		begin
			Final_sign_80 = s2_80;
		end
		else
		begin
			if (m1_80 > m2_80)
			begin
				Final_sign_80 = s1_80;
			end
			else
			begin
				Final_sign_80 = s2_80;
			end
		end
		Result_80 = {Final_sign_80, Final_expo_80, Final_mant_80};
	end
	always @(posedge clk)
	begin
		if (reset)
		begin
			Num_shift_80 <= #1 0;
		end
	end
endmodule

module test();
	reg [31:0] Number1,
		Number2;
	reg reset,
		clk;
	wire [31:0] Result;
	IEEE_SP_FP_ADDER ia1(clk, reset, Number1, Number2, Result);
	always
		#2
			clk = ~clk;
	initial
	begin
		$monitor("%t %h %h %h", $time, Number1, Number2, Result);
		#2
			clk = 1;
			reset = 1;
		#4
			reset = 0;
			Number1 = 32'h3f000000;
			Number2 = 32'h3f000000;
		#2;
		#200 $finish;
	end
endmodule





```

#実行結果


```

                   0 xxxxxxxx xxxxxxxx xxxxxxxx
                6000 3f000000 3f000000 3f800000


```


以上。