Analog Integrated Circuit Design Automation [electronic resource] : Placement, Routing and Parasitic Extraction Techniques /
Martins, Ricardo.author.(orcid)0000-0002-8251-1415https://orcid.org/0000-0002-8251-1415aut
Lourenço, Nuno.author.
Horta, Nuno.author.
This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.
Includes bibliographical references at the end of each chapters and index.
1 Introduction -- 2 State-of-the-Art on Analog Layout Automation -- 3 AIDA-L: Architecture and Integration -- 4 Template-based Placer -- 5 Optimization-based Placer -- 6 Fully-Automatic Router -- 7 Empirical-based Parasitic Extractor -- 8 Experimental Results -- 9 Conclusions and Future Work.
This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.
Electronic circuits.
Microprocessors.
Electronics.
Microelectronics.
Circuits and Systems.
Processor Architectures.
Electronics and Microelectronics, Instrumentation.