Principles of VLSI RTL Design [electronic resource] : A Practical Guide /
Churiwala, Sanjay.author.
Garg, Sapan.author.
� In the process of integrated circuit design, front-end activities start with a register transfer level (RTL) description, of the functionality desired from the IC.� During subsequent steps in the design flow, issues may arise related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc. which are a function of the way the RTL was originally written. As a result, RTL designers need to take care of many aspects which can have impact on later steps in the design process. Since RTL design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains those various aspects, their significance, what caution needs to be taken during RTL design and why.� Readers will benefit from a highly practical approach to the fundamentals of uncertainties around functionality, clock domain crossing and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling, and routing congestion. Hopefully, this book will find its place in the hearts and minds of anyone who generates RTL code. This includes RTL designers as well as those writing tools that generate RTL. Relatively new RTL designers will find this book to be a single-source of interesting, rich and useful knowledge.� Experienced RTL designers will be able to appreciate and cement some already known concepts, given the focus on practical situations encountered in real designs. � * Provides a highly accessible, single-source reference to all key topics essential to an RTL designer; * Describes in detail specific actions/cautions that designer needs to consider in design to avoid problems in downstream implementation; * Covers content based on practical experience with numerous real designs from large semiconductor design companies. � �.
""Foreword""; ""Preface""; "" Acknowledgments""; ""Contents""; ""1 Introduction to VLSI RTL Designs""; ""1.1 A Brief Background""; ""1.2 Hardware Description Languages (HDL)""; ""1.3 RTL  Designs""; ""1.4 Design Goals and Constraints""; ""1.5 RTL Based Chip Design Flow""; ""1.6 Design Challenges""; ""1.6.1 Simulation Friendly RTL""; ""1.6.2 Timing-Analysis Friendly RTL""; ""1.6.3 Clock-Domain-Crossing (CDC ) Friendly RTL""; ""1.6.4 Power Friendly RTL""; ""1.6.5  DFT Friendly RTL""; ""1.6.6 Timing-Exceptions Friendly RTL""; ""1.6.7 Congestion Conscious RTL""; ""1.7 Summary""
""2 Ensuring RTL Intent""""2.1 Need for Unambiguous Simulation""; ""2.2 Simulation Race""; ""2.2.1 Read-Write Race""; ""2.2.1.1 Combinational Read-Write Race""; ""2.2.1.2 Sequential Read-Write Race""; ""2.2.2 Write-Write Race""; ""2.2.3 Always-Initial Race""; ""Scenario 1""; ""Scenario 2""; ""2.2.4  Race Due to Inter-leaving of Assign with Procedural Block""; ""2.2.5 Avoiding Simulation Race""; ""2.3 Feedthroughs""; ""2.3.1 Feedthroughs Because of Races""; ""2.3.2 Feedthroughs Without Simulation Race""; ""2.3.3 VHDL Feedthroughs""; ""2.4 Simulation-Synthesis Mismatch""
""2.5 Latch Inference""""2.6 Synchronous Reset""; ""2.7 Limitations of Simulation""; ""3 Timing Analysis""; ""3.1 Scope of STA""; ""3.1.1 Simulation Limitations in the Context of Timing""; ""3.1.2 Exhaustiveness of STA""; ""3.2 Timing Parameters for Digital Logic""; ""3.2.1 Delay Parameters""; ""3.2.2 Slew Parameters for Digital Logic""; ""3.2.3 Delay and Slew Measurement""; ""3.3 Factors Affecting Delay and Slew""; ""3.3.1 Discrete Factors""; ""3.3.1.1 Gate's Geometry and Schematic""; ""3.3.1.2 Specific Path""; ""3.3.1.3 Specific Directions of the Transitions""
""3.3.1.4 Conditions on Other Pins""""3.3.2 Continuous Factors""; ""3.3.2.1 Load on the Gate""; ""3.3.2.2 Input Slew""; ""3.3.2.3 Interpolation/Extrapolation""; ""3.3.2.4 Temperature""; ""3.3.2.5 Voltage""; ""3.3.2.6 Process""; ""3.3.2.7 Operating Condition""; ""3.3.2.8 Derating""; ""3.4 Sequential Arcs""; ""3.4.1 Pulse Width""; ""3.4.2 Setup""; ""3.4.3 Hold""; ""3.4.4 Recovery""; ""3.4.5 Removal""; ""3.5 Understanding Setup and Hold""; ""3.5.1 Understanding Setup""; ""3.5.2 Understanding Hold""; ""3.6 Negative Timing Check""; ""3.7 Basic Analysis""; ""3.8 Uncertainty""
""3.9 STA  Contrasted with Simulation""""3.9.1 Setup Violation in STA, No Violation in Simulation""; ""3.9.2 Setup Violation in STA, Hold Violation in Simulation""; ""3.9.3 Hold Violation in STA, Setup Violation in Simulation""; ""3.10 Accurate Timing Simulation""; ""3.11 Limitations of Static Timing Analysis""; ""3.12 SSTA""; ""3.13 Conclusion""; ""4 Clock Domain Crossing (CDC)""; ""4.1 Clock Domain""; ""4.2 Metastability Due to CDC""; ""4.2.1 Understanding Metastability""; ""4.2.2 Problems Due to Metastability""; ""4.3 Synchronizer""; ""4.3.1 Double Flop Synchronizer""
""4.3.2 Mean Time Between Failures (MTBF)   ""
Includes index.
� In the process of integrated circuit design, front-end activities start with a register transfer level (RTL) description, of the functionality desired from the IC.� During subsequent steps in the design flow, issues may arise related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc. which are a function of the way the RTL was originally written. As a result, RTL designers need to take care of many aspects which can have impact on later steps in the design process. Since RTL design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains those various aspects, their significance, what caution needs to be taken during RTL design and why.� Readers will benefit from a highly practical approach to the fundamentals of uncertainties around functionality, clock domain crossing and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling, and routing congestion. Hopefully, this book will find its place in the hearts and minds of anyone who generates RTL code. This includes RTL designers as well as those writing tools that generate RTL. Relatively new RTL designers will find this book to be a single-source of interesting, rich and useful knowledge.� Experienced RTL designers will be able to appreciate and cement some already known concepts, given the focus on practical situations encountered in real designs. � * Provides a highly accessible, single-source reference to all key topics essential to an RTL designer; * Describes in detail specific actions/cautions that designer needs to consider in design to avoid problems in downstream implementation; * Covers content based on practical experience with numerous real designs from large semiconductor design companies. � �.
Electronic circuits.
Computer-aided engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.