The definitive guide to ARM Cortex-M0 and Cortex-M0+ processors /
Joseph Yiuauthor.
The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques.    Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program co
Description based upon print version of record.
2.4 What Is ARMv6-M Architecture?2.5 Software Portability Between Cortex®-M Processors; 2.6 The Advantages of the ARM® Cortex®-M0 and Cortex-M0+ Processor; 2.7 Applications of the Cortex®-M0 and Cortex-M0+ Processors; 2.8 Why Using a 32-Bit Processor for Microcontroller Applications?; Chapter 3 - Introduction to Embedded Software Development; 3.1 Welcome to Embedded System Programming; 3.2 Some Basic Concepts; 3.3 Introduction to ARM® Cortex®-M Programming; 3.4 Software Development Flow; 3.5 Cortex® Microcontroller Software Interface Standard; 3.6 Other Information on Software Development
Chapter 4 - Architecture4.1 Overview of ARMv6-M Architecture; 4.2 Programmer's Model; 4.3 Memory System; 4.4 Stack Memory Operations; 4.5 Exceptions and Interrupts; 4.6 Nested Vectored Interrupt Controller; 4.7 System Control Block; 4.8 Debug System; 4.9 Program Image and Start-up Sequence; Chapter 5 - Instruction Set; 5.1 What Is Instruction Set; 5.2 Background of ARM® and Thumb® Instruction Set; 5.3 Assembly Basics; 5.4 Instruction List; 5.5 Pseudo Instructions; Chapter 6 - Instruction Usage Examples; 6.1 Overview; 6.2 Program Control; 6.3 Data Accesses; 6.4 Data Type Conversion
6.5 Data ProcessingChapter 7 - Memory System; 7.1 Memory Systems in Microcontrollers; 7.2 Bus Systems in the Cortex®-M0 and Cortex-M0+ Processors; 7.3 Memory Map; 7.4 Program Memory, Boot Loader, and Memory Remapping; 7.5 Data Memory; 7.6 Little Endian and Big Endian Support; 7.7 Data Type; 7.8 Memory Attributes and Memory Access Permission; 7.9 Effect of Hardware Behavior to Programming; Chapter 8 - Exceptions and Interrupts; 8.1 What are Exceptions and Interrupts?; 8.2 Exception Types on the Cortex®-M0 and Cortex-M0+ Processors; 8.3 Brief Overview of the NVIC
8.4 Definition of Exception Priority Levels8.5 Vector Table; 8.6 Exception Sequence Overview; 8.7 EXC_RETURN; 8.8 NVIC Control Registers for Interrupt Control; 8.9 Exception Masking Register (PRIMASK); 8.10 Interrupt Inputs and Pending Behavior; 8.11 Details of Exception Entry Sequence; 8.12 Details of Exception Exit Sequence; 8.13 Interrupt Latency; Chapter 9 - System Control and Low-Power Features; 9.1 Brief Introduction of System Control Registers; 9.2 Registers in the SCBs; 9.3 Using the Self-Reset Feature; 9.4 Using the Vector Table Relocation Feature; 9.5 Low-Power Features
Chapter 10 - Operating System Support Features
The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques.    Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program co

Includes bibliographical references and index.
Description based on print version record.
Embedded computer systems.
Microprocessors.