On-Chip Interconnect with aelite [electronic resource] : Composable and Predictable Systems /
Hansson, Andreas.author.
Goossens, Kees.author.
On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
Description based upon print version of record.
Contents; 1  Introduction; 1.1  Trends; 1.1.1  Application Requirements; 1.1.2  Implementation and Design; 1.1.3  Time and Cost; 1.1.4  Summary; 1.1.5  Example System; 1.2  Requirements; 1.2.1  Scalability; 1.2.2  Diversity; 1.2.3  Composability; 1.2.4  Predictability; 1.2.5  Reconfigurability; 1.2.6  Automation; 1.3  Key Components; 1.4  Organisation; 2  Proposed Solution; 2.1  Architecture Overview; 2.1.1  Contention-Free Routing; 2.2  Scalability; 2.2.1  Physical Scalability; 2.2.2  Architectural Scalability; 2.3  Diversity; 2.3.1  Network Stack; 2.3.2  Streaming Stack
2.3.3  Memory-Mapped Stack2.4  Composability; 2.4.1  Resource Flow-Control Scheme; 2.4.2  Flow Control and Arbitration Granularities; 2.4.3  Arbitration Unit Size; 2.4.4  Temporal Interference; 2.4.5  Summary; 2.5  Predictability; 2.5.1  Architecture Behaviour; 2.5.2  Modelling and Analysis; 2.6  Reconfigurability; 2.6.1  Spatial and Temporal Granularity; 2.6.2  Architectural Support; 2.7  Automation; 2.7.1  Input and Output; 2.7.2  Division into Tools; 2.8  Conclusions; 3  Dimensioning; 3.1  Local Buses; 3.1.1  Target Bus; 3.1.2  Initiator Bus; 3.2  Atomisers; 3.2.1  Limitations
3.3  Protocol Shells3.3.1  Limitations; 3.4  Clock Domain Crossings; 3.5  Network Interfaces; 3.5.1  Architecture; 3.5.2  Experimental Results; 3.5.3  Limitations; 3.6  Routers; 3.6.1  Experimental Results; 3.6.2  Limitations; 3.7  Mesochronous Links; 3.7.1  Experimental Results; 3.7.2  Limitations; 3.8  Control Infrastructure; 3.8.1  Unified Control and Data; 3.8.2  Architectural Components; 3.8.3  Limitations; 3.9  Conclusions; 4  Allocation; 4.1  Sharing Slots; 4.2  Problem Formulation; 4.2.1  Application Specification; 4.2.2  Network Topology Specification; 4.2.3  Allocation Specification
4.2.4  Residual Resource Specification4.3  Allocation Algorithm; 4.3.1  Channel Traversal Order; 4.3.2  Speculative Reservation; 4.3.3  Path Selection; 4.3.4  Refinement of Mapping; 4.3.5  Slot Allocation; 4.3.6  Resource Reservation; 4.3.7  Limitations; 4.4  Experimental Results; 4.5  Conclusions; 5  Instantiation; 5.1  Hardware; 5.1.1  SystemC Model; 5.1.2  RTL Implementation; 5.2  Allocations; 5.3  Run-Time Library; 5.3.1  Initialisation; 5.3.2  Opening a Connection; 5.3.3  Closing a Connection; 5.3.4  Temporal Bounds; 5.4  Experimental Results; 5.4.1  Setup Time
5.4.2  Memory Requirements5.4.3  Tear-Down Time; 5.5  Conclusions; 6  Verification; 6.1  Problem Formulation; 6.1.1  Cyclo-static Dataflow (CSDF) Graphs; 6.1.2  Buffer Capacity Computation; 6.2  Network Requirements; 6.3  Network Behaviour; 6.3.1  Slot Table Injection; 6.3.2  Header Insertion; 6.3.3  Path Latency; 6.3.4  Return of Credits; 6.4  Channel Model; 6.4.1  Fixed Latency; 6.4.2  Split Latency and Rate; 6.4.3  Split Data and Credits; 6.4.4  Final Model; 6.4.5  Shell Model; 6.5  Buffer Sizing; 6.5.1  Modelling the Application; 6.5.2  Synthetic Benchmarks; 6.5.3  Mobile Phone SoC
6.5.4  Set-Top Box SoC
Includes bibliographical references and index.
On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
Electronic circuits.
Computer-aided engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Embedded systems