Protecting Chips Against Hold Time Violations Due to Variability [electronic resource] /
Neuberger, Gustavo.author.
Wirth, Gilson.author.
Reis, Ricardo.author.(orcid)0000-0001-5781-5858https://orcid.org/0000-0001-5781-5858aut
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements.  The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.  ·         Provides a comprehensive review of various reliability mechanisms; ·         Describes practical modeling and characterization techniques for reliability ·         Includes thorough presentation of robust design techniques for major VLSI design units ·         Promotes physical understanding with first-principle simulations.
Description based upon print version of record.
Includes bibliographical references and index.
Introduction, Process Variations and Flip-Flops -- Process Variability -- Flip-Flops and Hold Time Violations -- Circuits Under Test -- Measurement Circuits -- Experimental Results -- Systematic and Random Variablility -- Normality Tests -- Probability of Hold Time Violations -- Protecting Circuits Against Hold Time Violations -- Padding Efficiency Of the Proposed Padding Algorithm -- Final Remarks.
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements.  The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.  ·         Provides a comprehensive review of various reliability mechanisms; ·         Describes practical modeling and characterization techniques for reliability ·         Includes thorough presentation of robust design techniques for major VLSI design units ·         Promotes physical understanding with first-principle simulations.
Electronic circuits.
Microprocessors.
Circuits and Systems.
Processor Architectures.