by eschu | 2026-01-25 21:32:57+00:00
There was a lot of learning and reinventing to do. It started with a team of 1, and we eventually grew to a team 5. We all started working on it more or less fresh out of university. We were trained as mathematicians, physicists and computational science engineers, not electrical engineers. So just that was a journey. Along the way we learned about SPICE, PLECS, power electronics, and how to manage ourselves. In the end, it turned out to be quite a strength to come from the outside and give the field a fresh look.

But there were serious technical challenges too.

- Most circuit simulators use either trap or BDF methods for stepping in time. Most are 2nd order. It has been the case for many decades. We went ahead in the end with modern 3rd order (E)SDIRK (Runge-Kutta) methods. It took a lot of digging, research and trial and error to make that work. But we basically had to, because since we wanted PLECS models to run alongside SPICE circuits as a whole system (just straight up building the equations together, avoiding the synchronization required by bi-directional coupling strategies or relaxation methods), we needed a memoryless solver that was tough enough to handle the very frequent discontinuities from the ideal switch models of PLECS. To compensate for the implicit steps, we needed to develop a strategy to track convergence rates and reliably bypass Jacobian computations when possible (and inform the convergence detection). The new solver has an embedded error estimator, an optimized PPID stepsize controller, a discontinuity detector and dense interpolation for zero-crossing detection built-in (to handle those ideal switches and discontinuous pulses from system-level power electronics and digital controls). Each components also inform the stepsize control.

- We have implemented condensed MNA to reduce the number of degrees of freedom (from the capacitor currents), and implemented and tested different recent research suggestions from Sandia Labs, e.g. different forms of PCNR for voltage limiting. We had to reinvent convergence helpers (homotopy) that worked with our formulation. And since PLECS was originally designed to solve ODEs, it started with initial conditions, while SPICE typically starts performing an operating point. So we needed there too to invent a graph algorithm that could initialize the combined formulations (MNA + piecewise state-space) consistently in a way that avoids over-determined states.

- A major endeavor was also the netlist parser. It was built from scratch and handles many dialects. Rather than making yet another rigid set of rules and push another syntax to the SPICE world, we wanted a parser that could parse it all, so that most semiconductor manufacturer's netlists could be used.

- Netlists in SPICE aren't full descriptions based on elementary elements. They often assume built-in compact models, which are standardized models of semiconductors like MOSFET, diode, etc. Rather them wrapping existing code, we built them from scratch to be able to optimize and regularize problematic equations. We could improve on the basic compact models and adopted charge-conservative formulations.

Then, there was the UI integration into the PLECS schematic editor, optimization, parallelization etc. Overall, the result is quite a modern take on circuit simulation.