Position: PHY-RTL Engineer
Company: A-Listware
Category: C++
Experience required: 2y
English level: upper

A-LISTWARE welcomes a PHY-RTL Engineer

**Our customer:**
Our mission is to reorganize communication between space robots, and spacecraft through deep space, in earth orbit, and with ground stations.

**Required experience and skills:**
Experience with signal processing functions and mixed-signal systems;
Experience with FPGA build flow including design, synthesis, place and route, timing constraints, and timing closure;
Experience with development in Verilog/VHDL/Vivado/Vitis;
Knowledge of debugging methodologies;
B.Sc. in Electrical Engineering or related with an emphasis on signal processing;
English — Upper-Intermediate.

**Would be a plus:**
Experience with Xilinx Versal;
Experience with beamforming and MIMO systems;
Experience with analog and RF front-end design;
Experience in space system development;
Ability to write scripts in MATLAB, python, or other scripting languages;
Experience with C/C++.

**Working conditions**
5-day working week, 8-hour working day, flexible schedule
All public holidays are days off
Vacation and sick leave are covered by the company
Remote work