Position: FPGA developer
Company: Luxoft
Category: Other
Experience required: 2y
English level: intermediate

Project Description:
Our Client provides market data, trading access, liquidity venue connectivity, pre-trade risk and execution management for Investment Banks, Hedge Funds and Proprietary Trading Firms globally. By facilitating low latency, resilient and secure trading, Our Client enhances operational efficiencies for the world's electronic trading communities.
The role is for 'Zero Latency' product development. This is a next generation FPGA-based pre-trade risk system that is capable of running industry risk checks on orders as they are being generated. As a consequence, orders can be placed without incurring the latency that other forms of pre-trade risk control sustain by having to interrupt the order 'mid-flight' to check it.
We are looking for a candidate for a challenging role of FPGA developer, which involves the architecture, development, implementation and verification of RTL modules. RTL, or register transfer level, is code that can easily be synthesized from what looks like a procedural program into digital hardware.
Responsibilities:Working with software and hardware teams to build and delivery designs. RTL Development and implementation of modules for our FPGA product. Module level verification and system level verification.
Mandatory Skills:
- САМОЕ ГЛАВНОЕ: опыт разработки обработчиков TCP/UDP на ПЛИС/FPGA
- 10+ year's commercial experience in technical design, development and implementation
- RTL coding for synthesis and verification (VHDL and Verilog)
- RTL verification: testbenching, STA (Static Timing Analysis)
- SCM: subversion or Git
- Tools: Questasim (simulation), Vivado (Xilinx) and Quartus (Intel/Altera)
- Debugging on hardware: Chipscope, SignalTap
- TCP/IP and networking
- Demonstrable analytical and problem-solving ability
- Excellent verbal and written communication skills
Nice-to-Have Skills:
- System Verilog for RTL coding and testbenching
- Scripting: Tcl, Python, Perl
- Low latency design
- DMA
- Ethernet 10BASE-R
- PCIe
- UVM/OVM methodology
- Formal verification
- Continuous Integration (Jenkins)
- Financial protocols (FIX, Arrowhead, Ouch)