Position: FPGA Verification Engineer
Company: United Software
Category: C++
Experience required: 2y
English level: upper

We are looking for an excellent FPGA Verification Engineer, to Join a unique R&D FPGA team in developing next generation products.

**This role requires the following capabilities:**
- All aspects of Verification design activity:
   System Verilog Coding, simulation, Debugging, Coverage, design and lab 
   support.
- Block-level verification and Chip-level verification. developing Tests plans
- Collaborate with other teams: Design, SW, QA, system and board-design.

**Job Requirements:**
- B.Sc. degree from a University / College
- 2-5 years experience in Verification Environment development.
- Experience with System Verilog – Must. UVM knowledge – Advantage.
- Familiar with Synopsys / Cadence tools – Advantage.
- Experience with Xilinx families and tools – Advantage.
- Random direct method. Coverage driven.
- Familiar with SVA - Advantage.
- Excellent system understanding.
- High motivation.
- Team Player.

**...and of course, your benefits:**
- 20 fully paid business days of vacation.
- 15 sick leaves.
- public holidays.
- premium health insurance.
- sports club membership.
- ability to work from home or remotely.
- flexible working hours without time trackers.
- corporate events.
- office with excellent kitchen and full refrigerator 😊