Position: Silicon Verification Engineer
Company: GlobalLogic
Category: C++
Experience required: 2y
English level: intermediate

**Job Description**
- Several years of experience working in pre-silicon verification
- Working hands-on knowledge in UVM (including using SystemVerilog)
- Experience in vertical reuse verification environments (block level up to full-chip/subsystem)
- Block-level and system-level code verification experience
- Debug expertise focusing on system-level environments
- Experience with Synopsis tools and flows

**Job Responsibilities**
Be part of a team working for one of the world's largest silicon developers
participate in pre-silicon verification of next-gen products

**Department/Project Description**
This is a great opportunity for experienced Silicon Verification Engineer to get experience working with one of the largest chip companies in the world. If you always dreamed of working with cutting-edge hardware and getting to know what powers Internet of tomorrow, this job is for you!

You will be a part of the talented technical team that is now more than 50 engineers working in various domains and projects, and you will have the opportunity to grow our expertise into Silicon Verification domain.