Miracle-dz/UniFAR-FTUs huggingface dataset:
Regressing Poses from Monocular Images in an Underwater Environment

Re-localization is crucial to underwater vehicles especially for short-range missions, such as inspection and maintenance. While re-localization has been tackled successfully in the land and aerial environments, it remains to be a challenge in the underwater environment where radio communications and global positional systems are unavailable. Traditionally, underwater localization methods include dead reckoning (DR), inertial navigation systems (INS) and acoustic sensors. However, DR and INS tend to accumulate errors along time and are vulnerable to changes in water speed while acoustic sensors often require complex architectures which are expensive. Inspired by recent progress in land re-localization methods, we implemented a regression learning method, which is simple and cost-effective, for re-localization in short-range missions. The method is able to regress a 6-DOF pose from a single RGB image. We trained and evaluated the method on datasets collected from an underwater simulator. We also investigated its robustness towards changes in lighting and made improvements.
Sonnet Modelling and Simulation of Broadband Branchline Coupler

Modern communication systems need various hybrids to enable digital data transmit via microwave bands. Thus, several types of microwave quadrature hybrids have been reported for the realization of balanced circuits, matched attenuators, and phase shifters. The branch-line coupler is one of the most popular hybrids for the convenience of design and implementation. But, it offers limited bandwidth and requires a large circuit area (1). Thus, in this paper, a study and investigation of the simulation performance of subdivision of the multisectional broadband branchline coupler is to be carried out using SONNET®. The purpose is to overcome problems with regard to high memory space usage and time consumption due to large circuitry of broadband branchline coupler with the goal of increasing the bandwidth at the same time. The simulation results of the full model is to be compared to that of sub- models to evaluate potential differences in the performance and further examination would be conducted in terms of having more sections added to the broadband branchline coupler to study the multisectional branchline hybrid from performance and size point of view. The results of this study are to be reported and presented in this work.
Maximum Fast-Charging Current Estimation Algorithm Considering Temperature of Lithium-ion Batteries in Electrical Vehicles

This paper proposes a thermal modeling method and a real-time maximum fast-charging current estimation algorithm to manage the temperature of the Lithium-ion battery in electrical vehicles. The proposed modeling method has a simple structure and high accuracy by experimentally identifying the parameters with the curve fitting method. Based on the proposed model, the maximum fast-charging current is estimated in real-time by reflecting the cooling system and the ambient temperature. The feasibility of the proposed algorithm is experimentally verified through the Lithium-ion batteries manufactured for the electric vehicles.
Performance Comparison and Modelling of Instantaneous Current Sharing Amongst GaN HEMT Switch Configurations for Current Source Inverters

Power electronics converters find their applications in future means of transportation including superconducting machines (SCM), energy storage modules and cables. Such converters operate at extreme low temperatures to ensure higher power efficiencies and power densities because of reduced semiconductor losses and filter size and weight respectively. Utilizing the advantages associated with superconducting materials, current source inverters (CSI) can outweigh their counterpart voltage source inverters and can potentially be good candidates for megawatt class motors. CSIs have been shown to offer better output power quality and reduced input side conducted electromagnetic interference (EMI), hence more suitable for SCM. Since CSI needs reverse voltage blocking switches, this paper evaluates four different GaN based configurations. The paper also models the instantaneous currents between commutating branches and models the impact of parasitic components. Tests were performed onto a three phase CSI built to verify the analysis conducted. The three-phase inverter built will be operated under extreme low temperatures.
Analysis and Experimental Verification of Overvoltage Suppression in a Hybrid DC Circuit Breaker

Sequential tripping with energy balancing control in dc hybrid circuit breakers (HCBs) has shown to be an effective strategy in reducing the peak fault current and fault interruption time. However, the inevitable voltage overshoots during the tripping process need to be suppressed. Increasing turn-off gate resistance of a semiconductor switch to suppress its overvoltage is a simple method, which has been avoided in power converter applications because of its additional losses. These additional power losses, nevertheless, are not problematic in HCB applications. This paper analyzes the HCB overvoltage with respect to the switch gate resistance, and experimentally compares the performance and capability of the gate resistance method with the conventional snubber circuit solution in terms of overvoltage suppression and sequential tripping. Hardware verification corroborates the theoretical analysis and demonstrates that both methods can reduce the voltage overshoots while maintaining similar energy balancing results.
EM SCA & FI Self-Awareness and Resilience with Single On-chip Loop & ML Classifiers

Securing ICs are becoming increasingly challenging with rapid improvements in electromagnetic (EM) side-channel analysis (SCA) and fault injection (FI) attacks. In this work, we develop a pro-active approach to detect and counter these attacks by embedding a single on-chip integrated loop around a crypto core (AES-256), designed and fabricated using TSMC 65nm process. The measured results demonstrate that the proposed system 1) provides EM-Self-awareness by acting as an on-chip H-field sensor, detecting voltage/clock glitching fault-attacks; 2) senses an approaching EM probe to detect any incoming threat; and 3) can be used to induce EM noise to increase resilience against EM attacks. This work combines EM analysis, ML based secured system and shows the efficacy by measurements from custom-built 65nm CMOS IC.
Time-Effective Component Selection Automation in Electric Vehicles using Openly-Available Data

Transportation electrification is at the core of the possible solutions to many challenges the world is currently facing. Efficient vehicle electrification has the potential to si-multaneously reduce greenhouse gasses emissions and decrease range anxiety. This paper proposes a methodology for component selection in each part of electric vehicle (EV) architecture, demon-strating the method with Power Electronics switches selection. A Design Automation (DA) simulation platform is introduced to facilitate EV model-based design. The approach includes considerations on the mechanical and electrical domain of the vehicle, accounting for the effect of the component in the whole system, and yielding the solution that optimizes range. Using the proposed method, the Pareto Front of a large pool of candidates is found, yielding a range-efficiency variation of approximately 16% within it.
Blockchain-based Crowd-sensing Trust Management Mechanism for Crowd Evacuation

With the continuous urban expansion, the safety of public places has attracted more and more attention. Once an accident occurs and people distrust their surroundings, it will cause congestion, trampling and other events. Individual trust value is particularly important in crowd evacuation. However, it is very difficult to evaluate the individual credibility with existing methods. We propose a blockchain-based crowd-sensing trust management mechanism (B-CSTM) to address this problem. First, we provide a message credibility evaluation mechanism that can evaluate the credibility of messages sent by individuals on spot. Second, we developed a trust calculation method that uses a distributed Evacuation Perception Unit (EPU) to calculate individuals’ trust values by perception scores. Finally, we build a blockchain-based trust management mechanism model that uses blockchain to store and query trust values. Through experimental analysis, we visualize the trust results in the evacuation scenario. It is shown that the mechanism is feasible for the management of trust values (collection, calculation and storage, etc.) in crowd evacuation.
A Comprehensive Analysis of Current Spikes in a Split-Phase Inverter

Compared with a conventional two-level inverter, split-phase inverter decouples the top and bottom switches and antiparallel diodes in a phase leg through addition of split inductors. These split inductors prevent current shoot-through with zero deadtime operation, which lowers the distortion in the output waveforms and makes this topology ideal for fast-switching devices such as SiC or GaN. Further, decoupling between top and bottom device's output capacitance also results in lower overall switching loss and improves Electromagnetic Interference (EMI) performance. However, the split inductors experience current spikes during switching transition, which can lead to significant core loss. This paper presents a comprehensive analysis of current spikes in a split phase inverter with SPWM, characterized by the load power factor (PF). The proposed model can be used to optimize the size of split inductor. At first, the circuit of a single phase-leg with split inductors, is analyzed and a mathematical model for spike current estimation is proposed. The proposed model is verified on a SiC-based hardware prototype switching at 72 kHz. It is shown that the spike amplitude depends on the load PF as well as on the values of the split inductors and parasitic capacitances of the power semiconductors. Lastly, the proposed model is extended to the three-phase configuration.
Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections

The reliability of deep neural networks (DNNs) against hardware errors is essential as DNNs are increasingly employed in safety-critical applications such as automatic driving. Transient errors in memory, such as radiation-induced soft error, may propagate through the inference computation, resulting in unexpected output, which can adversely trigger catastrophic system failures. As a first step to tackle this problem, this paper proposes constructing a vulnerability model (VM) with a small number of fault injections to identify vulnerable model parameters in DNN. We reduce the number of bit locations for fault injection significantly and develop a flow to incrementally collect the training data, i.e., the fault injection results, for VM accuracy improvement. Experimental results show that VM can estimate vulnerabilities of all DNN model parameters only with 1/3490 computations compared with traditional fault injection-based vulnerability estimation.
LoWPAN fragment Forwarding and Recovery

Considering that 6LoWPAN packets can be as large as 2K bytes and that an 802.15. 4 frame with security will carry in the order of 80 bytes of effective payload, a packet might end up fragmented into as many as 25 fragments at the 6LoWPAN shim layer. If a single one of those fragments is lost in transmission, all fragments must be resent, further contributing to the congestion that might have caused the initial packet loss. This draft introduces a simple protocol to recover individual fragments that might be lost over multiple hops between 6LoWPAN endpoints.
Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance

Recent research has revealed that runtime bad blocks are found in the early lifespan of solid state drives. The reduction in overprovisioning space due to runtime bad blocks may well have a negative impact on performance as it weakens the chances of selecting a better victim block during garbage collection. Moreover, previous studies focused on reusing worn-out bad blocks exceeding a program/erase cycle threshold, leaving the problem of runtime bad blocks unaddressed. Based on this observation, we present a salvation scheme for runtime bad blocks. This paper reveals that these blocks can be identified when a page write fails at runtime. Furthermore, we introduce a method to salvage functioning pages from runtime bad blocks. Consequently, the loss in the overprovisioning space can be minimized even after the occurrence of runtime bad blocks. Experimental results show a 26.3% reduction in latency and a 25.6% increase in throughput compared to the baseline at a conservative bad block ratio of 0.45%. Additionally, our results confirm that almost no overhead was observed.
Architecture design of the HORSE hybrid manufacturing process control system

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Modular Switching Cell Design for High-Performance Flying Capacitor Multilevel Converter

Multilevel topologies provide an attractive alternative to two-level converters because they enable utilization of devices with lower blocking voltage and correspondingly high figure-of-merit. The flying capacitor multilevel converter (FCML) has demonstrated both very high power density and efficiency in a variety of applications. These converters are modular in design, consisting of series-connected switching cells. As such, the optimization of this unit cell provides a framework to build up high-performance FCMLs of any level count. This work presents a novel switching cell design which uses daughterboards containing a cascaded bootstrap gate drive power supply as well as isolated signaling and gate drivers, all of which can operate up to 1000 V. The motherboard layout provides extremely low commutation loop inductance of 940 pH, the best to date for this blocking voltage, through a combined parallel hybrid and electrically thin vertical design. A 300 V, 1.3 kW, 4-level FCML prototype is fabricated to validate the proposed design, which achieves > 1 kW/in3 power density and 98.3% peak efficiency.
On-line detection and measurements of tool wear for precision boring of titanium components

On-line detection and measurements of tool wear is important to assure manufacturing accuracy, enhance manufacturing efficiency, and reduce manufacturing costs. In this research, adaptive neuro-fuzzy inference systems are utilized in conjunction with features extracted from three-axis cutting force data for the on-line detection and measurements of tool wear for precision boring of titanium components. Cutting force data were measured for carbide tools during the boring of titanium parts. At the end of every boring process, the average flank wear width was measured to determine the cutting tool conditions. Measurements were accomplished with the aid of a toolmaker’s microscope. In total, 14 features were obtained from the cutting force data. Euclidean distance measure was utilized to determine which features showed the best indication of cutting tool conditions. This approach can reduce the number of features for on-line detection and measurements of tool wear for precision boring of titanium parts. The selected two most prominent features were kurtosis of longitudinal force and average of the ratio between tangential force and radial force. On-line detection of boring tool wear obtained excellent results, using a 2×2 adaptive neuro-fuzzy inference systems, of being able to predict tool conditions on-line with 100% reliability. On-line measurements of boring tool wear also produced exceedingly successful results with a minimum error for a 1×10 adaptive neuro-fuzzy inference systems of 0.87%.
Convolutional Neural Network (CNN) based Planar Inductor Evaluation and Optimization

Magnetic component as one of the most lossy and bulky components in power electronic converters has been researched on optimization through calculation, experimental and FEM simulation. However, the traditional methods are normally time-consuming or inaccurate. A novel method that combined FEM simulation and convolutional neural network (CNN) is discussed in this paper, which can predict the inductance and core loss efficiently and accurately. Experimental result shows the accuracy of CNN prediction. Based on the CNN inductor inductance and loss prediction, a novel optimization method is presented which can comprehensively and quickly provide the optimization result considering power loss and power density.
Isolated Three-Port Bidirectional DC-DC Converter for Electric Vehicle Applications

To further reduce size, weight, and cost of power converters in an electric vehicle (EV), the dc-dc converter of onboard charger (OBC) and the auxiliary power module (APM) are electrically integrated. However, a key challenge of the electrical integration is to design a power-stage topology and its control which not only achieves high power density but also achieves independent regulation of voltage at each output port. In this paper, a new, isolated, three-port, bidirectional dc-dc converter topology and its control are proposed to achieve high power density and high efficiency in integrated OBC and APM for EV applications. The operation and control of the proposed converter is explained in detail in different operating modes. Finally, the design details about a 6.6 kW experimental prototype with three-winding transformer which integrates all the resonant inductors are provided. The experimental waveforms and measured efficiencies in charging mode, discharging mode, and EV running mode have also been provided. The measured efficiency in the charging mode at $\mathrm{V}_{\text{Bus}}=400\ \mathrm{V},\ \mathrm{P}_{\text{HV}}=4.5\ \text{kW},\ \mathrm{V}_{\text{LV}}=13.8\ \mathrm{V}$, and $\mathrm{P}_{\text{LV}} =300\mathrm{W}$ is greater than 97% at all HV battery voltage levels. The measured efficiency in the discharging mode at $\mathrm{V}_{\text{Bus}}=400 \mathrm{V},\ \mathrm{P}_{\text{Bus}}=4.4\ \text{kW},\ \mathrm{V}_{\text{LV}}=13.8\ \mathrm{V}$, and $\mathrm{P}_{\text{LV}} =300\mathrm{W}$ is greater than 96.9% at all values of VHV. Also, a peak efficiency of 96.5% is achieved in EV running mode at $\mathrm{V}_{\text{HV}} =380\mathrm{V}, \mathrm{V}_{\text{LV}} =13.8\mathrm{V}$, and $\mathrm{P}_{\text{LV}} =800\mathrm{W}$.
Investigation of Suitable Areas for Integrated Multi-Trophic Culture of Kappaphycus alvarezii and Crassostrea gigas in Santa Elena-Ecuador

According to the Food and Agricultural Organization the mariculture has generated interest in recent years due to its importance in obtaining foods of high nutritional value for the growing world population. In Ecuador, the aim is to promote the diversification of the aquaculture sector, so this project goals to identify potential areas for the multi-trophic cultivation of Kappaphycus alvarezii and Crassostrea gigas, in Santa Elena – Ecuador. To enhance the production of these species spatial planning is necessary, based on the biological requirements of the organisms to be cultivated, the current legal regulations and considering possible conflicts of use. Nine environmental and socio- economic criteria were identified and obtained, making use of Geographic Information Systems (GIS) and remote sensing. Subsequently, the reclassification of these criteria was carried out based on the optimal cultivation ranges of both species, to finally continue with the Boolean superposition of layers, resulting in a map showing the areas suitable for cultivation. These results indicate that multi-criteria analysis offers an overview that is important for decision-making within integrated coastal management and spatial planning.
Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators

Hardware platforms comprise general-purpose processors and application-specific accelerators. Unlike processors, application-specific accelerators often do not have clearly specified architecture-level models/specifications (the instruction set architecture or ISA). This poses challenges to the development and verification/validation of firmware/software for these accelerators. Manually writing architecture-level models takes great effort and is error-prone. When Register-Transfer Level (RTL) designs are available, they can be a source from which to automatically derive the architecture-level models. In this work, we propose an approach for automatically generating architecture-level models for processors as well as accelerators from their RTL designs. In previous work we showed how to automatically extract the architectural state variables (ASVs) from RTL designs. (These are the state variables that are persistent across instructions.) In this work we present an algorithm for generating the update functions of the model: how the ASVs and outputs are updated by each instruction. Experiments on several processors and accelerators demonstrate that our approach can cover a wide range of hardware features and generate high-quality architecture-level models within reasonable time.
WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal Effect

Resistive random-access memory (RRAM) has shown great potential for computing in memory (CIM) to support the requirements of high memory bandwidth and low power in neuromorphic computing systems. However, the accuracy of RRAM-based neural network (NN) accelerators can degrade significantly due to the intrinsic statistical variations of the resistance of RRAM cells, as well as the negative effects of high temperatures. In this paper, we propose a subarray-based thermal-aware weight remapping and processing framework (WRAP) to map the weights of a neural network model into RRAM subarrays. Instead of dealing with each weight individually, this framework maps weights into subarrays and performs subarray-based algorithms to reduce computational complexity while maintaining accuracy under thermal impact. Experimental results demonstrate that using our framework, inference accuracy losses of four DNN models are less than 2% compared to the ideal results and 1% with compensation applied even when the surrounding temperature is around 360K.
High-Performance Class-E Quasi-Resonant Inverter for Domestic Induction Heating Applications

Induction heating has become a relevant player in household decarbonization through electrification of heating processes. Its application to cooking process, provides high performance and high efficiency appliances, with a superior user performance. This technology requires high-performance and cost-effective inverters that takes the most of the power device and converter topology. Nowadays, most of appliances uses the well-known series resonant half-bridge topology, whereas single-switch topologies are used only in low-cost low-performance applications. This paper proposes a high-performance class-e quasi-resonant inverter for modern induction heating appliances. Unlike state-of-the-art proposals, this converters achieves full output power operating range up to 3.6 kW. Consequently, it provides a high-performance cost-effective alternative to current implementations. The proposed converter is analyzed in this paper and experimentally verified using a 3.6-kW 2-load induction heating implementation.