Deep-submicron CMOS Single Photon Detectors and Quantum Effects

Quantum parasitic effects and miniaturization of Single Photon Avalanche Diodes in deep-submicron technologies have been studied in this thesis in detail. Tunneling noise and Random Telegraph Signal (RTS) noise have been the main two parasitic effects addressed comprehensively. While the fundamental equations for tunneling count rate in SPADs have been presented, the tunneling study has been performed by comparing two different topologies of SPADs on the same technology. The tunneling evaluation has been performed by implementing a new n-tub guard ring SPAD in 0.35 ? m standard CMOS technology. The NTGR SPAD has been characterized theoretically by simulations, and experiments. The tunneling noise effects have been verified in the I-V characteristics and Dark Count Rate responses of the new NTGR SPAD. While the NTGR SPAD has shown 3 % improvement in the maximum Photon Detection Probability (PDP), the timing jitter Full Width Half Maximum (FWHM) has been increased from 80 ps in p-tub guard ring SPAD to 152 ps in the NTGR SPAD. The breakdown voltage has been decreased 4.1 V due to using different doping profiles for NTGR SPAD implementation. Avalanche photoemission of the active area of NTGR SPAD demonstrated the ability for single photon detection in comparison with the other diodes, which show photoemssion in guard rings as a sign of Premature Edge Breakdown (PEB). The second parasitic effect which has been studied in this thesis was the RTS behavior of dark count rate (DCR); this is characterized as a bistability and multistability of DCR. RTS behavior of DCR has been observed in a SPAD fabricated in 0.8 ? m CMOS technology and in four proton-irradiated SPADs designed and fabricated in 0.35 ? m CMOS technology. To the best of our knowledge, this was the first time RTS behavior of DCR has been reported in SPADs in any CMOS technology. RTS characteristics have been evaluated experimentally and verified theoretically with respect to the bias and temperature. The RTS hypothesis of the fluctuations has been verified by measurements that have been in excellent agreement with the theory. The RTS behavior is expected to affect large array of SPAD detectors being used for 3D imaging applications. Demonstrating the functionality of SPADs in deep-submicron technologies has been the second main challenge of this thesis. We have demonstrated that singlephoton detectors can be fabricated in commercial deep-submicron CMOS processes. Miniaturization has been explored with the first SPAD designed and successfully tested in technologies smaller than 130nm. The proposed structures, implemented in 90nm standard CMOS technology, emerged from a systematic study aimed at miniaturization, while optimizing overall performance. The guard ring design has been the result of an extensive modeling effort aimed at constraining the multiplication region within a well-defined area where the electric field exceeds the critical value for impact ionization. By implementing different SPAD structures, we have studied the geometric trade-offs involved in the design of deep-submicron SPADs. Numerous SPADs with different arrangements of doping layers and different guard ring sizes have been implemented. Among them, as many as 45 structures were functional with a range of well-defined, reproducible breakdown voltages. The implemented structures have also been simulated and characterized. The detectors feature an octagonal multiplication region and a guard ring to prevent PEB using a standard mask set, exclusively. The proposed structure emerged from a systematic study aimed at miniaturization, while optimizing the overall performance. The devices exhibit a DCR of 8.1 kHz, a maximum PDP of 14 % at maximum excess bias. At 0.13 V of excess bias, a PDP of 9 % and a jitter of 398ps at a wavelength of 637 nm, were measured at room temperature. An afterpulsing probability of 32 % was measured at the nominal dead time. The main weak point of SPADs which have been demonstrated in this thesis in 90nm technology was the lack of isolation with the substrate, while different solutions have been proposed confining the NTGR SPAD, not to communicate with the substrate. Simulation based analysis of SPADs designed in 65nm CMOS technology has been described in the last section. The design of SPADs in 65nm technology was based on the characterization results of functional SPADs in 90nm technology. While implementation of SPADs in imaging CMOS technologies can lead to better performance due to the special layers, one of the main achievements of this thesis has been the demonstration of SPAD in a standard CMOS technology without employment of imaging doping layers. Because of the isolation issues described above, novel circuits have been implemented for the SPAD quenching and pulse detection.