Addressing Manufacturing Challenges in NoC-based ULSI Designs

Advances in manufacturing technologies enable the integration of a growing number of transistors on a single chip, devoted mainly to increase the number of cores and cache memory. As the number of cores increases, the communication infrastructure becomes critical. In this context, networks on chip (NoCs) have been chosen as the interconnect choice for current and future Multiprocessor System-on-Chip (MPSoCs) and Chip Multiprocessor (CMPs) systems. The main benefits of NoC-based architectures are higher performance and predictability than previous bus-based designs and larger scalability than crossbar-based designs. Unfortunately, the same large integration scales that allow to include a high number of components in the same die are also compromising the reliability of designs. In this context process variations arise as one of the main challenges to be faced by designers, and is likely to be the most important source of unreliability for technologies below 45nm. In the context of CMPs and MPSoCs, manufacturing faults may appear in the form of defective cores, memories, links, or switches. For example, due to the small feature size dopant fluctuations or lens aberrations may cause circuits to completely malfunction or to present different behaviour than the expected one. Our efforts in this dissertation have been first focused on the development of a detailed process, voltage, and temperature (PVT) variability model that improves the current state-of-art modeling of process variations in the computer architecture community. By leveraging the model developed in this thesis the impact of process variations in different NoC-based designs has been characterized. Results of the analysis of different NoC designs reveal that on one hand, systematic variations considerably impact both NoC and processor performance. As a consequence of systematic variations the maximum achievable frequency of CMP components varies considerably across the chip surface. In this sense, systematic variations cause, if ignored, both the reduction of NoC performance and the inefficient utilization of CMP resources. On the other hand, random variations severely impact the performance of NoC links for technologies below 32nm. In addition, higher defect density levels are expected for smaller technologies causing the probability of having faulty wires in NoC links to increase. In this context, efficient variability-aware and fault-tolerant NoC link architectures are required. In this dissertation we propose to face the impact of systematic variations in the energy and performance of CMPs by means of a variation-aware mapping policy. The proposed mapping policy efficiently schedules applications in CMP systems under process variations. In this proposal, performance is achieved by first considering fast CMP regions and efficiency is provided by choosing regions presenting uniform frequencies. The goal of this mapping strategy is avoiding to map threads to regions where routers and cores present very different speeds, as this would cause both an inefficient utilization of resources and the induction of communication bottlenecks in the NoC. In order to mitigate the impact of random variations and the presence of defective wires in NoC links, a variable phit-size NoC architecture is proposed in this dissertation. The proposed fault-tolerant NoC architecture addresses the impact of both manufacturing defects and random variations in NoC links by performing a suitable reduction of phit size at network interfaces. By leveraging the variable phit size NoC architecture, the link bandwidth retrieved is maximized. Finally, in this thesis a novel area-efficient vertical link design is also presented. The proposed fault-tolerant vertical link design is able to noticeably increase the yield of three dimensional Integrated Circuits (3DICs) while keeping performance and minimizing the amount of required resources. Actually, our new proposal significantly reduces the amount of Through-Silicon-Vias (TSVs) per link without reducing performance. In comparison with a conventional N-wide vertical link, our proposal requires N/2 + m TSVs, where m is significantly smaller than N/2 (m is usually one or two TSVs). Thus, deploying our proposal reports noticeable area savings.