Study and integration of 3D resistive memories for high density application

The scope of the thesis was to characterize and help further development of the first LETI-fabricated vertical resistive RAM (VRRAM). Among emerging memories Resistive RAMs (ReRAM) seems promising in terms of scalability, switching speed, fabrication costs and ease of production. As in the case of FLASH devices, which are attaining their physical limits in terms of scalability, resistive memories are already being studied in vertical geometry in order to propose solutions that maximize memory density. This work proceeded as follows: at first 1 Resistor (1R) devices were characterized to gain a general understanding of the memory cells functioning and to perform the first screening in terms of stack composition and thicknesses. Once the best configurations were identified 1 Transistor- 1 Resistor (1T-1R) devices were integrated in order to assess memory performances in an industrial-like fashion. 1R devices were integrated in a MESA structure while 1T-1R devices were integrated in both MESA and VIA architectures. In both architectures the memory cell is found on the sidewall of the structure; particularly challenging was the deposition of the top electrode. Devices were electrically characterized to extract the following information: initial resistance, forming, set and reset voltages, switching times, high and low resistance states (HRS and LRS) resistances, endurance characteristics and data retention times. This set of measurements allowed to extensively study the capability of VRRAM as a non-volatile memory candidate. It was shown that HfO2-based VRRAM have 107 endurance capability for a set current (ISET) of 300 [µA], more than 105 [s] data retention for a SET current of 100 [µA] at 200 [˚C] backing temperature and down to 20 [ns] switching time. ISET was also reduced down to 7 [µA] and memory cell showed switching capability although the conductive filament (CF) resulted unstable after data retention tests. Experimental results obtained were in accordance with previous studies conducted on planar devices showing that vertical geometry did not have a significant effect on memory behavior. Finally 2-level memory devices were fabricated. These samples were really useful to perform important tests for future high density integration: the 2 level devices were compared in terms of switching voltages and resistances to verify the reproducibility of the integration along the sidewall of the structure. Disturb tests were carried out to be sure that write/erase operations on one level did not influence the state of the un-selected level. Another part of the thesis was dedicated to the physical investigation of the conducting filament behavior during cycling. This study showed that a correlation exists among resistances while cycling. In order to explain these measurements both analytical and physical models were proposed. Both rely on the assumption that there is a parameter during cycling that is related to its previous values; in the case of the analytical model this parameter is simply the resistance while in the physical model the parameter is the CF gap (LGAP). Both models show good fit with experimental data suggesting therefore that at any given cycle the morphology of the conductive filament is dependent on the morphology during the previous cycles. Another part of the thesis was also dedicated to a study on high density applications:starting from the electrical results obtained on 2-level VRRAM and supposing to work with an integrated selector the maximum array size attainable was calculated as a function of various parameters such as the node half pitch, the plane thicknesses and the number of integrated levels. Finally neuromorphic applications were investigated and a VRRAM pillar was proposed as a synapse emulator. VRRAMs can act as synapses in two ways: using the intrinsic probability of the ReRAM technology or programming each VRRAM cell in the pillar with a probability given from an external circuit.