Reconfigurable and self-optimizing multicore architectures

For the last 30 years, the microprocessor industry has relied on instruction-level parallelism (ILP) and aggressive clock scaling to translate Moore's Law into exponential performance growth. Over this time frame, system performance has increased by a factor of 10, 000, enabling novel software applications and capabilities beyond the reach of earlier hardware platforms. Due to mounting challenges in power dissipation and system complexity, however, this long-standing approach to microprocessor performance scaling is no longer practical. The industry's initial response to the end of uniprocessor performance scaling is a paradigm shift towards Chip Multiprocessors (CMPs). Although a general consensus exists on the power, performance, and complexity advantages of CMPs, the way these systems will meet the intrinsically diverse requirements of the software products that will be running on them is much less clear. Both the initial adoption and the longevity of CMPs hinges on their ability to embrace a diverse and dynamically changing software eco-system, consisting of software products with very different characteristics and in different stages of development. Unfortunately, this stands in sharp contrast to the rigid nature of existing CMP architectures, which are typically focussed on optimizing average or worst-case performance, and are statically tuned to perform well over a relatively narrow class of applications. This dissertation addresses the design of next-generation, flexible, efficient, and self-optimizing CMP architectures. Our work is structured in two phases. The first phase addresses flexibility in the execution substrate in terms of per-core performance and core count, a critical capability that is absent from existing CMP architectures. We propose core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at runtime by applications. Core fusion gracefully accommodates software diversity and incremental parallelization in CMPs. It provides a single execution model across all configurations, requires no additional programming effort or specialized compiler support, maintains ISA compatibility, and leverages mature micro-architecture technology. The second phase of our work addresses flexibility and sophistication in the architectural control policies that manage scarce system resources. Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance CMP platforms. Conventional memory controllers deliver relatively low performance in part because they often employ fixed, rigid access scheduling policies designed for average-case application behavior. As a result, they cannot learn and optimize the long-term performance impact of their scheduling decisions, and cannot adapt their scheduling policies to dynamic workload behavior. We propose a new, self-optimizing memory controller design that operates using the principles of reinforcement learning (RL) to overcome these limitations. Our RL-based memory controller observes the system state and estimates the long-term performance impact of each action it can take. In this way, the controller learns to optimize its scheduling policy on the fly to maximize long-term performance. Our results show that an RL-based memory controller improves the performance of a set of parallel applications run on a 4-core CMP by 19% on average (up to 33 %) compared to a state-of-the-art controller.