Effective Low Power Testing strategy with respect to Built in Self-Test ( BIST ) : A Survey

Low-power VLSI circuits are indispensable for modern electronic devices, and numerous hardware/softwarebased techniques have been developed for drastically reducing functional power dissipation. However, testing such low-power devices has increasingly become a severe challenge, especially in at-speed scan testing. The reason is that functional constraints with respect to circuit operations and clocking are mostly ignored in at-speed scan testing, which may result in test power that is 3X to 8X higher than functional power. This paper presents different low power techniques which can be applied to reducing the test power of Built in Self Test (BIST) circuits used for various digital IC’s. I.INTRODUCTION The device density and the operating frequency were low enough in the past that power dissipation was not a constraining factor in VLSI chips. Nowadays, increased device density, speed and complexity have increased the power dissipation of the chip. The continuous demands from the user to expand the functionality of portable devices, without affecting the key product features, imposes tight constraints on the design technology with power optimization as its focal point . The amount of heat generated also limits the density of a chip. This power dissipated is contributed both by the actual power consumed by the circuit during normal operation and also by the test power. Test power is the power consumed by the circuit during testing. The dynamic power is mainly due to the switching activities of the circuit which may be attributed to the switching transient current and the charging and discharging of load capacitances during switching from one logic level to another level in the signal lines of the circuit. By reducing the dynamic power, majority of power saving can be obtained. As a result, lot of low power design techniques has been proposed at all levels of design hierarchy, with majority of these methods focusing on power dissipation in normal mode rather than in the test mode. II LOW-POWER TEST A high density system like ASIC or SoC always demands the nondestructive test which satisfies all the power constraints defined during design phase. On the other way, the current testing philosophy demands much more power consumption during test compared to power consumption during functional m ode. This section describes the reasons and effects of such high-power consumption. A. Reasons of High-Power Consumption during Test. There are several reasons for this increased test power. Out of them, the main reasons are as follows. (i) The test efficiency has been shown to have a high correlation with the toggle rate; hence, in the test mode, the switching activity of all nodes is often several times higher than the activity during normal operations. (ii) In an SoC, parallel testing is frequently employed to reduce the test application time, which may result in excessive energy and power dissipation. (iii) The design-for-testability circuitry embedded in a circuit to reduce the test complexity is often idle during normal operations but may be intensively used in the test mode. (iv) That successive functional input vectors applied to a given circuit during system mode have a significant correlation, while the correlation between consecutive test patterns can be very low. This can cause significantly larger switching activity and hence power dissipation in the circuit during test than that during its normal operation [3]. B. Effects of High-Power Dissipations. The most adverse effect of very high-power dissipation during test is the destruction of IC itself. In addition, to prevent the IC from destruction, the power dissipation during test can affect the cost, reliability, autonomy, performance-verification, and yield-related issues [4]. Some of the effects are as Asian Journal of Convergence in Technology Volume III, Issue II ISSN No.:2350-1146, I.F-2.71 www.asianssr. org ID: 518 follows. (i) The growing need of at-speed testing can be constrained because of the high-power dissipation. So stuck at faults can be tested without any effect, but the testing of the delay fault will become difficult. (ii) During functional testing of the die just after wafer etching, the unpackaged bare die has very little provision for power or heat dissipation. This might be a problem for applications based on multichip module technology, for example, in which designers cannot realize the potential advantages in circuit density and performance without access to fully tested bare dies [5]. (iii) Circuit can be failed because of erosion of conductors caused by electro migration. (iv) The online BIST in battery-operated remotes and portable systems consumes very high power for testing only. Remote system operation occurs mostly in standby mode with almost no power consumption, interrupted by periodic self-tests. Hence, power savings during test mode directly prolong battery lifetime. (v) The elevated temperature and excessive current density severely decrease circuit reliability. (vi) Because of excessive power dissipation, the simple low-cost plastic packages used in consumer electronics cannot be used, but expensive packages which can remove the excessive heat are forced to be used. III LOW POWER TECHNIQUES A. Low-Power Test Pattern Generation Test pattern generation is main part of testing circuits by which switching activity can be decreased. Power can be reduce during testing by low power test compaction, low power X-filling, and test vector ordering. [1] With the help of this technique two problems, like circuit overheat and performance degradation can be overcome. B. Low power test compaction The requirement of compaction is to reduce number of test vectors. Test cube can be exploited using test compaction, test cubes are the test vector containing unspecified bits or Xbits. Test data compaction can be done as dynamic compaction and static compaction. Dynamic compaction specifies the Xbits in a test cube in order to detect more faults than the initially targeted fault, while static compaction uses the X-bits in compatible test cubes to merge them into one test cube. [3]