Miracle-dz/UniFAR-FTUs huggingface dataset:
Radip light-induced phosphorylation changes in microtubule related proteins in arabidopsis

Rapid hypocotyl elongation allows buried seedlings to reach the surface, where light triggers de-etiolation and inhibits hypocotyl growth mainly by phytochromes A, B and cryptochromes 1, 2. Dynamic phosphorylation/dephosphorylation events provide a mechanism to rapidly transduce light signals. Only recently we have begun to uncover the earliest phospho-signaling responders to light. Here, we report a large-scale phosphoproteomic analysis and identify 20 proteins that change their phosphorylation pattern after 20 min of white light pulse compared to darkness. Microtubule-associated proteins (MAPs) were highly overrepresented in this group. Among them, we studied CIP7 (COP1-INTERACTING-PROTEIN-7), which presented microtubule (MT) localization, in contrast to what was previously described. Phosphorylated isoform in Serine 915 (Sp915) of CIP7 was detected in etiolated seedlings but undetectable after a light pulse in the presence of photoreceptors, while its expression decays with long light exposure. The short hypocotyl phenotype and rearrangement of MTs in etiolated cip7 mutants are complemented by CIP7-YFP and the phospho-mimetic CIP7S915D-YFP, but not the phospho-null CIP7S915A-YFP suggesting that Sp915CIP7 is the active isoform that promotes hypocotyl elongation thorough MT reorganisation in darkness. Our results reveal that the small repertory of proteins that changes the phosphorylation status after a rapid light signal is tightly focused on MAPs; suggesting that phospho-regulation of microtubule-base processes are early targets during de-etiolation. The evidence on Sp915CIP7 supports this idea.
Gene expression QTL mapping in stimulated iPSC-derived macrophages provides insights into common complex diseases

Many disease-associated variants are thought to be regulatory but are not present in existing catalogues of expression quantitative trait loci (eQTL). We hypothesise that these variants may regulate expression in specific biological contexts, such as stimulated immune cells. Here, we used human iPSC-derived macrophages to map eQTLs across 24 cellular conditions. We found that 76% of eQTLs detected in at least one stimulated condition were also found in naive cells. The percentage of response eQTLs (reQTLs) varied widely across conditions (3.7% - 28.4%), with reQTLs specific to a single condition being rare (1.11%). Despite their relative rarity, reQTLs were overrepresented among disease-colocalizing eQTLs. We nominated an additional 21.7% of disease effector genes at GWAS loci via colocalization of reQTLs, with 38.6% of these not found in the Genotype–Tissue Expression (GTEx) catalogue. Our study highlights the diversity of genetic effects on expression and demonstrates how condition-specific regulatory variation can enhance our understanding of common disease risk alleles.
Identification of Inverse Dynamics Model Based on Support Vector Machine and Its Application

To research the control problem of nonlinear system, it is a crucial problem to establish its inverse dynamic model. The on-line identification for inverse dynamics of thermal object based on support vector machine (SVM) was realized, and the validity of inverse dynamic model of nonlinear system based on SVM was proved according to three typical simulation examples. The result shows that the inverse dynamic model based on support vector machine has not only upper identification precision, but also quite perfect generalization and traceable ability. The right control can be acquired that ensures the output of model to achieve the setting value according scheduled track by utilizing the identification model of inverse dynamics of system.
Progress in large eddy simulation of turbulent flows

The paper introduces the principles of LES for turbulence and its advantage. Authors focuses on the existing problems in LES and the way of their solution, such as the filters, subgrid modeling, near-wall models and scalar turbulence. The communicative error of inhomogeneous filter is mentioned and the method of its reduction is recommended. (Existing) subgrid models are introduced with evaluation of their feasibility. The importance of near-wall model in LES for wall-bounded flows with large Reynolds number is mentioned; and algebraic model and wall boundary layer model are introduced with experimental and numerical comparison. The problem of scalar turbulence is put forward in the paper that the mass transportation of scalar turbulence strongly depends on the molecular diffusivity at fixed Reynolds number when the ratio of molecular viscosity to molecular diffusivity, Prandtl number for instance, is less than 1. The authors emphasize that the turbulent transportation between resolved and unresolved turbulence in LES is the fundamental mechanism of subgrid stress and subgrid scalar flux, hence inclusion of correct transportation mechanism in modeling is the proper way of establishing subgrid model. The authors propose a new subgrid stress model based on the Kolmogorov equation for resolved turbulence, in which the mass or momentum transportation between resolved and unresolved turbulence is included. The new model is tested in both isotropic and shear turbulence. The predicted statistical properties in a turbulent channel flow are in good agreement with DNS results up to Re=590.
Numerical simulations of parameters inversion for multi-component solutes transportation

A mathematical model was discussed for multi-component solutes transport in porous medium dominated by sulfate.Since the model parameters could not be measured directly,an inverse problem of determining model parameters was put forward,and numerical inversions for a real life example of multi-component solutes transport under different conditions were carried out by applying an optimal perturbation iteration algorithm.The computational inversion results show that the optimal perturbation iterative algorithm used in this paper is effective at least to the inverse problem of multi-parameter identification arising in a group of partial differential equations.
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing

Optical Probing (OP) has been shown to be capable of retrieving intellectual property of the chips. However, to design a robust circuit against OP, the chip must be designed, fabricated, and optically probed in an experimental setup to determine the OP robustness of the design which is time consuming. To mitigate the aforementioned problems, we propose a simulation framework, namely FELOPi, which takes the layout file format of a design as an input and then performs OP on it. FELOPi can help designers to design robust circuits toward OP attacks before fabricating the chip. Hence, utilizing FELOPi results in tremendous time and cost reduction.
ConfigDroid: Configuration-aware GUI testing of Android Applications

Android applications (a.k.a., Android apps) have developed rapidly in the last decade, and have become an indispensable part in people's lives. However, it is challenging to guarantee their quality and reliability. The prevalence and severity of Android apps issues have driven the design and development of a number of detection and testing techniques. However, these techniques mainly target the generation of test sequences using GUI events in the applications, lacking of attentions to complex Android system configurations. In this paper, we conducted an in-depth study on real-world Android bugs related with configurations from 20 open-source popular Android applications, to help understand the characteristics of these bugs. We find the majority of configurations-related Android bugs would lead to catastrophic consequences, e.g., crash and hang. Based on the study, we design and implement ConfigDroid, a tool for configuration-aware GUI testing of Android applications. We use 10 open-source popular Android applications to evaluate the effectiveness. The result shows that, ConfigDroid can detect 4 more unique configuration-related crashes than state-of-the-art tools, Monkey and Stoat.
AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips

Digital microfluidic biochips exploit the electrowet-ting on dielectric effect to move and manipulate microliter-sized liquid droplets on a planar surface. This technology has the potential to automate and miniaturize biochemical processes, but reliability is often an issue. The droplets may get temporarily stuck or gas bubbles may impede their movement leading to a disruption of the process being executed. However, if the position and size of the droplets and bubbles are known at run-time, these undesired effects can be easily mitigated by the biochip control system. This paper presents an AI-based computer vision solution for real-time detection of droplets and bubbles in DMF biochips and its implementation that supports cloud-based deployment. The detection is based on the YOLOv5 framework in combination with custom pre and post-processing techniques. The YOLOv5 neural network is trained using our own data set consisting of 5115 images. The solution is able to detect droplets and bubbles with real-time speed and high accuracy and to differentiate between them even in the extreme case where bubbles coexist with transparent droplets.
Architecture Research of Novel Digital Intelligent Substation System

This paper, taking substation as an example, studies the novel digital intelligent substation system. Firstly, the concept of this substation system is proposed, and its construction objective is introduced. Furthermore, its functional framework is clarified, and the four core characteristics of intelligent brain are pointed out, thus providing the guiding ideology for the application of top-level intelligent business in substation. Finally, the application prospect of the novel digital intelligent substation system is discussed, which provides a reference research idea for the further development of this professional field.
Proteus : HLS-based NoC Generator and Simulator

Networks-on-chip (NoCs) form the backbone fabric for connecting multi-core SoCs containing several processor cores and memories. Design-space exploration (DSE) of NoCs is a crucial part of the SoC design process to ensure that it does not become a bottleneck. DSE today is often hindered by the inherent trade-off between software simulation vs hardware emulation/e- valuation. Software simulators are easily extendable and allow for the evaluation of new ideas but are not able to capture the hardware complexity. Meanwhile, RTL development is known to be time-consuming. This has forced DSE to use simulators followed by RTL development, evaluation and feedback, which slows down the overall design process. In an effort to tackle this problem, we present Proteus, a configurable and modular NoC simulator and RTL generator. Proteus is the first of its kind framework to use HLS compiler to develop NoCs from a C++ description of the N oC circuit. These generated N oCs can be simulated in software and tested on FPGAs. This allows users to do rapid DSE by providing the opportunity to tweak and test NoC architectures in real-time. We also compare Proteus-generated RTL with Chisel- generated and hand-written RTL in terms of area, timing and productivity. The ability to synthesize the NoC design on FPGAs can benefit large designs as the custom hardware results in faster run-time than cycle-accurate software simulators. Proteus is modeled similar to existing state-of-the-art simulators and offers users modifiable parameters to generate custom topologies, routing algorithms, and router microarchitectures.
Extreme value theory in engineering

Introduction and Motivation. Order Statistics. Asymptotic Distributions of Maxima and Minima (I.D. Case). Shortcut Procedures: Probability Papers and Least-Square Methods. The Gumbel, Weibull, and Frechet Distributions. Selection of Limit Distributions from Data. Limit Distributions of K-TH Order Statistics. Limit Distributions in the Case of Dependence. Multivariate and Regression Models Related to Extremes. Multivariate Extremes. Appendixes.
Detection of Diabetic Retinopathy Image Analysis using Convolution Graph Neural Network

Diabetic retinopathy is caused by high blood sugar levels, which damage and obstruct the small blood vessels in the retina. The eye creates new blood vessels to make up for the diminished blood flow. These don't work properly and result in blood loss, which impairs eyesight. 1) A vascular hemorrhage might occur if diabetes is not treated and blood sugar levels are not under control. 2) Retinal separation 3) glaucoma-induced blindness. Expertise and technology are generally scarce in areas where the diagnosis of diabetic retinopathy is most important. The majority of research in the field of diabetic retinopathy has been concentrated on disease detection or manually extracting features, but this study hopes to apply deep learning to automatically diagnose the condition in its many stages. This study focuses on the automated identification and categorization of diabetic retinopathy symptoms using a pre-trained convolutional graph neural network (CGNN). A collection of retinal images are used from the eyepacs diabetic retinopathy database. , which was categorized into five groups based on the severity of retinal damage. Images from this database were preprocessed and utilized as training and testing data. In addition to being more effective and accurate than manual tests, this method of DR detection also conserves time and money. The transfer learning paradigm used by Alexnet incorporates CGNN technology. In this study, accuracy above 90% is predicted and also plotted the confusion matrix and ROC curve using Matlab.
ML and DL Classifications of Route Conditions Using Accelerometers and Gyroscope Sensors

The Modern Era has undergone vast transformations in terms of automation in a wide array of industrial applications. The Artificial Intelligence platform has revolutionized our daily lives with the advent of Intelligent systems. The usefulness of AI in Road Mapping and Route Classification is demonstrated in our study where an Intelligent Transport System (ITS) is proposed which enables monitoring and classification of road conditions by implementing Machine Learning (ML) and Deep Learning (DL) algorithms on data recorded by cellular accelerometer, gyroscope, and GPS sensors. Field Data was recorded in two different scenarios on different vehicles. The route mapping was performed by plotting latitude and longitudes on Google Earth. The labelling of different classes of road was done manually with correlation done via video camera recording. Road Terrain was classified into Bumps. Potholes, Rough and Smooth Roads. Six classical Supervised Machine Learning models (K Neighbors Classifier, Decision Tree Classifier, Random Forest Classifier, Support Vector Classifier, Gaussian Naive Bayes Model and Logistic Regression Model) were implemented. Furthermore, Ensembler classifier was used on all six classifiers. The selection of an Optimum Classification Model is done via Soft Voting Algorithm. Finally, K-Fold cross validation was performed to determine the accuracy of our trained model.
A Compact Elliptically Slotted Multiband Antenna for Wireless Applications

A novel elliptical shaped slotted antenna for multiband applications is proposed. The antenna has a 50 Ω microstrip line, a partial ground, and an elliptically slotted structured patch. The size of the radiator is 14×23 mm2 that provides a triple band -10 dB impedance bandwidth of 3.2-3.5 GHz, 8.6-12.6 GHz, and 13.9-15.4 GHz for WiMAX, X-band satellite communications and Ku band applications, respectively. The suggested radiator is appropriate for WiMAX, X, and Ku multi band applications owing to its excellent agreement between the simulated and experimental S11, omni directional radiation patterns, and peak radiation efficiency of 93.28%.
Low-Noise Amplifier Design: An Open-Source Perspective

LNA stands for Low-Noise Amplifier.It is an integral part of the receiver chain in any RF system. The LNA is the first in a long chain of devices in the receiver chain however it also has the most impact on the sensitivity as well as the overall performance of the subsequent stages of the receiver. LNA design for RFIC has a lot of trade-offs that need to be made in order to achieve good performance both in terms of noise Figure and gain. The cascode topology is selected as the main focus for this brief. It is basically a two-stage amplifier that is built around a Commongate and Common-Source stages. The cascode LNA topology with inductive degeneration is best able to circumnavigate the hurdles posed in 5G or other wide-band RF technologies. It is able to balance good gain flatness with respectable noise Figure over a wide range of frequency spectrum while providing good impedance matching and reverse isolation. A three-stage Cascode LNA built using Advanced Spice Model for High Electron Mobility Transistor (ASM-HEMT) using Cadence Virtuoso is initially implemented. Its performance analysis using simulation results is done. This work also discusses the design of a cascode low-noise amplifier (LNA) using completely open-source tools namely Xschem and Magic among others. The design environment setup is also discussed in detail. The technology used to realize the circuitry is Google Skywater130.
Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT Devices

Firmware update is an essential service on Internet-of-Things (IoT) devices to fix vulnerabilities and add new functionalities. Firmware update is energy-consuming since it involves intensive flash erase/write operations. Nowadays, IoT devices are increasingly powered by energy harvesting. As the energy output of the harvesters on IoT devices is typically tiny and unstable, a firmware update will likely experience power failures during its progress and fail to complete. This paper presents an approach to increase the success rate of firmware update on energy-harvesting IoT devices. The main idea is to first conduct a lightweight flash write with reduced erase/write time (and thus less energy consumed) to quickly save the new firmware image to flash memory before a power failure occurs. To ensure a long data retention time, a reinforcement step follows to re-write the new firmware image on the flash with default erase/write configuration when the system is not busy and has free energy. Experiments conducted with different energy scenarios show that our approach can significantly increase the success rate and the efficiency of firmware update on energy-harvesting IoT devices.
A Hybrid Neural Network Based on Bayesian Optimization for Non-Intrusive Load Disaggregation

Non-intrusive load disaggregation is an important technology for the smart grid to realize demand-side refinement management. Non-intrusive load disaggregation refers to the decomposition of the operating power of a single appliance from the total power. Considering the strong correlation of household loads in time series, a hybrid neural network load disaggregation method based on Bayesian optimization is proposed in this paper. The hybrid neural network is used to extract features in power sequences and Bayesian optimization is used to find a set of hyperparameter combinations suitable for hybrid neural networks. The method extracts deeper information, obtains a more flexible perceptual field, and improves the performance of the model. Finally, the constructed algorithm has experimented on the public dataset UK-DALE. The experimental results show that the MAE and F1 evaluation metrics are improved by 18.4% and 8.1%, respectively, which proves the superiority of the method in this paper.
Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing

With the ubiquitous IoT sensors and enormous real-time data generation, data privacy is becoming a critical societal concern. State-of-the-art privacy protection methods all demand significant hardware overhead due to computation-insensitive algorithms and divided sensor/security architecture. In this paper, we propose a generic time-domain circuit architecture that protects raw data by enabling a differentially-private compressed sensing (DP-CS) algorithm secured by physical unclonable functions (PUF). To address privacy concerns and hardware overhead at the same time, a robust unified PUF and time-domain mixed-signal (TD-MS) module are designed, where PUF enables private and secure entropy generation. To evaluate the proposed design against a digital baseline, we performed experiments based on synthesized circuits and SPICE simulation and measured a 2.9x area reduction and 3.2x energy gains. We also measured high-quality PUF generation with TD-MS circuit with a inter-die Hamming distance of 52% and a low intra-die Hamming distance of 2.8%. Furthermore, we performed attack and algorithm performance measurements demonstrating the proposed design preserves data privacy even under attack, and the machine learning performance has minimal degradation (within 2%) compared to the digital baseline.
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips

The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in $\mathbf{33D}$ stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1) $\mathbf{100x}$ performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2) $\mathbf{50x}$ processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.
Algorithm based Digital Twinning for different stages of Microelectronic Manufacturing Cycle

The emerging globalization trend in the silicon manufacturing cycle has added vulnerabilities in production at different stages. Time-to-market requirements make the manufacturing process even more challenging. Digital twinning is one such recent method that can be used to model real things through input data sets. This technique mimics the real manufacturing process with the help of input data sets. The mentioned proposed framework introduces the use of algorithms with digital twinning for semiconductor manufacturing environments after taking all specified and interesting requirements and possible vulnerabilities in terms of feasible solutions and security liabilities into account, directly mimicking real design as it is through simulation upgrade digital twinning with algorithms at different stages of development and can ease learning and feedback to improve the performance of the manufacturing process. Usually, the silicon production cycle includes interpretation of ai artificial intelligence framework with formulations. These functions of objects are formed after expert analysis to enhance these models, algorithmic approaches can be used. This framework directs potential research possibilities in using DT (Digital Twins) for different stages of silicon manufacturing using Algorithms.