Miracle-dz/UniFAR-FTUs huggingface dataset:
A Robust Super-Regenerative Receiver with Optimal Detection on BER Level

This paper presents a robust super-regenerative receiver (SRR), which is insensitive to the temperature variations. A constant-alpha biasing circuit is proposed to make the start-up oscillation and start-up time of the VCO immune from temperature drifts. The prototype chip is measured in the range of −20 degrees to 90 degrees (Celsius) to verify this functionality of the constant-alpha biasing circuit. Besides, another new perspective on the detection level is proposed to derive the lowest BER. This SRR is fabricated in UMC standard $0.18\mu\mathrm{m}$ CMOS process, and the chip area is $1.65\text{mm}\times 1.45\text{mm}$.
A Subthreshold-Inverter-Based Strong PUF with High Reliability and Energy Efficiency

In this paper, we present an energy-efficient strong physical unclonable function (PUF) based on subthreshold inverters (STIs) that are regulated by a native NMOS transistor. Two groups of STIs can be dynamically regrouped to 4 stages according to the provided challenge, with each stage having different number of STIs connected in parallel. By adopting the first two stages as the entropy source and the last two stages for generating the PUF bits, the equivalent 4-stage STI chain can exhibit high reliability under largely varied temperature and supply voltage. Moreover, the proposed strong PUF implementation is validated using a standard 65-nm 1.2 V CMOS process. With the temperature and supply voltage changing from 0°C to 120°C and 0.7 V to 1.5 V, respectively, the worst-case bit error rate (BER) is reported to be 5.025%. Meanwhile, the energy consumption is simulated to be 0.26 pJ/bit at the maximum throughput of 10 Mb/s. Moreover, the proposed strong PUF shows high resilience to various machine learning (ML) attacks, including logistic regression, support vector machine and covariance matrix adaptation evolution strategy.
Analysis of Machine Learning and Deep Learning to Forecast Prices on Several Crypto Exchanges

These days, virtual currencies-the term used to describe cryptocurrencies-are more well-known and have aroused the interest of numerous people. As a result of using blockchain technology, which decentralizes banking, daily cryptocurrency trading has become quite popular among observers, investors, customers, and many other groups. However, due to the daily fluctuations in the value of cryptocurrencies, prediction techniques enable stakeholders to look into the future and identify potential threats to their crucial investment operations. The increasing popularity of cryptocurrencies has made price predictions more promising for investors along with researchers. As artificial intelligence (AI) has advanced to such a level, forecasting the price of cryptocurrencies has grown in significance. In this study, we develop an approach based on machine learning and deep learning as a form of AI to forecast the price of various cryptocurrency exchanges, such as Bitcoin (BTC), Ethereum (ETH), BinanceCoin (BNB), and FTX (FTT), based on their various pricing points. The results from the machine learning models demonstrated that linear regression performed better in forecasting all types of cryptocurrency, with a maximum R2 score of 0.9477, 0.9232, 0.9204, and 0.8925 for BTC, ETH, BNB, and FTT, respectively. However, our study found that the Gated Recurrent Unit (GRU), a deep learning-based model, was the most effective algorithm for predicting the prices of all four types of cryptocurrencies. With GRU, we were able to predict the price of ETH with an R2 score as high as 0.9983, and we were also able to predict the prices of BTC, BNB, and FTT with R2 scores of 0.9969, 0.9772, and 0.9873, respectively. The proposed approach demonstrated superior results with minimal prediction errors on estimating the price of all the different crypto exchanges when the outcomes of our research were dealt with those of the existing studies.
Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications

Reconfigurable nanotechnologies such as Silicon Nanowire Field Effect Transistors (FETs) serve as a promising technology that not only facilitates lower power consumption but also supports multi-functionality through reconfigurability. It enables reconfigurability and supports multiple functionalities per computational unit. These features motivate us to design a novel state-of-the-art energy-efficient hardware accelerator for implementing memory-intensive applications including convolutional neural networks (CNNs) and deep neural networks (DNNs). To accelerate the computations, we design Multiply and Accumulate (MAC) units to perform the computations. For the design of MACs, we employ Silicon nanowire reconfigurable FETs (RFETs). The use of RFETs leads to nearly 70% power reduction compared to the traditional CMOS implementation and also reduced latency in performing the computations. Further to optimize the overheads and improve memory efficiency, we introduce a novel approximation technique for RFETs. The RFET-based approximate adders lead to reduced power, area, and delay while having a minimal impact on the accuracy of the DNN/CNN. In addition, we carry out a detailed study of varied combinations of architectures involving CMOS, RFETs, accurate adders, and approximate adders to demonstrate the benefits of the proposed RFET-based approximate acclerator. The proposed RFET-based accelerator achieves an accuracy of 94% on MNIST datasets with 93% and 73%reduction in the area, power and delay metrics respectively compared to the state-of-the-art hardware accelerator architectures.
Detecting Eating and Social Presence with All Day Wearable RGB-T

Social presence has been known to impact eating behavior among people with obesity; however, the dual study of eating behavior and social presence in real-world settings is challenging due to the inability to reliably confirm the co-occurrence of these important factors. High-resolution video cameras can detect timing while providing visual confirmation of behavior; however, their potential to capture all-day behavior is limited by short battery lifetime and lack of autonomy in detection. Low-resolution infrared (IR) sensors have shown promise in automating human behavior detection; however, it is unknown if IR sensors contribute to behavior detection when combined with RGB cameras. To address these challenges, we designed and deployed a low-power, and low-resolution RGB video camera, in conjunction with a low-resolution IR sensor, to test a learned model's ability to detect eating and social presence. We evaluated our system in the wild with 10 participants with obesity; our models displayed slight improvement when detecting eating (5%) and significant improvement when detecting social presence (44%) compared with using a video-only approach. We analyzed device failure scenarios and their implications for future wearable camera design and machine learning pipelines. Lastly, we provide guidance for future studies using low-cost RGB and IR sensors to validate human behavior with context.
Revolutionizing Collectibles Trading with Youtooz’s Blockchain-Based Platform

The idea of collectibles has been around for a while and is well-known in popular culture. To add, a product’s appeal to the general public has been shown to rise when it is distinctive or sold in limited quantities. Therefore, an increase in fraud and counterfeiting for those specific products is unavoidable. One of these products is the Youtooz plushies and figurines, which are sold for a limited time before they are discontinued [6]. It is inevitable to find duplicates of a product or for others to try to make money off of it if. Some may likely deceive and manipulate trusting customers to trick them or cheat them out of the real product. A blockchain approach would be beneficial, in large part, because it records all the different events pertaining to each unique figurine and greatly reduces, if not eliminate, the risk of counterfeit, fraud, or incorrect information surrounding the product. By building confidence between all parties involved in the process and guaranteeing that each client is purchasing from a reputable supplier, the solution will safeguard the ordering process.
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control

Power gating (PG) is an important technique of energy-efficient LSIs to realize additional applications for Internet-of-Things devices in the future, but it also has issues including circuit performance degradation and increased area overhead. In this paper, we designed a new PG switch array with its control unit based on an optimum switch-timing control scheme to obtain a high-performance/low-area implementation. According to the simulation results based on 45nm CMOS under HSPICE, the maximum inrush current is reduced by up to 95.6% and the minimum wake-up-time is only 0.22ns.
Portable Instrument for Precise Ethanol Content Measurement in Sanitizers

Since the covid-19 epidemic outbreak, hands and surface sanitizers have become very much in demand in order to disinfect hands and surfaces, In response to this, we have developed our own instrument. The later is small and portable to allow it to be used in different locations as needed. We have successfully achieved a measurement precision of 1.3 % ethanol concentration in water. The single measurement used only takes 10 seconds to determine whether a sanitizer is going to be effective based on confirming its ethanol concentration to be 70 % or more.
Vedic Divider: A Novel Design for Deconvolution Algorithm based on Vedic Math

Convolution and deconvolution are commonly employed in digital signal processing. Binary division is used in the field of digital image processing for image restoration, red-eye removal, and blur reduction via deconvolution operations. Long sequences must commonly undergo convolution and deconvolution comparable to DSP in many applications. The essential prerequisite for speed in any application is an increase in the speed of its fundamental building block. Both convolution and deconvolution have a central component known as a multiplier or divider. It is the most important component of the system, yet it is also the slowest and most time-consuming. Many approaches for increasing the multiplier and divider's speed have been explored, but the Vedic multiplier and divider are currently the focus of interest. Because it operates more swiftly and with less energy. In this work, the convolution and deconvolution modules are accelerated using Vedic multiplier and divider. Xilinx ISE 14.7 can be used to accomplish this division algorithm's operation. The suggested design is contrasted with current FPGA topologies, including the non-restoring division Algorithm and other Vedic Dividers (Paravartya Sutra, Nikhilam Sutra).
A Gamification and Biofeedback-based Serious Game for Adherence to Physical Activity

The effective use of exercise prescriptions for the re-habilitation of patients with cardiovascular diseases significantly improves the quality of life and reduces mortality rates. In this sense, the development of strategies to increase adherence and consequently, the time of physical activity of the population as a whole. Several recent technological advances, such as Internet of Things and sensors, represent an improvement in the monitoring and prescription of physical activity. Such technologies can be integrated to provide biofeedback on the prescribed physical activities, which can be accessed by smartphones. In this paper, we introduce a serious game that integrates Gamification and biofeedback techniques to be used by patients with Physical activities prescription to prevent and rehabilitate cardiovascular diseases. Specifically, the game has differentiated and integrated approaches through (i) the use of applications with a Gamification system to increase user adherence; (ii) the use of biofeedback to monitor prescribed physical activities. The game has a carefully crafted visual identity, icons, and avatars, considering a system of colors, typography, shapes, sounds, and images that seek to frame the general public.
Broadband Conductor Backed-CPW with Tapered Microstrip Line to Corrugated Via Wall-SIW Transition for Different-Bands (2–40 GHz)

This paper proposes the Corrugated Via-Wall Substrate Integrated Waveguide (CVWSIW) (with enhanced performance compared to the traditional SIW) and the transitions to this newly proposed CVWSIW from a conductor-backed coplanar waveguide (CB-CPW). The CB-CPW slot lines and the gap between two metallic via rows play a prominent role in widening the bandwidth and reducing the loss. The CB-CPW-CVWSIW transition is initially designed in the 4–8 GHz (C-band) range. Following the same design procedure, the transitions are made for other five different bands to cover the frequencies from 2 to 40 GHz. Improved performance in terms of bandwidth, insertion loss, and total loss is the benefit of the designed transitions with the proposed CVWSIW. Laboratory prototypes of the transitions are fabricated and experimentally measured to cross verify the simulation results. The measured results show, for example, the minimum return loss of 15 dB, maximum insertion loss of 0.36 dB, and fractional bandwidth of 62.16% for C-band.
Low Overhead Interdependent Source-Channel Coding with Sequence Preservation

Internet of Things (IoT) devices are small, battery-powered, and energy-limited. In IoT, data communication to the cloud poses a severe challenge in energy consumption. The reliability of the communicated data is another primary concern. An Interdependent Source-Channel Code (ISCC) was proposed to communicate reduced but reliable data. ISCC performs well in error correction with data compression and low energy consumption. However, by design, ISCC does not preserve the sequence of the data. The main objective of this paper is to address the order preservation issue, keeping the transmitted bits' overhead minimal. We propose three solutions to the problem in this paper. The effectiveness has been evaluated in terms of the overall transmitted bit overhead for sequence-preserved ISCC. In addition, the efficiency of the sequence preserved ISCC is also shown by comparing the total number of transmission bits with separate source-channel coding (SSCC). It has been observed that each solution shows its significance for different types of data transmission scenarios. The results show that sequence-preserved ISCC results in up to 27% reduced transmission bits overhead compared to SSCC.
Possibilities of Edge Repetition using Double Mean Labeling

In this research article we improvised for absolute detection of edge Labeling by finding out the ordered pairs for an edge label. There are some theorems proves the distinctiveness of the edge labels in previous articles. Suppose that, if all the adjacent nodes from the parent node receives equal value for the edges, such that, the parent node gets changes according to the adjacency of the parent node to achieve non-distinct edge values. Here, the label of the adjacent vertices is static and parent node splits into multifarious singleton vertex, which depends on the dimension n. Thus, the following theorem and proofs emerge from the idea of non-distinct edge labeling of the star graphs. Here we Constructed the Successor Vertex Graphs of Edge Recursion and the lemma is stated of how the vertex function looks for set of all ordered pairs of vertex label to achieve singleton edge labels using double mean labeling.
Mew: Enabling Large-Scale and Dynamic Link-Flooding Defenses on Programmable Switches

Link-flooding attacks (LFAs) can cut off the Internet connection to selected server targets and are hard to mitigate because adversaries use normal-looking and low-rate flows and can dynamically adjust the attack strategy. Traditional centralized defense systems cannot locally and efficiently suppress malicious traffic. Though emerging programmable switches offer an opportunity to bring defense systems closer to targeted links, their limited resource and lack of support for runtime reconfiguration limit their usage for link-flooding defenses.We present Mew1, a resource-efficient and runtime adaptable link-flooding defense system. Mew can counter various LFAs even when a massive number of flows are concentrated on a link, or when the attack strategy changes quickly. We design a distributed storage mechanism and a lossless state migration mechanism to reduce the storage bottleneck of programmable networks. We develop cooperative defense APIs to support multi-grained co-detection and co-mitigation without excessive overhead. Mew's dynamic defense mechanism can constantly analyze network conditions and activate corresponding defenses without rebooting devices or interrupting other running functions. We develop a prototype of Mew by using real-world programmable switches, which are located in five cities. Our experiments show that the real-world prototype can defend against large-scale and dynamic LFAs effectively.
DevFuzz: Automatic Device Model-Guided Device Driver Fuzzing

The security of device drivers is critical for the entire operating system’s reliability. Yet, it remains very challenging to validate if a device driver can properly handle potentially malicious input from a hardware device. Unfortunately, existing symbolic execution-based solutions often do not scale, while fuzzing solutions require real devices or manual device models, leaving many device drivers under-tested and insecure.This paper presents DevFuzz, a new model-guided device driver fuzzing framework that does not require a physical device. DevFuzz uses symbolic execution to automatically generate the probe model that can guide a fuzzer to properly initialize a device driver under test. DevFuzz also leverages both static and dynamic program analyses to construct MMIO, PIO, and DMA device models to improve the effectiveness of fuzzing further. DevFuzz successfully tested 191 device drivers of various bus types (PCI, USB, RapidIO, I2C) from different operating systems (Linux, FreeBSD, and Windows) and detected 72 bugs, 41 of which have been patched and merged into the mainstream.
Inverter Chain Buffer Optimization for N-path Filter Switch Drivers and Validation through Simulations in 22nm FD-SOI Technology

In this paper, the CMOS inverter chain buffer is optimized for N-path filter switch drivers in a technology-agnostic way. Figures-of-merit are proposed to minimize jitter for minimal power dissipation with consideration of rise/fall-time. Using these, mathematical models are derived based on a simple circuit model and expressed for optimization as a function of the technology-specific inverter output/input capacitance ratio, the number of inverters, and their taper factors. This enables finding designs with any set of taper factors that have lower jitter than common designs for the same power dissipation by sweeping many designs orders of magnitude faster than using circuit simulations. Additionally, analytical equations are derived to quickly allow a designer to find the optimal number and sizing of inverters for the constant and exponential taper designs, either of which is shown to be near-optimal depending on the set of specifications.
A Single-Inductor 4-Phase Hybrid Switched-Capacitor Topology for Integrated 48V-to-1V DC-DC Converters

This paper introduces a single-inductor 4-phase hybrid switched-capacitor (4PSC) topology for integrated high-ratio direct down conversion suitable for point-of-load applications. The proposed topology consists of a 3-phase 4:1 switched-capacitor stage, reducing the switching node swing to 12-V (1/4 of the input) to significantly reduce switching loss, and an inductor to softly charge and discharge the flying capacitors with an extra phase (hence 4-phase operation) with controlled duty cycle to regulate the output voltage to 1V for direct-down conversion. The converter operates with a 4X effective switching frequency, which reduces the ripple/inductance required or switching frequency for better efficiency. With the same output voltage ripples as double step-down (DSD) and 3-level (3L1P) buck converters, the on-time is 4X that of DSD and 3L1P converters, which reduces the challenges in controller design. Lower-voltage (LV) transistors, such as 12-V devices, can be used in some of the switches to significantly improve efficiency. When compared to DSD and 3-Level converters that are state-of-the-art integrated topologies, with the same inductor, output capacitor, and output ripples in the same BCD process, this design achieves: 1) an efficiency comparable or higher than DSD (e.g., ∼3% higher at 48V-1V/5A); 2) along with using only one inductor instead of two for DSD, which can reduce the cost and increase the power density; and 3) much higher efficiency compared to a 3-level buck converter. The 4PSC topology is verified in simulations, showing peak efficiencies of ∼85% and ∼91% in a 180-nm BCD process with 48V-1V and 48V-2V conversions, respectively.
A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC

This paper presents a novel architecture of a SAR assisted 2 step ADC where the SAR residue is quantized with a bidirectional digital slope time-based converter. The bidirectional slope halves the conversion time of the second stage. Furthermore, the redundancy requirements in the second stage are considerably reduced through a unified global calibration scheme. A practical example is given for a 12-bit 64 MS/s ADC with 67 dB SNDR and $\mathbf{208}\ \boldsymbol{\mu} \mathbf{W}$ estimated power consumption targeted at ultra-low power RF receivers. The complete architecture including calibration has been validated with VerilogA models including capacitor mismatch, comparator offsets and noise.
Lung Nodule Segmentation on CT Scan Images Using Patchwise Iterative Graph Clustering

One of the most important steps in lung nodule diagnosis is the automatic segmentation of nodules irrespective of their position and size in the lung parenchyma. In this paper, we propose a new way of applying graph clustering to nodule segmentation. Firstly, the image is preprocessed to extract the lung parenchyma from the CT scan image and identify the region of interest. This is followed by the application of Patchwise Iterative Graph Clustering to spilt the patches and generate superpixels. Next, a region adjacency graph is generated, and agglomerative hierarchical clustering is used to merge the superpixels into different structures such as nodules, and blood vessels. A thresholding algorithm is then used to extract the nodules from the clusters. The proposed method has shown good performance in segmentation with an average dice score of 0.88, an intersection over union score of 0.81, and a high average sensitivity of 89.32 %. Furthermore, the proposed method has been compared to several state-of-the-art methods in the field and has shown an increase in performance in terms of the evaluation metrics.
Edge cloud-enabled FIS-based Road Weather Management System for Connected and Autonomous Vehicles

To address the challenges posed by road weather management, there is a growing need for a comprehensive system that can collect, analyze, and disseminate real-time road weather information to connected and autonomous vehicles. Such a system must be able to assess the impact of weather conditions quickly and accurately on-road operations and provide relevant information to road users in real time. Edge cloud technology provides a solution to the challenges of road weather management by enabling real-time data collection, analysis, and dissemination. The purpose of this paper is to propose a comprehensive edge cloud-enabled road weather management system for connected and autonomous vehicles. The proposed system incorporates the use of Message Queuing Telemetry Transport (MQTT), a two-stage Fuzzy Inference System (FIS), and zone-based alerting. We have evaluated the performance of the proposed system through simulation experiments.