Investigating Energy / Performance Tradeoffs using Transactional Memory in a MPSoC Environment

Multi-core architectures have become pervasive in large-scale digital integrated systems. Manufacturers of general-purpose processors have essentially given up trying to increase clock speed, and instead are now focusing on multiprocessor-system-on-a-chip (MPSoC) architectures, in which multiple processors residing on a single chip communicate directly through shared hardware caches, providing increased concurrency instead of increased clock speed [6]. Integrated platforms for embedded applications are even more aggressively pushing core-level parallelism. SoCs with tens of cores are commonplace [12] , and platforms with hundreds of cores have been announced. In principle, multi-core architectures have the advantages of increased power-performance scalability (assuming on-chip interconnect scales well [5]) and faster design cycle time (by exploiting replication of pre-designed components). However, performance and power benefits can be obtained only if applications exploit a high level of concurrency. Indeed, one of the toughest challenges to be addressed by multi-core architects is how to help programmers expose application parallelism. Embedded applications in multimedia, imaging, and communication, have a high degree of exposed thread-level parallelism, and this is one of the main reasons for the rapid diffusion of multicore architectures in embedded systems [7]. However, managing concurrency is not easy. One major issue is how to synchronize concurrent accesses to memory. When multiple threads access a shared data structure, care must be taken to ensure that concurrent accesses do not interfere. Embedded multi-core architectures usually provide lock-based synchronization support for this purpose. Lock-based synchronization relies on dedicated hardware. Atomic read-modify-write memory access is probably the most commonly deployed synchronization mechanism (e.g., it is used in the ARM MPCore architecture [4]). It requires support in the processor tile, in the communication fabric, and/or in the memory targets. For instance, MPCore relies on hardware support for locked transactions in the system interconnect. Other architectures use semaphore target devices that provide direct atomic read-modify-write support. Embedded platforms are almost invariantly deployed in tightly resource constrained contexts. Hence, the performance and power cost of synchronization is a serious concern that is further compounded by the issue of providing effective programming abstractions. In fact, managing locks is very difficult and error prone. Deadlocks are difficult to avoid, especially when systems have multiple resources. Moreover, even when the system is operating correctly, conditions like lock spinning may impose a significant overhead in power and performance, since they tend to flood the interconnect with useless transactions. Transactional memories have been extensively investigated in general-purpose systems as an alternative to lock-based synchronization (e.g., [8, 10]). Transactional memory enables speculative execution of threads without acquiring locks, guaranteeing that transactions appear to execute atomically. Transactional memory has advantages over locks in terms of ease of programming, performance, and energy consumption [11]. However, their applicability to embedded multi-core platforms, based on simple cores and memory system interfaces, has not been explored yet. The main objective of this paper is to demonstrate, for the first time, a complete hardware transactional memory solution for an embedded multiStart/Stop