Superjunction MOSFET

of the surface MOSFET area and optimizing the cell structure, and the former entails reducing the drift resistance by optimizing the resistivity and thickness of the drift layer that ensure the inductive load avalanche withstand capability and the breakdown voltage. With a structure that uses a p-well region to ensure the inductive load avalanche withstand capability, there is a limit to extent with which the drift resistance can be reduced, but the application of quasi-plane junction technology enables this limit to be lowered(3). With quasi-plane junction technology, instead of using a p-well structure, the drift resistance is reduced by narrowing the distance between p-base regions without increasing the JFET resistance, and by optimizing the p-base shape, an inductive load avalanche withstand capability equivalent to that of a p-well structure is guaranteed. By applying quasiplane junction technology, the Ron· A of a conventional MOSFET has been improved to 110% of the silicon limit, and the Ron· QGD has also been improved significantly with the reduction in Ron· A and the narrower distance between p-base regions. Fuji Electric has applied this quasi-plane junction technology to commercialize the “SuperFAP-G Series” which is an easyto-use successor of the “SuperFAP-E3 Series(4). ” Recently, the SJ-MOSFET, which breaks through the silicon limit, has been attracting attention. As shown in Fig. 2, the SJ-MOSFET replaces the p-type and n-type regions in the drift layer of a conventional MOSFET with alternating regions of p-pillars and n-pillars, and because the impurity concentration of the n-type regions can be increased, the Ron· A can be reduced dramatically. Moreover, since the Ron· A can be reduced, the active area can be made smaller for the same on-resistance, thereby enabling the Ron· QGD to be reduced as well. 3. SJ-MOSFET Development 3.1 Multi-epitaxial growth technology The SJ structure enables a dramatically lower value of Ron· A, but because it is a charge compensation structure, it has the disadvantage of being unable to maintain its breakdown voltage unless a charge balance can be maintained between n-type and p-type regions. If the charge balance collapses, the breakdown voltage drops significantly and the rated voltage will not be maintainable. When fabricating an SJMOSFET, the impurity concentrations of the n-type and p-type regions must be controlled precisely. To reduce deviation of the breakdown voltage, the impurity concentration in the depth direction of the p-type region must be distributed. Therefore, the SJ structure is fabricated with a method of multi-epitaxial growth in which the processes of introducing impurities into a certain area by ion implantation, which has excellent impurity concentration control performance, and epitaxial growth are performed repeatedly(5). Figure 3 shows the process flow of SJ structure fabrication by the multi-epitaxial growth method. First, an n-type layer having a low impurity concentration is grown epitaxially on an n-type substrate with consideration given to the thickness of the buffer layer (step 1). Next after completion of the fabrication of that layer, phosphorous (P) and boron (B) ions are injected into regions Fig.2 Structure of conventional MOSFET and SJ-MOSFET