Novel Convex Optimization Approaches for VLSI Floorplanning

The floorplanning problem aims to arrange a set of rectangular modules on a rectangular chip area so as to optimize an appropriate measure of performance. This problem is known to be NP-hard, and is particularly challenging if the chip dimensions are fixed. Fixed-outline floorplanning is becoming increasingly important as a tool to design flows in the hierarchical design of Application Specific Integrated Circuits and System-On-Chip. Therefore, it has recently received much attention. A two-stage convex optimization methodology is proposed to solve the fixedoutline floorplanning problem. It is a global optimization problem for wirelength minimization. In the first stage, an attractor-repeller convex optimization model provides the relative positions of the modules on the floorplan. The second stage places and sizes the modules using convex optimization. Given the relative positions of the modules from the first stage, a Voronoi diagram and Delaunay triangulation method is used to obtain a planar graph and hence a relative position matrix connecting the two stages. An efficient method for generating sparse relative position matrices and an interchange-free algorithm for local improvement of the floorplan are also presented. Experimental results on the standard benchmarks MCNC and GSRC demonstrate that we obtain significant improvements on the best results in the literature. Overlapfree and deadspace-free floorplans are achieved in a fixed outline and floorplans with any specified percentage of whitespace can be produced. Most important, our method provides a greater improvement as the number of modules increases. A very important feature of our methodology is that not only do the dimensions of the floorplans in our experiments comply with the original ones provided in the GSRC benchmark, but also zero-deadspace floorplans can be obtained. Thus, our approach is able to guarantee complete area utilization in a fixed-outline situation. Our method is also applicable to area minimization in classical floorplanning. iii Acknowledgements Firstly, I would like to sincerely and deeply acknowledge my academic advisors, Prof. Anthony Vannelli and Prof. Miguel F. Anjos, for their guidance, encouragement, assistance, constant patience, and continued support. I greatly appreciate them for all that they taught me during the Ph.D. program. Their suggestions were most helpful. I would like to thank my examining committee, Prof. Shawki Areibi, Prof. Samir Elhedhli, and Prof. Catherine H. Gebotys. Special thanks to my external examiner, Prof. Richard Shi. I would like to thank our system administrators, Phil Regier and Fernando R. Hernandez, for maintaining our computers healthy. I would like to acknowledge financial support by Postgraduate Award from the Natural Sciences and Engineering Research Council (NSERC) of Canada, Ontario Graduate Scholarship, University of Waterloo President’s Graduate Scholarships, and University of Waterloo Graduate Incentive Awards; this support was a great encouragement. I also wish to thank the following friends and officemates for their assistance and friendship: Rafael Avalos, Hemantkumar Barot, Doris Chen, Mohamed Elsalih, Alexander Engau, Xinxin Fan, Bissan Ghaddar, Mohammad Towhidul Islam, Ibi Jankovits, Hai Jiang, Christie Kong, Nathan Krislock, Xinhua Ling, Stanley Liu, Matthias Takouda, Juan Vera, Kris Vorwerk, Ping Wang, Hua Wei, Zhizhong Yan, Chenxi Zhang, and Jichen Zhang. Last but not least, I am extremely grateful to my wife, Rong Yang, and my son, Martin Luo, for their love and patience. I also thank my dear parents Ronghua Luo and Xiuzhen Tian, my brother Youmin Luo, and my sister Ping Luo for their love, support, and encouragement despite the distance. None of this would have been possible without their understanding and patience. iv To my dear parents Ronghua Luo, Xiuzhen Tian and my dear wife and son Rong Yang, Martin Luo.