fT/fmax SiGe Technology

ance of the cross-coupled differential pair becomes positive. A new topology is demonstrated based on two cascaded emitter followers with resistive load, to implement the active circuitry compensating the losses of the tank circuit. This new topology is particularly suited for frequencies beyond fcross, and achieves a maximum oscillation frequency well beyond the limits for the classical cross-coupled pair. In addition, this new topology simul- taneously implements the output buffering function, thereby minimizing the total load to the tank-circuit. The implemented LC-VCO achieves an oscillation frequency of 35.2-37.6GHz and a phase noise of -105dBc/Hz at 2MHz from the carrier in a stan- dard SiGe production technology (1). The general principle of an integrated LC-VCO is shown in the top-left part of Figure 21.9. 1. The losses of the LC-tank are rep- resented by the parallel resistance Rt. The negative resistance Rp is needed to compensate the losses of the tank. The classical con- figuration to implement Rp is based on a cross-coupled differen- tial pair, implementing Rp ≈ -2/gm at low frequencies. For such a configuration, resistance Rp is negative up to a maximum fre- quency fcross ≈√ fVfT), where fV is the input bandwidth of the npn, mainly from base resistance and base-emitter plus base-collector capacitance (2). Therefore, fcross gives the theoretical maximum attainable oscillation frequency for this topology, even when assuming a lossless tank circuit. For our SiGe IC technology, typ- ical simulated and calculated values for Rp as a function of fre- quency are shown in Fig. 21.9. 2, demonstrating fcross ≈ 30-40 GHz. To fulfill the oscillation condition, we need Rt/|Rp|>1, resulting in a maximum oscillation frequency somewhat below fcross . On top of this, some margin in Rt/|Rp| is needed to allow for processing and temperature variation, resulting in a practical limit of about 25 GHz in our technology. The newly proposed implementation for Rp is shown in the bot- tom part of Fig. 21.9. 1. A negative input resistance is implement- ed using a cascaded circuit of two emitter followers with a resis- tive output load. The resistive load of output emitter follower T2 translates into a capacitive load for input emitter follower T1. The capacitive load of emitter follower T1 translates into a (fre- quency dependent) negative input resistance at the base of T1, thereby implementing the negative resistance RP used to undamp the LC-tank. In our implementation, we use the same circuit as output buffer, driving the two 50Ω resistive output loads. These off-chip resistive loads are part of Rl. To analyze the theoretical oscillation frequency limit for this new topology, we use the simplified small-signal diagram of Fig. 21.9. 3. This diagram represents the capacitively loaded emitter follower T1 in which capacitive load Cl represents the input capacitance from the resistively loaded emitter follower T2 plus the output capacitance of the bias current source I1. In the sim- plified transistor model, base and emitter series resistance are included. The frequency-dependant current gain β(ω) can be approximated by β(ω) ≈ -j(ωT/ω) with ωT = 2πfT. Base-collector capacitance has been omitted in the calculation and is added in parallel to the calculated input impedance. The calculated input admittance equals: