Design of Analog Circuits in 28nm CMOS Technology for Physics Applications

The exponential trend of the complementary metal-oxide-semiconductor (CMOS) technologies predicted by Moore’s law has been successfully demonstrated over the last three decades. A constant downscaling of CMOS technologies has been developed, in order to comply with requirements on speed, complexity, circuit density and power consumption of advanced high performance digital applications. With the arrival of nanoscale (sub-100nm) CMOS technologies, digital performance improve further, but many new challenges have been introduced for analog designers. In fact, for the digital circuits CMOS scaling-down leads to several benefits: speed improvement, reduced power consumption, high integration and complexity level. The analog circuits, instead, strongly suffers from the ScalTech trend, because the MOS behavior dramatically changes through the different technological nodes. Especially for the ultra-scaled nodes, second order effects, previously negligible, become very important and start to be dominant, affecting the transistors performance. For instance, lower intrinsic DC-gain, reduced dynamic range, operating point issues and larger parameter variability are some of the problems due to the scaling of physical (length, oxide thickness, etc.) and electrical (supply voltage) parameters. Analog designers have to manage these problems at different phases of the design, circuital and layout, in order to satisfy the market high-performance requirements. Despite that, the design of analog circuit in sub-nm technologies is mandatory in some cases or can be even strategical in others. For example, in mainly mixed-signal systems, the read-out electronic requires high frequency performance, so the choice of deep submicron technology is mandatory, also for the analog part. Other types of applications are the high-energy physics experiments, where read-out circuits are exposed to very high radiation levels with consequent performance degradation. Since radiation damage is proportional to gate oxide volume, smaller devices exhibit lower radiation detriment. It has been demonstrated in fact, that 28nm CMOS technology devices are capable to sustain 1Grad-TID exposure, not possible with previous technologies. In this thesis, the main challenges in ultra-scaled technologies are analysed and then integrated circuits designed in 28nm CMOS technology are presented. The aim of this work is to show the design approach and several solutions to be applied in order to outermost the limits of silicon scaling, address the major scaling problems and guarantee the required performance. The first circuit design, presented in the second chapter and integrated in 28nm CMOS technology, is a Fast-Tracker front-end (FTfe) for charge detection. The readout system has been developed starting from the main specifications and circuital solutions already adopted for muon detection in ATLAS experiment. The proposed front-end is able to detect an event and soon after to reset the system in order to make the read-out front-end already available for the following events, avoiding long dead times. Moreover, exploiting a two thresholds crossing solution, the required