Miracle-dz/UniFAR-FTUs huggingface dataset:
AVX2-Optimized Interpolation Filters for HEVC Inter Encoding

High Efficiency Video Coding (HEVC) sets the stage for economic video transmission and storage, but its inherent computational complexity calls for powerful implementations. This paper addresses the principal performance bottleneck of HEVC codecs by introducing AVX2-vectorized algorithms for HEVC interpolation filters. The proposed speed-up techniques include 1) a data permutation scheme for the horizontal interpolation stage; 2) a sliding window strategy for the vertical interpolation stage; 3) optimal usage of horizontal and vertical interpolation during fractional motion estimation; and 4) a lane-based approach to double the vector lengths from 128-bit legacy vector extensions to 256bits of AVX2. Our AVX2-optimized interpolation filters were benchmarked as part of the practical Kvazaar open-source HEVC encoder. On an Intel 8-core Xeon processor, they were shown to be 9.7 and 8.5 times as fast as scalar interpolation with the Kvazaar ultrafast and veryslow presets, respectively. In both cases, changing over from scalar to vectorized interpolation increases the coding speed of Kvazaar by more than 50%, which stresses the importance of interpolation optimizations in modern video encoders.
Machine Learning based Self Driving Car Simulator along with Graphic User Interface (GUI)

This paper demonstrates a self-driving car simulator using machine learning along with Graphic User Interface (GUI). The car components with their corresponding physics, road structuring, traffic patterns, and neural network for predicting the next movement stage are realized using JavaScript programming. The GUI of the developed car simulator looks like the drone is filming it from the top of the car. The car has several sensors that can cast rays to detect objects. The distance metric obtained from the sensors is then fed to a neural network that will control the car's movement. The collision detection algorithm, a polygon intersection, uses segment intersection and linear interpolation to get the coordinates of the nearby objects. The segment intersection method works on any shape of objects and orientation in o(n2) time complexity that works in the developed simulation consistently. By enabling the testing of various scenarios and control improvements, the simulation model of a self-driving car is created that replicates the operation of a physical car driver using randomly generated weights and biases of neural networks. Here, the neural network provides evidence for decision-making so that the car can drive itself reliably. The developed model works on the traffic patterns it was trained in and can be further meshed together in the future with the help of different traffic pattern models to achieve higher safety requirements.
A 0.5V, pico-watt, 0.06%/V / 0.03%/V low supply sensitive current/voltage reference without using amplifiers and resistors

The paper presents a 0.5V supply, gate leakage-based current/voltage reference for ultra-low power IoT and biomedical applications. The references are generated by the proper addition of PTAT and CTAT curves, which are obtained by exploiting the traditional architecture of the beta multiplier and using the body biasing effect. Gate leakage transistors replace the resistors to ensure low power and low area. The circuit doesn't involve any Op-Amps avoiding the issues of offset that are prominent in these circuits. Implemented in CMOS 90nm technology, the proposed current (voltage) reference achieves a typical accuracy of $34.6\text{ppm} /{ }^{\circ} \mathrm{C}(29.68 \text{ppm} /{ }^{\circ} \mathrm{C})$ over a wide temperature range of $-55^{\circ} \mathrm{C}$ to $75^{\circ}\mathrm{C}$ with typical value 63.32pA(0.35V). Excellent line sensitivity of 0.0318%N and 0.0576%N are observed for voltage and current reference, respectively, in a supply range of 0.5V - 2.3V. The area occupied by the total circuit is 0.0096mm2, while the power consumption is 415pW at the typical corner of $27^{\circ}C$ and 0.5V supply.
Adaptive Filter Based Control Method for Performance Improvement of Hybrid Energy Storage System in DC Microgrid

Energy storage devices are required to store energy for constant and consistent operation of microgrid. Batteries are the common energy storage system in microgrid applications. However, due to low power density, it cannot handle high-frequency charging and discharging. To improve power quality, reduce power fluctuation, and ensure power balance, a hybrid energy storage system with high energy density storage devices and high power density storage devices is used. A hybrid energy storage system comprised of batteries and supercapacitors is proposed in this paper. For intermittent power, the hybrid energy storage management system is critical for ensuring system stability and maintaining constant DC bus voltage. This paper proposes an adaptive filter-based method (AFBM) control strategy for a DC microgrid that focuses on smooth and stable operation while mitigating storage device safety and degradation issues. Based on the recent state of charge of storage device in the DC microgrid, the control strategy proposes a charging and discharging current distribution. The proposed method and the conventional filter-based method are both simulated in MATLAB/Simulink with the same configuration, value, and operation mode. The results show that the proposed system outperforms the traditional method in terms of voltage stability, proportional load sharing, and proper charging/discharging of storage devices.
Foot hemodynamics using optical tomography: A potential biomarker of peripheral arterial disease

Peripheral arterial disease (PAD) is the narrowing of the arteries within the lower extremities, which inhibits blood flow to the foot. We present the use of dynamic diffuse optical tomography (DDOT) system to measure blood flow in the foot during venous and arterial occlusions. DDOT is a non-ionizing, contrast-free, and fast imaging modality. The DDOT system consists of 4 sensors, each containing four laser diodes (at wavelengths of 670, 780, 808, and 850 nm) and two silicon photodiodes. We examined 11 healthy subjects with a protocol consisting of five consecutive measurements. Biomarkers were extracted from changes in hemoglobin concentrations during the measurements. The results from a pilot study are presented in this report. The average increase in total hemoglobin was $\mathbf{17.2\pm 5.8}\ \mu \mathbf{M}$ during a measurement with 60 mmHg occlusion and $\mathbf{10.4\pm 6.7} \ \mu \mathbf{M}$ during a measurement with 180 mmHg occlusion. The biomarkers can quantify blood perfusion and oxygen consumption in the foot, and they have the potential to detect and monitor PAD.
Design of a Sleep Modulation System with FPGA-Accelerated Deep Learning for Closed-loop Stage-Specific In-Phase Auditory Stimulation

Closed-loop sleep modulation is an emerging research paradigm to treat sleep disorders and enhance sleep benefits. However, two major barriers hinder the widespread application of this research paradigm. First, subjects often need to be wire-connected to rack-mount instrumentation for data acquisition, which negatively affects sleep quality. Second, conventional real-time sleep stage classification algorithms give limited performance. In this work, we conquer these two limitations by developing a sleep modulation system that supports closed-loop operations on the device. Sleep stage classification is performed using a lightweight deep learning (DL) model accelerated by a low-power field-programmable gate array (FPGA) device. The DL model uses a single channel electroencephalogram (EEG) as input. Two convolutional neural networks (CNNs) are used to capture general and detailed features, and a bidirectional long-short-term memory (LSTM) network is used to capture time-variant sequence features. An 8-bit quantization is used to reduce the computational cost without compromising performance. The DL model has been validated using a public sleep database containing 81 subjects, achieving a state-of-the-art classification accuracy of 85.8% and a F1-score of 79%. The developed model has also shown the potential to be generalized to different channels and input data lengths. Closed-loop in-phase auditory stimulation has been demonstrated on the test bench.
A Fully-Integrated Half-Bridge GaN Driver for Bidirectional Power Transfer

This paper presents a fully-integrated half-bridge GaN driver for bidirectional power transfer. Three-level/bipolar gate driver is introduced for the power switches to improve reliability at high dv/dt. On-chip bootstrap circuit with charge sharing reduces chip area and protects high-side switch. The designed GaN driver is fabricated with a 0. 18μm BCD process. Measurement results show that at 5MHz operating frequency, the highest input voltage reaches 40V in buck mode and the highest output voltage ups to 36V in boost mode. The peak efficiencies of the design are 93.21 % for the 20V-to-12V conversion and 91.17% for the 12V -to-18V conversion. The design delivers a maximum power of 21.15W in buck mode.
LARE: A Linear Approximate Reinforcement Learning Based Adaptive Routing for Network-on-Chips

The routing algorithm is crucial for network performance in network-on-chips (NoCs). With emerging applications bring new features to NoCs with more complex and time-varying traffic, which turns the routing computation process into multi-objective optimization. However, We found that the existing routing algorithms cannot effectively achieve load-balanced between different traffic due to the static method of routing design. The routing algorithm design space will increase if all factors affecting routing are considered. Reinforcement learning (RL) methods have demonstrated promising opportunities applied to architecture design exploration. In this paper, we proposed a novel RL framework for adaptive routing design in NoCs. This method uses network information to select the best path to achieve load balance and lower communication latency at the same time. Unfortunately, with this method, the implementation overhead of RL increases rapidly as the network scale increases. Therefore, we introduce a linear function of approximate RL-based adaptive routing (LARE) to reduce implementation over-head. We conduct extensive experiments against state-of-the-art routing algorithms to evaluate our design. Simulation results demonstrate the benefits of our design under synthetic traffic workloads and real applications. In addition, LARE can achieve similar network performance with traditional RL implementation with a much lower hardware overhead.
A Scalable RDMA Network Interface Card with Efficient Cache Management

Remote Direct Memory Access (RDMA) has been applied in large-scale clusters due to its high bandwidth and low latency features in recent decades. However, the scalability issue is a known intractable problem that the current RDMA Network Interface Card (RNIC) cannot overcome as the number of connections increases to thousands. The key to the scalability bottleneck is managing the connection information cached on the RNIC. To solve the scalability problem, firstly, we test and analyze the behavior of the commercial RNIC when the network performance declines in the case of large-scale connections. Further, we give the performance model of RNIC and point out that the cache design is the key to scalability issues. Then, we propose a Scalable RDMA NIC (ScalaRNIC) architecture with a non-blocking and priority-programmable cache design. Besides, our cache design supports parametric configuration by the extended API. ScalaRNIC can maintain $\mathrm{a}\approx 100\%$ cache hit ratio for higher priority connections and keep message rates nearly equal to peak performance. In contrast, commercial RNIC's performance drops by 47% when there are a few thousand connections.
REED: Enhanced Resource Allocation and Energy Management in SDN-Enabled Edge Computing-Based Smart Buildings

The number of applications of internet of things (IoT) devices in smart buildings keeps growing continuously, and with it, the computational tasks rendered by those devices. In smart buildings, IoT devices generate massive data traffic, and the number of devices and traffic volume increases exponentially. This issue is more sensitive in smart buildings as the management of their data is critical. Therefore, matching the task’s differential needs (e.g., energy, delay) with the network resources is paramount. In a device-to-device (D2D) aided edge computing (EC) architecture, tasks can be offloaded to the resource-rich IoT device or edge node to improve offloading efficiency and minimize energy consumption and delay. Exploiting these benefits, in this paper, we propose enhanced resource allocation and energy management in smart buildings enabled by software-defined networking and EC, as well as D2D aided end-to-end communications (REED). REED aims to minimize energy consumption and delay in a smart building by jointly optimizing resource allocation and offloading decisions. To find the near-optimal solution, we use the model-free deep reinforcement learning, i.e., deep deterministic policy gradient algorithm, because the formulated problem is a mixed-integer nonlinear optimization problem with a large dimensional continuous state and action spaces in a dynamic environment. Simulation results show that the intended REED model can perform better in terms of energy consumption and delay than the other benchmark approaches.
Ultra Wideband Low Noise N-path Direct Conversion Receiver for 5G-advanced and 6G Wireless System

Optimizing the N-path receiver for wide input range tunability and achieving good noise, gain, and linearity performance at lower power dissipation is a challenging task. This paper investigates the negative feedback-assisted wideband reactance cancelling front-end LNA topology in the N-path direct conversion receiver in terms of its performance parameters. The proposed low-power design is enabled due to LNA preceded by the N-path mixer and has good noise performance compared to the mixer first architecture for the same signal bandwidth. The proposed reactance cancelling LNA with negative feedback has reduced the overall noise figure (NF) by the square of the feedback factor. The proposed N-path receiver designed in a 65-nm CMOS process achieves 72 - 63 dB of gain and 2.39 - 2.78 dB of NF at a minimal power dissipation of 10.69 mW. It achieved an -10 dB of S11 bandwidth for the wide input frequency range from 1–7 GHz.
EXTENDED EDGE VERTEX CORDIAL LABELING OF GRAPH

A binary labeling that assigns 0 or 1 to each vertex of a graph with certain condition called as pairity condition is called as vertex binary labeling. Here we discuss a labeling that give some natural numbers as labels to edges but results in binary labeling of vertices. This graph labeling is called as extended edge vertex cordial (eevc) labeling and we show that path Pn, Cycles C n , K 1,n , K 2 ,n,snskes on C3 i.e. S(C3,n) have eevc labeling.
Encapsulation of Biosensor for Stress Monitoring in Fish: A Study on Design and Material Evaluation

This paper presents the packaging of an implantable fish-health monitoring system, called FishTag. The FishTag consists of biosensors, electronics, batteries, and an acoustic signal transmitter. For this system to function, it is vital for both the system and the fish that the tag is packaged properly. It is necessary to prove that the packaging approaches chosen will survive the environment inside a fish for the expected lifetime. The materials chosen for encapsulation were epoxy resin and biocompatible liquid silicone rubber. FishTag with a capsule shape was the main focus of this work. In addition, an alternative design of the tag was also proposed. The materials' capability to withstand the working environment of the tag was evaluated by water absorption and functional tests. The water absorption tests showed that the mean weight increase after 7 days was 2.4% and 0.2% for the epoxy and silicone, respectively. The FishTag packaged in epoxy functioned properly after being subjected to water and vibrations for a week during the functional test. Both silicone and epoxy in capsule-shape perform satisfactorily at keeping the system safe from the environment. Silicone is preferred as it absorbs less water, is flexible, and allows for change of battery and remoulding.
A Mini-Living Lab Project as a Pedagogical Approach to AI-driven Autonomous Systems in Undergraduate Engineering and CS+[X] Education

We present the living lab methodology as a pedagogical approach to artificial intelligence (AI) based autonomous systems under the framework of place-based learning. Due to time, location, weather, traffic safety, and other issues, performing road testing on autonomous cars is challenging. Autonomous driving testing has been made easier by the virtual test platform, which can partly replace road testing. To improve the system-designed skills of the students and to validate autonomous driving ideas in real life settings to further refine solutions proposed, we proposed Mini-Living Lab system. The platform may also give a significant number of test scenarios for the driver during early verification of the autonomous driving control approach. We provide the detailed system design and implement an artificial intelligence based autonomous driving model on our proposed system. For the neural network model, we adopt PointNet++ and improve its design to process the lidar point cloud data, then further to perform the autonomous steering control tasks. The proposed project provides an opportunity for students to actively participate in co-creation of knowledge and innovation in real-life contexts, thus leading to an enhanced understanding of complex engineering problems and development of required skills for their innovative solutions.
Energy-Efficient Stochastic Computing for Convolutional Neural Networks by Using Kernel-wise Parallelism

Stochastic computing (SC) is a low-cost computation paradigm that can replace conventional binary arithmetic to provide a low hardware footprint with high scalability. However, since the SC bitstream length grows with the precision of the represented data, regardless of its lower power consumption, the convolutional SC-based neural networks may not be efficient in hardware area and energy. This work proposes a novel SC accelerator, PSC-Conv, to implement the convolutional layer using a new binary-interfaced stochastic computing architecture. PSC-Conv exploits kernel-wise parallelism in CNNs, reducing hardware footprint and energy consumption. Experimental re-sults show that the proposed implementation excels among several state-of-the-art SC-based implementations regarding area and power efficiency. We also compared the implementations of three modern CNNs, including LeNet-5, MobileNet, and ResNet-50. Experimental results demonstrate that, on average, PSC-Conv can achieve 5.02x speedup and 87.9% energy reduction compared with the binary implementation.
Improving Semantic Segmentation Performance of Deep Networks for Autonomous Driving through Loss Functions

Semantic segmentation of images for autonomous driving is a dense pixel-level prediction task. Present-day algorithms make extensive use of deep learning models for parsing the image. A large number of classes and class imbalance in the autonomous driving dataset make accurate labeling of pixels challenging. Cross- Entropy(Ce)loss function is mainly used to optimize the network parameters during training. The overall performance gain resulting from CE loss comes from large object classes. In contrast, the segmentation accuracy of smaller classes and object boundaries remains inferior, even with increased overall accuracy. To address this limitation, task- specific custom loss functions have been developed and used for various applications like biomedical image processing. However, they have rarely been used for road scene segmentation in an autonomous driving context. To fill this gap, we develop a composite loss function by linearly combining the CE loss and boundary/region-based loss to improve the existing state- of-the-art model. We give empirical evidence that our custom loss function improves the segmentation scores on smaller object categories and object boundaries. Through extensive experiments on the Cityscapes dataset, we show that Deep networks trained with our loss function see a gain of more than 2 % on the overall $m$ IoU score. In some smaller classes, these scores are increased by more than 20%.
EACNN: Efficient CNN Accelerator Utilizing Linear Approximation and Computation Reuse

This paper proposes an efficient hardware accelerator named EACNN for use in Convolution Neural Networks. EACNN is an efficient CNN architecture that is based on co-optimization of algorithms and hardware. The proposed approach is based on linear approximation of the weights for pre-trained networks with low loss of accuracy. Furthermore, a weight substitution and remapping technique adopts linear approximation coefficients to replace CNN weights. That leads to a repetition of the weight values across different kernels and enables the reuse of CNN computations for various output feature maps. The input activations corresponding to the same linear co-efficient can be multiplied and accumulated first and then reused to generate multiple output feature maps. This computational reuse method reduces the number of multiplication and addition operations and memory accesses, which is efficiently supported by a dedicated element in the proposed EACNN. Experimental results on CIFAR 10 and CIFAR 100 datasets show that the proposed method eliminates around 61% of the multiplications in the network without significant loss of accuracy $(< 3\%)$. As a demonstration, a hardware accelerator based on EACNN was implemented on Xilinx FPGA Artix 7 and achieved a 50% reduction in the FPGA hardware resources.
A Dual-Ring Switched-Capacitor DC-DC Converter With Systematic Fractional Conversion Ratios

This paper presents a fully-integrated reconfigurable dual-ring switched-capacitor (DRSC) converter that overcomes the coarse output voltage resolution limitation of traditional switched-capacitor (SC) converters. The proposed DRSC converter cascades multiple stages of SC cells and achieves a fine voltage conversion ratio resolution from 1/n to (n-1)/n, where n is the number of phases. To improve efficiency, the bottom-plate parasitic loss is mitigated by the charge redistribution technique. Also, the power switches are divided into several segmentation groups to reduce the output ripple with different loads. This work is designed in a 180nm CMOS process with 30 cascaded reconfigurable SC power cells. It achieves a wide output voltage range of 0.5-3.3V from a battery input voltage (2.7-4.2V). The load regulation is implemented with a pulse-frequency modulation (PFM) control. The simulated peak efficiency is 78%, with a load current range of 0 to 20mA, using 1.5nF on-chip capacitors in total.
Per-Zone Resource Reuse for NR Sidelink Based Vulnerable Road User Protection

Benefiting from New Radio (NR) sidelink based Vehicle-to-Everything (V2X) communication, Vulnerable Road Users Protection (VRUP) can be further developed in intelligent transport systems. However, considering limited resources in the V2X network, the interference caused by resource collisions may restrict this development. This paper propose a spatial reuse scheme of frequency resources, namely the Per-Zone Resource Reuse (PZRR) scheme, for NR sidelink based VRUP enhancement. To efficiently characterize the VRUP behavior in the PZRR scheme, a stochastic geometry based theoretical framework is provided by carefully taking into account interference from multiple zones. With the help of this framework, the delivery probability of the VRUP message can be accurately described under various parameter settings. Furthermore, numerical results show that the VRUP message delivery probability can be significantly improved by properly tuning parameter settings.