RF Performance and Reliability of SiC MESFETs on High Purity Semi-Insulating Substrates

In this paper we report on our efforts to reduce trap effects, increase efficiency, and improve the yield and reliability of SiC MESFETs. By minimizing substrate and surface-related trapping effects that have previously been observed in SiC MESFETs, drain efficiencies as high as 68% have been achieved at 3.5 GHz with associated CW power densities of 3.8 W/mm. MESFETs fabricated with this process have passed 1,000 hour High Temperature Reverse Bias test (HTRB) with negligible change in dc or RF parameters. A sampling of these devices have also been running for over 2,000 hours in an RF high temperature operating life test (HTOL) with negligible change in parameters. This MESFET process has been transferred to 3-inch high purity semiinsulating (HPSI) substrates. The quality of this process is demonstrated by the cross-wafer uniformity of the breakdown voltage and a standard deviation in gate threshold voltage of 0.6 V. Introduction SiC MESFETs have received increased attention in recent years due to their high power density and high operating voltage, which will enable wider bandwidth, higher performance, and lighter weight systems than those using conventional Si or GaAs technology. Significant progress has been achieved in the development and demonstration of high power MESFETs and wide band amplifiers based on this technology [1]. However, undesirable problems related to trapping in the substrate and/or the surface have also been reported [2-5]. These issues need to be fully resolved to improve device performance, reliability, and to make this technology commercially viable. In this paper we present our recent results for SiC MESFETs that exhibit minimal trap-related effects. Extensive data on the reliability of these devices is also presented. MESFET Performance The MESFETs in this work were fabricated on 2-inch diameter high-purity semi-insulating (HPSI) 4H-SiC substrates available from Cree. The MESFETs were fabricated with dry-etched isolation mesas, sintered Ni ohmic contacts, a gate length of 0.45 μm, and air-bridge source interconnects. These devices were fully passivated with 0.5 μm of silicon nitride for environmental protection and reliability. Devices fabricated with this process typically show maximum channel current, Imax, of 360 mA/mm, pinch-off voltage of –10 V, peak transconductance of 42 mS/mm, and gate-drain breakdown voltage in excess of 120 V. These DC characteristics translate to excellent RF performance in both Class A and deep Class AB conditions. Fig. 1 shows an on-wafer CW load pull measurement at 3.5 GHz of a 1-mm device biased at a very low bias current of 3% Imax and VDS=50 V. The power output is 3.8 W with an associated drain efficiency of 68%. The associated PAE under these conditions is typically in the range of 53% 58%. The high drain efficiency under near pinch-off condition clearly demonstrates that substrate and surface trapping effects previously observed in SiC MESFETs have been greatly reduced. Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1205-1208 doi:10.4028/www.scientific. net/MSF.457-460.1205 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific. net. (Semanticscholar.org-11/03/20,15:23:56) 2 Title of Publication (to be inserted by the publisher) The reduction of trapping was also verified by measuring drain lag under both DC and RF operation. Fig. 2 is a histogram showing that there is essentially no reduction in pulsed IDSS when measured from a quiescent condition of VDS = 25 V, VGS = -16 V as compared to IDSS when measured from VDS = 0 V, VGS = 0 V. The absence of current collapse is evidence of very low trapping. In the past, devices fabricated on vanadium-doped substrates also exhibited a significant reduction in the quiescent drain current when the RF input power was abruptly turned off, and then slowly recovered to the original bias point. This effect can lead to signal distortion in RF operation, and the present devices on HPSI substrates do not show this undesirable feature. 5 10 15 20 25 30 35 15 20 25 30 35 40 Freq. = 3.5 GHz CW Power = 3.8 W Drain Eff. = 68% V DS = 50 V I DQ = 10 mA W G = 1 mm Input Power (dBm) O u tp u t P o w e r (d B m ) 0 10 20 30 40 50 60 70 D ra in E fic ie n c y (% ) -2 -1 0 1 2 0 10 20 30 40 Change in I DS S (% ) D ie C o u n t Fig. 1: On-wafer CW load pull measurement at 3.5 GHz of a 1-mm device biased 3% Imax and VDS=50 V. The power output is 3.8 W with an associated drain efficiency of 68% and PAE of 53%. Fig. 2: Drain lag measurements of 1-mm MESFETs showing an average change of zero in the pulsed IDSS when comparing quiescent bias points of VDS = 0 V, VGS = 0 V and VDS = 25 V, VGS = -16 V. This MESFET process has now been transferred to a 3-inch foundry process. The typical micropipe density on the 3-inch HPSI substrates has been reduced to 35 cm -2 , which is low enough to have minimal yield impact on typical RF power transistors, and progress continues to be rapid in this area. Cree’s R&D best result to date for the 3-inch HSPI process is a wafer with an average micropipe density of only 3 cm -2 , with 96% of the wafer area micropipe free. Epi uniformity on the 3-inch HPSI substrates is also excellent, with eddy current measurments showing typical standard deviations in sheet resisitivity to be less than 3% of the wafer average. The uniformity achieved with the 3-inch MESFET process is illustrated in Figures 3 and 4. Figure 3 shows a map of the breakdown voltage measured at 1 mA/mm for 0.25 mm FETs used as process control monitors (PCM) across a 3-inch wafer. Figure 4 shows the histogram of the threshold voltage from larger periphery MESFETs from a completed wafer. The standard deviation in Vth of 0.6 V illustrates the uniformity of the epitaxial layer and device fabrication processes. -14 -13 -12 -11 -10 -9 -8 0 100 200 300 400 500 Gate V th (V) D ie C o u n t Fig. 3: Map of Vbr for 0.25-mm SiC MESFETs used for process control monitors on a 3-inch HPSI substrate. Fig. 4: Histogram of the distribution of Vth for 10 W SiC MESFETs fabricated on a 3-inch HPSI substrate. 1206 Silicon Carbide and Related Materials 2003