Miracle-dz/UniFAR-FTUs huggingface dataset:
Teaching and Learning CS1 with an Assist of Manipulatives

Some educators make use of manipulatives for teaching Computer Science 1 (CS1) concepts in introductory programming courses. Their aim is to foster or enhance CS1 students’ comprehension, especially of the concepts that may be difficult or too abstract to comprehend. No framework validating the efficacy of using manipulatives to teach CS1 concepts could be found in the literature. The overall study is embarking on extensive research to identify and test manipulatives suitable for teaching challenging CS1 concepts with the aim of developing such a framework. However, in this paper we discuss manipulatives we used to teach and foster understanding of the assignment statement. The early results indicate the effectiveness of teaching and learning with manipulatives. This is ongoing research and more experiments to test other manipulatives will follow through our practical action research methodology.
Role of Parasitics in a Dual Active Bridge DC-DC Converter with Gallium Nitride devices

Owing to the large di/dt and dv/dt introduced by Gallium Nitride (GaN) switching devices, optimization of parasitic elements in a converter becomes very critical. This paper evaluates the impact of the parasitics of an high-frequency isolation transformer and printed circuit board (PCB) on the performance of a GaN based Dual Active Bridge isolated DC-DC converter. An iterative optimization tool is built to optimize the isolation transformer in terms of its weight and efficiency. Initial testing of the prototype revealed that parasitic elements of the PCB have adverse affects on the converter and it did not work beyond 35 VDC. Hence, based on practical results, PCB parasitic elements were optimized. With optimized layout design, converter did operate as it was intended to. However, due to excessive ringing in the switching voltages, converter efficiency was below the target efficiency (η > 90%). To eliminate this high-frequency ringing, inter-winding capacitance of the transformer was reduced by changing the winding configuration. This successfully reduced the ringing and aided the converter to reach its target efficiency.
Design and Fabrication of Multi-Layer Silicone Microchannel Cooler for High-Power Chip Array

With the development of high-power and highly-integrated microwave devices with chip array, there have been plenty of methods for high heat flux dissipation. However, the existing cooling architectures mainly focused on removal of single hot spot. For microwave devices with high-power chip array, there is a co-design of heat transfer enhancement and flow homogenization. In this study, we proposed a multi-layer silicone microchannel cooler for ${4\times 4}$ chip array cooling with heat flux of 500 $\mathbf{W}/\mathbf{cm}^{2}$. Using a finite-element simulation, the flow distribution optimization was conducted and an H-type bifurcation structure was obtained. The optimized cooler has three layers: the liquid supply layer, the liquid return layer, and the microchannel layer. The size of whole microchannel cooler ${44 \text{mm} \times 44 \text{mm} \times 1.5}$ mm. The simulated results showed that a uniform velocity and pressure distribution was achieved in ${4\times 4}$ microchannels with an average velocity of 0.8 m/s and total pressure drop of 0.42 bar under flow rate of 36 L/h. The maximum chip temperature rise above the inlet temperature is 39°C with the temperature deviation less than ${1.0\ ^{\circ}{\mathrm{C}}}$. We also fabricated a prototype of the optimized multi-layer silicone microchannel cooler using mature silicone etching and Si-Si bonding process. A thermal test system was built to evaluate the thermal performance of the cooler. The tested results showed that the maximum temperature rise was less than 40°C with the average temperature deviation less than ${\pm 5^{\circ}\mathrm{C}}$. In summary, the proposed compact multi-layer silicone microchannel cooler achieved efficient and uniform cooling of high heat-flux chip array.
Optimal Design of a Transformer-based Solid-State Pulse Modulator with a Damping Network for Ultra-Fast Rise Times

This paper presents an optimization procedure for a transformer-based solid-state pulse modulator with an additional damping network at the load. The design of the pulse transformer and the damping network are combined in the procedure, so that pulses with pulse lengths in the µs-range with a fast rise time and a compact transformer volume can be achieved.
Understanding the omnidirectional capability of a generic multi-rotor aerial vehicle

The aim of this work is to present the necessary conditions for the design of an omnidirectional Multi-Rotor Aerial Vehicle (MRAV), while taking into consideration its geometry, weight, and actuation limits. The work formally defines these conditions and presents numerical metrics that reflect the satisfaction of the omnidirectional property. These metrics are then applied to assess the omnidirectional property of “Omni-plus-seven ”, i.e., an omnidirectional MRAV consisting of a hepta-rotor with uni-directional thrusters [1]. Finally the work shows the use of such metrics in the design of a new platform with similar geometry and modified weight and actuators.
Understanding the Impact of Edge Cases from Occluded Pedestrians for ML Systems

Machine learning (ML)-enabled approaches are considered a substantial support technique of detection and classification of obstacles of traffic participants in self-driving vehicles. Major breakthroughs have been demonstrated the past few years, even covering complete end-to-end data processing chain from sensory inputs through perception and planning to vehicle control of acceleration, breaking and steering. YOLO (you-only-look-once) is a state-of-the-art perception neural network (NN) architecture providing object detection and classification through bounding box estimations on camera images. As the NN is trained on well annotated images, in this paper we study the variations of confidence levels from the NN when tested on hand-crafted occlusion added to a test set. We compare regular pedestrian detection to upper and lower body detection. Our findings show that the two NN using only partial information perform similarly well like the NN for the full body when the full body NN’s performance is 0.75 or better. Furthermore and as expected, the network, which is only trained on the lower half body is least prone to disturbances from occlusions of the upper half and vice versa.
Study on the Optimization of the Common Source Inductance for GaN Transistors

Optimization of the common source inductance of GaN-based transistors is investigated in this paper concerning different design levels, namely bond wires, package layout and PCB layout. The impact of different parameters is studied using 3D FEM field simulation. The simulation method is verified with experimental results. The contributions of bond wires, packaging and PCB layout in a half-bridge circuit to the common source inductance are separated, and a design guideline and a new chip layout are proposed to minimize the common source inductance. Final simulations show that the new chip layout is beneficial to reduce the common source inductance.
Sinusoidal-Flux Reluctance Machine Driven with Three-Phase Inverter for Improving Power Density with Reduced Torque and Input Current Ripples

Reluctance machines such as the switched reluctance machines (SRMs) and the synchronous reluctance machines (SynRMs) are recently investigated for propulsion motors of the electrified vehicles owing to their robust mechanical construction, high thermal tolerance, and cost-competitiveness. However, practical application of the reluctance machines to the vehicle propulsion has been hindered by the fact that the conventional SRMs and SynRMs are difficult to meet all the three preferable features for the vehicular application: 1. High power density, 2. Low torque and input-current ripples, 3. Being drivable by the normal three-phase inverter. This paper addresses this issue by proposing a novel reluctance machine. The prominent features of the proposed reluctance machine are the sinusoidal reluctance profile and the delta-connected phase windings, both of which differ from conventional reluctance machines. Along with the theoretical discussion of the basic operating principles of the proposed reluctance machines, this paper presents a simple performance estimation of the proposed machine, the SRM, and the SynRM, which supported that the proposed machine can meet the three preferable features. Furthermore, the experiment successfully supported the operating principles of the proposed machine, suggesting the feasibility of the proposed machine for vehicle applications.
Towards Fast and Scalable Firmware Fuzzing with Dual-Level Peripheral Modeling

Firmware vulnerabilities raise serious security concerns with the rapid growth in connected embedded devices. Fuzzing is an effective dynamic testing technique to find those vulnerabilities; however, firmware fuzzing is very limited by hardware dependence, such as on-chip and off-chip peripherals. The latest elegant approaches are making substantial progress in hardware-independent firmware fuzzing, but there is room for further improvement. We observe that hardware-independent peripheral modeling is scalable but slow at the register level; in contrast, at the abstract function level, it is fast but has limited scalability. Firmware fuzzing is still challenging in terms of achieving both scalability and efficiency. To address this problem, we present a dual-level approach that leverages register level modeling and selective function level modeling in a hybrid manner. Our method starts firmware fuzzing at the register level and connects peripheral handlers while executing hardware abstraction layer functions. We evaluate our method in terms of efficiency, scalability, and effectiveness with four real-world firmware and demonstrate the possibility of relatively fast and scalable firmware fuzzing that combines the benefits of the two levels.
Math proficiency prediction in computer-based international large-scale assessments using a multi-class machine learning model

This study examines whether a multi-class predictive machine learning model can be used to predict students’ math performance in computer-based international large-scale assessments. Raw data from the PISA 2012 computer-based assessment was used to conduct the experiments. Three-class neural network and random forest machine learning models were developed and compared in prediction performance for students’ proficiency in mathematics. The three levels of math proficiency were low, mediocre and high. Both machine learning models relied on background variables from student, parental and school questionnaires, as well as on the student math assessment data. Manual and a few automatic feature selection methods were explored while developing the machine learning models. Due to the imbalance in the three-class dataset Cohen’s Kappa coefficient and ROC AUC were used as main metrics of the model performance.
Velocity Measurement of Blast Furnace Molten Iron Based on Mixed Morphological Features of Boundary Pixel Sets

Accurately measuring the molten iron velocity at the taphole of a blast furnace is of great significance for stable operation and high-efficiency production. However, molten iron surface with sparse texture and uneven distribution of dust will affect the measurement accuracy of vision-based methods. To address these issues, a method for measuring the molten iron velocity based on the mixed morphological features of molten iron boundary is proposed. First, a detection method is developed for determining the molten iron boundary pixel sets based on the proposed modified Hough transform (HT). Then, the mixed morphological features of the molten iron boundary closely related to the velocity are extracted. Finally, the mixed morphological features are used to build an estimation model for realizing the measurement of the molten iron velocity. Industrial experiments illustrate that the proposed method can robustly and accurately measure the molten iron velocity under the interference of dust.
High-Power / High-Voltage (250 kW / 750V) SiC-Based Inverter for Electric Vehicles Applications

This paper presents the study and development of a high-power range traction inverter based on Full Silicon Carbide semiconductors. Implementing this breakthrough technology leads to an increase of the converter power density as well as its efficiency at high-frequency operation. Experimental characterization contributes to understanding of the power module switching behavior under different conditions with variation of some key parameters (gate driver resistor, load current, switching voltage, and stray inductor). Full-scale experimental results are provided to demonstrate a converter efficiency of 99% and a power density of 28 kW/L.
The Impact of Packaging Materials on Thermomechanical Reliability of FC-LGA (Flip-Chip Land Grid Array) Package for 5G Application

With the advent of the 5G era, power devices and telecom equipment require small form factor and excellent thermal performance. Flip-chip Land Grid Array (FC-LGA) is rapidly becoming the package choice for those devices, because of its low RDS (ON) and high frequency operation. However, it also brings great challenges to reliability design. Large number of flip chip solder joints between die and substrate lead to a more rigid package body, which will accumulate strong thermomechanical stress under alternating temperature and so inevitably trigger package reliability issues. Excessive warpage and body crack will occur if without appropriate package design consideration. In this study, the thermo-mechanical behaviors of FC-LGA were investigated by finite element simulation under different TCC conditions. Due to the complexity of the LGA substrate, the simulation with detail substrate model in use will incur expensive computation. This work proposed a simplification method considering a substrate of complicated structure as an equivalent anisotropic volume. With simulation models simplified, DoE study was performed to investigate the influence of packaging materials and geometry on the thermo-mechanical reliability of FC-LGA packages in high efficiency. A higher die-to-EMC thickness ratio will result in a more severe package convex warpage, while using a thinner die and a thicker EMC layer can prevent package body from cracking during heating or cooling processes. Besides packaging geometry, the influence of substrate layouts and EMC mechanical properties were also studied to find the optimal packaging design to mitigate the risks of excessive package warpage and body crack.
A Comprehensive Review on Energy Management Strategies for Electric Vehicles Considering Degradation Using Aging Models

Electrification in the transportation industry is becoming more important to face global warming and replace fossil fuels in the future. Among the available energy sources Li-ion battery and proton exchange membrane fuel cell (PEMFC) are the most promising energy sources. Therefore, employing them in fuel cell hybrid electric vehicles (FCHEVs) to combine their advantages is one of the favorable solutions. However, they still face a major challenge residing in their aging that cause the drop of system performance. On one hand, the degradation is the result of the interaction between several aging mechanisms that react differently with various operating conditions. On the other hand, a hybrid system requires an essential energy management strategy (EMS) for fuel economy and optimal power share. At the end, this EMS has an important impact on the lifetime of sources in term of reducing or favorizing the degradation. Therefore, it is important to consider the degradation in the objectives of the designed EMS. Since the degradation is usually neglected when designing an EMS, this paper tends to review the possible methods for designing a health-conscious EMS. Hence, this paper presents a summary of the main fuel cell (FC) and Li-ion battery aging mechanisms as well as the useful degradation models for state of health estimation. In addition, the existing works that consider the degradation of on-board energy sources in their approaches for increasing their durability are classified and analysed. Remaining challenges are detailed along with a discussion and outlooks about current and future trends of health-conscious EMS.
Experimental Investigation of Soft-Landing of Quadrotors via Induced Wind Modeling Approach

This paper presents an experimental study of the soft-landing problem in quadrotors using the induced wind modeling approach. The landing phase has been typically one of the critical phases in drone flight. Landing complexity drastically increases when the drone needs to land on sensitive sites, such as platforms or rack of pipes in refineries (for inspection purposes), in which explosive material is running through or there exist flammable/explosive material in the environment. Multirotor unmanned aerial vehicles (UAV s) are usually lightweight platforms and they are significantly disturbed by the aerodynamic ground effect while landing; so, near the ground, those drones are subjected to an external disturbance in proximity to the ground. In this situation, the airflow can be reflected after reaching the ground, disturbing the performance of the rotors significantly. This paper aims to model the induced wind velocity, caused by the propellers to see and consider the ground effect during the landing. The reduction of the total thrust near the ground provides a smooth landing and avoids bumping. The complex wind modeling formulation and limitation of the commercialized autopilots make the implementation a challenging task. Herein we propose how to incorporate the proposed soft-landing algorithm within an existing UA V autopilot. Experimental results show that the proposed approach successfully replicates the wind modeling which leads to a soft-landing.
A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs

On-chip memories, and in particular SRAMs, are among the most critical components in terms of data security because they might contain sensitive data such as secret keys. Whenever a tampering event is detected, one should be able to erase efficiently and rapidly the full content of a memory holding such sensitive data, but current solutions based on simple power-off lead to very long erasure times. In this paper, we present a non-invasive design technique based on an innovative mechanism to remove electric charges from SRAM bitcells still powered on, before refreshing them with a new content not correlated with the previous one. The particularity of this novel hardware countermeasure is to be natively compatible with any SRAM circuit designed from pushed-rule foundry bitcells. We have designed and characterized an 8kB SRAM in 22nm FD-SOI process technology exploiting the proposed security strategy demonstrating an erase operation accomplished in the nanosecond time scale (versus 295µs with the conventional power-off solution) at the cost of an additional area of less than 5%. We have also shown that our solution is more efficient than a solution without prior erasure consisting in writing identical data to all memory addresses in a single clock cycle (1 ns). The use of the latter drops the ratio of zeroized addresses at 92 %, while increasing the operating energy consumption by 2.1x under nominal operating conditions.
MR-CapsNet: A Deep Learning Algorithm for Image-Based Head Pose Estimation on CapsNet

Head pose estimation based on a single image is a challenging endeavor because of the complex background conditions and characteristics of the human face. In this report, we propose a Multi stage Regression-Capsule Network (MR-CapsNet) to predict head posture based on a single image input. In the study, we used the residual attention block and squeeze-and-excitation block to extract features in three levels. CapsNet overcomes the shortcomings of the traditional convolutional neural network and implements module aggregation to describe the spatial relationship of features after aggregation, in addition to realizing a compact and robust model using a multi-stage regression scheme. We tested our method on the AFLW2000 and BIWI datasets obtaining mean absolute errors of 4.26% and 3.95%, respectively. In addition, we discuss the accuracy of our method in the case of eye or mouth occlusion. The results of comprehensive experiments reveal that our method can accurately predict head posture.
A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA

A highly linear Trans-Impedance Amplifier (TIA) for 5G New Radio mobile communication receivers is presented. The TIA has a cut-off frequency programmable from 500 MHz up to 1.5 GHz. The TIA is based on a Feed-Forward compensated amplifier. To ensure stability while achieving high bandwidth and low power, an inductor is used inside the feed-forward stage. A test chip has been realized in 28 nm CMOS technology. The TIA achieves an In-band OIP3 of 32.9 dBm and the output integrated noise from 20 MHz to 1.5 GHz is lower than 300 µ Vrms with a power dissipation of 17 mW.
Research on BEOL Failures of the Chip-Package Interaction by Shear Tests of the Bumps

The continuous demand for high-speed, low-power consumption and multi-functionality of new generation electronic products has led to an exponential increase for high-yield and high-reliability packaging technologies, which has promoted the application of the 7nm node process technology to promote higher I/Os and smaller bump pitches. The advantages of copper pillar bump, which was widely used in high-density packaging, include fine pitch, high strength, low interconnection resistance, excellent electromigration performance, and lead-free packaging solutions. The low-k/ultra-low-k (LK/ULK) material medium used in back-end of the line (BEOL) can effectively reduce the parasitic capacitance without reducing the wiring density. Therefore, to improve thermomechanical and electrical performance, chips with a 42nm node and beyond usually integrate LK/ULK structure and metal line in BEOL. However, the encapsulation of the chip exceeding the 28nm node would lead to a sharp increment in the number of BEOL interconnection layers (vertical) and high-density copper traces (horizontal). The thermomechanical stress caused by the mismatch of the CTE of wafer and packaging material may cause LK/ULK delamination, bump cracks, and UBM peeling failures. Therefore, the accurate analysis and calculation of the thermomechanical stress in the film structure has always been the focus of engineering and academia. The integrity of the bumps and microstructure of BEOL can be evaluated effectively by shear test method, which was suitable for structural inspection. In this work, the shear test simulation was applied for single bump to characterize the failures of BEOL structures, e.g., fractures of ULK/LK. Owing to the fragile characteristics of LK/ULK, BEOL was susceptible to external loads. When the copper pillar bumps above BEOL were subjected to shearing forces caused by thermal mismatch, the failure would occur in some microstructures within BEOL, especially in ULK/LK interfaces. Because the bumps near die corner suffered a critical shear load, so the single bump of the aforementioned area was investigated by a shear simulation model. Studies had shown that the shear rate had less effect on the maximum shear stress, but the increment of the shear height brought about more fractures of LK, which showed that reducing the bump height helps to reduce the risk of BEOL damage under thermomechanical loads. Generally, the shear test of copper pillar bumps could effectively evaluate the strength and adhesion of the BEOL film interfaces. As an early evaluation under extreme conditions, this simulation was designed to check the integrity of ULK/LK stack film and the strength of the bump structure through the chip package interaction without underfill protection and finally find the optimal packaging solution.