Characterisation and modelling of chemical mechanical planarisation (CMP) for deep submicron integrated circuit (IC) fabrication

Chemical mechanical planarization (CMP) also known as chemical mechanical polishing has emerged as the fastest growing operation in the semiconductor manufacturing industry. It is expected to show equally explosive growth in the future [1]. CMP is the only known visible technology so far that can achieve the requirements of providing the global planarized thin film surface on wafer substrate. However, the CMP process still faces challenges such as material removal rate, uniformity of post thickness, selectivity, repeatability and defect for its successful implementation in deep submicron IC fabrication. Characterization and modeling are needed to address a variety of concerns in CMP applications. This thesis identifies and directs towards alleviating some of these major issues as highlighted in the following three paragraphs that associated with application of CMP in ultra large scale integrated (ULSI) circuit manufacturing. Beginning with the material removal rate, a wide range of new materials are expected to be employed in fabricating high-performance IC devices. Thus, this has motivated the need to verify CMP material removal rate models. Studies show the inadequacies of existing removal rate models in describing polysilicon material which is used to fill the deep trenches in bipolar complementary metal-oxide-semiconductor (BiCMOS) fabrication. A more general and versatile empirical material removal rate at the practical regime is proposed for CMP application in IC fabrication. The model is statistically evaluated by the cross-validation method which shows the predictive capability of the model. Selectivity is a crucial parameter as CMP is employed to remove more than one type of material concurrently and coupled with a wide range of pattern density. Conventional silica based slurry being unable to effectively planarize the oxide after trench filling and stopping on the silicon nitride. Therefore, reverse masking and etching are needed prior to shallow trench isolation (STI) CMP. The characterization work of direct STI CMP with ceria based slurry to eliminate non-value-added processes is reported in this thesis. Performances in terms of non-uniformity post thickness within wafer (NUWIW), non-uniformity post thickness within die (NUWID), nitride loss, dishing, roughness, metal contamination, and electrical properties of both approaches are documented. The requirement to consistently achieve the specific target mean film thickness for CMP applications is becoming more and more stringent as device geometry continues to shrink. In addition, cost and cycle time are the driving forces to avoid rework. A methodology based on contact mechanics modeling approach is developed to predict the optimal process time. It captures the variation of incoming wafer thickness, material removal rate and random behavior due to the CMP process environment. Experimental works show this approach offers better control of the average thickness for various types of devices with Cp and Cpk value above 1. Potential issues involving CMP applications in the near future advanced IC fabrication are highlighted for the first time through this contact mechanics modeling approach. VI ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library