Codesing Partitioning Using Memetic Algorithm in VLSI : A Review

The complexity and size of circuits have been rapidly rising, placing a stressing demand on industry for faster and more competent for VLSI design. If partitioning is not done in valuable manner, ignoring the parameters like firmness, time delay and robustness it may corrupt the overall performance of a design. Optimization is used to make a design particularly efficient, finding the maximum of a function. In the partitioning main objective is to minimize the number of cuts. Investigating the application of the Memetic Algorithm (MA) for solving the codesign partitioning problem can be done. © 2016 Elixir All rights reserved. Elixir Elec. Engg. 99 (2016) 43029-43031 Electrical Engineering Available online at www.elixirpublishers. com (Elixir International Journal) S. Prakasam et al./ Elixir Elec. Engg. 99 (2016) 43029-43031 43030 Reconfigurable system on chip is well known for its flexibility for high performance embedded systems [8]. Du et al., (2014) apply the SFLA algorithm to solving hardware/software partitioning problem on reconfigurable system on chip with coarse-grained. A benefit is that the potential of SFLA algorithm is substantially exploited so that we can get a short finishing time cost of the critical path. But in the future this SFLA algorithm can be improved and to be specific. Bahri et al., (2013) [9] aims to provide Hardware/Software (Hw/Sw) codesign guidelines for systemon-chip field-programmable gate array-based sensor less ac drive applications. This Hw/Sw partitioning is performed taking into account both the control requirements (bandwidth and stability margin) and the architectural constraints (e.g., available area, memory, and hardware multipliers). The proposed algorithm is an efficient to search for optimum solutions very fast and be used for functional partitioning of larger embedded systems. But the drawback is it should not find increasing attention and applications A heuristic solution is proposed by Han et al., (2013) [10] for scheduling and partitioning on multi-processor system on chips (MPSOC). In order to minimize the overall execution time, the proposed algorithm assigns different priorities to different tasks according to their out-degree and the software execution time. The scheduling algorithm can reduce unnecessary waiting time by assigning different priorities to different tasks on the basis of their out-degree and software execution time, so as to minimize the overall execution time. But this work can be extended to reduce the cost. Many types of embedded systems applications are implemented as a combination of software and hardware. For such systems the mapping of the application units into hardware and software, i.e. the partitioning process, is a key phase of the design. Although there exist techniques for partitioning, the entire process, in particular in relation to different application requirements and project constraints, is not properly supported. This leads to several unplanned iterations, redesigns and interruptions due to uncontrolled dependencies between hardware and software parts. In order to overcome these problems [11], Sapienza et al., (2013) provide a design process that enables the partitioning based on a multiple criteria decision analysis in a late design phase. From this design of an overall process suitable for enabling (i) platform independent design and reuse, and (ii) a systematic decision process to partition applications in a late stage of the design phase. But there is need for the formalization of a meta-model for enabling an accurate modeling of hardware and software components Hardware/software partitioning is a crucial problem in hardware/software co-design. Luo et al., (2012) [12] deeply investigate genetic algorithm (GA) for hardware/software partitioning, our co-design targets a heterogeneous multicore system on chip (SoC) which consists of several different types of processing engines(PE), Communicating structure adopts NOC, used GA for four task graphs to simulate the hardware/software partitioning, experiments show our method is an effective hardware/software partitioning algorithm. This algorithm will determine the best partition that minimizes the logic area. But this work can extends the system model to encompass other quality attributes, like power consumption, influence of communications, and the degree of parallelism. Mishra et al., (2012) [13] presents a framework for identifying such functions by proposing an algorithm. The framework uses the time profiling and clustering technique to achieve the objectives. Open source spark compiler has been used to convert functions to hardware description language. The final interfacing has been done in embedded development kit. The benefit in this process is that the design becomes faster although the complexity involved in the design requires more expertise. This work can be extended to improve the algorithm by more closely coupling compiler optimizations with the hardware/software partitioning Pando et al., (2013) [14] presents the results of applying a fuzzy approach to the HSP problem. This approach is more flexible than many others due to the fact that it is possible to accept quite good solutions or to reject other ones which do not seem good. The advantage of this analysis facilitates decision making in selecting the most appropriate algorithm depending on the application constraints but does not give solutions in the Pareto front. In the partitioning main objective is to minimize the number of cuts. For this, PSO algorithm is proposed is Singh et al., (2013) [15] for the optimization of VLSI interconnection (net list) bipartition. Meanwhile, the corresponding evaluation function and the operators of crossover and mutation are designed. The algorithm is implemented to test various benchmark circuits. It’s increasing in the number of iteration we can minimize the number of cuts in the different circuit series. This work algorithm can be extended by improving the techniques which provides better solution than this algorithm. Solanke et al., (2013) [16] presents framework for Research work to analyse effectiveness of System Verilog for system level modelling and Co-design. It further discusses how system Verilog can be used for modelling software components as well as hardware components of the system. One method is also proposed to carry out the Co-simulation and Codesign. Paper also discussed the expected results from the proposed work. System Verilog, will overcome the difficulties involve in traditional hardware/software codesign method and will help Design Engineers to develop the systems more accurately with minimum efforts. But the time consuming is high. Teich (2012) [17] presents major achievements of two decades of research on methods and tools for hardware/software codesign by starting with a historical survey of its roots, by highlighting its major research directions and achievements until today, and finally, by predicting in which direction research in codesign might evolve in the decades to come. In this work will provide the researches basic benefits and work of hardware/software design. The above reviews show the problems and conclusions of several literatures, different authors give various ideas to solve the codesign partitioning problem. Still there is a problem includes in codesign partitioning are high cost and execution time are directed in next section. Problems and Directions Partitioning usually consumes much time. The difficulties of partitioning are; (1). completely determines the following stages (Hardware and Software synthesis) NP-hard problem, (2). Generally made “by hand”, relying on experience. It is imperative to make it as efficient as possible to avoid costly feedbacks. Problem of VLSI circuit partitioning is non polynomial solid and cannot be effectively solved by deterministic algorithms. S. Prakasam et al./ Elixir Elec. Engg. 99 (2016) 43029-43031 43031 The problem involves isolating the circuit net list into two subsets and some of the connections (edges) are also cut. The number of edges belonging to two different partitions (Traditional and Automatic) is the cost of a partition. Traditionally partitioning was carried out manually, causing substantial delay. Automatic partitioning between hardware and software plays a key role and the results of partitioning directly affect the system area and processing time. When building embedded systems, executing functions directly in the hardware will always provide more efficient computation because of the simple fact that it avoids the overhead that software operations provide. Hard wiring functions in a device’s structure is thus preferred for its fast, however, there is a cost one has to pay: the more functions we want to apply in hardware, the bigger area of hardware needed. In real world situations, there is always a strict limit on the amount of hardware that one may use in building a single instance of an electronic device, so it is a good idea to decide on only a small subset of operations to be executed in hardware, while leaving everything else to run as software. Conclusion In advances technology, Computer Aided Design (CAD) tools play an important role in the VLSI physical design process. The physical design process is becoming increasingly complex allowing for more transistors to be integrated onto a single die. Although new techniques are continuously being investigated, the common goal of each algorithm is to produce better results in less time. Traditionally, these algorithms have been created in software due to its flexibility and ease of development. One of the drawbacks of software based programs, however, is that they execute in a sequential manner resulting in inefficient time usage. This has lead to the investigation of hardware algorithms to replace traditional software tools. As digital systems become more complex and performance criteria become more stringent, codesign wil