Miracle-dz/UniFAR-FTUs huggingface dataset:
Atomic-sized Pd Tunneling Junction Memory with 25ns Switching Capacity and Enhanced Endurance

We demonstrate an atomic-sized Pd tunneling junction memory that can operate in a vacuum, N2, or ambient environment. The device was fabricated by a simple 2-step electron-beam lithography/lift-off process and an electromigration process. Calculation based on quantum point contact model indicated the size of the tunneling gap is between 0.1 and 2nm, and the switching between high-resistance state and low-resistance state is achieved by a migration of a few atoms near the junction. The device’s RESET speed is 25ns, and the ON/OFF ratio is from 2 to 103, with an endurance of 1000 cycles. We proposed a phenomenological model to explain the reason for the imperfection of device performance, which could be useful for circuit design. It may be derived from two different migration processes, dominated by rapid changing electric field and current-induced Joule heat accumulation to affect the device performance, respectively. Compared to other reported works, our devices have the same fast RESET speed, better endurance, and potential for low power applications.
Ultra-Low-Power IoT 30nW 474mV 19 ppm/°C Voltage Reference and 2 nA 470 ppm/°C Current Reference

This paper proposes a high-precision sub-bandgap (sub-BGR) voltage reference (VR) and a temperature-compensated shared-resistive nanoampere current reference (CR) for ultra-low-power Internet of Things (IoT) devices. The CR is used to generate a bipolar junction transistor (BJT) complementary-to-absolute-temperature (CTAT) voltage, which is summed up with a proportional-to-absolute-temperature (PTAT) voltage generated using a summing network of CMOS-gate-coupled pairs. The proposed sub-BGR VR and CR are implemented in a 130 nm CMOS process. Post-layout simulations confirm the excellent performance of the second-order temperature-compensated VR across process corners with a mean temperature coefficient of 19 ppm/°C. The designed 474mV VR shows a line regulation of 0.1% N, with an overall power consumption of 30 nW.
A Self-Adaptive Wireless Network Service Embedding through SVM and MTA

Network virtualization (NV) provides a feasible mechanism for operating numerous diverse virtual networks concurrently on a shared physical infrastructure network. The key issue in NV is virtual network embedding (VNE), which efficiently and effectively maps virtualized networks (VNs) with multiple resource needs for nodes and links to the underlying physical network with limited resources. A multiple topological attributes (MTA) based embedding algorithm is proposed to address the issue of providing different virtual request ser-vices delivered in a wireless network environment, leading to an unstable utilization of physical network resources and a low access rate for subsequent requests. It is emphasized that machine learning (ML) should be integrated into the process of network slicing in order to properly classify the received wireless virtual request. In this work, virtual request services are categorized automatically using support vector machine (SVM), and resources are allocated accordingly. The proposed technique organizes nodes in the embedding process according to their priority based on multiple topological properties of virtual and physical networks. According to the findings of the simulations, the SVM-MTA algorithm enhances both the acceptance rate and the resource efficiency of the network.
Design Techniques of High Speed PHY using Highly compact FOVEROS Through Silicon Via

This paper presents the key design techniques used in a high-speed PHY in a 3D stacking SOC using FOVEROS Through Silicon Via (TSV). This IO PHY is placed in the base die of the SOC. It needed to accommodate TSV inside the PHY to connect to the package. It also needed to support uBump connectivity for its signal and power to support wafer level SORT testing. PHY also needed to accommodate Power/Ground TSV and uBump of the top die power delivery. The di/dt noise of the top die power/ground though this PHY posed a jitter coupling issue to this PHY PLL inductor. The paper discusses how effectively TSV and uBump patterns are defined inside PHY and other layout considerations are taken care of to minimize the performance impact to PHY and minimize coupling to PLL inductor from top die power di/dt and meet jitter spec.
Development of Nanocomposite Antimicrobial Polymeric Materials Containing Silver Nanoparticles

The presence of antibacterial materials in biomedicine and related fields of science and technology has become essential. Excellent antibacterial activity and low cytotoxic potential of silver nanoparticles generally depend not only on their size, but also on the distribution in matrix media. Here we show the novel aproach for synthesis of stabilized silver nanoparticles and study of functional properties of antimicrobial polymeric nanocomposite materials based on polyethylene oxide. Using the novel aproach for synthesis we recieve silver nanoparticles with average size around 8–10 nm. We found that stabilized silver nanoparticles has a significant effect on thermophysical and dielectric properties of polymer matrix at relatively low concentrations of the nanofiller (1–2 %). Nanocomposite with 1 % of silver nanoparticles shows significant activity for Klebsiella (zone of inhibition is 19 mm) and material with 2 % of silver nanoparticles shows significant activity for Staphylococcus aureus (zone of inhibition is 22 mm).
IoT-Based Aggregate Smart Grid Energy Data Extraction using Image Recognition and Partial Homomorphic Encryption

The high expense of upgrading traditional analog and digital smart grid meters with network sensor devices is a major implementation cost for collecting energy consumption statistics. A cost-effective solution for the information extraction from the meter images is to use a systematic IoT-Based periodic digital imaging methodology instead of manual reading techniques. The computations on and secrecy of the extracted energy information are enabled by the additive homomorphic nature of encryption in Paillier's cryptosystem. The encrypted data is then, retrieved via the IoT device with the image sensor installed at the industrial, commercial and residential subscriber metres. This power consumption ciphertext is subjected to decentralized progressive aggregation as it is en route online from the end user grid meter at level 0 to the level $n$ semi-trusted final collector for decryption through numerous minimum height spanning trees (MHST) constructed at $n-1$ geographic levels. The proposed scheme's robustness to replay, false data injection (FDI) attacks and data integrity are ensured by pairing based Boneh-Lynn-Shacham (BLS) short signature, time stamping and SHA-256 function. This practical technique, therefore, facilitates secure and distributed data aggregation from various sorts of users in a hierarchical fashion in an efficient manner.
Design of Differential Privacy Protection Algorithms for Cyber-Physical Systems

A new privacy Laplace common recognition algorithm is designed to protect users’ privacy data in this paper. This algorithm disturbs state transitions and information generation functions using exponentially decaying Laplace noise to avoid attacks. The mean square consistency and privacy protection performance are further studied. Finally, the theoretical results obtained are verified by performing numerical simulations.
Thermal Debonding: A Fundamental to Fanout Manufacturing

Fanout has been known to provide a more cost-effective packaging solution for advanced packaging alongside good electrical performance and flexibility, allowing multi-die and heterogeneous integration. This structure, however, has a typical process and material issue, namely die shift and warpage. Die shift is encountered several times throughout the reconstruction process and can be addressed by machine selection, process compensation, and possible design changes to allow more shift tolerance. Warpage, on the other hand, is a product of the reconstruction process, which is encountered due to the mismatch of the material properties. This is the difference in the Coefficient of Thermal Expansion between the epoxy mold compound and the silicon. Warpage is inherent to the structure resulting in manufacturing constraints in the succeeding processes. Thermal debonding is the last process step of the reconstruction flow and acts as a launchpad for RDL processing. This is where the warpage needs to be minimized to allow ease in production. Thermal debond is a fundamental process focusing on separating the wafer from the carrier. This, however, does not control the warpage. The enhanced thermal debond method must be done to not only seamlessly debond the wafer and detape the adhesive film without yield issue, it also minimizes warpage to a level that will allow wafers to run smoothly in the next machine.
Software-Defined Cognitive Radar Implementation for Spectrum Management using MATLAB

In order to test cognitive radar algorithms beyond a simulated environment, it is necessary to develop hardware in the loop (HWIL) testing environments. Findings summarized in this paper highlight salient equipment requirements, essential aspects of reconfigurable hardware programming, and design of experiments considerations for commercial-off-the-shelf (COTS) prototypical software defined radio (SDR) cognitive radar testbed development for application toward spectrum management scenarios.
Electronic technique and system for non-contact reading of temperature sensors based on piezoelectric MEMS resonators

This work investigates an electronic technique and system for non-contact reading of the temperature-dependent resonant frequency of piezoelectric MEMS resonators. The proposed approach exploits magnetic coupling between an interrogation unit and a sensor unit to achieve non-contact operation. A dedicated electronic circuit in the interrogation unit alternatively switches the system between the excitation and detection phases, thus implementing a time-gated technique. The MEMS resonator in the sensor unit is driven into resonance during the excitation phase, while its damped response is sensed in the detection phase. An electronic circuit down-mixes the damped response of the resonator and the frequency of the resulting signal is measured through a post-processing technique based on autocorrelation. The system has been applied to the reading of a temperature sensor based on a MEMS aluminum-nitride thin-film piezoelectric-on-silicon disk resonator vibrating in radial contour mode. The experimental characterization of the non-contact system determined the temperature coefficient of frequency of the MEMS resonator to be −47.4 ppm/°C, in good agreement with the measurements taken by directly probing the resonator.
A 10-mV-Startup-Voltage Thermoelectric Energy Harvesting System With a Piezoelectric Starter

An ultra-low-startup-voltage thermoelectric energy harvesting system assisted by a piezoelectric generator (PEG) is presented in this paper. When the energy harvesting system is implemented in a place where there is mechanical vibration, the associated PEG can generate a stable clock signal and drive the boost converter to start from the cold state even at extremely low thermoelectric generator (TEG) voltage. The proposed system is designed and simulated in a 180-nm BCD process. The simulations show that the proposed system can start the TEG system from the cold state from as low as 10 mV of TEG voltage while keeping a 63.9% efficiency. The peak power conversion efficiency is achieved at 74.9% when the TEG voltage is 50 mV.
Investigating Distinct Intensity Levels in Electrotactile Machine-to-Human Communication

The field of human augmentation (HA) has received an increased research focus from neurotechnologists due to advancements in information sensing and processing capabilities. Despite advancements in HA, machine-to-human communication (MHC) is still reliant on visual and auditory pathways. Electrotactile stimulation of peripheral nervous system can be used as an alternative pathway for MHC, contingent upon consistently distinct electrotactile sensations can be created. A person can be trained to associate a distinct electrotactile sensation with a specific information cue, effectively creating an alternative pathway for MHC. A technique for creating distinct electrotactile stimulation is modulating the intensity of the observed electrotactile waveform. Among the possible techniques to modify intensity, this paper investigates the possibility of manipulating a train of high-frequency pulses with the duty cycle of a superimposed mask. Furthermore, this paper explores the limits of human ability to distinguish intensity levels created through manipulation of high-frequency pulses. This paper found that using the presented frequency manipulation technique makes it possible to reliably create 3 intensity levels with an accuracy higher than 85%.
Higgs-Lepton Inflation in the Supersymmetric Minimal Seesaw Model

We investigate a scenario of cosmological inflation realised along a flat direction of the minimal seesaw model embedded in supergravity with a noncanonical R-parity violating K\"{a}hler potential. It is shown that with appropriate seesaw parameters the model is consistent with the present observation of the cosmological microwave background (CMB) as well as with the neutrino oscillation data. It is also shown that the baryon asymmetry of the Universe can be generated through leptogenesis. The model favours supersymmetry breaking with the gravitino as the lightest superparticle, and thus indicates the gravitino dark matter scenario. An interesting feature of this model is that the seesaw parameters are constrained by the CMB spectra. The 2-$\sigma$ constraints from the 9-year WMAP data yield a mild lower bound on the seesaw mass scale $\gtrsim$ TeV. We expect that the observation by the Planck satellite will soon provide more stringent constraints. The phenomenological and cosmological implications of the R-parity violation are also discussed.
Coupling Convolution, Transformer and Graph Embedding for Motor Imagery Brain-Computer Interfaces

Over the past ten years, convolution neural network (CNN) and self-attention based models (e.g., transformer) have shown extremely competitive performance in the classification of motor imagery (MI) tasks based on electroencephalogram (EEG) signals. CNN exploits local features effectively, while self-attention based models are good at capturing long-distance feature dependencies. In this paper, we propose a hybrid network structure, termed TransEEG, that takes advantage of convolutional operations and self-attention mechanisms to model both local and global dependencies for EEG signal processing. Specifically, EEG channel relationships are exploited to build a graph embedding that further improves signal classification accuracy. We evaluated the performance of TransEEG on two datasets performed MI movements. Experiments have shown that the TransEEG significantly outperformed the previous MI classification methods and achieved state-of-the-art accuracy in subject-specifical scenario.
A maximally-digital VCO-ADC with inherent mixing input capability

This work introduces a new VCO-ADC architecture. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We show in this paper that the oscillator frequency of such configuration reacts to the product of the two inputs. Therefore, the ring oscillator can be used both as a mixer and to digitally acquire the lowpass converted component. A first system-level approach is made to optimize the distortion by a proper number of taps in the ring oscillator. To confirm the system level predictions, some circuit simulations have been made. As a result, it is observed that VCO non-linearity limits the SNDR in a similar way as in conventional low pass VCOADCs. In a 65nm CMOS process, 55 dB of SNDR is achieved in a 5-MHz bandwidth for a 1 MHz downconverted signal, using a sampling clock of 2.5 GHz and input signals centered in 70 MHz and 71 MHz.
A 6.78MHz Regulating Rectifier With Constant On-Time Control for High Resolution and Ultra-Fast Transient Response

This paper presents a novel constant on-time (COT) single-stage reconfigurable regulating rectifier for wireless power transfer system. Compared with the discrete multi-cycle pulsewidth modulation technique adopting in the prior-art regulating rectifiers, the proposed rectifier achieves high regulating resolution by adjusting the duty ratio continuously and smoothly. In addition, the load-transient response is much faster with the COT control method. In order to optimize the output voltage ripples, the regulating cycle is designed to be small via minimizing the on-time. This single-stage wireless power receiver is designed in a 0.18$\mu$m BCD process, and regulates an output voltage of 5V. Simulation results show that the maximum output power is 850mW with a peak efficiency of 93.2% and a minimum regulating cycle of 0.12$\mu$s. For a load switching between 50mA and 170mA, the response of the proposed rectifier is instant with the unnoticeable overshoot and undershoot.
Chinese Society of Clinical Oncology (CSCO) diagnosis and treatment guidelines for colorectal cancer 2018 (English version)

3. Treatment principles for colon cancer 3.1 Treatment of non-metastatic colon cancer 3.1.1 Treatment of resectable colon cancer 3.1.1.1 Endoscopic treatment 3.1.1.2 Surgical treatment and postoperative adjuvant treatment 3.1.1.3 Annex: Commonly used adjuvant chemotherapy regimens after colectomy 3.1.2 Treatment of unresectable colon cancer 3.2 Treatment principles for metastatic colon cancer 3.2. 1 Synchronous metastatic colon cancer 3.2. 1.1 Treatment of initially resectable metastatic colon cancer 3.2. 1.2 Treatment of initially unresectable metastatic colon cancer 3.2. 2 Treatment of postoperative recurrence in metastatic colon cancer 3.2. 3 Annex: Commonly used systemic therapy regimens for metastatic colorectal cancer 3.3 Colon cancer follow-up
A 100dB-TCMRR 8-Channel Bio-Potential Front-End with Multi-Channel Common-Mode Replication

For a multichannel bio-potential signal acquisition front-end, it's total CMRR (TCMRR) is restricted by these three factors: the inherent CMRR (ICMRR) of the amplifier used in the acquisition front-end, the impedance mismatch of electrodes, and the systematic mismatch due to the shared reference electrode. This paper presents a 8-channel bio-potential front-end with multi-channel common-mode replication(MC-CMR). The frontend has been implemented in a standard CMOS 0.18-$\mu$m process, and the measurement results show that the amplifier has an adjustable gain of 46 to 64 dB, the input reference noise within 1Hz to 1k Hz is 1.62$\mu \mathrm{V}_{\mathrm{r}\mathrm{m}\mathrm{s}}$, TCMRR of the front-end is 100dB (at 50Hz). A single channel consumes 1.86$\mu$A at 1. 8V supply voltage, and the NEF is 2.7.
Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation

This paper presents a tiny charge injection-Successive Approximation (ci-SAR) A/D converter (ADC) to be integrated at the periphery of analog Matrix Vector Multiplication (MVM) accelerators for Deep Neural Network (DNN) inference. Derived from the ci-SAR ADC, this converter exploits a single charge injecting cell to minimize area and energy consumption. The ADC exhibits a signal-to-noise and distortion ratio of 30.5 dB, at 5 bits of nominal resolution. The energy per conversion is 86 fJ, running at 34 MS/s, with a silicon area of $75 \mu m ^{2}$, in 22 nm technology node. From the results of our analytical framework, an SRAM-based Analog in-Memory Compute (AiMC) array, including the proposed ADC at 5 bits of resolution, can achieve an energy efficiency of 1650 TOPs/W.
A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input

An 86.6-dB SFDR, 1-GS/s differential bootstrap sampler in a 0.18-um SiGe BiCMOS technology is presented. The performance is achieved using an amplitude-modulated bootstrap circuit. The results show 14-bit linearity over nearly 500-MHz bandwidth, while consuming less power compared to a conventional MOSFET switched-capacitor bootstrap circuit due to less parasitic capacitance and the use of high ft HBT.
Development of a Variety of Fast Machine Learning Model for ECG-based Arrhythmia Classifier

Although deep learning has been proving its capability in various fields, training and testing by learning a large amount of data and deep neural networks remain time consuming. To address this issue, a high-performance GPU and CPU, SSD storage, and a large amount of RAM is required, which is expensive. We propose a new classifier algorithm by feature point extraction that can be trained and tested quickly. The performance of the proposed algorithm was verified by classifying heart diseases by applying the MIT-BIH arrhythmia data set. First, the noise was removed by Wavelet transform, and feature points were extracted using root mean square (RMS), crest factor, margin factor, form factor, kurtosis, and pulse factor. Then, the performance was compared using various classification algorithms. The two feature extraction methods are compared to evaluate the accuracy of each algorithm, the execution time of the model during training, and the memory usage. Our proposed algorithm is applied to various health care systems such as heart disease and depression, and it is predicted that it will be able to help users toward health care at low cost.
Widely-Tunable RF Receiver Employing Synthetic Diversity for Interference Mitigation

This paper presents a novel technique for suppression of in-band artifacts from out-of-band (OOB) interference in widely tunable RF receivers. The technique employs a multi-tap inductor-capacitor network (LCN) to generate diversity in gain and phase between taps across the targeted frequency range. Using this network to feed a bank of identical receivers sharing a single local oscillator (LO) allows multiple kinds of interferer artifact to be suppressed. Here we considered spur-induced and phase noise-induced artifacts. In each case, the resulting artifacts are linearly separable from signal when the outputs of the sub-receivers are recombined. AC and transient simulations were first performed to show feasibility of the proposed approach. A prototype was implemented in 45nm CMOS which confirmed the validity of the synthetic diversity (SD) approach for suppressing interferer artifacts, showing a maximum lowering in EVM and BER of 38% and 60% respectively.
A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation

This paper presents a second-order VCO-based $\Delta\Sigma$ ADC with a fully digital feedback adder, which is highly digital, area efficient and low power. Both the first and second loop integrator are implemented by VCOs and are free of OTA. A novel digital adder is proposed to realize the secondary feedback, significantly reducing the power and area of the second stage. The proposed ADC is designed in a 28nm CMOS technology under 0.9V supply, consuming only 1.14mW. The simulated SNDR and SFDR are 72.5dB and 84.1dB respectively over a 5MHz signal bandwidth.
High-Pass Sigma–Delta Modulator with Operational Amplifier Sharing and Noise-Coupling Technique for Biomedical Signal Acquisition

A 3rd-order feedforward high-pass sigma-delta modulator (HPSDM) with operational amplifier (op-amp) sharing and noise-coupling techniques is presented in this paper. The modulator is suitable for biomedical signal acquisition with features of high resolution and low power consumption. Op-amp sharing technique has been utilized to reduce the number of amplifiers. To add an additional noise-shaping order, the noise-coupling technique is embedded in the summing stage without additional amplifier. To overcome the circuit sensitivity to process variation and capacitor mismatch, a new high-pass integrator structure is proposed. Simulation results reveal a Signal-to-Noise and Distortion Ratio (SNDR) of 79.64 dB consuming 1.31 $\mu$W under 1.2 V supply voltage, which can achieve peak Schreier Figure-of-Merit (FoM) of 161.64 dB and peak Walden FoM of 0.4 pJ/conv.