Miracle-dz/UniFAR-FTUs huggingface dataset:
N-Myristoyltransferase, a Potential Antifungal Candidate Drug-Target for Aspergillus flavus

As an opportunistic pathogen, A. flavus causes crop loss due to fungal growth and mycotoxin contamination. Investigating the role of virulence factors during infection and searching for novel drug targets have been popular scientific topics in the field of fungal control. Nmt has become a potential target in some organisms. ABSTRACT The filamentous fungus Aspergillus flavus causes devastating diseases not only to cash crops but also to humans by secreting a series of secondary metabolites called aflatoxins. In the cotranslational or posttranslational process, N-myristoyltransferase (Nmt) is a crucial enzyme that catalyzes the myristate group from myristoyl-coenzyme A (myristoyl-CoA) to the N terminus or internal glycine residue of a protein by forming a covalent bond. Members of the Nmt family execute a diverse range of biological functions across a broad range of fungi. However, the underlying mechanism of AflNmt action in the A. flavus life cycle is unclear, particularly during the growth, development, and secondary metabolic synthesis stages. In the present study, AlfNmt was found to be essential for the development of spore and sclerotia, based on the regulation of the xylose-inducible promoter. AflNmt, located in the cytoplasm of A. flavus, is also involved in modulating aflatoxin (AFB1) in A. flavus, which has not previously been reported in Aspergillus spp. In addition, we purified, characterized, and crystallized the recombinant AflNmt protein (rAflNmt) from the Escherichia coli expression system. Interestingly, the crystal structure of rAlfNmt is moderately different from the models predicted by AlphaFold2 in the N-terminal region, indicating the limitations of machine-learning prediction. In conclusion, these results provide a molecular basis for the functional role of AflNmt in A. flavus and structural insights concerning protein prediction. IMPORTANCE As an opportunistic pathogen, A. flavus causes crop loss due to fungal growth and mycotoxin contamination. Investigating the role of virulence factors during infection and searching for novel drug targets have been popular scientific topics in the field of fungal control. Nmt has become a potential target in some organisms. However, whether Nmt is involved in the developmental stages of A. flavus and aflatoxin synthesis, and whether AlfNmt is an ideal target for structure-based drug design, remains unclear. This study systematically explored and identified the role of AlfNmt in the development of spore and sclerotia, especially in aflatoxin biosynthesis. Moreover, although there is not much difference between the AflNmt model predicted using the AlphaFold2 technique and the structure determined using the X-ray method, current AI prediction models may not be suitable for structure-based drug development. There is still room for further improvements in protein prediction.
In Vitro Activity of Cefepime-Taniborbactam and Comparators against Clinical Isolates of Gram-Negative Bacilli from 2018 to 2020: Results from the Global Evaluation of Antimicrobial Resistance via Surveillance (GEARS) Program

Taniborbactam is a novel cyclic boronate β-lactamase inhibitor in clinical development in combination with cefepime. We assessed the in vitro activity of cefepime-taniborbactam and comparators against a 2018–2020 collection of Enterobacterales (n = 13,731) and Pseudomonas aeruginosa (n = 4,619) isolates cultured from infected patients attending hospitals in 56 countries. ABSTRACT Taniborbactam is a novel cyclic boronate β-lactamase inhibitor in clinical development in combination with cefepime. We assessed the in vitro activity of cefepime-taniborbactam and comparators against a 2018–2020 collection of Enterobacterales (n = 13,731) and Pseudomonas aeruginosa (n = 4,619) isolates cultured from infected patients attending hospitals in 56 countries. MICs were determined by CLSI broth microdilution. Taniborbactam was tested at a fixed concentration of 4 μg/mL. Isolates with cefepime-taniborbactam MICs of ≥16 μg/mL underwent whole-genome sequencing. β-lactamase genes were identified in meropenem-resistant isolates by PCR/Sanger sequencing. Against Enterobacterales, taniborbactam reduced the cefepime MIC90 value by >64-fold (from >16 to 0.25 μg/mL). At ≤16 μg/mL, cefepime-taniborbactam inhibited 99.7% of all Enterobacterales isolates; >97% of isolates with multidrug-resistant (MDR) and ceftolozane-tazobactam-resistant phenotypes; ≥90% of isolates with meropenem-resistant, difficult-to-treat-resistant (DTR), meropenem-vaborbactam-resistant, and ceftazidime-avibactam-resistant phenotypes; 100% of VIM-positive, AmpC-positive, and KPC-positive isolates; 98.7% of extended-spectrum β-lactamase (ESBL)-positive; 98.8% of OXA-48-like-positive; and 84.6% of NDM-positive isolates. Against P. aeruginosa, taniborbactam reduced the cefepime MIC90 value by 4-fold (from 32 to 8 μg/mL). At ≤16 μg/mL, cefepime-taniborbactam inhibited 97.4% of all P. aeruginosa isolates; ≥85% of isolates with meropenem-resistant, MDR, and meropenem-vaborbactam-resistant phenotypes; >75% of isolates with DTR, ceftazidime-avibactam-resistant, and ceftolozane-tazobactam-resistant phenotypes; and 87.4% of VIM-positive isolates. Multiple potential mechanisms, including carriage of IMP, certain alterations in PBP3, permeability (porin) defects, and possibly, upregulation of efflux were present in most isolates with cefepime-taniborbactam MICs of ≥16 μg/mL. We conclude that cefepime-taniborbactam exhibited potent in vitro activity against Enterobacterales and P. aeruginosa and inhibited most carbapenem-resistant isolates, including those carrying serine carbapenemases or NDM/VIM metallo-β-lactamases (MBLs).
LdtC Is a Key l,d-Transpeptidase for Peptidoglycan Assembly in Mycobacterium smegmatis

Mycobacteria have several enzymes to catalyze nonclassical 3-3 linkages in the cell wall peptidoglycan. Understanding the biology of these cross-links is important for the development of antibiotic therapies to target peptidoglycan biosynthesis. Our work provides evidence that LdtC can function as the sole enzyme for 3-3 cross-link formation in M. smegmatis and suggests that LdtC may be part of a carbapenem-resistant l,d-transpeptidase pathway. ABSTRACT The peptidoglycan of mycobacteria has two types of direct cross-links, classical 4-3 cross-links that occur between diaminopimelate (DAP) and alanine residues, and nonclassical 3-3 cross-links that occur between DAP residues on adjacent peptides. The 3-3 cross-links are synthesized by the concerted action of d,d-carboxypeptidases and l,d-transpeptidases (Ldts). Mycobacterial genomes encode several Ldt proteins that can be classified into six classes based upon sequence identity. As a group, the Ldt enzymes are resistant to most β-lactam antibiotics but are susceptible to carbapenem antibiotics, with the exception of LdtC, a class 5 enzyme. In previous work, we showed that loss of LdtC has the greatest effect on the carbapenem susceptibility phenotype of Mycobacterium smegmatis (also known as Mycolicibacterium smegmatis) compared to other ldt deletion mutants. In this work, we show that a M. smegmatis mutant lacking the five ldt genes other than ldtC has a wild-type phenotype with the exception of increased susceptibility to rifampin. In contrast, a mutant lacking all six ldt genes has pleiotropic cell envelope defects, is temperature sensitive, and has increased susceptibility to a variety of antibiotics. These results indicate that LdtC is capable of functioning as the sole l,d-transpeptidase in M. smegmatis and suggest that it may represent a carbapenem-resistant pathway for peptidoglycan biosynthesis. IMPORTANCE Mycobacteria have several enzymes to catalyze nonclassical 3-3 linkages in the cell wall peptidoglycan. Understanding the biology of these cross-links is important for the development of antibiotic therapies to target peptidoglycan biosynthesis. Our work provides evidence that LdtC can function as the sole enzyme for 3-3 cross-link formation in M. smegmatis and suggests that LdtC may be part of a carbapenem-resistant l,d-transpeptidase pathway.
Design Space and Memory Technology Co-exploration for In-Memory Computing Based Machine Learning Accelerators

In-Memory Computing (IMC) has become a promising paradigm for accelerating machine learning (ML) inference. While IMC architectures built on various memory technologies have demonstrated higher throughput and energy efficiency compared to conventional digital architectures, little research has been done from system-level perspective to provide comprehensive and fair comparisons of different memory technologies under the same hardware budget (area). Since large-scale analog IMC hardware relies on the costly analog-digital converters (ADCs) for robust digital communication, optimizing IMC architecture performance requires synergistic co-design of memory arrays and peripheral ADCs, wherein the trade-offs could depend on the underlying memory technologies. To that effect, we co-explore IMC macro design space and memory technology to identify the best design point for each memory type under iso-area budgets, aiming to make fair comparisons among different technologies, including SRAM, phase change memory, resistive RAM, ferroelectrics and spintronics. First, an extended simulation framework employing spatial architecture with off-chip DRAM is developed, capable of integrating both CMOS and nonvolatile memory technologies. Subsequently, we propose different modes of ADC operations with distinctive weight mapping schemes to cope with different on-chip area budgets. Our results show that under an iso-area budget, the various memory technologies being evaluated will need to adopt different IMC macro-level designs to deliver the optimal energy-delay-product (EDP) at system level. We demonstrate that under small area budgets, the choice of best memory technology is determined by its cell area and writing energy. While area budgets are larger, cell area becomes the dominant factor for technology selection.
Gzippo: Highly-compact Processing-In-Memory Graph Accelerator Alleviating Sparsity and Redundancy

Graph application plays a significant role in real-world data computation. However, the memory access patterns become the performance bottleneck of the graph applications, which include low compute-to-communication ratio, poor temporal locality, and poor spatial locality. Existing RRAM-based processing-in-memory accelerators reduce the data movements but fail to address both sparsity and redundancy of graph data. In this work, we present Gzippo, a highly-compact design that supports graph computation in the compressed sparse format. Gzippo employs a tandem-isomorphic-crossbar architecture both to eliminate redundant searches and sequential indexing during iterations, and to remove sparsity leading to non-effective computation on zero values. Gzippo achieves a 3.0× (up to 17.4×) performance speedup, 23.9× (up to 163.2×) energy efficiency over state-of-the-art RRAM-based PIM accelerator, respectively.
Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit Simulation

A number of sparse linear systems are solved by sparse LU factorization in a circuit simulation process. The coefficient matrices of these linear systems have the identical structure but different values. Pivoting is usually needed in sparse LU factorization to ensure the numerical stability, which leads to the difficulty of predicting the exact dependencies for scheduling parallel LU factorization. However, the matrix values usually change smoothly in circuit simulation iterations, which provides the potential to "guess" the dependencies. This work proposes a novel parallel LU factorization algorithm with pivoting reduction, but the numerical stability is equivalent to LU factorization with pivoting. The basic idea is to reuse the previous structural and pivoting information as much as possible to perform highly-scalable parallel factorization without pivoting, which is scheduled by the "guessed" dependencies. Once a pivot is found to be too small, the remaining matrix is factorized with pivoting in a pipelined way. Comprehensive experiments including comparisons with state-of-the-art CPU- and GPU-based parallel sparse direct solvers on 66 circuit matrices and real SPICE DC simulations on 4 circuit netlists reveal the superior performance and scalability of the proposed algorithm. The proposed solver is available at https://github.com/chenxm1986/cktso.
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures

Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of unmodified binaries. However, DBT systems face correctness and performance challenges, when emulating concurrent binaries from strong to weak memory consistency architectures. As a matter of fact, we report several translation errors in QEMU, when emulating x86 binaries on Arm hosts. To address these challenges, we propose an end-to-end approach that provides correct and efficient emulation for weak memory model architectures. Our contributions are twofold: we formalize QEMU’s intermediate representation’s memory model, and use it to propose formally verified mapping schemes to bridge the strong-on-weak memory consistency mismatch. Secondly, we implement these verified mappings in Risotto, a QEMU-based DBT system that optimizes memory fence placement while ensuring correctness. Risotto further enhances the emulation performance via cross-architecture dynamic linking of native shared libraries, and fast and correct translation of compare-and-swap operations. We evaluate Risotto using multi-threaded benchmark suites and real-world applications, and show that Risotto improves the emulation performance by 6.7% on average over ”erroneous” QEMU, while ensuring correctness.
WSQ-AdderNet: Efficient Weight Standardization based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization

Convolutional neural networks (CNNs) have been widely adopted for various machine intelligence tasks. Nevertheless, CNNs are still known to be computational demanding due to the convolutional kernels involving expensive Multiply-ACcumulate (MAC) operations. Recent proposals on hardware-optimal neural network architectures suggest that AdderNet with a lightweight ℓ1-norm based feature extraction kernel can be an efficient alternative to the CNN counterpart, where the expensive MAC operations are substituted with efficient Sum-of-Absolute-Difference (SAD) operations. Nevertheless, it lacks an efficient hardware implementation methodology for AdderNet as compared to the existing methodologies for CNNs, including efficient quantization, full-integer accelerator implementation, and judicious resource utilization of DSP slices of FPGA devices. In this paper, we present WSQ-AdderNet, a generic framework to quantize and optimize AdderNet-based accelerator designs on embedded FPGA devices. First, we propose a weight standardization technique to facilitate weight quantization in AdderNet. Second, we demonstrate a full-integer quantization hardware implementation strategy, including weight and activation quantization methodologies. Third, we apply DSP packing optimization to maximize the DSP utilization efficiency, where Octo-INT8 can be achieved via DSP-LUT co-packing. Finally, we implement the design using Xilinx Vitis HLS (high-level synthesis) and Vivado to Xilinx Kria KV-260 FPGA. Our experimental results of ResNet-20 using WSQ-AdderNet demonstrate that the implementations achieve 89.9% inference accuracy with INT8 implementation, which shows little performance loss as compared to the FP32 and INT8 CNN designs. At the hardware level, WSQ-AdderNet achieves up to 3.39× DSP density improvement with nearly the same throughput as compared to INT8 CNN design. The reduction in DSP utilization makes it possible to deploy large network models on resource-constrained devices. When further scaling up the PE sizes by 39.8%, WSQ-AdderNet can achieve 1.48× throughput improvement while still achieving 2.42× DSP density improvement.
Erms: Efficient Resource Management for Shared Microservices with SLA Guarantees

A common approach to improving resource utilization in data centers is to adaptively provision resources based on the actual workload. One fundamental challenge of doing this in microservice management frameworks, however, is that different components of a service can exhibit significant differences in their impact on end-to-end performance. To make resource management more challenging, a single microservice can be shared by multiple online services that have diverse workload patterns and SLA requirements. We present an efficient resource management system, namely Erms, for guaranteeing SLAs in shared microservice environments. Erms profiles microservice latency as a piece-wise linear function of the workload, resource usage, and interference. Based on this profiling, Erms builds resource scaling models to optimally determine latency targets for microservices with complex dependencies. Erms also designs new scheduling policies at shared microservices to further enhance resource efficiency. Experiments across microservice benchmarks as well as trace-driven simulations demonstrate that Erms can reduce SLA violation probability by 5× and more importantly, lead to a reduction in resource usage by 1.6×, compared to state-of-the-art approaches.
Stability and Explanatory Significance of Some Simple Evolutionary Models

The explanatory significance of equilibrium depends on the underlying dynamics. A number of questions of stability and robustness are relevant. Here I investigate these questions with respect to some simple evolutionary models from my book, Evolution of the Social Contract. These models use the replicator dynamics. In each of these models I identify the equilibria and characterize their local dynamic stability properties. In two of the models, I show that one equilibrium is globally asymptotically stable. I then show that the foregoing results are robust over a large class of adaptive dynamics that might be considered as alternatives to the replicator dynamics. I investigate the structural stability properties of the three models. The question of the structural stability of a model of bargaining with correlated encounters raised by D'Arms, Batterman, and Górny (1998) is answered in the affirmative. The other two models are not structurally stable. Modification of a structurally unstable signaling system to allow for correlated encounters results in a structurally stable model.
Piezoelectric doping and elastic strain relaxation in AlGaN–GaN heterostructure field effect transistors

We calculate the sheet electron density induced by the piezoelectric effect in AlxGa1−xN–GaN heterostructure field effect transistors. This density is limited by the elastic strain relaxation, which depends on AlGaN barrier layer thickness and on the Al molar fraction in the barrier layer. Piezoelectric doping is more important in structures with larger Al content and thinner barrier layers. These results agree with our experimental data.
Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet

Cache coherence overhead in manycore systems is becoming prominent with the increase of system scale. However, traditional electrical networks restrict the efficiency of cache coherence transactions in the system due to the limited bandwidth and long latency. Optical network promises high bandwidth and low latency, and supports both efficient unicast and multicast transmission, which can potentially accelerate cache coherence in manycore systems. This work proposes a novel photonic cache coherence network with a physically centralized logically distributed directory called PCCN for chiplet-based manycore systems. PCCN adopts a channel sharing method with a contention solving mechanism for efficient long-distance coherence-related packet transmission. Experiment results show that compared to state-of-the-art proposals, PCCN can speed up application execution time by 1.32x, reduce memory access latency by 26%, and improve energy efficiency by 1.26x, on average, in a 128-core system.
Superfast Full-Scale GPU-Accelerated Global Routing

Global routing is an essential step in physical design. Recently there are works on accelerating global routers using GPU. However, they only focus on certain stages of global routing, and have limited overall speedup. In this paper, we present a superfast full-scale GPU-accelerated global router and introduce useful parallelization techniques for routing. Experiments show that our 3D router achieves both good quality and short runtime compared to other state-of-the-art academic global routers.
QCiR: Pattern Matching Based Universal Quantum Circuit Rewriting Framework

Due to multiple limitations of quantum computers in the NISQ era, quantum compilation efforts are required to efficiently execute quantum algorithms on NI SQ devices Program rewriting based on pattern matching can improve the generalization ability of compiler optimization. However, it has rarely been explored for quantum circuit optimization, further considering physical features of target devices.In this paper, we propose a pattern-matching based quantum circuit optimization framework QCiR with a novel pattern description format, enabling the user-configured cost model and two categories of patterns, i.e., generic patterns and folding patterns. To get better compilation latency, we propose a DAG representation of quantum circuit called QCir-DAG, and QVF algorithm for subcircuit matching. We implement continuous single-qubit optimization pass constructed by QCiR, achieving 10% and 20% optimization rate for benchmarks from Qiskit and ScaffCC, respectively. The practicality of QCiR is demonstrated by execution time and experimental results on the quantum simulator and quantum devices.
Logic Synthesis for Digital In-Memory Computing

Processing in-memory is a promising solution strategy for accelerating data-intensive applications. While analog in-memory computing is extremely efficient, the limited precision is only acceptable for approximate computing applications. Digital in-memory computing provides the deterministic precision required to accelerate high assurance applications. State-of-the-art digital in-memory computing schemes rely on manually decomposing arithmetic operations into in-memory compute kernels. In contrast, traditional digital circuits are synthesized using complex and automated design flows. In this paper, we propose a logic synthesis framework called LOGIC for mapping high-level applications into digital in-memory compute kernels that can be executed using non-volatile memory. We first propose techniques to decompose element-wise arithmetic operations into in-memory kernels while minimizing the number of in-memory operations. Next, the sequence of the in-memory operation is optimized to minimize non-volatile memory utilization. Lastly, data layout re-organization is used to efficiently accelerate applications dominated by sparse matrix-vector multiplication operations. The experimental evaluations show that the proposed synthesis approach improves the area and latency of fixed-point multiplication by 77% and 20% over the state-of-the-art, respectively. On scientific computing applications from Suite Sparse Matrix Collection, the proposed design improves the area, latency and, energy by 3.6X, 2.6X, and 8.3X, respectively.