An Innovative Approach to Detect Glitches in Hardware Implementations on FPGAs

AN INNOVATIVE APPROACH TO DETECT GLITCHES IN HARDWARE IMPLEMENTATIONS ON FPGAS Kinjalben Shah, MS George Mason University, 2013 Thesis Director: Dr. Jens-Peter Kaps Glitches are unproductive signal transitions due to unbalanced path delays at the inputs of a gate. Unlike asynchronous circuits, the functionality of synchronous circuits is not significantly affected by the presence of glitches. Despite of that, detection of glitches in synchronous designs is important because the number of transitions increases due to glitches and the dynamic power dissipation linearly depends on the number of transitions. Glitches contribute to the dynamic power which itself is a major portion of the total power consumed by the design. Consequently, in presence of glitches, the overall power dissipation of the design increases. With the increased use of small battery powered devices, low power consumption has become a highly important concern for the designs. Many advantages of FPGAs like rapid prototyping, low cost and field re-programmability are offset by higher power consumption than ASICs. Therefore, detecting glitches that occur in FPGA designs is important in order to understand how much power is consumed by glitches. The accuracy of the post place and route simulation mainly depends on the simulation model for a given family of FPGAs and does not take process variations into account. Therefore, simulation might not detect all the glitches in the design. This research provides a novel approach for glitch detection in hardware implementations on FPGAs. We designed a circuit that does not merely detect the presence of glitches or counts the number of spurious transitions that a glitch causes, our circuit also captures the glitch waveform and provides information about the position and the width of glitches. We also propose a methodology to increase the resolution of the captured waveform. From our proposed glitch detection method we can reliably reproduce the glitch waveform and can detect glitches with a width of as small as 324 ps on Spartan-3E FPGA. Chapter 1: Introduction Field Programmable Gate Arrays (FPGAs) are highly desirable for the implementation of digital systems due to their flexibility and low time-to-market. FPGAs have many more advantages, such as rapid prototyping, field re-programmability, growing density and speed, simple design cycle and low cost for small volume, which makes them more viable alternative for many of the current Application Specific Integrated Chip (ASIC) applications. However, the advantages of FPGAs are offset by higher power consumption than ASICs. It is estimated that an FPGA design consumes overall 10 times more power than a functionally equivalent ASIC design [1]. 1.1 Power in Digital Circuits Power has become a significant design constraint in digital designs due to the demand of battery-powered devices in personal wireless communications and other portable digital applications. If advantages of FPGAs are to be fully exploited, the amount of power they consume must be reduced or carefully controlled. High power dissipation causes overheating, which degrades performance and reduces chip lifetime. To control their temperature levels, high power chips require specialized and expensive packaging and heat-sink arrangements. Reducing the power consumption of FPGAs leads to lower packaging and cooling costs as well as improved reliability. For any Complementary Metal-Oxide Semiconductor (CMOS) circuit, total power consumption can be divided into two sources of power: 1. Static Power Consumption 2. Dynamic Power Consumption