Modeling methodologies for multi level PCB-package co-simulation & co-design

Summary form only given. The continuous demand on wide bandwidth and high-speed data rate is pushing the signal spectra to be considered in simulations at the stage of 50GHz and beyond. Data rate through backplane is developing at 15Gbps and the next generation is targeted at 25Gbps. At such high data rates with extra wide frequency spectra for signals, lots of challenges are brought into the system level simulations including affordable simulation time, computational resources and required accuracy. Time to market is critical in industry due to the market share while products are outdated very quickly. Minimum simulation time is always desired and appreciated. The minimum simulation time is related to the available computational resources, simulation tools and the requirement on accuracy. For a system with above given conditions, which are the most cases in product development in the industry, the simulation time is solely dependent on modeling methodology, which is the key in system level simulation. Package and printed circuit board (PCB) co-design is common in system analysis for the prediction of high-speed channel performance. In recent times, chip companies have been closely looking into package and PCB co-simulations in order to guarantee the performances of these chips at the system level. However, full-wave package and PCB co-simulation can be challenging: if the package and the PCB are modeled together, the co-simulation is limited by either available computational resource, due to the extremely large memory consumption, or by affordable simulation time. The current, widely adopted method in industry, for PCB and package co-simulation, is to model them separately. There has been some investigation of where to separate/segment the PCB and package and build a reference plane; however, in most of the cases, only very simple models are used to verify the proposed methods. It is known that the reference plane is critical to the simulation results of the entire channel and it is recognized that a transversal electromagnetic wave (TEM) wave is required at the reference plane so that the current and voltage are well defined. Unfortunately, this is sometimes challenging due to the complexity of the structure and the port definition in most of the commercial Electromagnetic (EM) tools. This paper investigates these details on a realistic test structure and gives some general solution for PCB and package system co-simulation. The model under test consists of a 10 layers PCB in standard FR4 material with εr=4.5 and tgδ=0.035 at 1GHz. The package is 8 layers flip chip technology, εr=3.32 and tgδ=0.0175 at 1GHz. Due to the complexity and the high density of the nets routing, waveguide ports cannot be used. Therefore, in order to mimic a port set up as close as possible to TEM wave propagation, a virtual reference plane is used and the port is defined by a small port source gap between the end of a bump and/or pin and the metal sheet which acts as the virtual ground plane. Results of the proposed methodology applied to the partitioned model of PCB and package are compared with the 3D EM simulation of the full model and validated with measurements up to 40GHz. Other two modeling techniques are also investigated. In the first one, the GND layers are slightly extended and the ports are located inside the ground planes. In the second one, the ports are defined at the ground plane edges and a small gap is added between the boundaries and the truncated area. Details will be provided in the presentation. Very good agreement can be observed when comparing the S-parameters of the cascaded models with the S-parameters of the full model. The proposed techniques greatly simplified the co-design process and reduce the simulation time up to 5X, therefore they can be easily extended to study the influence of the PCB effects, such as PCB via length, trace routing, and escape area definition.