Miracle-dz/UniFAR-FTUs huggingface dataset:
ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited

This paper presents an enhanced version of a scalable HLS (High-Level Synthesis) framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models to highly-efficient and synthesizable C++ designs. The original version of ScaleHLS achieved significant speedup on both C/C++ kernels and PyTorch models [14]. In this paper, we first highlight the key features of ScaleHLS on tackling the challenges present in the representation, optimization, and exploration of large-scale HLS designs. To further improve the scalability of ScaleHLS, we then propose an enhanced HLS transform and analysis library supported in both C++ and Python, and a new design space exploration algorithm to handle HLS designs with hierarchical structures more effectively. Comparing to the original ScaleHLS, our enhanced version improves the speedup by up to 60.9× on FPGAs. ScaleHLS is fully open-sourced at https://github.com/hanchenye/scalehls.
A Deep Graph Network with Multiple Similarity for User Clustering in Human–Computer Interaction

User counterparts, such as user attributes in social networks or user interests, are the keys to more natural Human–Computer Interaction (HCI). In addition, users’ attributes and social structures help us understand the complex interactions in HCI. Most previous studies have been based on supervised learning to improve the performance of HCI. However, in the real world, owing to signal malfunctions in user devices, large amounts of abnormal information, unlabeled data, and unsupervised approaches (e.g., the clustering method) based on mining user attributes are particularly crucial. This paper focuses on improving the clustering performance of users’ attributes in HCI and proposes a deep graph embedding network with feature and structure similarity (called DGENFS) to cluster users’ attributes in HCI applications based on feature and structure similarity. The DGENFS model consists of a Feature Graph Autoencoder (FGA) module, a Structure Graph Attention Network (SGAT) module, and a Dual Self-supervision (DSS) module. First, we design an attributed graph clustering method to divide users into clusters by making full use of their attributes. To take full advantage of the information of human feature space, a k-neighbor graph is generated as a feature graph based on the similarity between human features. Then, the FGA and SGAT modules are utilized to extract the representations of human features and topological space, respectively. Next, an attention mechanism is further developed to learn the importance weights of different representations to effectively integrate human features and social structures. Finally, to learn cluster-friendly features, the DSS module unifies and integrates the features learned from the FGA and SGAT modules. DSS explores the high-confidence cluster assignment as a soft label to guide the optimization of the entire network. Extensive experiments are conducted on five real-world data sets on user attribute clustering. The experimental results demonstrate that the proposed DGENFS model achieves the most advanced performance compared with nine competitive baselines.
Architecting DDR5 DRAM caches for non-volatile memory systems

With the release of Intel's Optane DIMM, Non-Volatile Memories (NVMs) are emerging as viable alternatives to DRAM memories because of the advantage of higher capacity. However, the higher latency and lower bandwidth of Optane prevent it from outright replacing DRAM. A prevailing strategy is to employ existing DRAM as a data cache for Optane, thereby achieving overall benefit in capacity, bandwidth, and latency. In this paper, we inspect new features in DDR5 to better support the DRAM cache design for Optane. Specifically, we leverage the two-level ECC scheme, i.e., DIMM ECC and on-die ECC, in DDR5 to construct a narrower channel for tag probing and propose a new operation for fast cache replacement. Experimental results show that our proposed strategy can achieve, on average, 26% performance improvement.
Pref-X: a framework to reveal data prefetching in commercial in-order cores

Computer system simulators are major tools used by architecture researchers to develop and evaluate new ideas. Clearly, such evaluations are more conclusive when compared to commercial state-of-the-art architectures. However, the behavior of key components in existing processors is often not disclosed, complicating the construction of faithful reference models. The data prefetching engine is one of such obscured components that can have a significant impact on key metrics such as performance and energy. In this paper, we propose Pref-X, a framework to analyze functional characteristics of data prefetching in commercial in-order cores. Our framework reveals data prefetches by X-raying into the cache memory at the request granularity, which allows linking memory access patterns with changes in the cache content. To demonstrate the power and accuracy of our methodology, we use Pref-X to replicate the data prefetching mechanisms of two representative processors, namely the Arm Cortex-A7 and the Arm Cortex-A53, with a 99.8% and 96.9% average accuracy, respectively.
PIPF-DRAM: processing in precharge-free DRAM

To alleviate costly data communication among processing cores and memory modules, parallel processing-in-memory (PIM) is a promising approach which exploits the huge available internal memory bandwidth. High capacity, wide row size, and maturity of DRAM technology, make DRAM an alluring structure for PIM. However, dense layout, high process variation, and noise vulnerability of DRAMs make it very challenging to apply PIM for DRAMs in practice. This work proposes a PIM structure which eliminates these DRAM limitations, exploiting a precharge-free DRAM (PF-DRAM) structure. The proposed PIM structure, called PIPF-DRAM, performs parallel bitwise operations only by modifying control signal sequences in PF-DRAM, with almost zero structural and circuit modifications. Comparing the state-of-the-art PIM techniques, PIPF-DRAM is 4.2× more robust to process variation, 4.1% faster in average cycle time of operations, and consumes 66.1% less energy.
PatterNet: explore and exploit filter patterns for efficient deep neural networks

Weight clustering is an effective technique for compressing deep neural networks (DNNs) memory by using a limited number of unique weights and low-bit weight indexes to store clustering information. In this paper, we propose PatterNet, which enforces shared clustering topologies on filters. Cluster sharing leads to a greater extent of memory reduction by reusing the index information. PatterNet effectively factorizes input activations and post-processes the unique weights, which saves multiplications by several orders of magnitude. Furthermore, PatterNet reduces the add operations by harnessing the fact that filters sharing a clustering pattern have the same factorized terms. We introduce techniques for determining and assigning clustering patterns and training a network to fulfill the target patterns. We also propose and implement an efficient accelerator that builds upon the patterned filters. Experimental results show that PatterNet shrinks the memory and operation count up to 80.2% and 73.1%, respectively, with similar accuracy to the baseline models. PatterNet accelerator improves the energy efficiency by 107x over Nvidia 1080 1080 GTX and 2.2x over state of the art.
CDB: critical data backup design for consumer devices with high-density flash based hybrid storage

Hybrid flash based storage constructed with high-density and low-cost flash memory are becoming increasingly popular in consumer devices during the last decade. However, to protect critical data, existing methods are designed for improving reliability of consumer devices with non-hybrid flash storage. Based on evaluations and analysis, these methods will result in significant performance and lifetime degradation in consumer devices with hybrid storage. The reason is that different kinds of memory in hybrid storage have different characteristics, such as performance and access granularity. To address the above problems, a critical data backup (CDB) method is proposed to backup designated critical data with making full use of different kinds of memory in hybrid storage. Experiment results show that compared with the state-of-the-arts, CDB achieves encouraging performance and lifetime improvement.
GLite: a fast and efficient automatic graph-level optimizer for large-scale DNNs

We propose a scalable graph-level optimizer named GLite to speed up search-based optimizations on large neural networks. GLite leverages a potential-based partitioning strategy to partition large computation graphs into small subgraphs without losing profitable substitution patterns. To avoid redundant subgraph matching, we propose a dynamic programming algorithm to reuse explored matching patterns. The experimental results show that GLite reduces the running time of search-based optimizations from hours to milliseconds, without compromising in inference performance.
An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection

Recently wearable EEG monitoring devices with seizure detection processor using convolutional neural network (CNN) have been proposed to detect the seizure onset of patients in real time for alert or stimulation purpose. High energy efficiency and accuracy are required for the seizure detection processor due to the tight energy constraint of wearable devices. However, the use of CNN and multi-channel processing nature of seizure detection result in significant energy consumption. In this work, an energy-efficient seizure detection processor is proposed, featuring multi-stage CNN classification, segmented data processing and adaptive channel selection to reduce the energy consumption while achieving high accuracy. The design has been fabricated and tested using a 55nm process technology. Compared with several state-of-the-art designs, the proposed design achieves the lowest energy per classification (0.32 μJ) with high sensitivity (97.78%) and low false positive rate per hour (0.5).
Rethinking key-value store for byte-addressable optane persistent memory

Optane Persistent Memory (PM) is a pioneering solution to byte-addressable PM for commodity systems. However, the performance of Optane PM is highly workload-sensitive, rendering many prior designs of Key-Value (KV) store inefficient. To cope with this reality, we advocate rethinking KV store design for Optane PM. Our design follows a principle of Single-stream Writing with managed Multi-stream Reading (SWMR): Incoming KV pairs are written to PM through a single write stream and managed by an ordered index in DRAM. Through asynchronously sorting and rewriting large sets of KV pairs, range queries are handled with a managed number of concurrent streams. YCSB results show that our design improved upon existing ones by 116% and 21% for write-only throughput and read-write throughput, respectively.
PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration

Deep hashing has gained growing momentum in large-scale image retrieval. However, deep hashing is computation- and memory-intensive, which demands hardware acceleration. The unique process of hash sequence computation in deep hashing is non-trivial to accelerate due to the lack of an efficient compute primitive for Hamming distance calculation and ranking. This paper proposes the first PIM-based scheme for deep hashing accelerator, namely PIM-DH. PIM-DH is supported by an algorithm and architecture co-design. The proposed algorithm seeks to compress the hash sequence to increase the retrieval efficiency by exploiting the hash code sparsity without accuracy loss. Further, we design a lightweight circuit to assist CAM to optimize hash computation efficiency. This design leads to an elegant extension of current PIM-based architectures for adapting to various hashing algorithms and arbitrary size of hash sequence induced by pruning. Compared to the state-of-the-art software framework running on Intel Xeon CPU and NVIDIA RTX2080 GPU, PIM-DH achieves an average 4.75E+03 speedup with 4.64E+05 energy reduction over CPU, 2.30E+02 speedup with 3.38E+04 energy reduction over GPU. Compared with PIM architecture CASCADE, PIM-DH can improve computing efficiency by 17.49× and energy efficiency by 41.38×.
Memory-efficient training of binarized neural networks on the edge

A visionary computing paradigm is to train resource efficient neural networks on the edge using dedicated low-power accelerators instead of cloud infrastructures, eliminating communication overheads and privacy concerns. One promising resource-efficient approach for inference is binarized neural networks (BNNs), which binarize parameters and activations. However, training BNNs remains resource demanding. State-of-the-art BNN training methods, such as the binary optimizer (Bop), require to store and update a large number of momentum values in the floating point (FP) format. In this work, we focus on memory-efficient FP encodings for the momentum values in Bop. To achieve this, we first investigate the impact of arbitrary FP encodings. When the FP format is not properly chosen, we prove that the updates of the momentum values can be lost and the quality of training is therefore dropped. With the insights, we formulate a metric to determine the number of unchanged momentum values in a training iteration due to the FP encoding. Based on the metric, we develop an algorithm to find FP encodings that are more memory-efficient than the standard FP encodings. In our experiments, the memory usage in BNN training is decreased by factors 2.47x, 2.43x, 2.04x, depending on the BNN model, with minimal accuracy cost (smaller than 1%) compared to using 32-bit FP encoding.
HIMap: a heuristic and iterative logic synthesis approach

Recently, many models show their superiority in sequence and parameter tuning. However, they usually generate non-deterministic flows and require lots of training data. We thus propose a heuristic and iterative flow, namely HIMap, for deterministic logic synthesis. In which, domain knowledge of the functionality and parameters of synthesis operators and their correlations to netlist PPA is fully utilized to design synthesis templates for various objetives. We also introduce deterministic and effective heuristics to tune the templates with relatively fixed operator combinations and iteratively improve netlist PPA. Two nested iterations with local searching and early stopping can thus generate dynamic sequence for various circuits and reduce runtime. HIMap improves 13 best results of the EPFL combinational benchmarks for delay (5 for area). Especially, for several arithmetic benchmarks, HIMap significantly reduces LUT-6 levels by 11.6 ~ 21.2% and delay after P&R by 5.0 ~ 12.9%.
Write or not: programming scheme optimization for RRAM-based neuromorphic computing

One main fault-tolerant method for a neural network accelerator based on resistive random access memory crossbars is the programming-based method, which is also known as write-and-verify (W-V). In the basic W-V scheme, all devices in crossbars are programmed repeatedly until they are close enough to their targets, which costs huge overhead. To reduce the cost, we optimize the W-V scheme by proposing a probabilistic termination criterion on a single device and a systematic optimization method on multiple devices. Furthermore, we propose a joint algorithm that assists the novel W-V scheme by incremental retraining, which further reduces the W-V cost. Compared to the basic W-V scheme, our proposed method improves the accuracy by 0.23% for ResNet18 on CIFAR10 with only 9.7% W-V cost under variation with σ = 1.2.
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory

SRAM-based computing-in-memory (SRAM-CIM) provides fast speed and good scalability with advanced process technology. However, the energy efficiency of the state-of-the-art current-domain SRAM-CIM bit-cell structure is limited and the peripheral circuitry (e.g., DAC/ADC) for high-precision is expensive. This paper proposes a charge-pulsation SRAM (CP-SRAM) structure to achieve ultra-high energy-efficiency thanks to its charge-domain mechanism. Furthermore, our proposed CP-SRAM CIM supports configurable precision (2/4/6-bit). The CP-SRAM CIM macro was designed in 180nm (with silicon verification) and 40nm (simulation) nodes. The simulation results in 40nm show that our macro can achieve energy efficiency of ~2950Tops/W at 2-bit precision, ~576.4 Tops/W at 4-bit precision and ~111.7 Tops/W at 6-bit precision, respectively.
Nonlinear decay of ion--acoustic instability in a current plasma

From 3rd international symposium on toroidal plasma confinement; Garching, Germany (26 Mar 1973). The probability characteristic of plasma uhf noise was obtained in the Uragan'' stellarator. Thermal and nonthermal uhf emission was detected in helium discharges. These emissions were observed in the vicinity of plasma frequencies corresponding to various density regions of the plasma column. Intensive Langmuir oscillations in the plasma were probably excited by the beam of runaway'' electrons. The x-ray emission associated with this beam was observed from a tungsten target at 7 cm from the column axis. The fluctuation spectrum of the uhf emission versus plasma parameters allows the ion- acoustic nature of the turbulent pulsations to be established. (GE)
Oil spill remote monitoring by using remotely piloted aircraft

Purpose This paper aims to analyze the application of remotely piloted aircraft (RPA) for remote oil spill sensing. Design/methodology/approach This paper is an analysis of RPA strong points. Findings To increase the accuracy and eliminate potentially false contamination detection, which can be caused by external factors, an oil thickness measurement algorithm is used with the help of the multispectral imaging that provides high accuracy and is versatile for any areas of water and various meteorological and atmospheric conditions. Research limitations/implications SWOT analysis of implementation of RPA for remote sensing of oil spills. Practical implications The use of RPA will improve the remote sensing of oil spills. Social implications The concept of oil spills monitoring needs to be developed for quality data collection, oil pollution control and emergency response. Originality/value The research covers the development of a method and design of a device intended for taking samples and determining the presence of oil contamination in an aquatorium area; the procedure includes taking a sample from the water surface, preparing it for transportation and delivering the sample to a designated location by using the RPA. The objective is to carry out the analysis of remote oil spill sensing using RPA. The RPA provides a reliable sensing of oil pollution with significant advantages over other existing methods. The objective is to analyze the use of RPA employing all of their strong points. In this paper, technical aspects of sensors are analyzed, as well as their advantages and limitations.
Investigation on Tactile Perception of Ultrasonic Haptics Devices

Haptics have increasingly gained importance in the field of user interface design by addressing tactile sensing in addition to visual and acoustic stimulation. Mid-air haptics allow tactile feedback without contact or wearable hardware and offer advanced control and output mechanisms as well as different sensory modalities for user interfaces (UI) and Virtual/Augmented Reality (VR/AR) applications. Using mid-air haptics virtual objects can offer tactile interaction, thus making contact-free UI interaction more viable. This paper investigates the user perception of ultrasonic haptic signals. By presenting test subjects a broad selection of haptic signals and researching the actually perceived stimuli as well as inquiring the test subjects’ thoughts about their experience, conclusions on the optimal design and application of ultrasonic haptic signals are made. This is done by comparing haptic signals of different shapes and dynamics but constant intensity and researching the subjectively perceived signal intensity and the participant’s success in detecting the correct shape. This allows better targeting of specific sensations in order to let users perceive concrete signals. It also offers insight into better design of haptic signals to achieve optimal user detection. The results of this investigation were applied in form of a demonstrator, which highlights multiple mid-air haptics and input modalities in different application scenarios.
Towards a Vowel Formant Based Quality Metric for Text-to-Speech Systems: Measuring Monophthong Naturalness

This contribution proposes an objective, vowel formant based quality metric for assessing the naturalness of monophthongs synthesized by Text-to-Speech (TTS) systems. This could eliminate the need for time and resource-intensive perception-based mean opinion score metrics. We show that vowel space plots can serve as a basis for developing a more comprehensive, linguistically sound quality metric for TTS systems. In addition, our metric provides detailed insights on the quality of individual monophthongs, which could help with identifying areas for further optimization in TTS systems. We use a state-of-the-art neural TTS pipeline based on Tacotron and WaveGlow, trained on the LJ Speech dataset, to generate the same audio as in our validation set and compare the two sets of audio files. Our quality metric is automatically calculated using the Montreal Forced Aligner for aligning text and audio, Praat for measuring formant values and a custom R script to calculate the vowel spaces and their overlap. Our results show that the vowel spaces of the original audio and the synthesized audio overlap to a large extent, especially for the means and the central 75% of the data, with more variation when considering all data points. Furthermore, we show that there is considerable variation in the overlap of the vowel spaces of different monophthongs.
Soft Homotopy through Moore-Penrose Inverse

The acquisition of a discrete-time signal is an important part of a compressive sensing problem. A fine algorithm that could bring better signal recovery performance is often called for. In this work, two homotopy algorithms that involve a soft thresholding decision are proposed using the Moore-Penrose inverse. The additional complexity required in the two proposed methods is relatively minimal, since the necessary matrix inverse (AA⊤)−1 and the matrix multiplication A⊤(AA⊤)−1 can be done before the iteration starts, where •⊤ is the transpose. Numerical examples illustrate the improved error performance for different values of the shrinking parameter γ. It is found that the greater the shrinking parameter, the less the signal recovery error one could obtain from the two new approaches.