Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme)

Ongoing technological innovation and success in the miniaturization and fabrication of sub-micron microelectronic devices have come to the point that nowadays, complete systems including multiple full-fledged microprocessors may be integrated together with complex interconnection structures and memory systems on a single chip of area less than one fingernail. This so-called System-on-a-Chip (SoC) technology is readily available. Unfortunately, applications exploiting SoC technology demand in many cases very specific solutions and standard chips cannot be used efficiently for most applications. On the other hand, the development of specialized ASICs (applicationspecific integrated circuits) is often prohibitive because of very high mask production costs and high design times. This matters especially in low and medium volume market segments such as typical for embedded systems. Reconfigurable Computing Systems open an interesting alternative to custom ASIC solutions and offer the potential to economically exploit SoC technology for a broad range of application domains: Apart from the conventional programmability by means of software, their function and hardware structure may be reconfigured individually at the programmer’s site reducing design times considerably. Sometimes, reconfiguration may be exploited even at run-time, and a system thus has capabilities to adopt its behavior dynamically to changes of requirements and/or to dynamically changing operating environments. Because of steadily decreasing product introduction cycles, reconfigurable computing systems will gain more and more market importance because only they are capable of offering highly optimized dedicated and highly efficient solutions for applications that are often not fully specified at design time. Also, redesign times can be reduced. Finally, the potential of reconfigurability at run-time, also often called dynamic reconfiguration, offers a vast potential for new intelligent products, optimizing themselves at runtime by means of reconfiguration or healing themselves in case of occuring defects. Unfortunately, neither on the hardware nor on the tool side is dynamic hardware reconfiguration well understood. Devices such as field programmable gate arrays (FPGA) [1; 2] offer already tool support to develop SoC solutions including aids for microprocessor core instantiation, memory mapping and communication support by means of on-chip buses to integrate dedicated hardware IP designs on a single device. They include also programming support for the processors and simulation support for the complete SoC. Also, basic principles how to reconfigure these most often SRAM-based devices statically and to some extent also dynamically at the level of logic functions and at the level of bit-level interconnect structures are known. However, dynamic hardware reconfiguration is still very tedious, if not impossible at all. The exploitation of new system architectures, methodologies and applications profiting from dynamic hardware reconfiguration in particular requires the interdisciplinary cooperation of top-notch research teams including SoC technology experts, computer architects (multiprocessor technology, fault-tolerant computing), middleware specialists (compiler, operating systems), application providers as well as experts on design automation of electronic systems (modelling, partitioning, placement and reconfiguration scheduling, etc.). In 2003, the German Research Foundation (Deutsche Forschungsgemeinschaft) granted the Priority Program 1148 to provide 6 years of funding for currently a team of 19 funded projects of research teams throughout Germany. In the following, the research topics of this program and the individual projects and project partners will be introduced. Due to space requirements, only 6 projects have been given the opportunity to describe the results of their current state-of-the-art work in dedicated contributions in this special issue. The remaining projects will be honored here next.