TERMINAL SOLDER DIP TESTING FOR CHIP CERAMIC AND TANTALUM CAPACITORS

Thermal shock (TS) associated with soldering conditions is one of the major causes of first turn-on failures of tantalum capacitors and fracturing of Multilayer Ceramic Capacitors (MLCCs) that results in latent defects and might cause failures with time during application. The probability of damaging of the parts and failures are typically greater for manual soldering that is often used to assemble circuits for high-reliability space systems. This work analyzes deficiencies of the existing resistance to soldering heat tests and describes a terminal solder dip (TSD) testing that is argued to be the most adequate test simulating TS conditions caused by manual soldering. Different types of MLCCs and tantalum capacitors, including regular chips, microchips, and polymer cathode capacitors were used in this study. Results of TSD testing are described and analyzed to evaluate the robustness of parts to soldering stresses, demonstrate the effectiveness of the test, and select adequate test conditions. Mechanisms of fracturing of MLCCs and damage to tantalum capacitors caused by soldering are discussed. INTRODUCTION Damage to surface mount ceramic and tantalum capacitors during soldering is considered one of the prime reasons of failures of these parts during operation. In case of ceramic capacitors, soldering-induced thermal shock (TS) creates transient mechanical stresses that might exceed the strength of materials and result in cracking [1]. Thermo-mechanical stresses in tantalum capacitors might cause damage to thin tantalum pentoxide dielectric that reduces breakdown voltages and results in first turn-on failures of the parts [23]. Although soldering-induced damage might not lead to immediate failures of capacitors, it can cause degradation of characteristics with time (hours to months) resulting eventually in field failures. In this regard, microcracks in capacitors generated during assembly can be considered as a “time bomb” [4] that causes increased leakage currents, opens, or intermittent contacts as degradation develops or cracks propagate with time during application. Cracking in ceramic capacitors is an old problem. It appeared in the 1970s when the first surface mount technology (SMT) chip capacitors were introduced to the market and began to be employed in NASA applications [56]. According to J. Maxwell [7] this problem will continue to be with us in the foreseeable future. Two main factors contribute to the problem: brittleness of ceramic materials and thermal and mechanical stresses associated with the assembly process. Both factors are intrinsic to chip ceramic capacitors and explain the persistence of the problem. A breakdown of about 40 different mechanical failures of capacitors shows that 25% were caused by flex cracking, 23% by thermal shock cracking, and 34% were due to manufacturing defects [8-9]. Volumes of literature have been written over the years about cracks in ceramic capacitors, mechanisms of their formation, and factors affecting the probability of their occurrence. Based on these studies, a substantial progress in the quality of materials and manufacturing processes has been made. This, as well as development of detailed application guidelines, resulted in a significant decrease in cracking-related failures and allowed for application of chip capacitors in high-reliability systems including space instruments. Still, failures related to cracking in capacitors after assembly onto printed wiring boards (PWB) do occur, and further analysis and improvement in screening and qualification techniques are necessary. To decrease the probability of fracturing during soldering, one should both reduce the level of stress and select capacitors with high resistance to soldering stresses. Assuring that capacitors are not abused during soldering is the purpose of the workmanship control that should ensure compliance with the existing guidelines for assembly. These guidelines are based on decades of industry practice that are well-developed and documented. However, the level of testing that is typically used to assure the robustness of MLCCs to soldering stresses is not sufficient. Manual soldering of capacitors, which is often used during assembly or rework for space projects, might be more stressful compared to the standard solder reflow processes due to a greater temperature gradients in the part and is known to have a high risk of damaging the parts that is increasing with the size of capacitors [7]. All manufacturers are warning against manual soldering of large MLCCs and