Efficient distributed bounded property checking

Today, verification of industrial size designs like multi-million gate ASICs (Application Specific Integrated Circuit) and SoC (System-on-a-Chip) processors consumes up to 75% of the design effort. The trend to augment functional verification with formal verification tries to alleviate this problem. Efficient property checking algorithms based on binary decision diagrams (BDDs) and satisfiability (SAT) solvers allow the automatic verification of medium-sized designs. However, the steadily increasing design sizes still leave verification as the major bottleneck, because formal methodologies do not yet scale to very large designs. To address these problems researchers came up with the idea of combining symbolic simulation and bounded model checking on-the-fly. The current tools pioneer in handling comparatively larger designs by partitioning the state set and they can be represented using partitioned ordered BDDs (POBDDs). These partitions will be explored in a divide-and-conquer manner. However, still they face memory exhaustion for very large models due to the BDD explosion problem. Even the SAT based bounded model checking (BMC) can search up to a maximum depth allowed by the physical memory on a single server. These observations motivated the parallelization of symbolic state space traversal algorithms. Distributed algorithms verify larger models and return results faster than sequential versions. Existing schemes for parallelizing BDD-based verification algorithms often suffer from state overlap or duplicate work, cross over states among partitions, inefficient work distribution, improper load balancing, synchronicity and communication overhead. The algorithms concentrate heavily either on reachability (validation) or falsification but not both together. My main contributions include a dynamic overlap reduction and a hybrid distributed algorithms. The dynamic overlap reduction technique smoothens the state space traversal of each network node by removing the state overlap that it suffers from. The removal of overlap works in an asynchronous manner, i.e., with out waiting for other processors to complete their image computations. This method has the natural side effect of dynamic load balancing among network nodes, i.e., the nodes that deal with a large state space at one time point will be later assigned a small state space and vice versa. Since all the nodes perform asynchronous state space traversal on their whole state subsets, the method is best suitable for validation. The hybrid method is an asynchronous distributed algorithm, suited for both fast error detection and complete validation. This approach combineswell known windowing and dynamic overlap reduction techniques. The windowing technique has partitions that are identified by unique combination of variables. Each window restricts its state space at regular intervals to keep the reachable state space within it’s window region. The real state space is discriminated by the window as owned and non-owned states. The nodes on the cluster machine are employed with two different types of tasks. Some nodes, windows aim at faster falsification on the basis of the windowing technique. The other type of nodes called helpers are intending for validation on the basis of the dynamic overlap reduction. All the network nodes asynchronously traverse their local state spaces for both error states detection and reachability of a time bound. Thus, the hybrid algorithm efficiently combines both windowing and dynamic overlap reduction techniques to obtain more synergy and gains the advantages of using both the approaches. Further, the algorithm expedites the verification process by reassigning the work to idle nodes as quickly as possible. As a result it avoids the wasted computation power and makes the system work efficient. The dynamic overlap reduction and hybrid algorithms are best suitable for homogeneous system configurations like a cluster. However, this thesis also presents a grid-based parallelization algorithm which is suitable for fast falsification of very large designs. In addition, all the parallel algorithms in this thesis partition the state space using the Minimal overlap algorithm which pioneers in statically minimizing the cross over states or state overlap among the partitions. The parallel algorithms speedup the distributed verification and automatically checks the correctness of very large hardware designs. The distributed computation shows approximately linear speedups in execution time and enables faster verification of properties. As a supplement, this thesis also presents a novel distributed algorithm, which uses mixed forward and backward traversal mechanism for Black Box verification.