Miracle-dz/UniFAR-FTUs huggingface dataset:
A stylebase as a tool for modelling of quality-driven software architecture

The main goal of model-driven engineering (MDE) is to improve software quality by using models as a means of producing high-quality systems with decreased development costs. Thus MDE makes it possible to represent software solutions by models and to evaluate and maintain models instead of the source code. However, software quality, i.e. quality of models, depends on how the quality characteristics of a system or a systems family have been taken into account in the architecture development. The main contribution of this paper is a stylebase, a tool including architectural styles and patterns, and design patterns, intended to be used while architecting. The stylebase is an integrated part of the architect’s tooling environment, providing support for the design of the architecture and for quality evaluation of architectural models. The stylebase can be used as a part of a commercial tool and as an independent component of a distributed software development environment with heterogeneous modelling tools.
Research on Power Grid Fault Diagnosis Technology Based on Deep Learning

The traditional grid fault diagnosis has the following problems: the lack of grid structure information, feature input depends on manual experience, and the model logic is complex. For the above problems, this paper studies a deep learning-based grid fault diagnosis technology. Firstly, an adaptive grid advanced feature extraction method is designed, as well as a depth iterative network for the grid structure for extracting the structure-related abstract characteristics. Then design a grid fault diagnosis model (AFD_SL) based on supervision learning and a power grid fault diagnosis model (AFD_RL) based on strengthening learning. Among them, the AFD_SL is designed with a way one by one to design the diagnose model, which is suitable for power grid fault diagnosis scene with sufficient label data; AFD_RL transforms troubleshooting problems into a sequential decision-making process, which is suitable for power grid fault diagnostics scenes with insufficient label data. The experimental results show that the grid fault diagnosis method designed herein has a good mode l portability and robustness while better handling multiple fault diagnosis.
An Enhanced Collision Detection Scheme for ISO 18000–6C RFID Systems

Abstract In radio-frequency identification systems, tag collision resolution is a significant issue for fast tag identification. Dynamic framed slotted ALOHA (DFSA) is one of the most widely used algorithms to resolve tag collision. Collision detection (CD) plays an important role in determining the efficiency of DFSA-based algorithms because most DFSA-based algorithms determine the next frame size according to the number of collided slots in the current frame. Existing CD methods do not respond quickly enough to detect a collision and have difficulty in distinguishing a collision from noise, resulting in a degradation of system efficiency. This paper presents a CD scheme based on the ISO/IEC 18000–6C protocol to improve CD efficiency. This scheme enables fast and accurate CD by detecting the number of pulses transmitted by tags. The effectiveness and practical feasibility of the scheme is verified by simulation and implementation. Performance evaluation results show that the proposed scheme achieves faster identification speed than the conventional methods, especially under noise conditions.
The Queueing Theory in Cloud Computing to Reduce the Waiting Time

Cloud computing is an emerging technology of business computing and it is becoming a development trend(r). The process of entering into the cloud is generally in the form of queue, so that each user need to wait until the current user is being served. In the system, each Cloud Computing User (CCU) requests Cloud Computing Service Provider (CCSP) to use the resources, if CCU(cloud computing user) finds that the server is busy then the user has to wait till the current user completes the job which leads to more queue length and increased waiting time. So to solve this problem, it is the work of CCSP's to provide service to users with less waiting time otherwise there is a chance that the user might be leaving from queue. CCSP's can use multiple servers for reducing queue length and waiting time. In this paper, we have shown how the queuing model, M/M/S model is used for multiple servers to reduce the mean queue length and waiting time.
Processing Requirements for a Product-Service Engineering Platform – A Multiple Use Case Approach.

Currently, there is a growing trend towards highly customized products, ultimately one-off products, enhanced with a variety of services. These services are delivered together as product service systems. Manufacturing and business based on product service systems require software platforms capable of supporting offerings over their lifecycle thus securing long term customer value. The European H2020 Manutelligence project aims at supporting this trend, allowing enterprises to develop sustainable innovative product-services efficiently addressing customer needs. The project aim is to integrate the Product Lifecycle Management and Service Life_cycle Management concepts resulting in an intelligent and collaborative product-service engineering and manufacturing platform. In this paper we will present the platform requirement engineering process, as a multiple use case approach.
Implementation of fault tolerance techniques for integrated network interfaces

The increasing demand for safety and mission-critical computational systems to operate in hostile environ-ments, along with the component miniaturization for such systems, have triggered the need for developing fault tolerance techniques to mitigate the incidence of system failures and increase reliability. Communication architectures used in computers for aerospace applications are made up of a growing number of processing cores. Some approaches that are proposed in the literature do not meet the communication requirements of future on-board computers composed of multiple cores. Networks-on-Chip are the successors of the bus for multicore interconnection, integrating cores by the means of Network Interfaces. This work discusses the implementation and evaluates the performance of the Hamming encoding, the Triple Modular Redundancy (TMR), and temporal redundancy into the eXtensible Interface for Routing Unit (XIRU) Network Interface. Five scenarios are considered based on the combination of these techniques. Results show that the TMR in FIFO bu ﬀ ers is the most costly technique in terms of area usage, the Hamming code has the highest power dissipation, while the temporal redundancy has the lower operation frequency. Finally, a modiﬁed version of XIRU to integrate cores into Network-on-Chip systems with reliability requirements is devised. We intend to use the interface to integrate the cores of future cubesats developed in the FloripaSat project.
Processing corrective focus and information focus at different positions: an electrophysiological investigation

ABSTRACT Focus is the most emphasised constituent of a sentence and either marks information that is newly asserted or indicates a contrast between current information and its alternatives. To investigate how readers process information focus (IF) and corrective focus (CF) at different positions in sentences, participants were visually presented with dialogues through a sentence comprehension task. The results showed that focus elicited a larger P2 and late positive component (LPC) than background, possibly reflecting a process of attention allocation and immediate discourse updating. Additionally, IF elicited a larger P2 than CF at the clause-medial position, while CF elicited a larger LPC than IF at the clause-final position, indicating that readers use various strategies to process the two kinds of focus at the different positions. The present study suggests that focus processing is influenced by both context and focus position.
On the Performance of Regenerative Relaying for SWIPT in NOMA Systems

As a potential access strategy in 5G mobile communication systems, non-orthogonal multiple access (NOMA) has been proposed as a supplement to the traditional orthogonal multiple access (OMA). This paper investigates simultaneous wireless information and power transfer (SWIPT) in a NOMA relaying system. The data is transferred from a source to two end terminals among which the one close to the source acts as a relay employing decode-and-forward protocol to assist the far-end one. In order to simultaneously harvest the energy and information processing at relay node, power-splitting relaying (PSR) and time switching-based relaying (TSR) protocols are sequentially considered. Outage probability and ergodic rate of both protocols are firstly analyzed to realize the impacts of various parameters including energy harvesting time, power splitting ratio, energy harvesting efficiency, source data rate, and the distance between the source and the relay node. Numerical results are then provided to validate the analytical findings. It is shown that the PSR outperforms the TSR at normal SNR regime in terms of throughput and ergodic rate.
Empirical Study of Decentralized Multi-Channel Active Noise Control Based on the Genetic Algorithm

In an active noise control (ANC) system, computational complexity is one major concern when designing practical control algorithms. One approach to reducing computational complexity is to apply a decentralized control scheme rather than the centralized scheme. The decentralized scheme attempts to control a number of ANC subsystems independently, where for simplicity, one subsystem consists of one loudspeaker and one error microphone. Our recent published article has shown theoretically that a decentralized two-channel ANC system can achieve the same noise reduction performance as the centralized one with guaranteed convergence in the frequency domain. In this work, we attempt to extend the results from two-channel case to N (N>1) channel case. The challenge sits in finding N complex numbers that could properly shape the eigenvalues of an N ́ N matrix for each frequency bin towards guaranteed convergence. Due to the problem complexity, we conduct empirical study by using the genetic algorithm (GA). Simulation results on the channel numbers of 4, 6, and 12 demonstrate that the resulting decentralized ANC controller is also able to achieve the same noise reduction performance as the centralized controller.
Modelling of retention of media service users based on power-law

In this paper, a model of the visitor retention in media services via the Internet such as video distribution service is shown. Visitor intervals of media services usually follow power-law. Based on the theory, we describe the modeling of visitor intervals and separate the residual into the elements of return and retention. Moreover, the result of the separation according to access log of the Internet TV station “AbemaTV” is shown as an example.
What makes a 'good' program?

As SAS® programmers, we create hundreds and thousands of programs; generating tables, listings, figures, datasets etc. But are these programs actually any ‘good’? What exactly makes a program ‘good’? If my program produces what is required, and is correct in its output, then is this a ‘good’ program? For example, if the runtime is inefficient, is this a ‘good’ program? Efficiency is a factor often used, and is easily measurable. However, is there more to a ‘good’ program than just correctness and efficiency? Perhaps the programs ability to cope with unexpected cases, or the ease of which the program can be updated and maintained? The aim of this paper is to discuss a variety of such software quality factors; how and to what extent they can be applied to the world of statistical programming in the pharmaceutical industry.
Modeling and simulation of photovoltaic cells/modules/arrays

The first purpose of this paper is to present a brief introduction to the behavior and functioning of a PV device and write its basic equation, without the intention of providing an in-depth analysis of the photovoltaic phenomena and the semiconductor physics. The introduction on PV devices is followed by the modeling and simulation of PV cell/PV module/PV array, which is the main subject of this paper. A MATLAB Simulink /PSIM based simulation study of PV cell/PV module/PV array is carried out and presented . The simulation model makes use of basic circuit equations of PV solar cell based on its behaviour as diode, taking the effect of sunlight irradiance and cell temperature into consideration on the output current I-V characteristic and output power P-V characteristic . A particular typical 50W solar panel was used for model evaluation, and results of simulation were compared with points taken directly from the data sheet and curves published by the manufacturers show excellent correspondence to the model.
Deep Transfer Bug Localization

Many projects often receive more bug reports than what they can handle. To help debug and close bug reports, a number of bug localization techniques have been proposed. These techniques analyze a bug report and return a ranked list of potentially buggy source code files. Recent development on bug localization has resulted in the construction of effective supervised approaches that use historical data of manually localized bugs to boost performance. Unfortunately, as highlighted by Zimmermann et al., sufficient bug data is often unavailable for many projects and companies. This raises the need for cross-project bug localization – the use of data from a project to help locate bugs in another project. To fill this need, we propose a deep transfer learning approach for cross-project bug localization. Our proposed approach named TRANP-CNN extracts transferable semantic features from source project and fully exploits labeled data from target project for effective cross-project bug localization. We have evaluated TRANP-CNN on curated high-quality bug datasets and our experimental results show that TRANP-CNN can locate buggy files correctly at top 1, top 5, and top 10 positions for 29.9, 51.7, 61.3 percent of the bugs respectively, which significantly outperform state-of-the-art bug localization solution based on deep learning and several other advanced alternative solutions considering various standard evaluation metrics.
Balanced-force two-phase flow modelling on unstructured and adaptive meshes

Two-phase flows occur regularly in nature and industrial processes and their understanding is of significant interest in engineering research and development. Various numerical methods to predict two-phase phase flows have been developed as a result of extensive research efforts in past decades, however, most methods are limited to Cartesian meshes. A fully-coupled implicit numerical framework for two-phase flows on unstructured meshes is presented, solving the momentum equations and a specifically constructed continuity constraint in a single equation system. The continuity constraint, derived using a momentum interpolation method, satisfies continuity, provides a strong pressure-velocity coupling and ensures a discrete balance between pressure gradient and body forces. The numerical framework is not limited to specific density ratios or a particular interface topology and includes several novelties. A further step towards a more accurate prediction of two-phase flows on unstructured meshes is taken by proposing a new method to evaluate the interface curvature. The curvature estimates obtained with this new method are shown to be as good as or better than methods reported in literature, which are mostly limited to Cartesian meshes, and the accuracy on structured and unstructured meshes is shown to be comparable. Furthermore, lasting contributions are made towards the understanding of convolution methods for twophase flow modelling and the underlying mechanisms of parasitic currents are studied in detailed. The mesh resolution is of particular importance for two-phase flows due to the inherent first-order accuracy of the interface position using interface capturing methods. A mesh adaption algorithm for tetrahedral meshes with application to two-phase flows and its implementation are presented. The algorithm is applied to study mesh resolution requirements at interfaces and force-balancing for surface-tension-dominated two-phase flows on adaptive meshes.
Optimizing a Network Layer Moving Target Defense by Translating Software from Python to C

ii Dedication iii Acknowledgements iv Chapter 1: Introduction 1 1.1 Overview 2 1.2 Organization 2 Chapter 2: Overview of MT6D 4 2.1 Background 4 2.2 Changes in IPv6 over IPv4 4 2.2.1 Larger Address Size 4 2.2.2 Simplified Header Format 5 2.2.3 Improved Option and Extension Support 5 2.2.4 Flow Labeling 5 2.2.5 Authentication and Security 5 2.3 Address Assignment in IPv6 5 2.3.1 Stateless Address Autoconfiguration (SLAAC) 6 2.3. 2 Dynamic Host Configuration Protocol for IPv6 (DHCPv6) 6 2.4 Motivation for MT6D 8 2.5 Moving Target IPv6 Defense (MT6D) 9 2.5. 1 Session Key 10 2.5. 2 Address Hashing 10 2.6 MT6D Protocol 11 2.6. 1 Overhead 13 2.6. 2 Neighbor Discovery Protocol (NDP) Packet Handling 14 2.6. 3 Internet Control Message Protocol (ICMP) Packet Handling 14 2.7 An Implementation of MT6D in Python 15 2.7. 1 Overview of Python Implementation 16 2.7. 2 Main Thread 16 2.7. 3 Packet Listener Thread 17 2.7. 4 Rehash Worker Thread 18 2.8 Python Implementation Performance Concerns 20 Chapter 3: Design of C MT6D 21 3.1 Design Goals and Version Differences 21 3.1.1 External Libraries 22
Enhancing Security in Mobile Communication using a Unique Approach in Steganography

Mobile phones are the most commonly used devices in today’s scenario. The need for secured communication has become more imperative. Steganography is the most reliable technique for communicating critical information through publicly available communication channels. There are various techniques available for transfer of critical data such as cryptography and steganography. A proposed model of communicating hidden data through public portals has been discussed in this paper, where in text steganography and Image steganography are used.
BTOOLS: Trusted Transaction Generation for Bitcoin and Ethereum Blockchain Based on Crypto Currency SmartCard

This paper presents an innovative and open software framework whose goal is to increase the trust of blockchain transactions. Transactions are signed by the Elliptic Curve Digital Signature Algorithm (ECDSA) associated with a 32 bytes secret private key. We designed a Javacard application used for key generation, storage and cryptographic procedure dealing with the secp256k1 elliptic curve. Our open software BTOOLS generates Bitcoin and Ethereum transactions whose trust is enforced by the support of a Crypto Currency SmartCard (CCSC). Keywords-. Blockchain; Bitcoin; Ethereum; Trust.
Effect of clock gating in conditional pulse enhancement flip-flop for low
 power applications

Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flip-flop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. Its maximum power saving against conventional designs is up to 30.65% .
1-D Integer Transform for HEVC Encoder Using DSP Slices on FPGA

This paper presents an FPGA architecture for the 1-D integer transform of the latest video coding standard, the High Efficiency Video Coding (HEVC). The design employs hard multipliers in dedicated DSP slices, which are already embedded into an FPGA die, to gain high throughput and save general purpose LUTs. The proposed architecture can support 4x4, 8x8, 16x16, and 32x32 transform. A multiplier sharing scheme is introduced to reduce the total number of required DSP slices in order to be able to fit the design onto a Spartan-3A FPGA. The design can reach a maximum throughput of 1,692 Msamples/s irrespective of the transform size, which is enough to encode 8K (7680x4320) videos at 30 fps. This work is a pioneer research that utilizes the dedicated multipliers on FPGAs in the design of the HEVC transform.
End-to-end Deep Reinforcement Learning Based Coreference Resolution

Recent neural network models have significantly advanced the task of coreference resolution. However, current neural coreference models are usually trained with heuristic loss functions that are computed over a sequence of local decisions. In this paper, we introduce an end-to-end reinforcement learning based coreference resolution model to directly optimize coreference evaluation metrics. Specifically, we modify the state-of-the-art higher-order mention ranking approach in Lee et al. (2018) to a reinforced policy gradient model by incorporating the reward associated with a sequence of coreference linking actions. Furthermore, we introduce maximum entropy regularization for adequate exploration to prevent the model from prematurely converging to a bad local optimum. Our proposed model achieves new state-of-the-art performance on the English OntoNotes v5.0 benchmark.
High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims.