Multilevel Modeling, Formal Analysis, and Characterization of Single Event Transients Propagation in Digital Systems

RESUME La croissance exponentielle du nombre de transistors par puce a apporte des progres considerables aux performances et fonctionnalites des dispositifs semi-conducteurs avec une miniaturisation des dimensions physiques ainsi qu’une augmentation de vitesse. De nos jours, les appareils electroniques utilises dans un large eventail d’applications telles que les systemes de divertissement personnels, l’industrie automobile, les systemes electroniques medicaux, et le secteur financier ont change notre facon de vivre. Cependant, des etudes recentes ont demontre que le retrecissement permanent de la taille des transistors qui s’approchent des dimensions nanometriques fait surgir des defis majeurs. La reduction de la fiabilite au sens large (c.-a-d., la capacite a fournir la fonction attendue) est l’un d’entre eux. Lorsqu’un systeme est concu avec une technologie avancee, on s’attend a ce qu’ il connait plus de defaillances dans sa duree de vie. De telles defaillances peuvent avoir des consequences graves allant des pertes financieres aux pertes humaines. Les erreurs douces induites par la radiation, qui sont apparues d’abord comme une source de panne plutot exotique causant des anomalies dans les satellites, sont devenues l’un des problemes les plus difficiles qui influencent la fiabilite des systemes microelectroniques modernes, y compris les dispositifs terrestres. Dans le secteur medical par exemple, les erreurs douces ont ete responsables de l’echec et du rappel de plusieurs stimulateurs cardiaques implantables. En fonction du transistor affecte lors de la fabrication, le passage d’une particule peut induire des perturbations isolees qui se manifestent comme un basculement du contenu d’une cellule de memoire (c.-a-d., Single Event Upsets (SEU)) ou un changement temporaire de la sortie (sous forme de bruit) dans la logique combinatoire (c.-a-d., Single Event Transients (SETs)). Les SEU ont ete largement etudies au cours des trois dernieres decennies, car ils etaient consideres comme la cause principale des erreurs douces. Neanmoins, des etudes experimentales ont montre qu’avec plus de miniaturisation technologique, la contribution des SET au taux d’erreurs douces est remarquable et qu’elle peut meme depasser celui des SEU dans les systemes a haute frequence [1], [2]. Afin de minimiser l’impact des erreurs douces, l’effet des SET doit etre modelise, predit et attenue. Toutefois, malgre les progres considerables accomplis dans la verification fonctionnelle des circuits numeriques, il y a eu tres peu de progres en matiare de verification non-fonctionnelle (par exemple, l’analyse des erreurs douces). Ceci est du au fait que la modelisation et l’analyse des proprietes non-fonctionnelles des SET pose un grand defi. Cela est lie a la nature aleatoire des defauts et a la difficulte de modeliser la variation de leurs caracteristiques lorsqu’ils se propagent. ----------ABSTRACT The exponential growth in the number of transistors per chip brought tremendous progress in the performance and the functionality of semiconductor devices associated with reduced physical dimensions and higher speed. Electronic devices used in a wide range of applications such as personal entertainment systems, automotive industry, medical electronic systems, and financial sector changed the way we live nowadays. However, recent studies reveal that further downscaling of the transistor size at nano-scale technology leads to major challenges. Reliability (i.e., ability to provide intended functionality) is one of them, where a system designed in nano-scale nodes is expected to experience more failures in its lifetime than if it was designed using larger technology node size. Such failures can lead to serious consequences ranging from financial losses to even loss of human life. Soft errors induced by radiation, which were initially considered as a rather exotic failure mechanism causing anomalies in satellites, have become one of the most challenging issues that impact the reliability of modern microelectronic systems, including devices at terrestrial altitudes. For instance, in the medical industry, soft errors have been responsible of the failure and recall of many implantable cardiac pacemakers. Depending on the affected transistor in the design, a particle strike can manifest as a bit flip in a state element (i.e., Single Event Upset (SEU)) or temporally change the output of a combinational gate (i.e., Single Event Transients (SETs)). Initially, SEUs have been widely studied over the last three decades as they were considered to be the main source of soft errors. However, recent experiments show that with further technology downscaling, the contribution of SETs to the overall soft error rate is remarkable and in high frequency systems, it might exceed that of SEUs [1], [2]. In order to minimize the impact of soft errors, the impact of SETs needs to be modeled, predicted, and mitigated. However, despite considerable progress towards developing efficient methodologies for the functional verification of digital designs, advances in non-functional verification (e.g., soft error analysis) have been lagging. This is due to the fact that the modeling and analysis of non-functional properties related to SETs is very challenging. This can be related to the random nature of these faults and the difficulty of modeling the variation in its characteristics while propagating. Moreover, many details about the design structure and the SETs characteristics may not be available at high abstraction levels. Thus, in high level analysis, many assumptions about the SETs behavior are usually made, which impacts the accuracy of the generated results. Consequently, the lowcost detection of soft errors due to SETs is very challenging and requires more sophisticated techniques.