Electrical Operation of 6H-SiC MESFET at 500 °C for 500 Hours in Air Ambient

A high temperature n-channel 6H-SiC metal semiconductor field effect transistor (MESFET) was fabricated, packaged, and electrically operated continuously at 500 °C for over 500 hours in an air ambient with less than 10% change in operational transistor parameters. To the best of our knowledge, this is the first report of a semiconductor transistor operating in this harsh environment with excellent stability over an extended period of time. The fabrication process that enabled such stability in air atmosphere featured multiple levels of high temperature metal and dielectric passivation to prevent contamination (particularly oxygen) from reaching electrically sensitive interfaces. A thick-film metallization based ceramic package with conductive die attach material and Au wire bonds facilitated long-term testing under electrical bias at 500 °C. Over the course of the 500 hour operational test in air, the only observed degradation of transistor characteristics was increased leakage of the gate-channel diode as anneal time increased. This demonstration of 500 °C transistor durability represents an important step toward significantly expanding the operational envelope of sensor signal processing electronics for harsh combustion-engine environments. Introduction As the reliable operating temperature envelope of integrated silicon electronics has been expanded from 125 °C to temperatures above 200 °C, these electronics have found beneficial use in aerospace, automotive, industrial, and energy production systems [1,2]. Further extension of the reliable operational envelope of semiconductor electronics above 300 °C is also expected to offer additional benefits to these industries, particularly in aerospace combustion engine applications where temperatures can approach 600 °C [1,3]. The emergence of wide bandgap semiconductors, including silicon carbide (SiC), diamond, and gallium nitride (GaN), has enabled short-term electrical device demonstrations at ambient temperatures from 500 °C to 650 °C [4-6]. However, these devices have previously not demonstrated sufficient long-term durability when electronically operated at these high temperatures to be considered viable for most envisioned applications. In order to begin meeting the needs of most applications, a wide bandgap transistor technology must first demonstrate that it can achieve stable, long-term operation under electrical bias at temperature without significant changes in electrical operating parameters. This paper reports on the processing, testing, and numerical modeling of a 6HSiC transistor (MESFET) that achieved over 500 hours of electrical operation in 500 °C air ambient with less than 10% change in operational transistor parameters. To the best of our knowledge, this is the first report of a semiconductor transistor electrically operating in 500 °C harsh environment with excellent stability over an extended period of time. Experimental Procedures Fabrication The cross-sectional schematic of the MESFET is shown in Fig. 1. The MESFET was fabricated on a commercially purchased off-axis Siface 6H-SiC epitaxial wafer [7]. Epilayer doping and thicknesses were verified independently by secondary ion mass spectroscopy (SIMS) on a sliver sawed off the edge of the wafer. The transistor had originally been intended to be a junction field effect transistor (JFET), but the top p-type epitaxial layer was inadvertently lost in device processing. A scanning electron microscope (SEM) image of the device can be seen in Fig. 2. The intended JFET gate pattern and n-type channel were separately patterned with metal masks and etched in an inductively coupled plasma (ICP) reactive ion etcher (RIE). The ICP-RIE allows controlled etch rates with nearly vertical sidewalls. The metal masks were stripped in a piranha mixture. A thin blanket and a thicker patterned layer of Si were applied as a mask for elevated temperature nitrogen ion implant. The source/drain nitrogen ion implant had dosages of ~10 cm through a range of energies to create a box-like profile. After ion implantation, the Si mask was stripped. The wafer was then annealed in an inert atmosphere for less than an hour in order to activate the implant. Unexpectedly, this removed most of the p-layer of the intended JFET gate. The rest of the gate was probably consumed during the next step of thermal oxidation. Loss of the gate epitaxial layer was confirmed by SIMS, which also showed thinning of the channel not under the gate. The lower energy implants were thereby believed lost, but the highest energy implants of the box-like profile remained. The surface was thermally oxidized in steam [8]. Gate, source and drain contact vias were patterned with a BOE 6:1 wet etch. After stripping the photoresist the sample was cleaned in a piranha mixture. The device was baked-out in vacuum for 1 hour to drive water out of any micro-pipes and metalized with Ti/TaSi2/Pt without breaking vacuum [9]. The metallization was magnetron sputtered with argon as the backfill gas. The metal was patterned with photoresist and dry etched in a parallel plate RIE, following which the photoresist was removed. A backside Ti/TaSi2/Pt contact was deposited, and both metallizations annealed in nitrogen at 600 °C for 30 minutes. For passivation, Si3N4 was deposited onto the wafer. The Si3N4 was then patterned with photoresist and etched in a parallel plate RIE. Then the Ti/TaSi2/Pt metallization and the Si3N4 depositions were repeated two more times in order to insure excellent passivation. The sample was briefly annealed at 600 °C after each metallization was patterned in order to insure good adhesion with the next Si3N4 layer. The metal gate finger was only one metal layer thick and did not completely cover the channel (see Fig. 2b), since the gate finger was designed to be a JFET instead of a MESFET. Simulation Commercial device modeling software was employed to carry out two-dimensional simulations of the Fig. 1 device cross-section [10]. Table 1 summarizes the 6H-SiC material and MESFET device parameters used in the simulations. Band parameters not listed in Table 1 were taken from [11]. A single-energy-level approximation was used to model nitrogen freeze-out [12]. Refinements in simulation device parameters, such as doping compensation, channel etch depths, etc., were arrived at by iterative fitting of simulated results to measured data. However, all device parameters listed in Table 1 fall within expected uncertainties of the experimental device fabrication process across the wafer. The channel region not covered by the gate finger (Fig. 2b) was accounted for in the simulation. The approximate resistance of this parasitic leakage path was calculated from the slope of the measured belowthreshold drain I-V characteristic. Packaging and Interconnection An Al2O3 substrate and Au thick-film metallization [13] were used as the packaging framework. The SiC die was attached to the metallized packaging substrate using an in-house developed Pt-based electrically conductive die-attach p – type < 2 X 10, ~ 6-8 μm n – type 1-2 X 10 , ~ 0.2-0.4 μm p – type ~ 10 , ~ 1 μm SiC 6H p-type wafer ~ 400 μm Si3N4 Passivation Ti/TaSi2/Pt Ti/TaSi2/Pt Oxide Ion Implant Fig. 1: Schematic drawing of the structure of the MESFET. Source Gate