Synthèse et description de circuits numériques au niveau des transferts synchronisés par les données

RESUME Au-dela des processeurs d’instructions multi-coeurs, le monde du traitement numerique haute performance moderne est egalement caracterise par l’utilisation de circuits specifiques a un domaine d’application implementes au moyen de circuits programmables FPGA (reseau de portes programmables in situ). Les FPGA representent des candidats interessants a la realisation de calculs haute-performances pour differentes raisons. D’une part, le nombre importants de blocs de proprietes intellectuelles graves en dur sur ces puces (processeurs, memoires, unites de traitement de signal numerique) reduit l’ecart qui les separe des circuits integres dedies en termes de ressources disponibles. Un ecart qui s’explique par le haut niveau de configurabilite offert par le circuit programmable, une capacite pour laquelle un grand nombre de ressources doit etre dedie sans etre utilise par le circuit programme. Neanmoins dans un contexte ou souvent plus de transistors sont disponibles qu’on puisse en utiliser, le cout associe a la configurabilite s’en trouve d’autant reduit. De par leur capacite a etre reconfigures completement ou partiellement, les FPGAs modernes, tout comme les processeurs d’instructions, offrent la flexibilite requise pour supporter un grand nombre d’applications. Neanmoins, contrairement aux processeurs d’instructions qui peuvent etre programmes avec differents langages de programmation haut-niveau (Java, C#, C/C++, MPI, OpenMP, OpenCL), la programmation d’un FPGA requiert la specification d’un circuit numerique, ce qui represente un obstacle majeur a leur plus grande adoption. La description de circuits numeriques est generalement exprimee au moyen d’un langage concurrent pour lequel le niveau d’abstraction se situe au niveau des transferts entre registres (RTL), tels les langages VHDL et Verilog. Pour une application donnee, la realisation d’un circuit numerique specialise requiert typiquement un effort de conception significativement plus grand qu’une realisation logicielle. Il existe aujourd’hui differents outils academiques et commerciaux permettant la synthese haut-niveau de circuits numeriques en partant de descriptions C/C++/SystemC, et plus recemment OpenCL. Cependant, selon l’application consideree, ces outils ne permettent pas toujours d’obtenir des performances comparables a celles qui peuvent etre obtenues avec une description RTL produite manuellement. On s’interesse dans ce travail a un outil de synthese de niveau intermediaire offrant un compromis entre les performances atteignables au moyen d’une methode de conception RTL, ainsi que les temps de conception que permet la synthese a haut-niveau. ----------ABSTRACT Beyond modern multi/many-cores processors, the world of computing is also caracterized by the use of dedicated circuits implemented on Field-Programmable Gate-Arrays (FPGAs). For many reasons, modern FPGAs have become interesting targets for high-performance computing applications. On one hand, their integration of considerable amounts of IP blocks (processors, memories, DSPs) has contributed to reduce the resource/performance gap that exist with Application Specific Integrated Devices (ASICs). A gap that is easily explained by the high-level of reconfigurability that these devices provide, a feature for which a considerable amount of resources (transistors) must be dedicated. Nevertheless, in a context where often more transistors are often available than it is needed or required, the impact of such a cost is less important. The ability to reconfigure completely or partially modern FPGAs further offer the flexibility required to support multiple different applications over time, similarly to instruction processors. However, while instruction processors can be programmed with different high abstraction level software programming languages (Java, C#, C/C++, MPI, OpenMP, OpenCL), FPGA programming typically requires the specification of a hardware design, which is a major obstacle to their widespread use. The description of a hardware design is generally done at the register-transfer level (RTL), using hardware description languages (HDLs) such as VHDL and Verilog. For a given application, the design and verification of a dedicated circuit requires a significantly more important effort than a software implementation. Nowadays, numerous commercial and academic tools allow the high-level synthesis of hardware designs starting from a software description using programming languages such as C/C++/SystemC, and more recently OpenCL. Nevertheless, depending on the application considered, at current state of the art, these tools do not allow performances that matches those which can be obtained through hand-made RTL designs. In this work, we consider an intermediate-level synthesis methodology offering a compromise between the performances and design times that can be obtained with RTL and high-level synthesis methodologies. We consider an input hardware description language that allows the description of algorithmic state machines (ASMs) handling connections between sources and sinks with predefined streaming interfaces. These interfaces are similar AXI4-Streaming and Avalon-Streaming interfaces, featuring ready-to-send/ready-to-receive synchronisation signals.