Fault-tolerant design of RF front-end circuits

Kate Gleason College of Engineering Rochester Institute of Technology Degree Doctor of Philosophy Name of Candidate Tejasvi Das Program Microsystems Engineering Title Fault-Tolerant design ofRF Front-end Circuits The continuing trends of scaling in the CMOS industry have, inevitably, been accompanied by an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends . Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Two main reasons have contributed to the fact that fault-tolerant solutions for circuits that operate in the GHz domain have not been realized so far. First, GHz signals are extremely sensitive to higher-order effects such as stray pick-ups, interference, package & on-chip parasitics, etc. Secondly, the use of passives, especially inductors, in the feedback path poses huge area overheads, in addition to a slew of instability problems due to wide variations and soft faults. Hence traditional fault-tolerance methods used in digital and low frequency analog circuits cannot be applied in the RF domain. This work presents a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique is minimally intrusive and is transparent during 'normal' use of the circuit. It is characterized by low area and power overheads. does not need any off-chip computing or DSP cores, and is characterized by self-correction times in the range of a few hundreds of microseconds. It compares very well with existing commercial RF test solutions that use DSP cores and require hundreds of milliseconds. The methodology is demonstrated on a LNA, since it is critical for the performance of the entire front-end. It is validated with simulation and fabrication results of the system designed in IBM 0.25 Iilll CMOS 6RF process. Abstract Approval: Committee Chair Program Director DeanKGCOEApproval: Committee Chair Program Director DeanKGCOE iv P. R. Mukund Name Illegible Harvey J. Palmer Acknowledgements Four years of study at RIT culminates with this dissertation. As the 'graduate student' phase ofmy life ends, I take with me many cherished memories and humbling experiences. I express my gratitude and sincere appreciation to the many people who have been an integral part of it. To my dissertation committee members: Dr. Moon, Dr. Borkholder, Dr. Hirschman and Mr. Petilli, for your time and involvement in this work. Your suggestions and critique have made this work better. To Clyde Washburn, for your patient explanations and tutoring in circuit implementation and chip design. To Anand, for being a fellow traveler in this stimulating technical journey; and much more. To my colleagues: Ghanshyam, Anand, Simo, Priya, Sharmila, Mark, Eric and Chris. Working with you guys has been an exciting and delightful experience. To Sankha and Ajish, for being part of the insanity that was graduate-bachelorstudent-life. To my Aunt and Uncle in Brockport, for all your support and caring over the years. To Pooja and Preethi, for letting me behave like a ten-year old; and putting up with it. To Ajay. To my wife. To my parents and my brother. To Vanditha Aunty and Anu. To my fellow students: Prasanna, Anand, Ajay, Sharmila, Priya. This work and my time here at RIT are humbly dedicated to my teacher, my Guru, Dr. Mukund; from him I have had the privilege of learning much more than circuit design.