A track and hold circuit

A track and hold circuit is introduced, which includes a input buffer, a unit gain amplifier, a sampling switch, a current source, a driving NPN transistor and a over-driven protecting circuit. The over-driven protecting circuit is introduced to prevent the transistor of sampling switch from getting into linear working region. As a result, the sampling rate is improved dramatically. Meanwhile, two-stage insulation is adopted to prevent the incoming signal to disturb the holding signal on the sampling capacitor. Introduction Generally, track and hold circuits [1-4] are faster than the sample and hold circuits [5-9], because there is no settling time in the holding phase for track and hold circuits. A traditional track and hold circuit usually includes one or several input buffers, sampling switches, driving transistors and sampling capacitors. In the holding phase of the traditional track and hold circuit, the incoming signal is separated from the holding signal on the sampling capacitor only by one turn-off driving transistor which leads the strong coupling between the incoming signal and the holding signal. Furthermore, for traditional track and hold circuits, the transistor of the sampling switch gets into linear working region, which slows down the sampling rate dramatically. In this paper, a new track and hold circuit is introduced, which includes a input buffer, a unit gain amplifier, a sampling switch, a current source, a driving NPN transistor and a over-driven protecting circuit. The track and hold circuit works periodically, driven by a clock signal. The working period is divided into two phases: tracking and holding phases. In the tracking phase, the sampling switch is connected to the emitter of the driving transistor. The incoming signal is first buffered by the input buffer, then, amplified by the unit gain amplifier, and through the driving transistor to charge the sampling capacitor. At the end of the tracking phase, the sampling switch is disconnected from the emitter of the driving transistor and connected to its base, which starts the holding phase. In the holding phase, the base of the driving transistor is pulled down to shut it off resulting the holding of the charges on the sampling capacitor. Because of the adoption of the over-driven protecting circuit to prevent the transistor of sampling switch from getting into linear working region, the sampling rate is improved dramatically. Meanwhile, two-stage insulation is adopted to prevent the incoming signal to disturb the holding signal on the sampling capacitor. Circuit As shown in figure 1, the proposed track and hold circuit consists of a input buffer B1, a unit gain amplifier, a sampling switch S1, a current source U3, a driving NPN transistor N4, a sampling capacitor C1 and a over-driven protecting circuit. Furthermore, the unit gain amplifier consists of two NPN transistors N1 and N2 and two current sources U1 and U2. The two NPN transistors N1 and N2 form a differential pair with U2 as its tail current source and U1 as its sourcing load. The output of the unit gain amplifier is feedback to one of input of the differential pair and the other input is connected to the output of the input buffer B1. In order to set the unit gain amplifier in the best working condition, the magnitude of the current of U2 is designed to be two times that of the current of U1. International Power, Electronics and Materials Engineering Conference (IPEMEC 2015) © 2015. The authors Published by Atlantis Press 111 Furthermore, the over-driven protecting circuit consists of a PMOS transistor P1, a current source U4, a NPN transistor N3. A source follower is formed by PMOS transistor P1 and current source U4. The input end of the source follower is connected to the top plate of the sampling capacitor C1 while its output end is connected to the base of NPN transistor N3.