Heterogeneous Technology Configurable Fabrics : A Field-Programmable Paradigm for Leveraging Post-CMOS Devices in HPC

Discussions are advocated regarding the merits of Heterogeneous Technology Configurable Fabrics (HTCFs) to realize the needed architectural abstraction as a pathway to manage Extreme Heterogeneity (EH) facing High Performance Computing (HPC) in the post-Moore era. HTCFs are reconfigurable logic arrays that leverage the cooperative roles of emerging spintronic and CMOS devices within a runtime adaptable platform residing as compute-node accelerators within post-exascale computing centers. HTCFs advance the challenges of EH by providing a uniform and familiar programming interface to multiple emerging device technologies. HTCFs leverage and extend the robust experience base and versatility of reconfigurable computing technology, theory, and tools to reduce barriers towards hardware implementation and mass adoption of post-CMOS devices in HPC. Like CMOS-based FPGAs, they assist minimizing communication occurrence and cost while reducing software and hardware bloat. Finally, it will be advocated that HTCFs also enable the new advance of “technology co-design” which trades off alternative mappings between emerging devices and CMOS technology during circuit synthesis-time for placeand-route optimizations, and also during runtime by remapping hardware resource locality to vital features such as non-volatility. Keywords— Hardware Abstraction; Reconfigurable Computing Fabrics; Energy-Aware High Performance Computing; Dynamic Resource Optimization; Spintronics; Hardware Co-Design at Runtime. I. NEW PERSPECTIVE TOWARDS EMBRACING HETEROGENEITY It is advocated to debate the merits and implications of the vignette below as a transformative vision for post-Moore era HPC field-programmable accelerators. The perspective is to leverage both CMOS and post-CMOS devices for their relative strengths, such as fast switching speed, non-volatility, intrinsic addition/multiplication, and thresholding/neuromorphic computation which form a continuum of computational characteristics valuable to scientific computing. In particular, it is envisioned for Heterogeneous Technology Configurable Fabrics (HTCFs) to be available to the programmer and operating system as follows: Dateline: Advanced Scientific Computing Research (ASCR) site, USA; March 1, 2040. A scientific programmer seeks to solve incompressible Navier-Stokes equations facing challenging resolution and accuracy requirements. She considers the processing phases involved and functional modules of the algorithms used along with several hardware attributes. These include a TFLOPS budget, data retention time / non-volatility, and a static vs. dynamic energy profile of the primary modules. She proceeds to map her design onto a palette of computational resources that include some selected spinbased devices within a high gate-equivalent capacity HTCFcomponent, as depicted in Figure 1. This HTCF component is functionally-identical to a Field-Programmable Gate Array (FPGA) based accelerator in use today, except it allows field programmable access and mapping to beyond-CMOS devices. This mapping occurs “in the field,” i.e. in the computational center, without fabrication of custom hardware in the foundry, similar field-programmable access to CMOS-based hardware. She proceeds to enter source code which, as is already done today with FPGA-based translators via conversion to a Verilog functional description and configuration of IP blocks in a familiar FPGA-like specification, synthesis, and place-androute toolchain interface. Technology-aware design optimizers then examine a set of functionally-equivalent, but technologydistinct design mappings realized as a field-programmable interconnection within a heterogeneous fabric. This overcomes two near-term hurdles: (1) CMOS-only designs face challenges Figure 1: HTCF component vision. Physical devices consist of spintronic and CMOS elements within each HTCF Configurable Logic Block (H-CLB). H-CLBs comprise a larger field-programmable fabric of Functional Blocks (FBs) and Switch Blocks (SBs). DWM NML MTJ/SHE chargebased devices spinbased devices