The Evolution of Processor Architecture through Hardware & Software Advances for Energy Optimization and Power Reduction through the 21 st Century

The evolution of processor architecture has benefited the engineering community through optimization and power reduction. With optimization comes analysis of error and speedup times for different systems. The classical components of a computer are analyzed throughout this paper in order to compare values and how they have developed over a certain period of time. The metrics that will be presented are memory capacity, core count, clock rate, and word width. Throughout this paper, multiple examples will be given showing that faster does not always mean better and bigger does not always mean more storage or optimal performance. Other factors such as Moore’s Law is also included in this paper to show the reoccurring effects of previous theory. From the early 1900s to present day, the influence of pipelining and hardware advances in engineering have helped developers find ways to optimize certain architecture. Keywords—Memory Capacity, Clock rate, Moore’s Law, speedup, pipelining, power reduction, scaling, Amdahl’s Law, SNAP, OTBSAF, transistor growth I. OVERVIEW OF PROCESSOR ARCHITECTURE The 5 classic components of a computer system are input, output, memory, datapath and control. The input is the data that the user puts into the machine. The memory is the part of the machine that stores information. The datapath is a conveyer belt where bits move a long in order to transfer information. The control is part of the processor which gives instructions on how to use the data on the datapath. The output is the result of the given commands by the control given from memory. A bus in general is a bundle of wires. A processor can only operate on values that reside internally. Any value in memory must be transferred into the processor before the corresponding operation occurs. To obtain or provide a data value from or to memory, the processor must specify an address. Separate buses for address and data are used to connect the processor to memory. Operations the processor performs have different categories (i.e. arithmetic operations or data transfer between memory). Separate buses for address and data are used to connect the memory to processor. The data bus is a highway for data bits as d wires between processor and memory. The address bus has a=log_2 (memory size in bytes) wires which is determined by memory capacity only. The CPU clock rate determines how many instructions are executed per second. The number of different machine instructions is the instruction set size. Reducing the number of clock cycles is used to increase performance. Therefore it is necessary to reduce the instruction set size. The instruction set is the number of bits used for data representation. A bit is an acronym for Binary Digit. One bit indicates a single binary state (true/false). A byte is always 8 bits. A KB is 2^10 bytes. A MB is 2^20 (GB is 2^30 etc.). For memory, the prefixes always use base 2. For speed (frequency), the prefixes always use base 10. For example, 10KHz is 10*10^3 Hz. The specific metrics in Figure 1 are significant to describe the architectures at a high level of design abstraction because all computer systems have become faster and more efficient throughout the years. According to Moore’s law, the number of transistors on a chip doubles (2 fold) every 2 years. The clock rates are also increasing making program going through the instruction set exponentially faster. The processor performance equations for execution time in terms of instruction count, CPI, and cycle time is: CPU time = Instruction count x CPI x Cycle time The instruction count is the dynamic count of instructions executed at runtime, not the number of instructions of assembly code. The CPI is the effective or average number of clock periods that each instruction in the dynamic instruction mix of the program. The cycle time is the duration of time for one clock cycle of the processor. The use of parallelism and multiple cores to reduce execution time is an effective approach to improve performance by providing more processors or channels in