Towards Wearout-aware and Accelerated Self-healing Digital Systems

II. DISSERTATION ABSTRACT Background: Wearout (Aging) has been one of the most significant reliability concerns in digital systems as the technology scaling continues and technology node advances [1][2]. It is a long term process that is caused by several interrelated physical mechanisms that conspire to worsen system metrics by slowing the circuit down and increasing the power. Even though emerging technologies, such as FinFET, with excellent electrostatic properties and comparative ease of fabrication, appear to be good candidates for further extending the technology to the nanoscale regime, wearout is still a big threat [3][4]. Motivation: Wearout consists of both reversible and irreversible (permanent) parts that accumulate at different rates under stress, when the stress is removed, there is some level of recovery, but usually at much lower rate than the wearout. In the front-end of line (FEOL), Bias Temperature Instability (BTI) is one of the most prominent reversible wearout effects that shift transistor’s threshold voltage and further slow the circuit down. Similar shifts happen in the back-end of line (BEOL) for interconnect, with electromigration (EM) being the main wearout phenomenon that shortens metal wire lifetime, and become severe due to power delivery challenges for large ICs [2]. In the past decade, lots of work have been done in the field to deal with wearout issues from system level down to device level. There are two ways in general, one is to relax the design margin by adding guardband (>20% for several years), the added margins mean large timing slacks and therefore wasteful power consumption during the initial lifetime of the system. The second way is being adaptive to the wearout induced variations by tracking, monitoring and compensating dynamically [6], thus being able to design for the average case. The issue is that with scaling, the worst case becomes even worse and the distribution becomes skewed, thus the potential advantages of adaptation are also reduced, which means the system might function correctly with adaptation, but will still become sluggish and burn too much power. A better solution would be to somehow reduce the actual wearout induced variations. One way is to reduce the stress, thus to alleviate wearout during run time [7], it is obvious that this method will introduce performance overhead. Additionally, even for reversible wearout, like BTI, there is still a permanent part that is hardly recovered within a reasonable time. In this work, we propose an alternative solution which fundamentally repairs wearout without hurting performance by accelerating the recovery process with several methods, such as high temperatures, negative voltages and currents, UV light exposure and so on. To fully repair and avoid the irreversible wearout, a biology-inspired sleep-when-gettingtired strategy is also proposed and validated. Eventually, we will show how these methods will be applied at the system level and how to utilize accelerated recovery as a design knob during design phase by proposing a cross-layer optimization framework. Goals: The goals of our research are the following: 1. Explore and model the recovery behaviors of several wearout mechanisms, especially BTI and EM, with and without several accelerated self-healing techniques; 2. Explore the boundary between reversible and irreversible part of wearout, and the proper scheduled active and sleep ratio to fully alleviate wearout; 3. Develop and evaluate the on-chip solutions for the proposed accelerated self-healing techniques; 4. Develop a cross-layer optimization infrastructure that allows the design, analysis and optimization of systems across hierarchy. Accelerated Self-healing: Here we rephrase the notion of sleep for electronic systems since until now, sleep for systems is widely accepted as a period of inactivity or idleness, quite different from biological organisms which, during sleep, go through several essential active processes for the recovery of their full capabilities for the next day. In this work, we borrow the circadian rhythms inspired definitions for sleep, and demonstrate that sleep could actually be used as an active recovery period from wearout. During sleep, some of the effects (e.g. BTI and EM) can be reversed heavily by several techniques, such as applying high temperature and negative supply voltages, reversing the current direction flowing through the metal wire, using light exposure (e.g. UV), thus leading to effective accelerated self-healing. The sleep behaviors are studied on commercial FPGA chips fabricated in 40nm node, and the test structures are LUT-based ring oscillators that capture the frequency change during active and sleep periods. As shown in the Fig. 1, we demonstrate a test case where 72.4% of the wearout is recovered within only 1/4 of the stress time [C7]. The improvement will be directly translated to improved metrics, like relaxed design margin.