Low Voltage SC Circuit Design with Low-MOSFETs

In this paper, low threshold voltage (Vt) “natural” transistors, available in some n+/p+ dual poly gate CMOS/ BiCMOS processes [1], are proposed for low voltage switched capacitor circuit design. The impact of the subthreshold off-current of these low devices on the performance of analog switched-capacitor (SC) circuits is analyzed. Methods for reducing the subthreshold offcurrent in analog switches are discussed and two new switch topologies (series transmission gate and composite switch) addressing this problem are presented. 1.0 Introduction Analog integrated circuits are usually implemented using switched-capacitor (SC) techniques due to their high circuit accuracy. For low-voltage design, the most critical component in an SC circuit is the transmission gate switch which requires a gate voltage of at least 2Vt for proper, full-swing (strong inversion) signal handling [2]. In general, to achieve full signal transmission through a switch with acceptable on-resistance, either the gate voltage must be increased (i.e., clock multiplication if VDD<2Vt) [3], or the threshold voltage of the MOSFETs must be reduced. The former solution requires extra circuitry for voltage multiplication, may need an off-chip capacitor, and is noisy. The second solution solves the onresistance problem, but may require process modification [4]. It also raises concerns regarding the leakage current during the “off” phase. However, the second approach is compatible with the future of CMOS technology and low power digital design [7,8], because power supply scaling will eventually force Vt down-scaling. Moreover, in some dual n+/p+ poly gate processes [1], low-Vt MOSFETs (called “natural” transistors) are available without requiring any extra masks. In the following sections, the “natural” MOSFETs and associated subthreshold leakage off-current are briefly described. Then impacts of the leakage off-current on the precision of SC circuits are analyzed. Finally, methods and circuit techniques for reducing the leakage off-current through analog switches are discussed. ‡Currently on educational leave of absence from Bell Northern Research/Northern Telecom. 2.0 Low Vt Natural MOSFETs As channel lengths of MOSFET transistors are shrunk to 0. 5μm and below, buried-channel pMOSFET devices with strong short-channel effects must be replaced with surface channel devices. This requires a dual poly gate technology, where n+ poly is used for nMOSFET and p+ poly is used for pMOSFET. In some dual n+/p+ poly gate processes [1], it is possible to mask out the threshold adjust implant and obtain the low-Vt MOSFETs called “natural” transistors. The threshold of the natural transistors is about 0.2V-0.3V which is suitable for low voltage (e.g., V) design. 2.1 Subthreshold off-Current A turned off MOSFET (vG=0) operates in weak inversion mode where drain current is exponentially dependent on the value of “vGS-Vt”. In saturation (i.e., when drainsource voltage is much greater than the thermal voltage, 25mV@room temperature), the subthreshold off-current is given by the following simplified equation (1) where, ID0 is the value of the drain current when the gate to source voltage is set to Vt [2] and S is the subthreshold swing. Equation (1) shows that as Vt reduces, the offcurrent increases, causing degradation in the precision of the analog SC circuits, as described below. 2.2 Effects of leaky switches in an SC integrator A stray-insensitive SC integrator and its associated nonoverlapping clocks ( and ) are shown in Figure 1. For rail-to-rail signal handling, switch is implemented with a full transmission gate (an nMOSFET and an pMOSFET in parallel) and all the others switch to analog ground ( ) and thus can simply be nMOSFET transistors. Vt