All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores

The Internet-of-Things (IoT) revolution fueled new challenges and opportunities to achieve computational efficiency goals. Embedded devices are required to execute multiple applications for which a suitable distribution of the computing power must be adapted at run-time. Such complex hardware platforms have to sustain the continuous acquisition and processing of data under severe energy budget constraints, since most of them are battery powered. The state-of-the-art offers several ad-hoc contributions to selectively optimize the performance considering aspects like energy, power, thermal, or reliability. However, there is a need for a generic coordinated management strategy able to cope with all of these dimensions, while allowing the Operating System (OS) and the applications to “suggest” or constrain the actuation. This article proposes a unified control-theoretic scheme to coordinate the design of energy-budget and energy allocation solutions for multi-cores. The proposed controller can work with any actuator and it can interact, at run-time, with both the applications and the OS to optimize the actuation signals steering the computing platform. Such control scheme offers the possibility to integrate any performance related policy in the form of an energy-allocation strategy, still ensuring the theoretic exponential stability of the overall controller if the actuation of the policy, coming from the OS and the applications, “is not too fast. ” To demonstrate the feasibility of our solution, we have implemented the controller into a RISC multi-core running on the Xilinx Artix 100t FPGA device, available in the the Digilent Nexys4-DDR board. Results considering two actuators and both the quad- and the eight-core version of the considered computing platform, highlight the scalability of the proposed solution as well as an area overhead for the –all digital, on chip–controller limited to 0.86 percent (FFs) and 5.3 percent (LUTs) of the FPGA chip. We also considered a dynamic scenario validating the speed of the controller, where our framework has to face with modifications to the energy-allocation control policy carried out by the OS and the applications. The obtained results are collected by executing a huge mix of benchmarks and the statistical significance is accounted by executing each scenario 30 times. Such results are analyzed considering three quality metrics. First, the efficiency in exploiting the imposed budget (<inline-formula><tex-math notation="LaTeX">$EFF_g$</tex-math><alternatives><mml:math><mml:mrow><mml:mi>E</mml:mi><mml:mi>F</mml:mi><mml:msub><mml:mi>F</mml:mi><mml:mi>g</mml:mi></mml:msub></mml:mrow></mml:math><inline-graphic xlink:href="zoni-ieq1-2963859.gif"/></alternatives></inline-formula>) that is on average 98.27 percent. Second, the overflow of the actual average power consumption with respect to the assigned budget (<inline-formula><tex-math notation="LaTeX">$OVF_g$</tex-math><alternatives><mml:math><mml:mrow><mml:mi>O</mml:mi><mml:mi>V</mml:mi><mml:msub><mml:mi>F</mml:mi><mml:mi>g</mml:mi></mml:msub></mml:mrow></mml:math><inline-graphic xlink:href="zoni-ieq2-2963859.gif"/></alternatives></inline-formula>), which is limited to 1.43 mW on average. Last, the performance utility loss due to the control scheme that is limited to 1.87 percent on average.