Statistical Yield Analysis and Design for Nanometer VLSI

Process variability is the pivotal factor impacting the des ign of high yield integrated circuits and systems in deep sub-micron CMOS technologies. The electr ical and physical properties of transistors and interconnects, the building blocks of inte grated circuits, are prone to significant variations that directly impact the performance and power c onsumption of the fabricated devices, severely impacting the manufacturing yield. However, the l arge number of the transistors on a single chip adds even more challenges for the analysis of the variation effects, a critical task in diagnosing the cause of failure and designing for yield. Reli able and efficient statistical analysis methodologies in various design phases are key to predict th e yield before entering such an expensive fabrication process. In this thesis, the impacts of process variations are examin ed at three different levels: device, circuit, and micro-architecture. The variation models are provided for each level of abstraction, and new methodologies are proposed for efficient statistica l an lysis and design under variation. At the circuit level, the variability analysis of three cruc ial sub-blocks of today’s systemon-chips, namely, digital circuits, memory cells, and anal og blocks, are targeted. The accurate and efficient yield analysis of circuits is recognized as an e xtremely challenging task within the electronic design automation community. The large scale of the digital circuits, the extremely high yield requirement for memory cells, and the time-consu ming analog circuit simulation are major concerns in the development of any statistical analys is technique. In this thesis, several sampling-based methods have been proposed for these three t ypes of circuits to significantly improve the run-time of the traditional Monte Carlo method, w ithout compromising accuracy. The proposed sampling-based yield analysis methods benefit from the very appealing feature of the MC method, that is, the capability to consider any comp lex circuit model. However, through the use and engineering of advanced variance reduct ion and sampling methods, ultrafast yield estimation solutions are provided for different types of VLSI circuits. Such methods include control variate, importance sampling, correlatio n-c ntrolled Latin Hypercube Sampling, and Quasi Monte Carlo. At the device level, a methodology is proposed which introdu ces a variation-aware design perspective for designing MOS devices in aggressively scal ed geometries. The method introduces a yield measure at the device level which targets the sa uration and leakage currents of an MOS transistor. A statistical method is developed to optimi ze the advanced doping profiles and geometry features of a device for achieving a maximum device -lev l yield. Finally, a statistical thermal analysis framework is propo sed. It accounts for the process and thermal variations simultaneously, at the micro-architec tural level. The analyzer is developed, based on the fact that the process variations lead to uncerta in leakage power sources, so that the thermal profile, itself, would have a probabilistic nature. Therefore, by a co-process-thermalleakage analysis, a more reliable full-chip statistical le kage power yield is calculated.