Crossbar-Constrained Technology Mapping for ReRAM Based In-Memory Computing

In-memory computing has gained significant attention due to the potential for dramatic improvement in speed and energy. Redox-based resistive RAMs (ReRAMs), capable of non-volatile storage and logic operations simultaneously have been used for logic-in-memory computing approaches. To this effect, we propose <italic>Re</italic>RAM based <italic>V</italic>LIW <italic>A</italic>rchitecture for in-<italic>M</italic>emory com<italic>P</italic>uting (ReVAMP), supported by a detailed device-accurate simulation setup with peripheral circuitry. We present theoretical bounds on the minimum area required for in-memory computation of arbitrary Boolean functions specified using structural representation (And-Inverter Graph and Majority-Inverter Graph) and two-level representation (Exclusive-Sum-of-Product). To support the ReVAMP architecture, we present two technology mapping flows that fully exploit the bit-level parallelism offered by the execution of logic using ReRAM crossbar array. The area-constrained mapping (<italic>ArC</italic>) generates feasible mapping for a variety of crossbar dimensions while the delay-constrained mapping (<italic>DeC</italic>) focuses primarily on minimizing the latency of mapping. We evaluate the proposed mappings against two state-of-the-art technology in-memory computing architectures, PLiM and MAGIC along with their automation flows (SIMPLE and COMPACT). <italic>ArC</italic> and <italic>DeC</italic> outperform state-of-the-art PLiM architecture by <inline-formula><tex-math notation="LaTeX">$1.46\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1</mml:mn><mml:mo>. </mml:mo><mml:mn>46</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq1-2964671.gif"/></alternatives></inline-formula> and <inline-formula><tex-math notation="LaTeX">$4.3\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>4</mml:mn><mml:mo>. </mml:mo><mml:mn>3</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq2-2964671.gif"/></alternatives></inline-formula> on average in latency. <italic>ArC</italic> offers significantly lower area (on average <inline-formula><tex-math notation="LaTeX">$25.27\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>25</mml:mn><mml:mo>.</mml:mo><mml:mn>27</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq3-2964671.gif"/></alternatives></inline-formula> and <inline-formula><tex-math notation="LaTeX">$6.57\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>6</mml:mn><mml:mo>.</mml:mo><mml:mn>57</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq4-2964671.gif"/></alternatives></inline-formula>), while improving the area-delay product by <inline-formula><tex-math notation="LaTeX">$1.37\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1</mml:mn><mml:mo>. </mml:mo><mml:mn>37</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq5-2964671.gif"/></alternatives></inline-formula> and <inline-formula><tex-math notation="LaTeX">$1.12\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1</mml:mn><mml:mo>. </mml:mo><mml:mn>12</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq6-2964671.gif"/></alternatives></inline-formula> against two mapping approaches for MAGIC respectively. In contrast, <italic>DeC</italic> achieves average area (<inline-formula><tex-math notation="LaTeX">$1.45\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1</mml:mn><mml:mo>.</mml:mo><mml:mn>45</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq7-2964671.gif"/></alternatives></inline-formula> and <inline-formula><tex-math notation="LaTeX">$3.06\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>3</mml:mn><mml:mo>.</mml:mo><mml:mn>06</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq8-2964671.gif"/></alternatives></inline-formula>) and area-delay product (<inline-formula><tex-math notation="LaTeX">$1.12\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1</mml:mn><mml:mo>.</mml:mo><mml:mn>12</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq9-2964671.gif"/></alternatives></inline-formula> and <inline-formula><tex-math notation="LaTeX">$6.36\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>6</mml:mn><mml:mo>.</mml:mo><mml:mn>36</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="bhattacharjee-ieq10-2964671.gif"/></alternatives></inline-formula>) improvements over the mapping approaches for MAGIC architecture respectively. The proposed mapping techniques allow a variety of runtime efficiency trade-offs.