Miracle-dz/UniFAR-FTUs huggingface dataset:
MapReduce++: Ecient Processing of MapReduce Jobs in the Cloud ?

MapReduce is the most popular processing framework and it has gotten a big successful in the large scale applications on the clusters. In this paper, we proposed a new massive data processing framework MapReduce++. We focus on the massive MapReduce tasks’ ecient processing and hope to get a good response time for these tasks’ total time. To archive this goal, we designed an ecient processing algorithm of MapReduce tasks. We proposed a time cost model for the massive tasks’ processing. And our algorithm will consider all tasks’ time cost base this cost model of massive tasks processing, and nd a better tasks’ executing strategy and reduce all these tasks’ whole time cost. Simulation experiment showed that our algorithm will improve the eciency a lot.
One tree‐one unit: a hypothesis for the conceptual sources underlying generation

The work-a-day business of generation researchers is how to account for the enormous variation in expression that is available to human speakers, and how to bring that diversity under control for deliberate, contextually appropriate use by machine speakers. A necessary first step in any such account is to establish what the generator starts from - different assumtpions can lead to dramatically different accounts. Under contract to a funding agency, we take what-ever representation the application we are interfacing to uses and make do. But in doing basic research we would like a firmer basis for our accounts than just engineering adequacy.
Verifying security protocols by combining static analysis and model checking

In systems that require secure communication between agents, the protocols that are designed to make this as secure as required, often prove to be the weakest link in ensuring security. As a result, a lot of research has recently been done on methods to automatically verify certain properties about these protocols, so that we may find and correct flaws before a protocol is put to use. LySa is a process calculus which has been specifically designed to specify the behaviour of security protocols. In contrast to many more common methods of specifying these protocols, LySa forces the author to be explicit about all details of the behaviour. The LySa Tool is a program that reads a protocol specified in the LySa calculus and uses static analysis techniques to verify certain properties. Because the LySa Tool over-approximates the behaviour of the protocol in its analysis, no absolute certainty is provided if the tool reports a flaw. Additionally, the tool’s output is often not enough to reconstruct an attack or to fix the flaw. By means of model checking, a common technology for verifying communicating systems, we hope to address these limitations. Using a toolset such as mCRL2, we gain absolute certainty about the behaviour of a protocol in a finite scenario and we can automatically construct an instance of an attack if a flaw is found. We conclude that model checking using mCRL2 and LySa’s static analysis can be combined into a strong and efficient means of verifying security protocols, and we describe how this can be done.
First results and status of the PHARUS phased array airborne SAR

PHARUS is an airborne fully polarimetric C-band SAR. It uses a compact phased array antenna with electronic beam steering. Its design provides for a flexible and robust system concept, suited for operational use on small aircraft. PHARUS was developed in The Netherlands to cater for both the military and civil markets. Its development was initiated in 1987 and has now resulted in completion of the system, which made its maiden flight in September 1995. In the paper, the particulars of PHARUS are discussed, with special attention to the antenna, followed by the SAR processing, use of the system, its history and status, and foreseen future developments.
Overview of the START(*T) multithreaded computer

The author provides an overview of the START(*T) computer system being implemented by MIT and Motorola. *T is a scalable computer architecture designed to support a broad variety of parallel programming styles, including those which use multithreading to tolerate the increases in memory latency which occur as the machine size is scaled up. The hardware uses a customized reduced instruction set computer (RISC) microprocessor with a network messaging interface and synchronization unit tightly coupled into the processor architecture. This hardware is coupled with a high-performance network having a fat-tree topology with high cross-section bandwidth. In addition, a HIPPI I/O system provides access to the world of supercomputer-class I/O devices. An innovative software architecture is layered on this hardware to produce a working system which is at its foundation a UNIX-like software environment. The software architecture specifies the structure of parallel programs and the way that they can be controlled and debugged. <<ETX>>
Complexity of Linear Boolean Operators

How to compute a linear Boolean operator by a small circuit using only unbounded fanin addition gates? Because this question is about one of the simplest and most basic circuit models, it has been considered by many authors since the early 1950s. This has led to a variety of upper and lower bound arguments—ranging from algebraic (determinant and matrix rigidity), to combinatorial (Ramsey properties, coverings, and decompositions) to graph-theoretic (the superconcentrator method). We provide a thorough survey of the research in this direction, and prove some new results to fill out the picture. The focus is on the cases in which the addition operation is either the boolean OR or XOR, but the model in which arbitrary boolean functions are allowed as gates is considered as well.
Characterization of leakage power in CMOS technologies

A model to statistically characterize the leakage power of CMOS digital circuits is presented. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. Also, in order to estimate the leakage power variability for a fixed state, a model of variations due to process is introduced. Using these models, the P/sub LEAK/ distribution is found to be asymmetric around the nominal value showing a long tail for high consuming circuits. The model has been found effective in evaluating the correlation of leakage power with other performance specs, in particular delay. We have shown that an IC with short L, and therefore, with high P/sub LEAK/ will be faster than nominal ones and an IC with long L, and therefore, with low P/sub LEAK/ will be slower. Predicted results are consistent with available experimental data.
FPGA Based Implementation of Robust Watermarking System

The study of communication security includes not just encryption but also traffic security, whose essence lies in hiding information. In the paper we are going to introduce a new approach that enables us to conceal the very existence of the message: The host digital media file will be unchanged, but a key which is based on a seed number will be communicated and generates a sequence of numbers that identifies bits in the host digital media file that contains the secret message. Therefore, no statistical artifacts that would aid anyone trying to crack the code are introduced. However, the limitation of capacity has led us to think about an improved approach which can be achieved through hardware implementation systems on a help of a programmable gate array (FPGA) board.
3D Reconstruction of Dynamic Scenes Dedicated to an Image Sensor of a Visual intracortical stimulator

This paper explores the thermal problems in future CMPs in multiprogrammed environment for heat balancing. We first give the observation of the temperature variation of cores in this scenario. Then we propose a temperature-aware submesh allocation scheme to manage cores with submeshes and allocate submeshes of cores to jobs under temperature-aware policies to balance heat chip-wide. Several scheduling policies are suggested and a HotSpot-based thermal simulator is used to evaluate the scheme and its policies under the workloads of benchmark programs. Simulation results show that our proposed scheme with global coolest policy and global neighbor-aware policy can lead to lower peak temperatures and effectively reduce the temporal variance and spatial variance of temperatures of cores to achieve better heat balance.
Low-Power Bus Architecture Composition for AMBA AXI

A system-on-a-chip communication archi- tecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we pre- sent the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication archi- tecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.
A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (σVth) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-㎚ CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to 6σ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.
Multimedia summaries of broadcast news

Increasing amounts of text, audio, and video content has fueled efforts to provide direct, content based access to these materials. Summaries are often necessary to enable timely relevancy assessments, information extraction, or information analysis from source material. Whereas text summarization research is receiving increasing attention, comparatively few investigators have examined video summarization. We report on the extension of a broadcast news access system to provide multimedia summaries. We briefly overview our system for video analysis, focusing on our novel integration of image, speech and language processing techniques to support automated video summarization. We outline algorithms for proper name and keyphrase extraction, story segmentation, and key frame extraction which together underpin our current ability to automatically summarize video. We describe the systems ability to generate multimedia video summaries tailored to a user query. We discuss evaluation metrics for measuring the (quality) value of these summary artifacts.
A parallel architecture for arithmetic coding and its VLSI implementation

A new parallel architecture for arithmetic coding is presented in this paper. By dividing the input symbols into a number of groups and processing them in parallel, significant speed-up can be achieved in comparison with existing architectures. The advantages of this parallel architecture are its easier expandability, higher speed, and smaller latency. The parallel arithmetic coder has also been implemented on VLSI using the VHDL technique. The resultant chip layout has a size of 4993/spl times/6503 /spl mu/m/sup 2/.
Incremental inheritance mechanism and its message evaluation method

The semantics of inheritance is based on subtyping. Several authors have shown that the subtype relation is insufficient to explain the inheritance mechanism in object oriented approach. Inheritance is an incremental mechanism for software development, based on modification. This approach was introduced by W.R. Cook. The aim of this paper is to present, an incremental formal model of single and multiple inheritance, based on the wrapping concept. The model is based upon an intuitive explanation of the proper use and purpose of inheritance, and is essentially dedicated to dynamic (i.e. run-time) inheritance of properties, for OODBMS. The denotational semantics method proposed using the incremental model of inheritance, allows dynamic message evaluation.
Coefficient memory addressing scheme for high performance FFT processors

A novel scheme for coefficient address generation in a fast Fourier transform (FFT) processor is presented. The proposed addressing scheme involves manipulation of the address lines taking into consideration coefficient addresses required at various FFT stages. It is demonstrated that the scheme can be implemented more efficiently with much reduced hardware than approaches published to date, leading to faster, more power and area efficient realisation of FFT processors.
Code-coverage Based Test Vector Generation for SystemC Designs

This work presents a methodology for the automatic test vector generation for SystemC combinational designs based on code coverage analysis which is complementary to the functional testing. The method uses coverage information to generate test vectors capable of covering the portions of code not exercised by the black-box testing. Vectors are generated using an instrumented code followed by a numerical optimization method. This approach does not suffer from restrictions related to symbolic execution such as defining array reference values and loop boundaries, as the code is really executed together with the optimization. We expect this combined methodology to achieve total code coverage of the design and reduce the fault of omission problem, undetectable by structural testing alone.
The Trustworthiness Based on Hash Chain in Wireless Sensor Network

With a variety of attacks, this paper proposes a novel solution which requires establishing a trust among all nodes in mobile sensor networks and develops a material scheme which can achieve the goal. The scheme includes a mechanism to establish a trusted relation between all neighboring nodes and avoid untrustworthy nodes during the route discovery process. And it can resist DoS-style flooding attacks. The work presents this scheme, and reports its performance using an extensive set of simulation set of experiments. The results indicate clearly that resisting DoS can be achieved in wireless sensor network. And the additional overhead of our scheme is reasonably low.
State-based Time-Series Analysis and Prediction

Time representation and temporal reasoning plays an important role in time-series analysis and prediction, which involve dealing with varying situations in terms of states of the world evolving with time. Generally speaking, the world in the discourse persists in a given state until some action(s) is carried out, or some event(s) occurs, to change it into another state. This paper presents a framework for prediction and analysis based on time-series of states. It takes a time theory that addresses both points and intervals as primitive time elements on an equal footing as the temporal basis. A state of the world under consideration is defined as a set of time-varying propositions that include properties, facts, actions, events, processes and anything else with Boolean truth-values that are dependent on time. A time-series of states is then defined as a list of states temporally ordered one after another. The framework supports explicit expression of both absolute and relative temporal knowledge. While a formal schema for expressing general time-series of states is given, allowing a time-series of states to be incomplete in various ways, the concept of complete time-series of states is also formally introduced. As the application of the proposed formalism in prediction and time-series analysis, illustrating examples are provided.
A fractional&#8211;N frequency synthesizer with a 3&#8211;bit 4thorder &#931;&#8211;&#916; modulator

A fractional-N frequency synthesizer in a 0.5-µm BiCMOS technology is presented. A 3-bit 4th order Σ-Δ modulator employs an interpolative architecture with multiple feedback paths and metal-connected multipliers to implement the feedback coefficients, resulting in a simple hardware complexity, lower out-of-band phase noise, a frequency resolution of less than 10-Hz, and agile switching time. The experimental results show - 73dBc/Hz in-band phase noise and -142dBc/Hz out-of-band phase noise at 1MHz offset frequency. The fractional spurs are less than -80dBc/Hz at 200KHz offset frequency and the reference spur is -87dBc/Hz. The proposed synthesizer consumes 5.5mA from a single 3-V supply voltage and meets the requirements of most RF applications.
An optimization technique for the design of half-plane 2-D recursive digital filters

An iterative optimization technique, based on a Modified Marquardt algorithm, is proposed for the design of asymmetric 2-D half-plane recursive digital filters with a zero-phase implementation. To illustrate the technique a fan-filter and a circular lowpass filter were designed. The technique can also be used for the design of quarter-plane filters.
High resolution signal reconstruction

We present a framework for speech enhancement and robust speech recognition that exploits the harmonic structure of speech. We achieve substantial gains in signal-to-noise ratio (SNR) of enhanced speech as well as considerable gains in accuracy of automatic speech recognition in very noisy conditions. The method exploits the harmonic structure of speech by employing a high frequency resolution speech model in the log-spectrum domain and reconstructs the signal from the estimated posteriors of the clean signal and the phases from the original noisy signal. We achieve a gain in SNR of 8.38 dB for enhancement of speech at 0 dB. We also present recognition results on the Aurora 2 data-set. At 0 dB SNR, we achieve a reduction of relative word error rate of 43.75% over the baseline, and 15.90% over the equivalent low-resolution algorithm.
A genetic-based control design for damping power system inter-area oscillations

This paper presents the design of linear robust decentralized fixed-structure power system damping controllers using genetic algorithms (GA). A classical control structure consisting of a gain, a wash-out stage and two lead-lag stages is assumed. The GA searches for an optimum solution over the controller parameter space. Controller robustness is taken into account as the controller optimization is performed for various system operating conditions. A true decentralized control design is achieved as the loop control channels are closed simultaneously. The approach is used to design static VAR compensator (SVC) and thyristor-controlled series compensator (TCSC) damping controllers to enhance the damping of two inter-area modes in a small power system.
Elastically Ruling the Cloud: Specifying Application's Behavior in Federated Clouds

Most Infrastructure as a Service clouds present limited capabilities to control how a service behaves at runtime, once it has been deployed, beyond basic low-level scalability rules for VMs. Higher-level approaches fail to provide mechanisms for a fine grained level of control of the service at runtime, being only focused on scaling. These scalability rules are based on an ad hoc ``grammar'' that is not expressive enough to reflect other desired control mechanisms at runtime (e.g. reconfigurations, dynamic changes in the rules or in the components of the application, retiering, etc.). Here, we present an analysis on different alternatives for supporting such features. The Rule Interchange Format (RIF) emerges as a likely candidate to support the required flexibility and so it is proved in a typical use case. Also, a preliminary implementation of a mapping mechanisms is offered to parse RIF rules to widespread rule engines such as Drools and Jess.
A Simple and Analytical Design Approach for Input Power Matched On-chip CMOS LNA

A simple and analytical design approach for input power matched CMOS RF LNA circuits and their scaling for lower power consumption, is introduced. In spite of the simplicity of our expressions, it gives excellent agreement with numerical simulation results using commercial CAD tools for several circuit examples performed at 2.4GHz using 0. 18µm CMOS technology. These simple and analytical results are extremely useful in that they can provide enough insights not only for designing any CMOS LNA circuits, but also for characterizing and diagnosing them whether being prototyped or manufactured.
Cell contour detection in corneal endothelium in-vivo microscopy

In-vivo microscopy of corneal endothelium is a technique routinely adopted in ophthalmic investigation. The main features to be extracted are cell density and morphology. Even if recognizing cell contour and counting cell bodies is common practice for any ophthalmologist, this task has proven to be very difficult in its automation due to the very low image quality. The problem is actually a difficult segmentation problem where the two regions to be identified are cell bodies and cell boundaries. The quality of the image is generally so compromised that conventional and also sophisticated segmentation algorithms found in the literature do not work. The new algorithm we have developed is composed of a first segmentation module, based on a neural network structure with two-dimensional inputs and outputs, whose neuron weights are numerical filters specifically designed for a border extraction problem and derived from the boundary contour system approach (Grossberg et al.). However, gray-level information alone is not sufficient to correctly discriminate between cell bodies and cell boundaries. To cope with the wrong results still present in the segmented image (missing contours or false contours), a second module has been developed, which applies a so called "expert correction", based on an automatic, multiple-step approach, which includes missing contour recovery and tentative merging or splitting of cell bodies. The preliminary results are very satisfactory, since in a set of more than 300 images of corneal endothelium the difference between the automatic cell count and the human expert one is on average less than 5%.
A new mesh simplification algorithm combining half-edge data structure with modified quadric error metric

This paper presents a fast mesh simplification algorithm that combines the half-edge data structure with modified quadric error metric (QEM). When half-edge structure is used, the adjacency queries between components of the mesh, such as vertices, faces and edges, can be quickly achieved and thus the run time is reduced remarkably. Furthermore, with the modified quadric error metric, the quality of the simplified meshes for a certain kind of 3D medical models whose normal vectors are computed through voxel gradient during reconstruction can be greatly improved. The experimental results illustrate the efficiency of the algorithm.