Integration and evaluation of cache coherence protocols for multiprocessor socs

The objective of this thesis is twofold. The first objective is to provide generic methodologies for enabling efficient communication among heterogeneous processors in multiprocessor system-on-a-chips (MPSoCs). The second objective is to evaluate the coherence traffic efficiency based on a novel emulation platform using FPGA. Embedded systems have several properties for system-on-a-chip (SoC) designers to abide by: low-cost, low-power, soft or hard real-time constraint, and short time-to-market requirement. These properties coerce industries into embracing the IP-based design concept. Exhibiting this design trend, international consortia such as OCP-IP and VSIA devised standard SoC interface protocols for the seamless integration of heterogeneous IP blocks. To meet their performance and cost constraint, SoC designers integrate multiple, sometimes, heterogeneous processor IPs to perform particular functions. Nevertheless, the integration of heterogeneous processors arouses complications because of different interface protocols and incompatible communication mechanisms, in particular, cache coherence protocols. Whereas the interface problems are being well studied in academia and industry, the communication problems among heterogeneous processors have not been addressed. The first two contributions of the thesis provide efficient communication mechanisms among heterogeneous processors via the integration and support of cache coherence protocols in MPSoCs. Heterogeneous processors have incompatible coherence protocols. Hence, special care should be taken to efficiently make use of existing hardware in processors' IPs. Our contributions addressed coherence problems for two main MPSoC architectures: Shared-bus-based MPSoCs and Non-shared-bus-based MPSoCs. In shared-bus-based MPSoCs, the integration techniques guarantee data consistency among incompatible coherence protocols. An integrated protocol will contain common states from distinct coherence protocols. A snoop-hit buffer and region-based cache coherence were also proposed to further enhance the coherence performance. For non-shared-bus-based MPSoCs, the bypass and bookkeeping approaches were proposed to support cache coherence in a new cache coherence-enforced memory controller. The simulations based on micro-benchmark and RTOS kernel showed the benefits of the methodologies over a generic software solution. The third contribution of the thesis evaluated the coherence traffic efficiency. As the memory wall becomes higher, it is imperative to understand the impact of communication among processors and enhance future communication architectures based on observations. Traditionally, the evaluations of the snoopy protocols focused on reducing bus traffic using trace-based or execution-driven simulations, and the impact of coherence traffic on system performance has not been explicitly investigated. Using an Intel server system and an FPGA, our novel method measured and quantified the intrinsic delay of coherence traffic and evaluated its efficiency. The intrinsic delay was measured by completely isolating the impact of coherence traffic on system performance. The technique eliminated non-deterministic factors in measurements such as bus arbitration delay and stall in the pipelined bus. The experimental results showed that the cache-to-cache transfer in the Intel server system is less efficient than the main memory access.