Study of Various ADCs and Compare Their Performance and Parameters

The performance of the analog to digital converters has become very important in signal processing applications. Most important parameters on which theirperformance depend are: resolution, conversion time and the sampling frequency of input. It became very important to understand the functioning and performance before implementing the ADC in the system. This paper discusses various types of ADCs and compares the commonly used ADCs so that user can conveniently choose between various ADCs available for their application. KeywordsResolution, Conversion time, Chip area of ADC, sampling frequency. I. COUNTER TYPE ADC It is the basic type of ADC which is also called as digital ramp type ADC or stair case approximation ADC. Fig1: Counter Type ADC The counter generates an N bit digital output which is applied as an input to the DAC. The analog output corresponding to the digital input from DAC is compared with the input analog voltage using an OpAmp comparator. The Op-Amp compares the two voltages and if the generated DAC voltage is less, it generates a high pulse to the N bit counter as a clock pulse to increment the counter. The same process will be repeated until the DAC output equals to or greater than the input analog voltage. If the DAC output voltage is equal to or greater than the input analog voltage, then it generates low clock pulse and it also generates a clear signal to the counter and load signal to the storage resistor to store the corresponding digital bits. These digital values are closely matched with the input analog values with small quantization error. For every sampling interval, the DAC output follows a ramp fashion that is why, it is called as Digital ramp type ADC, this ramp looks like stair cases for every sampling time so, and it is also called as staircase approximation type ADC. Conversion time of Counter type ADC Conversion time of ADC is the time taken by the ADC to convert the input sampled analog value to digital value. Here the maximum conversion of high input voltage for N bit ADC is the clock pulses required to count its maximum count value. So, the maximum conversion of Counter type ADC is equal to (2 N -1) T where T is the time period of clock pulse. Limitations of Counter type of ADC is thatspeed is less because every time the counter has to start from ZERO.There may be clash or aliasing effect if the next input is sampled before completion of one operation. II. TRACKING TYPE ADC In counter type DAC, the counter has to come to zero for every conversion which is a disadvantageous with respect to high conversion time. To perform operation, instead of using normal counter, this ADC uses up /down counter. After the first sampled value, the up/down counter will tracks the input analog value so that it is called tracking type of ADC [19]. The detailed block diagram of Tracking type ADC is shown in below figure. Fig 2: Tracking Type ADC International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190 89 www.ijaert. org The N bit up/down counter starts counting according to the clock pulse and provides a digital input to the DAC. The DAC converts the digital input intocorresponding analog output which is applied to Op-Amp. The OpAmp compares the DAC analog output with the input analog sampled value, if the input value greater than the DAC output it provides a clock pulse to increment the counter or otherwise if it is lesser than the DAC output it provides a clock pulse to decrement the counter. But normally for first sampled value the counter will incremented to match to the analog value and for subsequent samples only the counter may get decrement pulse. When the DAC output is equal to the sampled value, the digital output will be taken from the up/down counter directly. Here shift register is not needed to capturedigital data because the counter will not go to reset state. Then, onwards for the next sample value, the counter will increment or decrement according to the difference output of Op-Amp. This is also called as Derivative Counter type ADC because the counter output depends on difference between the previous and next sampled value like as differentiator. Advantages of this ADC are that Shift register is not needed so the cost is less.Speed is high compared to digital ramp type as the counter will not reset. Disadvantages of tracking type ADC is that Up/Down counter leads to complexity of the circuit. The digital output will never be constant because of differentiator effect. i.e., for a constant analog value also the output will oscillating this is known as bitbobble. III. SUCCESSIVE APPROXIMATION ADC One method of addressing the digital ramp ADC’s shortcomings is successive approximationADC. The only change in this design is a very special counter circuit known asSuccessive Approximations RegisterInstead of counting up in binary sequence, this register counts by trying all values of bits starting with the most-significant bit and finishing at the least significant bit. Throughout the count process, the register monitor the comparator’s output to see if the binary count is less than or greater than the analog signal input, adjusting the bit values accordingly [19]. The advantage to this counting strategy is much faster results: the DAC output converges on the analog signal input in much larger steps than with the 0 to full count sequence of a regular counter. Important point to note on Successive Approximation ADC is that in Counter type or digital ramp type ADC the time taken for conversion dependson the magnitude of the input, but in SAR the conversion time is independent of applied input voltage. Fig 3: Successive Approximation ADC Advantages of this ADC arespeed is high compared to counter type ADC.Good ratio of speed to power.Compact design and inexpensive compared to flash type. Disadvantages of successive Approximation ADC Cost is high as compare to counter type ADC because of SAR and complexity in design. Applications of SAR ADC is used widely data acquisition techniques at the sampling rates higher than 10 KHz. IV. INTEGRATING ADC Integrating analog to digital convertersprovide high resolution analog to digital conversions, with good noise rejection. Single-Slope ADC Architecture: The simplest form of an integrating ADC uses single slope architecture (Figures 4a and 4b). Here, an unknown input voltage is integrated and this value is compared against a known reference value. The time it takes for the integrator to trip the comparator is proportional to the unknown voltage. In this case, the known reference voltage must be stable and accurate to guarantee the accuracy of the measurement [5]. One drawback to this approach is that the accuracy is also dependent on the tolerances of the integrator's R and C values. Thus in a production environment, slight differences in each component's value change the conversion result and make measurement repeatability quite difficult to attain. To overcome this sensitivity to the component values, the dual-slope integrating architecture is used. International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190 90 www.ijaert. org Fig 4(a) Single-Slope ADC Architecture, Fig 4(b) Output of integrator Dual-Slope ADC Architecture: A dual-slope ADC integrates an unknown input voltage (Vin) for a fixed amount of time, then de-integratesusing a known reference voltage (Vref) for a variable amount of time. In the dual-slope converter, an integrator circuit is driven positive and negative in alternating cycles to ramp down and then up, rather than being reset to 0 volts at the end of every cycle. In one direction of ramping, the integrator is driven by the positive analog input signal (producing a negative, variable rate of output voltage change, or output slope) for a fixed amount of time, as measured by a counter with a precision frequency clock. In the other direction, with a fixed reference voltage (producing a fixed rate of output voltage change) time is measured by the same counter. The counter stops counting when the integrator’s output reaches the same voltage as it was when it started the fixed-time portion of the cycle. The amount of time it takes for the integrator’s capacitor to discharge back to its original outputvoltage, as measured by the magnitude accrued by the counter, becomes the digital outputof the ADC circuit. Fig 5(a): Dual-Slope ADC Architecture Advantage of this method is that the input signal becomes averaged as it drives the integrator during the fixed-time portion of the cycle. Any changes in the analog signal during that period of time have a cumulative effect on the digital output at the end of that cycle. Other ADC strategies merely capture the analog signal level at a single point in time every cycle. If the analog signal is “noisy” (contains significant levels of spurious voltage spikes/dips), one of the other ADC converter technologies may occasionally convert a spike or dip because it captures the signal repeatedly at a single point in time. A dual-slope ADC, on the other hand, averages together all the spikes and dips within the integration period, thus providing an output with greater noise immunity. These types of converters ofteninclude built-in drivers for LCD or LED displays and are found in many portable instrument applications, including digital panel meters and digital multi-meters. Fig 5(b): Integrating and De-integrating action of Dual slope integrating ADC Initially, switch S1 is on and S2 and S3 are off. Theintegrator will integrate a sample of the input voltage,Vin, for a fixed period of time T1and then, switch S2 is closed. This disintegrates the input voltage to zero and time taken by it to come to zero voltage is proportional to applied input. The disadvantage of this ADC is it is the slowest of all ADCs but very chip and mostly used in DVMs. V. FLASH ADC Flash ADC