High-Voltage GaNon-Silicon HEMT ’ s

M/A-COM Technology Solutions has continued in the joint development efforts sponsored by the Department of Energy with MIT main campus and MIT Lincoln Labs to develop GaN-on-silicon three-terminal high-voltage/highcurrent HEMT switching devices. The first year developmental goals were for a three-terminal structure that has a reverse breakdown characteristic of >1200 volts and is capable of switching 10 amperes of current. An average three-terminal breakdown of 1322 volts was achieved on a single finger 250 μm GaN-on-silicon HEMT device utilizing a source connected field plate with a 4.5 μm drain region overlap. An individual device breakdown on a single finger, 250 μm GaN-on-silicon HEMT device with a SCFP of >1630 volts was measured at a current of 250 μA (1 mA/mm) – One of the highest yet reported for GaN-on-silicon in the industry. Fig. 1 – Details of Three-Terminal HEMT Devices Including Source Connected Field Plate Variants INTRODUCTION The following paper is a summary of the results to date of the developmental efforts at M/A-COM Technology Solutions of a Department of Energy sponsored joint effort in conjunction with MIT Lincoln Labs and the MIT Electrical Engineering and Computer Science Department to realize GaN-on-Silicon three-terminal HEMT devices having reverse breakdown voltages greater than 1200 volts. With respect to three-terminal design structures to produce a GaN-on-silicon HEMT device having a >1200 gate–to– drain breakdown, the main approach focused on “normally on” device designs and was based upon M/A-COM Tech’s standard high frequency test structures. The required high-voltage reverse breakdown was investigated by examining a range of larger source-to-drain spacings, and utilizing source connected field plate, SCFP, structures to spread the peak field in the gate-to-drain region. DISCUSSION A three-terminal test reticule, having single gate devices with 250 mm of gate periphery as well as multi-gate HEMT structures with 10 mm, 20 mm, and 30 mm gate peripheries was designed. The details of the single finger test FETs “Normally ON”, depletion mode, three-terminal devices can best be visualized as shown in Figure 1. The specific dimensions are as summarized as follows: 1 μm gate length; 250 μm gate width; ohmic source and drain contacts; source connected field plate & non-field plate devices; multiple gateto-drain spacings; and a 400 μm probe pad-to-probe pad pitch. The purpose of including multiple gate-to-drain spacings and SCFP overlap dimensions was to study and quantify the effect of these parameters on the overall HEMT breakdown. The purpose of the field plate approach is to reduce the peak field at the drain side edge of the gate and spread the reduced field over the drain region of the HEMT structure. By reducing the peak field, higher voltages can be applied 10 a 293 CS MANTECH Conference, May 13th 16th, 2013, New Orleans, Louisiana, USA before the critical breakdown field strength is reached. The critical design features of this SCFP approach in terms of peak field modification are the overlap of the field plate onto the drain region and the thickness of the intervening dielectric RESULTS Measurements were made on-wafer for high-voltage, threeterminal, reverse breakdown characteristics on the single gate devices with ohmic source and drain contacts, standard nonrecessed gates, and non-field plate devices having multiple GD spacings. In addition, single gate devices also having ohmic SD, standard non-recessed gates devices, and multiple GD spacings, but with source connected field plated devices also having multiple SCFP overlap dimensions were evaluated in this test matrix. All measurements were made on these single finger HEMT devices having a gate width of 250 μm and a gate length of 1.0 μm with the gate pinched-off at a gate bias of -6.0 volts and at a drain current of 250 μA (1.0 mA/mm of gate periphery). Because of difficulties and voltage limitations with the auto tester, all high-voltage data was taken using a curve tracer. Due to the manual nature of the curve tracer measurements, the data was limited to 10 reticules. Fig. 2 – Wafer Map of Breakdown Voltages by Reticule Position In Figure 2, a wafer map showing the range of threeterminal breakdown voltages that was observed on the various single finger FET geometries within each reticule is presented. A number of general characteristics can be seen. The center of the wafer seems to have lowest breakdown. In fact, the reticules with the highest breakdown are toward the edges of the wafer. As expected the devices with larger drain-to-gate spacings have higher reverse breakdowns. The highest individual device breakdown measurement occurred on a SCFP device with an extended source connected field plate drain overlap. In order to make some comparisons between the various device topologies, the low breakdown reticules were excluded and an analysis of the remaining reticules was performed. The graphical results of this analysis are shown in Figure 3 and Figure 4. Fig. 3 – Breakdown Voltage as a Function of GD Spacing with 1.5μm SCFP and No SCFP Figure 3 is a plot of the three-terminal reverse breakdown voltage as a function of gate-to-drain spacing with and without a source connected field plate and having standard ohmic contacts. The design purpose of the source connected field plate is to spread and reduce the peak field at the drain edge of the gate and allow higher voltages to be applied before critical field is reached enabling higher reverse breakdown. As can be seen in Figure 3, as expected, larger gate-todrain spacing results in higher reverse breakdown with a minimum average breakdown voltage of approximately 400 volts at a 5 μm gate-to-drain (GD) spacing and approximately 1200 volts at a 20 μm gate-to-drain (GD) dimension for the HEMT devices without a source connected field plate. This translates to a breakdown field strength in the drain region of 80 volts/μm (8x10 volts/cm) at a 5 μm GD spacing and at a 20 μm GD spacing the field strength begins to saturate but still has a very respectable value of 60 volts/μm (6x10 volts/cm). It is believed that the breakdown limitation for these non-field plated devices is due to the peak field at the drain-side edge of the gate exceeding the 3x10 volts/cm theoretical limit of the AlGaN/GaN active layer structure. Also in Figure 3, is a plot of the identical HEMT structures with the same gate-to-drain spacings but having a source connected field plate with a constant 1.5 μm field plate overlap beyond the gate edge toward the drain contact. It was expected that a significant increase in the breakdown characteristic would have been realized with the addition of the field plate structure to the basic HEMT topology. As can Highest Device