Miracle-dz/UniFAR-FTUs huggingface dataset:
A Coupled Multi-ALU Processing Node for a Highly Parallel Computer

Stephen W. Keckler April 12, 1994 Arti cial Intelligence Laboratory Massachusetts Institute of Technology Cambridge, Massachusetts 02139 skeckler@ai.mit. edu, NE43-619A Many current parallel machines focus upon vector operations or coarse grained tasks. Performance can be improved, however, if tasks are parallelized using a hierarchy of granularities. Large blocks of code can be divided into coarse grained tasks; then each task can be scheduled to take advantage of ne grain instruction level parallelism. Instruction level parallelism techniques enable operations which have neither data nor control dependencies between them to execute simultaneously. Runtime scheduling mechanisms are necessary because some dependencies can not be discovered at compile time. Furthermore, runtime scheduling of multiple threads is especially important for multiprocessor tasks because even though they can exhibit high degrees of instruction level parallelism, they often have serial tail sections during which they consume few processor resources. The coupled architecture is intended to both provide runtime scheduling support and counteract the problem of serial operations within a thread, as it will allow each functional unit to independently associate itself with a thread of its choosing on every cycle. To exploit instruction level parallelism, I propose a multiple functional unit processor that supports several active threads and interleaves them, not only in time, but also in space, based on their runtime processor resource requirements. This architecture will, at one extreme, behave like a Very Long Instruction Word (VLIW) [1, 2, 3] ma1This research is supervised by W.J. Dally and supported in part by a National Defense Science and Engineering Graduate Fellowship, by the Defense Advanced Research Projects Agency under contracts N00014-88K0738 and N00014-87K-0825, and by a National Science Foundation Presidential Young Investigator Award, grant MIP-8657531, with matching funds from General Electric Corporation, IBM Corporation, and AT&T. chine, while at the other perform as a process per element multicomputer. The location of this machine on that spectrum is determined dynamically on a cycle by cycle basis. Figure 1 demonstrates how the instruction streams for thread A and thread B have been scheduled at compile time, and how at runtime the tasks are interleaved to share processor resources. Each column in a thread's instruction stream represents an operation eld for a single functional unit, and each row shows the operations which may be executed simultaneously. The empty boxes indicate that there is not enough instruction level parallelism to occupy all of the functional units.
A new algorithm for electroencephalogram functional brain mapping based on an auditory-comprehension process

OF THE THESIS A NEW ALGORITHM FOR ELECTROENCEPHALOGRAM FUNCTIONAL BRAIN MAPPING BASED ON AN AUDITORY-COMPREHENSION PROCESS by Mercedes Cabrerizo Florida International University, 2003 Miami, Florida Professor Malek Adjouadi, Major Professor The main objective of this thesis is to gain insight on the dynamics of the human brain through electroencephalography (EEG) analysis, with emphasis placed on the characterization of the effects of an Auditory/Comprehension task. A thorough examination of the EEG recordings was accomplished through the use of the most common brain waves (Alpha, Beta, Delta, and Theta). Conceivably, as the EEG recordings based on these tasks become better understood, their use as a helpful tool in mapping the different functions of the brain will become more effective. The EEG data was collected from 15 patients at Miami Children's Hospital using the ESI-256 system. A final evaluation of spectral arrays is performed based on comprehensive color topographic maps of the various induced brain activities. This representation allows us to bring out how different patients react under different circumstances, and to detect consequently neurological disorders such as the Attention Deficit Disorder (ADD).
Rigid Body Dynamics, Inertial Reference Frames, and Graphics Coordinate Systems: A Resolution of Conflicting Conventions and Terminology

The field of rigid body dynamics has a long tradition of study in physics and engineering, and has achieved a high degree of standardization and clarity of exposition. In comparison, computer graphics is a relatively new and rapidly growing field with competing standards and still evolving terminology. The authors believe that there is much to be gained by examining commonalities and differences between these two fields with regard to choice of coordinate systems and methods used for representing rigid body motion. Toward that end, in what follows, the basic ideas of rigid body dynamics are first developed in coordinate-free form. The standard coordinate system used in aircraft and ship dynamics (north, east, down) is then introduced and utilized to derive rigid body dynamics in a form suitable for computation, the “Newton Euler” equations. After this, the coordinate system associated with OpenGL, and other graphics API’s, is compared to the standard dynamics coordinates. Finally, it is shown that it is possible to bring the dynamics and graphics perspectives on representation and display of rigid body motion into harmony through the use of a simple constant inverse homogeneous transformation matrix.
A gate array chip for high frequency DSP applications

A gate array architecture for high speed correlation and convolution is described. A gate array chip based on this architecture is designed and an FIR filter is implemented on this chip. Bit-level array in pipeline structure is used in the architecture. For high I/O data rate, true single phase clocking circuit technique in CMOS is applied. The gate array chip is designed in 1.2 /spl mu/m CMOS with the programming layer metal-2 only. Spice and Verilog simulations show that the throughput is over 100 MHz. <<ETX>>
IP Switching: Protocols and Architectures

From the Publisher: What kind of switch can actually deliver the reduced latency, improved QoS (quality of service), and greater bandwidth demanded by services such as videoconferencing, multicasting, and virtual reality? Which switches meet the needs of your network? And, perhaps most importantly, which will keep up with technology that's always on the move? This book, covering both the firmware and software of IP switching, and written by one of the field's foremost experts, has all the answers. It provides the best overview of the entire arena, giving you everything from a nuts-and-bolts explanation of switching technology to a detailed, all-inclusive analysis of vendor offerings. Network designers, network managers, Internet service providers, and anyone dealing with the technical aspects of fast data flow, all need IP Switching: Protocols and Architectures.
Learning syntactic structure

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Multi-thread IO in high quality digital broadcasting system

To meet the need of performance in high quality digital broadcasting systems (HQDBS), such as high IO width, no frame loss, and seamless switch etc, an algorithm called MPPDIO (multi-thread parallel prefetch Direct IO) is proposed in this paper. The size of the sharing buffer between multi-threads is modeled and calculated. To investigate the validation of the MPPDIO algorithm, the I/O performances are analyzed and compared when adopting a traditional pre-cache sequence algorithm and adopting the MPPDIO algorithm, and a set of comparable experiments is proceeded. Analysis and test results indicate that the traditional pre-cache sequence algorithm can't meet the need of performance, and the MPPDIO algorithm not only can perfectly satisfy the performance requirements but also can improve the utilization of disk I/O channel and reduce the load of CPU. The MPPDIO algorithm can also meet the requirements of digital broadcasting on HDTV (high definition television), which needs the same performance as the HQDBS.
LA LÓGICA EN LAS CIENCIAS COMPUTACIONALES

In this paper it is analyzed the need to include the logic in training processes in Computer Science (CS). It is part of a tour of the history of logic in these sciences, later it's described the relationship and the need to include it in the training processes related, and finally analyzed that, when and how deep it should work training CS. This is a revision to issue state and the importance of including this subject in undergraduate and graduate programs in computer sciences and Information Technologies areas.
RLL-1: A Representation Language Language. Supplement. Details of RLL-1

Abstract : This paper includes many implementation level details about the RLL-1 system, described in a companion paper, RLL-1: A Representation Language Language (Heuristic Programming Project Working Paper HPP-80-9, October 1980, at Stanford University, by Russell Greiner). The contents are as follows: Special Units, Naming conventions, Legend, Actual units, Index of Units, Environment, Top level Functions, Functions needed to Bootstrap RLL-1, Convenience Functions, Advised Functions, and Global Variables.
Children’s and Adolescents’ Processing of Temporary Syntactic Ambiguity: An Eye Movement Study

This study examined the eye movements of 24 children and adolescents as they read sentences containing temporary syntactic ambiguities. Prior research suggested that children primarily use grammatical information when making initial parsing decisions, and they tend to disregard semantic and contextual information. On each trial, participants read a garden path sentence (e.g., While the storm blew the boat sat in the shed), and, afterwards, they answered a comprehension question (e.g., Did the storm blow the boat? ). The design was 2 × 2 (verb type × ambiguity) repeated measures. Verb type was optionally transitive or reflexive, and sentences were ambiguous or unambiguous. Results showed no differences in first pass reading times at the disambiguating verb (e.g., sat). However, regressions did show a significant interaction. The unambiguous-reflexive condition had approximately half the number of regressions, suggesting less processing difficulty in this condition. Developmentally, we found that adolescents had significantly better comprehension, which seemed to be linked to the increased tendency to regress from the disambiguating word. Findings are consistent with the assumption that the processing architecture is more restricted in children compared to adolescents. In addition, results indicated that variance in ambiguity resolution was associated with interference control but not working memory.
OBJTEST: an experimental testing tool for algebraic specifications

Algebraic specifications involve the development of 'axioms' or equations to model the behaviour of systems. The technique is one example of a formal method of specification. By using the equations to drive a process of term-rewriting, test expressions can be evaluated, thus providing an execution facility. Such animation certainly helps in checking typographical and notational errors. However, there is still a need for thorough testing of algebraic specifications to uncover more subtle errors. The author describes in outline, a prototype testing tool for algebraic specifications, OBJTEST, built around the ObjEx system. The two principal facets of the tool are the automatic generation of 'exhaustive' sets of test expressions from a specification, followed by the use of these test expressions in mutation testing of the given specification.
Optimal Designing of Power System Stabilizers Using Differential Evolutionary Algorithm to Omit Inter-area Oscillations

In this paper the values of power system stabilizer converge to optimal response coordinately using differential evolutionary algorithm (DE) with small number of iterations and it is tuned in a way that inter-Area power system oscillations will be omitted. The case study is a three-area system which is simulated non-linearly in time domain using MATLAB software. Simulation results show that without using PSS and during fault occurrence, the damper torque and synchronizer torque are decreased and system become unstable which lead to low frequency oscillations such as Inter-Area ones. These problems have been omitted using optimal and coordinated PSSs'.
Reliable error estimation and mesh adaptation for the finite element method

Recent work in computational structural analysis and design has been greatly aided by the evolution of the finite element method into a powerful tool for the solution of a broad range of problems. This report addresses the following questions: how to calculate, at reasonable cost, reliable estimates of the error of computed finite element solutions; how to set up the overall solution process so as to achieve, with reasonable certainty and efficiency, a solution for which the accuracy either falls into a prescribed range or is best possible for the allotted computational cost. Certain one- and two- dimensional problems are considered first; later, the results are extended to nonlinear problems. Experimental results for a particular nonlinear two-point boundary-value problem show that the combination of continuation, error estimation, and adaptive mesh construction should be an extremely effective approach to the computational solution of many practical engineering problems. 15 figures, 11 tables. (RWR)
RDF : Un modelo de metadatos flexible para las bibliotecas digitales del próximo milenio

This presentation deals with the Resource Description Framework (RDF), a metadata model based on XML that was presented in this conference like a flexible standard for structuring the information of XXI century's Digital Libraries. It describes the context and principal features for this metadata format, as well as its posibilities and potencial development to enhance information retrieval in Internet. Some years after this paper(2004) RDF became a W3C recommendation and it is more and more used to describe digital objects in particular digital libraries or to create particular application profiles.
Layer based area partition using single-sequence for preferable routes

It has been recognized after much devotion for years to the placement in VLSI physical design that a successful placement is attained on the space-plan satisfying 1. Preferable Placement: partitioned clusters be laid out without violating the direction along the signal flow in the cluster and 2. Spacing-Planning: space for routing and space for modules are designed simultaneously on a plane. So far proposed methods such as those based on Slicing-Tree, BSG, SP, O-tree, B-tree, Q-seq, CBL, TCG, etc., are not suitable for the purpose by their definitions. This paper adopts a newly proposed data-structure called Single-sequence (SS) which is first used for the placement or floorplan, and also considered as a coding of a space-plan. Using SS, a strategy to promise the successful space-planning is suggested with convincing experimental results. SS may be considered as an enhancement of the Sequence-Pair but its underlying concept is different.
A neural networks system for traffic congestion forecasting

Advance Traffic Management Systems (ATMS) must not only control current traffic, but also predict where congestion will occur. Predicting congestion so that preventive actions may be taken in advance will greatly alleviate traffic gridlocks. This paper describes the results achieved utilizing a backpropagation neural network algorithm to predict the traffic flow on surface streets in metropolitan areas. The neural network is trained in two phases. First, an initial learning phase determines the most appropriate connecting weights for data on a typical business day. Second, adaptive learning is employed to learn the special case traffic classes and adapt the weights to the present situation. In the adaptive learning phase, the error function is computed by placing a restriction on the weight changes so that the knowledge learned through the initial learning phase is retained. The prototype system is tested through computer simulations, with results indicating that the application of the neural networks to traffic congestion forecasting is promising.
A novel contrast enhancement algorithm in IR imaging systems

The contrast enhancement of infrared image is useful and important to the infrared image system. The current techniques of local enhancing exists either over-enhancing or high complexity problems. In this paper, we propose a novel contrast enhancement algorithm which combines histogram equalization based methods (HEBM) and an improved unsharp masking based methods (UMBM). This proposed algorithm uses HEBM to achieve global contrast enhancement and UMBM to achieve local contrast enhancement. Some elaborate strategies are applied to the algorithm to avoid the overenhancement and magnification of noise when contrast is enhanced. The article is organized as follows. First, we review the techniques developed in the literature for contrast enhancement. After then, we introduce the new algorithm in details. The performance of the proposed method is studied on experimental IR data and compared with those yielded by two well established algorithms. The developed algorithm has good performance in global contrast and local contrast enhancement with noise and artifact suppression.
An overview of circuits and devices research on SOI technology for analog/mixed-signal systems

SOI technology has become the commercial technology of choice for both high performance and low power digital applications. By comparison, analog development in SOI is still in its infancy. To help emphasize analog/mixed-signal opportunities in SOI, both for circuits and new devices, this paper provides a sampling of the SOI research at the University of Tennessee. Circuit highlights include an operational amplifier with automatic offset cancellation, a VCO-based ADC, and body-driven analog circuits. The G/sup 4/-FET, a four-gate transistor in SOI, is introduced. Floating-gate devices on SOI are also presented, including their application to post-process trimmable analog circuits.
Pattern-finding in qualitative data - a suggested method of making data analyzable

I have examined or tutored some 500 bachelor theses and some 100 master theses at several Swedish universities. Over the past 20 years Swedish secondary school graduates has become less and less apt in mathematics, Mullis, I.V. S. et al. (2009). Due to this development university students mostly chose to make qualitative studies, irrespective if this is the best choice to study the research question on not. Most of them don’t even make good qualitative studies.To help them get good qualitative use of their empirical material I have developed the following method. It is suitable for studies based on interviews, focus groups and observations. It is suitable both for deductive and abductive research, well grounded theory, and critical studies. As the dataset grows, the method becomes cumbersome, which I don not consider is a big problem, as big qualitative datasets would preferably be analyzed by non-parametric statistics, rather than the iterative interpreting qualitative method I suggest here.
Application of Genetic Algorithm for Cancer Diagnosis by Feature Selection

The main aim of feature selection is to select a set of input variables by removing features with very little or no analytical information. Feature selection strategies are often decomposed into three broad categories. View of the substantial range of existing feature selection algorithms, the necessity arises to count on criteria which enable to adequately decide in certain situations which algorithm should be used. This work reviews many basic algorithms found within the literature and assesses their performance in a very controlled state of scenario. To solve this kind of problems genetic algorithm approach uses for feature selection and parameters optimization. This work involves brief study and designing a framework that incorporates genetic algorithm with SVM for feature selection and classification on the training dataset. Diagnosis of diseases is very important and difficult task, and this study helps for finding technique that performs feature selection and parameters setting. The objective of this work is to research existing work for feature set and discussed technique for improving classification accuracy.
The Compleat Mozart : a guide to the musical works of Wolfgang Amadeus Mozart

Published to coincide with the 200th anniversary of Mozart's death in 1791, this book is designed to be a guide to the composer's works and is aimed at the music-lover who wishes to read something informative about any particular piece. Although there are many books which deal with the handful of famous operas, symphonies, concertos, or string quartets upon which Mozart's reputation rests, this collection contains in a single volume details about any work composed by Mozart and where, when and why he wrote it, what it is like, and what special significance it may have.
Event Correlated Usage Mapping in an Embedded Linux System - A Data Mining Approach

A software system composed of applications running on embedded devices could be hard to monitor and debug due to the limited possibilities to extract information about the complex process interactions. Logging and monitoring the systems behavior help in getting an insight of the system status. The information gathered can be used for improving the system and helping developers to understand what caused a malfunctioning behavior. This thesis explores the possibility of implementing an Event Sniffer that runs on an embedded Linux device and monitors processes and overall system performance to enable mapping between system usage and load on certain parts of the system. It also examines the use of data mining to process the large amount of data logged by the Event Sniffer and with this find frequent sequential patterns that cause a bug to affect the system’s performance. The final prototype of the Event Sniffer logs process cpu usage, memory usage, process function calls, interprocess communication, system overall performance and other application specific data. To evaluate the data mining of the logged information a bug pattern was planted in the interprocess communication, that caused a false malfunctioning. The data mining analysis of the logged interprocess communication was able to find the planted bug-patterna that caused the false malfunctioning. A search for a memory leak with the help of data mining was also tested by mining function calls from a process. This test found sequential patterns that was unique when the memory increased.