Circuit Design for Memristor based In-Memory Computing

Modern computing systems suffer due to inability of CMOS-device technology and conventional Von-Neumann architectures to support today's ever-increasing demand of high performance, reliability, cost and energy-efficiency. While CMOS device suffers from high static leakage, reduced reliability and manufacturing complexity; conventional computing architecture suffers from high power consumption with memory access and performance bottlenecks. Non-volatile and CMOS-compatible emerging memristive device technology with extremely compact memory structures offers in-memory computing solutions. However, research lacks quantitative benchmarking of memristor-based primitive logic designs. Moreover, the arithmetic and functional circuit design solutions are inefficient and hence incompetent to replace the state-of-the-art.The thesis first covers device level physics of different memristive devices, elaborating their basic structures, working principles and behavioural analyses using Verilog-A models. Building on single device behavioural analyses, a comprehensive exploration and quantitative benchmarking of all existing primitive gates is provided, thereby concluding that scouting logic design technique is the optimal logic gate to perform in-memory computing. Going forward, using scouting logic as the building block, the work presents efficient arithmetic and functional circuit designs that outperform previously proposed in-memory computing solutions and attempts to make a strong case to challenge the current CMOS-based state-of-the-art computing paradigm.Different flavours of a novel circuit design are proposed to tackle limitations common to circuits implementing primitive arithmetic operations and complex multiply-accumulate (dot-product) operations supporting data-intensive applications. The proposed circuit deploys in-built sample-and-hold and two bit-wise weighting techniques to enable pipelining and self-timing-path to improve accuracy against variations. As compared to 4-bit adder utilising integrate and fire circuit (IFC) that is optimised for area/power, the proposed design improves the speed, area, and energy consumption by 4X, 2.5X, and 11X, respectively. Incorporating additional components such as high-gain differential amplifier and modified IFC provides a highly accurate, linear, power efficient dot product engine with significant improvement in memristor endurance. To perform 64_4 dot 64_1, the proposed dot product engine improves the speed, area and energy consumption by 2X, 3.5X and 54X, respectively, as compared to area-efficient IFC-based engine, while also extending the range of operands operated in parallel by g3X. Compared to highly accurate SAR-ADC(current sense amplifier) based dot product engine, the proposed design improves the speed, area and energy by a factor of 0.4X(1.2X), 200X(6X) and 260X(108X), respectively, with comparable accuracy. Read endurance is significantly improved as l 0.1V is maintained across the memristors during the dot-product operation, as opposed to g 1V endured using prior proposed designs. To showcase the scalability and versatility of the proposed circuit designs, design prepositions of multi-operand 4-bit adder, 4x4 multiplier and 4-bit comparator are also presented. Supporting equations, graphs, figures and tables have been included to justify the choices made as part of this work and to enhance the understanding of novel non-volatile memristor based in-memory computing.