Fault-tolerant architectures for nanoelectronic and quantum devices

The progress in CMOS technology has entered the sub-micron realm, and the technology will approach its limits within about 15 years. Already various novel information processing devices, based on quantum mechanical effects at the nanometer scale, have been widely investigated and some have been successfully demonstrated at the circuit level. This advance in nanoelectronic devices has also motivated efforts in the research of nanoelectronic and quantum computer architectures. Due to the components' poor reliabilities, these architectures will have to be robust against device and interconnect failures. In order to avoid power dissipation problems, the components will have to be applied in the quantum mechanical domain, while due to potential problems in interconnects, the components should be locally interconnected only. This dissertation is devoted to pursuing solutions to architectural issues that come up when designing a nanoelectronic computer. It explores the possibility of building viable and reliable computer systems from novel nanoelectronic and quantum devices. In particular, parallel processor architectures that are fault-tolerant and locally-coupled have been researched. Chapter 1 presents an introduction to the issues that play a role in nanoelectronics, in contrast with microelectronics, and discusses implications for nanocomputer architectures. A brief review of the current status in nanoelectronics and recent progress in nanoarchitecture research is presented in Chapter 2. Chapter 3 describes research on fault-tolerant architectures. We review von Neumann's NAND multiplexing technique and extended his study from a high degree of redundancy to a fairly low degree of redundancy. We show the stochastic Markovian nature of a multi-stage multiplexing system and work out its characteristics. We develop a system architecture based on the NAND multiplexing structure that copes with the problem of random background charges in single electron tunneling (SET) circuits. Our study shows that, although a rather large amount of redundant components is required, an architecture based on the multiplexing technique could be a fault-tolerant system solution for the integration of unreliable nanoelectronic devices affected by dominant transient errors. In addition, in Chapter 4, a defect- and fault-tolerant architecture is proposed, that uses the multiplexing technique for its fundamental circuits and a hierarchical reconfigurability in the overall system. It is shown that the required redundancy could be brought back to a moderate level by adding reconfigurability to the system concept. This architecture is robust in an efficient way against both manufacturing defects and transient faults, and tolerates a gate error rate of up to 10 which, for any current microelectronic system, would be unacceptable. Derived from von Neumann's multiplexing technique, we propose triplicated interwoven redundancy (TIR), as a generalization of triple modular redundancy (TMR), but then with random interconnections. A prototype processor architecture and its simulation-based reliability model have been set-up and are used to evaluate the fault-tolerance. The processor is, by way of comparison, implemented using both TIR as well as so-called quadded logic. In general, the reliability of a TIR circuit is comparable with that of an equivalent TMR circuit while, for certain interconnect patterns, the TIR structure may present an inferior performance to TMR, due to its interwoven nature in gate interconnections. TIR can be extended to higher orders, which we label N-tuple interwoven redundancy (NIR). The use of 5-tuple interwoven redundancy leads to an economical redundancy factor of less than 10 for the reconfigurable system architecture. It has been shown that the design and implementation of restorative devices (voters) are important for TIR/NIR and quadded structures. Only with a simple voter design is it possible to obtain -with a higher order of NIR- a better system reliability than with TIR. TIR or NIR is in particular suitable for implementation in molecular nanocomputers, which are likely to be fabricated by a manufacturing process of stochastic chemical assembly. In Chapter 5, superconducting circuits of Josephson junctions have been investigated with as aim to possibly use them in locally-connected processor structures. Both a classical SIMD computer architecture and an array-based quantum computer structure are presented that use the same basic circuit, the Josephson junctions. Our ideal is that the classical computer can serve as a pre-, post- and intermediate processor for the quantum computation that is performed in the heart of the Josephson circuit array. As such, it then establishes a heterogeneous quantum/classical computer for implementations of algorithms such as Shor's factoring algorithm which mixes classical computation steps with quantum computation steps in a single algorithm. Although not specifically worked out and discussed in this study in detail, an architecture in the form of an all-reversible computing network based on superconducting circuits of Josephson junctions, could in principle be used for this. A quantum CNN (cellular nonlinear networks) architecture using the Josephson circuits has also been proposed, presenting a novel computing paradigm for Josephson circuits. Since classical computing architectures (SIMD arrays), quantum computing architectures and semi-quantum computing architectures (quantum CNNs) can be simultaneously studied on the same device, the Josephson circuit is a good vehicle for investigating the architectural issues of quantum and nanoelectronic computer systems, independently from the question of which device will be the ultimate implementation vehicle. This last chapter concludes this dissertation, which can be placed in the "early days" of research on architectures of nanoelectronic and quantum computers. And beyond this thesis: The scientific papers that form the foundation of the chapters in this thesis have meanwhile been followed up by many new studies in fault-tolerant techniques such as using Monte Carlo simulations, bifurcation theory and an exact analysis using combinatorial arguments to investigate the error behavior in a multiplexed nanosystem of Markov chains. Moreover, a probabilistic-based methodology has been proposed for designing nanocomputer architectures based on Markov Random Fields (MRF), and CAD tools are being developed to automate the evaluation of various fault-tolerant schemes and their reliability/redundancy trade-offs. The redundancy techniques, originating from von Neumann, are basically error-correcting codes (ECC). The multiplexing construction boils down to the use of a repetition code, in which each symbol of a message is repeated many times to create redundancy. The use of error-correcting codes, as well as the issue of fault-tolerance in nanocomputing in general, awaits further investigation. Novel computing systems, envisioned now as adaptive systems based on molecular electronics, biology-inspired self-learning and -evolving systems, nonlinear dynamical systems and quantum computers, may in the long term emerge, possibly leading to new types of algorithms and architectures. The choice of algorithms and architectures must aim towards applications in nanotechnology. An architecture will strongly influence the design of devices and circuits, and vice versa: the opportunities and problems found in nanoelectronic devices and circuits will strongly influence the choice of an architecture. In research on nanocomputer architectures, therefore, an interdisciplinary approach must be followed and the success will eventually rely upon a multidisciplinary effort in the fields of chemistry, physics, electrical engineering, computer science, and, perhaps, many others.