Miracle-dz/UniFAR-FTUs huggingface dataset:
Mobility Improves the Security of Location Awareness in Wireless Networks

Mobility has become an integral feature of many wireless networks. Along with this mobility comes the need for location awareness. A prime example for this development are today’s and future transportation systems. They increasingly rely on wireless communications to exchange location and velocity information for a multitude of functions and applications. At the same time, the technological progress facilitates the widespread availability of sophisticated radio technology such as software-defined radios. The result is a variety of new attack vectors threatening the integrity of location information in mobile networks. Although such attacks can have severe consequences in safety-critical environments such as transportation, the combination of mobility and integrity of spatial information has not received much attention in security research in the past. In this thesis we aim to fill this gap by providing adequate methods to protect the integrity of location and velocity information in the presence of mobility. Based on physical effects of mobility on wireless communications, we develop new methods to securely verify locations, sequences of locations, and velocity information provided by untrusted nodes. The results of our analyses show that mobility can in fact be exploited to provide robust security at low cost. To further investigate the applicability of our schemes to real-world transportation systems, we have built the OpenSky Network, a sensor network which collects air traffic control communication data for scientific applications. The network uses crowdsourcing and has already achieved coverage in most parts of the world with more than 1000 sensors. Based on the data provided by the network and measurements with commercial off-the-shelf hardware, we demonstrate the technical feasibility and security of our schemes in the air traffic scenario. Moreover, the experience and data provided by the OpenSky Network allows us to investigate the challenges for our schemes in the real-world air traffic communication environment. We show that our verification methods match all requirements to help secure the next generation air traffic system.
Charge Balance Control for Improving the Load Transient Response on Dynamic Voltage Scaling(DVS) Buck Converter

In this paper, two programmable voltage-detect charge balance controls (CBC) are implemented on a buck converter. The proposed CBC simultaneously optimizes both load transient and dynamic voltage scaling (DVS) to minimize output voltage spikes and settling time. Firstly, this paper introduces a computational method that is equipped with high resolution analog-to-digital (ADC) converter to achieve better CBC performance. Secondly, an auto-tuning mechanism is introduced to achieve the same performance but with less cost for the circuit. The proposed computational CBC and auto-tuning CBC were tested on the MATLAB Simulink/ Modelsim co-simulation platform to verify the effectiveness of transient response. Simulation results show that the output voltage (Vout) spontaneously follows the DVS function at various Vout levels (from 0.9V to 1.2V) with very fast transient response.
Universal Language Model Fine-Tuning with Subword Tokenization for Polish

Universal Language Model for Fine-tuning [arXiv:1801.06146] (ULMFiT) is one of the first NLP methods for efficient inductive transfer learning. Unsupervised pretraining results in improvements on many NLP tasks for English. In this paper, we describe a new method that uses subword tokenization to adapt ULMFiT to languages with high inflection. Our approach results in a new state-of-the-art for the Polish language, taking first place in Task 3 of PolEval'18. After further training, our final model outperformed the second best model by 35%. We have open-sourced our pretrained models and code.
A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning

This paper presents a dual-loop digital low-dropout regulator (DLDO) with asynchronous-flash (AF) binary coarse tuning for fast transient response. In steady state, the DLDO operates with a unary-weighted low power fine-tune loop to improve the regulation accuracy. Besides, a freeze mode is also employed to further reduce the power budget and to eliminate the limit cycle oscillation phenomenon. When a load-transient is detected, the proposed AF bidirectional shift register will direct the binary-weighted power switches for coarse and fast tuning. The prototype is fabricated in a 28nm bulk CMOS process. With Vin=0.5V and 50mV dropout, the AF-DLDO can deliver 33mA output current and consume only 10. 5μA quiescent current. We measured 102mV voltage undershoot for a 30mA/20ns load step, showing a 0.11ps FOM.
Morbidly obese with severe ARDS: ECMO or no ECMO?

Background: Obesity, defined according to body mass index (BMI > 30 kg/m2), is an increasing problem in the world's population. The proportion of extremely obese patients (BMI > 40 kg/m2) in intensive care units varies between 2.8 and 6.8%. 1 A BMI higher than 40 kg/m2 seems to be associated with an increased risk of developing acute respiratory distress syndrome (ARDS) along with greater morbidity, length of stay, and duration of mechanical ventilation in the intensive care unit (ICU). 2 The use of veno-venous extracorporeal membrane oxygenation (ECMO) has reemerged as an option for acute respiratory distress syndrome (ARDS) refractory to conventional support.3 In addition to cannulation difficulty, morbid obesity can pose a significant challenge to obtaining sufficient circuit flow, indexed to either weight or body surface area (BSA), required to sustain lung rest and recovery.4 Owing to this hypothetical obstacle, there remains significant hesitancy in many centers to offer ECMO support to this patient population. However, Zachary N and his colleague in 2015 proved the efficacy of veno-venous ECMO in this patient population.5Methods: In King Fahd Jeddah ECMO center, Patients requiring ECMO for ARDS between April 2014 and May 2016 were reviewed retrospectively with institutional review board approval. Demographics, ECMO variables, and outcomes were assessed. Obesity, morbid obesity, and super obesity were defined as a body mass index (BMI) greater than 30 kg/m2, greater than 40 kg/m2, and greater than 50 kg/m2, respectively. Results: Forty-nine patients (36M/13F) with ARDS were placed on ECMO during the study period. Fifteen were obese with a BMI of 32.7 kg/m2 (interquartile range [IQR]: 31.6–34.9 kg/m2). Four were morbidly obese with a BMI of 46 kg/m2 (IQR: 43.5–48.5 kg/m2). Nine were super morbidly obese with a BMI of 59 kg/m2 (IQR: 54.5–69.5 kg/m2). Pre-ECMO mechanical ventilator support and indices of disease severity were similar between the three groups, as were the cannulation strategy and the duration of ECMO support. The 90-day survival rate was 71% (20/28) in patients with a BMI more than 30 kg/m2 compared with 42% (9/21) in the non-obese group. Subgroup analysis showed improved survival in morbidly obese patients as 75% (3/4), and super morbidly obese patients as 88.8% (8/9). There were four bleeding complications, two in each morbidly and super morbidly obese group. Conclusions: ECMO in obese patients is feasible and life-saving. Therefore, a percutaneous cannulation remains feasible. The goals of the ECMO therapy include early spontaneous breathing, tracheotomy, rapid reduction of sedation, and adequate analgesia.
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling

The paper proposes a novel practical replacement of conventional high-speed clock-gates for wide voltage scaling. The proposed clock-gate enhances the energy-delay-product by 43% and improves the low-voltage operation by 50 mV reducing the sampling window by 31% as compared with a conventional high-speed pulse-base clock-gate. The comparison also indicates 50% speed improvement resulting in up to 60% EDP reduction as compared with conventional low-power clock-gates. A test chip was fabricated using a 14 nm CMOS FinFET process with five representative process corners, SS, TT, FF, SF and FS, and measured under three temperature conditions, −25°C, 25°C and 100°C, for production-level silicon verification.
A Capacitor-less LDO With Fast-transient Error Amplifier and Push-pull Differentiator

This paper presents a fully-integrated and fast-transient capacitor-less low-dropout regulator (LDO) with high loop gain and bandwidth in full load range for SoC application. It utilizes a combination of a signal- and transient-current boosting (STCB) error amplifier (EA) with transient enhancement circuit (TEC) and a push-pull differentiator to drive gate capacitance of the power transistor. The STCB-based EA with TEC ensures fast response of the regulator and the differentiator is also adopted to enhance the loop stability while improving transient response simultaneously. Moreover, adaptive biasing is implemented in the circuit to compensate decrease of loop gain and bandwidth at heavy load. The proposed LDO is fabricated in a 0. 5μm CMOS process and occupies an active chip area of 0.077mm2. Simulation results demonstrate that it can deliver 100mA load current at 100mV dropout voltage. The voltage spike at the output, undergoing a maximum load current change, is controlled below 300mV and good line/load regulation is achieved at the same time.
A Generic Foreground Calibration Algorithm For ADCs with Nonlinear Impairments

This paper presents a generic foreground calibration algorithm which compensates for memoryless nonlinear impairments in pipeline, SAR or hybrid ADC architectures. Amplifier nonlinearity, comparator offsets, capacitance mismatch and settling time errors are considered. During the calibration process, each element of a look up table is computed by mapping each raw ADC output value to an estimate of the corresponding input, and the most likely input corresponding to each raw ADC output is computed and stored in the table; this table is then used during normal operation to map the raw values to the calibrated ADC outputs. Complexity reduction techniques are presented to facilitate an in-circuit hardware implementation in order to reduce foreground calibration time. The algorithm's performance is evaluated using a SAR ADC model suffering from various nonlinear impairments. Results are presented for settling time errors, capacitor mismatch scenarios, and a wide range of nonlinear amplifier parameters, demonstrating a significant performance improvement in all cases.
Fast-Startup High-Efficiency Tripler Charge Pump in Standard 0.18-μm CMOS Technology

A new tripler charge pump with switch bootstrapping technique is presented. The circuit is fully integrated in a standard 0.18-μm CMOS process and operates with a 1.8-V supply. Analysis and measurement results demonstrate a faster startup transient than the conventional design and, at the same time, a lower energy consumption when charging a capacitive load. In static conditions, driving capability and conversion efficiency are improved as well.
A Near-Zero-Power Temperature Sensor with ±0.24 °C Inaccuracy Using Only Standard CMOS Transistors for IoT Applications

We propose a near-zero-power temperature sensor only by using standard CMOS transistors without any resistor and special device or process. A pair of temperature sensing elements by employing the normal CMOS transistors is adopted to generate the proportional-to-absolute temperature (PTAT) and constant with temperature (CWT) sensing voltages. Then the two sensing voltages are converted to two reference current sources by using the proposed ultra-low-power voltage-to-current (VI) converter. The VI converter converts the linear voltage signal to an exponential current source with a constant exponent coefficient by using CMOS transistors instead of the conventional resistors. As a result, both power loss and chip area are saved. The whole temperature sensor is designed in standard 0.18 pm CMOS process with active area of only 0.017 mm2. The supply voltage is 600 mV. After 1-point calibration, an accuracy of ±0.24 °C is achieved across the temperature range of 0 °C − 80 °C. The power consumption is only 22 pW for the sensing element, 25 pW for VI converter and 80 pW for total at room temperature (27 °C). The good performance and ultra-small facility of the temperature sensor shows its good practicality for Internet-of-Thing (IoT) applications.
Variables to Be Monitored via Biomedical Sensors for Complete Type 1 Diabetes Mellitus Management: An Extension of the “On-Board” Concept

Type 1 diabetes mellitus (DM1) is a growing disease, and a deep understanding of the patient is required to prescribe the most appropriate treatment, adjusted to the patient's habits and characteristics. Before now, knowledge regarding each patient has been incomplete, discontinuous, and partial. However, the recent development of continuous glucose monitoring (CGM) and new biomedical sensors/gadgets, based on automatic continuous monitoring, offers a new perspective on DM1 management, since these innovative devices allow the collection of 24-hour biomedical data in addition to blood glucose levels. With this, it is possible to deeply characterize a diabetic person, offering a better understanding of his or her illness evolution, and, going further, develop new strategies to manage DM1. This new and global monitoring makes it possible to extend the “on-board” concept to other features. This well-known approach to the processing of variable “insulin” describes some inertias and aggregated/remaining effects. In this work, such analysis is carried out along with a thorough study of the significant variables to be taken into account/monitored—and how to arrange them—for a deep characterization of diabetic patients. Lastly, we present a case study evaluating the experience of the continuous and comprehensive monitoring of a diabetic patient, concluding that the huge potential of this new perspective could provide an acute insight into the patient's status and extract the maximum amount of knowledge, thus improving the DM1 management system in order to be fully functional.
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation, yet, its dynamic nature leads to limited retention time that requires periodic, power-hungry refresh cycles. However, the emerging approximate computing paradigm utilizes the inherent error resilience of some applications to tolerate data errors. Such error tolerance can be exploited by reducing the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption, at the cost of an increase in cell failure probability. In this demonstration, we present the first fabricated and fully functional GC-eDRAM in a 28 nm bulk CMOS technology. The array, which is based on a novel mixed-VT 4T bitcell, can be used in both traditional and for approximate computing applications, featuring a small silicon footprint and supporting high-performance operation. Silicon measurements demonstrate successful operation at 800 Mhz under a 900 mV supply, while retaining almost 30% lower area than a single-ported 6T SRAM in the same technology.
Rooting Phylogenies and the Tree of Life While Minimizing Ad Hoc and Auxiliary Assumptions

Phylogenetic methods unearth evolutionary history when supported by three starting points of reason: (1) the continuity axiom begs the existence of a “model” of evolutionary change, (2) the singularity axiom defines the historical ground plan (phylogeny) in which biological entities (taxa) evolve, and (3) the memory axiom demands identification of biological attributes (characters) with historical information. Axiom consequences are interlinked, making the retrodiction enterprise an endeavor of reciprocal fulfillment. In particular, establishing direction of evolutionary change (character polarization) roots phylogenies and enables testing the existence of historical memory (homology). Unfortunately, rooting phylogenies, especially the “tree of life,” generally follow narratives instead of integrating empirical and theoretical knowledge of retrodictive exploration. This stems mostly from a focus on molecular sequence analysis and uncertainties about rooting methods. Here, we review available rooting criteria, highlighting the need to minimize both ad hoc and auxiliary assumptions, especially argumentative ad hocness. We show that while the outgroup comparison method has been widely adopted, the generality criterion of nesting and additive phylogenetic change embodied in Weston rule offers the most powerful rooting approach. We also propose a change of focus, from phylogenies that describe the evolution of biological systems to those that describe the evolution of parts of those systems. This weakens violation of character independence, helps formalize the generality criterion of rooting, and provides new ways to study the problem of evolution.
A 27.2GHz bipolar LC-VCO using class-C biasing to maximize achievable Fosc in 130nm BiCMOS

A BJT based cross-coupled pair limits the maximum achievable oscillation frequency of LC-VCOs due to high parasitic capacitance in mature Si/SiGe technologies. In this work, class-C biasing is exploited to reduce cross-coupled pair parasitics, helping to enhance oscillation frequency without compromising phase noise performance. A design methodology is suggested to optimize cross-coupled pair parasitics with better phase noise performance. A dual-core architecture helps to achieve further phase noise improvement. The VCO is designed and fabricated in a 130nm BiCMOS technology using a bipolar cross-coupled pair. It achieves a maximum oscillation frequency of 27.2GHz and exhibits a measured phase noise performance of −110.7dBc/Hz @ 1MHz offset from the carrier, with an FoM of 181dBc/Hz.
Effective extractive summarization using frequency-filtered entity relationship graphs

Word frequency-based methods for extractive summarization are easy to implement and yield reasonable results across languages. However, they have significant limitations - they ignore the role of context, they offer uneven coverage of topics in a document, and sometimes are disjointed and hard to read. We use a simple premise from linguistic typology - that English sentences are complete descriptors of potential interactions between entities, usually in the order subject-verb-object - to address a subset of these difficulties. We have developed a hybrid model of extractive summarization that combines word-frequency based keyword identification with information from automatically generated entity relationship graphs to select sentences for summaries. Comparative evaluation with word-frequency and topic word-based methods shows that the proposed method is competitive by conventional ROUGE standards, and yields moderately more informative summaries on average, as assessed by a large panel (N=94) of human raters.
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC

A split-based background calibration technique for pipelined-ADC is proposed in this brief to handle both capacitors' mismatches and non-linearity of residue amplifiers in multiple pipeline stages. Some concepts and approaches of machine learning, say multilayer perceptron and backpropagation algorithm, are introduced to deal with the problems appearing in modeling and solving the nonlinear calibration filter. Computer simulations demonstrate an exaltation of both SNDR and SFDR for more than 50dB in a 15-bit 7-stages pipelined-ADC with non-ideal first three stages.
Characterization and Attenuation of Streptozotocin-Induced Diabetic Organ Damage by Polysaccharides from Spent Mushroom Substrate (Pleurotus eryngii)

The aim of this work was to characterize spent mushroom substrate polysaccharides (MSP) from Pleurotus eryngii and their antioxidant and organ protective effects in streptozotocin- (STZ-) induced diabetic mice. The enzymatic-, acidic-, and alkalic- (En-, Ac-, and Al-) MSP were extracted from P. eryngii with snailase (4%), hydrochloric acid (1 mol/l), and sodium hydroxide (1 mol/l), respectively. The characterizations were evaluated by spectral analysis. In animal experiments, the enzymatic activities, lipid peroxide contents, and serum lipid parameters were measured, and histological observations of the liver, kidney, pancreas, and heart were conducted. The results demonstrated that treatment with En-, Ac-, and Al-MSP increased the organ enzymatic activities, decreased the organ lipid peroxide contents, mitigated the serum biochemistry values, and ameliorated the histopathology of diabetic mice, indicating that En-, Ac-, and Al-MSP could potentially be used as functional foods for the prevention of diabetes.
Background Subtraction using Compressed Low-resolution Images

Image processing and recognition are an important part of the modern society, with applications in fields such as advanced artificial intelligence, smart assistants, and security surveillance. The essential first step involved in almost all the visual tasks is background subtraction with a static camera. Ensuring that this critical step is performed in the most efficient manner would therefore improve all aspects related to objects recognition and tracking, behavior comprehension, etc. Although background subtraction method has been applied for many years, its application suffers from real-time requirement. In this letter, we present a novel approach in implementing the background subtraction. The proposed method uses compressed, low-resolution grayscale image for the background subtraction. These low-resolution grayscale images were found to preserve the salient information very well. To verify the feasibility of our methodology, two prevalent methods, ViBe and GMM, are used in the experiment. The results of the proposed methodology confirm the effectiveness of our approach.
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique

A novel low-power and wide-locking-range divide-by-three injection-locked frequency divider with single inductor is presented in this paper. The classical topology with divide-by-two locking scheme is improved via the introduction of an extra tail-injection driven by the central node of the floating-source direct injector. This new concept is applied to the design of a 15GHz divider-by-three in a standard 65-nm LP CMOS technology, which reaches, in post-layout simulations at 100° C temperature, a 23.6% locking range at an input power of 0dBm and DC power consumption of 1.56mW. The divider figure of merit together with the compact size of only 0.09mm2 are best in class for injection-locking dividers with single inductor and same input power. The figure of merit is also very close to the values reached by the best injection-locking dividers-by-three, that, however, use more inductors.
Accurate Prediction of Resonant Converters' ZVS Behavior in the Time Domain

Based on the needs for high power densities and ultra-high efficiencies, the popularity of resonant converters has never been as high before. However, by pushing the upper limit of switching frequency to higher levels, their beneficial soft-switching ability is massively endangered. Although circuit designers are aware of this fact, serious ZVS investigations including the nonlinear output capacitances of the input switches are often missing due to the time-consuming simulations of their switching transients. This paper proposes two calculation methods allowing fast but also accurate predictions of the ZVS behavior without the need for complex and exhausting time domain simulations.