A 4kb memory array for MRAM development

The circuits for a A 4kb array of Magnetic Tunnel Junctions (MTJs) have been designed and fabricated in a 0. 18μm CMOS process with three levels of metal. Support circuitry for addressing, reading, writing, and test mode probing enables the characterization of the switching of a thin-film ferromagnetic layer in the MTJs. Specifically, novel mechanisms involving spin-transfer or thermal assistance can be studied and compared to current MRAM designs that switch the MTJ with current-induced magnetic fields. Using this array design, both high speed digital and quasi-static dI/dV experiments can be conducted to investigate the nature of the MTJ resistance hysteresis and process variation in addition to the switching behavior under both polarities of current. Thesis Supervisor: John K. DeBrosse Title: Senior Technical Staff Member, IBM Thesis Supervisor: Anantha P. Chandrakasan Title: Professor of Electrical Engineering Acknowledgements At the heart of the semiconductor industry is semiconductor memories, and at the heart of semiconductor memories is IBM. The kind of project I have had the fortune to undertake could only have come to fruition under the auspices of IBM memory development. First, I would like to thank Andy Anderson for taking the risk to hire me in 2004. I am also grateful to my manager John Gabric for compelling me to meet his high expectations and return every year since my first assignment. I suspect that only later in my professional career will I fully appreciate how lucky I was to have him as my first “boss. ” I also appreciate the support from Bill Gallagher at IBM research for his role in conceiving a challenging, risky project for me and providing the guidance at critical junctures of this work that made it succeed as a thesis. The MRAM processing technology involved in this project is based on the comprehensive body of knowledge and expertise cultivated by the MRAM team at IBM research. In particular, Solomon Assefa has played a central role in developing the process for fabricating the experimental magnetic tunnel junctions for which this 4kb array was intended. Furthermore, Jonathan Sun has been forthcoming in discussing his research on spin transfer effects in nanomagnets in addition to introducing me to the rich field of magnetism and magnetic materials. Janusz Nowak has also helped in characterization measurements on magnetic tunnel junctions that have guided my experiments. For the circuit design, which is more immediate to the contributions of this thesis, I would like to thank Tom Maffitt for sharing his insight obtained over years of experience in DRAM and, more recently, MRAM design. I also appreciate Mark Jacunski’s willingness and ability to teach me about memory circuit design, particularly for his methodical approach to integrated circuits and for taking time from his demanding responsibilities in embedded DRAM design. I would also like to thank Mark Lamorey for his extensive work on mask-related processing issues; he ultimately ensured that my design data got appropriately translated to physical masks for fabrication. I am grateful to Mark Wood for not only his assistance in the layout of this project but for taking me through the elements of laying out a complex chip design with 10 to 10 transistors, drawing upon principles of hierarchy, robust wiring, techniques for tight pitch circuits, and device matching for analog circuits. His personality made the weeks of sitting with him in front of the layout software tools much more enjoyable than they should have been. This project also received significant contributions from Kim Maloney in laying out several circuit blocks of the 4kb Array. For the formidable task of wafer-level test on a memory array with over 40 signals— several of which require timing control on a time scale of 10ns—I cannot emphasize enough the vital role of John Parenteau and the memory tester which he helped develop over the course of twenty years. His test environment enabled me to exercise the array in several different ways, many of which were unanticipated during the design phase. In fact, the memory tester functioned as almost an extension of the integrated hardware on the wafer— in my incremental approach to extracting functionality from experimental, uncontrolled, and less-understood magnetic memory elements. I would also like to thank Alan Yaeger for helping me with testing. His problem solving skills and fearless attitude in the face of new and unexpected challenges with electrical equipment helped me overcome severe obstacles to the data gathering phase of this project. Finally, my mentor John DeBrosse has been involved in each step of this project, keeping me on a path—for over one and a half years—that ultimately resulted in viable integrated hardware. In working with him, I have experienced a form of teamwork beyond the mere partitioning of responsibilities; his feedback and ideas shaped my inchoate thoughts into a design for a 4kb memory array and exposed me to work in MRAM and DRAM beyond the scope of my project. Because of his experience in the multifaceted elements of memory development and ability to articulate his thought process, he has made work in MRAM circuit design challenging, exciting, and rewarding. In the course of my career, I hope to acquire such elements of technical leadership. It is self-evident from the nature of the work described in this thesis how dependent it was upon these people. Remarkably, they made their contributions to my thesis in parallel to fulfilling their own work obligations. May this project ultimately reflect an additional capacity of theirs to advance memory technologies. Masood Qazi Cambridge, MA