Miracle-dz/UniFAR-FTUs huggingface dataset:
HAKD: Hardware Aware Knowledge Distillation

Despite recent developments, deploying deep neural networks on resource constrained general purpose hardware remains a significant challenge. There has been much work in developing methods for reshaping neural networks, usually with a focus on minimising total parameter count. These methods are typically developed in a hardware-agnostic manner and do not exploit hardware behaviour. In this paper we propose a new approach, Hardware Aware Knowledge Distillation (HAKD) which uses empirical observations of hardware behaviour to design efficient student networks which are then trained with knowledge distillation. This allows the trade-off between accuracy and performance to be managed explicitly. We have applied this approach across three platforms and evaluated it on two networks, MobileNet and DenseNet, on CIFAR-10. We show that HAKD outperforms Deep Compression and Fisher pruning in terms of size, accuracy and performance.
A Wide-Range Highly Power Efficient RF-to-DC Rectifier for RF Energy Harvesting Systems

In this paper, a wide input range, 4-stage threshold voltage compensated RF-DC power converter is introduced. A novel threshold voltage compensation scheme is proposed that can be applied to a rectifier chain with a relatively low number of stages. This proposed structure is shown to provide a high power conversion efficiency (PCE) over a wide input power range that increases the coverage area of wireless powering. Designed and simulated in IBM 130-nm CMOS technology, the proposed 915-MHz rectifier exhibits a PCE of above 20% over the 20-dB input power range while driving a load resistor. For the same load, utilizing a minimal number of compensated rectifier stages, the proposed circuit exhibits a record maximum PCE of 52% at −10 dBm for single-ended Dickson-based CMOS rectifiers. The proposed circuit demonstrates a −22.3 dBm sensitivity for 1 V output across a 1-Mfi resistive load.
Mismatch Compensation Technique for Inverter-Based CMOS Circuits

Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using model: from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy and area, and compared against the geometry scaling approach.
Letters: Unmoved but not Unchanged

should be considered jointly when examining strategy development in ecologically valid contexts. The comprehensiveness of the research represented in these volumes should be applauded. However, there is one thing missing from the research as discussed in these volumes, and that is a consideration of aptitude. Two lessons can be learned from aptitude-treatment interaction research. First, interacts are difficult to replicate (Cronbach & Snow, 1977). With this search for real-world validity, and an ever-increasing interactional model, will we ever be able to replicate an experimental result? Second, aptitude research has taught us that studying complex interactions results in a wealth of diagnostic information about why and when stratgegy shifts occur for particular aptitude groups on specific tests (Kyllonen, Lohman, & Snow, 1984). This information is useful to cognitive strategy researchers who want to develop models of strategy transitions. These books under review suggest that progress has been made in understanding cognitive strategies, but there are still many side streets to be explored before we are comfortable with the research route we have selected. These side streets may have serious implications for our current accounts of cognitive processing. If complex interactions of the sort reported here are necessary to have a valid model of the learner for specific forms of instruction, are the current accounts of cognitive processing valid? Reality testing in the area of cognitive strategy research may lead to revisions in our current models of cognition.
Integration of Double Barrier Memristor Die with Neuron ASIC for Neuromorphic Hardware Learning

This paper details the design of an integrate & fire (I & F) neuron ASIC and its integration with a double barrier memristor device. The memristor has a non-volatile analog memory characteristic which changes with time and voltage. The neuron ASIC is designed to interact with the memristor by integrating its current and firing when a certain threshold is reached. The resulting spikes increase the memristor's conductance and consequently the firing rate of neuron increases. Together, the ASIC and the memristor mimics neuromorphic learning on hardware. The ASIC has been fabricated in AMS 350nm process.
CURIOUS: Intrinsically Motivated Multi-Task, Multi-Goal Reinforcement Learning

In open-ended and changing environments, agents face a wide range of potential tasks that may or may not come with associated reward functions. Such autonomous learning agents must be able to generate their own tasks through a process of intrinsically motivated exploration, some of which might prove easy, others impossible. For this reason, they should be able to actively select which task to practice at any given moment, to maximize their overall mastery on the set of learnable tasks. This paper proposes CURIOUS, an extension of Universal Value Function Approximators that enables intrinsically motivated agents to learn to achieve both multiple tasks and multiple goals within a unique policy, leveraging hindsight learning. Agents focus on achievable tasks first, using an automated curriculum learning mechanism that biases their attention towards tasks maximizing the absolute learning progress. This mechanism provides robustness to catastrophic forgetting (by refocusing on tasks where performance decreases) and distracting tasks (by avoiding tasks with no absolute learning progress). Furthermore, we show that having two levels of parameterization (tasks and goals within tasks) enables more efficient learning of skills in an environment with a modular physical structure (e.g. multiple objects) as compared to flat, goal-parameterized RL with hindsight experience replay.
Endoscopic Management of Lacrimal System Dysgenesis and Dacryocystoceles in Fraser Syndrome: A Case Report and Literature Review

Background Fraser syndrome is an autosomal recessive disorder characterized primarily by syndactyly, cryptophthalmos, urinary tract anomalies, ambiguous genitalia, and laryngeal anomalies. A 28-year-old man with Fraser syndrome presented with cryptophthalmos, microphthalmia, lacrimal system dysgenesis, and chronic sinusitis. Objective The patients’ clinical condition and surgical treatment are described. A literature review was conducted, and articles relevant to the case are presented. Methods Case report. Results To our knowledge, this is the first published case report of endonasal management of dacryocystoceles in a Fraser syndrome patient. The patient was treated via endoscopic endonasal marsupialization and drainage. Conclusion Fraser syndrome patients may initially present to many different specialties as the spectrum of clinical manifestations is broad. Physicians treating these patients should take a collaborative approach to surgical and medical management.
Precipitation Nowcasting: Leveraging bidirectional LSTM and 1D CNN

Short-term rainfall forecasting, also known as precipitation nowcasting has become a potentially fundamental technology impacting significant real-world applications ranging from flight safety, rainstorm alerts to farm irrigation timings. Since weather forecasting involves identifying the underlying structure in a huge amount of data, deep-learning based precipitation nowcasting has intuitively outperformed the traditional linear extrapolation methods. Our research work intends to utilize the recent advances in deep learning to nowcasting, a multi-variable time series forecasting problem. Specifically, we leverage a bidirectional LSTM (Long Short-Term Memory) neural network architecture which remarkably captures the temporal features and long-term dependencies from historical data. To further our studies, we compare the bidirectional LSTM network with 1D CNN model to prove the capabilities of sequence models over feed-forward neural architectures in forecasting related problems.
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltage VDD down to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (around VDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications.
The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator

This paper presents a chopper stabilized amplifier with a discrete time parametric amplifier (DTPA) based signal demodulator. The DTPA demodulator enables signal amplification while down converting the chopped signal to baseband frequency. The low frequency noise and chopping ripples are cancelled during the track-and-hold process involved in the parametric amplification. The design is implemented in a standard 180 nm CMOS technology and the layout occupies 0.12 mm2 of area. The post layout simulation results confirm the gain augmentation of 9 dB from the DTPA demodulator. The proposed amplifier consumes 1.02 μA DC current from a 1.5 V supply. The achieved input noise spectral density of 147 nV/√Hz gives a noise efficiency factor of 5.4 over 400 Hz bandwidth. Furthermore, the design shows satisfactory performance for −20° C to 80° C temperature range and ±10 % of supply voltage variation at various process corner combinations of transistors. The worst case result is found at slow corner for −20° C with 1.35 V supply and the corner shows 47 dB of gain and 425 nV/√Hz of input noise spectral density.
The impact of planning intervention on business development: Evidence from the Netherlands

There has been a growing research interest in measuring the impact of planning and land-use regulations on housing market outcomes, but parallel development of the evidence base for the business sector has yet to occur. This article examines the impact of planning intervention on the amount of building investment taking place at sites allocated for industrial and business development. Measures that capture different dimensions of planning intervention are incorporated into models of industrial building investment. The models are estimated using a novel micro dataset on permit activity that covers a sample of industrial and business sites in the Netherlands. The results provide evidence of some of the expected negative effects of the regulatory role of planning intervention, but also show that proactive, targeted planning policies exert a significant and positive influence on investment activity. Specifically, policy-induced improvements to the physical environment will stimulate both new construction and refurbishment activity.
Epigenetic Control of Endocrine Pancreas Differentiation in vitro: Current Knowledge and Future Perspectives

The raising worldwide prevalence of Type 1 and Type 2 diabetes mellitus (T1DM and T2DM) solicits the derivation of in vitro methods yielding mature and fully functional β-cells to be used in regenerative medicine. Several protocols to differentiate human embryonic stem cells (hESCs) and induced pluripotent stem cells (iPSCs) into human pancreatic β-like cells have recently been developed. These methods, coupled with a bioengineering approach using biocompatible encapsulating devices, have recently led to experimental clinical trials showing great promises to ultimately end the battle of diabetic patients for managing hyperglycemia. However, in vitro differentiation protocols face the challenge of achieving homogenous population of mono-hormonal insulin-secreting mature β-cells. Major epigenetic events such as DNA methylation, post-translational modification of histones and non-coding RNAs expression, orchestrate physiological endocrine pancreas specification into α-, β-, γ-, and δ-cells, both in vivo and in vitro. The dysregulation of such epigenetic processes is associated to multiple pancreatic disorders including diabetes. Understanding the epigenomic and transcriptomic landscape underlying endocrine pancreas development could, therefore, improve in vitro differentiation methods. In this review, we summarize the most effective protocols for in vitro differentiation of hESCs/hiPSCs toward pancreatic β-cells and we discuss the current limitations in the derivation of functional glucose-responsive, insulin-releasing β-cells. Moreover, we focus on the main transcriptional and epigenetic events leading to pancreatic specification and on the applicative potential of novel epigenetic drugs for the establishment of innovative pharmacological therapeutic approaches.
A Portable Monitoring System with Automatic Event Detection for Sleep Apnea Level-IV Evaluation

To meet the demands on a comfortable screening, or even diagnostic, equipment without interfering with the sleep, this study develops a level IV portable system, equipped with two tri-axial accelerometers (TAA) measuring the thoracic and abdominal respiratory efforts, and one oximeter measuring the oxygen saturation (SpO2), to identify obstructive sleep apnea (OSA), central sleep apnea (CSA), and hypopnea (HYP) events. The prototype integrates all the hardware and software for physiological information extraction. In addition, an automatic event detection algorithm is proposed to reduce the labor-intensive work on scoring the events. Based on 63 subjects, with 80% data for training and 20% for validation, the classification accuracy of the apnea hypopnea-index (AHI) is 84.13%. The results indicate that the proposed algorithm has great potential to classify the severity of patients in clinical examinations for both the screening and the homecare purposes.
A New Soft-input Hard-output decoding algorithm for Turbo Product Codes

Turbo product codes (TPCs) are being considered as a competitive forward error correction scheme for ultra high speed network communication beyond 100Gbps [1], [2]. Conventional soft-input soft-output (SISO) decoders for turbo product codes (TPCs) need to exchange extrinsic soft messages between row and column component decoders. However, the extrinsic information increases the difficulty of hardware implementation. First of all, for a two dimensional message memory, row and column component decoders access soft messages in horizontal and vertical directions, respectively, resulting in potential memory access conflict. Secondly, the computation complexity of calculating the soft extrinsic information is very high. Finally, storing the extrinsic information needs additional memory and updating it frequently increas the decoding latency and power consumption. In this paper, we propose a new soft-input hard-output (SIHO) decoding algorithm for TPCs. The proposed SIHO decoding algorithm requires the exchange of only hard information between row and column component decoders, leading to simpler decoder architectures. Moreover, each component decoder of a SIHO TPC decoder does not generate any soft information. In terms of error correction performance, the SIHO decoding algorithm is in between the SISO and the hard-input hard-output decoding algorithm. It is believed that the SIHO decoding algorithm is a good tradeoff between high net coding gain (NCG) and low complexity implementation.
Flexible Wideband Radio Transceiver Testing using Non-Uniform Subsampling Demodulation

Software defined radios are a key enabling technology for Cognitive Radio Systems. However, production testing of software defined radios remains a difficult and costly endeavor. This paper introduces a new implementation of a loopback Built-in Self-Test (BIST) strategy using periodically non-uniform sampling of second order for RF loopback test of flexible transceivers, by means of charge-domain sampling. The novel architecture is compared to voltage-based sampling architectures, and simulation results demonstrate that our charge-based sampling approach performs better and is more tolerant of clock jitter. Our proposal can also be advantageously applied in transmitter architectures that use pre-distortion compensation to improve power amplifier linearity, provided that the main receiver baseband channel is available (idle).
A Multi-Mode Visual Recognition Hardware Accelerator for AR/MR Glasses

A multi-mode visual recognition hardware accelerator for AR/MR glasses is designed in this paper. The accelerator supports state-of-the-art deep neural networks, including DNN, CNN, RNN and LSTM. To achieve higher utilization rate of computational components, the accelerator supports two mapping modes of neural networks to physical computational structures in a single PE (Processing Engine) array: a) 2D systolic flow of both filter and image data, b) each neural network output maps to a PE. The accelerator adaptively chooses the more efficient mapping mode layer by layer, achieving a higher PE utilization rate than single mapping mode accelerators. When benchmarking with Inception-v4 network, the accelerator's PE utilization rate is 79.5%, which is 20 points higher than state-of-the-art embedded accelerators. Higher PE utilization rate contributes to lower latency, higher throughput, less power consumption and smaller chip area. When benchmarking with AlexNet, the accelerator processes 108 images per second, which fully meets the real-time requirement for AR/MR applications.
Mitigation technique for non-linear DC-shift induced by power supply noise in a 28 nm BGR reference

This paper presents a non-linear analysis of DC-shift induced by power supply noise in bandgap voltage references based on a diode connected PNP bipolar junction transistors (BJT) couple. The analysis is based on diode non-linear characteristic causing a variation of biasing currents involved in closed loop feedback. The observed effect is discussed, simulated, measured and compared with analytical derivation. A bandgap reference has been implemented in a CMOS 28 nm technology and used for successfully validating the proposed analysis.
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices

A real-time global matching optical flow estimation (OFE) processor is proposed for action recognition in mobile devices. The global OFE requires a large number of external memory accesses (EMAs) and matrix computations, thus it is incompatible on mobile devices with real-time constraints. For real-time OFE on mobile devices, this paper proposes two key features, both of which to reduce the required memory bandwidth and a number of computations: 1) Tile-based hierarchical OFE enables intermediate data to be processed within 328 KB on-chip memory without external memory access. 2) Background skipping eliminates redundant matrix computation for zero optical flow region. Therefore, the proposed features reduce external memory bandwidth and computation by 99.7 % and 50.7 %, respectively. The proposed 4 mm2 OFE processor is implemented in 65 nm CMOS technology, and it achieves real-time OFE of 46.1 frames-per-second (fps) throughput for an image resolution of QVGA (320×240) and the resulting optical flow can be successfully used for action recognition.
A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor

A 10 GHz bang-bang all-digital phase-locked loop (BB-ADPLL) is proposed for high-speed wireline communication. A novel high resolution fractional capacitor is proposed in LC-DCO, which overcomes the process limitation of MOM capacitors and raises Q factor. The resolution of DCO is improved more than ten times and the Q factor of the LC-tank increases two times. The ADPLL is fabricated in 65 nm CMOS process. The phase noise of the proposed 10 GHz ADPLL is −95.7 dBc/Hz @ 1 MHz offset and the RMS jitter is 0.88 ps (1 kHz to 100 MHz). The ADPLL consumes 10.5 mW from a 1.2 V supply voltage and occupies an active area of 0.06 mm2.
Convergence of IoT, Edge and Cloud Computing for Smart Cities

Cities require extensive underlying infrastructure to make them smart. But what does the concept of a “smart city” really mean? Does it mean a city designed for just one goal using standalone infrastructure—for example, an optimal transportation system, healthcare system, or safety system? Or, to qualify as a smart city, do we mean that all such services have been optimized to communicate and work together through fully-instrumented infrastructure? Of course, it all depends on who you talk to. I am more of the mind that all city services need to be optimized for a city to become truly “smart. ”
TRIM21 Restricts Coxsackievirus B3 Replication, Cardiac and Pancreatic Injury via Interacting With MAVS and Positively Regulating IRF3-Mediated Type-I Interferon Production

Tripartite motif-containing 21 (TRIM21) is a regulator of tissue inflammation and pro-inflammatory cytokine production, and has been implicated in negative regulation of IRF3-dependent type I interferon signaling. However, the antiviral activity of TRIM21 varies among diverse viruses and its role on regulation of type I interferon remains inconsistent in different microbial infections. Here, we investigate the potential role for TRIM21 in controlling Coxsackievirus B3 (CVB3) replication and susceptible organ pathology. We found that CVB3 infection up-regulated the expression of TRIM21 in hearts of mice and cardiomyocytes at early phase of infection. Knock-down of TRIM21 resulted in increased viral replication, while overexpression led to increased phosphorylation and dimerization of IRF3, increased IFN-β transcription and reduced viral replication in vitro. We demonstrate that TRIM21 promotes the activation of IRF3 in CVB3-infected cells via interacting with MAVS and catalyzing the K27-linked polyubiquitination of MAVS, thereby enhancing type I interferon signaling. The RING domain of ubiquitin ligase activity and PRY-SPRY domain of TRIM21 are critical for its anti-viral effect. In vivo overexpression of TRIM21 significantly protected mice against viral myocarditis by suppressing CVB3 replication and reducing cardiac inflammatory cytokine production. While TRIM21 deficient mice exhibited a decreased IFN-β production, an increased cardiac and pancreatic CVB3 replication, and aggravated pancreatic injury as well as myocarditis during acute infection. Thus, our results demonstrate TRIM21 as a positive regulator of IFN-β signaling by targeting MAVS during CVB3 infection and suggest it as a potent host defense against CVB3 infection and viral-induced injury in hearts and pancreas.