Beyond CMOS: Logic Suitability of In0.7Ga0.3As HEMT

We have fabricated 100 nm InAlAs/InGaAs HEMTs that feature a tunneling cap designed to minimize parasitic resistance. We have characterized these devices from the point of logic, studying figures of merit such as gate delay (CV/I), subthreshold slope (S), drain-induced barrier lowering (DIBL), and ION/IOFF. We have found that these devices exhibit promising logic characteristics. In particular, 100 nm Lg devices yield DIBL as low as 80 mV/V, S of 77 mV/decade, and ION/IOFF ratio in excess of 10 with a gate delay of about 1.2 ps. We have also found that these devices, from a logic application point of view, at 100 nm gate length have reached their scaling limit. Realizing the logic potential of In0.7Ga0. 3As HEMTs will require a more scalable device design with better electrostatic integrity. If this can be accomplished, InGaAs HEMTs could well be the technology of choice when the CMOS roadmap comes to end. INTRODUCTION Moore’s law has been a guiding principle for the semiconductor industry for over 30 years [1]. Sustaining Moore’s law requires continuous scaling of Si-transistors. In the current 65 nm technology node, the physical gate length of a Si MOSFET is about 30 nm. This dimension is expected to reach about 10 nm by 2011 [2]. This is broadly believed to be the ultimate limit for CMOS scaling [2]. Identifying a new semiconductor logic device technology is becoming increasingly pressing. Often mentioned candidates are carbon nanotube (CNT) transistors, semiconductor nanowires and, further out, spintronics [3-5]. Unfortunately, many of these device concepts are hardly beyond the prototyping stage. In contrast, III-V FETs and in particular InAlAs/InGaAs high electron mobility transistors (HEMTs) closely lattice matched to InP constitute a very real device technology that is worth considering. For the last almost 20 years, InAlAs/InGaAs HEMTs have held the world record of frequency response, as measured by cutoff frequency (fT), with a current record of 562 GHz [6]. This technology is also space qualified [7], and it is being actively considered for future optical fiber systems with transmission speeds in excess of 160 Gb/s [8]. Endowed with extraordinary electron transport properties, it seems imperative to evaluate the potential of InGaAs HEMTs for future beyondCMOS logic applications. In spite of all the progress realized in the last decade in this technology, until recently there has not been an analysis of the suitability of InGaAs HEMTs for logic applications. Figures of merit relevant to logic, such as logic gate delay (CV/I), ION/IOFF, Drain-Induced Barrier Lowering (DIBL) and subthreshold slope (S), have not been evaluated in this family of devices. Recently, we have studied these figures of merit in 50 nm In0.7Ga0. 3As HEMTs [9]. In spite of the fact that these devices were not optimized for logic operation, we found that they show substantial promise for logic. In this work, we have designed and fabricated 100 nm InAlAs/InGaAs HEMTs that feature a tunneling cap designed to minimize parasitic resistance and enhance logic operation. These devices offer excellent logic performance. However, at 100 nm gate length, we find that they have reached their scaling limit. Further gate length scaling will require aggressive insulator thickness scaling. PROCESS TECHNOLOGY Figure 1 shows the epitaxial layer structure which was used in this work. This was grown by molecular-beam-epitaxy. It features a strained In0.7Ga0. 3As subchannel in order to enhance electron transport. It also includes a 6 nm InP layer which acts as good gate recess etch-stopper as well as good surface passivation layer [10]. In addition, this structure features a multicap layer structure designed to yield extremely low parasitic source and drain resistance (RS and RD) which is critical for logic [11][12]. This includes a 5 nm strained and heavily-doped In0.65Ga0. 35As cap to reduce metal-tosemiconductor contact resistance and 15 nm heavily-doped In0.52Al0. 48As subcap to lower the energy potential barrier with the undoped In0.52Al0. 48As insulator layer in the source and drain access region. This will be discussed in more detail below. The Hall mobility (μn,Hall) and 2-DEG sheet carrier concentration (ns) for this sample were around 11,000 cm/V-sec and 3.0 × 10/cm at room temperature, respectively.