Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure

In this article, structure optimization of high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> IL can be formed during the high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> IL (<inline-formula> <tex-math notation="LaTeX">${T}_{\text {hk}}$ </tex-math></inline-formula>) with gate length (<inline-formula> <tex-math notation="LaTeX">${L}_{\text {G}}$ </tex-math></inline-formula>), spacer length (<inline-formula> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula>), and source/drain (S/D) length (<inline-formula> <tex-math notation="LaTeX">${L}_{\text {S/D}}$ </tex-math></inline-formula>), improved electrical performances were obtained. By optimizing <inline-formula> <tex-math notation="LaTeX">${T}_{\text {hk}}$ </tex-math></inline-formula> with properly adjusted <inline-formula> <tex-math notation="LaTeX">${L}_{\text {G}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">${L}_{\text {S/D}}$ </tex-math></inline-formula>, highly saturated ON-/OFF-current ratio (<inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula>) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay (<inline-formula> <tex-math notation="LaTeX">${C}_{\text {gg}}$ </tex-math></inline-formula>) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shown when <inline-formula> <tex-math notation="LaTeX">${L}_{\text {ext}}$ </tex-math></inline-formula> shrinks with extending <inline-formula> <tex-math notation="LaTeX">${T}_{\text {hk}}$ </tex-math></inline-formula>, was also investigated. Finally, the optimized electrical characteristics were obtained when <inline-formula> <tex-math notation="LaTeX">${T}_{\text {hk}}$ </tex-math></inline-formula> is adjusted with <inline-formula> <tex-math notation="LaTeX">${L}_{\text {G}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${L}_{\text {S/D}}$ </tex-math></inline-formula>. The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when <inline-formula> <tex-math notation="LaTeX">${T}_{\text {hk}}$ </tex-math></inline-formula> is optimized through <inline-formula> <tex-math notation="LaTeX">${L}_{\text {G}}$ </tex-math></inline-formula>. On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with <inline-formula> <tex-math notation="LaTeX">${L}_{\text {S/D}}$ </tex-math></inline-formula>, which result in lower static power. Based on this comparison, optimization method and guideline for high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> IL was proposed.