Potentialities of common-used TDC chips for high-speed event timer design

Potentialities and drawbacks of the off-the-shelf Time-to-Digital Converter (TDC) chips for building high-speed event timers are considered. To overcome the main shortcoming of TDCs, which is their limited measured interval range, a new technique to obtain the continuous and unlimited time scale is proposed and realized in a pilot version of a TDCbased high-speed event timer. The performance parameters of the pilot device such as RMS resolution vs. aggregate input event rate, non-linearity of time interval measurement between adjacent events, and non-linearity of event instance measurement have been evaluated. It is noted that, although the results show applicability of TDC chips for Laser Ranging related applications, the performance of the TDCs is still not up to the mark and might be improved. Introduction During last years the chips called Time-to-Digital Converters (TDC) became available on the market. Such chips provide time interval measurements with high event rate and multiple input channels with independent control. The independent channels allow measuring very short time intervals between Start and Stop events, including small negative time intervals. The chips employ digital interpolation circuitry, which allows achieving a very short dead time for each input channel. As a rule the dead time is limited by maximum write rate of internal buffer memory. Some TDC chips have arithmetic logic unit that are used for interpolation data preprocessing, including the averaging of results to increase the precision. One of the best TDC products is the chip TDC-GPX from ACAM Mess-electronic Gmbh. It offers several modes with different resolution and available number of channels. The mode with 8 LVTTL channels for Stop events offers typical RMS resolution of 81 ps and up to 182 MHz burst event rate for each channel (up to 32 events in one burst). Continuous average aggregate (for all channels) event rate in this mode is up to 40 MHz. Such rate can be supported by employing fast PC buses or new generation interfaces, for example USB 3.0. For lower average aggregate rates up to 15 MHz could be used existing interfaces: USB 2.0, FireWire. In the most accurate measurement mode only two LVPECL differential inputs for Stop events are available. In this mode 10 ps RMS resolution can be obtained although, at relatively low event rate (up to 500 KHz). The main drawback of TDC chips is that they are implemented according to the traditional time interval measurement technique and have a limited time interval measurement range. It means that they cannot be used directly to build true Event Timers. The goal of this work was to solve that problem and develop a high-speed TDC-GPX-based Event Timer with unlimited time range. The other goal was to evaluate potentialities and actual performance of such Event Timers. Proceedings of the 16th International Workshop on Laser Ranging 418 Constructing of Unlimited Single-valued Time Scale To solve the problem of the limited measurement range the manufacturer of TDC-GPX offered the possibility of an internal Start generation with controlled periodicity for a time counter re-triggering. Additional Restart counter allows to extend the measurement range up to 1.28 ms. The simplified block diagram of this mechanism is shown in Fig. 1. Start Stop 1 . Stop m TDC Restart counter MSB Time-base Frequency Timing Data Input Events Retrigger To external counter Figure 1. A TDC with Additional Restarting Circuitry The manufacturer suggested to count the most significal bit (MSB, Fig.1) changes in the external counter to get the unlimitted measurement range. Such simple way to extend the range can not be easily realized due to the problems with correct data reading, especially at high event rates. Indeed, if the user just directly employs an external counter, the state of the counter should be read at the moments when the input events arrive. It may lead to errors of association between codes that are written into the internal FIFO and those read from the external counter (so-called timing uncertainty) into some external FIFO. Even if such design is done correctly, with the use of a proper circuitry of timing uncertainty ellimination, it nevertheless is bulky and may degrade the accuracy performance of a timer. Besides, the amount of data to be transferred increases according to the required time scale extension length. And finally, the timeless measurement range cannot be obtained at all. To solve this problem we have come to a different solution (Artyukh 1 , 2008). One measurement input of the TDC was assigned as a specific marker input (see Fig. 2). The MSB signal of the restart counter is delayed (to avoid any timing uncertainty (Беспалько, 1985)) and then is fed into this input. The marker input is configured for accepting both positive and negative edges. In this way we insert specific marker events, corresponding to transitions of the MSB of the restart counter, into the output digital data stream that is transmitted further (into some controller block based on C, CPLD or FPGA). The constructing of single-valued time scale could be done either by the controller block firmware or by PC software where the data finally come in most of applications. The firmware or software detects the marker measurement data blocks and constructs the extension time scale simply as a variable to use for composing resultant time stamps. When it is done on a PC, this solution not only allows constructing practically limitless single-valued time scale by means of software but also substantially reduces the amount of transferred data for high rate event streams. Proceedings of the 16th International Workshop on Laser Ranging 419 Start Stop 1 . Stop m TDC Restart counter MSB Time-base Frequency