Miracle-dz/UniFAR-FTUs huggingface dataset:
Novel 60 GHz DRA topology adapted to the LTCC process

This paper presents a novel topology for the conception of millimeter-wave (60 GHz) cylindrical dielectric resonator antenna (DRA) compatible with LTCC (Low Temperature Co-Fired Ceramic) technology. The design process deals with the strategical modification of the shape of the resonator, in order to properly integrate its structure. This technique, compatible with the LTCC process, allows to avoid the use of glues, soldering substances or other mechanical parts which could disturb the antenna properties and to optimize the fabrication process. Moreover, the LTCC technology delivers an additional degree of freedom for the design, since it allows to build non canonical resonator shapes. The developed antenna covers the 57-63 GHz spectrum, being enabled for future 5G applications at the 60 GHz band. The design of the antenna is based on the Theory of Characteristic Modes analysis.
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware

Energy-constrained neural network processing is in high demanded for various mobile applications. Binary neural network aggressively enhances the computational efficiency, and in contrast, it suffers from degradation of accuracy due to its extreme approximation. We propose a novel accurate neural network model based on binarization and "dithering" that distributes the quantization error to neighboring pixels. The quantization errors in the binarization are distributed in the plane, so that a pixel in the multi-level source expression more accurately represented in the resulting binarized plane by multiple pixels. We designed a low-overhead binary-based hardware architecture for the proposed model. The evaluation results show that this method can be realized with a few additional lightweight hardware components.
What Do All These Numbers Mean? Data Visualization as an Innovative Methodology to Make Program Decisions

Background: There is a lack of consistent, comprehensible data collection and analysis methods for evaluating teacher preparation program’s coverage of required standards for accreditation. Of particular concern is the adequate coverage of standards and competencies that address the teaching of English learners and teachers of students from culturally and linguistically diverse backgrounds. Purpose: To graphically convey the findings of a faculty survey regarding English learner and multicultural content in teacher preparation coursework in order to inform them of inadequate coverage (and saturation) of those particular teaching standards and competencies. Setting: A small teacher preparation program in a Northern California public university that prepares elementary school teachers and special education teachers. Intervention: 10 full and part-time faculty members in a teacher preparation program that prepares elementary and special education teachers. Research Design: Congruency study, in which raw data from faculty survey responses were compared with rated program responses to teacher preparation standards by means of a relational database with graphing output capabilities. Data Collection: A survey instrument was designed and administered to all faculty members in the program. Findings: The resulting radar maps and other graphic outputs allowed faculty to clearly see where their course content aligned with the program accreditation response and where more coverage of that particular competency was necessary. Conclusions: The use of relational databases was a highly effective method for helping one teacher preparation program to visualize their progress towards meeting standards for teacher preparation in the area of student diversity and the teaching of English learners. Keywords: data visualization, program evaluation, teacher development
Sub-Array Clustering for Reconfigurable Reflectarrays with a Reduced Control Complexity

A method for the synthesis of reconfigurable reflectarray antennas with sub-array clustering is here presented. The approach is made up by two stages: an aperture synthesis devoted to the determination of the optimal clustering, common to all the beam configurations, and a reflectarray synthesis wherein the reflecting element belonging to the same cluster are driven with the same command phase.
Wideband SIW Cavity-Backed Slot Array Antenna with Flat Gain Characteristics for 79 GHz Automotive Radar

A wideband millimeter-wave SIW cavity-backed slot array antenna is proposed for 79 GHz automotive radar applications. The antenna element is composed of a slot fed substrate integrated waveguide (SIW) cavity which operates in TE210 mode, 2 pairs of rotationally symmetrical L-shaped radiating slots and 2 matching metallic blind holes. An 8-way SIW parallel power divider together with the antenna element is then utilized to feed a 2 × 4 array. By arranging the positions of metallic blind holes and metallic via holes, the electromagnetic energy leaking from bonding layer can be suppressed so that it causes no disturbance on radiation pattern while the SIW structure remains unchanged. The measured results show that the array antenna has flat gain characteristics in the frequency band of 75–82 GHz with gain variation less than 1 dB. Simulation and measurement results agree very well.
DP-Pack: Distributed Parallel Packing for FPGAs

Packing is one of the most critical stages in the FPGA physical syntheses flow. In this paper, we propose DP-Pack, a distributed parallel packing approach. DP-Pack consists of two primary steps. First, all of the minimal circuit units are assigned into several subsets where the conflicting units are located in the same subset and the non-conflicting units are distributed in different subsets. Then, the non-conflicting subsets are partitioned by round robin such that the number of subsets in each processor core is equal approximately, leading to good load balance in parallel packing. Second, the parallelization between processor cores is implemented by the MPI-based message queue in a distributed platform. Note that DP-Pack has been integrated into the VTR 7.0 tool. Experimental results show that our DP-Pack scales to 8 processor cores to provide about 1.4~3.2× runtime advantages with acceptable quality degradation, comparing to the academic state-of-the-art AAPack.
Support Vector Machine Based Method for Automatic Detection of Diabetic Eye Disease using Thermal Images

Diabetic eye disease is one of the major problems worldwide. That can cause major impairment to the eyes, including a permanent loss of vision. Early detection of eye diseases increase the survival rate by successful treatment. The proposed methodology is to explore machine learning technique to detect diabetic diseased using thermography images of an eye and to introduce the effect of thermal variation of abnormality in the eye structure as a diagnosis imaging modality which are useful for ophthalmologists to do the clinical diagnosis. Thermal images are pre-processed, and then Gray Level Co-occurrence Matrix (GLCM) based texture features from gray images, statistical features from RGB and HSI images are extracted and classified using classifier with various combination of features. To detect diabetic diseased eye, here Support Vector Machine classifier is used for classification and their performance are compared. A 5-fold cross validation scheme is used to enhance the generalization capability of the proposed method. Experimental results obtained for various feature combinations gives maximum accuracy of 86. 22%, sensitivity of 94. 07% and specificity of 79. 17% using SVM classifier with five-fold validation.
Improved Fabrication Methodology for Foldable All-Textile Cavity-Backed Slot Antennas

In this work, a new fabrication methodology for the production of textile cavity-backed substrate integrated waveguide slot antennas is proposed. This methodology involves laser cutting the entire electrotextile part in one single patch, which is then folded around a dielectric textile substrate. Since this procedure realizes the vertical cavity walls by slabs protruding from the electrotextile patch, heavy metal eyelet vias can be omitted, leading to a drastic reduction in antenna weight and improving wearability. Furthermore, this method is more suitable for automated mass production compared to existing design procedures: it requires fewer manipulations, diminishes alignment errors and suffers less from textile cutting inconveniences such as inaccuracies and textile fraying. This leads to a higher yield, and thus lower production costs. As a proof of concept, a broadband multi-moded cavity backed slot antenna is realized in this novel fabrication methodology. Measurements show a broadside gain of 6.5 dBi, a radiation efficiency of 70% and a fractional impedance bandwidth of 16%.
One-Meter Deployable Mesh Reflector for Deep Space Network Telecommunication at X- and Ka-band

A deployable one meter mesh reflector compatible with 12U-class CubeSat is introduced for telecommunication. It is compatible with NASA’s deep-space network (DSN) at X-band (i.e., uplink: 7.145-7.19 GHz; downlink: 8.4-8.45 GHz) and Ka-band frequencies (i.e., uplink: 34.2–34.7 GHz; downlink: 31.8–32.3 GHz). Three right-handed circularly polarized (RHCP) antennas, both transmit and receive, are introduced here: X-band only, Ka-band only, and X/Ka-band.
Estimation of Transmitted Power Density from Temperature Experiment for EMF Exposure Assessment at 60 GHz

This study aims to develop an experimental approach to estimate the transmitted power density inside human body for dosimetry study of millimeter wave exposure. We developed a temperature measurement system comprised of a millimeter wave generation apparatus at 60 GHz, a semi-solid glycerin phantom and an infrared camera. Based on this system, an estimation method of transmitted power densities was proposed by analyzing the temporal trend of temperature elevation on phantom surface. The validity of the proposed method was confirmed for the case of using a standard horn, and some results of using multi-element patch array antennas were demonstrated.
Injecting FPGA Configuration Faults in Parallel

When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challenges. In this paper, we present a framework and a concrete implementation of a parallel fault injection cluster that addresses these challenges. Scalability is addressed by using multiple identical FPGA devices, each testing a different region in parallel. Reliability is addressed by using reconfigurable system-on-chip devices, that are isolated from each other. Flexibility is addressed by using a pending commit structure, that continually checkpoints the overall experiment and allows elastic scaling. We test and showcase our approach by exhaustively flipping every bit in the configuration memory of the CHStone benchmark suite and a VivadoHLS generated k-means clustering image processing application. Our results show that: linear scaling is possible as the number of devices increases; the majority of error inducing bitflips in the k-means application do not significantly impact the output; and that the Xilinx Essential bits tool may miss some bits that can induce errors.
Comparative experiments of robust and adaptive control with new robust adaptive controllers for robot manipulators

Several conceptually different robust adaptive schemes, namely, a smooth robust adaptive sliding mode controller with guaranteed transient performance, a robust desired compensation adaptive controller with guaranteed transient performance, a simple robust performance based adaptive control scheme which has a nonlinear PID feedback structure with adaptation gains, and a robust desired compensation adaptive controller which is synthesized by combining the design techniques of performance based adaptive control and model based adaptive control and is easy to tune, are proposed for trajectory tracking control of robot manipulators. The schemes as well as other established adaptive schemes are implemented and compared on the UCB/NSK SCARA direct drive robot. Experimental results are obtained to show the advantages and the drawbacks of each method. <<ETX>>
Study on Characteristics of Paper Degradation in Natural Ester from Palm Oil-Based Insulation Liquid

Replacing mineral oil as transformer insulation by natural ester has been an issue since a long time ago. Natural ester is not only produced from sustainable materials, but also has other advantages as its environmentally friendly characteristic and more resistant to the high temperatures compared with mineral oil. Several types of research have been conducted to find out the change of paper and natural ester characteristic under thermal aging. This paper aims to study and analyze the kraft paper degradation of natural ester-based insulation liquid characteristic under accelerated thermal aging. In the present study, the natural ester is made from palm oil. This study is also intended to determine the influence of the initial water content of kraft paper on the thermal aging. The accelerated thermal aging was conducted in a closed container with two variations of temperature 100° C and 85° C for 1344 hours. The experimental results show changes in the degree of polymerization and tensile strength of kraft paper under accelerated thermal aging. Besides, this study also aims to determine the kraft paper degradation through morphological changes on the surface by using scanning electron microscope (SEM) test.
Transient Overvoltage Analysis in HVDC MMC Power Cables: Assessment of the Critical Points

The current scenario of continuous and increasing production of energy from renewable sources and the progressive increase of interties between different countries, gives the high voltage direct current transmission lines (HVDC) a role of present and future protagonist in the electrical power transmission. One of the main issues concerning the HVDC systems is the effect of the transient overvoltages (TOV) which occur during fault conditions on the DC side of a HVDC link. In fact, even if power cables are tested in order to withstand overvoltages with standardized characteristics, the real TOV phenomena do not have standard features. In this paper, the analysis of the TOVs of a HVDC symmetrical monopolar configuration is carried out, by studying the TOV propagation along the cable line and by defining step by step the overvoltage trend for different fault sections. Moreover, by means of a probability study, the most stressed points along the cable are identified by taking into account all the possible fault positions, so to highlight which are the more critical positions of the cable system irrespective of the fault section.
Exploiting Channel Hardening and Sphere Hardening for Large Antenna Arrays

For reliable and low latency communications, we consider encoding the data streams across the spatial channels instead of transmitting independent data stream over each spatial channel, and also instead of encoding the data across time. Using a stochastic MIMO channel model, we re-examine implications of using large Massive Multiple Input Multiple Output (MIMO) antenna arrays, such as those that extend across a large surface. The effects of additive noise at receivers, with large number of antennas, for Massive MIMO systems have not been fully addressed. We present a system model that achieves both channel hardening and noise sphere hardening. With channel hardening, the receiver does not need channel state information at the receiver (CSIR), for a sufficiently large transmit array. With receiver noise sphere hardening, the variations of the length of the noise vector is constrained to very small values, enabling error free communication above an average signal-to-noise ratio (SNR), for sufficiently large receive antenna array. Such systems are advantageous for applications with low latency requirements where at a given time instant, data can be received with improved reliability.
FPGA Implementation of 32-bit RISC-V Processor with Web-Based Assembler-Disassembler

In this study, a pure structural implementation based, 32-bit open source RISC-V processor is presented. The proposed processor is designed using Verilog and it is implemented on Cyclone IV 4CE115 FPGA device available on Altera DE2-115 Board. Additionally, web-based assembler and disassembler tools are developed and published as a part of this project. Before using the target RISC-V processor, the user can generate machine code using the web-based assembler tool. Then, the generated machine code can be downloaded onto the RISC-V processor using UART. The web-based assembler and disassembler tools are developed with technologies such as HTML5, CSS and JavaScript. The proposed processor is a fully functional processor that uses RV32I base integer instructional set with 37 instructions. The amount of hardware resources used by the whole processor circuit is about 43.7% of the Cyclone IV 4CE115 FPGA device and the maximum frequency achieved for the processor is 150MHz without using any timing constraint.
Deep Learning for Detection and Severity Classification of Diabetic Retinopathy

The objective of this project is to automate the detection of Diabetic Retinopathy and evaluate the severity with high efficiency, through an overall feasible approach. This project explores the use of various Convolutional Neural Network Architectures on images from the dataset after being subjected to appropriate image processing techniques like local average color subtraction to aid in highlighting the germane features from a fundoscopy, thereby augmenting the detection and evaluation process of Diabetic Retinopathy as well as serve as an expert guidance system for practitioners around the world.
Finite-Set Model Predictive Control Based Thrust Maximization of Linear Induction Motors Used in Linear Metros

This paper proposes a finite set model predictive control (FS-MPC) based thrust maximization technique for linear induction machines used in linear metros. For modeling of the proposed control method, the end effect is taken into consideration. The proposed control method is used to achieve maximum thrust per ampere and to reduce the thrust ripples. It differs from the FS-MPC methods, where the cost function consists of the thrust and angle errors. The thrust error is calculated from the difference between the reference thrust and the predicted thrust, and the angle error is calculated from the difference between the angle of predicted primary current and the angle of the predicted secondary flux in one side and π/4 on the other side. A comparison between the proposed method and the finite set model predictive direct thrust control (FS-MPDTC) is presented to illustrate the superiority of the proposed method. Both simulation and experimental analysis are conducted to validate the effectiveness of the proposed finite set model predictive direct angle control (FS-MPDAC). A prototype test platform is developed in the laboratory with two 3 kW arc induction motors. The simulation model, experimental test platform, and test results are presented in this paper.
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB

Fault detection is becoming more and more essential to the cryptographic circuits protection (for the purpose of fighting against both natural and malicious faults). While finite field multiplier is regarded as the bottleneck arithmetic unit for cryptosystems such as elliptic curve cryptography, efficient implementation of finite field multiplier with high fault detection capability is still missing in the literature. In this paper, therefore, we propose a novel fault detection scheme for finite field multipliers over GF(2m), where the proposed work aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation. To successfully carry out the proposed design strategy, we have used the modified shifted polynomial basis (MSPB) to represent the field and have conducted three coherent interdependent stages of efforts: (i) a novel 1-bit parity based detection scheme for bit-serial MSPB multiplier is presented after thorough mathematical derivation; (ii) a novel Toeplitz matrix-vector product (TMVP)-based multi-bit parity detection scheme for digit-serial MSPB multiplier is proposed then to obtain both high detection performance and low-complexity implementation; (iii) detailed complexity analysis and comparison show that the proposed designs have significantly better performance over the best of existing ones. For instance, for the bit-serial multipliers, the proposed design (using 1 parity bit) can achieve around 99.49% fault detection performance while the best existing one with 2-bit parity checking scheme achieves only 75.12% fault detection. The proposed scheme, because of its high fault detection capability and low-complexity, can be extended further in many cryptographic applications.
A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metal–oxide–semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology. This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current–voltage characteristics. At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor, a flexible logic circuit is realized in this work, which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor. It turns out that MOS-NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.
Resilience-Oriented Distribution System Restoration Considering Mobile Emergency Resource Dispatch in Transportation System

After major outages, local power sources, including mobile power sources (MPSs), can be coordinated to serve critical loads in distribution systems (DSs). Repair crews (RCs) are sent to repair faulted components. Both mobile emergency resources, i.e., MPSs and RCs, need to travel through the transportation system (TS) before they reach the destination for service. However, traffic congestion may happen after natural disasters and impact the dispatch of the MPSs and RCs. Therefore, the dynamic traffic state in the TS should be considered for efficient dispatch of mobile emergency resources. This paper proposes a framework to determine critical load restoration strategy for the DS, considering the dispatch strategy of the MPSs and RCs in the TS. The cell transmission model (CTM) is used to formulate the weighted dynamic traffic assignment problem (WDTA) in the TS as a linear program (LP), aiming at minimizing the total prioritized travel time of the MPSs and RCs. For the DS, the multi-period critical load restoration problem (CLR-DS) is formulated as a mixed-integer linear program (MILP) to maximize the cumulated service time to critical loads. Unbalanced three-phase power flow and time-varying topological constraints are considered. Case studies validate the effectiveness of the proposed method.