Design and Characterization of a 3 . 5 um pitch , 8192 resolution , 5 Spectrum CMOS TDI image sensor

In this paper we present a 5 spectrum TDI image sensor which is manufactured with a modified 1P6M CMOS process. Concept of CCD in CMOS with 3.5um pixel pitch has been verified. Design, characterization method and results will be addressed. Introduction TDI applications used to be dominated by CCDs because of its intrinsic charge transfer in array. Although there are many benefits in CMOS process such as low power, high integration, etc. we hardly see products for TDI processed with CMOS. Past works on TDI in CMOS can be categorized in two directions, with one working on signal summation in readout circuits [1-2] and the others on charge domain transfer in array [3-4]. Developments are shifting in the direction of charge domain transfer because it is noise free for signal adding while in circuit level, the noise will increase. We report in this paper a five band TDI image sensor with charge domain summation in CMOS process (CCD in CMOS). The middle band (P Band) is designed with 3.5um pitch, 8192 resolution, 192 stages CCD array. The other four bands (B1-B4 Band) are identical and designed with 7um pitch, 4096 columns, 96 stage CCD array. Stage selection, gain controls for these 5 bands can be freely configured with SPI setting. For each band, charge domain binning can be easily done in vertical direction with CCD gate control, while horizontal binning is done outside with FPGA in digital domain. The first part of the paper will focus on the full chip design, followed by a description of the test system and characterization results. Sensor Design Figure 1 shows a block diagram of the developed TDI image sensor. It is designed based on a modified 0.15um CMOS process. Together with the 5 band CCD arrays, we integrate on chip the signal readout chain, periphery circuit driving blocks and gate control blocks. Gate control blocks are designed with logic switches only for stage selection, scan direction change, etc. The driving of the gates is placed outside on board for best flexibility in slew rate control and voltage level tuning. This allows for best optimization when the fabricated sensor goes back. For a normal TDI scanning with multi-band on chip, the line rate is inversely proportional to the pixel size. Since the pixel size for P band is half of B band, the line rate for P band is double of the one in B band. When B band is working with pixel binning to 14um, the line rate will be reduced to one fourth of line rate in P band. In order to readout all the five band signals, we placed readout blocks on both top and bottom of the array. Each side of the readout will be responsible for half of the P-band pixel together with two B band arrays. The image sensor readout is quite similar to the one shown in [5]. Image signals will first be amplified and P17 Figure 9. TDI drum image captured using the test vehicle. Different pixel splits are delineated by single-column gaps (vertical white strips in the image). The test results are summarized and compared to the performance parameters of our proprietary CCD-TDI camera in TABLE I. The developed imager matches and/or outperforms the traditional CCD-TDI in several key performance parameters. TABLE I. Performance comparison between the developed imager and the traditional CCD-TDI. Parameters Unit Developed imager Traditional CCD-TDI CCD-CMOS monolithic integration Yes No Pixel pitch m 5 5.2 Selectable TDI stages Stages 64/128/192/256 (full) TDI scan direction Bi-directional Maximum TDI scan rate kHz 270 90 CTE per transfer Fraction of 1 > 0.99999 > 0.99999 Full well capacity Electrons > 30,000 > 35,000 AB ×Saturation Design for > ×100 (to be quantified) ×100 Dark current at 25C nA/cm 3.7 < 0.1 Non-linearity % < 2 < 2 Peak responsivity (DN12b)/(nJ/cm) 14,000 at 670 nm 4,800 at 520 nm Read noise Electrons 12 30 Power consumption Watt 2 for 4k resolution imager 40 for 12k resolution camera V. CONCLUSION We have developed the charge-coupled CMOS TDI imager using the custom CCD technology successfully integrated into a standard 0.18 m CMOS technology. The ultra-compact imager with CCD pixels and CMOS peripheral circuits monolithically integrated demonstrates promising results such as low noise, high speed, very high responsivity and low power consumption for a variety of applications that the CCD-TDI imager has served traditionally. REFERENCES [1] Martin Popp et al., “TDI System on Chip in OHC15L CCD / CMOS technology,” CNES Workshop Image Sensors, 2013. [2] Olivier Marcelot et al., “Study of CCD Transport on CMOS Imaging Technology: Comparison Between SCCD and BCCD, and Ramp Effect on the CTI,” IEEE Trans. Elect. Dev. , vol. 61, no. 3, 2014. [3] Piet De Moor et al., “Enhanced time delay integration imaging using embedded CCD in CMOS technology,” Proc. IEDM 2014. [4] James Janesick et al., “Fundamental performance differences between CMOS and CCD imagers Part III,” Proc. SPIE, vol.7439, 2009. [5] James Janesick, “Scientific Charge-Coupled Devices,” SPIE Press, 2001. [6] http://www.teledynedalsa. com/imaging/products/cameras/hs-line-scan/piranha-hs/HS-S0-12K40/.