Miracle-dz/UniFAR-FTUs huggingface dataset:
Feature formalisms and linguistic ambiguity

Typed feature formalisms are the most common representation for linguistic data in current natural language processing systems. They are applied across various linguistic levels ranging from syntax and semantics to morphology and even phonology. This book presents material at the core of natural language processing and computational linguistics throwing light on a number of interesting new developments, approaches and results.
Equivalence of results from two citation analyses: Thomson ISI's Citation Index and Google's Scholar service

Citation counts were performed across a wide range of disciplines using both the Thomson ISI files and Google Scholar, and shown to lead to essentially the same results, in spite of their different methods for identifying citing sources. This has strong implications for future citation analyses, and the many promotion, tenure and funding decisions based thereon, notably because ISI products are rather costly, while Google Scholar is free.
Natural Language Processing of Online Applications

Solids are separated from a liquid in a gravity settler provided with inclined solid intercepting surfaces to intercept the solid settling path to coalesce the solids and increase the settling rate. The intercepting surfaces are inverted V-shaped plates, each formed from first and second downwardly inclined essentially planar sections which extend from the apex within the vessel to the lower portion thereof adjacent the vessel wall.
Limited Resource Feature Detection, Description, and Matching

Limited-Resource Feature Detection, Description, and Matching Spencer G Fowers Department of Electrical and Computer Engineering Doctor of Philosophy The aims of this research work are to develop a feature detection, description, and matching system for low-resource applications. This work was motivated by the need for a vision sensor to assist the flight of a quad-rotor UAV. This application presented a realworld challenge of autonomous drift stabilization using vision sensors. The initial solution implemented a basic feature detector and matching system on an FPGA. The research then pursued ways to improve the vision system. Research began with color feature detection, and the Color Difference of Gaussians feature detector was developed. CDoG provides better results than gray scale DoG and does not require any additional processing than gray scale if implemented in a parallel architecture. The CDoG Scale-Invariant Feature Transform modification was developed which provided color feature detection and description to the gray scale SIFT descriptor. To demonstrate the benefits of color information, the CDSIFT algorithm was applied to a real application: library book inventory. While color provides added benefit to the CDSIFT descriptor, CDSIFT descriptors are still computationally intractable for a low-resource hardware implementation. Because of these shortcomings, this research focused on developing a new feature descriptor. The BAsis Sparse-coding Inspired Similarity (BASIS) descriptor was developed with low-resource systems in mind. BASIS utilizes sparse coding to provide a generic description of feature characterstics. The BASIS descriptor provided improved accuracy over SIFT, and similar accuracy to SURF on the task of aerial UAV frame-to-frame feature matching. However, basis dictionaries are non-orthogonal and can contain redundant information. In addition to a feature descriptor, an FPGA-based feature correlation (or matching) system needed to be developed. TreeBASIS was developed to answer this need and address the redundancy issues of BASIS. TreeBASIS utilizes a vocabulary tree to drastically reduce descriptor computation time and descriptor size. TreeBASIS also obtains a higher level of accuracy than SIFT, SURF, and BASIS on the UAV aerial imagery task. Both BASIS and TreeBASIS were implemented in VHDL and are well suited for low-resource FPGA applications. TreeBASIS provides a complete feature detection, description, and correlation system-on-a-chip for low-resource FPGA vision systems.
Teaching Our Children to Read: The Role of Skills in a Comprehensive Reading Program

One of the major concerns in education is the number of children who have a low comprehension of what they read. Many approaches have been adopted over the decades in an attempt to redress this situation - including phonics, discrete skill training and whole language - largely without success. Recent research indicates, however, that the most effective solution combines all three of these approaches. Bill Honig makes a strong case for a balanced approach to teaching reading in nursery school and primary school, and provides a step-by-step guide to the reading skills that should be introduced and mastered in each grade.
PENGUJIAN MONDAY EFFECT DAN ROGALSKI EFFECT PADA RETURN SAHAM LQ-45 DI BURSA EFEK INDONESIA

Anomali pasar merupakan bentuk dari penyimpangan terhadap pasar modal efisien. Beberapa peneliti menemukan bentuk anomali pasar seperti the day of the week effect, Monday effect, week end effect, dan January effect. Tujuan dari penelitian ini adalah untuk menguji fenomena Monday effect dan Rogalski effect pada return saham di Bursa Efek Indonesia. Sampel yang dipilih pada penelitian ini menggunakan teknik purposive sampling. Dalam penelitian ini ada 21 sampel perusahaan yang berturut-turut masuk indeks LQ-45 selama periode Januari 2012 sampai Desember 2014. Alat uji yang digunakan untuk menguji hipotesis ini adalah independent sample t-test. Hasil pengujian menemukan adanya fenomena Rogalski effect. Fenomena Monday effect terjadi pada periode tahun 2012, 2013, dan 2012-2014, tetapi tidak terjadi pada periode tahun 2014. Kata kunci: Anomali Pasar, Monday effect, Rogalski effect
Toward 'Complexics' as a transdiscipline

The proposed transdisciplinary field of ‘complexics’ would bring together all contemporary efforts in any specific disciplines or by any researchers specifically devoted to constructing tools, procedures, models and concepts intended for transversal application that are aimed at understanding and explaining the most interwoven and dynamic phenomena of reality. Our aim needs to be, as Morin says, not “to reduce complexity to simplicity, [but] to translate complexity into theory”. New tools for the conception, apprehension and treatment of the data of experience will need to be devised to complement existing ones and to enable us to make headway toward practices that better fit complexic theories. New mathematical and computational contributions have already continued to grow in number, thanks primarily to scholars in statistical physics and computer science, who are now taking an interest in social and economic phenomena. Certainly, these methodological innovations put into question and again make us take note of the excessive separation between the training received by researchers in the ‘sciences’ and in the ‘arts’. Closer collaboration between these two subsets would, in all likelihood, be much more energising and creative than their current mutual distance. Human complexics must be seen as multi-methodological, insofar as necessary combining quantitative-computation methodologies and more qualitative methodologies aimed at understanding the mental and emotional world of people. In the final analysis, however, models always have a narrative running behind them that reflects the attempts of a human being to understand the world, and models are always interpreted on that basis.
Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Prime Time

The first € price and the £ and $ price are net prices, subject to local VAT. Prices indicated with * include VAT for books; the €(D) includes 7% for Germany, the €(A) includes 10% for Austria. Prices indicated with ** include VAT for electronic products; 19% for Germany, 20% for Austria. All prices exclusive of carriage charges. Prices and other details are subject to change without notice. All errors and omissions excepted. H. Bhatnagar Advanced ASIC Chip Synthesis
State-of-the-Art: Interaktion in Erweiterten Realitäten

Die folgende Arbeit soll einen Uberblick uber bestehende Losungen zur Interaktion in Erweiterten Realitaten (Augmented Reality) schaffen. Hierzu werden anhand dreier grundlegender Betrachtungsweisen unterschiedliche Interaktionskonzepte und -umsetzungen sowohl von der technischen, als auch von der konzeptuellen Seite her, vorgestellt. Neben Fragen der Visualisierung werden unterschiedliche Typen von Benutzungsschnittstellen vorstellt. Den grosten Teil nehmen die drei typischen Interaktionsaufgaben Selektion- und Manipulation, Navigation und Systemkontrolle und die damit verbundenen Interaktionstechniken ein. Die Inhalte des Arbeitsberichts beschranken sich auf den Einsatz von Interaktionelementen in Augmented Reality Umgebungen. Dies geschieht in Abgrenzung zu Forschungsarbeiten auf dem Gebiet zu Interaktionstechniken in Virtual Reality Umgebungen (vollimmersiv oder auch desktoporientiert). Zwar standen und stehen viele Interaktionstechniken aus dem Bereich VR in der AR Pate, doch haben sich gerade im Bereich der AR neue Techniken und Konzepte entwickelt. Folglich sollen VR Techniken nur dann betrachtet werden, wenn Sie in AR Anwendungen angewendet wurden bzw. wenn ihre Anwendung sinnvoll erscheint.
Algorithmes de relaxation chaotique à retards

© AFCET, 1975, tous droits réservés. L’accès aux archives de la revue « Revue française d’automatique, informatique, recherche opérationnelle. Analyse numérique » implique l’accord avec les conditions générales d’utilisation (http://www.numdam.org/legal. php). Toute utilisation commerciale ou impression systématique est constitutive d’une infraction pénale. Toute copie ou impression de ce fichier doit contenir la présente mention de copyright.
Problemas de programación de tareas en máquinas en paralelo.

1 Departamento de Investigación de Operaciones, Escuela de Ingeniería de Sistemas y Centro de simulación y modelado CESIMO – Universidad de Los Andes, Mérida, Venezuela. Instituto de Organización y Control de Sistemas Industriales, Universidad Politécnica de Cataluña, Barcelona, España. liliana.capacho@upc.es 2 Instituto de Organización y Control de Sistemas Industriales, Barcelona, España. rafael.pastor@upc.es
Numerical techniques for the American put

This dissertation considers an American put option written on a single underlying which does not pay dividends, for which no closed form solution exists. As a consequence, numerical techniques have been developed to estimate the value of the American put option. These include analytical approximations, tree or lattice methods, finite difference methods, Monte Carlo simulation and integral representations. We first present the mathematical descriptions underlying these numerical techniques. We then provide an examination of a selection of algorithms from each technique, including implementation details, possible enhancements and a description of the convergence behaviour. Finally, we compare the estimates and the execution times of each of the algorithms considered.
Dijkstra's Dream Internal Iterators as Software Theorems

One of the main goals of structured programming is to make it possible for programmers to reason about and prove the correctness of programs. The assertions that describe the algorithm make explicit the complexity of the code. Encapsulation and inheritance remove an important part of that complexity in object-oriented programming. This paper shows that the reduction in com- plexity we get by replacing iteration structures by internal iterators is so big that it brings us very close to zero-defect software becoming viable.
Trace cache in simultaneous multithreading

Instruction fetch throughput is one of the most significant performance bottlenecks of a Simultaneous Multithreading Processor. Instruction fetch throughput limits the execution throughput of a Simultaneous Multithreading Processor even when the processor supports a large number of threads. A Trace Cache can improve instruction fetch throughput of a Superscalar Processor. In this dissertation, we have presented a new processor microarchitecture, Topaz, which adds a Trace Cache to a Simultaneous Multithreading Processor. We show that Topaz improves performance of a Simultaneous Multithreading Processor. An improvement of nine to fourteen percent is observed through our simulations. The results are achieved through mathematical analysis and simulation of SPEC2000 benchmark programs on Topaz. Also, in this dissertation, an analytical model of Trace Cache Miss Rates, and Trace Cache instruction fetch performance are presented. The analytical models are used to develop a new tool, Tulip, for fast performance analysis of Simultaneous Multithreading and Super-scalar processors. Implementation, benefits, and applications of Tulip are presented. The new tool is used as a guide for Topaz design and simulation. The actual simulation is carried out using a detailed cycle accurate out-of-order simulator. A new detailed microarchitecture simulator, Topazsim, is also presented in this dissertation.
Leader-Follower Consensus Problems of Multi-agent Systems with Noise Perturbation and Time Delays

考虑到为随机的微分延期方程的稳定性理论，有噪音不安和通讯时间延期的领导人追随者一致问题被调查。 当一张加权的指导的图和重量随机地与白噪音被使不安，在代理人之中的通讯被建模。 它是证明的经分解一致能与噪音和通讯时间的不安几乎肯定被完成，这推迟。 而且，数字例子被提供说明理论结果的有效性[摘要从作者]
Dickens and the city

List of Plates A note on the References Introduction: The Genesis of a Myth 1 Sketches by Boz: Fiction for the Metropolis 2 Pickwick Papers, Oliver Twist and Nicholas Nickleby: Labyrinthine London 3 The Old Curiosity Shop and Barnaby Rudge: Breakdown and Breakthrough 4 Martin Chuzzlewit: Architecture and Accommodation 5 Dombey and Son: The World Metropolis 6 Bleak House: Homes for the Homeless 7 Hard Times: The Industrial City 8 Little Dorrit: People Like Houses 9 A Tale of Two Cities, The Uncommercial Traveller and Great Expectations: Paradise Revisited 10 Our Mutual Friend: The Changing City Epilogue: Dickens and the City Appendix I: A Note on George Scharf Appendix II: A Note on Sources and Further Reading Select Bibliography Notes Index
Implementing Data-Parallel Software on Dataflow Hardware

The data-parallel programming model has become the de facto, baseline standard programming model for a variety of parallel computers, both SIMD and MIMD. The data-parallel programming model is easy to reason about, and has proven to be eeective for a variety of applications. For the most part, MIMD parallel computer designs have not been driven by the requirements and characteristics of data-parallel programming, despite the fact that those computers will likely be programmed in the data-parallel programming model. Designs that have considered data-parallel programming have included special hardware for explicitly implementing operations such as global barrier synchronization, scan and reduction. To examine the hardware support useful for implementing the data-parallel programming model, we have written a compiler and run-time system for a small data-parallel language targeted for EM-4, a hybrid dataaow/von Neumann computer. EM-4 provides an interesting alternative MIMD parallel architecture because of its unusually good hardware support for communications and synchronization. Our results show that EM-4's dataaow-style processor/network interface and a low la-tency, high bandwidth general routing network give excellent performance for data-parallel scatter and gather operations. In addition, such support provides equivalent performance, as well as more generality than special-purpose hardware for global barrier synchronization and scan-like operations, including parallel preex, reduction, and broadcast. Dataaow-style message synchronization is helpful, but not necessary. Acknowledgments This thesis would not have been done without the help of many people : : : Professor Arvind has supported my work since I was an undergraduate, and since that time, I have continually questioned his wisdom, examined those questions, gained insight, and realized that he was right. He gave me the freedom to pursue unlikely avenues of research when I left for Thinking Machines, and when I left for Japan { but in the end, I always came back home to dataaow. I'm not sure how many more times I'm going to run around this circle, but each time I do, I learn something new, and I hope that I also contribute something new. Bradley Kuszmaul suggested the topic for this thesis, and we spent many hours discussing it in the early stages of research. Steve Heller was my mentor at Thinking Machines, and our work together in compiling for communications on the CM-2 started me thinking about the data-parallel programming model. My boss at ETL, Yoshinori Yamaguchi, made my stay in Japan very smooth. Shuichi Sakai designed the EM-4, and helped me in …
Storage management for large scale systems

Because of the slow access time of disk storage, storage management, is crucial to the performance of many large scale computer systems. This thesis studies performance issues in buffer cache management and disk, layout management, two important components of storage management. The buffer cache stores popular disk pages in memory to speed up the access to them. Buffer cache management algorithms used in real systems often have many parameters that require careful hand-tuning to get good performance. A self-tuning algorithm is proposed to automatically tune the page cleaning activity in the buffer cache management algorithm by monitoring the I/O activities of the buffer cache. This algorithm achieves performance comparable to the best manually tuned system. The global data structure used by the buffer cache management algorithm is protected by a lock. Access to this lock can cause contention which can significantly reduce system throughput in multi-processor systems. Current solutions to eliminate lock contention decrease the hit ratio of the buffer cache, which causes poor performance when the system is I/O-bound. A new approach, called the multi-region cache, is proposed. This approach eliminates lock contention, maintains the hit ratio of the buffer cache, and incurs little overhead. Moreover, this approach can be applied to most buffer cache management algorithms. Disk layout management arranges the layout of pages on disks to improve the disk I/O efficiency. The typical disk layout approach, called Overwrite, is optimized for sequential I/Os from a single file. Interleaved writes from multiple users can significantly decrease system throughput in large scale systems using Overwrite. Although the Log-structured File System (LFS) is optimized for such workloads, its garbage collection overhead can be expensive. In modern and future disks, because of the much faster improvement of disk transfer bandwidth over disk positioning time, LFS performs much better than Overwrite in most workloads, unless the disk is close to full. A new disk layout approach, called HyLog, is proposed. HyLog achieves performance comparable to the best of existing disk layout approaches in most cases.
A Lisp-Stat- Based System for Experimentation in 3 DStatistical Graphics

W edescribeasystem, writteninL isp-Stat, fordesigningandconductingexperiments intheperception ofthree-dimensionaldynamic scatterplots. T he system includes tools fordesigning stimuli thatsystematicallyvaryaspects ofthedisplay(e.g., thepresence ofgraphicalelementssuchasaxes, regressionsurfaces, andresiduals)andforconvenientlygeneratingdatasets thatcan incorporatefeatures suchasnonlinearityand outliers. T hesystem is designedtopresentstimuli to subjects automatically, to interactwith the subjects, and tocollectinformation abouttheirresponses and response-latencies. Itis hopedthatthis softwarewill contributetotheinvestigationofthepropertiesofthreedimensionalstatisticalgraphs, and, ultimately, totheir improvement.
Short Range Pulse Based Inductive Transceiver

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Industrial experiences of developing quality gates for software development process

The purposes to use quality gates in software development are many. Quite often companies see that the usage of quality gates improves their overall efficiency, effectiveness and output quality of software delivery chain. They also see that the usage of quality gates helps them to make things right at once by not skipping quality assurance actions. This paper defines quality gate model for a software company. As well it shows that even quality gates might be in place they are not always followed because of a business reason. Companies can forget their well structured quality gate systems when business reason justifies it. The results of neglecting quality gates might lead to a situation where software asset output is not trusted anymore and quality is not known. In a longer run quality gate system seems to be as good as human being who is keeping it. This paper discusses about the most typical software development quality gates in an industrial context. As well it gives reasoning why these gates are usable and defines general criteria for each of them. Paper notifies that even quality gates are in place, they are not useful if not followed.
A decision support system for trust formalisation

Business to consumer (B2C) electronic commerce (EC) has seen a phenomenal growth since the development of the Internet, and there is a growing interest from many organizations to use it as a way to improve their competitiveness and reach a wider customer base. According to eMarketer, the total business of B2C EC has increased from $30 billions in 2002 to $90.1 billions in 2003 and continued increasing aBstract
DESIGN AND IMPLEMENTATION OF HIGH-SPEED DATA TRANSFER PROTOCOL IN CORBA ENVIROMENT

A limited slip differential includes a friction clutch mechanism, an electromagnetic coupling, and a camming mechanism disposed between the friction clutch mechanism and the electromagnetic coupling. The camming mechanism converts shearing forces within the electromagnetic coupling to an axial force applied to engage the clutch mechanism. The camming mechanism includes annular discs having axially inclined ramps, and a roller bearing for movement along the ramps to provide for variable spacing between the annular discs, wherein increased spacing is used to apply the axial force.