Design and Automation for Low Power Systems

This report is to present some results of the project funded by National Science Council from 2003 to 2006. Our objectives are mainly to explore and find new techniques in physical design, including floorplanning/placement and clock tree physical synthesis, for low power demand. In this report, we will demostrate the effectiveness of our execution in three years [42], [34], [9], including additional publications [10], [11], [23], [54], [53]. In the first part, we show some results in improving clustered voltage scaling by better power-timing slack sensitivity strategy [42]. We further generate voltage islands f or low power designs with performance constraints consideration in second part [34]. As for the third part, we present a methodology for low power clock tree synthesis by transition time manipulation from library study [9]. I. A M ORE EFFECTIVE POWER-TIMING SLACK SENSITIVITY METRIC IN DUAL VDD A SSIGNMENT OF LOW POWER VLSI A RITHMETRICS Power consumption problem has been critical for a long time. It increases the design difficulty for battery powered applications, and also affects ordinary designs in terms of time to market, cost, and reliability. Clustered Voltage Sc aling (CVS) is an effective way to reduce IC power consumption. CVS utilizes the excess time slacks inside circuits and trad e them for power reduction. Methods based on CVS for saving power have been studied for years. In this work, we study the previous approaches and propose an improved CVS method called Bilateral CVS (BCVS). BCVS is a general Clustered Voltage Scaling method which subsumes both CVS and ECVS (also GECVS), and also includes a more effective priority criterion metric in power-timing slack sensitivi ty. The experimental results show that previous CVS approaches, especially GECVS [30], save substantial power in some arithmetic cell-based designs. Among all approaches, BCVS outperforms GECVS 13% power saving in a 32-bit multiplier under our experimental setup with level converter insertio n consideration. A. Background and Objective Power dissipation is an important design parameter in the design of microelectronic circuits nowadays, especial ly in portable computing devices and personal communication applications, also in battery powered applications. A desi gn might be considered not valuable because it consumes too much power. Thus the low power skills become more significant than before [14]. Since dynamic power dissipation in CMOS circuits is directly proportional to the square of the supply voltage (VDD), reduction in VDD can lower the power dissipation considerably. Voltage scaling, sometim s with dual threshold voltage [5], [2], [29], [28], is one of the most effective techniques in reducing the power consumption of CMOS circuits. However, decreasing VDD leads to increase in circuit delay. In the designs of most microprocessors or ASIC chips, the operating frequency is set by the design specification according to the target marke t. The timing constraints in chips are in turn set by the operati ng frequency. Designers need to optimize designs to reduce power consumption within the specified timing constraints. If the supply voltage is reduced while VTH remains constant, the critical-path delay will not meet the timing constraint s (Fig.1). Clustered voltage scaling (CVS) is a technique which partially reduces the supply voltage. It utilizes the exces s time slack within circuits and then trades the time slack for powe r saving. Methods based on CVS for saving power have been studied for years, including [46], [48], [30], [47], [8]. [4 6] was one of the original papers discussing CVS. Due to some limitation in inserting level converter [22], [48] improve d CVS in inserting non-flip-flop-type level converters. Not greedily enough, [30] found a way to assign power-timing slack sensitivity (propagation priority) to further impro ve power saving. However, due to mixed information in the sensitivity assigned for dual VDD assignment, it will not obtain tremendous power saving at all times. In this work, we propose an improved power-timing slack sensitivity strategy for dual VDD assignment. Our main contributions are as follows. First, we have studied previo us Fig. 1. Output timing distribution of some design in our experimental platform. It shows the migration of output arrival time and this causes the difficulty in designing dual VDD systems. CVS techniques and experimented on some arithmetic circuits under our experimental setup. We further demostrate t he effectiveness of those approaches, like in [30]. Second, du e to our improved propagation priority from [30], we obtain more power saving with our greedy based bilateral CVS (BCVS). Among all approaches, BCVS outperforms GECVS 13% power saving in a 32-bit multiplier under our experimental setup with level converter insertion consideration. B. Clustered Voltage Scaling Techniques In the following subsections, we briefly describe three earlier VDD assignment methodologies for low power design and give our problem formulation. 1) Cluster Voltage Scaling (CVS): As shown in Fig. 1, the output arrival time of a circuit usually distributes ove r a range. After lowering down the supply voltage for low power operation, the output arrival time migrates to a slower rang e. If the required timing constraint lies on an interval, such a s 5.5∼6ns in the shown case, we might fail to find a low power solution in total supply scaling down (voltage island [31] f or a subcircuit). Clustered Voltage Scaling (CVS), firstly proposed by Usami et al. [46], is a simple and practical technique for low power design. The essence of CVS is based on the utilization of excess timing slack in synchronous circuits. It relies on the inner excess time slack inside circuit blocks. Since mos t circuits have a critical path and other non-critical paths, we usually have the opportunity to minimize power consumption