Miracle-dz/UniFAR-FTUs huggingface dataset:
Build reliable and efficient neuromorphic design with memristor technology

Neuromorphic computing is a revolutionary approach of computation, which attempts to mimic the human brain's mechanism for extremely high implementation efficiency and intelligence. Latest research studies showed that the memristor technology has a great potential for realizing power- and area-efficient neuromorphic computing systems (NCS). On the other hand, the memristor device processing is still under development. Unreliable devices can severely degrade system performance, which arises as one of the major challenges in developing memristor-based NCS. In this paper, we first review the impacts of the limited reliability of memristor devices and summarize the recent research progress in building reliable and efficient memristor-based NCS. In the end, we discuss the main difficulties and the trend in memristor-based NCS development.
Segurança da Informação: Proposta de arquitetura de alta disponibilidade para aplicações web

This short paper discusses the context of high availability within the information security in web applications presenting a proposal for development of an infrastructure cluster with load balancing. For development of same personal computers will be used, Linux operating system and software for high availability, server will be used to provide access to web pages, databases and distributed file system, and all free tools. Resumo. Este artigo aborda o contexto da alta disponibilidade dentro da seguranca da informacao em aplicacoes para web apresentando uma proposta de desenvolvimento de uma infraestrutura de cluster com balanceamento de carga. Para desenvolvimento da mesma serao utilizados computadores pessoais, sistema operacional Linux e softwares de alta disponibilidade, servidor para prover ao acesso a paginas da web, banco de dados e sistema de arquivos distribuidos, sendo todas as ferramentas livres. 1. Introducao Devido ao constante crescimento no uso da Internet motivado pelo barateamento de equipamentos como computadores, notebooks, smartphones, etc e a conexao com a Internet tornando-se cada vez mais barata e rapida, as organizacoes estao cada vez mais utilizando a web como uma solucao eficaz de comunicacao, marketing e comercio eletronico. Uma empresa que trabalha com comercio eletronico pode ter inumeros prejuizos se o seus servicos web ficarem indisponiveis por qualquer periodo de tempo, nao importando a origem do problema, seja ele por ataques de negacao de servico, congestionamento na rede, falhas na infraestrutura do datacenter como hardware defeituoso, erros de software ou paradas de manutencao programada. Esses sao problemas que alem de prejudicar a imagem da empresa irao comprometer sua confiabilidade. Segundo (LAUREANO 2012), a seguranca da informacao e um ponto chave em qualquer sistema, para o mesmo ser dito seguro ele deve prover tres aspectos que sao a integridade, confiabilidade e disponibilidade. O objetivo desse trabalho e propor a criacao de um ambiente totalmente tolerante a falhas como acontece em datacenters de grande porte, utilizando apenas computadores pessoais e softwares open source visando garantir a disponibilidade continua de 99,999% do sistema, ou seja ter a garantia que o sistema podera ficar inoperante por um periodo maximo de aproximadamente cinco minutos durante um ano.
Cognate Identification to improve Phylogenetic trees for Indian Languages

Cognates are present in multiple variants of the same text across different languages. Computational Phylogenetics uses algorithms and techniques to analyze these variants and infer phylogenetic trees for a hypothesized accurate representation based on the output of the computational algorithm used. In our work, we detect cognates among a few Indian languages namely Hindi, Marathi, Punjabi, and Sanskrit for helping build cognate sets for phylogenetic inference. Cognate detection helps phylogenetic inference by helping isolate diachronic sound changes and thus detect the words of a common origin. A cognate set manually annotated with the help of a lexicographer is generally used to automatically infer phylogenetic trees. Our work creates cognate sets of each language pair and infers phylogenetic trees based on a bayesian framework using the Maximum likelihood method. We also implement our work to an online interface and infer phylogenetic trees based on automatically detected cognate sets. The online interface helps create phylogenetic trees based on the textual data provided as an input. It helps a lexicographer provide manual input of data, edit the data based on their expert opinion and eventually create phylogenetic trees based on various algorithms including our work on automatically creating cognate sets. We go on to discuss the nuances in detection cognates with respect to these Indian languages and also discuss the categorization of Cognate words i.e., "Tatasama" and "Tadbhava" words.
Phone-nomenon: a system-level thermal simulator for handheld devices

This work presents a system-level thermal simulator, Phone-nomenon, to predict the thermal behavior of smartphone. First, we study the nonlinearity of internal and external heat transfer mechanisms and propose a compact thermal model. After that, we develop an iterative framework to handle the nonlinearity. Compared with a commercial tool, ANSYS Icepak, Phonenomenon can achieve two and three orders of magnitude speedup with 3.58% maximum error and 1.72°C difference for steady-state and transient-state simulations, respectively. Meanwhile, Phone-nomenon also fits the measured data of a built thermal test vehicle pretty well.
Where to Post: Routing Questions to Right Community in Community Question Answering Systems

At present, question-answer (QA) sites have become one of the most important sources of information sharing. In order to ease search and categorization, QA sites create communities to discuss a specific topic or interest. As a consequence, a large number of communities have been created in the last few years. A lot of research has been conducted on community QA sites to address various problems including expert identification and tag recommendation. However, an important problem that has been neglected so far is to automatically route a question to the right community. In this paper, we propose a novel word-embedding based method to route a question to the right community. We use syntactic as well as semantic features to characterize a question and community. Although this approach of characterization performs well, it is highly computationally expensive. To deal with this problem, we use topic modeling, which effectively summarizes a community and reduces the computation time. Our experimental results reveal that usage of both syntactic and semantic features helps in question routing and leads to a better community prediction. We evaluate our methods on a well-known question answering system Stack Exchange and show the effectiveness of the proposed method.
On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA

It is very challenging to design an on-chip memory architecture for high-performance kernels with large amount of computation and data. The on-chip memory architecture must support efficient data access from both the computation part and the external memory part, which often have very different expectations about how data should be accessed and stored. Previous work provides only a limited set of optimizations. In this paper we show how to fundamentally restructure on-chip buffers, by decoupling logical array view from the physical buffer view, and providing general mapping schemes for the two. Our framework considers the entire data flow from the external memory to the computation part in order to minimize resource usage without creating performance bottleneck. Our experimental results demonstrate that our proposed technique can generate solutions that reduce memory usage significantly (2X over the conventional method), and successfully generate optimized on-chip buffer architectures without costly design iterations for highly optimized computation kernels.
Travel Time Prediction of Taxis using Tensor Factorization

The analysis of data streams offers a great opportunity for development of new methodologies and applications in area of Intelligent Transportation System. Travel time prediction of a path is an important task in route planning and navigation applications. As more GPS floating car data has been collected to monitor urban traffic, GPS trajectories of floating cars have been frequently used to predict path travel time. Solving this problem involves two major impediments which are the facts that firstly many road segments may not be traveled by any GPS equipped vehicles in given time slot and in most cases a trajectory exactly traversing a query path cannot be found either. Second for the fragment of a path with trajectories there are multiple ways of combining the trajectories to estimate corresponding travel time. To address these challenges different drivers travel times on different road segments in different time slots is modeled with a three dimension tensor. Combined with geospatial, temporal and historical contexts learned from trajectories the tensor's missing values are filled through a context-based tensor decomposition approach. Therefore this paper aims to solve the problem that given a travel time prediction query, the congestion patterns around the query path are identified from historical trajectories, then its travel time is inferred in near future. Experiment results using Uber GPS traces[1] of black cab pickups which comprises of 14500 trips (after data cleaning) in areas of San Francisco shows that the prediction has on average 3.36 minutes of error on trips of duration 6 to 25 minutes.
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter

A secure version of the naïve Bayesian filter (NBF) is proposed utilizing partially homomorphic encryption (PHE) scheme. SNBF can be implemented with only the additive homomorphism from the Paillier system, and we derive new techniques to reduce the computational cost of PHE-based SNBF. In the experiment, we implemented SNBF both in software and hardware. Compared to the best existing PHE scheme, we achieved 1,200x (resp., 398,840x) runtime reduction in the CPU (resp., ASIC) implementations, with additional 1,919x power reduction on the designated hardware multiplier. Our hardware implementation is able to classify an average-length email in 0.5 s, making it one of the most practical NBF schemes to date.
A sharing-aware L1.5D cache for data reuse in GPGPUs

With GPUs heading towards general-purpose, hardware caching, e.g. the first-level data (L1D) cache is introduced into the on-chip memory hierarchy for GPGPUs. However, facing the GPGPU massive multi-threading, the small L1D requires a better management for a higher hit rate to benefit the performance. In this paper, on observing the L1D usage inefficiency, such as data duplication among streaming multiprocessors (SMs) that wastes the precious L1D resources, we first propose a shared L1.5D cache that substitutes the private L1D caches in several SMs to reduce the duplicated data and in turn increase the effective cache size for each SM. We evaluate and adopt a suitable layout of L1.5D to meet the timing requirements in GPGPUs. Then, to protect the sharable data from early evictions, we propose a sharable data aware cache management, which leverages a lightweight PC-based history table to protect sharable data on cache replacement. The experiments demonstrate that the proposed design can achieve an averaged 20.1% performance improvement with an increased on-chip hit rate by 16.9% for applications with sharable data.
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing

Training Convolutional Neural Networks(CNNs) is both memory-and computation-intensive. The resistive random access memory (ReRAM) has shown its advantage to accelerate such tasks with high energy-efficiency. However, the ReRAM-based pipeline architecture suffers from the low utilization of computing resource, caused by the imbalanced data throughput in different pipeline stages because of the inherent down-sampling effect in CNNs and the inflexible usage of ReRAM cells. In this paper, we propose a novel ReRAM-based bidirectional pipeline architecture, named HUBPA, to accelerate the training with higher utilization of the computing resource. Two stages of the CNN training, forward and backward propagations, are scheduled in HUBPA dynamically to share the computing resource. We design an accessory control scheme for the context switch of these two tasks. We also propose an efficient algorithm to allocate computing resource for each neural network layer. Our experiment results show that, compared with state-of-the-art ReRAM pipeline architecture, HUBPA improves the performance by 1.7X and reduces the energy consumption by 1.5X, based on the current benchmarks.
An approximation algorithm to the optimal switch control of reconfigurable battery packs

The broad applications of lithium-ion batteries in cyber-physical systems attract intensive research on building energy-efficient battery systems. Reconfigurable battery packs have been proposed to improve reliability and energy efficiency. Despite recent efforts, how to simultaneously maximize battery usage time and minimize switching count during reconfiguration is rarely addressed. In this work, we devise a control algorithm that, under a simplified battery model, achieves the longest usage time under a given constant power-load while the switching count is at most twice above the minimum. It is further generalized for arbitrary power-loads and adjusted for refined battery models. Simulation experiments show promising benefits of the proposed algorithm.
Comparing the efficacy of intravenous ketorolac versus intravenous ibuprofen in relieving renal colic pain; a randomized clinical trial

Introduction: Various therapies have been used to relieve or improve the urinary colic pain, but many of these treatments have been limited due to side effects associated with the drugs. In this regard, opioid drugs and nonsteroidal anti-inflammatory drugs (NSAIDs) have a higher priority than other treatments. Objectives: The aim of the present study was to compare the level of pain relief from renal stones after the administration of two types of NSAIDs, including intravenous ibuprofen versus intravenous ketorolac. Patients and Methods: In this clinical trial (identifier: IRCT20180108038276N1), 70 patients with renal colic pain were randomly treated with intravenous ketorolac (30 mg, n = 35) or with intravenous ibuprofen (800 mg, n = 35). The patient’s pain severity was assessed by the visual analogue scaling (VAS) method before and 20 and also 60 minutes after interventions. Results: Although pain severity considerably reduced within 60 minutes of prescribing ibuprofen and ketorolac, the trend of the change in pin score was not different between the two groups (P = 0.734). We found no significant difference in appearance of some side effects including nausea and vomiting, requiring use of ondansetron, need to prescribe additional analgesics. However epigastric pain and need to administrating H2 blockers were not revealed in the group receiving ketorolac, but these complications were found in 25.7% of the patients received ibuprofen indicating a significant difference (P = 0.002). Conclusion: A single dose administration of both intravenous ketorolac and ibuprofen is associated with significant improvement in renal colic pain within one hour after administration. However, due to the lower incidence of gastrointestinal complications in the administration of ketorolac compared to ibuprofen, the use of ketorolac in treatment and relief of renal colic pains is preferable.
Redeeming chip-level power efficiency by collaborative management of the computation and communication

Power consumption is the first order design constraint in future many-core processors. Conventional power management approaches usually focus on certain functional components, either computation or communication hardware resources, trying to optimize its power consumption as much as possible, while leave the other part untouched. However, such unilateral power control concept, though has some potentials to contribute overall power reduction, cannot guarantee the optimal power efficiency of the chip. In this paper, we propose a novel Collaborative management approach, coordinating both Computation and Communication infrastructure in tandem, termed as CoCom. Apart from prior work that deals with power control separately, it leverages the correlations between the two parts, as the "key chain" to guide their respective power state coordination to the appropriate direction. Besides, it uses dedicated hybrid on-chip/off-chip mechanisms to minimize the control cost and simultaneously guarantee the effectiveness. Experimental results show that, compared with the conventional unilateral baselines, CoCom is able to achieve abundant power reduction with minimal performance degradation at the same time.
Space-time Prediction of High Resolution Raster Data: An Approach based on Spatio-temporal Bayesian Network (STBN)

Prediction of spatial raster time series, especially those obtained from satellite remote sensing imagery, plays a crucial role in monitoring various complex spatio-temporal processes, such as urban growth, deforestation, flooding, and so on. With the recent advancement of remote sensing technology, the availability of such raster data with high spatial/temporal density has increased exponentially. However, efficiently extracting complex spatio-temporal relationships by proper utilization of these enormous volumes of data is a critical issue which imposes significant challenge in timely processing and prediction of such spatio-temporal data. This paper proposes spatio-temporal Bayesian network (STBN) which is able to efficiently model/capture the temporal dynamics of spatial dependency among variables and eventually helps accelerating the spatial time series prediction process. The performance of the proposed STBN has been evaluated in comparison with several state-of-the-art prediction models and baseline techniques. Overall, the proposed STBN-based prediction model is found to show improved accuracy with considerably reduced computational cost.
Quel musée pour l’art contemporain ?

L’auteur demontre comment l’evolution des pratiques artistiques conduit les musees a se remettre en cause. Etudiant le concept de « contemporaneite », elle se penche sur la relation existant entre l’art contemporain et les institutions museales, s’interrogeant sur les perspectives s’offrant a celles-ci.
A 65-nm CMOS fully-integrated circulating tumor cell and exosome analyzer using an on-chip vector network analyzer and a transmission-line-based detection window

A fully-integrated CMOS circuit based on a vector network analyzer (VNA) and a transmission-line-based detection window for circulating tumor cell (CTC) and exosome analysis is presented. We have introduced a fully-integrated architecture, which eliminates the undesired parasitic components and enables high-sensitivity, for analysis of extremely low-concentration CTC in blood. To validate the operation of the proposed system, a test chip was fabricated using 65-nm CMOS technology. Measurement results shows the effectiveness of the approach.
A staircase structure for scalable and efficient synthesis of memristor-aided logic

The identification of the memristor as fourth fundamental circuit element and, eventually, its fabrication in the HP labs provide new capabilities for in-memory computing. While there already exist sophisticated methods for realizing logic gates with memristors, mapping them to crossbar structures (which can easily be fabricated) still constitutes a challenging task. This is particularly the case since several (complementary) design objectives have to be satisfied, e.g. the design method has to be scalable, should yield designs requiring a low number of timesteps and utilized memristors, and a layout should result that is hardly skewed. However, all solutions proposed thus far only focus on one of these objectives and hardly address the other ones. Consequently, rather imperfect solutions are generated by state-of-the-art design methods for memristor-aided logic thus far. In this work, we propose a corresponding automatic design solution which addresses all these design objectives at once. To this end, a staircase structure is utilized which employs an almost square-like layout and remains perfectly scalable while, at the same time, keeps the number of timesteps and utilized memristors close to the minimum. Experimental evaluations confirm that the proposed approach indeed allows to satisfy all design objectives at once.
Detection externalisée de vulnerabilités pour la plateforme Android à l'aide du langage OVAL

Nous proposons dans ce rapport une approche novatrice pour analyser les systemes Android et detecter leurs vulnerabilites de facon legere. Cette approche regroupe les principales composantes du processus d'analyse sous forme de service externalise que les clients mobiles peuvent ensuite exploiter a l'aide d'un agent minimal. Le langage OVAL est utilise comme support pour la description et l'analyse de vulnerabilites. En configurant la frequence des analyses et le pourcentage de vulnerabilites a traiter au cours de chacune d'entre elles, l'approche proposee permet de limiter l'allocation de ressources cote client et de transferer les differents traitements sur des serveurs distants. La strategie employee consiste a partager et distribuer les analyses a travers le temps pour reduire significativement l'activite sur les systemes mobiles, tout en assurant un traitement de la totalite des vulnerabilites connues dans un laps de temps fini. De cette methodologie resulte un processus d'analyse oriente cloud plus leger et plus rapide, pouvant limiter de facon significative la consommation de ressources et d'energie cote client.
Identification of the population

A common goal, in both general and psychological medicine, is to identify individuals ‘at risk’ of a particular disorder and to intervene in those ‘at risk’ to prevent the disorder from becoming manifest. For example, methods are being tested for detecting people at risk of diabetes with the aim of detecting and intervening early in the course of the disease (Barker et al., 2004), and for detecting individuals at high risk of breast cancer with the aim of providing some prophylactic treatment to prevent onset (Bouchard et al., 2004; Metcalfe, 2004; Prichard, Hill, Dijkstra, McDermott & O’Higgins, 2003). One strategy used in early detection within general medicine is genetic testing. With this technology, ‘at risk’ status can be diagnosed before any symptoms of disorder are present. This is possible even in utero or before implantation in the case of in vitro fertilisation. These techniques are possible for a range of diseases including achondroplasia, Huntington’s disease and Duchenne’s muscular dystrophy. But what of identifying individuals ‘at risk’ of psychotic disorders such as schizophrenia? There are no genetic tests for these disorders, nor even any aetiopathological diagnostic investigations. How can ‘at risk’ status for psychotic disorders be recognised? What are the implications of such ‘at risk diagnoses’ for treatment and prevention of disorder? A number of attempts have been made to define certain groups as ‘at risk’ either of schizophrenia or to psychotic disorders more generally. Different strategies have been used each with different meanings of ‘at risk’, including different implications for intervention. These will be briefly summarised, followed by a detailed discussion of our own approach.