LAYOUT DESIGNING AND OPTIMIZATION TECHNIQUES USED FOR DIFFERENT FULL ADDER TOPOLOGIES

In this paper VLSI layout designing and optimization techniques for different full adder topologies like Complementary MOSFET full adder (CMOS),Transmission gate full adder(TGA),Complementary Pass transistor Logic full adder(CPL) and Domino Full Adder has been discussed. Power consumption and propagation delay are the major issue for low voltage level circuit application designing in recent years. Full adders are the very important circuit element for calculating the basic four mathematical operations (addition, subtraction, multiplication and division) functions in Integrated circuits. In VLSI systems such as microprocessors and application specific DSP architecture are using different full adders for calculating mathematical operations. In this paper one bit full adders topologies has been used for analysis. The layout designing of the basic logic gates and different full adders is done using L-Edit v14.11 Tanner EDA tool using 0. 18μm technology node. The results shows that parameters like Power consumption and total propagation delay, for a particular aspect ratio the Transmission Gate Full adder consume less power and having less propagation delay. Keywords: layout designing, CMOS full Adder, Domino Logic Full adder, CPL full adder, Transmission Gate Full adder, L-Edit v14.11 Tanner EDA tool , 0. 18μm technology node. (1) INTRODUCTION Layout designing is the representation of an integrated circuit(IC) in terms of planar geometric shapes which correspond to the patterns of oxide or semiconductor layers and metal that makes up the components of the integrated circuits. To verify the safety of mechanical components and structures against collapse layout optimization technique is used. Layout optimization technique is applied to the problem of identifying the critical layout of slip-line discontinuities in a solid body. Layout can be characterized as the step in the design hierarchy where an electronic circuit is transferred to a silicon description (3). The layout designer is responsible for creating the patterns on every layer such that the resulting stacked structure defines the electronic switching devices (transistors) and the wiring that connects the switching devices together. To do this, we must first examine what constitutes a transistor, and then learn the characteristics of the conducting and insulating layers. These results in a set of rules that help guide the complex task of defining every part of every transistor correctly and then providing the metal wiring. Layout is performed entirely on a computer using layout editor. Every layer on the chip is patterned so that the resulting layers stack into three-dimensional structures that constitute the electronic network. A common grid is used throughout the process, and the screen portrays the entire design, but the patterning information for each layer is stored in a separate database. It is the responsibility of the layout designer to insure that the patterns follow the geometrical guidelines established for the fabrication process. Violating the rules may result in a non-functional chip. The layout tools also provide the ability to translate a set of patterns into the equivalent electronic circuit for comparison. The Layout Versus Schematic check insures that the patterns accurately represent the desired circuit. The tool set is used to extract a circuit schematic from the layout drawings. This provides a listing of every electronic element and the wiring details; the parasitic resistance and capacitance of every line can also be determined. The extracted file is used to simulate the electronic behavior of the silicon circuit (3). This simple overview shows that physical design is dependent on every level of the design hierarchy. The shapes and sizes of the material layers created in the layout process determine how much of the final electrical characteristics of the fabricated chip. It is therefore considered to be a critical part of the design hierarchy. The layout must pass a series of checks in a process, known as verification, for its correctness. The two most common checks in the verification process are Design Rule Checking (DRC) and Layout Versus Schematic (LVS). 1.1 Design Rule Check (DRC)