Miracle-dz/UniFAR-FTUs huggingface dataset:
VCO-ADC Resolution Enhancement Using Maximum Length Sequences

This paper shows how to enhance the resolution of a VCO based ADC by transforming a ring oscillator into a continuous-time maximum length sequence generator. The code spreading provided by the maximum length sequence can be decoded after sampling by a look up table. Compared to an M tap ring oscillator, an equivalent maximum length sequence generator enhances the resolution of the resulting ADC by a factor 2M/M. We derive the basic system analysis for this new ADC architecture and show a simulation example.
Microvascular Networks From Endothelial Cells and Mesenchymal Stromal Cells From Adipose Tissue and Bone Marrow: A Comparison

A promising approach to overcome hypoxic conditions in tissue engineered constructs is to use the potential of endothelial cells (EC) to form networks in vitro when co-cultured with a supporting cell type in a 3D environment. Adipose tissue-derived stromal cells (ASC) as well as bone marrow-derived stromal cells (BMSC) have been shown to support vessel formation of EC in vitro, but only very few studies compared the angiogenic potential of both cell types using the same model. Here, we aimed at investigating the ability of ASC and BMSC to induce network formation of EC in a co-culture model in fibrin. While vascular structures of BMSC and EC remained stable over the course of 3 weeks, ASC-EC co-cultures developed more junctions and higher network density within the same time frame. Both co-cultures showed positive staining for neural glial antigen 2 (NG2) and basal lamina proteins. This indicates that vessels matured and were surrounded by perivascular cells as well as matrix molecules involved in stabilization. Gene expression analysis revealed a significant increase of vascular endothelial growth factor (VEGF) expression in ASC-EC co-culture compared to BMSC-EC co-culture. These observations were donor-independent and highlight the importance of organotypic cell sources for vascular tissue engineering.
Image-based Natural Language Understanding Using 2D Convolutional Neural Networks

We propose a new approach to natural language understanding in which we consider the input text as an image and apply 2D Convolutional Neural Networks to learn the local and global semantics of the sentences from the variations ofthe visual patterns of words. Our approach demonstrates that it is possible to get semantically meaningful features from images with text without using optical character recognition and sequential processing pipelines, techniques that traditional Natural Language Understanding algorithms require. To validate our approach, we present results for two applications: text classification and dialog modeling. Using a 2D Convolutional Neural Network, we were able to outperform the state-of-art accuracy results of non-Latin alphabet-based text classification and achieved promising results for eight text classification datasets. Furthermore, our approach outperformed the memory networks when using out of vocabulary entities fromtask 4 of the bAbI dialog dataset.
Identifying Influential Nodes in Complex Networks via Semi-Local Centrality

Node influence refers to the ability of a node to disseminate information. The faster and wider the node spreads, the more inflential it is. With its great theoretical and practical significance, identifying influential nodes in complex networks becomes one of the most attractive research topics in recent years. Consequently, a variety of different methods, such as betweenness, closeness, and pagerank, have been proposed to identify influential nodes. However, most of the existing methods cannot lead to a tradeoff between the ranking accuracy and time complexity, which limits their application on many real-world complex networks. In this paper, we propose a novel and efficient ranking method named semi-local centrality, to evaluate the influence of nodes more accurately. The method performs random walk to collect the influential surround nodes which are used to evaluate the nodes' influence. We use susceptible-infected-recovered (SIR) model to evaluate the performance of our method. The experimental results on four real-world networks show that the proposed method can identify influential nodes more effectively compared with five state-of-the-art methods.
Design of a novel three-level voltage source converter for AC-DC-AC conversion

Power converter characterized with high controllability and has been widely popularized in smart grid. A novel three-level voltage source converter structured by H-Bridge for AC-DC-AC conversion is presented in this paper. The operation principle and control strategies of the proposed converter are investigated. A new simplified PWM strategy with redundant switching combination processor is adopted to control and balance the capacitors. Furthermore, the output performance of the proposed converter is evaluated by experimental results.
Semi-supervised Target-level Sentiment Analysis via Variational Autoencoder

Target-level aspect-based sentiment analysis (TABSA) is a long-standing challenge, which requires fine-grained semantical reasoning about a certain aspect. As manual annotation over the aspects is laborious and time-consuming, the amount of labeled data is limited for supervised learning. This paper proposes a semi-supervised method for the TABSA problem based on the Variational Autoencoder (VAE). VAE is a powerful deep generative model which models the latent distribution via variational inference. By disentangling the latent representation into the aspect-specific sentiment and the context, the method implicitly induces the underlying sentiment prediction for the unlabeled data, which then benefits the TABSA classifier. Our method is classifier-agnostic, i.e., the classifier is an independent module and various advanced supervised models can be integrated. Experimental results are obtained on the SemEval 2014 task 4 and show that our method is effective with four classical classifiers. The proposed method outperforms two general semi-supervised methods and achieves competitive performance.
1.3A,-2V Tolerant Solenoid Drivers for Pedestrian Protection in Active Hood Lift Systems

State of the art automotive systems demand smart system integration like the pre-crash systems and predictive driver assistance features to improve safety and reduce the injuries to pedestrians in addition to drivers and passengers in cars. The pedestrian protection has increased demand in all the cars. From a discrete solution in the last decade, state of the art systems, try to configure traditional Squib drivers to activate highly inductive solenoids to reduce injuries to pedestrians. These smart systems are the Active Hood Lift Systems. Pedestrian fatalities are mainly due to head injuries during a collision with a moving vehicle. To activate these solenoids a regulated current of 1.3A for 2ms is provided so that the rear part of the hood can be lifted to reduce pedestrian fatalities. Inductance range of solenoids is 3mH unlike the squib driver where the inductance is less than 100μH. When the driver turns OFF, the inductive flyback levels can be lower than ground for several hundreds of μs unlike squib drivers where this is only for tens of μs. To provide the free-wheeling current and limit the flyback level from flying far below ground, some solenoids have an in built Schottky diode. Other solutions use an external Schottky diode or integrated power diodes. This is expensive and the paper presented here presents a unique and cheaper solution where the free-wheeling current is provided by the driver itself by activating an on chip parasitic bipolar path. Flyback level is limited to −2V. This is verified in a 4 channel squib driver fabricated in a 40V, 0. 35μM BiCMOS process.
Versatile Framework for Power Delivery Exploration

Over the past decades, aggressive voltage scaling combined with increased power demands has placed stringent requirements on on-chip power quality. Unwanted voltage fluctuations and droops may cause a variety of issues, ranging from glitch power to device malfunction. If revealed at the later stages of the design process, mitigation techniques may become unbearably costly in both time and money. A framework for exploratory power delivery optimization is described to enhance the power delivery network during early stages of the design process in accordance with design specifications. The power delivery design process is converted into a constrained minimization problem, consisting of design metrics combined into objective and constraint functions. The framework supports the optimization of the power network characteristics while considering external, non-electrical design specifications, such as cost and area, providing a comprehensive network analysis capability. In one case study, a 15% reduction in decoupling capacitor placement along with a 38.6% reduction in power consumption is achieved while satisfying performance and power quality constraints.
Flexible Hybrid Electronics: Review and Challenges

Flexible Hybrid Electronics (FHE), heterogeneous electronics embodying both conventional silicon electronics and printed electronics, is an emerging technology with huge market potential as it is advantageous compared to conventional silicon electronics and the emerging Printed Electronics — FHE features better mechanical flexibility/conformability and lower cost compared to conventional silicon electronics, and higher performance compared to Printed Electronics. In this paper, a comprehensive literature view on FHE is provided, including the state-of-the-art FHE development, FHE supply chains, and design challenges.
Designing and Testing a Model of some Antecedents of Subjective Career Success

The purpose of this study was designing and testing a model of some antecedents of subjective career success. The participants of this study consisted of 230 employees of Khuzestan Water and Power Organization, who were selected by stratified random sampling method. The instruments used in the study were Work Climate Questionnaire, Perceived Competence Scale, Basic Need Satisfaction at Work Scale, Work Extrinsic and Intrinsic Motivation Scale, Career Satisfaction Scale, Perceived P-V Fit Scale, & Career commitment Scale. Structural equation modeling (SEM) through AMOS-21 was used for data analysis. Bootstrapping procedure also used to determine the significance of the indirect effects. The results showed that the proposed model fitted the data properly. Findings showed that work autonomy support and work competency support had significant direct effects on need satisfaction, self-determined motivation, and career success (career commitment, career satisfaction, and perceived p-v fit). Results also supported the meditating role of need satisfaction and self-determined motivation in these relationships. Based on our findings, SDT is a useful framework for predicting subjective career success in the form of career satisfaction, career commitment, and perceived p-v fit.
A 3D Tiled Low Power Accelerator for Convolutional Neural Network

It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 × 14 × 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.
A Convolutional Accelerator for Neural Networks With Binary Weights

Parallel processors and GP-GPUs have been routinely used in the past to perform the computations of convolutional neural networks (CNNs). However, their large power consumption has pushed researchers towards application-specific integrated circuits and on-chip accelerators implement neural networks. Nevertheless, within the Internet of Things (IoT) scenario, even these accelerators fail to meet the power and latency constraints. To address this issue, binary-weight networks were introduced, where weights are constrained to −1 and 1. Therefore, these networks facilitate hardware implementation of neural networks by replacing multiply-and-accumulate units with simple accumulators, as well as reducing the weight storage. In this paper, we introduce a convolutional accelerator for binary-weight neural networks. The proposed architecture only consumes 128 mW at a frequency of 200 MHz and occupies 1.2 mm2 when synthesized in TSMC 65 nm CMOS technology. Moreover, it achieves a high area-efficiency of 176 Gops/MGC and performance efficiency of 89%, outperforming the state-of-the-art architecture for binary-weight networks by 1.8× and 3.2×, respectively.
Noise Constrained Optimum Selection of Supply Voltage for IoT Applications

An optimization technique is proposed to set the supply voltage of an integrated circuit for a given range of threshold voltages. The algorithm accounts for the variations in maximum operating frequency f<sub>max</sub>, noise margins, and threshold voltage. The algorithmically determined supply and threshold voltages are compared with SPICE simulation for a 130 nm CMOS technology, where per cent error of up to 14% and 8% are observed for, respectively, the average noise margins NM<sub>avg</sub> and f<sub>max</sub> as compared to target circuit specifications for noise margin and frequency. The evaluated ranges of the supply and threshold voltages are, respectively, 200 mV ≤ V<sub>dd</sub> ≤ 1200 mV and 250 mV ≤ V<sub>t</sub> ≤ 700 mV. The technique is applied to both a 130 nm and 45 nm CMOS technology and results of noise margin and frequency are compared through SPICE simulation. The 45 nm technology node exhibits variation of up to 0.89× and 4.3× in, respectively, NM<sub>avg</sub> and f<sub>max</sub> as compared to an inverter in a 130 nm technology.
Masking Effects Based Rate Control Scheme for High Efficiency Video Coding

This paper presents a masking effects based rate control scheme for high efficiency video coding (HEVC). Rate control is regarded as a very effective tool to improve the performance of video coding under the limited bandwidth. However, the state-of-the-art rate control algorithm based on R-X model ignores the characteristics of human visual system (HVS), which leads to poor performance in subjective quality. Moreover, some structural similarity (SSIM) or saliency based perceptual rate control algorithms only consider spatial characteristics. Since spatial and temporal visual masking effects can better reflect the characteristics of HVS, in this paper masking effects based perceptual factor for coding tree unit (CTU) is proposed, which takes both texture complexity and motion information into account. Then the proposed perceptual factor is utilized to guide bit allocation in CTU-level rate control. Experimental results show that the proposed scheme can effectively improve the coding performance compared with the R-λ algorithm.
A Study of Three-Phase DC-DC Boost Converters

Three-phase DC-DC boost converters are attractive in applications where the input is a low voltage DC source, such as in renewable energy systems that are fed by solar cells. In spite of their advantageous features, they are not, however, as well known as conventional single-phase bridge topologies. In this paper, a comparison of three three-phase DC-DC boost converters is made, including a new converter proposed by the authors. Guidelines as to which converter is better suited for particular applications are derived and presented.
Methodology Towards Sub-ppm Testing of Analog and Mixed-Signal ICs for Cyber-Physical Systems

Guaranteeing correct and reliable cyber-physical systems requires testing of analog/mixed-signal ICs towards low defect escape rates, below the ppm level. It also requires guaranteeing correct functioning over the product lifetime. However, there are not yet industry-wide automated tools that can generate adequate tests to this end for analog/mixed-signal ICs, like it is currently the case with digital ICs. This paper presents different methods and algorithms that target decreasing defect test escapes in analog/mixed-signal ICs. These methods are based on structural testing for defects, they use fault analysis tools for escape rate analysis and employ DfT structures to increase test coverage, which reduces test escape rate. Furthermore, these structures activate possible latent defect, that may pose threats during the lifetime of integrated circuits.
Evaluation of the Anonymizability of Complex Networks

Privacy protection is one of the greatest challenges in the big-data era. A traditional solution to this problem is to remove the identity information of subjects while still exposing useful data content for further needs. However, complex networks such as online social networks, recommendation systems, instant online communication records, etc., in which network properties form a unique category of identity indicators, pose a new level of challenge to traditional data anonymization methods. In this paper, we will address this problem by first systematically evaluating the diversity of a unique class of identifiers of nodes, i.e., their topological properties, of which the differentiability indicates to what extend the nodes can be anonymized even with their name tags removed. In fact, numerous of structure-altering based anonymization algorithms for complex networks have been proposed. However, while the network structure is altered from heterogeneous to homogenous to protect user privacy, the usability of data also decreases therewith. In the latter part of this paper, we will establish a boundary between anonymizability and usability of complex network data from a network null model perspective. Specifically, different levels of data usability are defined by the preservation of the first, second and higher order ego-network structure of nodes while the boundary is measured by the success rate of random rewiring of edges in the construction of null models. In brief, our research provided a systematical evaluation of the intrinsic anonymity of complex networks and established a measure of the boundary between the anonymizability and usability of data from a network perspective.
Can SMASH Smash MASH?

In this paper, we present a thorough discussion and comparison between the single loop delta-sigma modulator (DMS), the multi-stage noise shaping (MASH) DSM and the sturdy MASH (SMASH) DSM focusing on circuit sensitivity and stability. It shows that the SMASH is least sensitive to the circuit non-idealities among all and its stability is in between the others.
A 0.78 mW Low-Power 4.02 High-Compression Ratio Less than 10−6 BER Error-Tolerant Lossless Image Compression Hardware for Wireless Capsule Endoscopy System

A 0.78mW low power error-tolerant lossless image compressor for a wireless capsule endoscopy system is proposed. In order to achieve high compression ratio of 4.02, this work proposes zero-skipping coding and mode switcher architecture that utilize high image sparsity on endoscopy systems. In addition, a Forward Error Correction (FEC) block is proposed to achieve low Bit-error Rate (BER) under 10−6, the integration error from prediction-based and variable length coding. The proposed error-tolerant lossless image compression hardware is implemented using 1P6M 65nm CMOS process and consumes only 0.78mW power at 40MHz with 2 fps throughput on VGA resolution image, and it is evaluated with real capsule endoscope images.
An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing

JPEG compression is an important part in low-power multimedia applications. This paper proposes an approach that leverages the error resilience of JPEG for different energy budgets. We select and train neural networks to approximate DCT and quantization code regions in JPEG. Then we design an architecture called reconfigurable neural unit (RNU) to accelerate trained neural networks which replace original codes. In addition, some architecture innovations are proposed to make our JPEG encoder works efficiently in near-threshold voltage region. This JPEG encoder synthesized with a 40nm CMOS technology, is able to operate at 40MHz for a 0.6V supply voltage. Results show up to 5.0 × energy reduction with 2.5 × performance degradation when compared to using a 1.0V nominal supply voltage.
Live Demonstration: Front and Back Illuminated Dynamic and Active Pixel Vision Sensors Comparison

The demonstration shows the differences between two novel Dynamic and Active Pixel Vision Sensors (DAVIS). While both sensors are based on the same circuits and have the same resolution (346×260), they differ in their manufacturing. The first sensor is a DAVIS with standard Front Side Illuminated (FSI) technology and the second sensor is the first Back Side Illuminated (BSI) DAVIS sensor.
Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics

Memristive biosensors have been proved as excellent candidates for ultrasensitive biosensing. In this work, a novel portable bio-detection system based on memristive biosensors is designed, developed and tested for providing a significantly fast, automatic and simultaneous sensing output of multiple memristive biosensors on a single chip. The suggested compact and independent bio-sensing prototype is achieved through the realization of an electronic board designed for addressing the specifications of the memristive biosensor signal acquisition. Memristive bio-sensing-chips are specially designed and fabricated as well. The system was tested for successfully sensing of Prostate Specific Antigen, one of the main biomarkers of prostate cancer, at fM concentrations. Overall, this novel scheme resembles to a memristive-biosensing-kit approach, paving the way for fast and ultrasensitive PoC (point-of-care) devices.
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM

While the spin transfer torque magnetic memory (STT-MRAM) suffers from its shortcomings such as high write power, slow write operation and reliability issues, spin orbit torque magnetic random access memory (SOT-MRAM) can offer relatively faster write operation with low power based on giant spin hall effect. Although SOT-MRAM provides low power write operation, to meet the power level of current embedded memories, significant reduction of write power is highly required. In this paper, we present a low power write technique for SOT-MRAM. In order to prevent redundant write operation, read-compare-write operation is adopted. As a result, only the SOT cells having different data are written, and write power is saved in the cells with the same data. For further optimization, bitline switching scheme is used to reduce bitline and source line swing in write operation. The negative bitline scheme is also exploited by re-cycling the charge from read operation to increase write current. Simulation results using 65nm CMOS technology show that up to 40.1 % of write energy can be saved compared to the conventional unnecessary write avoidance approach.