Miracle-dz/UniFAR-FTUs huggingface dataset:
A Comprehensive Method to Taxonomize Mechanical Energy Harvesting Technologies

Traditional industry is experiencing a worldwide development with Industry 4.0. Wireless sensor networks (WSNs) have a main role in this revolution as an essential part of data acquisition. The way in which WSNs are powered is one of the main challenges to face if Industry wants to achieve the digital transformation. Energy harvesting technologies are one of the possible solutions to this challenge. The main purpose of this paper is to present a novel method to taxonomize knowledge in the field of mechanical energy harvesting in order to enhance the use of energy harvesting technologies for industrial applications. Additionally, the taxonomy allows to identify upcoming challenges for research purposes.
A High Speed True Random Number Generator with Cellular Automata with Random Memory

Cellular Automata with Random Memory (CARM) is a recently proposed Cellular Automata (CA) model with its digital implementation which is designed by the chain of logic gates (delay line). CARM models which are able to magnify physical noise in its delay line are a good candidate to design True Random Number Generator (TRNG). In this paper, a novel TRNG based on CARM is proposed and implemented on a FPGA. The proposed TRNG passes all the tests given by National Institute of Standards and Technology (NIST) without any post-processing. Furthermore, the implementation of proposed TRNG which ensures the 1Gbit per-second-bit-rate at 100 Mhz input clock, is compared with the other RNGs which were also implemented on FPGA.
Brain-on-a chip technologies for investigating neuronal diseases: Toward precision medicine applications

Neurodevelopmental disorders (NDDs) are a collection of heterogeneous syndromes involving disruption of early neurobiological development. While the identification of disease genes has great benefits for diagnostic and prognostic purposes, for the vast majority of these genes there is little knowledge about neurobiological mechanisms that they control at the cellular and network level. Recent studies demonstrate that NDDs are "diseases of the synapse". Synaptic malfunction can severely affect network connectivity and dynamic. Understanding the neural circuit basis of NDDs is therefore imperial for a better understanding of these disorders. Kleefstra syndrome (KS) is a NDD characterized by moderate to severe intellectual disability, childhood hypotonia, and facial dysmorphism associated with genes deficiency. Here, we studied how KS genes-deficiency affects neuronal network maturation using dissociated neuronal cultures (i.e. from rodent or KS patient induced pluripotent stem cells). Using micro-electrode arrays technology we characterized the electrophysiological activity of control and KS genes-deficient neuronal networks. We showed that KS genes-deficient neuronal networks exhibited different pattern of synchronous activity compared to control condition. In particular, KS genes-deficiency induced an inappropriate network organization and irregular pattern of activity, indicating that KS genes are required for proper network formation. The neuronal network phenotype found here, provides for relevant future directions in the elucidation of pathophysiology in KS.
What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?

A novice continuous-time delta-sigma designer is faced with an admittedly complex maze of possible design choices. The right architecture often determines how efficiently the modulator can be implemented. This paper critically examines various popular delta-sigma architectures. It concludes that a single-bit modulator with FIR feedback is a prime candidate that enables a power-efficient implementation for a variety of specifications. To support this thesis, measurement results of an audio delta-sigma modulator, designed in a 65 nm CMOS process are given. The modulator, which incorporates FIR feedback and chopping to reduce 1/f noise, achieves 98.6 dB peak SNDR in a 24 kHz bandwidth and consumes only 260 μ W from a 1.2 V supply.
NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines

The 3D design of SRAM LLCs has made the thermal problem, even more, sever and therefore incurs more leakage energy consumption compared to conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose a runtime cache architecture called NIZCache. The core idea of NIZCache is to use the non-uniform distribution of the accesses, invalid lines, and zero-value lines in banks of last level cache for decreasing both dynamic and leakage energy. The proposed architecture that is based on non-uniform cache architectures (NUCA) disables cache banks that have low accesses and high invalid and zero lines and leads to high energy-efficiency. The Experimental results show that the proposed method improves the energy-delay product by about 17% on average under PARSEC benchmarks compared to previous work.
Library Optimization for Near-Threshold Voltage Design

A circuit operating at near-threshold voltage (NTV) dissipates much less energy, but it suffers from significant increase in cell delay as well as delay variation. In this paper, we address two library optimization methods for NTV design: (1) transistor lengths are increased to benefit from reverse short channel effect (RSCE), and (2) each flip-flop is optimized into a few versions with different timing parameters by redistributing clock signals to clocked transistors. Flip-flops are remapped to optimized ones via integer linear programming (ILP); a goal is to minimize total negative slack (TNS) under hold time constraints, which is a critical concern in NTV design. Experiments demonstrate that our proposed method achieves 22%, 56%, and 13% reductions in clock period, energy dissipation, and circuit area, respectively, on average of a few test circuits in 55-nm technology.
Double Standards in Frontline Decision Making: A Theoretical and Empirical Exploration

Drawing on status characteristics and double standards theory, this study explores how social categories may affect the standards tax officials use in evaluating citizen-clients’ trustworthiness, leading to differential evaluation. Whereas the street-level bureaucracy literature mainly focuses on the direct effect of social categories on officials’ judgments, this study shows how stereotyping in the public encounter could be much subtler and more pervasive than is hitherto studied. Based on semistructured interviews containing 40 stories of tax officials who inspect entrepreneurs’ tax returns, this study suggests that similar signals may indeed be interpreted differently for different social groups.
Leveraging eBPF for programmable network functions with IPv6 segment routing

With the advent of Software Defined Networks (SDN), Network Function Virtualisation (NFV) or Service Function Chaining (SFC), operators expect networks to support flexible services beyond the mere forwarding of packets. The network programmability framework which is being developed within the IETF by leveraging IPv6 Segment Routing enables the realisation of in-network functions. In this paper, we demonstrate that this vision of in-network programmability can be realised. By leveraging the eBPF support in the Linux kernel, we implement a flexible framework that allows network operators to encode their own network functions as eBPF code that is automatically executed while processing specific packets. Our lab measurements indicate that the overhead of calling such eBPF functions remains acceptable. Thanks to eBPF, operators can implement a variety of network functions. We describe the architecture of our implementation in the Linux kernel. This extension has been released with Linux 4.18. We illustrate the flexibility of our approach with three different use cases: delay measurements, hybrid networks and network discovery. Our lab measurements also indicate that the performance penalty of running eBPF network functions on Linux routers does not incur a significant overhead.
Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation

There is growing demand for circuits that can provide ever greater performance from a minimal power budget. Example applications include wireless sensor nodes, mobile devices, and biomedical implants. High speed clock circuits are an integral part of such systems, playing roles such as providing digital processor clocks, or generating wireless carrier signals; this clock generation can often take a large part of a system's power budget. Common techniques to reduce power consumption generally involve reducing the clock speed, and/or complex designs using a large circuit area. This paper proposes an alternative method of clock generation based on driving a high-Q resonator with a periodic chain of impulses. In this way, power consumption is reduced when compared to traditional resonator based designs; this power reduction comes at the cost of increased period jitter. A circuit was designed and laid out in 0. 18μm CMOS, and was simulated in order to test the technique. Simulation results suggest that the circuit can achieve a FoM of 4.89GHz/mW, with a peak period jitter of 10.2ps at 2.015GHz, using a model resonator with a Q-factor of 126.
Design and Implementation of a Smart Headband for Epileptic Seizure Detection and Its Verification Using Clinical Database

Epilepsy is a common neural disorder disease; about 0.5% of the global population has epilepsy [1]. Most patients take antiepileptic drugs to reduce their seizures. Among them, nearly one-third of the patients are drug-resistant epilepsy. The alternative treatment is the resection surgery of removing the epileptogenic zone. However, all above patients will still suffer seizures occasionally, which will influence the patients' quality-of-life, and further introduce danger and inconvenience to patients and people around. This paper presents the design and development of the smart headband for epileptic seizure detection. The headband consists of a fabric headband with flexible print circuit (FPC) inside and fabric electrodes on it. The whole system includes the following circuits: an analog front-end circuitry, an epileptic seizure detection tag (ESDT), and a Bluetooth Low Power (BLE) chip. The result of designed circuits yields a compact and low-power design of smart headband for epileptic seizure detection which is suitable for wearable usage. The epileptic seizure detection algorithm is validated by Children's Hospital Boston-MIT (CHB-MIT) EEG database [2].
A Sinusoidal Signal Generator Using a Constant Gain Finite Impulse Response (FIR) Filter for Electrical Bioimpedance Spectroscopy

We propose a sinusoidal signal generator (SSG) using a constant gain finite impulse response (FIR) filter for measuring impedance spectrum from 1-kHz to 2.048-MHz range. A simple digital-to-analog converter (DAC) using eight unit resistors generates differential stepwise signals and the FIR filter attenuates close-in harmonics of the stepwise signals using its inherent nulls. A continuous-time (CT) low-pass filter (LPF) attenuates high-order harmonics of the FIR filter's output. The fabricated SSG achieved the total harmonic distortion less than 0.2% up to 10th harmonic using a simple DAC and low oversampling ratio of 8. Since our SSG adopts a passive type of CT LPF and a constant gain FIR filter which does not require any gain compensation circuit, the fabricated SSG consumed 5.1 mW which is about 30% of our previous SSG.
On the Use of Approximate Multipliers in LMS Adaptive Filters

Approximate computing relaxes algorithm precision constraints to improve digital circuit performance. Adaptive filters based on least-mean-square (LMS) algorithm constitute a standard in many DSP applications. The LMS algorithm, being an approximation of the Wiener filter, is inherently imprecise, and constitutes a fertile ground to employ approximate hardware techniques with the additional challenge related to the presence of a feedback path for coefficients update. In this paper, approximate LMS adaptive filters are explored for the first time, by employing approximate multipliers. A system identification scenario is adopted to assess the algorithm behavior. The analysis reveals that the choice of the approximate multiplier topology should be carefully examined, otherwise the stability and convergence performance of the algorithm can be compromised. We propose a novel approximate multiplier able to reduce the power dissipation in adaptive LMS filters up to 29% with tolerable convergence error degradation.
Analysis of Coil Misalignment Issue in Resonance-based Wireless Power Transmission System for Implantable Biomedical Applications

In modern medicine, the batteries in implantable devices are replaced with wireless power transmission (WPT) technology. The resonance-based WPT method is widely used in biomedical implantation applications as it enables the mid-field operation within the human body. The shape and misalignment of the implantable coil due to human breathing activity and body moments are the main obstacles to achieve the high power transfer efficiency. In this paper, we designed, optimized, and analyzed the spherical and circular shaped implantable coils to mitigate the misalignment issue. Results show that the spherical shaped implantable coil has superior performance under misalignment situations when compared to the circular shaped implantable coil.
A Step-Up Charge Pump with High Integration and Full-Coverage Voltage Conversion Ratio

In this work, a feasible charge pump structure with complete voltage conversion ratios (VCRs) of 1–2n is proposed. For a charge pump with off-chip capacitors for current-drive-capacity enhancement, some capacitors can be removed directly and the one in the following stage is utilized for charge storage. The proposed scheme only requires n flying capacitors and can achieve maximum integration. Based on 0.25 μm 5 V/12 V/24 V process, a three-stage topology has been verified by simulation as an example. It has been operated with VCRs of 1×–8× with only three flying capacitors. It has supplied at least 90 μA current with a maximum current of 3.33 mA. Meanwhile, a peak power efficiency of 84% has been achieved.
Paraoxonase 1 activities and its gene promoter single nucleotide polymorphisms (-108, -126, and -162) in diabetes mellitus

Background Paraoxonase 1 (PON1) enzyme is known enzyme with, aryl esterase, phosphatase, peroxidase, and lactonase activities. According to some studies, the activity of PON1 enzyme is decreased in type 2 diabetic patients. We analyzed the enzyme activity and its single nucleotide polymorphisms (SNPs) distribution on promoter regions (-108, -126, and -162) in type 2 diabetic patients compared with non-diabetic individuals to reveal the likely relationship between PON1 activity and its gene promoter polymorphisms. Methods On the whole, 98 diabetic and 104 non-diabetic individuals were examined in this study. The enzyme activity and the genotypes were studied using spectrophotometry, real-time PCR-HRM, and sequencing techniques, respectively. Results There was no meaningful difference in enzyme activity between two under-studied groups (P.V = 0.671). Moreover, no meaningful difference was also seen between two groups in terms of the frequency of polymorphism -108 (P.V = 0.277). The frequencies of SNPs -126 and -162, however, showed a meaningful difference between two groups (P.V = 0.000 and P.V = 0.017, respectively). Conclusions We indicated PON1 activity could be similar in DM-2 patients and non-DM-2 individuals. The significant role of SNP -108 in PON1 activity in DM-2 patients compared with non-DM-2 individuals was confirmed in the study too. On the other hand, the role of -162 and -126 SNPs in causing diabetes cannot be easily overlook because of a meaningful difference of their distribution in understudied groups. However, they may be attributed to DM-2-associated genes.
Smart Wearable Wristband for EMG based Gesture Recognition Powered by Solar Energy Harvester

With the recent improvement of flexible electronics, wearable systems are becoming more and more unobtrusive and comfortable, pervading fitness and health-care applications. Wearable devices allow non-invasive monitoring of vital signs and physiological parameters, enabling advanced Human Machine Interaction (HMI) as well. On the other hand, battery lifetime remains a challenge especially when they are equipped with bio-medical sensors and not used as simple data logger. In this paper, we present a flexible wristband for EMG gesture recognition, designed on a flexible Printed Circuit Board (PCB) strip and powered by a small form-factor flexible solar energy panel. The proposed wristband executes a Support Vector Machine (SVM) algorithm reaching 94.02 % accuracy in recognition of 5 hand gestures. The system targets healthcare and HMI applications, and can be used to monitor patients during rehabilitation from stroke and neural traumas as well as to enable a simple gesture control interface (e.g. for smart-watches). Experimental results show the accuracy achieved by the algorithm and the lifetime of the device. By virtue of the low power consumption of the proposed solution and the on-board processing that limits the radio activity, the wristband achieves more than 500 hours with a single 200 mAh battery, and perpetual work with a small-form factor flexible solar panel.
Layout-dependent effects aware gm/iD-based many-objective sizing optimization for analog integrated circuits

Layout-dependent effects (LDEs) as one type of second-order effects in addition to parasitics, the primary second-order effect, are considered in our proposed two-stage hybrid sizing methodology for analog circuits. The first-stage sizing optimization is realized by using gm/ID-based symbolic modeling and nonlinear programming. A many-objective evolutionary algorithm based sizing refiner works for the second-stage optimization. MOSFET characterization and considerations of intrinsic and interconnect parasitics as well as LDEs are addressed progressively throughout the proposed hybrid sizing flow. Finally, the experimental results demonstrate high efficacy of our proposed gm/ID-based parasitic-aware and LDE-aware two-stage sizing methodology.
An Approximated Verilog-A Model for Memristive Devices

This paper presents an approximated linear model for memristive devices. Because of the abundance of technology solutions, the many models so far presented, more or less complicated, are generally technology-specific and this represents a problem for resistive memory designers who need to test the analog and digital periphery without affecting the computational costs. For this reason, an approximated model, formally derived from the traditional one, has been conceived and tested with a Verilog-A implementation. Based on the linear model, our approximation preserves a good fit with the experimental data, ensuring scalability and generality. Moreover, very important for memory applications, the computational costs and resources are considerably reduced. The model validity has been proven in some design cases, while model parameters have been extracted from measurements carried out on devices implemented in a 250-nm BiCMOS technology.
Design and Application of an Approximate 2-D Convolver with Error Compensation

This paper proposes an error compensation scheme of two-dimensional (2D) convolver in which both approximate circuit- and algorithm-level techniques are utilized in the design. Truncation and voltage scaling are used as circuit techniques, while bit-width reduction is utilized at the algorithm level. These different techniques are related to the configuration of the convolver by which its operation can be configured to meet different and often contrasting figures of merit. An extensive evaluation of different error metrics is performed. An error analysis is also presented to substantiate the simulation results; an error compensation scheme is introduced to remedy a loss of accuracy in computation. Convolution for image processing is treated in detail to show the effectiveness of the proposed approach. The design, the analysis and the simulation results show that the approximate techniques utilized in the inexact convolver can operate in synergy.
Design and implementation of passive memristor emulators using a charge-flux approach

In this work we present a methodology to design circuits emulating memristive behaviour. This methodology is based initially on a charge and flux description of the system, and the equations are decomposed into blocks that can be implemented using very simple CMOS topologies. As an example, we implement a simple memristor with long term memory, showing that the resulting system behaves as expected using either voltage ramps or pulses as the driving signals.
Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS

This paper presents a novel low cost and double node upset (DNU) online self-recoverable latch design using radiation hardening by design (RHBD) technology. The latch mainly consists of 8 interlocked input-split inverters. Since all internal nodes are interlocked, if any of the possible node pairs occurs a DNU, the latch can restore back. Simulation results have demonstrated the DNU online self-recoverability and also demonstrated that the proposed latch design saves 71.68% transmission delay, 72.92% power dissipation and 93.69% comprehensive delay-power-area product (DPAP) on average, compared with the up-to-date DNU online self-recoverable latch designs.
A Ka-band Phase Shifting Low Noise Amplifier with Gain Error Compensation for 5G RF beam forming array using 14nm FinFET CMOS

A Ka-band phase shifting low noise amplifier (LNA) using stacked-FET structure in 14nm FinFET CMOS is presented for 5G beam forming array. The gate capacitance of the middle CG-FET is adjusted for phase variation. The additionally stacked CG-FET provides low load impedance to the phase shifting CG-FET for minimizing gain error. Moreover, the higher output isolation for stable phase shifting and power gain can be achieved by additional CG-FET stacking. The designed phase shifting low noise amplifier shows a gain of 15 dB and noise figure of 5 dB with less than 2 dB gain variation while the phase shifting can be controlled up to 22.5 degrees from 30 GHz to 40 GHz. The use of the developed phase shifting LNA can give a better phase and gain performance resulting in the improved array factor in the 5G beam-forming array network.
Steady-State Analysis of Electronic Electrostatic Generators

This paper presents a systematic procedure for the formulation of the equations required for the analysis of electrostatic generators used for energy harvesting, considering specially the behavior when operating at steady state connected to a DC/DC converter. The generators are considered composed of variable and fixed capacitors, diodes, a switch representing the converter, and may include voltage sources too. The required equations are obtained in matrix form, and usually can be solved algebraically. Examples are then presented, with the application of the procedure in the analysis of several structures, most not previously analyzed in detail.