Power Estimation and Minimization of Digital Signal Processing Systems

Power dissipation has become a critical design concern in recent years driven by the emergence of mobile applications. Reliability concerns and packaging costs have made power optimization relevant even for tethered applications. Digital Signal Processing Systems are used in many applications where low-power dissipation is an important goal. In this thesis, we present techniques to estimate and reduce power dissipation in digital processing systems. We first present a technique to estimate the power dissipation in filters, which are used extensively in DSP applications. We present a novel methodology to determine the average number of transitions in a signal from its word-level statistical description. The proposed methodology employs: (1) high-level signal statistics, (2) a statistical signal generation model, and (3) the signal encoding (or number representation) to estimate the transition activity for that signal. The proposed method is employed in estimation of transition activity in DSP hardware. After presenting power estimation techniques for filters, we present two techniques to reduce the power dissipation in digital filters. We first present decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in digital filters by coding the filter coefficients and/or the input. The DECOR transform is suited for narrow-band filters because there is significant correlation between adjacent coefficients. The second power reduction technique for digital filters is applicable to Distributed Arithmetic (DA) architectures. In a DA architecture, a memory is employed to store linear combinations of coefficients. The probability distribution of addresses to the memory is usually not uniform because of temporal correlation in the input. We present a rule governing this probability distribution and use it to partition the memory such that the most frequently accessed locations are stored in the smallest memory. After focusing on reducing power dissipation in processing blocks (filters) we concentrate next on reducing the power dissipation in busses that transmit data between the processing blocks. Transitions on high capacitance busses result in considerable system power dissipation. We present practical novel encoding schemes to reduce transition activity. The encoding schemes are developed via a communication-theoretic approach, whereby a data source is passed through a decorrelating function followed by a variant of entropy coding function which reduces the transition activity. We also present fundamental bounds on the activity reduction capability of any encoding scheme for a given source, and (2) practical novel encoding schemes that approach these bounds. The fundamental bounds in (1) are obtained via an information-theoretic approach where a signal x(n) with entropy rate H is coded with R bits per sample on average. We have so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for dual-output domino logic that reduces area, dock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output.