A Survey of Techniques for Mapping and Scheduling Applications to Network on Chip Systems

Network on Chip (NoC) architectures with regular topology provide scalable platforms for designing Systems on Chip (SoC) with large number of cores. Developing products and applications using a NoC architecture offers many challenges and opportunities. Many tools will be required to develop a NoC architecture for a specific application. A tool which can map an application or a set of applications to a given NoC architecture will be essential. In this report we survey the techniques for mapping and scheduling concurrent applications to NoC platforms. NoC platforms are basically a special class of Multiprocessor Embedded Systems (MPES). Conventional MPES architectures are mostly bus-based systems which have problems of scalability and reusability. There has been a lot of research on MPES development including research on mapping and scheduling applications on them. NoC researchers can easily adapt many of the results, techniques and ideas from MPES for NoC tool development. Therefore, we also include a survey of techniques for mapping and scheduling applications to bus-based MPES. The parameter which affects the performance of an application running on a NoC platform is the communication delay for moving data from one IP core to another. This delay is affected by, besides other factors, the relative positions of IP cores on the NoC platform. This step in NoC development is generally referred as Network Assignment. We first classify the mapping and scheduling approaches for NoC available in literature according to whether or not the approach combine mapping and scheduling of computations with communication mapping and scheduling. Similarly we classify mapping and scheduling approaches for bus-based MPES into three categories according to their focus on energy minimization, handling soft real time constraints or memory awareness. NoC and MPES share the same design goals and constraints, which mainly refer to reducing energy consumption, verifying real time constraints and minimizing on-chip memory. Off-line mapping and scheduling is usually recommended for embedded systems. Therefore all NoC and bus-based MPES approaches in this paper with a single exception are performed offline. Non-pre-emptive scheduling with dynamic or static priorities is applied in the surveyed methodologies. All but one Voltage Selection approaches surveyed apply Dynamic Voltage Selection. School of Engineering Mapping and Scheduling to NoC Jönköping University Mapping and scheduling are known to be computationally hard problems. A large range of exact and approximate optimization algorithms have been proposed by different groups for solving these problems. The methods include Branch-and–Bound (BB), constructive and transformative heuristics such as List Scheduling (LS), Genetic Algorithms (GA) and various types of Mathematical Programming algorithms. We have also carried out a comparison between presented approaches based on the achievement of their design goals. Communication issue is highlighted for NoC approaches verifying hard deadlines, while Voltage Selection is stressed for approaches minimizing energy consumption. The comparison lists the strong points and weak points of various approaches and identifies the best approach for a particular design objective. The survey points to many problems for future research. There is a scope for improving the model for estimation of communication delay in every approach. Our study shows that no research group has considered dynamic mapping and scheduling techniques for NoC platforms. Also no research group has yet reported techniques for mapping and scheduling for a NoC platform with topology other than a two-dimensional mesh topology.