Miracle-dz/UniFAR-FTUs huggingface dataset:
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing

Compact and energy-efficient computing systems may advantageously harness nanoscale sources of randomness, such as superparamagnetic tunnel junctions (SMTJs). The collective behavior resulting from the coupling between such SMTJs could be helpful in the hardware implementation of cognitive computing systems where randomness is a low-cost way to encode and explore available information states. Using a simple linear circuit, we mutually couple two such perpendicular SMTJs through the stochastic jumps of their binary resistive states. This approach led to the largest mutual SMTJ coupling strength reported in the literature at this stage. This first demonstration opens a promising path for implementing larger networks of coupled SMTJs that, using simple connectivity schemes, could emulate energy-based models such as Boltzmann and Ising machines or stochastic-based brain-inspired neural networks. In the case of SMTJs, thermal fluctuations at room temperature are the source of randomness that makes the magnetization switch randomly between two states, leading to random changes in the voltages across the two SMTJs. As a result of this voltage change, the magnetization switching probability of coupled SMTJs is, in turn, modified. Using this mechanism, we found a nearly 36 % cross-correlation between the states of the two coupled nanodevices. We use a generalized Néel-Brown model applied to individual SMTJs reproducing the positive (attractive) coupling strength of the coupled SMTJs with a four-state Markov model. Based on this model, we predict the external conditions (applied magnetic field, electrical current) and SMTJ features needed to obtain negative (repulsive) coupling strength.
RL-Ripper:: A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques

Physical designers have been using heuristics to solve challenging problems in routing. However, these heuristic solutions are not adaptable to the ever-changing fabrication demands and their effectiveness is limited by the experience and creativity of the designer. Reinforcement learning is an effective method to tackle sequential optimization problems due to its ability to adapt and learn through trial and error, creating policies that can handle complex tasks. This study presents an RL framework for global routing that incorporates a self-learning model called RL-Ripper. The primary function of RL-Ripper is to identify the best nets to rip to decrease the number of total short violations. In this work, the final global routing results are evaluated against CUGR, a state-of-the-art global router, using the ISPD 2018 benchmarks. The proposed RL-Ripper framework's approach can reduce the short violations compared to CUGR. Moreover, the RL-Ripper reduced the total number of short violations after the first iteration of detailed routing over the baseline while being on par with the wirelength, VIA, and runtime. The major impact of the proposed framework is to provide a novel learning-based approach to global routing that can be replicated for newer technologies.
Research on Export Prediction Model Based on Machine Learning: Application of China's Agricultural Products Export

In international trade, the detection of Agricultural Products is very strict, there are many detection indicators and high requirements. Under the new situation, superimposed epidemic factors and international food security are facing challenges such as resources and environment. As one of the major agricultural countries, China exports a large proportion of agricultural products every year. With the continuous increase in the demand for data analysis in various industries in the era of big data, the efficient acquisition of key information through Machine Learning (ML) has steadily evolved into the primary factor propelling the advancement of ML technology today. This paper compares comprehensive methods to verify the feasibility of using KNN, SVM, RF and ARIMA to predict Chinese farm products, and the optimal choice is proclaimed.
Hardware Accelerators for Spiking Neural Networks for Energy-Efficient Edge Computing

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. GLSVLSI ’23, June 5–7, 2023, Knoxville, TN, USA © 2023 Copyright held by the owner/author(s). Publication rights licensed to ACM. ACM ISBN 979-8-4007-0125-2/23/06. $15.00 https://doi.org/10.1145/3583781.3590254 on VLSI 2023 (GLSVLSI ’23), June 5–7, 2023, Knoxville, TN, USA. ACM, New York, NY, USA, 2 pages. https://doi.org/10.1145/3583781.3590254
Efficient Synchronization-Light Work Stealing

Work Stealing (Ws) is a provably efficient scheduler of parallel computations. In WS each processor owns a deque that it uses as a call stack; when out of work, processors try to steal tasks from other processors' deques. Unfortunately, the concurrent nature of processors' deques entails expensive synchronization even when processors access their own deques. Recently, Rito and Paulino have found that the use of split deques allows to provably avoid most synchronization costs while keeping WS's asymptotically optimal expected runtime; in Low-Cost Work Stealing (LCWS) - the variant of WS introduced in their work - processors need not synchronization for most local accesses to their (split) deques. In this paper we assess the concrete efficiency gains of LCWS in practice. More concretely, we implemented LCWS in the Parlay library and show how it compares against Parlay's original work stealing algorithm on the execution of the benchmarks from the Problem-Based Benchmark Suite (PBBS). Experimental results show that our signal-based LCWS implementation obtains speedups with regard to WS for at least 65% of PBBS' benchmarks in three different computers.
Low-count PET image reconstruction algorithm based on WGAN-GP

Positron emission tomography (PET) technique can visualize the working status or fluid flow state inside opaque devices, and how to reconstruct high-quality images from low-count (LC) projection data with short scan time to meet the real-time online inspection remains an important research problem. A direct reconstruction algorithm CED-PET based on gradient-penalized Wasserstein Generative Adversarial Network (WGAN-GP) architecture is proposed. This network combines content loss, perceptual loss, and adversarial loss to achieve fast and high-quality reconstruction of low-count projection data. In addition, a special dataset for obtuse body bypassing was produced by combining Computational Fluid Dynamics (CFD) simulation software and the Geant4 Application for Tomographic Emission (GATE) simulation platform. The results on this dataset show that CED-PET can quickly reconstruct high-quality images with more realistic detail contours.
CDKN2A/B gene classification method for glioma with attention ConvNeXt

Noninvasive prediction of glioma CDKN2A/B gene homozygous deletion can assist doctors in preoperative diagnosis of glioma patients, which is crucial for guiding prognosis and the best therapeutic regime. At present, the task of glioma gene classification has the problem of too many parameters and high computational complexity. It can not capture the spatial information of different scale channels, and the introduced attention can only capture local information. Aiming at this problem, a ConvNeXt glioma gene classification method integrating pyramid channel attention is proposed. Firstly, so as to reduce network parameters, group convolution is used to extract information of different scale channel. Secondly, in order to learn important features, attention mechanism is introduced. Finally, the obtained weights are weighted to each channel to recalibrate the feature map and stablish a long-term dependence. Multiparametric brain magnetic resonance imaging (MRI) data and corresponding genomic information of 127 subjects (68 positives and 57 negatives for CDKN2A/B homozygous deletion) were obtained from The Cancer Imaging Archive (TCIA) and The Cancer Genome Atlas (TCGA) respectively. The experimental results certify that proposed method achieves 83.34%, 81.12% and 84.62% on ACC, AUC and F1, respectively. Compared with the baseline model ConvNeXt, the classification performance is improved, which proves the effectiveness and efficiency of the proposed model in the CDKN2A/B gene classification task of glioma.
ATC: Approximate Temporal Coding for Efficient Implementations of Spiking Neural Networks

Spiking Neural Networks (SNN) update their neurons' states, the most energy consuming action, only after receiving or firing spikes for energy efficiency. So reducing the number of spikes would lead to more efficient SNN implementations. We propose an approximate temporal coding (ATC) for this purpose. Because the reduction of spikes leads to more synapses being used rarely, we develop a pruning method for further energy improvement. Experimental results validate the efficiency of ATC and the pruning method. On the MNIST dataset, for example, 61% of the spikes are reduced, leading to 60% energy saving without any accuracy loss.
An End-to-end Trust Management Framework for Crowdsourced IoT Services

We propose a novel end-to-end trust management framework for crowdsourced Internet of Things (IoT) services. The framework targets three main aspects: trust assessment, trust information credibility and accuracy, and trust information storage. We harness the usage patterns of IoT consumers to offer a trust assessment that adapts to IoT consumers’ uses. Additionally, our framework ascertains the credibility and accuracy of trust-related information before trust assessment. This is achieved by validating the data collected by IoT consumers and providers. In addition, our framework ensures the contextual fairness between IoT services and trust information. Moreover, we propose a blockchain-based trust information storage approach. Our proposed storage solution preserves the integrity and availability of trust information.
Deep learning based music genre classification algorithm

The classification of music genres is of great significance in the research and applications related to the efficient organization, retrieval and recommendation of music resources. To address the current problem of low accuracy of digital music genre classification algorithms based on deep learning, this paper improves the ECAPA-TDNN model proposed based on the x-vector architecture of TDNN by implanting a bi-directional LSTM network to obtain more information about temporal context, based on which the ECAPA-TDNN-BLSTM model. Finally, a dataset containing 1000 music tracks from ten music genres was divided and tested, and the effectiveness of the model was proved by the good results in the test set. The results show that the accuracy of the proposed model for music genre classification and recognition has been improved compared with the existing models.
MAYAVI: A Cyber-Deception Hardware for Memory Load-Stores

Rapid evolution of security attacks presents a perpetual challenge to computer system defenders in terms of continuously upgrading their defense capabilities and being aware of adversarial tactics. Emerging technologies like cyber-deception offer the unique advantage of intelligently surveying hostile behavior while actively safeguarding sensitive assets by manipulating the malware execution flow to non-useful states or misrepresenting critical data. This paper explores the untapped potential of a hardware-assisted cyber-deception framework that augments a contemporary processor's abilities to realize a proactive deception platform. We present MAYAVI, a load/store unit-based hardware deception engine that dynamically alters the target addresses of memory requests issued by a malicious process. The redirected requests can lead to honey-pots that actively engage and deceive the adversary. Our experimental results show MAYAVI's efficacy against recent malware families while incurring negligible performance impact.
M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding

Video transcoding is a general but compute-intensive technology in video streaming services. Traditional single-encoder accelerators transcode multiple streams independently in the multi-output scenario. However, this mode neglects redundant computation and introduces high hardware complexity. To solve these issues, we propose a multi-encoder accelerator supporting reuse scheme. We introduce four fast algorithms based on parameter sharing to simplify encoding complexity. To further optimize the architecture, we also propose the standalone stream insertion (SSI) to increase the pipeline efficiency, and co-optimize memory access. Implementation results show that multi-encoder can reduce 68.03% computation complexity. Moreover, the area and power efficiency improve 3.05x and 2.62x.
Brief Announcement: List Defective Colorings: Distributed Algorithms and Applications

The distributed coloring problem is at the core of the area of distributed graph algorithms and it is a problem that has recently seen remarkable progress. Much of the progress on deterministic algorithms is based on two main tools: a) defective colorings in which every node can have a limited number of neighbors of the same color and b) list coloring, a natural generalization of standard coloring that naturally appears when one has to extend a previously computed partial coloring to a full coloring. In this paper, we introduce list defective colorings, which can be seen as a generalization of the two coloring variants. In a list defective coloring instance, each node υ is given a list of colors together with a list of allowed defects for each color in υ's list. We highlight the role of list defective colorings by showing that faster list defective coloring algorithms would directly lead to faster (Δ + 1)-coloring algorithms. Further, we extend a recent distributed list coloring algorithm by Maus and Tonoyan [DISC '20] to the list defective coloring problem. This in particular leads to the first deterministic (Δ + 1)-coloring algorithm in the standard CONGEST model with a time complexity of O(√ Δ ․ poly log Δ + log * n), matching the best complexity in the LOCAL model up to a poly log Δ factor.
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors

Application Specific Instruction Set Processor (ASIPs) have been proposed in the past to increase the performance while reducing the energy of general-purpose processors. These ASIPs are normally generated at the RT-Level (Verilog or VHDL). In this work we leverage the advantages of High-Level Synthesis (HLS) by designing the complete ASIP in ANSI-C. HLS is a single process synthesis method, thus, the key is to merge the CPU and hardware accelerator descriptions. This allows us proposed flow to synthesize the entire system together, which has numerous advantages like being able to reduce the total area, while further minimizing the power as the HLS process can now fully co-optimize the ASIP by e.g., maximizing resource sharing. Moreover, HLS allows to generate a variety of different implementations by simply setting different synthesis options. We leverage this unique feature in this work to automatically generate ASIPs with different area vs. performance and power trade-offs. Experimental results show that our proposed flow is very effective leading to smaller area overheads than traditional methods, while substantially reducing the energy and increasing the performance as compared to the original general-purpose RISC-V processor and the state of the art.
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking

As logic locking becomes more sophisticated and new technologies emerge (e.g., laser probing for failure analysis), the statement "logic locking is dead" will become more common. While recent studies have investigated the possibility of defining a security metric(s) for logic locking, none are sufficient against all threat models and potential future threats. In this paper, we first examine the quantitative and qualitative metrics as a MUST for logic locking. Then, by establishing a bridge between metrics and the potential methods, we introduce a compound-style logic locking that can meet the criteria needed for logic locking based on the defined metrics.
Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks

In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power side-channel attacks. We first analyze the impact of the number of independent voltage islands on the resulting signal-to-noise ratio and trace misalignment. As part of our analysis of misalignment, we propose a novel unsupervised machine learning (ML) based attack that is effective on systems with three or fewer independent voltages. Our results show that iRDVS with four voltage islands, however, cannot be broken with 200k encryption traces, suggesting that iRDVS can be effective. We finish the talk by describing an iRDVS test chip in a 12nm FinFet process that incorporates three variants of an AES-256 accelerator, all originating from the same RTL. This included a synchronous core, an asynchronous core with no protection, and a core employing the iRDVS technique using asynchronous logic. Lab measurements from the chips indicated that both unprotected variants failed the test vector leakage assessment (TVLA) security metric test, while the iRDVS was proven secure in a variety of configurations.
Design of Energy Efficient Posit Multiplier

Posit number system is an emerging number system which aims to be a competitor to the existing IEEE floating-point number system. The posit number system aims to overcome certain inherent flaws associated with the floating-point system and improve the performance of VLSI arithmetic circuits. Recent studies indicate that posit number system has the potential to vastly improve the performance of deep neural network hardware. As a result, posit arithmetic has become an important area of research. Among all the arithmetic operations in computer arithmetic, the most frequently used is multiplication. Multiplication is ubiquitously used in applications varying from image processing, signal processing to neural networks and machine learning. Multiplication also has an extremely high cost in terms of power, area and delay and thus extensive research work goes into optimization of the above parameters. In this brief, two new multiplier designs based on the Modified Booth algorithm have been proposed- P1 and P2 with novel control logic circuits to reduce dynamic power dissipation. The proposed work also involves the design of a novel sign extension with lower gate count for the Modified Booth Algorithm. Results have indicated that the proposed designs P1 and P2 achieve an improvement of 24% and 22% respectively in the PDP over the existing designs.
Hardware Efficiency Stochastic Computing based on Hybrid Spatial Coding

As the era of silicon-based microchips advances by Moores Law approach to physical limits, new computational paradigms are proposed for future systems, i.e., stochastic computation. However, the current stochastic computing faces the challenge of high latency and low accuracy. In this work, we propose spatial coding based on the hybrid stochastic computation (SHSC) method, which is a stochastic-binary hybrid domain computation. Instead of sequential bits computing, the proposed SHSC expands stochastic bits in the spatial dimension. To balance the accuracy and complexity, the multiplication is divided into high and low precision parts, where the high precision parts are performed in the binary domain, and low precision parts are performed in the stochastic domain. A low-cost error compensation circuit is proposed to further improve the computation accuracy. According to the implementation outcomes, the proposed method exhibits a 28% hardware efficiency improvement with the same inference accuracy as traditional neural network applications.
Massively Parallel Tree Embeddings for High Dimensional Spaces

Efficient computation on massive high-dimensional data greatly benefits from efficient embedding techniques into simpler metrics. Perhaps the most celebrated technique is the dimension reduction a-la Johnson and Lindenstrauss [46]. Another important method embeds the data into a tree metric space, first efficiently achieved by Bartal [15]. Both of these algorithmic tools are among the most general theorems with numerous applications. In this paper, we study these two embedding methods in the Massively Parallel Computation (MPC) model. We develop a new hybrid partitioning algorithm which generalizes both random shifted grid and ball partitioning methods for generating tree embeddings. This leads to an O(1)-round randomized MPC algorithm for embedding high-dimensional data into a tree while approximating the distance between any two points within a factor of O(log(1.5)n) (and thus distortion O(log(1.5)n)) in expectation as long as the aspect ratio is O(poly(n)). This Euclidean result beats the lower bound of Ω(log n) MPC rounds for tree embeddings of general metric spaces and can extend to a number of problems, including densest ball, minimum spanning tree, and Earth-Mover distance. Along the way, we implement and use Ailon and Chazelle's Fast Johnson Lindenstrauss Transform [2] with sublinear memory and O(1) MPC rounds, which is of its own interest.
HSB-GDM: a Hybrid Stochastic-Binary Circuit for Gradient Descent with Momentum in the Training of Neural Networks

To enable an energy-efficient training of neural networks, this paper proposes a hybrid stochastic-binary (HSB) computing circuit for implementing the gradient descent with momentum (GDM) algorithm. By accumulating the weight-update values step by step, the proposed design executes the weight optimization of a neural network. At each step, the weight-update value is obtained by a linear combination of its previous value and the current gradient. In this design, it is computed in a hybrid stochastic-binary manner and encoded as a dynamic stochastic sequence consisting of 0, +1 and -1. Then, the weights are updated by accumulating the bits in the dynamic stochastic sequence. With the hybrid stochastic-binary design, this circuit can be readily integrated into a neural network accelerator to support online training with a small footprint. Experimental results show that, with little accuracy loss, the area efficiency of the proposed HSB-GDM is improved by 2.68× and energy efficiency by 4.41× compared to a floating-point design using bfloat16 data format.