New Challenges in Verification of Mixed-Signal IP and SoC Design

With the increasing demand in mobile and industry c ontroller applications, a SoC design has more and more mixedsignal contents with the usage of some advanced power management te chniques, such as power gating, dynamic voltage and frequency scaling etc. Traditional mixed-signal verification methodology r elies on circuit simulation at different abstract levels. At the SoC level, mixed-signal functional simulation is the most commonly used tec hnique to ensure the functional correctness of a mixed-signal design . However, will the functional correctness verified by simulation g uarantee fully functioning silicon? Some other short comings of th e simulation approach are strong dependency of the functionality coverage on the test vectors and the very long simulation time due to mixed-signal content. The paper starts with an example showing that a mix ed-signal block or IP with advanced power management techniques imp oses unique challenges to SoC level verification. Such a design may pass SoC level mixed-signal functional simulation but fail o n silicon due to electrical failures, even when low power functional ity is included during simulation. The paper then proposes to use t he static verification methodology, which is widely used for digital low power designs, on mixed-signal IP and SoC and demonstrate how it will help to catch the electrical failures, which cannot be detected by using the functional simulation. Such a methodology requires the proper modeling of a mixed-signal IP with power management features. Traditionally, a mixed-signal IP is considered as a block box at SoC integration lev el. As a result, the designer will face the challenges of how they can e nsure the IP is properly integrated into the SoC. Typically, desig ners can choose to create a cell model using Liberty to enable some ba sic checks. However, with advanced power management features, t h IP may have complex interface logic, such as isolation and clamp diodes, to ensure low power functionality. Such low power logi c imposes additional constraints on how this IP should be int grated at SoC level. In addition, power management introduces add itional complexity in the functional modes of the IP, which must be checked against top level modes to ensure the IP is used pr operly. As a result a more complex macro cell model is needed for such complex low power functionality of a mixed-signal IP. In this p aper, the author will introduce such a model and demonstrate a proto type of macro model generation of a mixed-signal IP with power ma nagement features from the conventional schematic driven ana log nd mixedsignal design environment. This automation can also ut matically identify the power and ground connection, special l ow power cells such as isolation and level shifter cells and is ab le to automatically create power intent abstracts. Such a model can the n be used by a formal power structure verification tool to check t he power connectivity and functionality at SoC level. The paper is then concluded with several real desig n examples where SoC level design failures can be caught using this new methodology.