Model Reduction for VLSI Physical Verification

In this paper, we will first introduce physical verification of Very Large Scale Integration (VLSI) circuits and put the challenges in perspective from a computational electro-magnetics point of view. We argue that any models obtained from electromagnetic (electrostatic) analysis should be as simple as possible for a given accuracy. We will then focus on two aspects of VLSI physical verification, namely Finite Element based interconnect resistance extraction and Boundary Element Based interconnect capacitance extraction. We will specifically highlight some associated model order reduction issues, some of them only arise upon a specific interpretation of the FEM and BEM solution schemes. Introduction VLSI (Very Large Scale Integration) circuits consist of a small (approx. 1cm x 1cm) silicon chip. At one side of the chip the so-called active devices (typically for signal amplification and switching) are created inside the top few micrometers of the silicon, and on top of it an intricate interconnection pattern is created. Such chips may be very complex: the basic length scale of the devices is usually around 0.1 . 0.2 μm for the most advanced technologies and millions (>50 million for the Pentium IV) of such devices can be integrated on one chip. The interconnect pattern is also very complex: around 8 metalization layers criss-crossing over the chip, totaling several km’s in length, and with hundreds of millions of connections between the layers (through the insulating intermediate layer between each pair of interconnect layers). See Figure 1 for an example of such an interconnect pattern. The figure shows a SEM image where the insulating, dielectric layers have been etched away to show the 3D structures. The on-chip interconnections are not ideal: they e.g. exhibit non-negligible parasitic resistive, capacitive and inductive behavior. During the chip design process, care must be taken to account for their effects upon the performance and functionality of the chip. Indeed, these interconnection parasitics tend to determine the performance. With each new technology generation, their relative influence (compared to the intrinsic performance potentially offered by the active devices w./o. considering the interconnect parasitics) is rising, and for current state-of-the-art technologies it is even dominating. However, during the chip design phase, only simple interconnect models can be used. Accurate models would be far too complicated: the associated amount of detail would effectively inhibit any design optimization procedure because of the required amount of computing resources, and it would totally obfuscate conceptual design. Therefore, chip design is always followed by a so-called physical verification step, in which any design flaws are to be discovered before the design is released for manufacturing. If necessary, the verification results are used to fine-tune or change the design. In practice, design and verification form an iterative, hopefully converging, procedure. Physical verification by necessity employs much more accurate and detailed interconnect models than being used during design. Although this is feasible during verification, it still is a daunting task because of the complexity of scale (e.g. km’s of interconnect) on the one hand and the sub-micron scale geometric resolution on the other hand. In principle, one has to solve Maxwell’s equations for structures of which Figure 1 only shows 1 millionth part. Fortunately, however, many simplifications can be made and most often it is allowed to first compute a so-called ”equivalent circuit-model”. This is essentially the circuit as intended by the designer, but augmented (’back-annotated’) with lumped parasitic resistors, capacitors and inductors. Subsequent verification (either static analysis or simulation) will then show (lack of) compliance to the specifications. Given the scale of the problem, the equivalent circuit model (obtained by a process called ’layout to circuit extraction’) easily overwhelms the capacity of the actual verification task. Therefore, so-called reduced order modeling or model order reduction is of paramount importance. This activity aims at producing circuit models as simple as possible that still accurately predict the actual chip behavior. Obvious issues that are involved with this process include stability and/or passivity of the resulting models, accuracy and required computing resources (memory and CPU time). In this paper, we will focus on Finite Element based interconnect resistance extraction and 3D Boundary Element Based interconnect resistance extraction. We will specifically highlight some associated model order reduction issues, some of them only arise upon a specific interpretation of the FEM and BEM solution schemes. Our goal is to show our modeling philosofy, hoping for exposing cross-fertilization opportunities. FEM for Interconnect Resistance Modeling as Model Order Reduction Matrix Formulation of the FEM Without going into detail (but see, e.g. [8]), we state that the finiteelement method discretizes the interior of the interconnections and produces the following system of equations: [ Att Ait Ati Aii ] [ xt xi ]