MULTIPLIER SEQUEL CIRCUIT SIMULATOR LEAKAGE POWER DISTRIBUTION NMOS / PMOS DEVICES LUT LEAKAGE POWER NAND HYBRID MONTE − CARLO CODE Tox Lg Halo

This paper focuses on the impact of process variations on the estimation of static leakage power and its variability. A statistical methodology for the estimation of static leakage power dissipation due to subthreshold leakage and gate tunneling leakage in 65 nm CMOS digital circuits, in the presence of process variations, is presented. A 2-input NAND gate is used as a representative library element, whose leakage power is extensively characterized, by rigorous mixed-mode simulations. Also, an analytical model for leakage power is proposed at the gate level in terms of the device resistance data, for computational simplicity. The proposed methodology is demonstrated by characterizing the variations in the leakage power of a 4-bit× 4-bit Wallace tree multiplier by an extensive Monte Carlo analysis. To extend this methodology to a generic technology library for process characterization, an optimal second order hybrid model is proposed by combining a piece-wise quadratic model obtained by Least Squares Method (LSM) and Response Surface Modeling (RSM) of leakage power of NAND gate directly in terms of process parameters, using Design of Experiment (DOE). We demonstrate that our hybrid models based statistical design approach can result in upto 95% improvement in accurate prediction of variability with an error of less than 0.7%, with respect to worst case design. In terms of standard deviation, the predictability of leakage power distributions get tighter by atleast 13X, leading to considerable savings in the power budget of low power CMOS designs. This work aims to bridge the manufacturing to design gap, through the characterization of standard cell libraries for leakage power, in the presence of process variations. Index Terms mixed mode simulations, Design of Experiments, Response Surface Methodology,Least Squares Method, Monte Carlo analysis, hybrid model, analytical resistance model, leakage power distribution I. I NTRODUCTION Process variability and its impact on circuit design is becoming extremely critical to address power optimization and management issues in sub-90 nm CMOS designs for mobile applications. In sub-90 nm high performance CMOS designs, the static leakage power dissipation contributes about 33% of the total power consumption of the circuit [1] and is expected to increase further with technology scaling. It is estimated that across successive technology generations, subthreshold leakage increases by about 3-5X [2] while gate leakage can increase by as much as 30X [3]. Traditionally, the supply voltage ( Vdd) is being scaled to achieve the twin objectives: to limit the dynamic power dissipation and to maintain reliability across process generations. Along with Vdd scaling, the threshold voltage ( Vt) of the MOS transistors has been scaled down to sustain performance enhancements. As a result, sub-threshold leakage power is increasing drastically due to its inverse exponential dependence on Vt. Also, with scaling, as gate oxide gets thinner, oxide tunneling current is increasing exponentially and contributing significantly to leakage power. Moreover, the increasing statistical variation in process parameters has emerged as a serious challenge in nano-scale regime and can result in significant increase in leakage power and its spread. Device sensitivity to variance is increasing faster than process engineers can reduce the variance. Process variations can no longer be hidden behind the defensive barrier of tight design rules. The traditional circuit design techniques based on worst case leakage result in excessive guard-banding, lower performance and extremely pessimistic and expensive design solutions, as worst case model files can easily INTERNATIONAL JOURNAL OF CIRCUITS, SYSTEMS AND SIGNAL PROCESSING Issue 4, Volume 5, 2011 333 exhibit 10-100X larger leakage than a nominal device. Several methods have been proposed for predicting and minimizing the leakage power and its variations. A full chip leakage estimation technique is presented to accurately account for power supply and temperature variations [4]. A probabilistic framework for full-chip subthreshold leakage power distribution considering within-die and die-to-die variations in process, temperature and supply voltage has been presented [5]. A full-chip subthreshold leakage power prediction model that takes into account within-die threshold voltage variation is presented and verified against statistical measurements in0.18 μm CMOS [6]. An analytical model is proposed to estimate mean and standard deviation of leakage current as a function of process parameter distributions [7]. Analytical models have been developed to estimate mean and standard deviation of the gate leakage, band-to-band-tunneling (BTBT) leakage and the total leakage with parameter variation and to model the correlation among the leakage components with respect to different process parameters [8]. An analytical model is derived to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability and the need for statistical methods for leakage current analysis is demonstrated [9]. A novel statistically aware dual-Vt and sizing optimization method is presented considering both the variability in performance and leakage of a design [10]. A method is proposed to analyse the subthreshold and gate leakage power of a circuit that include spatial correlations due to intrachip variation [11]. The feasibility of leakage-aware placement of dualVt circuits to minimise leakage power variation due to correlated process variations has been explored using Monte Carlo simulations [12]. It has been shown that by upsizing the gate length of transistors in the non-critical paths by 6%, leakage power variability is reduced significantly by up to 41%, apart from reducing the leakage power by 24%38%, while incurring a small delay penalties of under 10% [13]. Voltage interpolation technique is proposed as a post-fabrication tuning design methodology to demonstrate design tradeoffs between circuit tuning range and static power overheads in the presence of process variations. The analysis showed that the scheme can match the nominal delay target with a 10% power cost or for the same power budget, incur only a 9% delay overhead after variations [14]. Adaptive body biasing scheme that computes unique body biases for each voltage/frequency level as the dynamic voltage/frequency scaling control policy at chip power-on offers the best tradeoff in terms of area, performance and power metrics [15]. But none of these works directly relate the leakage power to the process parameters. Earlier, we have presented a methodology, based on statistical modeling using DOE-RSM and LSM, to estimate the realistic variability in gate delay [16] and dynamic power [17] as a function of underlying process parameters. There is a need for such methodologies for reliable and accurate estimation of static leakage power as a function of process parameters. Such methodologies would facilitate “combination process-design mitigation techniques” exercising tight cooperation between process and design, which are key for managing process variations in future CMOS processes [18]. The major sources of static power are the subthreshold leakage current, the gate oxide tunneling current and the reverse-biased junction leakgage current. The junction leakage is typically negligible compared to the subthreshold leakge, especially for scaled down threshold voltages in nano scale technologies. A difference in Tox of just 2 A can lead to an order of magnitude change inIgate, making it extremely sensitive to process variations [19]. Measured variations in chip level leakage current that is as much as 20X have been reported in literature [20]. The growing incidence of parameter variability in sub-100 nm CMOS designs has highlighted the need to consider the impact of leakage variations during design phase itself and to evolve leakage variability-aware design methodologies. Such power conscious CAD tools and methodologies that support design for low power can achieve technology independent gains of the order of 3X to 5X for power [21]. In this direction, we present a statistical methodology to evaluate the effect of individual and concurrent process parameter variations on the static leakage power variations of a complex digital circuit. The proposed methodology, unlike traditional techniques ([4] [11]), directly relates the leakage power to underlying manufacturing process parameters through Process Compact Models (PCM). This enables the process engineers to tightly control the significant process parameters, to minimize the leakage variations. This will also facilitate the realistic estimation of variability in leakage power considering the actual short range and long range order of individual processes, as well as the correlations among process parameters. The design will, then, become more robust and less conservative. The proposed hybrid models can generate the probability distribution function of the leakage power and hence can also be used for estimating the yield. The static leakage mechanisms considered for study are the sub-threshold leakage and the gate leakage due to direct tunneling. We perform mixed-mode simulations, which bring the process simulated devices directly into the netlist INTERNATIONAL JOURNAL OF CIRCUITS, SYSTEMS AND SIGNAL PROCESSING Issue 4, Volume 5, 2011 334 SIMULATOR DEVICE DESSIS MODELS LEAKAGE POWER TEMPLATES DIOS