Design of Soft Error Tolerant Logic Circuits

We present two novel circuit design techniques that effecti v ly reduce the impact of radiation-induced single event tr ansients (SET) on logic circuits. Both techniques can be applied to la rge CMOS designs and have been verified by a recently develope d soft error rate analysis (SERA) methodology [3]. Rapid scaling of integrated circuit process technology has resulted in significant improvements in power consumption a nd throughput. However, reduced feature sizes and voltages ma ke current and future integrated microsystems more vulnera bl to soft errors due to alpha particles, high energy cosmic ray ne utrons, and neutron induced B fission [1], [2]. Prior research has shown that the soft errors caused by radiation events, if unc orre ted, result in a failure rate higher than all the other r eliability mechanisms combined [4]. Circuit level hardening techniqu es have been applied to sequential logic circuits in prior wo k, such as dual interlocked storage cell (DICE) [5], Whitaker de sign [6], and Barry/Dooley design [7], [8]. These designs ai m to protect the bits stored in bistable elements in the data re tention mode. Other sequential circuit designs [9], [10] ca n block a fraction of the single event transients (SET) propagation fr m the logic. Such design styles will typically require de layed versions of clock or data signals, which results in drastic i mapact on performance when the SET duration becomes large or when multiple SETs overlap with one another. The first design technique aims to reduce transient generati on nd propagation within the logic gate network, rather tha n blocking it after its generation and propagation. This desi gn style can be employed in both static and dynamic CMOS combinational circuits, and does not require any passive el em nts such as resistors or capacitors. A static circuit des gn d in the proposed style has two output ports while a dynamic cir uit has one. This design style achieves SET mitigation by incorporating two techniques simultaneously: 1) placing t ransistors that are closest to the output terminals in isola ted wells and tying their body terminals to the corresponding source term inals. The resulting low electric fields across the drain-bo dy and source-body junctions significantly weaken the charge coll e tion efficiency. 2) attenuating SETs caused by charge coll ction near other transistors outside the isolated wells via volta ge division. A dual output soft error tolerant inverter is compared with a conventional inverter in Fig. 1. The generation and propaga tion of a SET in inverter chain circuits are simulated and results are shown in Fig. 2. We assume in the circuit simulations that t ere is a particle strike on the n-type drain at the first inverter o utput att = 300ps, and one on the p-type drain at the first inverter output att = 800ps. Note that such an event sequence is for illustration purp oses only and that the probability of such an event sequence is very low in practice due to the low particle flux an d small drain area. It is clear from the waveforms in Fig. 2(a) that the generated SET in an inverter chain circuit composed f conventional inverters, if large enough in both magnitud e and duration, could propagate down the logic chain with little o r even no attenuation. This SET can have a detrimental effect on the reliability of a system if it arrives at a state node witho ut being detected and corrected. On the other hand, the wavef orms in Fig. 2(b) shows that only the output ports of the inverter u nder direct hit are adversely affected by the particle strik e.