A Guide to Literature on Chaotic Routing

The Chaotic Routing Project at the University of Washington encompasses a wide range of research pertaining to multicomputer communication networks. Most research is restricted to routing and ow control topics, but other issues, such as network topology and fault tolerance are covered as well. In general, the network model this research is targeted to is a high-speed, pointto-point network connecting the processors in a single large multicomputer. This does not include wide-area or even local-area networks of workstations. To date, the primary thrust of work on the Chaotic Routing Project has been in the areas of design, simulation, and implementation of the Chaos Router. The design and theory behind the chaotic routing concept was rst introduced in [Konstantinidou & Snyder 90] and a proposed architecture for a chaos router was presented in [Konstantinidou & Snyder 91]. Konstantindou's dissertation provides more in-depth details on the proposed design and architecture [Konstantinidou 91]. A more concise version of Konstantinidou's dissertation work can be found in [Konstantinidou & Snyder 94]. The chaotic router design was expanded to include not only hypercube, but also other k-ary d-cubes such as mesh and torus networks in [Bolding & Snyder 91b, Bolding & Snyder 92]. This work also introduced a streamlined virtual cut-through mechanism in the router, and demonstrated superior performance to oblivious routing techniques (more details can also be found in [Bolding 93a]). Expanded simulation studies of mesh, torus, and hypercube networks were presented in [Fulgham & Snyder 93] which explored the performance of several types of nonuniform tra c such as transpose, bit-revesal, complement, hot spot, and others in chaotic and oblivious routing. All of this work is summarized in [Bolding et al. 94]. The VLSI implementation of the Chaos Router Chip was detailed in [Bolding et al. 93] and [Bolding 93a]. Implementation of a high-performance, clock-skew tolerant version of a channel is discussed in [Wille 92]. The fault-tolerant aspects of chaotic routing were presented in [Bolding & Snyder 91a] and [Bolding & Yost 94a]. A reordering packet-router network interface is being designed by Neil McKenzie and is described in [McKenzie et al. 94]. Other work includes several papers on various aspects of networks and network routing. The invention of the Zenith minimal adaptive router is described in [Konstantinidou 90, Konstantinidou 91]. An analysis of another minimal adaptive router is desribed in [Nguyen & Snyder 94], while worst-case permutations for minimal adaptive routing are explored in [Chinn 94]. An analysis of the performance of hypercube and torus networks, when subjected to pinout and bisection bandwidth constraints, is presented in [Bolding & Konstantinidou 92]. An analysis of the harmful e ects of unbalanced loading caused by the common virtual-channel deadlock prevention scheme is presented in [Bolding 92]. Various technologies for channel design are compared in [Bolding 93b]. The chaos router simulator, a detailed simulator model which can simulate many di erent types on routing on any k-ary d-cube network is available for use by other research institutions via anonymous ftp from shrimp.cs. washington.edu in ftp/pub/chaos, as are most of the above mentioned documents. Abstracts of the Chaotic Routing Project documents follow: