Design Flow for Automatic Mapping of Graphical Programming Applications to Adaptive Computing Systems

Graphical programming environments such as Khoros [1] from KRI, LabVIEW from National Instruments and Simulink from MathWorks, separate application-level programming from low-level programming by allowing programs to be constructed by interconnecting precompiled programs or functions. These programming environments allow faster and easier development of complex applications; however, the execution times for image and digital signal processing are often long due to large input data sets and computationally intensive processing functions. With the advent of adaptive computing systems (ACS), these applications which are traditionally implemented in software can now be implemented in reconfigurable processing devices. As a result, the ACS can serve as a flexible hardware accelerator for time-consuming and computationally intensive applications. However, programming an ACS remains a significant obstacle to its widespread adoption by application programmers who are generally not familiar with hardware design. To enable designers to map their applications onto an ACS, a software design environment called CHAMPION is being developed. This paper presents the algorithms used in CHAMPION for mapping Khoros programs onto ACSs which utilize multiple FPGA-based architectures. LIBRARY CELL DEVELOPMENT AND VERIFICATION An overview of the design flow of CHAMPION is shown in Figure 1. Khoros is used as a function oriented programming environment where all the application programs are developed using predefined functions called glyphs. These primitive functions are part of the CHAMPION precompiled library developed using fixed-point C or C++. Each of these glyphs is derived from a VHDL source code file that has been synthesized using commercially available tools into the target ACS architecture. Additional cells can be added to the precompiled library as needed when CHAMPION is used for other applications of interest. To incorporate a new cell into CHAMPION, the designer must first develop the C or C++ program and the corresponding VHDL code for the cell. For complex functions, the C or C++ programs and VHDL codes can be formed as macros of lower-level functions. The Khoros tools can then be used to transform the C or C++ program into a Khoros glyph. For the installation of the VHDL hardware cell into the CHAMPION library, a CHAMPION software tool can be used. The CHAMPION tool automates the synthesis of the VHDL code using the commercial logic synthesis tool, Synplify. Based on the ACS architecture specified by the designer, the tool will generate the required technology-dependent file and a text file (named inf file) for storing the information such as the size, latency and I/O data bitwidths of the hardware cell. This information will be used during the data width matching, data synchronization and partitioning processes. CONVERTING KHOROS WORKSPACE TO CHAMPION NETLIST Using Khoros, the designer can develop the application by interconnecting CHAMPION glyphs to form the Khoros workspace. Simulation, data analysis and visualization can then be performed in Khoros on the UNIX workstation. Once the desired functionality of the application is achieved, the Khoros workspace can be automatically mapped onto the target ACS. The initial step in CHAMPION consists of translating the Khoros workspace into a more graph-oriented netlist format. The netlist format is a directed hypergraph where each glyph is represented as a node and the interconnections between glyphs are represented as directed hyperarcs. Based on the information from the inf file, weights are assigned to the nodes and hyperarcs of the directed graph. The weights of the nodes correspond to the size in terms of the number of logic blocks in the FPGA, and the weights of the hyperarcs correspond to the net-width of