Tunnel FET Promise and Challenges

This paper reviews recent advancements in tunnel field effect transistor (TFET) technology and assesses its promise for overcoming the energy efficiency limit of CMOS technology. Challenges for practical implementation of low-cost, low-power TFET digital logic are discussed. Introduction Increasing power density has become a major challenge for continued MOSFET scaling, due to non-scalability of the sub-threshold swing (S) which limits reductions in threshold voltage (VT) and power supply voltage (VDD) [1]. Alternative transistor designs that offer steeper switching behavior than a MOSFET, i.e. which can achieve the required on/off current ratio (ION/IOFF) at a lower VDD, are needed to surmount this challenge. Band-to-band tunneling (BTBT) current can be modulated more abruptly than thermionic emission current; therefore a TFET (Fig. 1) can in principle achieve S < 60 mV/dec [2] hence higher ION/IOFF at low VDD. Depending on the performance requirements, then, TFETs can allow for lower voltage operation to mitigate the CMOS power crisis. This paper reviews recent advancements to improve the performance of TFETs and discusses remaining challenges for their practical use in low-power digital circuits. Si1-xGex/Si TFETs Since BTBT current increases exponentially with decreasing band-gap energy (EG), the use of Si1-xGex or Ge as the tunneling material has been proposed to improve TFET ION [3,4,5]. Demonstrated Si1-xGex and Ge TFETs have undesirably higher IOFF, however. A heterojunction design, in which the Si1-xGex or Ge is used only in the source region (while Si is used in the channel and drain regions), can maintain low IOFF [5,6]. TFETs with Ge as the source material (Fig. 2) have been demonstrated to achieve the highest ION/IOFF for low-voltage (0.5 V) operation thus far [7]. Fig. 3 compares the projected energy-delay performances of Ge-source TFET technology [7] vs. CMOS technology [8] at 22 nm gate length (LG). The steeper switching behavior of the Ge-source TFET potentially can provide for lower delay at voltages below ~0.4V hence lower energy per operation at sub-500MHz frequencies. The use of a high-permittivity gate dielectric material and a gate-all-around (GAA) structure provides for superior gate control and hence better projected performance [9]. Advanced TFET Materials The range of performance over which TFETs offer an advantage over MOSFETs can be extended if more advanced semiconductor materials are used. III-V and carbon materials are of particular interest due to their small tunneling effective masses and direct band gaps. The most promising III-V materials for TFETs appear to be InAs (n-channel) [10] and InAs/AlxGa1-xSb (p-channel) [11]. Fig. 4 compares various simulated TFET transfer characteristics. Carbon nanotube (CNT) [12] and graphene nanoribbon (GNR) [13] TFETs potentially can achieve even lower average S because the tunneling probability is higher in a 1D system than in 2D and 3D systems due to the lack of transverse momentum, and also because the 1D density-of-states distribution can provide for high carrier density at small Fermi energy, allowing large tunneling current to be achieved with a small voltage swing [14]. TFET Technology Challenges The ability to tune VT is an important requirement for circuit design optimization. To date, no systematic study of TFET VT control has been reported. Process-induced VT variation can limit VDD scaling and should be studied. Because a TFET comprises a reverse-biased pn junction, channel-length (i.e. off-state depletion width) scaling below ~20 nm will result in significantly increased IOFF [15]. This issue can be mitigated by elevating the source region (Fig. 5) to allow for more aggressive LG scaling [16]. Since a TFET is an asymmetric structure, it cannot be used effectively in a transmission/pass gate or as an access transistor because these applications require current flow in both directions. This limits the utility of TFETs in static latches/registers and conventional 6-transistor SRAM cells. For a TFET-based SRAM cell to achieve good read and write margins, an additional read access transistor is needed – at the cost of increased cell area [17]. The series connection of TFETs (vs. MOSFETs) in standard pull-down/pull-up networks will also require more area. Because the channel-region inversion layer in a TFET is linked to the drain (rather than the source as in a MOSFET), larger gate-to-drain (“Miller”) capacitance is another concern for TFET-based circuit design [18]. For lightly loaded gates (Cout/Cin < 4), this increased capacitive loading can significantly degrade circuit performance [17,18]. Conclusion TFETs show promise for improving CMOS energy efficiency. To extend the potential advantage of TFET technology beyond low-throughput/high-parallelism applications, substantial improvements in ION via innovation in device design and advanced materials are needed. Fundamental challenges pertaining to VT control, LG scaling, and TFET-based circuit design remain to be addressed before TFET technology can be considered to be practical for the manufacture of low-power digital circuits. -689Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp689-690 C-3-1(Invited)