Rethinking Memory System Design

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck [103, 110]. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy efficiency, and reliability significantly more costly with conventional techniques (see, for example [27, 32, 53, 56–58, 66, 67, 70– 72, 82, 84, 85, 92, 107, 114, 123]). In fact, recent reliability issues with DRAM [97], such as the RowHammer problem [66, 107], are already threatening system security and predictability [10, 68, 107]. In this talk, we first discuss major challenges facing modern memory systems in the presence of greatly increasing demand for data and its fast analysis.We then examine some promising research and design directions to overcome these challenges and thus enable scalable memory systems for the future.We discuss three key solution directions: 1) enabling new memory architectures, functions, interfaces, and better integration of memory and the rest of the system (e.g., [2, 3, 9, 24– 27, 43–45, 47, 48, 56, 58, 65, 78, 79, 82, 84, 89, 107, 114, 115, 118, 123, 127, 129, 132, 134, 135]), 2) designing a memory system that intelligently employs emerging non-volatile memory (NVM) technologies and coordinates memory and storage management (e.g., [52, 69– 72, 87, 93–95, 122, 124, 146–148]), 3) reducing memory interference and providing predictable performance to applications sharing the memory system (e.g., [5, 23, 29–31, 34–37, 42, 51, 59, 60, 63, 64, 73– 75, 80, 99, 101, 108, 109, 113, 130, 138–143]). In the first solution direction, we will try to answer the question: can we design system architectures that treat memory as a more central, more intelligent, more autonomous component? We will discuss compute-capable memory architectures [2, 3, 9, 26, 43, 44, 47, 61, 115, 127, 129, 132, 134, 135], DRAM retention time analysis and mechanisms for refresh reduction [56, 57, 84, 85, 114, 123], DRAM error analysis and online detection and management of memory errors [27, 56–58, 66, 82, 85, 96, 114, 123], heterogeneous-reliability memory designs [89], DRAM latency analysis and low-latency DRAM architectures [25, 26, 45, 65, 78, 79, 82, 129], high-bandwidth DRAM architectures [65, 80, 81], memory energy reduction techniques [26, 27, 32, 65, 129], memory compression mechanisms [117–121], and new virtual memory architectures [47, 133]. In the second solution direction, we will try to answer the question: can we enable a system design where an emerging NVM technology can effectively replace, augment, or perhaps even surpass DRAM? We aim to discuss architecting memory systems to incorporate emerging memory technologies as DRAM replacement [69–72, 87, 88, 94, 122, 147, 148], hybrid memory systems that incorporate multiple different memory technologies and manage them to obtain the best of multiple technologies [83, 93, 95, 124, 146], systems that can merge memory and storage management into a single unified interface to make the most of the fast, byte-addressable persistence characteristics of emerging NVMs [87, 95, 124], and techniques for enabling programmers and systems to more easily take advantage of byte-level persistence characteristics of NVM [28, 124]. In the third solution direction, we will try to answer the question: can we enable a flexible and configurable memory system that can provide predictable performance and good quality-of-service to applications, enable software to enforce various different QoS policies, and maximize system performance? To this end, we aim to discuss new memory controller designs [5, 7, 37, 49, 51, 59, 60, 63, 64, 73, 75, 76, 80, 99–101, 108, 109, 130, 138–142, 148], new network-onchip designs [6, 8, 29, 30, 39–42, 98, 144, 145], new cache designs [7, 55, 117, 128, 130, 131], memory partitioning mechanisms [80, 101], source throttling mechanisms [6, 8, 23, 35, 36, 54, 112, 113], application scheduling mechanisms [31, 143], and intelligent prefetch management techniques [33, 34, 36, 50, 73, 74, 76, 111, 131, 136]. We will also touch upon new, open-source infrastructures my research group has released [27, 45, 46, 66, 67, 81, 82, 107, 124, 125, 128, 140–142] to facilitate exploration of novel ideas in all three solution directions. Finally, if time permits, we will describe our ongoing related work in combating technology scaling, reliability, and lifetime challenges of NAND flash memory (e.g., [12–21, 38, 86, 90, 91, 96]) to enable much more reliable, durable and high-performance storage systems.