Thermal Aware Delay Modelling

Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistanceand temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this work, we show that using wirelength as the evaluation metric does n ot always produce a floorplan with the shortest delay. We propos e a temperature dependent wire delay estimation method for the rmal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment results show th at a shorter delay can be achieved using the proposed method. In addition, we also discuss the congestion and reliability is sues as they are closely related to routing and temperature. I. I NTRODUCTION With technology scaling, the feature sizes of both CMOS devices and wires shrink and designers are able to integrate more and more functionalities into a single chip. Delay in CMOS transistors decreases as the channel length is reduced in each new process. Delay in metal wires, on the other hand, shows different behaviors. For local wires, delay decrease s as the distance between the end points becomes smaller with scaling. For global wires, which has to span across the chip, delay increases due to the fact that die size does not shrink b ut slightly increases in each new process. In fact, delay in glo bal wires has increased steadily with technology scaling over t h years and already dominates path delays. In addition to technology scaling, modeling of global wires is further complicated by thermal effects. Due to the high degr e of integration and aggressive power management techniques (clock gating, power gating, etc.), the power consumption i n different regions of the chip (e.g. the power density) can va ry significantly. The spatially non uniform power consumption within the chip exhibits as thermal gradients, which are temperature differences between different regions. The high temperature and large thermal gradient in metal layers can affect many aspects of interconnect design, including signal delay, routing congestion and reliability. The propagation delay in metal wires is severely degraded by high temperature as the electrical resistivity in metal inc reases linearly with temperature. The large within-die thermal gr adients result in performance mismatch between wires of the same length but subject to different temperatures. Traditi onal physical design algorithms such as floorplanning and routin g assume resistivity in interconnects is uniform and constan t. Consequently, wirelength is used as a metric to estimate signal delay and congestion of interconnects. However, in designs where the substrate has nonuniform thermal profile, the traditional way of estimating wire delay can lead to larg e errors. This is because wire performance decreases with an increase in temperature and the delay of two wires of the same length are no longer equal. The thermal effect is more prominent in global wires than in local wires because global wires are routed in layers that are far away from the heat sink, and because global wires are routed for long distance and may develop a large thermal gradient. In recent years, temperature variation induced c lock skew in clock distribution network has received a lot of attention. In [1], [2], the authors described design time cl ock tree synthesis algorithms to modify merging locations agai nst onuniform substrate thermal profile. While in [3], optimal insertion of tunable delay buffers into clock trees is discu ssed to adjust at run time the delay of clock distribution paths th at are more susceptible to temperature variations. Thermal aw re global routing algorithms for improving reliability are al so discussed in [4], [5]. On the other side, regarding global signal wires, although extensive work has been done on thermal aware floorplanning, all of them assume electrical resistivity in wires is consta t and thermal gradients in the substrate has no impact on wire delay. This assumption is in general invalid and increasing ly inaccurate in nanometer high performance designs where lar g t mperature gradients already exist in the substrate. In this paper, we study the problem of estimating the temperature dependent wire delay during the floorplanning stag e. We first illustrate the impact of nonuniform thermal profile o n the delay in wires. Then we propose a new way to estimate the wire delay in thermal aware floorplanning algorithms. Th e proposed algorithm takes the delay, instead of the wireleng th, as one of the optimization goals, in this way, mitigating the excessive delay increase caused by high temperature. In addition, we also consider the impact of routing congestion and the reliability of wires, which are important metrics in evaluating floorplans in a realistic setting. II. T HERMAL AWARE FLOORPLANNING Floorplanning is the initial stage of physical implementat ion of VLSI circuits, which to a large extent determines the quality of the final design. During the floorpalnning stage, the main design tasks include macro block placement, global wire planning and Power/Ground network design. Traditiona l floorplanning algorithms only optimizes the total area and wirelength. In recent years, as thermal issues become more prominent, the maximum temperature is also added to the cost functions in so called thermal aware floorplanning algorith ms [6], [7], [8]. Since the thermal coupling between high power consumption blocks can significantly affect the temperatur e distribution in the whole chip, thermal aware floorplanning algorithms consider peak temperature in addition to area an d wirelength in the evaluation of a floorplan. The estimation o f peak temperature usually requires the use of compact therma l models that can compute the temperature profile in a very efficient way [9]. The floorplanning tool proposed in [6], HotFloorplan, is a very representative thermal aware floorplanner. The topolo gy of the floorplan is represented in Normalized Polish Expression and the optimization process is implemented as a simulated annealing process. During the annealing, for every candida te floorplan, the algorithm invokes routines in HotSpot [10] to compute the temperature distribution and uses the maximum temperature as one of the metrics in the cost function. The other metrics in the cost function are total area and total wirelength. The connectivity information in HotFloorplan is stored in a two-dimensional connectivity matrix and manhat tan distance is used to estimate the wirelength between two endpoints in a wire. III. T EMPERATUREESTIMATION AND WIRE DELAY CALCULATION The high temperature in global wires is caused not only by self heating, but also by heat diffusion from the substrate. According to [11], the temperature within the interconnect for a given substrate temperature can be expressed as: T (x) = Tsub + θ λ2 ( 1− sinhλx + sinhλ(L− x) sinhλL ) (1) where θ and λ are constants for a chosen metal layer in a specific technology node and depend on the thermal conductivity of metal and insulator, on their geometries, and on th e electical parameters of the interconnect (current density and resistivity). The peak temperature rise is equal to θ/λ for interconnects whose lengths ( L) are larger than the heat diffusion length. As the global wires are routed in top metal layers, the distance from the substrate is larger than local wires, and, as a resul t, the temperature rise in global wires is higher. The electrical resistance of metal has a linear relationshi p with its temperature and can be expressed as: R(x) = R0(1 + β · T (x)) (2) whereR0 is the resistance at reference temperature, β is the temperature coefficient ( 1/◦C) and T (x) is the temperature profile along the length of the wire. The value of β for copper 0 5 10 15 20 25 30 50