Building blocks for fast circuit simulation

Aalto University, P.O. Box 11000, FI-00076 Aalto www.aalto. fi Author Mikko Honkala Name of the doctoral dissertation Building blocks for fast circuit simulation Publisher School of Electrical Engineering Unit Department of Radio Science and Engineering Series Aalto University publication series DOCTORAL DISSERTATIONS 174/2012 Field of research Circuit theory Manuscript submitted 8 June 2012 Date of the defence 18 January 2013 Permission to publish granted (date) 30 August 2012 Language English Monograph Article dissertation (summary + original articles) Abstract Modern electronic circuits are typically large, consisting of thousands of transistors and other components. During the design process, there is a need to perform computationally demanding numerical simulations to verify the functionality of the circuit. Thus, the need for fast and accurate circuit simulation tools is obvious. Four approaches to improve the speed and the convergence of the numerical circuit simulation are presented. The first approach utilizes efficient iteration methods for nonlinear DC analysis. Newton–Raphson (NR) iteration is the most used nonliner iteration method for nonlinear circuit equations, but it lacks good global convergence properties. Some new variants of nonlinear iteration methods are proposed to improve the convergence of DC analysis. In the second approach, the computing time is reduced by using parallel processing. Parallelization of harmonic balance (HB) analysis using multithreads is studied. Also, the modified multilevel NR method that has improved convergence properties is presented. The third approach concentrates on improving the convergence of iterative solvers for linear systems using preconditioners. The emphasis is in the preconditioning of Jacobians of the HB method. It is shown how to use time-domain preconditioners with frequency-domain preconditioners in order to benefit from both. The fourth approach to speed up the circuit simulation is to use model-order reduction (MOR), where the idea is to approximate complex circuit models with simpler ones. This thesis concentrates on MOR methods for linear circuits or the linear parts of nonlinear circuits. Efficient partitioning-based MOR methods and a new global approach to projection-based MOR are proposed.Modern electronic circuits are typically large, consisting of thousands of transistors and other components. During the design process, there is a need to perform computationally demanding numerical simulations to verify the functionality of the circuit. Thus, the need for fast and accurate circuit simulation tools is obvious. Four approaches to improve the speed and the convergence of the numerical circuit simulation are presented. The first approach utilizes efficient iteration methods for nonlinear DC analysis. Newton–Raphson (NR) iteration is the most used nonliner iteration method for nonlinear circuit equations, but it lacks good global convergence properties. Some new variants of nonlinear iteration methods are proposed to improve the convergence of DC analysis. In the second approach, the computing time is reduced by using parallel processing. Parallelization of harmonic balance (HB) analysis using multithreads is studied. Also, the modified multilevel NR method that has improved convergence properties is presented. The third approach concentrates on improving the convergence of iterative solvers for linear systems using preconditioners. The emphasis is in the preconditioning of Jacobians of the HB method. It is shown how to use time-domain preconditioners with frequency-domain preconditioners in order to benefit from both. The fourth approach to speed up the circuit simulation is to use model-order reduction (MOR), where the idea is to approximate complex circuit models with simpler ones. This thesis concentrates on MOR methods for linear circuits or the linear parts of nonlinear circuits. Efficient partitioning-based MOR methods and a new global approach to projection-based MOR are proposed.