Miracle-dz/UniFAR-FTUs huggingface dataset:
Toward Building a Semantic Network Inventory for Model-Driven Telemetry

Network telemetry based on data models is expected to become the standard mechanism for collecting operational data from network devices efficiently. But the wide variety of standard and proprietary data models along with the different implementations of telemetry protocols offered by network vendors become a barrier when monitoring heterogeneous network infrastructures. To facilitate the integration and sharing of context information related to model-driven telemetry, this work proposes a semantic network inventory that integrates new information models specifically developed to capture context information in a vendor-agnostic fashion using current standards defined for context management. To automate the integration of this context information within the network inventory, a reference architecture is designed. Finally, a prototype of the solution is implemented and validated through a case study that illustrates how the network inventory can ease the operation of model-driven telemetry in multi-vendor networks.
A Patch Antenna Based on Filtering Feed Structure With Cross-Polarization Suppression

This paper investigates a filtering patch antenna with cross-polarization suppression. The patch antenna is fed by a filtering feed network, which consists of two vertical C-shaped microstrips arms printed on four PCB layers and two vertical probes. In the proposed design, a novel feeding scheme excites patch mode to achieve an operating bandwidth of 13.4%, with an average antenna gain of 7.2 dBi. Meanwhile, the filtering feed network filter the energy fed to the antenna, thus the antenna has a good selectivity. Furthermore, owing to the two pairs of vias in the substrates with out of phase current, the cross-polarization of the antenna can be suppressed. The total size of the filtering patch antenna is $0.38\lambda 0\times 0.38\lambda 0\times 0.06\lambda 0$, which is almost the same as the footprint of a traditional patch antenna.
14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur

Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying delay-locked loops (MDLLs) are promising candidates for low-cost, high-performance clock generation, thanks to the largely suppressed phase noise of the RO due to the reference injection, small area, and technology-friendly scaling. For such architectures, the fractional-N operation is typically realized with a digital-to-time converter (DTC) to delay the reference-injection signal with a proper fractional-N phase shift such that it aligns with the RO phase at the injection node. However, the non-idealities of the DTC, including offset, gain, and integral-nonlinearity (INL) errors, introduce a periodic injection error into the RO and are key error mechanisms for generating reference and fractional spurious tones. Previous research on MDLLs or IL-PLLs that addressed DTC non-idealities falls mainly in two categories: DTC error calibration and DTC error randomization. [1], [2] calibrated gain and offset errors, and [3] also corrected INL. However, these techniques are limited by either the error estimation or correction accuracy. [4] demonstrated a nonuniform injection skip to randomize the DTC INL, but the spur reduction is constrained by the limited degree of randomization in addition to the elevated noise floor. To address the aforementioned challenges, we propose 1) an injection-error scrambling technique that allows a higher degree of randomization and thus suppresses spurs even more, 2) a background error compensation technique that mitigates the timing mismatch associated with the injection-error scrambling, and 3) a background third-order delay equalizer that corrects DTC offset, gain, and INL errors at multiple points of an MDLL, with a relaxed analog implementation requirement. For the maximal performance, we performed the DTC error calibration and randomization simultaneously. To prove the concept, a fractional-N digital MDLL prototype was implemented in 65nm CMOS demonstrating $800\text{fs}_{\text{rms}}$ jitter and −67dBc fractional spur with 29dB spur suppression.
Tensor Movement Orchestration in Multi-GPU Training Systems

As deep neural network (DNN) models grow deeper and wider, one of the main challenges for training large-scale neural networks is overcoming limited GPU memory capacity. One common solution is to utilize the host memory as the external memory for swapping tensors in and out of GPU memory. However, the effectiveness of such tensor swapping can be impaired in data-parallel training systems due to contention on the shared PCIe channel to the host. In this paper, we propose the first large-model support framework that coordinates tensor movements among GPUs to alleviate PCIe channel contention. We design two types of coordination mechanisms. In the first mechanism, PCIe channel accesses from different GPUs are interleaved by selecting disjoint swapped-out tensors for each GPU. In the second method, swap commands are orchestrated to avoid contention. The effectiveness of these two methods depends on the model size and how often the GPUs synchronize on gradients. Experimental results show that compared to large-model support that is oblivious to channel contention, the proposed solution achieves average speedups of 38.3% to 31.8% when the memory footprint size is 1.33 to 2 times the GPU memory size.
A New NVM Storage System with High Throughput Device Driver

NVM device offers an effective way to solve the storage wall of the computer system, but its high read/write speed poses a significant challenge to the existing I/O software stack in Linux. This paper designs an effective BIO management strategy for NVM device driver and builds a high throughput NVM storage system to improve the concurrency and reduce BIO management overhead. First, a two-phase dynamic BIO management strategy module is proposed to separate BIO reception and execution, thereby improving the concurrency of BIO management in the NVM device driver. A lightweight BIO migration strategy is then designed to reduce the access number to NVM devices and improve the throughput of NVM device driver. Finally, based on Intel's open-source NVM device driver named PMEM, a high throughput NVM device driver named SVTNVM is implemented to build the new NVM storage system prototype. Some tests and analysis were carried out by using Filebench and Fio to simulate application workloads for evaluation. The results show that SVTNVM can improve IOPS by 29.3% and I/O bandwidth by 23.3% compared with current NVM storage system with PMEM.
An Ultra-Wideband Antenna Based on Co-Planar Waveguide Feeding

An ultra-wideband (UWB) antenna is proposed in this paper. The proposed UWB antenna consists of a couple of fan-shaped ground plane with a series of rectangular slots and a gourd-shaped radiating patch. The ground plane and the patch are printed on the same side of the dielectric substrate, and the co-planar waveguide feeding is employed. Which enables the proposed antenna have compact structure and is easy to be integrated. By adding three quarter wavelengths open ended stubs to the microstrip feeding line, and etching symmetrical serrated slots at both sides of the patch, the antenna can obtain ultra-wideband performance. The simulation results show that the proposed antenna operates at 10 GHz and the impedance bandwidth is 156.6%, ranging from 2.84 to 18.5 GHz. And the antenna has a compact size of $1.5 \lambda_{0}{}^{*}\boldsymbol{0.6}\lambda_{0}$.
Routing Strategy for SDN Large Flow Based on Deep Reinforcement Learning

With the expansion of network scale, traditional routing strategies in Software-Defined Networking (SDN) have difficulty adapting to fast traffic variability. The large flow in the network occupies 80% of the network traffic. An unreasonable schedule of the large flow will lead to the emergence of bottleneck links and reduce the network performance. To solve the above problems, this paper proposes a different routing method, called Routing Strategy for SDN Large Flow Based on Deep Reinforcement Learning (RSDRL). Considering the links in the network that can carry large flow are limited, RSDRL can schedule large flow firstly and generate routing strategies adaptively. At the same time, in order to avoid the occurrence of congestion, RSDRL quantifies the degree of congestion in the network to implement routing. Experiments show that the proposed model has better Quality of Service (QoS) performance under the test traffic, realizing a reasonable schedule of traffic.
Sum and Difference Beams Antenna Based on Odd-Even Mode Composite Waveguide

A novel sum and difference beams antenna is proposed, which based on odd-even mode composite waveguide. The in-phase electromagnetic field is realized by exciting the even mode of spoof surface plasmon polariton (SSPP), and the out-of-phase electromagnetic field is realized by exciting the even mode. They transmit at the same frequency band. In this design, a gradient vivaldi-shaped flaring structure achieves sum and difference beams in the endfire direction. The transmission characteristics are given and analyzed. The simulated results show that the sum and difference beams antenna can operate from 10.5 GHz to 14.5 GHz. The sum beam realized gain is 11.9 dBi at 13 GHz, and the difference beam realized gain is 9.67 dBi at 13 GHz.
Temporal Rule-Based Counterfactual Explanations for Multivariate Time Series

The black-box nature of machine learning models is the main reason impeding their full adoption in decision-making processes. In order to reduce models’ opacity and overpass this challenge, major efforts that aim to increase stakeholders’ trust and ensure the fairness of decisions are being made by the data mining community under the Explainable Artificial Intelligence (XAI) paradigm. The two main categories of solutions are 1) developing fully transparent algorithms and 2) providing post hoc explanations. However, the literature is rather scarce when it comes to time series data, and even more so in the context of multivariate time series. In this work, we aim to exploit the discriminative power of shapelets and temporal rules in time series mining and capitalize on their inherent interpretability to develop a model-agnostic, temporal rule counterfactual explainer (TeRCE) for multivariate time series datasets. Counterfactual explanations indicate how should the input change such that the decision output changes too. Thus, they can highly increase the interpretability of black-box models. We test TeRCE on five benchmark datasets from the UEA archive and prove that it produces high-quality counterfactuals. Moreover, we show that in addition to being visually and conceptually interpretable, our approach performs better than the state-of-the-art algorithms in terms of proximity, sparsity, and second in terms of plausibility.
Wheats the Deal? Understanding the GMO debate in online forums

How can we comprehensively understand the main concerns and beliefs of the GMO debate in online forums? Genetically Modified Organisms (GMOs) have historically been a hotly debated topic, both within and outside of the agriculture industry. Understanding the complexity of these beliefs can lend policy makers the knowledge necessary to counteract misinformation. In this paper we develop Forumlyze, a systematic framework to understand user beliefs in online discourse surrounding an issue. As a case study, we focus on data collected from Reddit between 2019–2020 from four sub-forums: farming, agriculture, horticulture, and vegetable gardening. In our approach we (a) illustrate the fundamental and temporal characteristics of the issue (b) extract and characterize sentiments surrounding the issue (c) uncover the dominate concepts prevalent in this discussion and the context surrounding these concepts. The comprehensive nature of this analysis led to the following results. (1) The dominant concepts surrounding GMOs are Climate Change, Monsanto and Soil Science. (2) The sentiment of discourse around GMOs and its related concepts indicates a polarized affective system. (3) Evidence that real-world events impact online forum communities' sentiment surrounding GMOs-related concepts.
NvWa: Enhancing Sequence Alignment Accelerator Throughput via Hardware Scheduling

Sequence alignment is the most time-consuming step in the genome analysis pipeline. Since sequence alignment generally follows the seed-and-extension paradigm, prior proposed hardware accelerators either opt to accelerate the seeding phase or the seed-extension phase. However, the diversity of each sequence in the alignment workflow leads to the pipeline stall or bubbles, which finally results in a decreased throughput for the end-to-end sequence alignment.In this paper, we propose NvWa, which is a hardware scheduling accelerator for sequence alignment. To solve the diversity problem, we propose three novel scheduling mechanisms and corresponding architecture, which target the seeding phase, the seed-extension phase, and the interaction between the two phases, respectively. For the seeding phase, we propose a Seeding Scheduler to schedule all idle seeding units in only one cycle. For the seed-extension phase, the Extension Scheduler can achieve both lower latency and higher parallelism when facing seed-extension tasks with different scales. Between the two phases, an efficient Coordinator caches and dispatches seeding hits to optimal and sub-optimal seed-extension units. Furthermore, to avoid algorithmic obsolescence for the new sequence technologies, we propose a loosely coupled design, which decouples the data path and the control scheduling path. Experimental results show that NvWa can achieve 493×, 200×, 12.11×, 2.30× speedup and 14.21×, 5.60×, 4.34×, 5.85× energy reduction when compared with a 16-thread CPU baseline, an NVIDIA A100 GPU, and two state-of-the-art accelerators, respectively.
Intrinsic parameter extraction of a-InGaZnO thin-film transistors by a gated-four-probe method

We analyzed the intrinsic electrical characteristics of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) using a gated-four-probe method. Based on the back channel potential, the extraction of intrinsic field-effect mobility (μFEi) and parasitic resistance in source (Rs) and drain (Rd) electrodes was performed especially for low VGS and VDS conditions. The resulting μFEi showed typical VGS dependency of amorphous semiconductor TFTs. However, Rs and Rd showed that there can be non-uniformity in source/drain parasitic resistance, which indicates that a separate analysis of the parameters of each electrode is essential for further improvement of the performance of a-IGZO TFTs.
Recurrent Neural Network-Based Video Compression

Recently, video compression gained a large focus among computer vision problems in media technologies. Using state of the art video compression methods, videos can be transmitted in a better quality requiring less bandwidth and memory. The advent of neural network-based video compression methods remarkably promoted video coding performance. In this paper, a video compression method is presented based on Recurrent Neural Network (RNN). The method includes an encoder, a middle module, and a decoder. Binarizer is utilized in the middle module to achieve better quantization performance. In encoder and decoder modules, long short-term memory (LSTM) units are used to keep the valuable information and eliminate unnecessary ones to iteratively reduce the quality loss of reconstructed video. This method reduces the complexity of neural network-based compression schemes and encodes the videos with less quality loss. The proposed method is evaluated using peak signal-to-noise ratio (PSNR), video multimethod assessment fusion (VMAF), and structural similarity index measure (SSIM) quality metrics. The proposed method is applied to two different public video compression datasets and the results show that the method outperforms existing standard video encoding schemes such as H.264 and H.265.
A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm2/Ch and $1.78\mu \text{W/ch}$

As neural-recording devices get denser and generate more data [1], on-chip and online neural-signal processing becomes crucial to reduce the data-transmission power and enable real-time closed-loop applications with minimum latency. Spike sorting (SS) is an important data-reduction technique that allows the classification of extracellularly recorded spikes into clusters representing the neuron sources. SS requires computationally intensive algorithms usually implemented offline in software [2]. However, to enable on-chip and online SS (OSS), a low-complexity and hardware-efficient algorithm is required to achieve minimal area, energy and latency, while maintaining comparable accuracy. Although several multi-channel OSS chips have been reported recently [3]–[7], they either require offline [3], [6] or on-chip training [4], [5], [7], consume high power [5] or area [5], [6], or achieve low accuracy [4], [6] or high latency [4], [6]. Moreover, they struggle to balance the trade-off between computational complexity and performance, limiting the number of channels to <128. To overcome these limitations, this work proposes 3 key techniques for area-and energy-efficient hardware OSS, achieving software-comparable accuracy with 384 channels.
HyQSAT: A Hybrid Approach for 3-SAT Problems by Integrating Quantum Annealer with CDCL

Propositional satisfiability problem (SAT) is represented in a conjunctive normal form with multiple clauses, which is an important non-deterministic polynomial-time (NP) complete problem that plays a major role in various applications including artificial intelligence, graph colouring, and circuit analysis. Quantum annealing (QA) is a promising methodology for solving complex SAT problems by exploiting the parallelism of quantum entanglement, where the SAT variables are embedded to the qubits. However, the long embedding time fundamentally limits existing QA-based methods, leading to inefficient hardware implementation and poor scalability.In this paper, we propose HyQSAT, a hybrid approach that integrates QA with the classical Conflict-Driven Clause Learning (CDCL) algorithm to enable end-to-end acceleration for solving SAT problems. Instead of embedding all clauses to QA hardware, we quantitatively estimate the conflict frequency of clauses and apply breadth-first traversal to choose their embedding order. We also consider the hardware topology to maximize the utilization of physical qubits in embedding to QA hardware. Besides, we adjust the embedding coefficients to improve the computation accuracy under qubit noise. Finally, we present how to interpret the satisfaction probability based on QA energy distribution and use this information to guide the CDCL search. Our experiments demonstrate that HyQSAT can effectively support larger-scale SAT problems that are beyond the capability of existing QA approaches, achieve up to 12.62X end-to-end speedup using D-Wave 2000Q compared to the classic CDCL algorithm on Intel E5 CPU, and considerably reduce the QA embedding time from 17.2s to 15. 7µs compared to the D-Wave Minorminer algorithm [11].
DIRS: Dynamic Initial Rate Setting in Congestion Control for Disaggregated Storage Systems

This paper focuses on network congestion control in a disaggregated storage system. In such a system, the supporting network requires low latency and is extremely sensitive to network congestion. The existing congestion control algorithms for data center networks do not work well in our target system because of the unique characteristics of the network topology and the storage I/O workload. Motivated by the existing issues, we develop a new solution, DIRS, which dynamically sets the initial sending rate for each flow. Our scheme helps improve the effectiveness of the congestion control protocols, especially under heavy I/O traffic. It chooses an appropriate initial rate for a flow and mitigates the congestion from the beginning while not degrading the flow’s network performance.
Review and Analysis on Network on Chip

Moore's law has been extended with the introduction of multiprocessor architectures and platforms. To boost design productivity and system performance, they leverage concurrency and synchronisation in both software and hardware. Furthermore, these systems must be highly scalable, reusable, and repeatable. They'll also have to be low-cost and low-energy. It is expected that deep sub-micron technology, defined by gate lengths of 60–90 nm, will be plagued by wire delays, signal integrity issues, and unsynchronized communications as billion transistors age. The important developments in NOC research are discussed, as well as aspects that demand more exploration. The most widely used and researched topology is a packet-switched 2-D mesh. It's also a bit of an average NoC right now. There are lots of positive outcomes and intriguing proposals. However, there were significant discrepancies in implementation results, ambiguous documentation, and a lack of comparability.
Design of Ultra-Broadband 3-dB 90° Directional Coupler

This paper presents the research and design of an ultra-wideband (UWB) 3 dB 90° directional coupler, which is implemented with symmetric multi-section coupled lines and bias-coupled ribbon lines to cover the operating bandwidth from 2 to 18 GHz. The short truncation compensation structure is designed for the discontinuity of each coupling line. The simulation and measurement results show that the coupler has an amplitude consistency of ± 1 dB, a phase difference of ± 5°, and an isolation of batter than 17.5 dB in the 2 – 18 GHz range.
A 123 GHz Wideband Patch Antenna with Parasitic Modified Mushroom Structures

A low-profile microstrip-fed wideband patch antenna using BCB substrate is presented in the paper. The antenna is composed of a central patch radiator and two pairs of parasitic modified mushroom structures with different dimensions. Characteristic mode analysis is applied to revealing the mechanism of bandwidth broadening, which shows that the three different modes contribute to the radiation. The simulated −10-dB impedance bandwidth is 20.03% (110.55-135.17 GHz) with a peak gain of 10.5 dBi at 133.5 GHz. In addition, the radiation patterns are stably fixed in the boresight direction and the cross-polarization levels are relatively low over the whole bandwidth.
A Novel Embedded Discretization-Based Deep Learning Architecture for Multivariate Time Series Classification

Deep learning-based time series classification techniques have significantly improved in recent years. While previous works have mentioned the fundamental importance of temporal discretization, most studies focus on improving model architectures. In this article, several models have been presented that use temporal discretization as a step of preprocessing time series and embed it in the deep neural network. The proposed models consist of two parts: temporal discretization and model training. The first part does the task of discretization and partially the selection of primary features, and the second part does the job of selecting more accurate features and classification. For this purpose, two loss functions have been used: a loss function to evaluate the discretization quality and the other one to evaluate the classification accuracy. The evaluation of the proposed models using 20 benchmarks multivariate time series shows that the proposed methods are more accurate than the state-of-the-art methods.