Efficiency and predictability in resource sharing multicore systems

Multiprocessor and multicore systems are of increasing importance for industrial applications in the control, automotive and avionic domain. Applications in these domains often perform mission critical functionalities. In other words, these applications perform tasks with hard real-time constraints. The demand on computational resources grows with the computational complexity of these functionalities, e.g., control algorithms. Traditionally, these requirements for computational resources have been met with higher execution frequencies and instruction level parallelism. In order to satisfy rising computational demands, an industry wide shift to parallel computing, and thus multicore and multiprocessor systems, has taken place. The increased performance requirements are met by parallelization of threads and tasks on multiprocessor and multicore systems. Communication among tasks on different processing elements leads to contention on the communication fabric, e.g., buses or shared memories, and thus, to additional delays. This limits the gain that can be achieved by parallelization. Consider a system with multiple concurrently executing tasks on different processing elements. Futhermore, consider that each task requests access to the shared memory. Then it is clear that tasks have to wait their turn for accessing the shared resource, and thus experience a delay. This interdependency of tasks limits performance in general, and increases the complexity of deriving hard real-time guarantees in particular. In this thesis, we propose methods to design and analyze multicore systems with respect to power efficiency and timing predictability. The major contributions are as follows: • We propose an algorithm that optimizes the mapping of tasks to processing elements. It can handle applications that are characterized by multiple concurrently executing multi-mode applications. Each mode is associated with an execution probability. The target hardware platform is given as a library of processing element types. Each processing element type is specified with power and performance characteristics. The proposed algorithm derives mappings that minimize the average expected power consumption. We consider systems with dynamic and static (leakage) power consumption. • We propose a dynamic power aware mapping approach by providing a set of pre-computed template mappings. Template mappings are computed offline, based on the set of feasible system states (denoted scenarios) and are stored on the system. A manager monitors system state transitions and chooses an appropriate template mapping to assign new tasks to their respective processing elements. • We propose a task model, where tasks are sequences of superblocks. A superblock is a functional block that has a unique entry and exit point. Superblocks are associated with worst-case execution times (WCETs) and worst-case communication demands. We propose different resource access models, that exhibit differing amounts of uncertainty with respect to the resource access pattern of a superblock. • A worst-case analysis framework for resource sharing systems is proposed that takes contention on the shared resource into account. The framework allows to analyze systems with static or adaptive arbitration policies on the shared resource. We apply the analysis to two protocols, namely Time Division Multiple Access (TDMA), as an example for static arbitration, and FlexRay, as an example for adaptive arbitration. • We derive worst-case response time (WCRT) bounds for the proposed resource access models and show that separating communication and computation is advantageous to achieve timing predictable systems, i.e., tight WCRT guarantees.