Miracle-dz/UniFAR-FTUs huggingface dataset:
Efficient Seed Selection for IC-IS Multiphase Diffusion Model

The increased availability of high-speed internet and social networking websites such as Twitter, Facebook, etc., has made people more highly connected. Many topics of interest such as news, rumor, etc., quickly spread in an online social network. This paper proposes a new information propagation model named the IC-IS model, where the seed nodes are selected in multiple phases and diffusion is triggered in each phase with a predefined time gap between successive phases. In this model, active nodes in one phase can return to an inactive state in the successive phases during the diffusion process. This model represents a diffusion phenomenon where diffusion is initially increasing up to a certain time phase and then the diffusion spread attains almost a steady state. This paper also proposes a Degbet seed selection scheme to address the challenge of selecting the best users that can activate the maximum number of nodes within a limited budget. A comparative analysis is performed to study the influence spread of seed nodes selected from the different centrality-based seed node selection schemes and the proposed Degbet scheme under the IC-IS model. The analysis is performed over three different real-world datasets.
A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process

We present a low phase noise 4.5-to-6.5 GHz injection-locked oscillator-based frequency tripler (ILT) from an ultra-low jitter 1.5-to-2.16 GHz clock source. Class-C biasing is employed in the digitally controlled LC oscillator (LC-DCO) and the injection circuit to simultaneously achieve low phase noise in the LC-DCO and improve the third harmonic injection strength. Using BJT in the injection transistors and DCO greatly improves the low-frequency phase noise performance of the ILT. Fabricated in a $0.13 \mu \mathrm{m}$ BiCMOS process, the ILT has a measured tuning range of 4.5-to-6.5 GHz, with a jitter tracking bandwidth of 25 MHz for sub-harmonic injection. The ILT demonstrates good sub-harmonic rejection ratios SHRR1 and SHRR2 as 48 dB and 58 dB, respectively. The ILT adds 15 fs additional rms jitter to an input clock source with rms jitter of 68 fs.
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations

Previous RRAM-based computing-in-memory works mainly focus on the current-domain approach. However, the performance and accuracy of current computation are limited by large read currents of RRAM cells and their variations. This work presents a novel RRAM-based charge-domain design, C-RRAM, to resolve these limitations. A 3TlRlC cell is proposed to execute MAC operations by capacitor discharging. The resistance variations can be tolerated with reasonable discharging time, which is accelerated by a positive feedback loop. Also, the output from each cell is accumulated by charge sharing instead of summing currents to eliminate the static current path in readout circuits. In this way, robust and efficient RRAM-based CIM operation is enabled with fully input parallelism. A $512\times 514$ RRAM array is implemented to evaluate the benefits of the proposed charge-domain approach. The experiment results show that C-RRAM can suppress the output variations by $41\times$ and incur negligible accuracy loss for ResNet-18 on Cifar10 dataset. Compared to previous ITIR current-domain RRAM designs, it achieves $1.2\times$ energy efficiency and $127\times$ area efficiency due to improved parallelism.
Performance Analysis of Memristive-CNN based on a VCM Device Model

Cellular Nonlinear Networks (CNN) as a powerful paradigm is highly suitable for signal processing of multiple tasks, since they can execute cascaded processing operations in a one-layer array via real-time template updating. Their VLSI implementation by using the conventional CMOS-based integration technology, however, remains a big challenge. The memristive CNN (M-CNN) offers several merits over conventional CNN, such as compactness, nonvolatility, versatility. This paper presents a direct comparison of computing performance between the M-CNN and the conventional CNN for the implementation of a LOGAND operation template using circuit simulation. Our findings show that the M-CNN implementation offers rapid attainment of equilibrium state compared to the CNN implementation. In addition, the result is stored in a non-volatile manner in the M-CNN whereas the CNN only offers a volatile storage.
A Miniaturized Flexible Functional Near-infrared Spectroscopy System for Obstructive Sleep Apnea Detection

The clinical manifestations of OSA (obstructive sleep apnea) are night sleep snoring accompanied by apnea. fNIRS (functional near-infrared spectroscopy) can measure the relative concentration changes of oxyhemoglobin and deoxyhemoglobin, thereby measuring hemodynamics and oxygenation. Combined with the clinical manifestations of obstructive sleep apnea, fNIRS technology can be used in the monitoring of OSA. According to the principle of fNIRS, a miniaturized, wireless, and flexible device is designed in the article. The device can measure the change of blood oxygen concentration in the forehead of the brain, so that achieve the purpose of detecting OSA. To verify the effectiveness of the equipment, a breathing experiment was designed in the article to compare the equipment with the existing NIRX system. To our best knowledge, this is the first work that proposed a miniaturized flexible sleep apnea system based on monitoring fluctuations of cerebral hemodynamics. Meanwhile, the feasibility of the proposed system was verified. However, the stability of the equipment and related data processing algorithms need to be enhanced. The proposed system is expected to pave the way for the investigation of the involvement of the cerebral hemodynamics in the pathogenesis of OSA patients.
Singular value decomposition in parametrized tests of post-Newtonian theory

Various coefficients of the 3.5 post-Newtonian (PN) phasing formula of non-spinning compact binaries moving in circular orbits is fully characterized by the two component masses. If two of these coefficients are independently measured, the masses can be estimated. Future gravitational wave observations may measure most of the eight independent PN coefficients calculated to date. These additional measurements can be used to test the PN predictions of the underlying theory of gravity with a similar PN structure. Since all of these parameters are functions of the two component masses, there is a strong correlation between the parameters when treated independently. Using singular value decomposition of the Fisher information matrix, we remove these correlations and obtain a new set of parameters which are a linear combination of the original phasing coefficients. We show that the new set of parameters can be estimated with significantly improved accuracies which have implications for the ongoing efforts to implement parametrized tests of PN theory in the data analysis pipelines.
Zero-crossing-prediction-based Single-slope ADC with a Constant Charge Bias Amplifier for Low Power Image Sensors

This paper presents a single-slope analog-to-digital converter (SS-ADC) with a proposed zero-crossing (ZC)-prediction-based power-gating technique for low-power complementary metal-oxide-semiconductor (CMOS) image sensor applications. The proposed ZC prediction utilizes the DC gain difference between the preamplifier and main comparator in the SS-ADC without an additional ramp signal. For a consistent prediction with a low power operation, the constant charge bias amplifier (CQBA) is implemented as a preamplifier, which exhibits input level independent output common mode and gain response. The proposed SS-ADC is demonstrated for a 110-nm CMOS image sensor process, assuming a $640\times 480$ image resolution, a 10-bit ADC resolution, and 120 frames/s. The simulation results show that the CQBA output common mode and gain response only vary by 1% and 6.4%, respectively. Furthermore, the overall power consumption of the sensor is reduced by about 80% compared with the static comparator by the prediction-based power-gating, achieving high energy efficiency (51. 5 pJ/pixel of the Figure of merit).
Energy Harvesting by Mini-Converters Based on Nanostructured Silicon

In the work, mini-converters based on nanostructured silicon with an area of 0.5 cm2 for collecting photovoltaic energy in rooms with electric or daylight lighting are presented. Nanostructured silicon layers were obtained by an efficient and inexpensive method of chemical etching (texturing) of the surface of single-crystal silicon. The influence of the thickness of a nanostructured silicon layer on its reflection coefficient has been studied. Mini converters based on nanostructured silicon and their panels can be integrated into electronic circuits and microchips for various purposes with low power consumption. The low cost and ease of fabrication of the obtained photovoltaic power converters open up the possibility of their use in wireless sensor networks for the oil, gas, and resource industries, for health and environmental monitoring in residential buildings, and in military applications.
The 21-cm Signal from the Cosmological Epoch of Recombination

The redshifted 21-cm emission by neutral hydrogen offers a unique tool for mapping structure formation in the early universe in three dimensions. Here we provide the first detailed calculation of the 21-cm emission signal during and after the epoch of hydrogen recombination in the redshift range of z ~ 500-1,100, corresponding to observed wavelengths of 100-230 meters. The 21-cm line deviates from thermal equilibrium with the cosmic microwave background (CMB) due to the excess Ly-alpha radiation from hydrogen and helium recombinations. The resulting 21-cm signal reaches a brightness temperature of a milli-Kelvin, orders of magnitude larger than previously estimated. Its detection by a future lunar or space-based observatory could improve dramatically the statistical constraints on the cosmological initial conditions compared to existing two-dimensional maps of the CMB anisotropies.
Interleaved Hybrid Domain Learning for Super-Resolution MRI

In super-resolution magnetic resonance imaging (SR-MRI), the low-resolution scans are acquired keeping the central low-frequency components intact. The scan-time for a given matrix size is shortened by acquiring only the central low-frequency part of the k-space (Fourier space), and filling the unacquired portion with zeroes. While transforming the zero-padded low-resolution acquired k-space to the image domain through inverse Fourier transformation, an inherent blur and high-frequency oscillatory artifacts are manifested in the reconstructed image. State-of-the-art methods including reconstruction-based and deep-learning-based approaches have addressed this problem to a large extent; however, it remains a challenging problem to completely eliminate the remnant effects of blur or ringing in some of the subtle clinical features. In the proposed SR method, we have implemented an interleaved hybrid domain convolutional neural network (CNN) model consisting of a k-space and spatial domain network together with local residual connections. This helps to improve the accuracy of hyper-parameter estimation and effectively reduce the loss function, with the resulting advantage of attaining improved peak-signal-to-noise-ratio (PSNR), structural similarity index measure (SSIM) and normalized root mean square error (NRMSE) as compared to the state-of-the-art methods.
Implementation of Support Vector Machine with Lexicon Based for Sentiment Analysis on Twitter

Twitter is one of the social media that is widely used where Indonesia occupies the 6th largest Twitter user in the world. This research is a quantitative study on fine-grained sentiment analysis that extracts sentiment with the topic of the covid vaccine from Twitter with the aim of implementing the Support Vector Machine algorithm. The research flow uses the SEMMA method (Sample, Explore, Modify, Model, and Assess). The collection of data sets in the form of tweets crawled from Twitter by utilizing the Twitter API at the sample stage for further exploration of the attributes of the data set at the explore stage. The modify stage is text preprocessing so that the data set is more structured. After that is the model stage which applies the lexicon based method to assign sentiment classes to the data set. Data sets that have labels will be classified using the Naïve Bayes method and the Support Vector Machine. The final stage of the SEMMA method is to assess the method applied using confusion matrix and k-fold Cross Validation. The accuracy results from the Support Vector Machine method, the best parameter results using the CV Grid Search are the rbf kernel with $\boldsymbol{C=100}$ and degree = 0.01 resulting in an accuracy of 85%. The accuracy of the implementation of the Support Vector Machine algorithm produces good scores for the Covid-19 vaccine topic, so that the algorithm can be applied to the classification of sentiment analysis on new data.
Bionic Robust Memristor-Based Artificial Nociception System for Robotics

Nociception is an important ability for robots to interact safely with humans or work in hostile environments. By referring to previous research in mechanical receptors with ring oscillators and memristor-based nociceptors, we propose a complete robotic sensing system that senses forces and processes electrical signals at both the edge and the central. This artificial system mimics the nociception behavior of the human nervous system processing external damaging mechanical stimuli. Given mechanical receptors and nociceptors are subject to damage under harsh working conditions, we designed an error detection module that involves memristor crossbar arrays (CBA) to detect components’ potential failures. Furthermore, we propose solutions to non-idealities such as the quantization error and the memristance programming variations to boost the accuracy and the robustness of our failure detection memristor crossbar array. The precision CBA proposed reduces the quantization error for a single cell to at least 1/180 of the error under the common strategy. Our simulations show that using serial connection memristors cells and high resistance ratio cells reduce the output current variation due to programming variation to 62.2% and 71.52% respectively. The full-system simulation under a typical application scenario shows the system's ability to sense noxious stimuli and maintain system robustness at a high level.
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers

Analog non-volatile memory (NVM)-based accelerators for deep neural networks perform high-throughput and energy-efficient multiply-accumulate (MAC) operations (e.g., high TeraOPS/W) by taking advantage of massively parallelized analog MAC operations, implemented with Ohm’s law and Kirchhoff’s current law on array-matrices of resistive devices. While the wide-integer and floating-point operations offered by conventional digital CMOS computing are much more suitable than analog computing for conventional applications that require high accuracy and true reproducibility, deep neural networks can still provide competitive end-to-end results even with modest (e.g., 4-bit) precision in synaptic operations. In this paper, we describe a 14-nm inference chip, comprising multiple 512$\times$ 512 arrays of Phase Change Memory (PCM) devices, which can deliver software-equivalent inference accuracy for MNIST handwritten-digit recognition and recurrent LSTM benchmarks, by using compensation techniques to finesse analog-memory challenges such as conductance drift and noise. We also project accuracy for Natural Language Processing (NLP) tasks performed with a state-of-art large Transformer-based model, BERT, when mapped onto an extended version of this same fundamental chip architecture.
0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications

Mel frequency cepstral coefficient (MFCC) features are widely used in applications such as keyword spotting, bearing fault detection and heart sound classification. This work proposes a low power MFCC engine that enables its use for battery-powered edge applications. Three hardware algorithm co-optimizations were adopted to achieve energy efficient MFCC hardware implementation. The approximated MFCC features due to the optimizations still allows good accuracy when deployed in several applications such as keyword spotting and bearing fault detection, reporting negligible accuracy drop of $\le 1.5$%. The proposed MFCC hardware consumes only 128nW at 0.3V supply and occupies only 0.08mm2 in 40nm CMOS technology, which are $5 \times $ and $2.75 \times $ power and area reduction respectively when compared to the prior arts.
Automated Quantization Range Mapping for DAC/ADC Non-linearity in Computing-In-Memory

Computing-in-memory (CIM) has demonstrated the great potential of analog computing in improving the energy efficiency of matrix-vector multiplications for deep learning applications. Albeit low-power feature of CIM, the non-linearity of digital-to-analog converters (DACs)/analog-to-digital converters (ADCs) causes deviation between the computed outputs and desired values, thus degrading classification accuracy. This paper proposes Automated Quantization Range Mapping (A-QRM) mechanism to mitigate the negative effect of non-linearity on model accuracy. Instead of fixing the quantization range for quantized deep learning models, the proposed A-QRM automatically finds a better quantization range that balances the model capability and quantization errors caused by the non-linearity. Experimental results show that our proposed A-QRM achieves 89.02% and 86.93% of top-1 accuracy in ResNet20 and VGG8 on Cifar-10, respectively, under the non-linearity of DACs/ADCs.
An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs

This paper presents an exhaustive comparison of two different techniques for In-Memory Computing in SRAM: bit-serial arithmetic (BSA), and bit-parallel arithmetic (BPA). We have modeled both BSA and BPA and integrated them with CACTI for the CMOS 28nm technology node. The results are analyzed for both approaches with ten different sub-array configurations ranging from 128x128 to 2048x2048. We performed the convolution operation on the ImageNet dataset for comparison. The key observation is that the BPA begins to yield at least 25% better (lower) Energy Delay Product (EDP) as compared to that in BSA for large (2048x2048) sub-array sizes. The BSA yields $4 \times$ lower delay on an average, while the BPA yields $\sim 6 \times$ lower dynamic energy. Hence, the choice of the IMC architecture needs to be made depending on the application need (low energy/high performance). We have also simulated 12 different multi-bank IMC arrangements and show that just modifying the memory array structure can improve the EDP by up to $8 \times$.
Optimal Coverage-Aware Hovering UAV Height

In this paper, a low complexity solution method is proposed to find the optimal height of a hovering unmanned aerial vehicle acting as wireless base station (UAV-BS) to maximize the average coverage probability to ground users in a given coverage field. In contrast to existing literature, where the optimal height solution has been defined numerically using exhaustive search without providing any closed form expression of coverage probability, we provide analytical depth to provide closed form expression for tight approximation of coverage probability and to find the optimal altitude of UAV-BS with less complexity. Numerical and simulation results confirm the optimal UAV-BS height in terms of coverage probability and reduction in complexity to find the optimal altitude solution.
Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique

In this paper, we propose a triple-mode baseband (BB) receiver (RX) architecture for cyclic prefix orthogonal frequency division multiplexing (CP-OFDM) with weighted overlap and add (WOLA) technique. The system specifications follow the IEEE 802.11ad/ay standard for next-generation millimeter wave communications. This BBRX is a flexible and expandable architecture due to the modularized, parameterized, and feed-forward data flow design strategies. The non-ideal circuit effects, such as frequency offset, phase noise, power amplifier (PA) non-linearity, and adjacent channel interference are jointly considered for the overall performance evaluation. The simulation results show that CP-OFDM with WOLA (W-CP-OFDM) and filter bank multicarrier (FBMC) present similar out-of-band performance while considering PA non-linearity. The synthesis results indicate that the W-CP-OFDM/FBMC has 2.1%/97% gate count increased overhead as compared to CP-OFDM.
Few-shot Text Classification with Saliency-equivalent Concatenation

In few-shot text classification, the lack of significant features limits models from generalizing to data not included in the training set. Data augmentation is a solution to the classification tasks; however, the standard augmentation methods in natural language processing are not feasible in few-shot learning. In this study, we explore data augmentation in few-shot text classification. We propose saliency-equivalent concatenation (SEC)11Our code is available at https://github.com/IKMLab/SEC. The core concept of SEC is to append additional key information to an input sentence to help a model understand the sentence easier. In the proposed method, we first leverage a pre-trained language model to generate several novel sentences for each sample in datasets. Then we leave the most relevant one and concatenate it with the original sentence as additional information for each sample. Our experiments on the two few-shot text classification tasks verified that the proposed method can boost the performance of meta-learning models and outperform the previous unsupervised data augmentation methods.
A CMOS Axon-sharing Neuron Array with Background Calibration

The implementation of a power-efficient neuron array system with high throughput and controllable mismatch plays an important role in power-sensitive applications and brain simulations. This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain circuits and comparator-sharing in neuron design achieves the integration of 3125 neurons/mm2 and power consumption of 5.3 pJ/spike. The proposed time modulated axon-sharing synapse architecture realizes 5500 events/s/neuron unit throughput. A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations presents a 45% improvement in SD of inter-spike interval variation. Finally, we validate the architecture by implementing a spiking neural network for solving a 3-stage Sudoku Puzzle. 100% success rate is obtained after calibration.
A 19-bit Range and 4.5-ps Resolution Fully-Synthesizable Time-to-Digital Converter with Quad-Edge Offset Cancellation

This presents a fully-synthesizable cyclic Vernier time-to-digital converter (TDC) which cancels the offsets by a quad-edge offset cancellation (QOC) scheme. The system delays its internal clocks and uses the clock offsets to compensate for many types of offsets altogether, which includes the wiring mismatches, the duty cycle skews, and the long-term jitters of the clocks. During calibration, the QOC-TDC measures the offsets of the clock paths. The measured offsets are then canceled in the normal mode. An additional scheme of coarse-fine boundary synchronization further enhances the output monotonicity. Consisting of only standard library cells offering fully-automated implementation, the QOC-TDC achieves a 19-bit range, a 4.5-ps resolution, and the throughput of 22MS/s, while drawing 3.4mW from a 1. 0V supply, as shown by the post-layout simulations in 28nm CMOS.