Implementation for Two-Stage Hybrid Decoding for Low Density Parity Check (LDPC) Codes

ABSTRACT LDPC codes are gaining high attention in Channel Coding field these days. However, one of the main problems facing usage of these codes in communication systems is the high complexity decoding scheme that results in high decoding delay. Such delay is not acceptable in some applications that depend on time such as video transmission. This paper presents hardware implementation technique for Two-Stage Hybrid decoder resulting in better complexity and delay. Also, it shows comparison between soft, hard and hybrid decoding techniques in terms of memory usage, and delay time as to be used for real implementation for some applications such as DVB-S2. Keywords Channel Coding, LDPC, VHDL, Hybrid decoding. 1. INTRODUCTION The first Low-Density Parity Check Code (LDPC) was discovered by Gallager [1], [2] in 1960s where this code proved the extraordinary performance with iterative decoding that was very close to Shannon limit which is difficult to reach. LDPC codes are used in many applications such as DVB-S2 [3], which is a standard for Digital Video Broadcasting–Satellite-Second Generation because of its excellent Bit Error Rate (BER) performance. These codes are expected to be included in many future standards as well as to replace many existing channel coding techniques. There are many types of LDPC decoding algorithms that have good performance with acceptable delay time. These algorithms can be classified into soft-decision decoding algorithm such as the Sum-Product Algorithm (SPA) and hard-decision decoding algorithm such as Bit-Flipping (BF) algorithm which was discovered by Gallager. The Bit-Flipping algorithm has many modified versions [4], [5], [6] that have better BER performance compared to the original Bit-Flipping algorithm. The good BER performance of SPA comes on the expense of the high complexity which increases the delay time for the used design. Such high delay is considered as a drawback for some applications especially for those who are greatly affected by the delay such as video and audio transmission. On the other side, hard decision such as Bit Flipping algorithm and its modified versions have limited BER performance with lower complexity and delay time if compared to (SPA). So, Two-Stage Hybrid decoding algorithm proposed in [7] was used as a new decoding algorithm, where this algorithm provides a trade-off algorithm between hard and soft-decision algorithms and has better performance compared to that of BF and less complexity and delay time compared to that of SPA. This paper shows an FPGA design of the real hardware implementation for Two-Stage Hybrid decoder with comparison to SPA, and BF in terms of memory usage and delay time. The rest of the paper is organized as follows. Section (2) presents the background on SPA and BF algorithms. These algorithms provide the basis for the Two-Stage Hybrid decoding. Also, this section presents the existing Two-Stage Hybrid algorithm and how it is composed of SPA as the first stage and BF as the second stage. Section (3) introduces the hardware implementation technique for the three algorithms with showing the procedure of each algorithm to compare between their performances. Section (4) includes typical simulation results for the three decoders. Also, comparison between the three decoders is shown with respect to memory usage and delay time. Finally, conclusion and future work are presented in Section (5).