Efficient system traversal and property verification by exploiting circuit locality

Bugs in hardware cost money. Whenever an error creeps into a design, time and money must be spent to locate the problem and correct it. With the growing complexity of digital systems, and the tremendous pressure for early-time-tomarket schedules, the need for verification tools that can help designers to catch bugs at an early stage in the design process cannot be overemphasized. Statistically, verification takes nearly 75% of the design time. Traditional methods of verification are empirical in nature and are based on extensive simulation of hand-written or automatically generated diagnostic test vectors. Although, provably effective in early stages of the debugging process, their effectiveness drops quickly along the maturity of the design. Hence, functional verification has problems in catching the corner cases, therefore formal verification complements it in order to cope up with the design growth. In formal verification efficient search procedures are used to automatically determine whether the state space of a design satisfies an abstract logical specification (properties). In general, reachability analysis is known to be a key component of formal verification. For large classes of properties, verification can be reduced to reachability analysis. The term reachability analysis corresponds to the set of states that can be reached by means of traversal step from a set of defined initial states. The typical problem of such analysis is that after some steps of traversal, the system can not handle the overwhelming state space anymore and hence the memory overflow problem occurs. There is constant work on finding algorithms to reduce the memory requirement bottlenecks. One such approach to reduce the memory requirement is the symbolic representation of the state space, where Binary Decision Diagrams (BDDs) are used as data structures. Therefore, the state space traversal is then carried out symbolically by BDD manipulations. However, large designs may require many millions of BDD nodes that also often causes memory overflow. This phenomenon is well known as BDD blowup. There are several proposed solutions to deal with the large memory requirements of BDDs. One such novel proposal is to partition the BDD into two or more pieces and handle them separately for further state space traversal. Although there exists a few algorithms to partition the actual BDD, the lack of optimization in these algorithm are often responsible for the excessive growth of the BDDs resulting in slow verification or memory problems. This thesis deals with intelligent heuristics that optimizes the partitioning. The thesis contributes two heuristics, MinOverlap for the full validation approach and Guiding for a fast falsification approach. To validate a design completely which is relatively large, a divide-and-conquer approach is state-of-the-art. It partitions the original BDDs that exceeds a threshold size of node count and deals with the partitions separately. The major problem of this methodology is revisiting of states in different partitions and is known as state space overlap that results in redundant computations. The MinOverlap algorithm aims at a reduction of state space overlap of different partitions that minimizes the redundant computation and decreases the verification time. The reduction is achieved automatically by means of collecting the information in the form of influence table of state variables by exploiting the design’s transition relation. Similarly, to verify a property faster, guiding by means of providing hints is state-of-the-art technique. However, this is not fully automatic and requires expert intervention. The Guiding algorithm in this thesis aims at steering the state space traversal algorithm in the direction of the target states automatically. It avoids the un-interesting state space saving memory and speeds up the finding of bugs. The guiding is realized by exploiting the property and the transition relation for information on target states, and utilizing them for the efficient guiding and steering the traversal automatically. The experimental results shows substantial speed up of the verification process by these heuristics.