On-Chip Reliability Monitor for Measuring Frequency Degradation

In the aging tolerant digital circuit design, precise measurement of digital circuit degradation is a kind of key aspect. In this project, we will build a type of digital on-chip reliability monitor for measuring degradation of frequency in high-resolution for digital circuits. This technique is made by measuring the beat frequency of two ring oscillators, which has one stressed and another unstressed for reference, to get the sensing resolution which is 50 times higher than the conventional methods. In our design, we are using the 1 V, 32 nm CMOS technology to build this frequency degradation monitor scheme,. INTRODUCTION As the CMOS process technology currently growing in the scale, it is becoming more difficult to design the reliable circuit while dealing with each node. Different kinds of reliability problems, such as TDDB (time-dependent dielectric breakdown), BTI(bias temperature instability), HCI(hot carrier injection) is happening more frequently than before in the CMOS devices. NBTI(negative bias temperature instability)is one of the most pressing of these challenges. [1]-[4] It is resulted from the trap generation in the pMOS transistors’ Si-SiO2 interface, whose structural mismatch caused the dangling bonds. The dangling Si bonds will be changed to the Si-H bonds, which are easier to break when using the device, leading to the H atoms becoming gate oxide and broken bonds becoming traps, which caused the driving current of pMOS transistors getting lower. When the device is stressed, the value of the threshold voltage Vtp is increasing in its absolute value (|Vtp|), which indicates the NBTI effect. When the stress condition is removed(Vgs=0), the device is reaching the recovery or passivation phase, causing the H atoms diffuse back towards the Si-SiO2 interface, and the broken Si-H bonds will be annealed, and thereby the value of Vtp is decreased. ([5]-[11]) In order to know the NBTI effect on the circuit, we need to accurately measure the reliability of the circuit. There are some types of conventional ways to measure the reliability, such as device probing or onchip ring-oscillator frequency monitoring, but those methods need an extensive measurement setup or have some limitations of the sensing resolution. [12][13] Furthermore, it cannot acquire statistically large number of data points in different stress conditions, which is important in understanding the complexity of aging. In our project, we will build an on-chip reliability monitor which can improve the sensing resolution and monitor the aging effect precisely in digital circuits, and we will use HSPICE software simulation to validate the function of our design. DESCRIPTION OF SYSTEM MODEL THE SCHEME OF BEAT FREQUENCY DETECTION Fig.2. (a) Beat-frequency detection circuit for highresolution NBTI monitoring (b) Principles of the beatfrequency detection circuit (c) Comparison of frequency sensing resolution between conventional and proposed schemes, for 1% degradation, the sensing resolution of the circuit is 50 times higher than conventional circuit. Our design in detecting the frequency degradation consists of two ring oscillators and one phase comparator. We will stress only one in two ring oscillators in the stress period, and the other reference oscillator is unstressed. We use the supply voltage VDDSTR and 0V respectively for the stressed and unstressed oscillators in stress period, and use VDD-REF for both of them in measurement period. The reason that the supply voltage is set to 0V for reference oscillator in stress period is that it can prevent the device from aging. The phase comparator is used to measure the beat frequency which is defined by fstress-fref, where fstress and fref are the stressed and reference oscillator frequency respectively. After each stress period, the counter will get the output value N, and the beat frequency period is the same as the duration when there is one clock difference between the number of reference and stress pulses. The beat frequency has both the equation of N/fref and (N-1)/fstress. The counter output after stress has the value N’, and similarly the beat frequency after stress can be defined as N’/fref and (N’1)/f’stress. We can derive the frequency degradation equation (f’stress-fstress)/fstress=(N’-N)/(N’(N-1)). The advantage of this measurement is that it can achieve a high sensing resolution when there is only small frequency degradation. From fig.2, we can see that when there is only 1% frequency degradation, the counter output N will decrease by almost half of the total value. As for the previous techniques, only a single ring oscillator is used, so it cannot make comparison between the already stressed ring oscillator and the intact reference ring oscillator, and 1% degradation in ring oscillator frequency will only cause 1% change in counter output. [9] Frequency degradation which is caused by device aging is usually less than 10% [9], so we can use almost 90% of the code to detect the 10% change in frequency. By seeing the equation in fig.2(b), we can find that if the initial counter output value N is becoming larger, the sensing resolution will also increase. 2. ARCHITECTURE OF SILICON ODOMETER TEST CHIP Fig.3. Test chip architecture of silicon-odometer Figure 3 give us an illustration of the silicon odometer test chip architecture. The two ring oscillators are using the identical structures which both have 105stages, but they have different inputs. Because the output of these two ring oscillators serve as the differential input of phase comparators, the Process-VoltageTemperature (PVT) variations that affect both ring oscillators equally will be cancelled out. The phase comparator will generate the signal which shows the difference between the frequencies of stressed and reference ring oscillators, and some bubbles may appear in the output of phase comparator because of jitter effect, and it can be erased through the 5-bit majority voting circuit. The beat frequency detector will detect the pulse coming from the 5-bit majority voting circuit, and produce a DETECT signal, which will be sent to the counter to get the output, and sent to the register to reset the counter for the next measure cycle. The measured counter outputs will be used for calculating the frequency degradation.