Compound Semiconductor Based Tunnel Transistor Logic

In this invited talk, we introduce a new transistor architecture based on inter-band tunneling mechanism as a step towards exploring steep switching transistors for energy efficient logic applications. While others have researched on developing these transistors in the Si, Ge and their alloys, we have focused specifically on narrow gap compound semiconductor (CS) systems to develop tunnel transistors. We address the following topics regarding the CS-based tunnel transistor architecture: a) the choice of appropriate materials to tune the transfer characteristics over a specified gate voltage swing b) the characteristic screening lengths in these device essential for scaling, c) an effective way to estimate the switching speed of tunnel transistors, d) digital circuit design methodologies utilizing tunnel transistors. INTRODUCTION Continued miniaturization of the silicon CMOS transistor technology, has resulted in an unprecedented increase in single-core and multi-core performance of modern-day microprocessors. However, the exponentially rising transistor count has also increased the overall power consumption, making performance per watt of energy consumption the key figure-of-merit for today’s highperformance microprocessors. Today, energy efficiency serves as the central tenet of high performance microprocessor technology at the system architecture level as well as the transistor level ushering in the era of energy efficient nanoelectronics. Aggressive supply voltage scaling while maintaining the transistor performance is a direct approach towards reducing the energy consumption since it reduces the dynamic power quadratically and the leakage power linearly. To that effect, narrow gap compound semiconductor-based (e.g. indium antimonide, indium arsenide and InxGa1-xAs) inter-band tunnel transistor (TFET) architecture could enable the next generation of logic transistors operating below 0.5 V supply voltage. In this invited paper, we present a comprehensive study of the basic TFET architecture, the optimum materials choice to improve TFET performance, the advanced TFET architectures, the transient response of the TFETs in a digital circuit configuration, and, finally, embedded memory design strategy with TFET. INTER-BAND TUNNEL TRANSISTOR Inter-band tunnel field effect transistors (TFETs) with a gate modulated zener tunnel junction at the source have recently attracted a great deal of interest, both theoretically and experimentally [1]-[4]. Figure 1 shows a schematic of an n-channel TFET architecture which incorporates a highly doped p+ source region, a near intrinsic channel region and n+ drain region. The n-channel TFET operates on the principle of band to band tunneling of electrons across the source to channel tunnel junction under the influence of a gate electric field. The major advantage of the TFETs in comparison with the metal-oxide-semiconductor field-effect transistors (MOSFETs) is that the reverse biased tunnel junction in the former eliminates the high energy tail present in the Fermi-Dirac distribution of the valence band electrons in the p+ source region and allows sub-kT/q sub-threshold slope device operation over a certain gate bias range near the off-state. This allows TFETs to achieve, in principle, much higher ION-IOFF ratio over a given gate voltage swing compared to the MOSFETs, making the TFET architecture an attractive vehicle to implement low supply voltage (VDD) digital logic circuits. Figure 2 shows the transfer characteristics of a silicon (Si) double gate 30 nanometer Fig.1 (a) Schematic of a double gate inter-band tunnel transistor (TFET) architecture; (b) Energy band diagram illustrating the TFET ON and OFF state conditions Fig. 2 Transfer characteristics of 30nm gate length double gate silicon TFET and MOSFET at 1V supply voltage [4] CS MANTECH Conference, May 17th-20th, 2010, Portland, Oregon, USA gate length TFET benchmarked against a Si MOSFET of identical dimensions, both operating under 1V supply voltage. The very low off-state current of the TFET is set by the reverse bias saturation current of the p-i-n diode. Near the off-state, the TFET clearly exhibits < 60mV/decade which results in a vastly superior ION-IOFF ratio compared to the MOSFETs. However, the on current in a TFET is significantly lower than its MOSFET counterpart being limited by the low transmission rate of electrons across the reverse biased tunnel junction between the source and the channel. It is evident that narrow gap semiconductors such as Ge and InAs can significantly enhance the source side tunneling rate due to the combined effect of reduced barrier height and shorter tunneling distance in addition to the reduced tunneling mass. Figure 3compares the transfer characteristics of Si, Ge and InAs TFETs under various supply voltages. The InAs TFET shows the highest on current (275 μA/μm) at the lowest supply voltage of 0.25V with an ION/IOFF ratio exceeding 4x10. However, the InAs TFETs also exhibit strong ambipolar characteristics due to the tunneling of carriers from the drain into the channel at negative gate voltages. This warrants the need for other advanced tunnel transistor architecture in addition to introducing the narrow bandgap semiconductors to enhance its overall performance and its energy efficiency. We have recently fabricated a vertical InGaAs Tunnel FET by using a side gated structure. Fig 4 shows the SEM images of fabricated In0.53Ga0. 47As vertical TFET featuring gate airbridge and conformal high-k dielectric and metal gate stack on the sidewall. Fig. 5 shows the measured transfer and output characteristics of the 100nm channel length tunnel transistors at room temperature. The minimum current (“leakage floor”) at VDS = 50mV is only 40 pA/μm increasing to 6nA/μm at VDS = 0.75V. The corresponding on currents are 0.5μA/μm (linear) and 20μA/μm (saturation). This translates to Ion-Ioff ratio of ~ 10 and 3x10, respectively. Two distinct regions of operation are evident from the output characteristics – a reverse biased zener diode and a forward biased Esaki diode as a function of the gate voltage. Gated negative differential resistance (NDR) behavior in TFET output characteristics during drain-tosource forward bias operation confirm the inter-band tunneling process HETEROJUNCTION TUNNEL TRANSISTOR Careful benchmarking with the state-of-the art double gated Si NMOS transistors indicate that, the homojunction InGaAs Tunnel FETs of similar dimensions (Tsi, Tox) will still fall short in terms of performance. This is illustrated in Fig. 6, where our fabricated device as well as projected TFET performance is compared with both high Vt and low VT CMOS transistors. In order to enhance the tunnel transistor performance, we propose two advanced TFET device architectures: (a) δ-TFET with a 2nm thin heavily doped n-type (δ-N+) layer adjoining the source and (b) δHTFET with a thin (3nm) layer of narrow band-gap material Fig. 4 Schematic and tilted view SEM of a fabricated InGaAs Tunnel FET with gate length of 100 nm. [5] P+