Characterization of LOCOS and oxidized mesa isolation in deep-sub micrometer SOI NMOS processes

Device isolation is a very important component of VLSI manufacturing. In this work, an NMOS process and isolation test structures and devices were designed to characterize LOCOS and Oxidized Mesa isolation for use in SOI technology. For LOCOS, the key variables were the field-implant dose, stress-relief oxide thickness, field-oxidation time/thickness, silicon-film thickness, and field spacing. The four latter variables control the extent of lateral encroachment and stress-related oxidation effects. These parameters along with the field-implant dose, effectively controithe extent of lateral isolation and its effects on devices. The sidewall implant dose and oxidation thickness, which control 2dimensional charge sharing effects at mesa corners and the existence of parasitic devices, were the variables of interest for Oxidized Mesa isolation. Focusing on thin films, substrates with top layer silicon film thicknesses of 50nm and 90nm were used to fabricate arrays of isolation islands, diode structures, sidegating structures, and transistors of varied dimensions and geometries. LOCOS characterization began with the testing of and performing data analysis on the isolation islands to quantify design constraints on isolation in terms of leakage. Hoand and Colinge suggested that top layer silicon film thicknesses 2 150nm necessitated excessive oxidation times to achieve complete isolation[12,14]. Results showed this phenomenon not to exist with top layer silicon film thicknesses of 90nm and below, and presented in design space graphs defining allowable process and structure parameters leading to effective isolation. Thesis Supervisor: James Chung Title: Assistant Professor of Electrical Engineering Thesis Supervisor: Craig Keast Title: Director of Microelectronics Laboratory (ML), Lincoln Laboratory Acknowledgments I would like to express my deepest gratitude to Professor Jim Chung and Dr. Craig Keast for supervising this project, imparting your knowledge of the subject on me, and unknowingly giving me the ever so timely words of encouragement. Thanks to the staff of the Microelectronics Laboratory, Lincoln Laboratory for your patience in enduring the many questions which arose while learning my way around the clean room as well as when doing this thesis work. A special thanks to Dick, Bernie, Doug, Sandy, Kevin, Jim, Sue, Andy, Gwen, Bruce, Debbie, Bob, Jeff, and Johanna of Groups 87 and 23 for your added support. Gratitude also goes out to Jim's research group on campus, Eric, Jeff, Huy, Rajesh, Jung, Jee-Hoon, Jocelyn, Wenjie, and Ben for making my transition back to campus as smooth as possible. You all were a great help. Special thanks to the Black Graduate Student Association, BGSA, the staff of the Graduate office, and my other friends for being my family away from home and giving me the distractions which forced me to keep the much needed balance. Many thanks to my very close friends, Dee, Don, Nadine, Araba, Rob,,Pennis, LaCreis, Matt, Andy, Daniel, Nicole, Cheryl, Sheree, Sylvester, and Amy. Last, but certainty not least I would like to give a very special thanks to my family and loved ones for the emotional support you displayed since day one back in September, 1993. With the support and love from you that reached Massachusetts from Virginia, my stay was bearable. I dedicate this thesis to you, Betty, William, Deena, LaVerne, Kimberly, and Victor. This work has been sponsored by MIT Lincoln Laboratory.