Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

The main purpose of this paper is to achieve as low as possible leakage current (<inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ </tex-math></inline-formula>) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths <inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {eff}}$ </tex-math></inline-formula>, gate stacks, gate contact materials, and gate-sidewall spacers (<inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {sp}}$ </tex-math></inline-formula>). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length <inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {sp}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {HK}}$ </tex-math></inline-formula> is investigated to get low leakage current keeping <inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ </tex-math></inline-formula> as high as possible. Moreover, the effective channel length in subthreshold conduction (<inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {eff}}$ </tex-math></inline-formula>) is maintained greater than the gate length (<inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {g}}$ </tex-math></inline-formula>) and the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm {th}}$ </tex-math></inline-formula>) is adjusted by the proper metal gate work function. The performance of the proposed n- and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted <inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ </tex-math></inline-formula> is 17 pA/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m for n-FinFET and 14.7 pA/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> for p-FinFET which are the lowest leakage currents found in recent publications. The achieved <inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ </tex-math></inline-formula> ratio for both proposed devices is found to be <inline-formula> <tex-math notation="LaTeX">$12.3 \times 10^{6}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$11 \times 10^{6}$ </tex-math></inline-formula>, respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of <inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {sp}}=10$ </tex-math></inline-formula> nm and <inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {HK}}= 5$ </tex-math></inline-formula> nm. In addition, the short channel effects variations with <inline-formula> <tex-math notation="LaTeX">$\text{L}_{\mathrm {HK}}$ </tex-math></inline-formula> have been investigated.