Accurate Analog Synthesis Based On Circuit Matrix Models

Automated synthesis is imperative for the rapid design of analog circuits. Knowledge based and optimization based methods have emerged to provide solutions for analog synthesis, especially for device sizing. Posing analog sizing as a constrained optimization problem facilitates the application of many well developed algorithms for this purpose. All optimization based sizing methods are based on the common thread of design space exploration and performance evaluation. Design space exploration is required for finding design solutions satisfying the given performance constraints. During exploration a performance evaluator is required to determine the quality of the examined solutions. The efficiency of the sizing procedure is completely dependant upon the speed of the performance evaluator. Some of the recently proposed techniques construct models for performance parameters in the circuits design space and use them for performance prediction. Methods based on this principle can be collectively called Performance Macromodeling methods. Avoiding simulation gives the advantage of fast synthesis to these methods at the expense of moderate modeling errors. Performance macromodeling methods can rapidly explore the design space and offer sizing solutions in a reasonable time. However, they are successful only for synthesizing those specifications who models have been developed. In this dissertation we propose performance prediction using Circuit Matrix Models to estimate the performance of analog circuits. Using these models the entire a.c. behavior of the circuit is captured. With the use of matrix models, the limitation that a circuit can by synthesized for the modeled performance specifications is eliminated. Any linear performance characteristic can be calculated from the models. Analog circuits need to be designed with high accuracy. With circuit matrix models it is seen that performance prediction is precise and synthesized circuits are very accurate. We then develop techniques to expedite synthesis by making matrix model evaluation extremely fast. The first technique uses hashing for obtaining the desired speedup. This technique takes advantage of matrix elements being dependent on a subset of design variables. Design sub-spaces are visited several times when the entire space is being explored in a synthesis run. Hash tables save the matrix element values computed in the visited subspace and reuse them when that subspace is visited again. This saves a large amount of recomputations and imparts speedup to the synthesis procedure. i The second technique has a nearest neighbor searching algorithm at its core. It uses values at design points visited to incrementally compute values at neighboring design points. A first order Taylor series approximation is sufficient for such incremental computation and this makes performance estimation procedure extremely fast. A balanced box decomposition tree data structure makes detecting exact or approximate neighbors quite efficient. The circuit design variables form the dimensions of the search space. The distance metric for neighbor computation is modified by considering sensitivity of matrix elements to the search space dimensions. Using this method, very few computations are required during the synthesis process. Layout parasitics are detrimental to the performance of analog circuits. Considering their effects early in the design flow is essential for achieving designs with parasitic closure. We have developed circuit matrix models inclusive of parasitic effects. The models use area and perimeter as predictor variables and can be used to compute parasitic inclusive matrix element values for many geometries. Thus, the most suitable geometry for component modules is selected dynamically by the optimizer as a part of synthesis. Operational amplifiers and filter topologies have been synthesized as a part of this work. The optimization objectives for analog circuits can be conflicting and often for improving a particular performance several others have to be sacrificed. Considering the performance tradeoffs is quite important for such multi-objective optimization problems. The developed circuit matrix models have been used to generate parasitic-aware pareto-optimal performance curves. The method stores an archive of non-dominated performance points and the corresponding design points that achieve this performance. This can be used for determining the limits of achievable performance for a given topology as well as for sizing.