Digital control of utility and parallel connected three-phase PWM inverters

This thesis is mainly concerned with fundamental investigations into digital current control of utility-connected PWM inverters with output LCL filter whose capacitors are connected to the dc link rails. The thesis also presents analysis and evaluations of alternative three-level PWM inverters and alternative filter configurations. Additionally, the thesis presents investigations into parallel-connected PWM inverters. Various pulse width modulated (PWM) controllers including hysteresis and linear controllers have been reviewed. Hysteresis controller combines the current control task with the voltage modulation task. This makes the hysteresis controller unable to dampen resonance when used with an LCL filter and also unable to reject utility disturbance. On the other hand, linear controllers separate the current control task from the voltage modulation task. This allows exploitation of the advantages of open loop modulators including carrier based PWM (CB-PWM) and space vector modulation (SVM) such as constant switching frequency and well-defined harmonic spectrum. A linear digital current controller with CB-PWM has been analysed and designed, aided by computer simulation using Matlab Simulink. The controller structure is based on two feedback loops of the output current and the filter capacitor current, which has been shown to provide extra degree of freedom, and enables better controller performance compared to controllers with a one-feedback-loop structure. Additionally, the controller incorporates a feedforward loop to compensate for utility voltage disturbance. The effect of the processor computational time delay on system stability has been investigated using the modified Z-transform. The investigations have shown that the optimum sampling rate should be twice the PWM carrier frequency, and the optimum sampling instant should be synchronized with the peaks of the PWM carrier in order to minimize the effect of the current switching frequency ripple disturbance. However, in practice due to computational time delay, it is not possible sample at the peaks of the PWM carrier, which may result in distortion in the output current due to sampling of the switching frequency ripple. Hence a novel nonlinear time delay compensator that accurately calculates the variation in the capacitor current during time has been proposed and demonstrated to be effective in rejecting the switching ripple disturbance. In addition, a novel digital sampling scheme in which the sampling is delayed by half a PWM carrier cycle been proposed. Using this scheme combined with a time delay state observer, better switching disturbance rejection was achieved. The proposed current controller has been experimentally implemented using a digital signal processor DSP and the results have shown that the quality of the output current complies with the standards on harmonic limits for electricity distribution systems. An alternative three-level inverter structure has also been studied in order to reduce switching frequency ripple and hence the inductor cost. Simulation results have shown that filter inductor ripple current of a three-level inverter is on average half that of a two-level inverter but at the cost of extra power switches. A comparative study between different filter structures has also been carried out. It has been shown that connecting the capacitors to the dc-link decouples the phase and removes neutral voltage fluctuations with respect to the dc link. On the other hand, connecting the filter capacitor in delta or star, halves the inductor ripple current. Wireless control of parallel-connected PWM inverters using frequency and voltage drooping has been investigated to assess hardware and software requirements to implement such a system. The results have shown that this controller forces the inverters to share active power equitably, but good reactive power sharing requires a higher output inductor than that used in the current system.