PANEL: analog intellectual property: now? or never?

There is considerable controversy as to whether or not the trade in analog intellectual properties (IP) will ever represent a viable business opportunity. One school of thought suggests that analog design will always be too specialized to constitute a major market; another school of thought says this will be big business if certain nagging technical problems are solved. While the demand for analog interface components is high, the ability of IP creators to render it in a tradable format is limited. And the ability of digital design teams to successfully utilize analog IPs — without a considerable amount of handholding — is similarly limited. EDA tools here are looked upon as both culpable and offering the best hopes for the future. This panel of experts — representing analog designers, analog EDA tool providers, silicon foundries and analog IP vendors — bring their own points of view on some of the business and technology issues which need to be resolved to provide the context for analog IP development and trade. Among the open questions: • Is IP created and validated within the design environment for re-use a more productive approach than imported IP? How many 'traditional' analog designers would admit they are still using kit parts and breadboards — maybe even SPICE and manual IC layout techniques — today in their every-day job? • What CAD tools are needed to help analog designers? Are newly emerging EDA technologies, designed to enhance analog design productivity, maturing rapidly enough to be accepted by designers? • What is the future of analog designs at the very low voltageswings coming with sub-100nm CMOS? • Though silicon foundries need to process a wide set of external IP offerings in order to allow their users to build complete systems, are foundries seeing enough activity in analog IP designs to justify specialized fab runs or the kind of process tuning that would allow analog and digital IPs to coexist on the same chip? • How likely – and how soon – can we get to analog IP development and trade? Technology Issues Process scaling has enabled unprecedented levels of integration. The most advanced systems-on-chip (SoC) now embodies 200 million transistors on one IC, and that number is expected to increase exponentially over the next decade. Rather than create new designs from a blank slate, design teams are reusing previously-designed blocks and importing the work of other design teams into their efforts. As a consequence, analysts have predicted an exponential growth in the market for IPs — that functional IC blocks will be traded externally, and well as between design departments of a large IC company. Though ARM and MIPS CPU cores now constitute the largest number of blocks traded between companies, analysts project that future trade will include other CPU and DSP cores, memories, communications protocol controllers and multimedia decoders, as well as bus interface components. With more and more SoC makers hoping to include analog functional blocks as a means of differentiating their designs, it is therefore tempting to believe that analog IP can be created, traded and integrated with the same tools and methodologies with which digital IP are moved about. But analog has a different heritage and calls forth a different set of design issues. The simple act of moving a high-speed digital signal off-chip (the use of an analog line driver) can produce more heat and noise, and utilize more power than the SoC design team is prepared to cope with. The problem becomes more complex with the sophistication of the analog blocks that are incorporated: cable drivers and bus interface components present one level of difficulty; operational amplifiers and phased locked loops present another level; data converters and RF interfaces put most digital design teams into uncharted territory. Currently, every manufacturer who licenses an analog IP must provide an engineer (or an engineering team) along with the IP just to get it working properly in the customer’s design. There are two reasons for this: First, analog designs are typically processspecific and do not scale with shrinking CMOS geometries. Unlike digital circuits that can appear to gain performance in a process shift from (say) 0.18-microns to 0.13-microns, analog circuits can loose performance and, in some case, cease working entirely. Dynamic range is severely curtailed with submicron CMOS, and parasitics (like interconnect resistivity and gate capacitance) play a much larger role. Analog functions must frequently be entirely redesigned in the move from one process environment to another, but there are limitations on the extent to which redesign will help. Participants in panels at this year’s International Solid States Circuits Conference (ISSCC), for example, were openly terrified of the leakage currents that would appear at 100and 90-nm CMOS geometries. Second, analog functional blocks — performing well in isolation — will often be disabled on a digital SoC substrate. Digital switching noise, bubbling up through the substrate, is frequently identified as the culprit. Newly emerging EDA technologies, designed to enhance analog design productivity, provide some relief. There are two sets of tools needed: One set would enable designers — regardless of whether their primary expertise is analog or digital — to create analog IP cell blocks more rapidly. The expression “analog synthesis,” analysts agree, has been abused because it will not (on the near horizon) offer the same kind of movement from highlevel language description to gate-level implementations. However, there are many new-generation model-generating, circuit-resizing and optimization tools — many available from silicon foundries — that will speed the process of moving analog functions from one geometry to another. Some new tools provide “design tuning” that allows IPs to verified within the design environment where they are created. The second set of tools — 12.1