A CMOS Broadband Amplifier with Flatness Bandwidth for UWB Application

In this paper, a broadband distributed amplifier (DA) is presented. This circuit adopts two-stage cascode gain cell and m-derived matching section to enhance the gain and bandwidth performances. The series inductor placed at the inter-stage of the cascode cell can increase gain without any additional power consumption. A parallel resistor between the two-stage also enhances the gain flatness at low frequencies. The broadband DA is fabricated by a standard 0.18 μm CMOS process. The simulated results demonstrate that it achieves a power gain of around 10 dB, input and output return losses better than 8.3 and 8.56 dB, respectively. Isolation of this DA is better than 30 dB. The noise figure is around 5.23 dB. INTRODUCTION A distributed amplifier is commonly applied to high-speed data links, satellite communications, high-resolution imaging system, broadband optical communication, and ultra-wideband system. Thanks to the distributed architecture, it provides such performance by absorbing the parasitic capacitances of parallel gain stages into an artificial transmission line, which not only results in the gain flatness and uniformity, but also lets input/output match within the bandwidth of operation [1]. Although conventional DAs can achieve a broadband bandwidth, its gain is not high because of the additive gain mechanism. In order to improve the gain of the DA, a cascade of inductively coupled common-source gain cells was proposed [2]. The DA uses a cascade gain cell to increase the gain and m-derive matching sections to reach input matching lower than -8 dB, and contains the gain 7.3±0.8 dB [3]. Besides, there are a lot of methods to improve the performance of DA. A CMOS DA with extended flat bandwidth and improved input matching by using gate lines and coupled inductors was be presented, and its input and output return losses are lower than 16 and 18 dB, respectively [4]. In [5] and [6], the DAs used four and five gain cells to achieve high gain and bandwidth flatness. In this paper, a two-stage cascode gain cell with a series inductor extends the bandwidth, and the parallel resistor between two stages enhances the gain flatness at low frequencies. CIRCUIT DESIGN DAs can achieve broadband bandwidth because of the distributed architecture. A conventional DA in Fig. 1 consists of an input and an output transmission lines coupled by the transconductances of the MOSFETs. The transmission lines are formed by using series inductors and gate-to-source capacitances of the transistors. In this topology, the input and output parasitic capacitances are absorbed in the distributed structures, which composed by these series inductors. Due to the distributed structure, the input and output signal can be not only separated obviously, but also enhance the isolation. The gain G of the conventional distributed amplifier has been analyzed in [2], [9], by 978-1-4673-5225-3/14/$31.00 ©2014 IEEE 2 2 n g Z Z m 0g 0d G = 4 (1) where n is the number of the gain stages, gm is the transconductance of each gain cell, and Z0g and Z0d are the characteristic impedance of input line and output line, respectively. From equation (1), when the Z0g and Z0d are fixed to a certain value, the gain G of DA is affected by gm and n. θrd ln θrg N = opt θ θrg rd ⎛ ⎞ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ (2) Where θrd and θrg are real parts of the gate and drain line propagation constants, respectively. There is no limit on the number of stages in a DA with lossless artificial lines. However both gate and drain artificial lines are lossy in practice. Therefore, there is an optimum value for the number of stages, which is given by [4], as described in (2). Although the gain can be increased by number of stages before it reaches a maximum number, as given in [2] and [9], limited by the increasing losses of the artificial transmission lines, it results in larger die area and higher power consumption. Fig. 1 A conventional distributed amplifier topology Fig. 2 Schematic of the proposed DA In this work, the CMOS DA was designed using two cascade gain cells, which provides high available gain, bandwidth, improves input-output isolation, and variable gain-control capability. The proposed DA uses m-derived sections [3] to achieve input matching, and the series-peaking inductor (L4) in gain cell can extend the bandwidth without any power consumption [4]. The parallel resistor between two gain cells can enhance the gain flatness at low frequencies. The simulation gain versus different parallel resistances is shown in Fig. 3. It can see obviously that as the resistance becomes larger, the flat gain response is achieved at low frequencies. In this work, 36 ohm is chosen for the resistance to obtain a flat gain response. The L1, C1 and C2 (m-derived matching sections) are used to implement the input matching network. And the output matching network is designed by a buffer amplifier and L3. The resistors Rb in the body of transistors M1-M4 are used to increase the overall gain in the circuit, shown in Fig. 4. The CMOS distributed amplifier design uses two stages to enhance the total gain with reasonable die area and small power consumption. Fig. 5 shows its microphotograph, and it consumes a chip area of 0.93 × 0.84 mm. 0 5 10 15 20 -20 -10 0 10 20