Miracle-dz/UniFAR-FTUs huggingface dataset:
CMOS-Based Multifrequency Impedance Analyzer for Biomedical Applications

In this paper, we present a monolithic microsystem, which can perform bioimpedance analysis and electroimpedance tomography measurements as well as record electrocardiogram signals. In contrast to a full analog lock-in approach, a mixed analog/digital solution is adopted. The proposed solution has been designed, implemented, and tested using a commercial 0.35-μm CMOS technology. The tuning range of the signal generator and the detector is from 10 kHz to 10 MHz in 1 kHz steps. The circuit ensures a CMRR of 81 dB@10 kHz, which increases to 84 dB@10 MHz. The measured equivalent input noise power spectral density is en = 2.57 nV/√Hz at 10 kHz in the worst case, close to the 1/f corner frequency. It decreases until en = 1.8 nV/√Hz at 1 MHz and en = 1.9 nV/√Hz at 10 MHz. Measurements of a reference RC network performed with the proposed monolithic solution and compared with a Keysight E4980A Precision LCR Meter shows a maximal relative error of 0.8% over the whole operating frequency range.
Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression

Convolutional neural networks (CNNs) are rapidly gaining popularity in artificial intelligence applications and employed in mobile devices. However, this is challenging because of the high computational complexity of CNNs and the limited hardware resource in mobile devices. To address this issue, compressing the CNN model is an efficient solution. This work presents a new framework of model compression, with the sparseness ratio allocation (SRA) and the neuron re-pruning (NRP). To achieve a higher overall spareness ratio, SRA is exploited to determine pruned weight percentage for each layer. NRP is performed after the usual weight pruning to further reduce the relative redundant neurons in the meanwhile of guaranteeing the accuracy. From experimental results, with a slight accuracy drop of 0.1%, the proposed framework achieves 149.3× compression on lenet-5. The storage size can be reduced by about 50% relative to previous works. 8–45.2% computational energy and 11.5–48.2% memory traffic energy are saved.
Boosted Convolutional Neural Networks for Motor Imagery EEG Decoding with Multiwavelet-based Time-Frequency Conditional Granger Causality Analysis

Decoding EEG signals of different mental states is a challenging task for brain-computer interfaces (BCIs) due to nonstationarity of perceptual decision processes. This paper presents a novel boosted convolutional neural networks (ConvNets) decoding scheme for motor imagery (MI) EEG signals assisted by the multiwavelet-based time-frequency (TF) causality analysis. Specifically, multiwavelet basis functions are first combined with Geweke spectral measure to obtain high-resolution TF-conditional Granger causality (CGC) representations, where a regularized orthogonal forward regression (ROFR) algorithm is adopted to detect a parsimonious model with good generalization performance. The causality images for network input preserving time, frequency and location information of connectivity are then designed based on the TF-CGC distributions of alpha band multichannel EEG signals. Further constructed boosted ConvNets by using spatio-temporal convolutions as well as advances in deep learning including cropping and boosting methods, to extract discriminative causality features and classify MI tasks. Our proposed approach outperforms the competition winner algorithm with 12.15% increase in average accuracy and 74.02% decrease in associated inter subject standard deviation for the same binary classification on BCI competition-IV dataset-IIa. Experiment results indicate that the boosted ConvNets with causality images works well in decoding MI-EEG signals and provides a promising framework for developing MI-BCI systems.
Video Service Function Chaining with a Real-time Packet Reordering Circuit

There is a growing demand for more complex services in cloud computing. To provide high-intensity cloud services optimized for each user's purpose, we propose a technique for chaining image processing functions utilizing a CPU-field programmable gate array (FPGA) coupled server architecture. Packet reordering is essential for ensuring the correctness of processing images when we handle them via the cloud network. In order to ensure the correct order of image data and combine multiple image processing functions on the network, the most important requirement for server nodes is low latency. Our contribution is to present a real-time packet reordering circuit that provides ultra-low latency with a memory-saving architecture. We examined the efficiency of our idea with the histogram of oriented gradients as an offloaded image processing function. The results show that the proposed architecture can transfer image data encapsulated in packets about 2,370 times faster than the conventional CPU-FPGA architecture with external memories. Moreover, we confirmed the robustness of the proposed circuit in that the performance degrades less than 3.7% under the worst-case condition that 90 percent of the packets are randomly swapped at a 40-Gbps transfer rate.
Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels

Low-density parity check (LDPC) codes are an attractive error correction scheme for ensuring data integrity in new generation of NAND flash memories. A quick assessment of the iterative decoders for LDPC codes reveals a wide range of varying complexities. The simple Bit-Flipping (BF) and binary-message-passing algorithms such as the Gallager A/B algorithms occupy one end of the spectrum, while Belief Propagation (BP) and A Posteriori Probability (APP) decoders lie at the other end. The gamut of existing decoders filling the intermediate space can simply be understood as the implementation of BP (and its variants, such as the min-sum algorithm) at different levels of message precision. Decoders with low-precision messages are desirable because of their low complexity and power efficiency, but in such decoders it is highly nontrivial to prevent performance degradation known to as error floor and to guarantee fast convergence to a codeword. In this paper we present our results on a new class of low-complexity iterative decoders for flash memory channels. They involve two main innovations: global computation and randomness. Our decoding algorithm, Probabilistic Gradient Descent Bit-Flipping (PGDBF) is motivated by the analogy between Tanner graphs and the graphical models used in statistical mechanics, and prescribe a rule for flipping a bit based on the so-called energy function and a binary random sequence associated to that bit. Energy function is computationally simple, but involves all the bits. We present the PGDBF algorithm analysis, explain how it benefits from global computation and randomness, and present the hardware synthesis results as well as comparisons with the state-of-the-art decoders.
Reconfigurable Voltage/Current Readout Instrumentation Amplifier for Cardiovascular Health Monitoring

A single common instrumentation amplifier (IA) architecture to measure voltage and current input signals is presented and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) sensing. The reconfigurable IA switches between the voltage and current sensing modes in timely multiplexing manner faster than ECG and PPG bandwidth. A design to reduce noise is applied in the current sensing mode. The designed IA is implemented using CMOS 180-nm process technology. The current consumption, voltage noise, and current noise are measured as 45 μA, 2.7 μVrms, and 384 pArms, respectively. In addition, the measured PPG signals are compared with/without the proposed noise reduction scheme.
Analysis and Implementation of Block Least Mean Square Adaptive Filter using Offset Binary Coding

In this paper, we present a new mathematical analysis and implementation of block-least-mean-square (BLMS) for finite-impulse-response (FIR) adaptive filter using offset binary coding (OBC). The proposed approach is based on distributed arithmetic (DA) in which OBC combination of input samples are stored in look-up-table (LUT). The filter output and weight adaptation terms are computed by successive shift-and-accumulation (SA) of LUT contents. The recursive use of OBC scheme have reduced the complexity of LUT. Also, we suggested new structure for LUT update unit which involve fewer adders. In addition, a new SA unit is proposed to include the offset term in OBC representation of weights and error signals. Application Specific Integrated Circuit (ASIC) synthesis results show that the proposed scheme utilizes 51.73% less area, consumes 48.32% less power, provides nearly 2.33 times higher throughput for 32nd order filter with block length of 4 over the best existing scheme.
An Energy-Efficient 11-bit 10-MS/s SAR ADC with Monotonie Switching Split Capacitor Array

In this paper, a 11-bit 10MS/s asynchronous differential SAR ADC is presented. A monotonic switching procedure is used with a split capacitor structure to reduce the area and energy consumption. A digital calibration method is proposed to minimize the effect due to capacitor mismatch and the bridge parasitic capacitor. The SAR ADC is implemented with a 0.18um CMOS technology. At a 1.8-V supply and 10 MS/s, the ADC achieves an SNDR of 65.2 dB and consumes 0.62 mW, resulting in a figure of merit (FOM) of 42.8 fJ/conversion-step.
Spatio-temporal compressed sensing for real-time wireless EEG monitoring

Wearable electronics capable of recording and transmitting biosignals can provide convenient and pervasive health monitoring. The wireless transmission bandwidth limits the number of recording sites that can be monitored at one time. Compressed sensing (CS) is a promising approach that uses computationally efficient encoding to reduce the number of samples that are transmitted wirelessly, allowing more channels to be monitored over a transmission channel. The rakeness CS approach shows improved performance for higher compression rates, but in prior work it has only been evaluated for single channel data. We analyze the fidelity tradeoffs for compressed sensing implemented on a mobile electroencephalography (EEG) system. We propose several methods for spatiotemporal encoding in rakeness CS and evaluate the performance using a spontaneous EEG dataset recorded during moderate movement. Reconstruction performance depends strongly on the compression ratio and weakly on the method of spatiotemporal encoding. This suggests weak spatial correlation between the different channels of EEG data, which were recorded in an experiment involving self-initiated movement.
A Same-Channel Full-Duplex Receiver Using Direct RF Sampling

Time selective sampling is capable of eliminating strong interference signals without requiring a high linearity receiver front-end. This can be used to implement a full-duplex transceiver front-end by sampling the weak received signal at the zero-crossings of the strong transmitted signal. In this work, we propose a circuit technique to directly sample the received RF signal at the antenna port by exploiting implicit voltage-to-delay conversion occurring in a full-duplex system. The sampler is implemented in a 65 nm CMOS process, and simulation results show a sensitivity of −67 dBm in the presence of a +5.5 dBm Tx signal. The received signal has a 10 MHz bandwidth, and the overall receiver consumes 33.2 mW from a 1.2 V power supply.
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure

Digital filters based on stochastic computation have recently gained considerable attention because the stochastic computation attains significant reduction of hardware complexity of digital filters compared with the classical deterministic binary computation-based filters. For stochastic IIR filters, Liu and Parhi proposed an elegant method that achieves high precision by means of the normalized state-space lattice structure. This paper extends the result and presents stochastic state-space IIR filters with higher precision than the conventional method. Instead of using the normalized lattice structure, our method makes use of the minimum roundoff noise structure in realizing stochastic state-space filters, leading to further improvement of arithmetic precision of IIR filtering compared with the conventional method. Experimental results show that our method gives higher signal-to-error ratio at the filter outputs than the conventional method.
RNS Hardware Matrix Multiplier for High Precision Neural Network Acceleration: "RNS TPU"

An arithmetic circuit is introduced that performs efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications. The circuit is comprised of a plurality of two-dimensional systolic arrays of multiplier-accumulators; these systolic arrays are connected to form a hardware matrix multiplier which processes data using high precision, fixed-point RNS arithmetic. The matrix multiplier takes advantage of the carry-free properties of RNS arithmetic by partitioning each RNS digit into its own dedicated matrix multiplier unit. By operating a plurality of digit matrix multipliers in parallel, a suitable RNS word size is realized. Each partitioned digit matrix multiplier processes a plurality of product summations, or dot products. After dot product summation is complete, the matrix multiplier transfers each summation to a normalization pipeline unit. The systolic architecture favors a narrow RNS digit encoding, so each digit matrix multiplier is realized in minimal IC area, using fast adders and multipliers. These features and others result in greater speed and efficiency versus binary fixed-point arithmetic, especially when comparing high precision implementations. Using an FPGA based implementation and analysis, the RNS matrix multiplier performs matrix multiplication of 32.32 fixed-point arithmetic 7 to 9 times more efficiently than a binary matrix multiplier provided the dimension of the matrices multiplied are sufficiently large.
Post-drought Resilience After Forest Die-Off: Shifts in Regeneration, Composition, Growth and Productivity

A better understanding on the consequences of drought on forests can be reached by paying special attention to their resilience capacity, i.e., the ability to return to a state similar to pre-drought conditions. Nevertheless, extreme droughts may surpass the threshold for the resilience capacity triggering die-off causing multiple changes at varying spatial and temporal scales and affecting diverse processes (tree growth and regeneration, ecosystem productivity). Combining several methodological tools allows reaching a comprehensive characterization of post-drought forest resilience. We evaluated the changes in the abundance, regeneration capacity (seedling abundance), and radial growth (annual tree rings) of the main tree species. We also assessed if drought-induced reductions in growth and regeneration of the dominant tree species scale-up to drops in vegetation productivity by using the Normalized Difference Vegetation Index (NDVI). We studied two conifer forests located in north-eastern Spain which displayed drought-induced die-off during the last decades: a Scots pine (Pinus sylvestris) forest under continental Mediterranean conditions and a Silver fir (Abies alba) forest under more temperate conditions. We found a strong negative impact of a recent severe drought (2012) on Scots pine growth, whereas the coexisting Juniperus thurifera showed positive trends in basal area increment (0.02 ± 0.003 cm2 yr-1). No Scots pine recruitment was observed in sites with intense die-off, but J. thurifera and Quercus ilex recruited. The 2012 drought event translated into a strong NDVI reduction (32% lower than the 1982–2014 average). In Silver fir we found a negative impact of the 2012 drought on short-term radial growth, whilst long-term growth of Silver fir and the coexisting Fagus sylvatica showed positive trends. Growth rates were higher in F. sylvatica (0.04 ± 0.003 cm2 yr-1) than in A. alba (0.02 ± 0.004 cm2 yr-1). These two species recruited beneath declining and non-declining Silver fir trees. The 2012 drought translated into a strong NDVI reduction which lasted until 2013. The results presented here suggest two different post-drought vegetation pathways. In the Scots pine forest, the higher growth and recruitment rates of J. thurifera correspond to a vegetation shift where Scots pine is being replaced by the drought-tolerant juniper. Conversely, in the Silver fir forest there is an increase of F. sylvatica growth and abundance but no local extinction of the Silver fir. Further research is required to monitor the evolution of these forests in the forthcoming years to illustrate the cumulative impacts of drought on successional dynamics.
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs

FM-index is an efficient data structure for string search and is widely used in next-generation sequencing (NGS) applications such as sequence alignment and de novo assembly. Recently, FM-indexing is even performed down to the read level, raising a demand of an efficient algorithm for FM-index construction. In this work, we propose a hardware-compatible Self-Aided Incremental Indexing (SAII) algorithm and its hard-ware architecture. This novel algorithm builds FM-index with no memory overhead, and the hardware system for realizing the algorithm can be very compact. Parallel architecture and a special prefetch controller is designed to enhance computational efficiency. An SAII-based FM-index constructor is implemented on an Altera Stratix V FPGA board. The presented constructor can support DNA sequences of sizes up to 131,072-bp, which is enough for small-scale references and reads obtained from current major platforms. Because the proposed constructor needs very few hardware resource, it can be easily integrated into different hardware accelerators designed for FM-index-based applications.
Efficiency Model of Fully-Integrated Boost DC-DC Converters

This paper introduces a model for fully-integrated dc-dc converters that takes both resistive and capacitive losses into consideration. The parasitic elements of the inductor, which become crucial when using integrated inductors, are also taken into account. Different tradeoffs are studied and highlighted. Three boost converters are designed in TSMC 65-nm technology using integrated chamfered inductors. The simulation results are in good agreement with the proposed model.
A regularized fusion based 3D reconstruction framework: analyses, methods and applications

Recent developments in depth sensing technologies enabled mobile robots to perceive surroundings with high accuracy. Robotic applications, equipped with depth perception technology, enable the capability of autonomous navigation to self-driving cars, assist in critical surgical procedures, or reconstruct the 3D model of a potentially hazardous environment. There exists a variety of 3D sensors ranging from highly accurate laser-based range sensors to low-range active depth cameras; the selection of a 3D sensor, however, directly affects the capabilities of robotic applications to perceive surroundings. Unlike self-driving autonomous vehicles, which are equipped with high-cost LiDAR 3D sensors to ensure safety, mobile robots are usually equipped with low-cost active or passive depth sensors. This means that acquired depth information from low-cost 3D sensors is prone to accumulating estimation noise. In principal, existing 3D reconstruction frameworks employ multiple instances of erroneous depth samples in an incremental fashion to produce high-quality 3D models. In this thesis, the research objective is focused on reducing the effects of error-prone depth information by employing a proposed 3D reconstruction framework capable of reducing accumulated noise, using a regularizing 3D integration system. The underlying principal of existing state-of-the-art volumetric reconstruction techniques is unchanged since the introduction in 1996. The novelty of the proposed framework lies in the use of a prior smoothing constraint that represents, on a small-scale, that the surface of the perceived object is smooth. The application of this smoothing constraint on depth information, acquired from low-cost 3D sensors, can enhance the quality of 3D information without sacrificing fine details in surface geometry. Critical experimentation and empirical evaluation of the new reconstruction framework have shown a significant increase in accuracy and quality of reconstructed shapes compared to state-of-the-art methods. Furthermore, by quantitative assessments it has been observed that
A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications

This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is −114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than −51.3 dBc.
Niji: Bitcoin Bridge Utilizing Payment Channels

Bitcoin's enormous success has inspired the development of alternative blockchains, such as consortium chains. Several cross-chain protocols have been proposed as ways of connecting these universes of individual blockchains in a distributed and secure manner. In this paper, we present Niji, a new cross-chain protocol that allows parties to perform virtual Bitcoin payment securely on a consortium chain, without any trusted third-party or mediators. Our work focuses on the issue that it is difficult for a consortium chain's token to hold a stable market value, and Niji makes it possible for smart contract services to acquire means of payment in the consortium chain. With the Bitcoin payment channel built on the consortium chain, the process from payment to service provision runs autonomously without any interaction between parties. Niji introduces the concept of a transaction template to validate Bitcoin payments efficiently on different blockchains, and it allows a service provider to delegate all of its tasks for verifying state updates to a smart contract on the consortium chain. We also propose a novel bi-directional payment channel adapted for design of the Niji protocol, which can update payments non-interactively between parties. We implemented a prototype of the Niji protocol and conducted an experiment measuring the computational cost and latency that demonstrates the protocol's feasibility on practical platforms.