Electrical Characterization and Modeling of Low Dimensional Nanostructure FET

At the beginning of this thesis, basic and advanced device fabrication process which I have experienced during study such as top-down and bottom-up approach for the nanoscale device fabrication technique have been described. Especially, lithography technology has been focused because it is base of the modern device fabrication. For the advanced device structure, etching technique has been investigated in detail. The characterization of FET has been introduced. For the practical consideration in the advanced FET, several parameter extraction techniques have been introduced such as Y-function, split C-V etc. FinFET is one of promising alternatives against conventional planar devices. Problem of FinFET is surface roughness. During the fabrication, the etching process induces surface roughness on the sidewall surfaces. Surface roughness of channel decreases the effective mobility by surface roughness scattering. With the low temperature measurement and mobility analysis, drain current through sidewall and top surface was separated. From the separated currents, effective mobilities were extracted in each temperature conditions. As temperature lowering, mobility behaviors from the transport on each surface have different temperature dependence. Especially, in n-type FinFET, the sidewall mobility has stronger degradation in high gate electric field compare to top surface. Quantification of surface roughness was also compared between sidewall and top surface. Low temperature measurement is nondestructive characterization method. Therefore this study can be a proper surface roughness measurement technique for the performance optimization of FinFET. As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has been introduced. Important of strain engineering has been known for the effective mobility booster. The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowire FET showed huge short channel effect. Subthreshold current was bigger than strained SiGe channel. Temperature dependent mobility behavior in short channel unstrained device was completely different from the other cases. Impurity scattering was dominant in short channel unstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is not necessary only for the mobility booster but also short channel effect immunity. Junctionless FET is very recently developed device compare to the others. Like as JFET, junctionless FET has volume conduction. Thus, it is less affected by interface states. Junctionless FET also has good short channel effect immunity because off-state of junctionless FET is dominated pinch-off of channel depletion. For this, junctionless FET should have thin body thickness. Therefore, multi gate nanowire structure is proper to make junctionless FET. Because of the surface area to volume ratio, quasi-1D nanowire structure is good for the sensor application. Nanowire structure has been investigated as a sensor. Using numerical simulation, generation-recombination noise property was considered in nanowire sensor. Even though the surface area to volume ration is enhanced in the nanowire channel, device has sensing limitation by noise. The generation-recombination noise depended on the channel geometry. As a design tool of nanowire sensor, noise simulation should be carried out to escape from the noise limitation in advance. The basic principles of device simulation have been discussed. Finite difference method and Monte Carlo simulation technique have been introduced for the comprehension of device simulation. Practical device simulation data have been shown for examples such as FinFET, strongly disordered 1D channel, OLED and E-paper.