Implementation of Log-Domain FFT Based LDPC Decoder on a GPU

IMPLEMENTATION OF LOG-DOMAIN FFT BASED LDPC DECODER ON A GPU Hanan Alqarni George Mason University, 2019 Thesis Director: Dr. Brian L. Mark Forward error correction enables reliable one-way communication over noisy channels by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance using belief propagation (BP) decoding. However, the computational complexity of a BP decoder is O(q2) operations for each checksum calculation, where q represents number of symbols in the underlying Galois field. The complexity is reduced by transforming the operations into the log and frequency domains. This thesis explores how a GPU implementation of a Log-domain FFT based LDPC decoder performs in comparison to a CPU implementation for regular MacKay construction. Numerical results show that the GPU implementation is about twice as fast as the CPU implementation. The thesis also studies the performance of GPU implementations of a Quasi-cyclic LDPC decoder for WIFI (IEEE 802.11n) and WIMAX (IEEE 802.16e) LDPC codes. Chapter 1: Introduction Low-density parity-check (LDPC) codes were first introduced by R. G. Gallager in 1960 [5], are a class of linear block codes. Theses codes are characterized by their parity-check matrix, a low density of non-zero elements. The benefit of LDPC codes is that closely approaches the capacity of many channels. In addition, LDPC codes are more convenient for heavy implementations. However, these codes were ignored until the 90’s due to the computational complexity of the implementation and the limitation of the hardware. A convenient way to represent LDPC codes is via a Tanner graph representation, which is an e ective graphical representation that e ciently helps to describe the decoding algorithm. Tanner graphs are bipartite graphs, which have nodes separated into two di erent sets (variable nodes and check nodes), and edges connecting nodes of the two di erent sets, representing parity-check matrix. The decoding algorithms decode the codes by performing local calculations and passing those local results via messages. This message passing algorithm. Belief-propagation algorithm is one of the most common message passing algorithm for decoding binary LDPC codes. The log-domain Fourier transform belief-propagation algorithm is message passing algorithm used for the case of non-binary LDPC codes which achieve good decoding performance. A parallel computing architecture is e ective method used to raise the performance of iterative decoding of highly computational codes such as LDPC. Compute Unified Device Architecture (CUDA) is a parallel computing architecture developed by NVIDIA Corporation, remains in the current NVIDIA graphics cards. It is accessible to software developers through variants of industry standard programming languages. Using regular programing languages such as C/C++ it is possible to program CUDA devices with NVIDIA extensions and certain restrictions. CUDA chip technology is based on a multiprocessor with many 0 cores and hundreds of ALU’s, several thousand registers and some shared memory. Besides, a graphics card contains global memory, which can be accessed by all multiprocessors, local memory in each multiprocessor, and special memory for constants. The several multiprocessor cores in a Graphical User Interface (GPU) are single instruction, multiple data (SIMD) cores. Motivated by both the parallel computation power of the CUDA architecture implementation of LDPC codes, the decoding performance of LDPC codes are studied in this thesis. Parallel implementation using CUDA is implemented using an existing C software based log-domain Fourier transform belief propagation algorithm, as well as Quasi-Cyclic LDPC algorithm. The main objective is achieving an e cient performance of CUDA implementation of decoding system and exposing to di erent implementation of LDPC decoding algorithm. Chapter 2 introduces the necessary theoretical background for understanding LDPC codes both Log-domain FFT and Quasi-Cyclic algorithms, and CUDA architecture. The LDPC codes are presented together with their main characteristic, the parity-check matrix, and their graphical representation (Tanner graph), which is the base for performing the iterative LDPC decoding. Algorithms belief propagation and the log-domain Fourier transform, and QC-LDPC are explained step by step. Afterwords, the CUDA architecture is introduced and its parallel processing capabilities of these graphical cards, as well as performance considerations to achieve better performance is explained. Chapter 3 discusses the CUDA implementation of the LDPC decoders in CPU in detail. Then, the belief propagation and the log-domain Fourier transform algorithms are parallelized and assembled in kernels using CUDA implementation. Each kernel uses the hardware resources in a di erent way, in order to achieve the best performance. The implantation of Log-FFT LDPC on Tesla k40m GPU is detailed in this chapter. Also, QC-LDPC implementation on GPU is discussed along with its optimization solution for memory latency. Chapter 4 Discuss the performance of the implementation of Log-domain FFT based