Waffle MOS channel aspect ratio calculation with Schwarz-Christoffel transformation

The main goal of this work is to describe alternati ve way of effective channel width to length ( W/L) ratio calculation for Waffle MOS structure. Due to non-co nventional gate geometry of the Waffle MOS transist or compare to the fingers structure, the channel W/L ratio calculation is not trivial and conformal map ping can be used. In terms of mapping the Schwarz-Christoffel ( SC) Transformation is proposed. The optimal element shape of the Waffle MOS is proposed, to be easy solved by SC conformal mapping. Because result of the confor mal mapping for the Waffle MOS element is rectangle sha pe in transformed domain, the solving of the effect ive channel W/L ratio of the element is become very easy because i t is aspect ratio of rectangle in transformed domain. INTRODUCTION OF WAFFLE MOS STRUCTURE There are many reasons why this old approach Waffle MOS structure Fig. 1 should be in scope of interest even for actual processes and designs. Compare to classical fingers MOS structure the Waffle MOS is known due to 40 % lower resistance Ron [1]. Another not negligible advantages of this structure is lowe r source and drain capacitance [6]. And it was described that Waffle MOS structure in terms of under die stress induced by packaging are much better than fingers MOS structures [2]. Fig. 1: Waffle MOS structure, active area (green), polysili con gate electrode (red), contacts (yellow), metallic interconnection (blue),source electrode (S) , drai n electrode (D) . All of this is obtained without any process change. Because there is no need for extra cost due to additional process step we can implement Waffle MOS structure in almost all CMOS processes. All what is needed is just to change the pattern shape of the polysilicon gate electrode mainly. In addition there is need to change the contact and interconnection metallization for electrode source (S) and drain (D) also. In some processes diagonal meta l interconnection routed at 45 degree should be problematic. In such cases alternative routing shou ld be apply (Fig. 2) [9]. Fig. 2: Waffle MOS structure, with orthogonal metal interconnection routing. As was mention in [1] several different layout schemes that are useful for implementing low resistance switches with MOS transistors was discussed and characterized. A comparison of the area required for implementing a switch with a standard alternating gate finger MOS (Fig. 3) approach was made with physical layouts using waffle structures and serpentine structures. When designing low-resistance MOS switches, significant reduction in area was achievable by using Waffle structures. A reduction in area of over 40% was demonstrated for a typical process [1]. Base on [8] today’s integrated DC-DC converters require low-voltage power devices with low onresistance Ron and low gate charge QG to provide good power conversion efficiency. Since the conduction and switching losses are dependent on th e on-resistance Ron and total gate charge QG, it is necessary to minimize both parasitic resistance and capacitance. According to [2] common centroid geometries (or point symmetric) are recommended for optimum matching. However, these structures become increasingly complex for more than two transistors, with severe penalties in area. The interdigitated waffle (Fig. 2) and the quad (common centroid) transistor layout structures show no systematic mismatch, and the matching follows the well established linear relationship with the inverse of the transistor channel area. Under induced die stress d ue to packaging, the waffle and the quad (common centroid) is better because the finger style transi stor pair shows a significant systematic mismatch, which is a function of its position in the die. The finge r style transistor pair and the interdigitated finger struc ture show a mismatch up to 5 times higher than the value predicted by only considering random fluctuation of the channel area. Fig. 3: Interdigitated Waffle MOS structure, active area (g reen), polysilicon gate electrode (red), contacts (yellow) , first metallic interconnection (blue), second metallic interconnection (purple),source electrode (S) , fi rst drain electrode (D1), second drain electrode (D2) . On first look the interdigitated waffle and the quad (common centroid) transistor layout looks that they are almost same in terms of matching. But the interdigitated waffle has one main advantage. Because on same area we can reach smaller resistanc e compare to standard finger structure, on same area we can match transistors with larger effective channel width. Or alternatively we can match transistors wi th same effective channel width on smaller area. In practice designer generally preferred to use finger structure as much as possible instead of Waf fle structure. The main reason for that is that rectang ular geometry of standard finger structure is convenient for layout, transistors should have sufficient dens ity, are easy to reshape and for this device precise mod el have been developed [3]. To bypass one of this disadvantages the precise model of the Waffle MOS structure is requested. Fig. 4: MOSFET with rectangular shape of gate electrode wit h length of the channel L and width of the channel W, active area (green), polysilicon gate electrode (red), con tacts (yellow), metallic interconnection (blue),source e l ctrode (S) , drain electrode (D) . Let’s consider simple DC electrical model of the MOSFET (Fig. 4) with rectangular shape of gate electrode with length of the channel L and width of the channel W in saturation region without considering channel length parameter ( ) T GS OX D 2 V V L W μC I − = (1) where ID ,VGS and VT are drain current, gate to source voltage and threshold voltage. The μ is a chargecarrier effective mobility and COX is a gate oxide capacitance per unit area. The only one model parameter which depends on gate or channel shape geometry is width to length ( W/L) ratio. For nonrectangular gate geometry the effective W/L ratio parameter should be considered. ( ) T GS EF OX D 2 V V L W C I −       = μ . (2) The (W/L)EF represent effective W/L ratio of gate geometry. As we can see the precision of this parameter should have significant influence on tota l precision of electrical model of Waffle MOS structure. Due to this reason for precise model of the Waffle MOS structure the precise effective channel W/L ratio calculation is needed. DESCRIPTION OF THE PROBLEM When we look on Waffle MOS structure (Fig. 5) we should recognize and define two different types of channel areas. Fig. 5: Waffle MOS structure with defined areas of interest A, B and main dimension W’ and L’ . Fig. 6: Macro element with orthogonal mesh after SC transformation with defined areas of interest A, B. The first area A type represent all channel areas where Source (S) and Drain (D) electrodes are located on two opposite sides of rectangle A. Those regions are with almost homogenous current distribution in channel area. And due to this effec tive W/L ratio for rectangle A is directly aspect ratio of rectangle A