Your core - my problem? integration and verification of IP

As the popularity of reusing existing designs or Intellectual Property (IP) continues to grow, design challenges escalate. The most time-consuming and critical part of IF’ design and reuse is verifying that it will work as it was designed to and as the user intends. Designers are pushing the limits of IP for new, distinctive and innovative applications. With this innovation come problems that need creative solutions. Product verification, for example, will become more and more important in ensuring the correctness of the design. Over the years, various solutions have come on the market, all seemingly useful, but none reducing the time or manpower it takes to verify the design. With designs becoming increasingly more complex with each new project and verification consuming up to 70 percent of a design cycle, something must be done to alleviate the bottleneck. Most of today’s verification techniques rely on old simulation and emulation technologies, combined with add-on products designed to target specific functional items facilitated by the increased importance of the functionality they provide. These environments have led to an overall degrading in productivity, with a decrease in tool speed and a sharp rise in learning curve and installation issues. In addition, interaction between add-on products created in isolation lead to further complications, usually discovered as products are incorporated in design flows. An improved verification flow is required to provide high-level productivity improvement over the entire design. The larger and more complex the design, the higher probability of errors slipping through the verification process, making System-On-Chip (SOC) devices the most vulnerable. With the integration of entire systems within single chips, the need to test hardware and software before the circuitry is produced, within as natural an environment as possible is critical to ensuring design success. The most important aspect in the selection and verification of IP is the collaboration of the vendor and the foundry. Designers need to be able to evaluate the core before a final selection is made. The evaluation should not just use the testbench provided by the vendor, but should provide an indication of the behavior in the intended use environment. In parallel, the designer must look at fabrication option by obtaining its fabrication profile. How many foundries have certified the core? How many times has the core been used in previous designs kom each foundry? And, more important, is the core certified by the foundry chosen for the ASIC under development? With the microprocessor or microcontroller IP, the designer might have projected the use of an off-the-shelf RTOS. In this case, it is imperative to make sure that either the IP or RTOS has been used successfully already, or that the software vendor and the hardware vendor are committed to insure proper integration in a timely manner. Most of this work is tedious and costly because it must take place before final selection and business negotiations can take place. Once the IP has been chosen, user and vendor must work as a team during the verification process. The vendor has an interest in this process, since bugs can be found when a new set of tests and a new use methodology is available. Those who assume that IP commerce is similar to standard parts commerce are mistaken and are apt to encounter serious obstacles to IP integration. An SOC must be verified at various levels of abstraction: fhctional to check the correctness of system design, RTL to insure that what is going to be synthesized is correct, and gate for timing accuracy and possibly to check signal integrity and power consumption. Many verification improvements have been proposed which target specific parts of the design flow. The panel will look at various alternatives for IF’ verification today, including universal simulation, hardware acceleration, formal verification and semi-formal verification. Functional verification, used to verify that the implementation meets the specification, requires a significant amount of time because of the large amount of test vectors required to meaningfully test all of the functionality of a complex system, including the interfaces among the various logical blocks that make up the system. Traditional HDL simulation falls short of the required capabilities when Verilog is used because the language lacks appropriate behavioral constructs. Although VHDL provides the required constructs, its popularity is more limited, so C based dialects or new languages are required. Being able to develop a testbench is only the first of many obstacles. The amount of time required to execute a full suite of functional simulations is significant, even if processors speeds continue to increase. Simulation farms are becoming a popular tool to decrease functional verification time. Moving kom behavioral to RTL code is the step in the methodology that has the least amount of tool support. Verifying the KTL implementation of a system is crucial. Given the size of today’s designs, traditional simulation methods are running out of steam. Formal verification and hardware acceleration methods are being adopted and improved, respectively. EDA tools implementing formal methods have seen a resurgence in the last year, due to improved user interface as well as algorithms implemented to prove the equivalence between a RTL and a gate-level representation of a system. Emulation is also becoming a more popular method to verify gate-level implementations, although the initial cost of the equipment is still quite high. Panelists, experienced designers and representatives of EDA tools providers, as well as IP providers, will explore ways to beat the verification bottleneck and to identify the methodology best suited for IP design. They will attempt to answer the question, “What methodology works best for IF’ Design? ’ Panelists/Position Statements Tom Anderson Vice President of Applications Engineering 0-In Design Automation, Inc., USA There are many aspects to designing for reuse, but increasingly verification is a key for virtual components (VCs) that are successful either as reusable cores in a company’s design repository or as