A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection

This thesis discusses among the modeling and the design methodology of on-chip high-perfbrmance interconnection. Due to the advances in LSI fabrication process, chip performance is continuously improving. As the performance of LSIs improves, on-chip signaling h.as been becoming a bottleneck of the whole chip performance. The performance of on-chip interconnects has been discussed but the main focuses are the signal propagation delay and the power dissipation. On the other hand, multircore architecture is considered to be a mainstream of high-performance microprocessor design. Networkon--Chip (NoC) is also discussed. NoC is an architecture integrating a network of processors into a single chip. According to these technology trends, the throughput of on-chip interconnection is becoming an important metrics in circuit design. The core components of on-chip signaling are a driver, a receiver and an interconnect. In this research, modeling and performance estimation methods for each component are proposed. First, a parameter extraction from a physical structure of on-chip interconnects is discussed. Conventionally, on-chip interconnects are modeled by a lumped RC model. However as the operating frequency becomes higher, the inductance of on-chip interconnects become significant. Ib evaluate such interconnect characteristics, return current distribution is a crucial problem. In LSIs, huge amount of interconnects are integrated and it is difucult to specify return paths from those wires. This thesis proposes a screening method to select wires that have to be considered as return path. Conventionally, only the parallel wires are considered as the candidate of return path. This research evaluates the interconnect characteristics by real-chip measurement and field-solvers. Experimental results reveal that wide and dense orthogonal wires such as powetiground rails can be return paths and affect the interconnect characteristics. The effk)ct of silicon substrate is also discussed. Modeling of lossy substrate is one of the difficulties in modeling on-chip interconnects. This research shows that the powetiground wires interrupt the coupling between the signal interconnects in upper layers and the substrate. From the measurement results, the effect of lossy substrate is negligible if there are poweofground grid in the lower interconnect layer. Next, an interconnect modeling method is proposed. The characteristic of on-chip interconnects depends on the frequency due to the skin-effect, the proximity-effect and the return current distribution. Interconnect models that can treat frequency-dependence are already developed. On the other hand, a conventional frequency-independent model is used in the early stage of the circuit design. Therefore improving the accuracy of the conventional frequency-independent model is important issue as well as developing the frequency-dependent models. This thesis proposes a method to determine a single extraction frequency based on the transfer characteristics of transmission-lines. Then an analytical performance estimation of on-chip interconnects is proposed. In interconnect