Reduction of architecture vulnerability factor using Modified Razor flipflops

Title of thesis: Reduction of Architecture Vulnerability Factor using Modified Razor Flip-flops Kiran K Seshadri, Master of Science, 2007 Thesis directed by: Professor Manoj Franklin Department of Electrical and Computer Engineering Microprocessors are increasingly being used in a variety of applications from small computers to life critical applications. With increasing dependence on microprocessor based systems in critical applications, greater importance needs to be given not only to performance but also to correctness and dependability. Research has shown that microprocessors and structures of the microprocessors such as microarchitectural logic state elements and memories are vulnerable to alpha particle impacts (Single Event Upsets) and timing errors which will lead to Soft errors and affect program correctness and reliability. In this thesis, we have modified the Razor flip-flops and explored the use of these Modified Razor flip-flops in the Instruction Queue (IQ), the Reorder Buffer (ROB), the Level 1 Data Cache (DL1), the Load Queue (LQ) and the Store Queue (SQ) to increase their respective reliability and hence the overall reliability of the microprocessor. Modified Razor flip-flops detect soft errors and along with architectural modifications, ensure correctness of the microprocessor operation, thus resulting in decrease of vulnerability and increase of reliability. We have adopted Architecturally Correct Execution (ACE) time based techniques to measure the Architecture Vulnerability Factor (AVF) of high performance microprocessors and their internal structures using the SPEC 2000 integer benchmarks. The contribution of individual bit-fields of the structures towards the overall AVF is computed, and the fields with higher contribution towards the overall ACE Time are identified. We have computed the reduction in AVF with the introduction of Modified Razor flip-flops for various combinations of fields that have high vulnerability. However, introduction of Modified Razor flip-flops results in higher area requirement on the die and higher power consumption. We have developed RTL models for IQ, ROB, LQ, and SQ to measure the increase in area and average power consumption. Area requirement and power consumption estimates for the data cache are done using Cacti-based techniques. We have identified the most cost-effective solution by identifying the fields of these microarchitectural structures where Modified Razor flip-flops are introduced that result in the highest percentage decrease in AVF per unit area-power product. We observe that, by introducing Modified Razor flip flops selectively in fields with the highest percentage decrease in AVF per unit area-power (identified by our work as opcode and destination operand field of IQ, destination operand and destination operand value field of ROB, tag array of DL1, address field of LQ and SQ), the overall AVF of the micro-processor decreases by 32.23%, but the area requirement increases by 16.99% and the average power consumption increases by 10.33%. REDUCTION OF ARCHITECTURE VULNERABILITY FACTOR USING MODIFIED RAZOR FLIPFLOPS