An Efficient Power Constrained Test Scheduling using the Grouping Algorithm

The basic p TAM design t design of scan total number of an SOC. In th architecture in SOC under the proposed grou proposed arch we compute tes bandwidth fo experimental r industrial IC experiments w method. Introdu I The increa problems. One times which amount of test time has becom have been pro and test vector The basic i parallel in orde concurrently. H such as sharin test, which in scheduling iss design of the s possibility for constraints mu system under te An Efficient Power Constrained Test Scheduling using the Grouping Algorithm nghoon Chun Yongjoon Kim Yongseung Shin Dongsub Song Sungho Kang Department of Electrical and Electronic Engineering, Yonsei University shkang@yonsei.ac. kr Test wrapper and TAMs [10] are important in SOC environment since it directly impacts the vector memory depth required on the ATE, as well as testing time, and thereby affects test cost. Therefore, TAM scheduling, a special case of test scheduling, has gained interest recently [11-12]. An important issue then is the techniques to reduce test power dissipation allowing testing at higher clock frequencies. roblem in test scheduling is scan chain and o minimize the test time of an SOC. The chains has a large impact on the resulting SOC-level test patterns and the test time for is paper, we propose a novel scan chain order to minimize the total test time for an power constraint. We also implemented our ping TAM scheduling algorithm for the itecture. Using a 3-dimensional constraint, t time, power consumption and assign TAM r the proposed architecture. We give esults of the proposed architecture for an and ITC’02 benchmark circuits. Through e demonstrate the efficiency of the proposed We consider an SOC with multiple embedded scan testable cores. For each core, the number of scan flip flops and the number of scan test patterns are given. The assignment of the scan chains to the cores has a large impact on the size of the test vector set. In [9], the scan chain distribution problem (SCDP) is defined as the problem of finding a distribution of a given number of scan chains over the cores, such that the test time of the SOC is minimized. They proposed an optimization algorithm for SCDP. However, an optimization algorithm for SCDP is inefficient algorithm since it does not consider that the test time for each core has large deviation. Therefore, in this paper, we propose a novel scan chain architecture in order to schedule tests using a new algorithm which optimize test time under the power constraints. We call this algorithm a grouping algorithm. ction sing complexity of SOC created many test of the most difficult problems is long testing are caused by transporting a substantial data to an SOC design. Minimizing the test e an important issue and several techniques posed [1-4], including test scheduling [5-8] set reduction [9]. The paper is organized as follows. In the next section we describe previous works in this area. We compare previous proposed techniques and present a new architecture for our approach in Section 3. The algorithm to minimize the total test time for an SOC under the power constraint is explained in Section 4. In Section 5, we present experimental results for an industrial IC and ITC’02 benchmarks. The paper is concluded in Section 6. dea of test scheduling is to schedule tests in r to test cores in an SOC as many as possible owever, there are usually many conflicts, g of common resources, in a system under hibit parallel testing. Therefore the test ue must be taken into account during the ystem under test in order to maximize the parallel test. In addition, test power st be considered carefully, otherwise the st may be damaged due to overheating. Previous Works II The basic problem in test scheduling is scan chain and TAM design to minimize the test time of an SOC. The topic of scan chain design is discussed in various papers. Oostdijk et al.[13] order the individual flip flops in the scan chains to minimize the test vector set size. Each scan flip flop f is assigned a weight which represents the number of patterns which are captured by f minus the number of patterns which are applied by f. The scan flip flops within one scan chain are ordered from scan-in pin to scan-out pin by increasing weights. Narayanan et al.[14] presented a comprehensive and structured methodology to efficiently configure multiple scan chains. The main idea is to assign flip flops involved in testing kernels with larger test lengths to shorter chains. A polynomial time algorithm was derived to obtain a configuration that minimizes of the design strategy over configuring equal length scan chains. This reduces the number of test vectors even further. The above mentioned techniques are inefficient for SOC in practice, since all scan flip flops within one core get the same number of test patterns, which implies that their weights would all be zero and hence do not form a basis to design the scan chains. In scan testing, after initializing the flip flops, a test pattern is applied to the primary inputs, the results are latched at the flip flops, and then they are propagated to the output by placing the circuit in a test mode and clocking enough times to capture the results. Thus, each test vector is shifted in and after a capture cycle, the test response is shifted out. This process contributes to a major part of the test time. It can be reduced by partitioning the scan flip flops into several chains of shorter length. Aerts and Marinssen [9] investigated partitioning where the constraints are defined by available bandwidth. They proposed three different scan chain architectures which all are intended to maximize the bandwidth utilization of the transport mechanism. Testing of core-based systems is a relatively new topic and publications in this area are only beginning to emerge. Test access is eased by placing the core in a wrapper such as Boundary scan[15], TestShell[16], or IEEE P1500[17]. These approaches assume one single TAM bandwidth per core. Test access mechanisms (TAMs) and test wrappers are important components of an SOC test access architecture. Therefore, TAM scheduling, a special case of test scheduling, is important issue. The techniques to reduce test power dissipation allowing testing at higher clock frequencies are also another important issue, since the shift process in scan test contributes to a major part of the test power consumption. A New Scan Chain Architecture III To explain why a new scan chain architecture needs and the disadvantages of multiplexing architecture [9] and distribution architecture [9], we compare them. Next, the architecture for our approach is described. In multiplexing architecture, it assigns the full scan bandwidth to every core and multiplexes the scan chains per core onto the SOC pins. The test time per core is minimal. However, the cores can only be tested sequentially, because of the TAM sharing, and the TAM is utilized inefficiently for cores which have smaller number of scan chains than the size of TAM bandwidth. In addition, wiring problems occur in the cores with few flip flops. To avoid this, a minimum length on the internal scan chains is introduced; a consequence is that part of the scan bandwidth by-passes the smaller cores. If the TAM bandwidth is large, in order to minimize the test time per core, the number of scan chains in cores is small and the number of scan chains which occur scan shifting concurrently on an SOC is large. Therefore, the test power is maximized, which could damage the core, since the test time per core is minimized. In distribution architecture, each core gets assigned it private scan chains, so the number of scan chains has to be at least as large as the number of cores ( | ). | C Ntam > In general, if the TAM bandwidth is low, then the multiplexing architecture is used efficiently without concerning power problem, since the number of scan chains which concurrently occur scan shifting is small. Otherwise, the distribution architecture is more efficient than the multiplexing architecture. However, the distribution architecture is not utilized the scan chains of cores inefficiently, because of large deviation of the length of scan chains which are assigned in each core. The efficiency of usage of the scan chains in each core is low in distribution architecture. Therefore, we propose a new architecture to utilize the scan chains efficiently. The proposed architecture divides the available TAM bandwidth over the groups, the combinations of cores which have T : the test time for the SOC similar test time per core assuming that TAM size is 1. The TAM bandwidth is assigned based on the amount of test data has to be transported to each individual core. Each distributed scan chain bandwidth in the proposed architecture is assigned every core in a group. Thus, all cores in a group are connected to all scan inputs and all scan outputs of the group. Group m SOC Test Source N1