Fast Circuit Satisfiability Algorithms and Applications

We survey circuit complexity theory, satisfiability algorithms for circuits, and the recent framework of Ryan Williams’s for obtaining circuit lower bounds from these nontrivial satisfiability algorithms. We give some slightly improved arithmetization constructions based on -biased sets which reduce the sample space of the resulting probabilistic polynomials. We also examine an application of circuit satisfiability to fast tropical matrix multiplication and all-pairs shortest path, and we present some progress on obtaining a faster sparse all-pairs shortest path algorithm by defining and studying a class of structured sparse graphs 1. CIRCUIT COMPLEXITY The circuit approach to complexity theory stems from the fact that digital circuits used in modern computers are built from logic gates. The corresponding theoretical model of computation is a boolean circuit which takes some number of input gates, performs a computation specified by the circuit structure, and returns an output at an output gate. The complexity of these circuits can be parametrized by the number of gates and depth of the circuit as a function of the number of inputs, as well as the types of gates allowed, and this provides a concrete alternative to the abstract construction of complexity classes using Turing machines. The motivation for studying circuit complexity is that the Turing machine model was discovered to be insufficient for proving certain desirable results in complexity theory, such as the P vs NP problem [7], [8]. The relativization barrier intuitively means that any proof which treats an algorithm as a black box is incapable of proving either of those statements to be true or false. Most arguments involving Turing machines are black box arguments which use universal Turing machine simulation and diagonalization, which fall under this category of black box methods. A circuit class consists of a family of circuits {Cn}n=1, one for each input size n, such that the number of gates of Cn is asymptotically bounded by a function of n, denoted t(n). The circuit takes n boolean values as inputs and outputs a single boolean value. Overall this circuit class is denoted by C[t(n)]; this can be interpreted as meaning the size of the circuit increases as O(t(n)) as the number of input variables increase. A polynomial size circuit is when t is a polynomial function; that is, we have C[n] where k is the degree of the relevant polynomial. The circuit complexity of a problem ∗Advisor: Sanjeev Khanna (sanjeev@cis.upenn.edu). is then the smallest function t which is needed for a circuit family to solve that problem. The depth of a circuit is the longest path from any input bit to the output bit, where length is measured by how many gates the bit must pass through. Circuit classes are related to the usual complexity classes by the following classical theorem, which can be found in [8]. Theorem 1. For any Turing machine A, if A runs in time t(n), then A has circuit complexity O(t(n)). This theorem highlights the motivation for studying circuit classes. In particular, showing that a complexity class does not have polynomial size circuits implies that P is not contained in it, which may eventually lead to something like proving P 6= NP. The major circuit complexity classes of interest are: Definition 1. ACC are the circuits of depth O((logn)), consisting of polynomially many AND, OR, and MOD m gates of unbounded arity, for a constant m. The MOD m gate takes the sum of the input bits and outputs 1 if this sum is divisible by m. Definition 2. TC consists of depth O((logn)) circuits with polynomially many AND, OR, and MAJORITY gates of unbounded arity. The MAJORITY gate outputs the majority (0 or 1) of the input bits, with ties broken by a fixed rule. Equivalently, a THRESHOLDm gate can be used instead of the MAJORITY gate, where this gate outputs 1 if the sum of the inputs is greater than m and 0 otherwise. In both of these cases, we are primarily interested in the families of constant-depth circuits ACC and TC. Definition 3. SYM consists of depth-2 circuits. The first layer consists of only AND gates of unbounded arity with negations allowed of the inputs. The second layer is a symmetric function of the outputs of the first layer; that is, this function only depends on the number of output bits of the first layer which are equal to one. SYM circuits are intuitively multilinear polynomials over F2 inputs composed with a symmetric function. The product over a subset of variables in each monomial corresponds to the AND operation, and the sum of the monomials corresponds to the input to the symmetric function. Definition 4. P/poly is the class of problems decidable in polynomial time with a polynomial size advice string. Equivalently, it is the class of problems decidable using an unboundeddepth polynomial size boolean circuit with AND, OR, and NOT gates. The relationship between these circuit classes is as follows. We know that ACC ⊆ TC, because the MOD m gate can be simulated in the other circuit class. We also know that ACC ⊆ SYM by a classical result of Beigel and Tarui [1], which gives a particularly nice characterization of ACC circuits that we describe in the next section. Finally, all of these circuits can be evaluated in polynomial time, and are thus all contained in P/poly. 1.1 The circuit classes ACC0 and SYM+ ACC circuits are fairly powerful in the types of functions they can describe, since in practice constant-depth computations are desirable. On the other hand, SYM seems very restrictive for describing functions but potentially very powerful for designing satisfiability algorithms due to the highly structured nature of the circuits. An amazing result from Beigel and Tauri [1] is that ACC circuits can be transformed into SYM circuits without too large of a blowup in size, so that this transformation leads to improved satisfiability algorithms for ACC. Theorem 2. Every language L ∈ ACC can be recognized by a depth-two deterministic circuit with a symmetricfunction gate at the root and 2 O(1) AND gates of fan-in (logn) at the leaves. The proof of this result involves carefully arithmetizing the gates in the ACC circuit and pushing modulus operations outside of parenthesis inductively. First we need a way of arithmetizing the MOD m gate and the AND or OR gate. Recall that MODpe(x1, · · · , xn) = 1 if n ∑