Comparison of Sinusoidal Pulse Width Modulation based Seven and Five Level Cascaded Inverters

In this paper, new reduced switch count technique is introduced to construct a multilevel inverter topology which reduces the number of switches used in the system. Sinusoidal pulse width modulation is used to control proposed inverter. In conventional H-bridge multilevel inverter to produce a seven level ten number of switches are used. Due to involvement of high number of switches thereby the harmonics, switching losses, cost and the total harmonics distortion is increased. This proposed topology involves only eight number of switches. It dramatically reduces the switches for high number of levels that reduces the switching losses; cost and low order harmonics and thus effectively decreases total harmonics distortion. Keywords— cascaded multilevel inverter, H-bridge multilevel inverter, THD, PWM, IGBT, Multilevel Inverter (MLI). INTRODUCTION A multilevel inverter is a power electronic converter built to synthesize a desired AC voltage from several levels of DC voltages which the DC levels were considered to be identical in that all of them were batteries, solar cells, capacitors, etc. The multilevel inverter has gained much attention in recent years due to its advantages in lower switching loss better electromagnetic compatibility, higher voltage capability, and lower harmonics [1]-[3]. Several topologies for multilevel inverters have been proposed; the most popular being the diode-clamped [4], [5], flying capacitor [6], and cascade H bridge [7] structures. Besides the three basic multilevel inverter topologies; other multilevel converter topologies have been proposed, most of these are hybrid circuits that are combinations of two of the basic multilevel topologies. The main disadvantage still exists in diode clamped multilevel inverter topology, which restricts the use of it to the high power range of operation. The first topology introduced is the 542 M.Murugesan et al series H-bridge design [1] in which several configurations have been obtained. An apparent disadvantage of this topology is the large number of isolated voltage required to supply each cell. In this proposed topology three HBridges are combinely connected together to form a seven level inverter. The proposed topology for multilevel inverter has a high number of steps associated with a low number of power switches. In addition for producing all the levels (odd and even) at the output voltage, a procedure for calculating the required dc voltage source is proposed. In this topology pulse width modulation technique is used. The THD will be decreased by increasing the number of levels. It is obvious that an output voltage with low THD is desirable, but increasing the number of levels needs more hardware, also the control will be more complicated. It is a tradeoff between price, weight, complexity and a very good output voltage with lower THD. II.CASCADED H-BRIDGE MULTILEVEL INVERTER The general structure of the conventional cascaded multilevel inverter is shown in figure 1. Each of the separate voltage source (A1, A2, A3) connected in cascade with other sources via a special circuit associated with it. Each stage of the circuit consists of only two active switching elements that can make the output voltage source only in positive polarity with several levels; or it can be simply zero volts depending on the switching condition of the switches in the circuit [6]. Figure 1. Topology of Hybrid Multilevel Inverter with reduced number of switches Only one H-bridge is connected to get both positive and negative polarity. The main advantages of this hybrid multilevel inverter are high number of levels with reduced number of bridges and dc sources. The S number of dc source or stages and the associated number output level can be calculated by using the equation N level =2S+1 (1) For example if S=3, the output wave form has 7 levels (±7, ±6, ±5, ±4, ±3, ±2, ±1 Comparison of Sinusoidal Pulse Width Modulation 543 and 0) which is shown in the figure 17 and voltage on each stage can be calculated by using the equation Ai=1Vdc (i=1, 2, 3.) (2) The number switches used in this topology is given by the equation N switch=2S +4 (3) III. MODIFIED CASCADED MULTILEVEL INVERTER The general structure of the modified cascaded multilevel inverter is in Figure 2. Each of the separate voltage source (Vdc1, Vdc2, Vdc3) connected with three H-bridges which are connected together. The operation of modified cascaded multilevel inverter is shown in figure 4. From this diagram when S1 and S6 is turn on the voltage across the load is +1Vdc. To get second step (+2Vdc) switch S6 should be turned off and switch S7 has to be turned on. Similarly the negative half cycle steps can be obtained by keeping S5 in on state throughout the entire half cycle and the steps –1Vdc, -2Vdc, -3Vdc can be obtained by properly turning on the S2, S3 and S4 respectively. The main advantages of hybrid multilevel inverter are high number of levels with reduced number of bridges and dc sources. The S number of dc source or stages and the associated number output level can be calculated by using the equation N level =2S+1 (4) For example if S=3, the output wave form has 7 levels (±3, ±2, ±1 and 0) which is shown in the Figure 3 and voltage across the capacitor (S) on each stage can be calculated by using the equation Ai=1Vdc (i=1, 2, 3.) (5) Figure 2. Topology of Modified Cascaded Multilevel Inverter The number of switches used in this topology is given by the equation N switch=4S+2 (6) 544 M.Murugesan et al Figure 3. Typical Output Voltage Waveform for Modified Cascaded Multilevel Inverter Figure 4. Operation Diagram of Modified Hybrid Multilevel Inverter Comparison of Sinusoidal Pulse Width Modulation 545 V. PWM FOR HARMONICS REDUCTION PWM technique is extensively used for eliminating harmful low-order harmonics in inverters. In PWM control, the inverter switches are turned ON and OFF several times during a half cycle and output voltage is controlled by varying the pulse width. SPWM techniques are characterized by constant amplitude pulses with different duty cycle for each period. The width of this pulses are modulated to obtain inverter output voltage control and to reduce its harmonic content. Sinusoidal pulse width modulation is the mostly used method in motor control and inverter application [7]. In order to verify the ability of the proposed multilevel inverter topology to synthesize an output voltage with a desired amplitude and better harmonic spectrum, programmed SPWM technique is applied to determine the required switching angles. It has been proved that in order to control the fundamental output voltage and eliminate ‘n’ harmonics, ‘n+1’ equations are needed. The method of elimination will be presented for 7-level inverter such that the solution for three angles is achieved. The Fourier series expansion of output voltage waveform using fundamental frequency switching scheme as follows ( ) = ∑ (cos( )) ∞ , , + cos( ) + ⋯+ cos ( ))sin ( ) (6) Where K is the number of switching angle required for 7 level inverter. Ideally, for a given fundamental voltage V1, it is required to determine the switching angles , , . , so that output voltage Vo( t)=V1sin( t ) and a specific higher harmonics of Vn(n t) are equal to zero. According to the three phase theory in balanced three phase system third order harmonic is cancelled. The switching angles can be found by solving the following equations cos( ) + cos( ) + cos( ) = cos(5 ) + cos(5 ) + cos(5 ) = 0 cos(7 ) + cos(7 ) + cos(7 ) = 0 (7) Where modulation index, = ( ) One approach to solve theset of nonlinear transcendental equations (9), is to use an iterative method such as the Newton-Raphson method [8]. In contrast to iterative methods, the approach here is based on solving polynomial equations using the theory of resultants which produces all possible solutions [9]. The transcendental equations characterizing the harmonic content can be converted into polynomial equations. Then the resultant method is employed to find the solutions when they exist. These sets of solutions have to be examined for its corresponding total harmonic distortion (THD) in order to select the set which generate the lowest harmonic distortion (mostly due to the 11 and 13 harmonics). The computed THD in percent is defined by