The impact of interconnect process variations and size effects for gigascale integration

We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results indicate LER amplitudes start to become a substantial percentage of the nominal effective line-width dimension (2016 to 2020), leading to an increase in the conductor resistivity. Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture—as much as a 35% reduction for the maximum critical path delay mean and standard deviation is observed for the year 2020 with a 14nm half-pitch. Introduction As the industry continues to shrink critical dimension (CD), there is a parallel effort to control and/or tolerate process variations since these impact the overall chip performance, power, yield and cost [1]. In particular, copper interconnects have been a topic of interest [2]-[4]. It is understood that as device dimensions scale, transistor speed increases. However, the local interconnect delay is expected to worsen with respect to the transistor [1]. The trend of increasing interconnect delay is due largely to size-effects [2]. It is expected that process variations will exacerbate size-effects on overall interconnect performance. In this paper, we briefly review past research and the sources of interconnect variability. We then introduce an effective resistivity ( ρ eff) model as a function of line edge roughness (LER) and chemical mechanical polishing (CMP) variation parameters. Next, we apply our model in a Monte Carlo (MC) simulation framework to quantify the impact of interconnect process variations on the maximum critical path delay for both single core (sCore) and multi-core (mCore) highperformance microprocessors (MPU) to the year 2020. Finally, we summarize our findings in the conclusion. Sources of Interconnect Variability Although device variations tend to dominate over interconnect variations for current technologies [4], the impact of interconnect variability becomes more pronounced as we look into the future [5]. For our work, the sources of physical and electrical interconnect variability from photolithography and chemical mechanical polishing (CMP) are of primary concern. By 2008, M1 and intermediate wiring levels (i.e. long local wires) will begin to share the same line-widths, aspect ratios, and barrier/cladding thicknesses [1]. This implies that variability seen at M1 will also be seen at intermediate wiring levels. To elucidate this point, interconnect CD variation (M1 to intermediate level line-widths) is affected by photolithography, a contributor to both die-to-die (D2D) and within-die (WID) variations. Effective line-widths (w0) are projected to exhibit a 3σ 10% total CD variation for all generations [1], where CD is the ITRS MPU half-pitch. A recent study modeled the impact of line edge roughness (LER) on ρ eff [3], revealing that wires with w0=40nm can have variations as great as 15nm, resulting in widths from 25nm to 55nm along the length of a wire [3]. The amount of LER depends on the photolithographic and resist technology that is used [3]. As a result, LER is assumed to be an inherent and fixed-constant by-product that is superimposed on the metal line-width (which itself is affected by D2D and WID variations). No closed-form ρ eff model was published in [3]. CMP is also a known contributor to resistivity variability [7]. Since copper metal is relatively softer than silicon-oxide, metal dishing occurs. This phenomenon is also exacerbated by uneven pattern density that contributes further to oxide erosion [8]-[9]. As such, dishing is expected to recess no more than 10% of the actual conductor height [1]. Closed-Form Resistivity Model Copper resistivity is expected to increase due to size-effects for future technology nodes as line-widths approach the electron mean free path of copper (λCu = 40nm) [2]. We present a new closed-form compact ρ eff model in (1), which is derived from [3], [10], and [11]; here, ρ 0 is the effective bulk conductor resistivity, λ is the electron mean free path, and p is the specularity parameter. The remaining model parameters are defined in Fig. 1. To capture the average behavior of electrons through a conductor, resistivity is derived separately from the horizontal and vertical contributions of surface roughness and surface scattering. The contributions were then combined using Matthiessen’s rule. This approach is unlike that in [3], where the analysis included surface roughness and scattering from LER but not CMP dishing. Our model is independent of period length as it assumes both the vertical and horizontal period lengths are much larger than λ. In Fig. 2, the ρeff model (1) is compared to numerical simulations [3] and agrees well for a range of w0 and LER amplitudes (u/2). As w0 approaches u, the effective resistivity exponentially increases. The compact model dramatically reduces computation time as compared with a numerical simulator to facilitate the large number of MC simulations. ( ) ( ) ( ) ( ) ( ) ( ) 0 2 2 2 2 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 eff p p w u w h v h u w v h       λ − λ −       ρ = ρ + + + −   − −     − −       (1)