Transistor Level Reliability Estimation of Integrated Circuits

The history of semiconductor chips has been characterized by a steady growth in the level of integration. Although this growth has given computer designers more capable circuits, it has become increasingly di cult to ensure highly reliable designs. Until now, the reliability of semiconductor chips has been parametrized by the logic family; the operating voltage, temperature, and environment; and the level of integration of the component. Thus, to obtain highly reliable systems, it was often necessary to limit the number of transistors. An attractive and potentially important extension to the analysis of circuit reliability is to account for the connectivity of the individual internal components. For circuits in Complementary Metal Oxide Silicon (cmos) technology, this reliability analysis is accomplished by modeling open and shorted transistors, \stuck{at" wires, and failed power and ground sources. Direct analysis of the reliability of a circuit by exhaustive enumeration of all fault combinations is prohibitive, however, due to the exponential growth of the number of states in circuits. A tractable approach for digital systems, that includes all transistor level faults and calculates the reliability of combinational circuits exactly, can be based on a hierarchical decomposition of the circuit into manageable sub{units. For each level of the hierarchy, units are simulated exhaustively and critical statistical data are gathered. At the highest level, the resulting statistical data are combined to generate the exact probability of correct operation for the whole circuit. Analysis of the reliability of a set of fault tolerant gates with this hierarchical approach illustrates that redundancy techniques alone are not successful at increasing circuit reliability; each section of the circuit that is modi ed must be replaced with a structure with higher reliability. Analysis of a triple modular redundancy system shows that single point and double point failures must be included in the analysis to ensure numerical precision. Considering higher multiplicities of failures is not critical because the probability of such fault con gurations is typically insigni cant.v Acknowledgements I wish to express my deep appreciation to my principal advisor Prof. G. Leonard Tyler for his guidance and encouragement throughout the course of this research. I would also like to acknowledge the support of Prof. Allen M. Peterson, especially during the beginning of my graduate work and wish that he could be here to see the nal results. In addition, I would like to thank Dr. Ivan R. Linscott who provided insightful comments and di erent perspectives for approaching the problems that I encountered. Finally, my thanks go to Prof. Albert Macovski for chairing my Oral defense and Prof. David M. Bloom for serving as the third member of my reading committee. I would also like to acknowledge the especial friends I have made while here at Stanford. Thanks to Antonio Todesco, Samy Makar, and Margaret Martonosi for all the joyful times we spent together. My warm gratitude is extended to my wife Myrricia for all her love, support, patience, and encouragement. I am also grateful to her for proof{reading all of this work. Lastly, I thank my parents for their guidance that led to my continuing studies. vi