Miracle-dz/UniFAR-FTUs huggingface dataset:
Transactuations

A large class of IoT applications read sensors, execute application logic, and actuate actuators. However, the lack of high-level programming abstractions compromises correctness, especially in the presence of failures and unwanted interleaving between applications. A key problem arises when operations on IoT devices or the application itself fails, which leads to inconsistencies between the physical state and application state, breaking application semantics and causing undesired consequences. Transactions are a well-established abstraction for correctness, but assume properties that are absent in an IoT context. In this article, we study one such environment, smart home, and establish inconsistencies manifesting out of failures. We propose an abstraction called transactuation that empowers developers to build reliable applications. Our runtime, Relacs, implements the abstraction atop a real smart-home platform. We evaluate programmability, performance, and effectiveness of transactuations to demonstrate its potential as a powerful abstraction and execution model.
R2P2: Making RPCs first-class datacenter citizens

Remote Procedure Calls are widely used to connect data-center applications with strict tail-latency service level objectives in the scale of µs. Existing solutions utilize streaming or datagram-based transport protocols for RPCs that impose overheads and limit the design flexibility. Our work exposes the RPC abstraction to the endpoints and the network, making RPCs first-class datacenter citizens and allowing for in-network RPC scheduling. We propose R2P2, a UDP-based transport protocol specifically designed for RPCs inside a datacenter. R2P2 exposes pairs of requests and responses and allows efficient and scalable RPC routing by separating the RPC target selection from request and reply streaming. Leveraging R2P2, we implement a novel join-bounded-shortest-queue (JBSQ) RPC load balancing policy, which lowers tail latency by centralizing pending RPCs in the router and ensures that requests are only routed to servers with a bounded number of outstanding requests. The R2P2 router logic can be implemented either in a software middlebox or within a P4 switch ASIC pipeline. Our evaluation, using a range of microbenchmarks, shows that the protocol is suitable for µs-scale RPCs and that its tail latency outperforms both random selection and classic HTTP reverse proxies. The P4-based implementation of R2P2 on a Tofino ASIC adds less than 1µs of latency whereas the software middlebox implementation adds 5µs latency and requires only two CPU cores to route RPCs at 10 Gbps linerate. R2P2 improves the tail latency of web index searching on a cluster of 16 workers operating at 50% of capacity by 5.7× over NGINX. R2P2 improves the throughput of the Redis key-value store on a 4-node cluster with master/slave replication for a tail-latency service-level objective of 200µs by more than 4.8× vs. vanilla Redis.
Assessing the Acceptability of a Peer Mentor Mother Intervention to Improve Retention in Care of Postpartum Women Living with HIV

Abstract Background: Many women living with HIV (WLWH) experience poor postpartum retention in HIV care. There are limited evidence-based interventions in the United States aimed at increasing retention of WLWH postpartum; however, evidence from low-resource settings suggest that women who receive peer mentoring experience higher retention and viral suppression postpartum. Methods: We conducted 15 semistructured interviews with pregnant or postpartum women from an urban U.S. clinic to assess factors influencing maternal adherence to antiretroviral therapy (ART) and retention in HIV care. We then assessed the acceptability of a peer intervention in mitigating barriers to sustain adherence and retention in care postpartum. Interviews were audio taped, transcribed, and analyzed. Codes were developed and applied to all transcripts, and matrices were used to facilitate comparisons across different types of participants. Results: Participants included low-income black and Hispanic women with a mean age of 31 years (range 22–42). Social support and concern for infants' well-being were strong facilitators for engaging in care. Psychosocial challenges, such as stigma and isolation, fear of disclosure, and depression, negatively influenced adherence to ART and engagement in care. Regardless of their level of adherence to ART, women felt that peer mentoring would be an acceptable intervention to reinforce skill-related ART adherence and sustain engagement in care after delivery. Conclusion: A peer mentor mother program is a promising intervention that can improve the care continuum of pregnant and postpartum women in the United States. Messaging that maximizes maternal support and women's motivation to keep their infant healthy may leverage retention in care postpartum.
Architecture design for highly flexible and energy-efficient deep neural network accelerators

Deep neural networks (DNNs) are the backbone of modern artificial intelligence (AI). However, due to their high computational complexity and diverse shapes and sizes, dedicated accelerators that can achieve high performance and energy efficiency across a wide range of DNNs are critical for enabling AI in real-world applications. To address this, we present Eyeriss, a co-design of software and hardware architecture for DNN processing that is optimized for performance, energy efficiency and flexibility. Eyeriss features a novel RowStationary (RS) dataflow to minimize data movement when processing a DNN, which is the bottleneck of both performance and energy efficiency. The RS dataflow supports highlyparallel processing while fully exploiting data reuse in a multi-level memory hierarchy to optimize for the overall system energy efficiency given any DNN shape and size. It achieves 1.4× to 2.5× higher energy efficiency than other existing dataflows. To support the RS dataflow, we present two versions of the Eyeriss architecture. Eyeriss v1 targets large DNNs that have plenty of data reuse. It features a flexible mapping strategy for high performance and a multicast on-chip network (NoC) for high data reuse, and further exploits data sparsity to reduce processing element (PE) power by 45% and off-chip bandwidth by up to 1.9×. Fabricated in a 65nm CMOS, Eyeriss v1 consumes 278 mW at 34.7 fps for the CONV layers of AlexNet, which is 10× more efficient than a mobile GPU. Eyeriss v2 addresses support for the emerging compact DNNs that introduce higher variation in data reuse. It features a RS+ dataflow that improves PE utilization, and a flexible and scalable NoC that adapts to the bandwidth requirement while also exploiting available data reuse. Together, they provide over 10× higher throughput than Eyeriss v1 at 256 PEs. Eyeriss v2 also exploits sparsity and SIMD for an additional 6× increase in throughput. Thesis Supervisor: Vivienne Sze Title: Associate Professor of Electrical Engineering and Computer Science Thesis Supervisor: Joel Emer Title: Professor of Electrical Engineering and Computer Science
Devices-as-Services: Rethinking Scalable Service Architectures for the Internet of Things

We investigate a new distributed services model and architecture for Internet of Things (IoT) applications. In particular, we observe that devices at the edge of the network, although resource constrained, are increasingly capable – performing actions (e.g. data analytics, decision support, actuation, con-trol, etc.) in addition to event telemetry. Thus, such devices are better modeled as servers, which applications in the cloud compose for their functionality. We investigate the implications of this “ﬂipped” IoT client-server model, for server discovery, authentication, and resource use. We ﬁnd that by combining capability-based security with an edge-aware registry, this model can achieve fast response and energy efﬁciency.
JumpSwitches: Restoring the Performance of Indirect Branches In the Era of Spectre

The Spectre family of security vulnerabilities show that speculative execution attacks on modern processors are practical. Spectre variant 2 attacks exploit the speculation of indirect branches, which enable processors to execute code from arbitrary locations in memory. Retpolines serve as the stateof-the-art defense, effectively disabling speculative execution for indirect branches. While retpolines succeed in protecting against Spectre, they come with a significant penalty — 20% on some workloads. In this paper, we describe and implement an alternative mechanism: the JumpSwitch, which enables speculative execution of indirect branches on safe targets by leveraging indirect call promotion, transforming indirect calls into conditional direct calls. Unlike traditional inlining techniques which apply call promotion at compile time, JumpSwitches aggressively learn targets at runtime and leverage an optimized patching infrastructure to perform just-in-time promotion without the overhead of binary translation. We designed and optimized JumpSwitches for common patterns. If a JumpSwitch cannot learn safe targets, we fall back to the safety of retpolines. JumpSwitches seamlessly integrate into Linux, and are evaluated in Linux v4.18. We show that JumpSwitches can improve performance over retpolines by up to 20% for a range of workloads. In some cases, JumpSwitches even show improvement over a system without retpolines by directing speculative execution into conditional direct calls just-in-time and reducing mispredictions.
An estimation of distribution algorithm for hybrid flow shop scheduling under stochastic processing times

The estimation of distribution algorithm (EDA) has recently emerged as a promising alternative to traditional evolutionary algorithms for solving combinatorial optimisation problems. This paper presents a novel two-phase simulation-based EDA (TPSB-EDA) for minimising the makespan of a hybrid flow shop under stochastic processing times. To address the stochastic scheduling problem efficiently, the proposed TPSB-EDA incorporates a two-phase simulation model to estimate the performance of candidate solutions. In this model, an optimal back propagation network is firstly applied to identify a set of roughly good solutions, and then the selected solutions are further evaluated by a discrete-event simulation algorithm. Moreover, an annealing selection mechanism (ASM) is adopted to preserve the population diversity of EDA. Different from the selection operators of common EDAs, the ASM uses Boltzmann probability in the annealing algorithm to select part of population to establish the probabilistic model. Computation results indicate that the TPSB-EDA provides good solutions in the aspects of solution quality and computational efficiency.
Imperfect gaps in Gap-ETH and PCPs

We study the role of perfect completeness in probabilistically checkable proof systems (PCPs) and give a way to transform a PCP with imperfect completeness to one with perfect completeness, when the initial gap is a constant. We show that PCPc,s[r, q] ⊆ PCP1,s'[r + O(1), q + O(r)] for c --- s = Ω(1) which in turn implies that one can convert imperfect completeness to perfect in linear-sized PCPs for NP with a O(log n) additive loss in the query complexity q. We show our result by constructing a "robust circuit" using threshold gates. These results are a gap amplification procedure for PCPs, (when completeness is not 1) analogous to questions studied in parallel repetition [22] and pseudorandomness [15] and might be of independent interest. We also investigate the time-complexity of approximating perfectly satisfiable instances of 3SAT versus those with imperfect completeness. We show that the Gap-ETH conjecture without perfect completeness is equivalent to Gap-ETH with perfect completeness, i.e. MAX 3SAT(1 --- ∈, 1 --- δ), δ > ∈ has 2o(n) algorithms if and only if MAX 3SAT(1, 1 --- δ) has 2o(n) algorithms. We also relate the time complexities of these two problems in a more fine-grained way to show that T2(n) ≤ T1(n(log log n)O(1)), where T1(n),T2(n) denote the randomized time-complexity of approximating MAX 3SAT with perfect and imperfect completeness respectively.
The Driving Mechanism of Virtual Human's Action and Facial Expression Based on OSG

According to the poor code quality,low render low efficiency, and limited scalability of virtual human drive mechanism and other problems, 3D rendering engine Open Scene Graph(OSG) has realized the efficient simulation and expression of virtual human action.Firstly, on the basis of the skeletal animation and spherical interpolation algorithm to achieve the virtual human motion animation.Then design the generating methods of the virtual facial expression animation related to the behavior consciousness by using three Bessel interpolation algorithm and based on deformation animation technology.Finally by using the animation technology in the OSG,the synthesis of virtual human motion and expression is realized based on the parameter control.Experience confirms that under the same number of scene nodes, using OSG engine code is more concise, and render faster.
Home, SafeHome: Ensuring a Safe and Reliable Home Using the Edge

As smart home environments get more complex and denser, they are becoming harder to manage. We present our ongoing work on the design and implementation of “SafeHome”, a system for management and coordination inside a smart home. SafeHome offers users and programmers the flexibility to specify safety properties in a declarative way and to specify routines of commands in an imperative way. SafeHome includes mechanisms which ensure that under concurrent routines and device failures, the smart home behavior is consistent (e.g., serializable) and safety properties are always guaranteed. SafeHome is intended to run on edge machines co-located with the smart home. Our design space opens the opportunity to borrow and adapt rich ideas and mechanisms from related areas such as databases and compilers.
An Edge-based Framework for Cooperation in Internet of Things Applications

Edge computing and the Internet of Things (IoT) are irrevocably intertwined and much work has proposed enhancing the IoT through the use of edge computing. These solutions have typically focused on using the edge to increase the locality of cloud applications, achieving benefits mainly in terms of lower network latency. In this work, we argue that IoT systems can benefit much more from semantic properties which are best recognized and exploited in situ, at the edge of the network where the data streams and actuators exist. We outline the idea of a real-time semantic operating system, hosted on the edge, which can provide higher performance in energy consumption, latency, accuracy, and improve not only individual application performance but that of an entire IoT infrastructure. We have implemented a prototype system and show some initial results demonstrating the efficacy of our proposed optimizations, and provide insights into how to handle some of the most critical issues faced in such a system.
Speeding up Online POMDP Planning

A novel algorithm to speed up online planning in partially observable Markov decision processes (POMDPs) is introduced. I propose a method for compressing nodes in belief-decision-trees while planning occurs. Whereas belief-decision-trees branch on actions and observations, with my method, they branch only on actions. This is achieved by unifying the branches required due to the nondeterminism of observations. The method is based on the expected values of domain features. The new algorithm is experimentally compared to three other online POMDP algorithms, outperforming them on the given test domain.
A Tractography-Based Grading Scale of Brain Arteriovenous Malformations Close to the Corticospinal Tract to Predict Motor Outcome After Surgery

Background: Surgical decision-making for brain arteriovenous malformations (AVMs) close to the corticospinal tract (CST) is always challenging. The purpose of this study was to develop a tractography-based grading scale to improve preoperative risk prediction and patient selection. Methods: We analyzed a consecutive, surgically treated series of 90 patients with AVMs within a 10-mm range from the CST demonstrated by preoperative diffusion tensor tractography. Poor motor outcome was defined as persistent postoperative limb weakness. We examined the predictive ability of nidus-to-CST distance (NCD), the closest CST level (CCL), deep perforating artery supply, as well as variables of the supplemented Spetzler-Martin grading system. Three logistic models were derived from different multivariable logistic regression analyses, of which the most predictive model was selected to construct a prediction grading scale. Receiver operating characteristic analysis was conducted to test the predictive accuracy of the grading scale. Results: Twenty-one (23.3%) patients experienced persistent postoperative limb weakness after a mean 2.7-year follow-up. The most predictive logistic model showed NCD (P = 0.001), CCL (P = 0.017), patient age (P = 0.004), and AVM diffuseness (P = 0.021) were independent predictors for poor motor outcome. We constructed the CLAD grading scale incorporating these predictors. The predictive accuracy of the CLAD grade was better compared with the supplemented Spetzler-Martin grade (area under curve = 0.84 vs. 0.68, P = 0.023). Conclusions: Both NCD and CCL predict motor outcome after resection of AVMs close to the CST. We propose the CLAD grading scale as an effective risk-prediction tool in surgical decision-making. Clinical Trial Registration: www.ClinicalTrials. gov, identifier: NCT01758211 and NCT02868008
New advances in the routing of mixed analog and digital channels

A new channel routing algorithm for mixed analog/digital circuits is presented. This router uses two routing layers and is based on a classical vertical constraint graph (VCG) analysis. It is able to handle variable wire width, irregular top and bottom edges, and minimization of crosstalk. To make it more general and to suit the analog designers' needs, some new features have been added: critical nets are routed in one layer if possible and pins may be present on either layer. The problem of cycles in the VCG is also addressed. It is shown that new types of cycles may appear due to analog constraints. The authors describe the proposed solution. Some results obtained on real circuits designed at CNET are reported. <<ETX>>
OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface

Consumer-grade solid-state drives (SSDs) guarantee very few things upon a crash. Lacking a strong disk-level crash guarantee forces programmers to equip applications and lesystems with safety nets using redundant writes and ushes, which in turn degrade the overall system performance. Although some prior works propose transactional SSDs with revolutionized disk interfaces to o er strong crash guarantees, adopting transactional SSDs inevitably incurs dramatic software stack changes. Therefore, most consumer-grade SSDs still keep using the standard block device interface. This paper addresses the above issues by breaking the impression that increasing SSDs’ crash guarantees are typically available at the cost of altering the standard block device interface. We propose Order-Preserving Translation and Recovery (OPTR), a collection of novel ash translation layer (FTL) and crash recovery techniques that are realized internal to block-interface SSDs to endow the SSDs with strong request-level crash guarantees de ned as follows: 1) A write request is not made durable unless all its prior write requests are durable. 2) Each write request is atomic. 3) All write requests prior to a ush are guaranteed durable. We have realized OPTR in real SSD hardware and optimized applications and lesystems (SQLite and Ext4) to demonstrate OPTR’s bene ts. Experimental results show 1.27× (only Ext4 is optimized), 2.85× (both Ext4 and SQLite are optimized), and 6.03× (an OPTR-enabled no-barrier mode) performance improvement.
NEURAL NETWORK MATERIAL MODELLING

Santrauka Straipsnyje supažindinama su neuroninių tinklų metodo taikymų, kuriant fizikinius medžiagų modelius. Neuroninių tinklų metodas, pagrįstas žmogaus smegenų darbo modeliavimo principais, tik sį desimtmetį praktiskai pradėtas taikyti įvairiose mokslo srityse. Pirmieji du sio straipsnio autoriai pirmieji pasaulyje pritaikė neuroninių tinklų metodą. fizikiniams modeliams kurti. Neuroninį tinklą sudaro mazgai (neuronai), tarpusavyje sujungti rysiais. Mazgai yra suskirstyti į grupes, vadinamas sluoksniais: pradinių duomenų ir rezultatų sluoksniai bei tarpiniai sluoksniai (1 pav.). Mazgai charakterizuojami aktyvumu, o rysiai stiprumu. Mazgo aktyvumas nustatomas kaip į jį ateinancių ryssių stiprumo ir atitinkamų mazgų aktyvumo sandaugų suma. Rysių stiprumas, kuris gali turėti tiek teigiamą, tiek neigiamą. skaitine reiksme, nustatomas neuroninio tinklo „mokymo” metu. Tinklas dažniausiai „mokomas” pradinių duomenų ir rezultatų pavyzdžiu pagal tam tikras mokymo taisykles. Is visų žinomų neuroninių tinklų ben.
CoSMIX: A Compiler-based System for Secure Memory Instrumentation and Execution in Enclaves

Hardware secure enclaves are increasingly used to run complex applications. Unfortunately, existing and emerging enclave architectures do not allow secure and efficient implementation of custom page fault handlers. This limitation impedes in-enclave use of secure memory-mapped files and prevents extensions of the application memory layer commonly used in untrusted systems, such as transparent memory compression or access to remote memory. CoSMIX is a Compiler-based system for Secure Memory Instrumentation and eXecution of applications in secure enclaves. A novel memory store abstraction allows implementation of application-level secure page fault handlers that are invoked by a lightweight enclave runtime. The CoSMIX compiler instruments the application memory accesses to use one or more memory stores, guided by a global instrumentation policy or code annotations without changing application code. The CoSMIX prototype runs on Intel SGX and is compatible with popular SGX execution environments, including SCONE and Graphene. Our evaluation of several production applications shows how CoSMIX improves their security and performance by recompiling them with appropriate memory stores. For example, unmodified Redis and Memcached keyvalue stores achieve about 2× speedup by using a self-paging memory store while working on datasets up to 6× larger than the enclave’s secure memory. Similarly, annotating a single line of code in a biometric verification server changes it to store its sensitive data in Oblivious RAM and makes it resilient against SGX side-channel attacks.
Predictive Iterative Learning Control using Laguerre Functions

Abstract This paper develops a predictive iterative learning control algorithm starting from some recent results in the area of predictive repetitive control. Although similar in spirit to the original norm-optimal iterative learning control, the algorithm developed employs receding horizon control and Laguerre functions to parameterize the future control trajectory. As a result, difficulties encountered by the norm-optimal iterative control algorithm are overcome. The stability of the predictive iterative learning system is analyzed and conditions on error convergence are established. In addition, a strategy for learning the unknown plant initial conditions and the reduction of the initial plant errors is developed. A simulation example to illustrate the algorithm is also given.