Application and Implementation of DES Algorithm Based on FPGA

In order to meet the data transmission of security and real time requirement in trading system, in this paper, a design scheme of 16 level pipeline encryption system based on FPGA is proposed. Using the 7K325T model of the Xilinx company`s FPGA chip to achieve circuit design. The results show that the circuit can work stably, the maximum frequency of the encryption module is up to 166MHz, and the encryption speed is 10.62Gb/s, which can ensure the security and efficiency of the data. Introduction In the options, futures and other derivatives transactions, the transaction of real-time data processing speed has more and more high requirements. Normally, in order to improve the security of data transactions, transaction data are required to do encryption, and this step to deal with the time occupied by the larger proportion of the entire system. In addition, customers have more and more high requirements for the trading system delay and throughput. When dealing with massive amounts of data, the TCP/IP protocol will occupy a large amount of CPU resources. Therefore, with the emergence of Gigabit Ethernet, network link speed is higher than the processing speed of TCP/IP protocol, the real-time data processing can`t be guaranteed [1]. At present, the mainstream of data processing is realized by hardware acceleration. While using GPU and multi-core processor to achieve the acceleration scheme in dealing with transaction data is not only delay high but poor stability, has can`t meet the needs of transaction. According to the structure of FPGA and the characteristics of parallel processing data, we can know that using FPGA can effectively reduce the delay and power consumption [2]. Foreign countries have adopted the FPGA platform to achieve the acceleration program, the minimum delay can be achieved within 1us, With a good application value. DES algorithm is a packet with 16 iterations of symmetric ciphers, not only has the same structure with the encrypt and decrypt, but also involves only logical and LUT operation [3]. Therefore, Using FPGA to achieve the encryption algorithm has become relatively simple. In this paper, we put forward a kind of encryption scheme based on FPGA 16 level assembly line, and use the hardware boards to be verified. Encrypted Principle The 64-bit of plaintext are divided into 32-bit left and 32-bit right by the initial permutation, the transformation process is shown in Fig. 1. In the iterative process of I cycles, on the right of the Ri under the action of the 48-bit sub key to do F transform, and the data obtained do XOR operation with Li , Ri is directly used as the next round of the Li+1[4]. Mathematical description such as the Eq.1. { Li = Ri−1 1 ≦ i ≦ 16 Ri = Li−1 ⊕ f(Ri−1, Ki) 1 ≦ i ≦ 16 (1) In the iteration process, F function is the part of iterative operation [5]. Its process is the first to extend the 32-bit Ri−1 to 48-bit data, then do XOR operation with sub key ki, and the 48-bit data 6th International Conference on Management, Education, Information and Control (MEICI 2016) © 2016. The authors – Published by Atlantis Press 0715 are replaced by 32-bit by S-box. Finally, the final result can be obtained by the replacement of P. Form of function as shown in the Eq.2. f(R, K) = P(S(E(R) ⊕ K)) (2) The extended E operation is to extend the 32-bit data to 48 bits.