Technology-Accurate Variability-Aware Performance Macromodels for On-Chip Communication Synthesis

A major challenge in the design of multi-processor systems-on-chip (MPSoCs) is to provide an adequate on-chip communication architecture. Hereby, a series of parameters must be considered, including communication data size, speed, power consumption, and topology, to name only a few. Additionally, variable data flows, as well as increasing process and environmental parameter variations lead to undesired effects, such as reduced yield or increased leakage power levels. The main objective of this thesis is to provide a methodology for the parametrized joint optimization of delay and energy consumption during the communication architecture synthesis, by performing a statistical analysis and optimization of parametric yield under the influence of parameter variations. Moreover, in order to increase the accuracy of the proposed methodology, circuit-level models for the communication activities and technology-accurate models for the interconnection segments are developed. In order to accurately specify statistical parameter distributions in the application profile and process parameter variations, this thesis develops a complete methodology for variability description and propagation across performance macromodel expressions. For this purpose, a generalized random variable model is developed, capable of representing non-standard estimated distributions using discretized pdfs with adjustable accuracy. Another important contribution represents the development of a propagation method for statistical distributions across the modeling expressions using analytic implementations of the most often used operators as well as the introduction of a fast generalized method for implementing statistical operators with a precision comparable to Monte Carlo at a very small fraction of the execution time. Based upon this methodology, statistical performance macromodels for delay and energy consumption are constructed. Since the use of different signaling methods has a strong impact on communication performance, a further important contribution is the inclusion of signaling techniques in the communication synthesis in the form of circuit-level communication models. First, a technology-dependent statistical transistor model is derived, which supports variability descriptions for all process-dependent parameters and employs the previously-developed statistical operators to propagate the parameter distributions throughout the model expressions. Furthermore, pulsed current-mode and voltage-mode signaling circuits are analyzed and modeled using the statistical transistor model, equivalent circuit models, and analytic expressions of the current and voltage signals. Within this context, the impact of voltage scaling and body biasing on the circuit performance are also analyzed. Afterwards, the circuit-level models are employed for modeling entire communication segments and the segment models are included within the system-level performance macromodels for the communication synthesis. The accuracy of communication segment models is further enhanced through a wide-bandwidth characterization method for arbitrary interconnect segments. The method relies on an initial set of parameter extractions, designed to reflect the particularities of a given manufacturing process, and applies a sequence of incremental extrapolations to construct the model of a specified segment. Accuracy evaluations show a performance close to industry-standard field simulators. Finally, synthesis results in the context of delay-driven and energy-driven optimizations show the efficiency of pulsed current-mode signaling on long communication segments and the advantages of voltage-mode signaling on short links. In addition, it is shown that voltage scaling and body biasing can be integrated effectively in the communication synthesis to reduce energy consumption.