Miracle-dz/UniFAR-FTUs huggingface dataset:
Near LLC versus near main memory processing

Emerging advanced applications, such as deep learning and graph processing, with enormous processing demand and massive memory requests call for a comprehensive processing system or advanced solutions to address these requirements. Near data processing is one of the promising structures targeting this goal. However, most recent studies have focused on processing instructions near the main memory data banks while ignoring the benefits of processing instructions near other memory hierarchy levels such as LLC. In this study, we investigate the near LLC processing structures, and compare it to the near main memory processing alternative, specifically in graphics processing units. We analyze these two structures on various applications in terms of performance and power. Results show a clear benefit of near LLC processing over near main memory processing in a class of applications. Further, we suggest an architecture, which could benefit from both near main memory and near LLC processing structures, but requiring the applications to be characterized in advance or at run time.
Multi-objective Optimization of a DC Microgrid with a Back-up Diesel Generator

Nowadays, microgrid applications are proliferate all around the world. Owing to many grounds, such the ease of control, the high efficiency and reliability, the improvement of power electronics devices, the rise of DC type loads and sources, etc. researchers’ interest was diverted from AC to DC microgrids. Yet, on a global control and management level, several challenges are confronted. A variety of objectives can be achieved by controlling the power flow of each of the distributed energy sources. By means of this, an optimization problem is formulated and solved using heuristic methods such the genetic algorithm (GA), the particle swarm optimization (PSO), the pattern search (PS), etc. However, other techniques were exploited in the literature such the dynamic programming (DP) which is a stepby-step optimization algorithm. In this paper, a (DP) technique is applied to solve a multi-objective optimization problem. Two objectives are set: DC microgrid operation cost minimization, and pollutant gas emissions reduction. A sole cost function is established, and weights are assigned to each of the predefined goals. Besides, each objective function is detailed apart, and several constrains are set. Two simulations tests are performed to prove the convergence, and the viability of the applied (DP) technique. Finally, different weights are selected in each of simulation tests to validate the effectiveness, and robustness of the (DP) in solving such problems.
ScalaGraph: A Scalable Accelerator for Massively Parallel Graph Processing

Graph processing is promising to extract valuable insights in graphs. Nowadays, emerging 3D-stacked memories and silicon technologies can provide over terabytes per second memory bandwidth and thousands of processing elements (PEs) to meet the high hardware demand of graph applications. However, this leap in hardware capability does not result in a huge increase but even a degradation sometimes in performance for graph processing. In this paper, we discover that the centralized on-chip memory hierarchy adopted in existing graph accelerators is the villain causing poor scalability due to its quadratic increase of hardware overheads with respect to the number of PEs.We present a novel distributed on-chip memory hierarchy by leveraging the network-on-chip (NoC) to enable massively parallel graph processing. We architect ScalaGraph, a brand new graph processing accelerator, to exploit this insight. ScalaGraph adopts a software-hardware co-design to minimize NoC communication overheads via an efficient row-oriented dataflow mapping and runtime aggregation. A specialized scheduling mechanism is also proposed to improve load imbalance. Our results on a Xilinx Alveo U280 FPGA card show that ScalaGraph on a modest configuration of 512 PEs achieves 2.2× and 3.2× speedups over a state-of-theart graph accelerator GraphDyns and a GPU-based graph system Gunrock, respectively. Moreover, ScalaGraph enables supporting at least 1,024 PEs with nearly linear performance scaling while GraphDyns fails to work.
Powstanie i rozwój kolei żelaznych w prowincji Pomorze jako wyraz aktywności lokalnych środowisk i sektora publicznego

The creation and development of railways in Prussia in the first two decades of their existence occurred by the private sector. Prussian state established railway law on 3 November 1838, the Berlin–Szczecin railway built relatively early line Berlin–Szczecin (1843) and Stargard–Szczecin (1846). Development of the railway was an important event for the province and Szczecin, affecting the economic, social and political importance. Prussian government has been actively involved in the process of construction of the railway in the early eighties of the 19th century. Local government have been active since 1892, which was related to the new law on local railways construction ( Gesetz uber Kleinbahnen und Privatanschlusbahnen vom 28 . 07 . 1892 ). Local authorities (eg. provincial assembly, counties, local municipalities) became an active participant in economic life, including the development of narrow-gauge railway infrastructure in Pomerania.
AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers

Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10 for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
Interconnect in the Era of 3DIC

Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].
Identification and functional expression of a new xylose isomerase from the goat rumen microbiome in Saccharomyces cerevisiae

The current climate crisis demands replacement of fossil energy sources with sustainable alternatives. In this scenario, second‐generation bioethanol, a product of lignocellulosic biomass fermentation, represents a more sustainable alternative. However, Saccharomyces cerevisiae cannot metabolize pentoses, such as xylose, present as a major component of lignocellulosic biomass. Xylose isomerase (XI) is an enzyme that allows xylose consumption by yeasts, because it converts xylose into xylulose, which is further converted to ethanol by the pentose‐phosphate pathway. Only a few XI were successfully expressed in S. cerevisiae strains. This work presents a new bacterial XI, named GR‐XI 1, obtained from a Brazilian goat rumen metagenomic library. Phylogenetic analysis confirmed the bacterial origin of the gene, which is related to Firmicutes XIs. After codon optimization, this enzyme, renamed XySC1, was functionally expressed in S. cerevisiae, allowing growth in media with xylose as sole carbon source. Overexpression of XySC1 in S. cerevisiae allowed the recombinant strain to efficiently consume and metabolize xylose under aerobic conditions.
ASAP: A Speculative Approach to Persistence

Persistent memory enables a new class of applications that have persistent in-memory data structures. Recoverability of these applications imposes constraints on the ordering of writes to persistent memory. But, the cache hierarchy and memory controllers in modern systems may reorder writes to persistent memory. Therefore, programmers have to use expensive flush and fence instructions that stall the processor to enforce such ordering. While prior efforts circumvent stalling on long latency flush instructions, these designs under-perform in large-scale systems with many cores and multiple memory controllers.We propose ASAP, an architectural model in which the hardware takes an optimistic approach by persisting data eagerly, thereby avoiding any ordering stalls and utilizing the total system bandwidth efficiently. ASAP avoids stalling by allowing writes to be persisted out-of-order, speculating that all writes will eventually be persisted. For correctness, ASAP saves recovery information in the memory controllers which is used to undo the effects of speculative writes to memory in the event of a crash.Over a large number of representative workloads, ASAP improves performance over current Intel systems by 2.3 on average and performs within 3.9% of an ideal system.
Augmented Reality-Assisted Autonomous View Adjustment of a 6-DOF Robotic Stereo Flexible Endoscope

Stereo visual servo based surgical instruments tracking enables quicker adjustment of the view and depth of the robotic stereo flexible endoscope (RSFE). However, there are two main drawbacks: 1) when the lesion is covered by organs, the observation angles, from which the endoscope observes it, need to be adjusted independently. But this cannot be achieved by only tracking surgical instruments; 2) the field of view is restricted by the shared area of the two cameras, which limits the tracking area. Therefore, a 6-DOF augmented reality visualizing robotic stereo flexible endoscope (ARSFE), which integrates a pair of HoloLens with the RSFE, is proposed. The Hololens is used for tracking the surgeon’s head and providing head-mounted display. In the ARSFE, the endoscope can be controlled in two modes: 1) The view and depth of the endoscope can be controlled by tracking surgical instruments; 2) The observation angles can be adjusted independently by tracking the surgeon’s head. Modes switching is realized via the foot pedals. Besides, a hybrid control method for tracking instruments is proposed, which significantly enlarges the control field for instruments tracking. In the experiment section, the performance of the proposed hybrid visual servoing control and the ARSFE is verified.
Kinematic Modeling of Human Forearm Rotation With Distal Radio-Ulnar Circumduction

A circumduction of the distal ulna as a complex movement has been observed at the distal radio-ulnar joint during forearm rotation and it has been reported that a stationary ulna makes postures of the hand to be transposed or tilted in the pro-supination. In this paper, a new forearm model reflecting the ulnar circumduction is proposed by changing the joint types of a spatial linkage mechanism. For this purpose, a conventional forearm model with R-R-U-S joint types (established by Whiteley in 2000) which generates the horizontal movement of the distal ulna is firstly analyzed to figure out a kinematic feature for its joint motions. And then this model is reconstructed as an equivalent model with R-R-U-U joints. At the same time, its joint types are realigned as U-R-U-R joints to realize the ulnar circumduction. Finally, a structural design based on the proposed forearm model with the U-R-U-R joints is presented, and its overall movements are described.
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems

The rapid growth of i-memory computing powered by data-intensive applications has increased demand for DRAM in servers. However, a DRAM-based system can be limiting for modern workloads because of its capacity, cost, and power consumption characteristics. Hybrid memory systems, which consist of different types of memory, such as DRAM and persistent memory, can help address many of these limitations. One promising direction that has been explored in the recent literature involves introducing persistent memory devices as a second memory tier that is directly exposed to the CPU. The resulting tiered memory design must address the fundamental challenge of placing the right data in the right memory tier at the right time while minimizing overhead. We present MULTI -CLOCK, an efficient, low-overhead hybrid memory system that relies on a unique page selection technique for tier placement. MULTl-CLOCK’s page selection captures both page access recency and frequency, and enables moving pages to appropriate tiers at the right time within hybrid memory systems. We implemented a Linux-based, NUMA-aware version of MULTI-CLOCK that is entirely transparent and backward compatible with any existing application. Our evaluation with diverse real-world applications such as graph processing and key-value stores shows that MULTI -CLOCK can improve the average throughput by as much as 352% when compared with several state-of-the-art techniques for tiered memory.
Tacker: Tensor-CUDA Core Kernel Fusion for Improving the GPU Utilization while Ensuring QoS

The proliferation of machine learning applications has promoted both CUDA Cores and Tensor Cores’ integration to meet their acceleration demands. While studies have shown that co-locating multiple tasks on the same GPU can effectively improve system throughput and resource utilization, existing schemes focus on scheduling the resources of traditional CUDA Cores and thus lack the ability to exploit the parallelism between Tensor Cores and CUDA Cores.In this paper, we propose Tacker, a static kernel fusion and scheduling approach to improve GPU utilization of both types of cores while ensuring the QoS (Quality-of-Service) of co-located tasks. Tacker consists of a Tensor-CUDA Core kernel fuser, a duration predictor for fused kernels, and a runtime QoS-aware kernel manager. The kernel fuser enables the flexible fusion of kernels that use Tensor Cores and CUDA Cores, respectively. The duration predictor precisely predicts the duration of the fused kernels. Finally, the kernel manager invokes the fused kernel or the original kernel based on the QoS headroom of latency-critical tasks to improve the system throughput. Our experimental results show that Tacker improves the throughput of best-effort applications compared with state-of-the-art solutions by 18.6% on average, while ensuring the QoS of latency-critical tasks.
TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit

As neural processing units (NPUs) for machine learning inference have been incorporated into a wide range of system-on-a-chips, NPUs are processing more and more mission-critical computations such as autonomous driving. With the increasing application scenarios, securing NPU operations from potential attacks has become crucial for the safety of the entire system. To address the security challenges of NPU operations, this study investigates how the trusted execution technology can be extended to harden the NPU execution by hardware supports. This paper proposes trusted NPU (TNPU) which supports trusted execution for NPUs integrated in a processor. For securing NPUs, a key performance challenge is in the encryption and integrity protection for external memory. This work proposes a novel tree-less integrity protection by exploiting the data flow semantics of DNN computation. The tree-less integrity protection maintains a version number for each tensor or sub-tensor inside the CPU enclave which drives the NPU computation. By exploiting the data flow of tensor updates, a per-tensor version number can efficiently verify the recency of the data in the tensor. The tree-less integrity protection eliminates performance losses by counter and hash cache misses, which are major performance overheads of hardware-based memory protection. Our evaluation with simulated NPUs shows that the performance overheads for trusted NPUs can be significantly reduced from the prior tree-based design, improving the performance of a single NPU by 10.0% and 7.5% on average over the prior one with two different NPU configurations. When the number of NPUs is increased to three, the performance gains further improve, achieving on average 13.3% and 8.7% improvements.
HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores

Efficiently exploiting parallelism remains a challenging problem in multicore processors. For many algorithms, executing tasks in some priority order results in a work-efficient execution. However, searching high-priority tasks requires communication that hampers performance. A concurrent priority scheduler (CPS) selects high-priority tasks and schedules them on different cores. Modern CPS designs offer various strategies to select high-priority tasks at low communication cost for improved performance. However, they do not explicitly track the priority of tasks and cannot adjust task distribution if the cores are processing low-priority tasks. Moreover, they cannot estimate the right amount of communication required to select high-priority tasks. This paper critically observes that the cores’ priority drift can be quantified and used for better performance. A novel CPS design, HD-CPS is proposed to use priority as a signal to optimize drift and communication at runtime. Furthermore, compute-intensive task transfer and processing aspects of the CPS are offloaded to per-core local hardware at a low cost to enhance performance. HD-CPS is shown to consistently improve performance over several state-of-the-art software-based and hardware-assisted CPS designs. With hardware-assist, it approaches near-linear performance scaling as a function of core counts for large shared-memory multicores.
A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection

As the demand of high-speed communication is growing for mobile connectivity, the design of a low-power high-data-rate wireless transceiver is essential. Even though the binary FSK (BFSK) modulation is a popular choice for low-power transceiver systems [1]–[5], it has difficulty in achieving a high data rate unless an open-loop oscillator or an injection-pulling oscillator [6] is employed. The direct modulation of the VCO with an open-loop method or within a narrowband PLL suffers from the pulling effect. A closed-loop modulation based on the PLL is challenging for the high data rate due to a limited loop bandwidth or a delay mismatch in the case of the two-point modulation. Moreover, the closed-loop BFSK modulation suffers from a data-pattern-dependency problem when a wideband PLL is considered. The binary frequency-domain OOK (BFOOK) modulation method provides a way of achieving a fully-balanced FSK modulation [7]–[8], so that a wideband PLL can be designed to minimize the VCO pulling effect. The BFOOK modulation, however, occupies twice as much bandwidth as the conventional BFSK modulation. In this work, we propose a quasi-balanced FSK (QB-FSK) modulation to achieve enhanced bandwidth efficiency, while having negligible data-pattern dependency. Based on the proposed modulation method, we present a sub-6GHz FSK transceiver that achieves the highest data rate with the PLL-based modulation.
Hardware-Accelerated Hypergraph Processing with Chain-Driven Scheduling

Beyond ordinary graphs, hypergraphs are a graph representation to flexibly express complex multilateral relationships between entities. Hypergraph processing can be used to solve many real-world problems, e.g., machine learning, VLSI design, and image retrieval. Existing hypergraph processing systems handle a hypergraph in order of its hyperedge and vertex indices. This makes processing hypergraphs on generalpurpose architectures suffer significantly from excessive offchip memory accesses, most of which however are redundant in frequently accessing overlapped hyperedges and vertices, but the index-ordered scheduling destroys this potential locality.In this paper, we propose a novel Generate-Load-Apply (GLA) execution model to improve locality in hypergraph processing. The key insight of GLA is to use a concept of chain to characterize the overlapped feature of a hypergraph, exposing data reuse opportunities missed in existing hypergraph systems. The precondition of driving GLA model is to generate expected chains on the fly, but the software solution is so expensive that its overheads may outweigh the benefits achieved from the chain-driven scheduling. We further present ChGraph, the first hardware-accelerated hypergraph processing engine near each core. ChGraph is specialized in accelerating the chain generation and the chain-guided data loading (to hide memory access latency) while the general-purpose cores are responsible only for handling the apply operations of GLA. We evaluate ChGraph against a state-of-the-art hypergraph processing system Hygra on six hypergraph algorithms using five large real-world hypergraphs. Results on a simulated 16core system show that ChGraph reduces the number of offchip memory accesses by up to 4.56× and achieves up to 4.73× speedup while introducing only 0.26% area overhead.