Miracle-dz/UniFAR-FTUs huggingface dataset:
Genome-Wide Analysis Identifies Candidate Genes Encoding Beak Color of Duck

Beak color diversity is a broadly occurring phenomenon in birds. Here, we used ducks to identify candidate genes for yellow, black, and spotted beaks. For this, an F2 population consisting of 275 ducks was genotyped using whole genome resequencing containing 12.6 M single-nucleotide polymorphisms (SNPs) and three beak colors. Genome-wide association studies (GWAS) was used to identify the candidate and potential SNPs for three beak colors in ducks (yellow, spotted, and black). The results showed that 2753 significant SNPs were associated with black beaks, 7462 with yellow, and 17 potential SNPs with spotted beaks. Based on SNP annotation, MITF, EDNRB2, members of the POU family, and the SLC superfamily were the candidate genes regulating pigmentation. Meanwhile, isoforms MITF-M and EDNRB2 were significantly different between black and yellow beaks. MITF and EDNRB2 likely play a synergistic role in the regulation of melanin synthesis, and their mutations contribute to phenotypic differences in beak melanin deposition among individuals. This study provides new insights into genetic factors that may influence the diversity of beak color.
Genomic prediction in plants: opportunities for ensemble machine learning based approaches

Background: Many studies have demonstrated the utility of machine learning (ML) methods for genomic prediction (GP) of various plant traits, but a clear rationale for choosing ML over conventionally used, often simpler parametric methods, is still lacking. Predictive performance of GP models might depend on a plethora of factors including sample size, number of markers, population structure and genetic architecture. Methods: Here, we investigate which problem and dataset characteristics are related to good performance of ML methods for genomic prediction. We compare the predictive performance of two frequently used ensemble ML methods (Random Forest and Extreme Gradient Boosting) with parametric methods including genomic best linear unbiased prediction (GBLUP), reproducing kernel Hilbert space regression (RKHS), BayesA and BayesB. To explore problem characteristics, we use simulated and real plant traits under different genetic complexity levels determined by the number of Quantitative Trait Loci (QTLs), heritability ( h 2 and h 2 e ), population structure and linkage disequilibrium between causal nucleotides and other SNPs. Results: Decision tree based ensemble ML methods are a better choice for nonlinear phenotypes and are comparable to Bayesian methods for linear phenotypes in the case of large effect Quantitative Trait Nucleotides (QTNs). Furthermore, we find that ML methods are susceptible to confounding due to population structure but less sensitive to low linkage disequilibrium than linear parametric methods. Conclusions: Overall, this provides insights into the role of ML in GP as well as guidelines for practitioners.
Drug-Related Problems of Children With Chronic Diseases in a Chinese Primary Health Care Institution: A Cross-Sectional Study

Introduction: Drug-related problems (DRPs) refer to events or circumstances involving drug therapy that actually or potentially interfere with desired health outcomes. DRPs might be severe for children with chronic diseases managed at primary health care institutions, but the relevant research is scarce. Objective: In this cross-sectional study, we aimed to explore the prevalence, types, causes, and influencing factors of DRPs in children with chronic diseases in a Chinese primary health care institution. Methods: We recruited children with chronic diseases who visited the pediatric outpatient department in a primary health care institution from July 1 to 12 October 2021. Clinical pharmacists identified DRPs through medication therapy reviews, classified the types and causes of DRPs, and distinguished the manifested DRPs that affected the outcome and potential DRPs that were going to affect the outcome. Results: A total of 188 children with chronic diseases was included, and 584 DRPs were identified in 89.89% of participants. The most common type of DRPs was “treatment effectiveness” (a manifested problem or potential problem with the effect of the pharmacotherapy; 83.56%), of which 67.29% were potential DRPs. The second common type was “treatment safety” (patient suffers or could suffer from an adverse drug event; 14.21%), of which 89.16% were potential DRPs. The most common cause of DRPs was related to the process of use (42.24%), such as “patient uses/takes less drug than prescribed or does not take the drug at all,” “patient stores drug inappropriately,” and “patient administers/uses the drug in a wrong way. ” The second common cause was related to the process of dispensing (29.83%), such as “necessary information not provided or incorrect advice provided” and “prescribed drug is not available. ” The third common cause was related to the process of prescribing (26.21%), such as “drug dose is too low” and “no or incomplete drug treatment despite an existing indication. ” The number of combined medications was an influencing factor for the frequency of DRPs (p < 0.05). Conclusion: This cross-sectional study showed that the current situation regarding DRPs among children with chronic diseases managed in the primary health care institution was serious. The types of DRPs were mainly related to treatment effectiveness, and improper usage of medications was one of the main causes of DRPs. The number of combined drugs was the influencing factor for the frequency of DRPs. In the future, pharmacists should consider formulating pharmaceutical intervention strategies for this specific group according to the characteristics of DRPs.
On Web Personalized e-Learning Recommendation System

:- e-learning framework provides learners a numerous amount of content with its ease of access. Since with the availability of enormous content, it is difficult for the learner to opt the most needful information from the available content. Recommendation system are the engines that filter the data depending on various parameters and produces most appropriate information as the result. In the context of e-learning recommendation system, recommender system is a engine that attempts to” intelligently” recommend activities to a learner based on the actions of previous learners. This recommendation could be an on-line activity such as doing an exercise, reading posted messages on a conferencing system, or running an on-line simulation, or could be simply a web resource. Most of the recommendation systems have been implemented in e-commerce platform to improve the sales of goods to improve the revenue generation for to compete in the market, but haven’t been implemented in e-learning. This paper proposes a recommender system that uses web mining techniques to recommend on-line learning activities or shortcuts in a course web site based on learners’ access history to improve course material navigation as well as assist the online learning process. Which helps the learner to learn very quickly and easily as the recommendation engine is assisting continuously throughout the learning process.
IMPROVEMENT OF ADVANCED ENCRYPTION STANDARD ALGORITHM USING ROW TRANSFORMATION AND 200 BIT DATA BLOCK

- In today’s modern world security of data has become one of the most important factor in our technological life. The main objective of this paper is to provide stronger security with higher encryption speed for data communication over the Internet by modifying the Advanced Encryption Standard (AES) algorithm. This paper suggests a new Advanced Encryption Standard encryption technique that provides a stronger encryption technique by enhancing its security and encryption speed. This new algorithm uses 200 bit size data block as well as key in a 5 x 5 matrix format alongwith an additional Row Transformation stage before the shift row stage for each round in the AES algorithm structure. The proposed algorithm can improve security and also enhance the speed of the encryption process.
Feature Extraction Techniques and their Role in Sentiment Analysis: A Survey

Web is a huge repository of facts and opinions available for people in the world about a product. Social networking sites on internet have become an essential part for everyone, which grows at rapidly. Consumers give their reviews about product which are useful for others. Sentiment analysis is used to study the people’s orientation for making better decision which leads to advancement of business. Analysis of sentiment of an entity is defined in term of positive, negative or neutral. In this paper we compare the existing feature extraction techniques which are used in sentiment analysis and also discussed challenges, applications of sentiment analysis.
Fault Effect Propagation using Verilog-A for Analog Test Coverage

— In today’s small size transistors technologies, transistors become more susceptible to defects that occur either due to process variations or defects like open and short circuits during the manufacturing process. To evaluate the quality of the IC test, Analog test coverage is essential, although it is computationally expensive. Performing system level Analog Defect Simulation (ADS) with several complex analog blocks at the transistor level is time-consuming. One possibility to reduce ADS time is to use behavioral models for circuit blocks where defects are not being injected. Yet, the models should be able to propagate the defects responses to the observation point (a pad). A methodology for augmenting fault effects to the Verilog-A behavior models of analog circuits using Look-Up Tables (LUT) is presented in this paper. System-level ADS is performed where analog blocks are replaced with their behavior models. This speeds up the simulation of defects in analog circuits.
Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level Synthesis

—Realizing software algorithms with hardware cores is a proven technique [1],[2] for power reduction. Evolving standards coupled with the enormous cost of chip design demand that the accelerators be programmable. In this paper we describe the development of a new low power programmable accelerator for Baseband, Phy and Video applications which fits into an LLVM compiler tool chain. The candidate architectures were expressed in SystemC. We chose SystemC for our source code because it provided a quick way to express design intent with a much simpler model than an equivalent RTL model. And there are several commercial HLS tools that could generate the RTL for us. Our SystemC source code also integrated well with our software tools and was simulate-able. In order to measure the effectiveness of a candidate architecture we first compiled an application to assembler using a configurable LLVM compiler tool chain. The compiled program was then run on the SystemC model of the accelerator for functional verification. We then used a HLS tool to create a RTL implementation and ran the same compiled program on the RTL. The RTL simulations gave us accurate estimates of area, performance and power with existing RTL design tools. Through a series of many benchmarks we discovered that typically 2-4 instructions would be executed in parallel per basic block in the C code. Architectural performance was measured by running common DSP and baseband (Viterbi/Turbo) algorithms. A small sample of the results that were generated for a 28 nm library is shown below:
Trading Monotonicity for Cost in Beam Search

Beam search is a popular satisficing heuristic search algo-rithm, but increasing the beam width sometimes causes the algorithm to return a worse solution. A recent variant of beam search, monobead, guarantees nonincreasing solution cost with increasing beam width. However, the monotonicity of monobead sometimes comes at the price of increased cost and time for small beam widths. In this paper, we explore two algorithmic variants that lie between beam search and monobead. We find that, as hoped, our hybrids of beam and monobead can often find solutions with better cost than monobead and typically have more monotonic behavior than bead. This work improves our understanding of the price of monotonicity in beam search.
Symmetric Searchable Encryption and Data Retrieval in Cloud Computing

-Cloud computing is a specialised form of distributed computing that introduces utilization models for remotely provisioning scalable and measured resources. The driving motivation behind the cloud computing is to provide IT resources as a service that encapsulates other IT resources. Data service outsourcing is one of the service that is economically enabled by the cloud computing. But in order to protect data privacy sensitive data has to be encrypted before outsourcing to the commercial public cloud. Data encryption protects data security to some extent, but this may lead to a compromise on the part of efficiency of storage and retrieval on the server. This paper analyzes various searchable encryption schemes where data owner itself is responsible for his data security. These searchable encryption schemes allow retrieval of encrypted data over the cloud thereby making data retrieval fast and efficient. These schemes also guarantee high security and efficiency.
Clustering and Classification of UVM Test Failures Using Machine Learning Techniques

—When verifying complex hardware designs, verification engineers are often faced with the problem of analyzing failures in large test suites. We describe how machine learning techniques can be applied to automate the clustering and classification of test failures according to root cause. Log files from simulations of UVM test benches were used as input and pre-processed to produce features suitable for machine learning algorithms. The performance of three clustering and eight classification algorithms was evaluated. In addition, the impact of dimensionality reduction on performance and computation time was investigated. Finally, the use of visualization algorithms for clustering was also examined. The results indicate that the most suitable clustering algorithm was DBSCAN, with AMI and ARI scores of 0.593 and 0.545 respectively. The best performing classification algorithm was random forest, with an accuracy of 0.907 and an F 1 -score of 0.913.
Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data Methods

— As the size of hardware (HW) design increases significantly, massive number of regression tests are required to validate its functional correctness with a huge amount of data generated during the design simulation for every test scenario. Debugging regression failures is a tedious and time consuming task. This paper addresses the challenge of reducing the debugging effort required to validate the changes between HW model iterations of the same design. It proposes the utilization of clustering machine learning technique to learn the design good behavior through the passing regression tests. Good tests grouped into testcases clusters such that the buggy test can be detected when it failed the assignment to any of the identified test clusters in the design regression test suite. Our framework utilizes x-means clustering techniques to identify the trace segment, design module name as well as design signals which are suspected to be the culprit of the bad behavior tests. Additionally, our work tackles two main challenges in the learning process. Firstly, signal selection step is done to decide which design signals should be included as the test features during the machine learning phase. Signal selection is based on the signal type as well as its connectivity network. Secondly, Big-Data processing technique, namely, Map-Reduce is used to overcome the challenge of processing huge trace dump resulted from design simulation. Our experimental results demonstrate the feasibility of the proposed approach to detect multiple design injected faults using mutation testing with HW designs.
SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes

—When developing a new system, it is important to confirm that the system conforms to documented requirements and supplies specific features. In verifying this, reliance on SystemVerilog Assertions (SVA), the assertion specification subset of the SystemVerilog (SV) language, has grown in recent years. There are many advantages to using SVA in design and verification: they are natively integrated into the language, they may be checked in both simulation and formal verification, and they are convenient for designers to use while coding. However, misuse of SVA and/or failure to express a requested behavior properly may lead to verification problems. This is not just a theoretical hazard; in recent Intel projects there have been numerous cases in which SVA assertions were written that either failed to match user intent, failed to be checked at all, or caused major performance degradation in simulation or formal verification. Many of these cases could have been detected early by "linting", that is, performing preprocessing or compile-time checks to detect constructs that, while formally legal, might cause correctness or performance issues. We present here lint rules we helped develop to minimize the number of verification holes caused by common mistakes.
Building Portable Stimulus Into Your IP-XACT Flow

- The upcoming Portable Stimulus standard from Accellera provides an abstract format for declaratively specifying verification intent for a given design-under-test (DUT), enabling multiple implementations of that intent to be gen-erated for the different verification platforms (simulation, emulation, prototypes, etc.) used throughout a typical verification flow. At Nokia, we use IP-XACT (IEEE Std 1685-2009) to characterize the IP blocks of our System-on-Chip (SoC) designs. This characterization captures the designers’ knowledge of a given block using machine-readable meta-data that can be used by an SoC assembly tool to build the actual design. We have found that each of these standards can increase our productivity by enabling reuse from the IP block to SoC level. This paper will examine ways to achieve even better results by combining them in our verification flow.
Field Programmable Gate Array with virtualization and dynamic channel allocation: An efficient solution for Deep Learning algorithms

— Field Programmable Gate Array (FPGA) is a computational unit that is used for custom logic implementation. These devices are special due to their flexibility in use. FPGA can be configured and reconfigured when there is a need for a change in the functionality of a connected device. To do any reconfiguration do not need to physically remove the connected FPGA hardware. FPGAs are also a better solution if looking for enhancing the existing hardware infrastructure for advanced usage. Increased execution lifetime is also an added advantage when we consider FPGAs for our implementation. Fetching data for computation is a very critical process when we execute any application on either our Personal Computer or in datacenter servers. If the CPU is involved in every data read/write operation then it becomes overhead for the processor because of this the total performance of the system will degrade. The direct Memory Access controller is an external device that takes care of data transfer in both CPU registers to memory and memory to memory. The MCDMA IP for PCI Express enables the efficient transfer of data using multiple DMA channels between the host and device. The flexible nature of an FPGA arises with the considerable overhead in size, time, and energy usage: an FPGA requires approximately much more area when compared with a normal Application Precise IC component, and also gives slower performance when considering the speed of computation with Application Specific IC and needs much more dynamic power. This drawback is due to FPGA’s programmable routing fabric which needs more space, computation time, and energy to implement “immediate” fabrication. Reprogrammable hardware devices used for performance enhancement have the drawbacks that the connecting functionality provided by hardwired IP blocks covers only the lower protocol layers, and a huge effort is required to achieve high-throughput data transmission between host and accelerator devices. MCDMA for PCI Express operates using a FIFO data structure that stores descriptors, the descriptor queue is set up by the driver program to move data between FPGA and host. Its program fetches descriptors and processes them to get transmission data. To improve the performance, different descriptor queue structures can be used for host-to-device and device-to-host operations for each channel. On the user logic side, we can use memory-mapped and streaming interfaces which will allow for easy integration of the Multi-Channel Direct Memory Access Intellectual Property with other Platform Designer components. In summary, introducing Single Root IO Virtualization on the physical function which supports the creation of virtual functions, and using dynamic channel allocation, can achieve enhanced speed and performance efficiency. With this experiment, we got an 8.49% performance enhancement in terms of bandwidth, when SRIOV and DCA are enabled.
An Integrated SiC CMOS Gate Driver for Power Module Integration

With high-temperature power devices available, the support circuitry required for efficient operation, such as a gate driver, is needed as part of a complete high-temperature solution. The design of an integrated silicon carbide (SiC) gate driver using a 1.2-μm complementary metal–oxide–semiconductor (CMOS) process is presented. Adjustable drive strength is added to facilitate a minimal external component requirement for high-temperature power modules and lays the groundwork for dynamic adjustment of drive strength. The adjustable drive strength feature demonstrates a capability of reducing overshoot and controlling dv/dt dynamically. Measurement of the gate driver was performed driving a power mosfet gate over temperature, exceeding 500 °C. High-speed and high-voltage room temperature evaluation is provided, demonstrating a system capable of high performance over temperature. The driver accomplishes better than 75 ns of rise and fall time driving the Cree CPM3-0900-0065B from room temperature to over 500 °C indicating that it will be ideal for integration into an all-SiC power module where driver, protection circuits, and power devices are fabricated in SiC.
Maternal employment and childhood nutrition in Ecuador

This study explores the association of maternal employment on childhood nutrition in Ecuador by understanding the trade-off between the maternal time devoted to work and childcaring. I use exogenous regional variation of the labor market as an instrument. Using the National Health and Nutrition Survey 2018, I estimate the causal effect of maternal labor supply on children’s nutrition outcomes based on anthropometrics measurements. Maternal employment increases the probability of having stunted children, while I have not found any effect of maternal employment on children suffering from wasting, underweight and overweight. The results are robust and account for possible endogeneity sources.