Aalborg Universitet Measurement , Modeling and Suppression of Substrate Noise in Wide Band Mixed-signal

Ultra-Wideband (UWB) technology is expected to become one of the key main-stream communication platforms for the coming decades. At the same time, the demand for low-cost and compact implementations of wireless systems makes Complementary Metal-Oxide Semiconductor (CMOS) one of the most promising technologies for the development of such single chip UWB systems. However, UWB systems are sensitive to noise owing to the ultra wideband nature and low power spectral density of the signal. Using CMOS to implement UWB systems makes the situation even worse as it brings along another noise issue, substrate noise. To solve this problem, the substrate noise has to be characterized and subsequently efficient strategies for cancellation/suppression have to be developed. The main goal of this research work is to study substrate noise related issues in mixed-signal integrated circuits, focusing on ultra wide band (UWB) systems, and to find mitigating solutions for those issues. To provide reliable measurement results for the validation of proposed models and noise suppression techniques, a measurement method suitable for measuring wide band substrate noise is proposed. The method relies on a passive fixture based on ohmic contacts and a layout that makes it suitable for on-wafer measurement using ground-signal-ground probes. The parasitic components affecting the measurement are investigated by EM simulations and measurements. Test chips are designed using a 0.18 μm lightly doped CMOS process to evaluate the performance of the fixture. Several practical design rules for reducing the parasitical effects are concluded based on measurement results. An experimental impact evaluation of substrate noise on an UWB LNA has been conducted, aiming to find out the mechanism by which the substrate noise affects the UWB sensitive circuits. The measured results reveal the significant performance (noise figure) deterioration of the UWB LNA due to substrate noise issues. A novel analytical model for the switching noise generated by individual inverters is proposed. Based on the proposed model, the spectrum envelope of the substrate noise can be predicted in the early design stage. This has been verified by the measured results from a test chip implemented using a standard 0.18 μm CMOS process. In addition, statistical methods have been used to analyze the noise features of large scale digital blocks. The random switching activities of digital circuits leads to variable time delays and amplitude fluctuations of substrate noise, which can be equivalently modeled as multi-path fading. Therefore, the frequency selective feature of the substrate noise is modeled using the propagating delay of the digital circuits. MATLAB and SPICE simulation results have shown supports for this. In the analysis of suppression methods both active and passive strategies are considered. Based on the substrate noise model developed in this work a novel active noise suppression technique is proposed. In this technique, an active spectrum shaping section is used to generate extra switching currents to modify the shape of the original switching noise in both time and frequency domain. The relative time delays of these switching currents to the original switching current are realized by controllable delay lines. The pulse widths and magnitudes of the switching currents are also controllable. By manipulating the extra switching currents, the spectrum of the total switching noise can be shaped to have a suppressed magnitude at desired frequencies. In addition, analytical modeling of guard rings for substrate noise isolation in lightly doped substrates is presented. A resistive T-network is proposed to characterize the aggressor-guard ring-victim layout, and closed form expressions for the calculation of spreading resistances in the network are presented. Using this model the effects of the layout parameters can be taken into account during the pre-layout design phase, and the isolation performance of the design can be accurately predicted.