Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

The semiconductor industry, governed by the Moore's law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor that allowed the manufacturers to pack more and more functionality into the same chip area. However, it is now widely agreed that the happy days of scaling are well over and we are about to reach the physical limits of the CMOS concept. One major, insurmountable limit of CMOS is the so-called thermionic emission limit which dictates that the switching slope of the transistor cannot go below 60mV/dec at room temperature. This makes it impossible to scale down the supply voltage for CMOS transistor without dramatically increasing the static power consumption. To address this issue, a novel transistor concept called Tunnel FET (TFET) which utilizes the quantum mechanical band-to-band tunneling (BTBT) has been proposed. TFETs possess the potential to overcome the thermionic emission limit and therefore allow for low supply voltage operation. This thesis aims at investigating the performance of TFETs with alternative architectures exploiting quantized carrier gases through quantum mechanical simulations. To this end, 1D and 2D self-consistent Schrodinger-Poisson solvers with closed boundaries are developed along with the phonon-assisted and direct BTBT models implemented as a post-processing step. Moreover, we propose an efficient method to incorporate the quantization along the transverse direction which enables us to simulate different dimensionality combinations. The implemented models are calibrated against experimental and more fundamental quantum mechanical simulation methods such as k.p and tight-binding NEGF using tunneling diode structures. Using these tools, we simulate an advanced TFET architecture called electron-hole bilayer TFET (EHBTFET) which exploits BTBT between 2D electron and hole gases electrostatically induced by two separate oppositely biased gates. The subband-to-subband tunneling is first analyzed with the 1D simulator where the device working principle is demonstrated. Then, non-idealities of the EHBTFET operation such as the lateral tunneling and corner effects are investigated using the 2D simulator. The origin of the lateral leakage and techniques to reduce it are analyzed in detail. A parameter space analysis of the EHBTFET is performed by simulating a wide range of channel materials, channel thickness and oxide thicknesses. Our results indicate the possibility of having 2D-2D and 3D-3D tunneling for the EHBTFET, depending on the parameters chosen. A novel digital logic scheme utilizing the independent biasing property of the EHBTFET n- and p-gates is proposed and verified through quantum-corrected TCAD simulations. The performance benchmarking against a 28nm FD-SOI CMOS technology is performed as well. The results indicate that the EHBTFET logic can outperform the CMOS counterpart in the low supply voltage (subthreshold) regime, where it can offer significantly higher drive current due to its steep switching slope. We also compare the different dimensionality cases and highlight important differences between the face and edge tunneling devices in terms of their dependence on the device parameters (channel material, channel thickness and EOT).