Design of an Accurate LLRF System for an Array of Two-Gap Resonators

A particle accelerator based on an array of two-gap resonators requires a control system, which is responsible for precise setup and stabilization of the phase and magnitude of the electromagnetic field in resonators. We develop a cost-effective LLRF system for the array of more than 80 resonators and three different operating frequencies. The design is based on proved solution used for 5-resonators accelerator HILAC (project NICA, Dubna). This paper gives an overview of the basic structure and some specific features of the developing LLRF control system. STRUCTURE OF THE LLRF The low-level radio-frequency control system is a part of more general system controlling the whole linear accelerator as it is shown in Fig. 1. Components of the system are distributed over the large area along the accelerating structure and inside of service rooms. The communication network based on Ethernet technology unites the modules into single fast and stable system. Some control tasks are incapsulated into subsystems supported by virtual subnet networking. The accelerating section is built as a row of similar two-gap resonators (see Fig. 2) Figure 2: Two-gap resonators in a row. The structure of the accelerator also determines the structure of the system for monitoring and stabilizing highfrequency fields in resonators. Such a structure is shown in Fig. 3. The carefully synchronized multi-channel reference generator REF is mounted in a single housing and installed in the radio equipment room together with powerful highfrequency amplifiers A. Control measurements are the responsibility of many distributed control unit modules (CU) that serve each accelerating resonator separately. Figure 1: The general structure of the linac control system. ___________________________________________ † liakin@itep.ru 12th Int. Particle Acc. Conf. IPAC2021, Campinas, SP, Brazil JACoW Publishing ISBN: 978-3-95450-214-1 ISSN: 2673-5490 doi:10.18429/JACoW-IPAC2021-WEPAB298 WEPAB298 C on te nt fr om th is w or k m ay be us ed un de rt he te rm s of th e C C B Y 3. 0 lic en ce (© 20 21 ). A ny di st ri bu tio n of th is w or k m us tm ai nt ai n at tr ib ut io n to th e au th or (s ), tit le of th e w or k, pu bl is he r, an d D O I 3360 MC6: Beam Instrumentation, Controls, Feedback and Operational Aspects T27 Low Level RF Figure 3: The general structure of the LLRF. The LLRF system of the linac deal with resonators operating on different frequencies. There are 40.5, 81 and 162 MHz resonators in use. A large number of similar resonators encourages the development of a small standard circuit, which is located in the near of the controlled cavity. Such a device closes the local control loop, covering the measuring and mechanical parts of the automatic frequency control system. THE RESONATOR CONTROL UNIT Figure 4 shows the general signal structure of the local control unit of an accelerating resonator. The unit mainly consists of a multichannel analog-to-digital converter with an FPGAbased digital signal processor, and this is combined to another multicore processor for general purposes use. Figure 4: A control unit of a resonator. The controller involves three signals to see the input RF power level and the resonator frequency mismatching. It also performs full control over the mechanics of the resonator tuner. Nevertheless, the measured data is transmitted to supervisor unit which is also responsible for issuing of the movement commands. It is also important to keep exact phase relation between resonators in the long resonators array. One of the functions of the control unit is a precise control of the phase advance between electromagnetic field in resonator from one hand and a stable dedicated reference signal from another. Signals from the reflectometer are received without rectification. They are numerically converted from sinusoidal to the complex vector form in cartesian or polar coordinates. Programming model of the control unit is presented in Fig. 5. The DSP implements an agile but straightforward data transformation algorithm using expensive FPGA resources. The memory blocks of the FPGA are filled by decimated RF pulse data in a burst mode. This takes about one millisecond after receiving of the synchronisation pulse. Then the classical ARM processor has enough time to rewrite the data into the buffer in the low-cost dynamic memory. Figure 5: Programming model of the control unit. THE SIGNAL PROCESSOR The RF signals are sampled directly by the ADC. The signal strength and spectra allow eliminate analog electronics in front of the ADC. The downstream digital data processing is quite conservative (see Fig. 6). The signal A is shifted in the frequency domain toward the low-frequency region. The mirror component of the signal is suppressed by a low-pass filter. The decimator rarefied the data reducing the data rate down to value which is more adequate to the bandwidth of the input signal. More detailed description of the used algorithms could be found here [1]. Figure 6: The base algorithm for the digital data processor. There is a small difference in the processing of the reference signal. The reference signal is constantly present at the measurement input and the digital PLL circuit with the IIR filter makes the most of this feature. The effective and proven choice for the AD-converter is an 8-channel device with 14-bit resolution. This device operates in undersampling mode reducing the raw data rate and, therefore, does not required expensive interface to the FPGA chip. Eight AD channels option is a good opportunity for improving the cost factor of the control unit. Single module could implement two virtual control units as it is shown in Fig. 7. REF R A