Characterization of negative bias temperature instability and lifetime prediction for pMOSFETs

In order to achieve high speed and packing density, the size of the transistor has shrunk aggressively. The gate dielectric, as the most critical component in the transistor, is undergoing rapid and substantial changes with the adoption of ultra-thin plasma nitrided oxide and more recently high-k dielectrics. As the nitrogen concentration in silicon oxynitrides (SiON) increases, the negative bias temperature instability (NBTI) rises and becomes a limiting factor for device lifetime. The NBTI can recover significantly during typical measurement time when using conventional instruments. To suppress this recovery, several fast techniques have been developed, including ultra-fast pulse Id-Vgtechnique and the On-The-Fly technique. These techniques, however, give different threshold voltage degradation (~VI) after the same stress. The interpretation of this difference is still controversial. The objective of chapter 3 is to bridge the gap between the ~Vt extracted from these techniques. Degradation and recovery during measurement, measurement and truncation errors, and evaluation of transconductance are examined. After taking these factors into account, the gap in llVt still cannot be filled. The effect of the sensing Vg on l::,. Vits considered and it is found that 111VtinI creases with sensing IVgl.The popular assumption of t:. Vt being independent of sensing Vg is invalid, thereafter. After taking both the effect of sensing Vg and recovery into account, the gap in llVt is successfully bridged. The difference between the effect of sensing Vg and recovery is explored, and the results show that they are two different phenomena. The recovery suppression and the sensing Vg effect challenge the applicability of the traditional lifetime prediction technique. In a large circuit with roughly 106 MOSFETs, there will always be some of them under the worst case condition, namely constant stress without recovery. The failure of one of these MOSFETs can lead to the malfunction of the whole circuit. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can be applied. In chapter 4, the worst case lifetime prediction is investigated. It is found that the prediction based on the Vg acceleration results in substantial errors. To predict the worst-case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects and it no longer follows a simple power law. Based on the new kinetics, a single test prediction method is proposed and its safety margin is estimated to be 50%. Mobility reduction is another important issue when oxide thickness becomes thinner. It is reported that when the gate SiON becomes thinner than 2 nm or the interfacial layer in high-k stack is thinner than 2.5 nm, carrier mobility reduces. Agreement has not yet been reached on the level of reduction, or on the underlying mechanism. Remote charge scattering (ReS) has been proposed to be responsible for this mobility reduction. However, one weakness of earlier work is that different samples were used when experimentally studying the Res and this introduces uncertainties. For example, a reduction in oxide thickness does not only bring the gate closer to the substrate, but also modulates other factors such as surface roughness. In chapter 5, the importance of ReS is assessed by varying charge in the same device through either processing or electron trapping, to remove the uncertainties from using different devices. It is found that by increasing charge density at 0.56 - 1 nm from the substrate interface to the order of 1020 ern", both electron and hole mobility change little.