ESD and ionizing radiation effects on ultrathin body SOI and multiple gate technologies

This thesis addresses two main reliability challenges of advanced UltraThin Body (UTB) Silicon On Insulator (SOI) and FinFET CMOS technologies: ElectroStatic Discharge (ESD) and (space) ionizing radiations. First, both technologies have a limited available silicon volume to dissipate the ESD current. Therefore, a detailed ESD analysis on such devices is required. Secondly, these advanced technologies will be incorporated in future Commercial-Off-The-Shelf (COTS) components that may be used in space applications, which rennires the impact of ionizing radiation on such technologies. ESD analysis has been performed on structures implemented in planar UTB SOI, SOI FinFET, and bulk FinFET technologies. Complex dependencies of the different ESD performance parameters on both device geometry and process technology are found. For UTB SOI devices, a detailed electrical investigation is carried out in order to carefully classify the observed failure mechanisms. It is found that grounded gate NMOS devices are robust enough when local clamping devices are used, and that strain improves the ESD robustness and has an impact on the device failure mechanisms. Concerning FinFET technology, non-uniform failure exists for grounded gate NMOS devices at high current levels which can be improved by increasing gate length and various ballasting techniques. On the other hand, voltage clamping capability seemed more of a concern due to the oxide breakdown voltage for long gate lengths. Narrow fin devices have improved cooling properties, especially for bulk FinFETs, but suffer from reduced area efficiency. Selective epitaxial growth, strain, and silicide blocking can improve the ESD performance of FinFET devices. From RF point of view, concerning SOI FinFET technology, the large overhead capacitance of the narrow-fin devices degrades the RF figure of merit with respect to the wide fin devices, making wide-fin devices the preferred choice. Regarding bulk FinFET technology, the landing pad of narrow-fin devices is not fully used during the current conduction; however, the full junction contributes to the parasitic capacitance. Therefore, despite the quite remarkable improvement in ESD robustness observed for narrow-fin bulk FinFET devices, narrow and wide-fin bulk FinFET diodes have similar ESD-RF performance, which is comparable to the best SOI FinFET diodes. Heavy-ions induced microdose has been investigated on MOS in planar UTB SOI and SOI FinFET technologies. The degradation of the electrical DC parameters is found to strongly depend on both device geometry and process technology. UTB SOI devices display the lack of early breakdown due to the very thin gate oxide, and varying impact on the long-term degradation kinetics depending on the adopted technological solutions. Concerning SOI FinFETs, the changes of the DC parameters after irradiation strongly depend on the Linear Energy Transfer (LET), incidence angle, strain, and channel type, depending on the balance between damage to the high-k (top and sidewall) gate oxide and to the buried oxide. In addition, heavy-ion strikes impact both on the degradation kinetics and on the time to breakdown under constant voltage stress. The soft rupture of the gate oxide is a considerable concern, not only for the increase in gate leakage, but also for the effects on the DC characteristics. Interface state generation in the side oxide/body interface, due to ions passing through the lateral gates, is another remarkable effect that can be observed only with these vertical devices. Heavy ions can induce permanent damage on FinFETs with large statistical spread. The distribution of the inverse of the gate leakage currents and of the threshold voltage shifts follows a Weibull distribution. Moreover, the reciprocal of the gate leakage current does not respect the Poisson area scaling. A new model for the gate leakage current is proposed, predicting a size of the heavy-ion damage of 30 nm and a higher defect generation takes place in the sidewall gate oxide. Dose enhancement effects due to interconnects in deep-submicron CMOS have been studied. The presence of metal-1 tracks in the proximity of the device active areas significantly modifies the response to X-rays. The impact of the secondary electron emission from metal-1 layers is strongly dependent on the relative position to the transistor lateral isolation and LDD spacers. In conclusion, ESD is not a showstopper for the introduction of UTB SOI and FinFET technologies. However, heavy-ion induced microdose is a serious concern for multiple gate technologies, while it is not a showstopper for the UTB SOI. Finally, dose enhancement in deep-submicron devices must be carefully considered when X-ray facilities are used to perform total-dose tests.