Fully Integrated Discrete-Time Superheterodyne Receiver in Nano-Scale CMOS

In a radio-frequency (RF) system-on-chip (SoC), a digital baseband/application processor, which occupies most of the silicon area, determines the SoC fabrication process technology and voltage supply. The rest of the circuitry, including RF front-end and frequency synthesizer, must then adopt the chosen process technology, i.e., presently low-voltage deep nano-scale CMOS. To design a fully integrated power/area efficient receiver in this respect, new RF/analog techniques are required to be able to function well at the reduced voltage headroom. In addition, new oscillator structures need to be developed that can work at low supply voltages and in face of poor quality current sources while providing high spectral purity. On the other hand, conventional RF/analog designs have not benefited significantly from CMOS scaling, which continually reduces transistor cost and improves digital performance. Here in this thesis, traditional continuous-time (CT) analog components, such as opamps, are avoided and, instead, most of signal processing and filtering is done using passive switched-capacitor circuits in discrete-time (DT) domain. In this way, the receiver front-end becomes process scalable similar to digital circuits enjoying performance and cost improvements with each process scaling node. In the first part of this dissertation, principles, design and implementation of a fully integrated DT superheterodyne receiver frontend are described. To start with, the optimal sampling scheme in a high-intermediate frequency (IF) receiver architecture is explained. It is followed by sequentially introducing all the constituent circuits. A novel DT high-order low-pass filter is proposed to be used at the receiver baseband. This filter has an exceptionally low noise and high linearity. Deep analysis, verified by test-chip measurements, is presented. Next, a very high 156 Summary sampling rate DT bandpass filter (BPF) using I/Q charge sharing is proposed and analyzed. Then, a novel wideband noise-cancelling LNTA is proposed with a two-fold noise cancellation technique. Finally, a fully integrated DT superheterodyne receiver is proposed with explanations to its DT model, frequency translations, and image rejection mechanisms. The whole idea, design and analyses are successfully verified by a 65-nm CMOS test chip. The implemented receiver has an exceptional high uncalibrated IIP2 of +90 dBm. In the second part of this dissertation, design and implementations of low-voltage fully integrated oscillators in nano-scale CMOS are discussed. First, a high-swing class-C oscillator is proposed that efficiently uses the drastically reduced supply voltage in nano-scale CMOS. Measurement results of a low-power low-voltage test chip in 90-nm CMOS shows phase noise figure-of-merit as high as 192 dBc/Hz from a 0.6V power supply. The idea of the high-swing class-C oscillator is extended to an ultra-low phase noise dual-core oscillator implemented in 65nm CMOS. This oscillator is the first-ever fully integrated design that meets phase noise requirements of a GSM basestation standard in a bulk CMOS technology. Next, another novel low-voltage oscillator topology is proposed that uses a series-LC tank ring structure. Its realization in 40-nm CMOS targets low silicon area using low-Q inductors. It exhibits 7–20 dB better phase noise than other state-of-the-art low area oscillators.