Toward dynamically reconfigurable high throughput multiprocessor Turbo decoder in a multimode and multi-standard context

Recent years have seen a huge evolution of wireless communication standards in the domains of mobile phone, local and wide area networks and video broadcasting. These evolutions aim at increasing the requirements in terms of throughput, robustness against destructive channel effects and convergence of services in a smart terminal. As an example, the fourth generation (4G) of cellular wireless standards aims at providing mobile broadband solution to laptop computer wireless modems, smartphones, and other mobile devices. Diverse features such as ultra-broadband Internet access, IP telephony, gaming services, and streamed multimedia are provided. In order to enable such advanced services at the algorithmic level, new state of the art data processing techniques have been developed and adopted in the emerging wireless communication standards. At the architecture level, many efforts are being conducted towards the design of flexible high throughput hardware platforms which can be configured to the required configuration. In order to reach high flexibility, the I.A. S. (Algorithm Silicon Interaction) team of the Lab-STICC laboratory has developed an Application Specific Instruction Set Processor (ASIP) based multi-standard multiprocessor Turbo decoder. This architecture is based on the DecASIP processor. Previous work provides an efficient way to reach the high performance and high flexibility requirements of emergent standards. However, dynamic reconfiguration aspect of the architecture has not been addressed. In this context, this Ph.D work targets the development of a dynamically reconfigurable multiprocessor Turbo decoder for future communication standards. For that purpose, this thesis work is divided in several steps: The first step consists on the study of the initial processor architecture in order to propose optimizations in a multiprocessor context. This step leads to a new implementation of the DecASIP processor integrating a new configuration memory organization in order to reduce the configuration transfer latency. The second step leads to the development of a configuration infrastructure allowing an efficient and high speed configuration transfer for the ASIPs and the controller of the platform. The proposed approach is based on a low complexity unidirectional pipeline bus implementing optimized transfer mechanisms such as multicast and broadcast. This configuration infrastructure provides an efficient solution in order to transfer an entire configuration for 128 processors in less than one microsecond. Finally, the last step of this thesis work concerns the development of a configuration management of the proposed platform in order to adapt the configuration parameters regarding the environment evolution and the application requirements. This step leads on an approach allowing the support of dynamic configuration of the platform in the context of highly constrained scenario in terms of throughput and error rate performances where each frame or group of frames is associated to a specific configuration. This thesis work will allow the laboratory to present a prototype of a dynamically reconfigurable Turbo decoder respecting future communication standards requirements in terms of flexibility, throughput and error rate performances. Such a contribution gathers the skills present in the Lab-STICC laboratory at the decoding algorithm, multiprocessor architecture, dynamic reconfiguration and self-adaptation levels in a single prototype.