A DAG-Based Approach to Modeling Bottlenecks on Modern Microarchitectures

Software and computing systems interact in such complex ways that applications rarely optimally utilize all the resources provided by the microarchitecture. Understanding what are the inherent bottlenecks (i.e., those determined by the true data dependencies of the applications’ computation DAG), as well as microarchitectural bottlenecks (i.e., those that result from the execution on a given platform), is difficult but important as it can help with both further optimizing the code or deciding which microarchitectural organizations match applications’ properties and yield balanced systems. In this dissertation we address the problem of formally reasoning about the interaction of applications’ inherent properties and the underlying microarchitectural resources using a modeling approach. We focus on a restricted but important domain: Floating-point numerical applications running on a single-core superscalar architecture with SIMD capabilities. We propose a novel DAG-based performance model and its implementation as a software tool, that dynamically analyze the execution of the application on an abstraction of a processor that includes common resources of modern microarchitectures, such as a multi-level cache hierarchy, or out-of-order execution. The proposed model provides more accurate estimates on performance than prior high-level DAG-based analytical models, without the need of sophisticated cycle-accurate simulators, or access to the platform. More important, it yields detailed data about the (modeled) execution of the application that we use to develop various forms of bottleneck analyses. First, we quantify the available ideal-case instructionand thread-level parallelism to understand if applications exhibit enough inherent parallelism to harness the parallel resources provided by the platform. We provide new insights into the amount of available parallelism by analyzing full distributions of ILP, rather than simply reporting average values as in previous limit-case parallelism studies. We also present an execution-driven approach to identifying the ideal task partitioning that minimizes data movement, along with a method to identify regions with potential data-level parallelism. Second, we identify microarchitectural bottlenecks by means of a generalized roofline plot that simultaneously visualizes bottlenecks through multiple rooflines. These are associated with processor resources including latency and throughput of the computational units and the memory hierarchy, and the size of caches and out-of-order execution buffers. We show that our proposed bottleneck model and associated generalized roofline plot yield tight bounds on performance and, additionally, provide insights about where execution cycles are spent, how they are distributed across resources, and their contribution to the application’s performance. Finally, we propose a new definition of balance for modern single-core microarchitectures that can be measured using our modeling framework to be usable in practice. Using the proposed framework, we show that we can find balanced derivatives starting from a given microarchitecture, and that they usually exhibit, whithin the model, high utilizations of computational and memory throughputs.