The Size and Depth of Boolean Circuits : A Dissertation Proposal

In this thesis, we study the relationship between size and depth for Boolean circuits. Over four decades, very few results were obtained for either special or general Boolean circuits since Spira gave the first related result. Spira showed in 1971 that any Boolean formula of size s can be simulated in depth O(log s). (A Boolean formula is a tree-like circuit, that is the fan-out of every gate is 1.) Spira’s result means that an arbitrary Boolean expression can be replaced by an equivalent ”balanced” expression, that can be evaluated very efficiently in parallel. For general Boolean circuits, the strongest known result is that Boolean circuits of size s can be simulated in depth O(s/ log s). This result was first proved by Paterson and Valiant in 1976, and later proved by Dymond and Tompa in 1985 using another method. There are many consequences if the simulation for general circuits can be improved in a uniform setting, including implications about the relationship between deterministic time and space in the Turing machine model, deterministic time of Turing machines versus parallel time in the PRAM model, circuit size versus formula size, and the Circuit Value problem. We obtain significant improvements over the general bounds for the size versus depth problem for special classes of Boolean circuits. We show that every layered Boolean circuit of size s can be simulated by a layered Boolean circuit of depth O( √ s log s). For planar circuits and synchronous circuits of size s, we obtain simulations of depth O( √ s). The proof for layered circuits uses an adaptive strategy based on the two-person pebble game introduced by Dymond and Tompa. Improving any of the above results by polylog factors would immediately improve the bounds for general circuits. We generalize Spira’s theorem and show that any Boolean circuit of size s with segregators of size f(s) can be simulated in depth O(f(s) log s). Moreover, if the segregator size is at least sc for a constant c > 0, then we can obtain a simulation of depth O(f(s)). This improves and generalizes a simulation of polynomial-size Boolean circuits of constant treewidth k in depth O(k2 log n) by Jansen and Sarma. Since the existence of small balanced separators in a directed acyclic graph implies that the graph also has small segregators, our results also apply to circuits with small separators. Our results imply that the class of languages computed by nonuniform families of polynomial size circuits that have constant size segregators equals non-uniform NC1. For f(s) log s-space uniform families of Boolean circuits, our small-depth simulations are also f(s) log s-space uniform. As an application, we show that the Boolean Circuit Value problem for circuits with constant size segregators (or separators) is in deterministic SPACE(log n). Our results also imply that the Planar Circuit Value problem, which is P -Complete, can be solved in deterministic SPACE( √ n log n). We also present a result for skew circuits, where we use the notion of algebraic degree defined by Skyum and Valiant, and apply the techniques in Valiant, Skyum, Berkowitz and Rackoff. We show that any skew Boolean circuit of size s can be simulated by a Boolean circuit of depth O(log s). The simulation for skew circuits does not follow from any of the results above. For future work, one direction is to try to improve our results for special circuit classes. Already small improvements of our results could potentially improve the best known bounds for general circuits. Another direction is to try to extend our