A Significant Technology Advancement in High-Speed Link Modeling and Simulation

As high-speed I/O (HSIO) and serial link data rates keep increasing, the requirements for accuracy and advanced simulation and modeling techniques get more stringent. Emerging requirements, such as the ability to model process, voltage, and temperature (PVT) variations at deep submicron process nodes or smaller, to fully account for all the circuit blocks of the link, and to close the gap between modeling and measurements, have become critical. However, conventional simulation and modeling methods cannot meet most, if not all, of the requirements. This paper reviews the techniques used in recent HSIO simulation and modeling, such as statistical behavioral, SPICE, and IBIS-AMI models, outlining the areas where they fall short in comparison with the emerging requirements. This paper also introduces the Intel® Advanced Link Analyzer and discusses how the tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the Intel Advanced Link Analyzer tool can meet the emerging requirements. Introduction HSIO and serial link speed double every two to three years on average (1) to meet the ever increasing bandwidth demands for network and computer systems. In addition to bandwidth benefits, speed doubling also enables density and throughput to double for a device or board. Using PCI Express* (PCIe*) as an example, its speed has increased from 2.5 Gbps (Gen1), to 5.0 Gbps (Gen2), to 8 Gbps (Gen3), and to 16 Gbps (Gen4). Another example is the Optical Internetworking Forum (OIF) Common Electrical I/O (CEI) implementation agreement, which states its Gen1 speed at 6.5 Gbps, Gen2 at 11.3 Gbps, Gen3 at 28 Gbps, and Gen4 at 56 Gbps. At 28 Gbps, the unit interval (UI) is only 35.7 ps for a non-return-to-zero (NRZ) modulated signal, and this timing budget has to be shared by the transmitter (TX), receiver (RX), and channel (CH). This means that the TX and CH will get approximately 30 percent of the UI each, and the RX will get approximately 40 percent (2). When all the timing and jitter impairments are considered, meeting a UI of 35.7 ps at 28 Gbps is challenging. It gets even more challenging at 56 Gbps, where the UI is 17.9 ps. Therefore, accurate and capable simulation and modeling techniques are critical for designing HSIO circuits, devices, and links. As the data rate increases, the intersymbol interference (ISI) gets worse due to the lossy characteristics of the copper channel. To mitigate the ISI at higher data rates, various equalization circuits have been developed, including TX finite impulse response (FIR), RX continuous linear equalizer (CTLE), and RX decision-feedback equalizer (DFE). Figure 1 shows a typical high-speed link and its subcomponents at 10 Gbps and above for a backplane, typically with an insertion loss of 25 dB or higher, and consisting of PCBs, connectors, and vias. In addition to the equalization circuit blocks, a clock generation (CG) circuit via a phase-locked loop (PLL) for Authors Mike Peng Li Fellow Intel® Corporation Hsinho Wu Principal Engineer Intel® Corporation Masashi Shimanouchi Principal Engineer Intel® Corporation Salman Jiva Senior Product Marketing Manager Intel® Corporation Udayan Sinha Product Marketing Engineer Intel® Corporation Lux Joshi Product Marketing Manager Intel® Corporation A Significant Technology Advancement in High-Speed Link Modeling and Simulation Intel® FPGA Table of