Latency directed multithreaded computation and its architectural support

Multithreading is an architectural technique, which allows the interleaved execution of multiple instruction streams (threads) on a von Neumann-like processor. Multithreaded architectures combine features from both von Neumann and data ow architectures, so that the new architecture possesses the simplicity of von Neumann architectures and avoids the complexity and ine ciencies of data ow architectures. While multithreading is conceptually appealing, little work has been reported on actual performance evaluation, on the architectural advantages and the limitations, and on the requirements of the execution model and its corresponding hardware support. The overall goal of this work is to investigate these issues systematically. This investigation is based on the belief that some fundamental changes in von Neumann architectures are required to build e cient multithreaded architectures. The work begins with an investigation of performance aspects of conventional pipelined processors. We use a simple performance model to evaluate di erent mechanisms used in pipelined processors for reducing the performace lost due to pipeline hazards. Multithreading, also as an alternative to conventional pipelining, allows to completely hide pipeline hazards by exploiting parallelism among multiple instruction streams (threads). To understand the potential performance advantage of the multithreading technique, the performance issues of multithreaded architectures have been investigated. Based on the investigations of di erent multithreading strategies and their performance, a new multithreaded computation model is proposed, called latency directed multithreaded execution (LDME). The LDME model separates instructions into two di erent groups: in one group all instructions have a xed execution latency (such as arithmetic or logic instructions), and in the other group all instructions have an unpredictable or longer execution latency (such as oating point operations, remote load or write, synchronization instructions etc.). All instructions with unpredictable or longer latency will be split with the technique called split phase transaction. We construct all such execution threads in which the result of an instruction with unpredictable latency will never be used by another instruction within the same thread. The consequence of this approach is that all threads are latency free, namely after initiation they are executed until completion without any long blocking. Hence, if su cient parallelism exists in a program, all kinds of latencies (i.e. memory and long execution latency) can be hidden. A corresponding processor architecture for the LDME model is then proposed. The main part of the LDME processor consists of a multithreaded pipeline and a synchronization processing unit. The multithreaded pipeline exploits the advantages of multithreading, while the synchronization processing unit executes all latency synchronization threads, which are introduced to synchronize parallel normal threads. Like other data ow and multithreaded processors, the proposed LDME processor can hide long remote latencies in a multiprocessor environment. To improve the single-thread performance the LDME processor employs the strategy of extracting inter-thread parallelism only when no intra-parallelism exists. The processor also uses the multithreading technique to completely hide e ects of pipeline hazards between instructions within the same thread: the dependency information is integrated in each instruction, so that the processor can detect the dependency after the instruction fetch and switches to another active thread if any dependency is detected. Thus, the processor interleaves several active threads during execution and sustains its peak performance if a limited number of active threads reside in the processor, without some related hardware mechanisns used for detecting and resolving such pipeline hazards as in conventional pipelined processors. The construct and the evaluation of LDME codes is a further issue of this work. To observe the e ects of di erent latencies on the performance of LDME codes, two di erent cases for storage of operation data are considered. The simulation results are presented. Finally, some perspectives for further research are outlined.