Quiescent Signal Analysis for IC Diagnosis

Theuseof IDDQ testasa defectreliability screenhasbeen widely used to improve device quality. However, the increasein subthresholdleakage currents in deep-submicron technologies has madeit difficult to set an absolute pass/failthreshold.Recentwork hasfocusedon strategies that calibrate for processand/or technology-relatedvariation effects. In this paper , a new IDDQ technique is proposed that is based on an extension of a VDDT-based method called Transient Signal Analysis (TSA). The method,calledQuiescentSignalAnalysisor QSA,usesthe IDDQs measur ed at multiple supply pins as a meansof localizing defects.Increasesin IDDQ due to a defectare regionalizedby the resistiveelementof the supply grid. Therefore, each supplypin sourcesa uniquefractionof the total IDDQ drawn by the defect.The methodanalyzesthe regional IDDQs and “triangulates” the position of the defectto an (x,y) location in the layout. This information can be used in combinationwith fault dictionary-based techniquesas a meansof further resolving the defect’ s location. 1.0 Introduction IDDQ hasbeenusedextensi vely asa reliability screen for shortingdefectsin digital integratedcircuits. Unfortunately, traditional IDDQ methodsappliedto devices fabricatedin newer deep-submicrontechnologiesare resulting in unacceptablyhigh levels of yield loss. The significant increasein subthresholdleakagecurrentsin thesetechnologiesis makingit difficult to setanabsolutepass/f ail threshold that fails only defecti ve devices [1]. Several methods have beenproposedassolutionsto the subthresholdleakagecurrentproblemand,more recently, to processvariation issues.Currentsignatures[2], delta-IDDQ [3] andratioIDDQ [4] arebasedon a “self-relative” analysis,in which the “average”parametricbehavior of eachdevice is factored into the pass/f ail thresholdvalue. In the following discussion,we will refer to the technologydependenc y of subthresholdleakagecurrentasa technology-relatedvariation effect to contrast it with the chip-to-chip variation effects causedby changesin processparameters(process variation). Theapproachproposedin this paperis basedon a previousVDDT-basedmethodcalledTransientSignalAnalysis (TSA) [5]. TSA usesregressionanalysisto calibratefor processand technology-relatedvariation effects by crosscorrelatingmultiple supplypin transientsignalsmeasured undereachtest sequence. The IDDQ methodproposedin thispaper , calledQuiescentSignalAnalysisor QSA,usesa setof IDDQ measurements instead,eachobtainedfrom the individual supply pins of the Device-Under -Test (DUT). The processandtechnologycalibrationprocedureusedin QSA is basedon a regressionanalysisproceduresimilar to TSA. In TSA, we referredto signalvariationresultingfrom defectsasregional variation,to contrastit with the global variations introducedby processand technology-related effects. For transientsignals,the supply rail’s impedance network modifiessignalcharacteristics, suchasphaseand magnitude,atdifferentsupplypin testpoints.In QSA,only the resisti ve componentof the supply rail network introducesvariationin theIDDQ valuesat differentsupplypins. In eithercase,the positionof the defectin the layout with respectto any given power supply pin is related to the amountof regional “defect” variationobservedat thatpin. For QSA, the variationis directly relatedto the resistance betweenthe defectsite andthe pin. For example,a larger value of IDDQ is expectedon supply pins closer to the defectsitebecauseof thesmallerR. Therefore,themultiple IDDQ measurements canbeusedto detectthedefectaswell as “triangulate” the physical position of the defect in the layout. Defectdetectionexperimentsareon-goingandwill be addressedin a future work. In this work, a diagnostic method for QSA is developed and a set of simulation resultsarepresentedto demonstrateits defectlocalization accuracy. A characterizationprocedureis proposedthatcan be performed beforehand to determine the mapping betweenresistanceanddistancein the layout. Our results show thatthe(x,y) predictiongivenby themethodis within 10% of the actualdefect location. This suggeststhat the techniqueis bestusedin combinationwith fault dictionary techniquesas a meansof further resolving the defect’ s location. This paper is organized as follows. Section 2.0 describesrelatedwork. Section3.0presentstheexperimental design.Section4.0 describesthe method.Section5. 0 presentsthe resultsof experiments.Section6.0 discusses Quiescent Signal Analysis for IC Diagnosis James F . Plusquellic, Chintan P atel and Ying Ouyang Department of Computer Science & Electrical Engineering University of Maryland Baltimore County the regressionanalysistechniquethat canbe usedto calibratefor processvariation effects.Section7. 0 provides a summary and conclusions. 2.0 Background Severaldiagnosticmethodshavebeendevelopedbased on IDDQ measurements. In general,thesemethodsproduce a list of candidatefaultsfrom a setof observed testerfailuresusinga fault dictionary. The likelihoodof eachcandidate fault can be determined by several statistical algorithms.For example,signatureanalysisusestheDempster-Shafertheory, which is basedon Bayesianstatisticsof subjecti ve probability [9]. Delta IDDQ makesuse of the conceptsof differentialcurrentprobabilisticsignaturesand maximum likelihood estimation [10]. Although these methodsaredesignedto improve theselectionof fault candidates,in many cases,they arenot ableto generatea single candidate.Other difficulties of thesemethodsinclude the effort involved in building the fault dictionaryandthe time required to generatethe fault candidatesfrom the large fault dictionary using device tester data. The QSA procedureproposedhere can help in the selectionof the most likely candidatefrom the candidate list producedby these algorithms. The physical layout information generatedby our method can be used with information that mapsthe logical faults in the candidate lists to devicesin thelayout.In addition,it maybepossible to usethe(x,y) locationinformationprovidedby QSA asa meansof reducingthesearchspacefor likely candidatesin theoriginal fault dictionaryprocedure.This canreducethe processing time and space requirements significantly . 3.0 Experimental Design QSA experimentswere conductedon a full-custom designof an8-bit 2’s complementmultiplier. A block diagram of this device is shown in Figure 1. The primary inputs, labeledA[0] throughA[7] and B[0] throughB[7] areshown alongthetop andright of thefigure.Only tenof theprimaryoutputsarewired to thepadframe(andobservableat thepackagepinsof thedevice.)Thepower supplies for the core logic are labeledasVDD1 throughVDD8 and aredistributedevenly alongtheperipheryof thecorelogic. Thecorelogic consistsof a rectangulararrayof AND gates andfull adders,shown assquaresin thecenterof thefigure. Bridging andopendefectswereinsertedinto thesecellsat the approximatelocationsshown by the Xs in the figure. TheSPACE extractiontool wasusedto generateRC models from the layout [11]. Two methodsareusedto measurethe individual IDDQ valuesat the supply padsshown in Figure 1. In a SPICE simulationenvironment,the most straightforward method is to use the VDD branch currentsof the ideal sources directly. For productiontest,this correspondsto usingthe testerelectronicsat wafer probeto monitor a setof power suppliesthat drive eachof the VDD pads.It is recognized that this may not be possibledue to testerlimitations on available power supply channels.Therefore, a second methodbasedon voltage measurementsis proposed.At waferprobe,it is possibleto measurethecurrentasa voltagedrop by insertingseriesresistorsbetweenthe supply padsand the supply ring on the probecard,as shown in Figure2. Thevalueof theseriesresistance(50Ohmsin our experiments)dependson the“average”steady-statecurrent drawn by devices in the process.It may be necessaryto “switch out” the resistorsto prevent excessi ve supply rail voltage drops, when the DUT is switched between states. 4.0 Experimental Method In this section,we describethe QSA techniqueused for localizing shortingdefects.Sincethe simulationswere carriedout on circuit modelsderived from a 2.0umnwell technology, backgroundcurrentwere very small (~30nA) and,therefore,arenotaccountedfor directly in thissection. However, Section6.0 describesseveral extensionsof the Figure 1. The layout of the 8-bit multiplier. GND VDD1 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]