Virtual Test Automation Generator ( VTAG )

For many years electronic design and test communities were disconnected entities. This paper presents a process that links design with test during the design phase. The process utilizes an automatic control system strategy to automate the design of test patterns for diagnostics. A basic control system includes a controller, plant and sensors. The target for this controller is the weighted sum of percent detection and the number of isolated faults. The components of the control system include a timed test proposer, Genetic Algorithm (test generator) and an unsupervised neural network called Fuzzy Adaptive Resonance Theory (FuzzyART) used as a “Virtual Sensor”. The system being evaluated is simulated using design software (i.e., Verilog HDL or VHDL digital and SPICE analog). The paper will describe the architecture of the control system and will address details of the selection algorithms for the Genetic Algorithm. The paper will also describe the FuzzyART, why it was used and some key advantages. Finally, the paper includes some results obtained for three different circuits (two digital and one analog) evaluated with this process. Background This paper describes a system that was envisioned to help couple the design and test efforts during the development of electronic systems. Test and diagnostic capability is typically developed after the design is complete, often by a different organization. In most cases, diagnosis of the Unit Under Test (UUT) is extremely difficult because the optimal test sites are not available at the edge connector. Developing the test and diagnostics during the design cycle could significantly improve diagnostic accuracy (reduce false pulls), reduce test time and considerably reduce costs both in development and maintenance. The intent is to increase the availability of the system in the field while reducing life-cycle costs. In the past, the method of generating a test program with its associated diagnostics relied on the use of a fault simulator by a test engineer. The engineer used the fault simulator to model the circuit and manually add test patterns to a sequence called the input pattern set (IPS). During the design of the IPS, the engineer used a fault simulator recursively try new patterns appended to the previous patterns. The fault simulator assessed the fault coverage based on detection and a statistical evaluation of occurrence to interpret isolation. Ultimately, the fault simulator provides, when the test engineer is complete, a portion of the Test Program Set (TPS), which includes the IPS, the diagnostic information (fault dictionary), and some of the control software for the Automatic Test Equipment (ATE). This method currently requires a significant amount of a test engineer's time for a UUT of moderate complexity. Obviously, the TPS is not presently developed during the design phase of the system due to time manpower, and cost constraints. The software required for fault simulation is not the same as that required for design and it is costly. If the designer builds the fault dictionary and test sequence during the design phase, improvements to fault detection and isolation can be made by literally designing the test points that will be provided as output pins at the edge connector. Presently, the designer makes an “educated guess” as to which internal states require access at the edge connector based on a priori knowledge of the circuits and systems. For design engineers to become involved with test engineering, the process that generates test sequences must be automated, reliable and predictable. The automated tools which synthesize the tests must use available standard design simulation languages (e.g., Verilog HDL and VHDL for digital circuits). The last crucial requirement is that the time to build a good test must be reasonable and fit within the current design cycle. System Identification-Intelligent Control The desire is to treat the circuit as a black box (see Figure 1) considering only input and outputs obtained at the edge connectors. This is how tests are implemented by ATE, and this is also how the interpretation of the results is accomplished. A test sequence must be generated and supplied to the UUT. Once this is accomplished, the output must be evaluated to identify the actual system. System Identification techniques apply this same philosophy. The basic objective of system identification is to form a mathematical equivalent to an unknown physical system. There are four requirements for System Identification to occur. They are: define the general physical properties of the internal structures, sufficiently excite those internal structures, measure the response with proper sensors, and provide adjustments to the equivalent system (model) to match performance. One can imagine a set of springs coupled together as in Figure 1. The object of this experiment would be to find an input or set of inputs that would cause each spring to vibrate at its natural frequency which would allow for reconstruction of the spring constants by exciting each spring at their own resonant frequency. Ultimately, the equivalent system would develop over time so that each spring would be clearly identified. F ( t ) x ( t ) s e n s o r (a c c) y ( t ) K 1 1 K 1 2 K 1 3 K 1 4 K 2 1 K 2 2 K 2 3 K 2 4 0 2 4 0 5 1 12 23 34 45 K11 K12 K14