Hardware Generation Languages as a Foundation for Credible, Reproducible, and Productive Research Methodologies

Cycle-approximate simulators (CAS) have long been a staple in the experimental toolkit of computer architecture researchers. However, recent technology trends have triggered a growing emphasis on specialization and heterogeneity, bringing into question the viability of a purely CAS-based methodology. In this position paper, we argue computer architects should consider adopting an increased focus on synthesizable hardware description languages (HDL) to improve credibility and reproducibility. Additionally, we discuss the need for hardware generation languages and integrated frameworks to improve researcher productivity and close the gap between current CAS and HDL methodologies. 1. A Tale of Two Research Methodologies Modern computer architecture research has increasingly relied on the use of cycle-approximate simulators (CAS) as the primary tool for evaluating novel architectural mechanisms. We characterize a CAS methodology as the use of a computer architecture simulation framework implemented in C or C++ (e.g., GEM5 [3], SimpleScalar [1]), configured and/or modified to model a particular system architecture and any enhancements. Models built using a CAS methodology are capable of generating fairly accurate estimates of system performance (in terms of cycles executed) provided that the simulated models properly implement a sufficient level of architectural detail [4]. Additional tools like McPAT [8] can augment these frameworks to generate preliminary estimates for other key metrics such as area, energy, and timing. The architecture community has generally considered the benefits (e.g., flexibility, simulation speed) of CAS frameworks to outweigh the drawbacks (e.g., accuracy, reproducibility), making them a popular choice among academic research groups. An alternative methodology for computer architecture research relies on the construction of synthesizable register-transfer-level implementations using a hardware description language (HDL) such as SystemVerilog, Verilog, or VHDL. Paired with a commercial ASIC EDA toolflow, a synthesizable implementation can generate highly accurate estimates of area, energy, cycle time, and cycles executed. Unlike the approximate models of hardware behavior created using a CAS methodology, an HDL methodology constructs a true hardware implementation which provides a number of advantages beyond just improved accuracy. An HDL methodology increases credibility with industry, enforces a model/simulator separation which enhances reproducibility, provides interoperability with a range of industry-grade tools, and enables a path to FPGA or ASIC prototypes. Although widely used by industry and VLSI research groups, the HDL methodology is less popular in computer architecture research due to long HDL development times and slow HDL simulation speeds. Attempts to leverage both CAS and HDL methodologies can be a challenging prospect due to the considerable gap between the tools and techniques used in each domain. For academic research groups lacking the resources and manpower of an industrial research lab, bridging this gap can be exceedingly difficult.