An Evaluation of Snoop-Based Cache Coherence Protocols

A common design for multiprocessor systems is to have a small or moderate number of processors each with symmetric access to a global main memory. Such systems are known as Symmetric Multiprocessors, or SMPs. All of the processors are connected to each other as well as to main memory through the same interconnect, usually a shared bus. In such a system, when a certain memory location is read, we expect that the value returned is the latest value written to that location. This property is definitely maintained in a uniprocessor system. However, in an SMP, where each processor has its own cache, special steps have to be taken to ensure that this is true. For example, consider the situation where two different processors, A and B, are reading from the same location in memory, and therefore, both processors have a copy of that data in their respective cache. As long as both processors are just reading the data, everything should be fine. However, if processor A wishes to write to that location, processor B needs to somehow be aware of that write; otherwise, the next time processor B reads from that location, it could read stale data. Therefore, in SMPs where each processor has its own cache, there is a need to keep the caches coherent. Mechanisms for keeping caches coherent in a multiprocessor system are known as cache coherence protocols. One solution to the cache coherence problem is to allow processors to be able to observe, or snoop, the reads and writes of other processors when necessary. Solutions that employ such a mechanism are known as snoop-based cache coherence protocols. These protocols can only be used in systems where multiple processors are connected via a shared bus. Therefore, snoop-based cache coherence protocols are ideal candidates for solutions to the cache coherence problem in SMPs. Despite solving the cache coherence problem, snoop-based cache coherence protocols can adversely affect performance in multiprocessor systems. For example, in uniprocessor systems, when a store is issued to a location that is present in the cache, in general, the write can proceed without any delays. However, in multiprocessor systems, even though the block may be present in the processor’s cache, it may need to broadcast the write on the bus so that other processors can snoop the write and take appropriate action, which can significantly hurt performance. Therefore, the best snoopbased cache coherence protocol is one that not only maintains coherence, but does so with minimal performance degradation. In the following sections, we will first describe some of the existing snoop-based cache coherence protocols, explain their deficiencies, and discuss solutions and optimizations that have been proposed to improve the performance of these protocols. Next, we will discuss the hardware implementation considerations associated with snoop-based cache coherence protocols. We will highlight the differences among implementations of the same coherence protocol, as well as differences required across different coherence protocols. Lastly, we will evaluate the performance of several different cache coherence protocols using real parallel applications run on a multiprocessor simulation model.