TOP-DOWN VS . BOTTOM-UP NEUROCOMPUTER DESIGN

Artificial neural networks are a form of connectionist architecture where many simple computational nodes are connected in a fashion similar to that of biological brains for the purpose of solving problems that require rapid adaptation or where underlying governing equations are not known or cannot be easily computed. This paper first discusses the use of various computer platforms for neurocomputer implementation. Two designs are then presented: (1) An artificial dendritic tree “bottom-up” VLSI chip; and (2) A vectorregister microprocessor “top-down” design with on-chip learning and a fullyparallel, entirely-digital implementation. INTRODUCTION A discussion of machine intelligence types is a good place to begin a neurocomputer design process. Machine intelligence includes both “symbolic” AI and artificial neural networks. Symbolic AI programs use heuristics, inference, hypothesis testing, and forms of knowledge representation to solve problems. This includes “Expert Systems” and programming languages such as Prolog or LISP, with knowledge contained in logic, algorithms, and data structures. A neural network (NN) is a form of connectionist computer architecture (hardware or software) where many simple computational nodes are connected in an architecture similar to that of a biological brain. Neurocomputers implement NN’s [1]-[3], [5]-[9]. A first step in designing a neurocomputer is choosing an architecture that is either structurally similar to, or merely produces results in a similar fashion to the human brain (i.e., “bottom-up” vs. “top-down” design). Most NN’s are top-down The designs trained to react to external stimuli. They learn via iterative mathematics to change inter-neuron connection strengths (weights) until outputs converge to desired tolerances. The NN learns such that multiple input/desired-output pairs are satisfied simultaneously; the final set of weights represents compromises made to satisfy the constraints. Once trained, the NN can react to new stimuli (i.e., other than the training-set). An implementation problem to consider is that the matrix and vector calculations common to most NN’s are often run on von Neumann uniprocessor machines with a “bottle-neck” forcing non-parallel computation. SMP (Symmetric MultiProcessing) architectures improve performance; however the best machines for these calculations are MPP (Massively Parallel Processing) or vector-register supercomputers; or embedded, application-specific, highly parallel systems – especially those providing learning in real-time. An all-digital vector-register NN processor (with on-chip learning) is presented below. bottom-up Predictions of when computer performance will reach that of the human brain often employ Moore’s Law to predict computing speed or number of transistors per chip: approach is to build a system which functions like a biological brain at the circuit-level. The artificial dendritic tree hybrid-analog/digital chip presented below is an example of this [6], [7]. ( ) Q Q NEW OLD n =    2 1 5 . ( 1 ) where Qold is today’s computing speed (or chip density), and Qnew is computing speed (or chip density) n years in the future (i.e., speed and chip density double every 18 months).