A Design Technique Based on Pole-zero Placements for Fast Settling , Low Power Operational Amplifier

This paper presents a new design technique for three-stage CMOS Operational Amplifier (opamp) with Nested Miller Compensation (NMC) scheme. This design technique is suitable for power optimization with fast settling. In this paper the characteristic of on-chip opamp (i.e. load is capacitive and known in advance) is exploited to obtain the best power and settling performance. NMC scheme has been improved for power optimization after carrying out analysis of power requirement for pole-zero placements. In the proposed design technique compensation resistance (Rc) is used to place poles and zeros at appropriate location so power can be optimized with minimum settling time. NMC capacitor sizing methods are found out on basis of appropriate placements of poles and zeros. In order to achieve required settling performance and optimum power consumption combination of ratio of transconductances of all three stages and ratio of load capacitor to compensation capacitors have been established. Validity of the proposed design technique has been checked by simulation using Tanner tool in 0.35 m μ CMOS technology. Simulation results obtained are Slew rate (SR) = 5.76 V/μs, Unity-gain frequency = 8 MHz, Phase margin = 64° and DC gain = 120 db. ” Is required to be modify as “Simulation results obtained are Slew rate (SR) = 5.76 V/μs, Unity-gain frequency (fu) = 8 MHz, Phase margin = 64° and DC gain = 120 db. 282 Uday Bhanu Singh Chandrawat and D.K. Mishra Introduction In modern low voltage CMOS technology, it is a major challenge to design low power fast settling opamps. Due to large headroom requirement gain enhancement techniques like cascade or telescopic is not suitable for low voltage applications. So multistage amplifiers are used in low voltage applications. The most challenging part in the multistage opamp designing is the frequency compensation. NMC and reversed nested miller compensation are two compensation techniques used in three-stage opamp. Multipath nested miller compensation structure was proposed by eschauzier [1]. This structure is suitable for bipolar transistors because of its high transconductance requirement. NMC method was improved in [2] by using feed forward transconductance stage and nulling resistor. A novel opamp design technique using NMC is presented in [3] and the use of nulling resistors to remove the right hand plane zeros was discussed. NMC methods presented in [1][3] have considered the compensation capacitor sizing criterion based on achieving the third order butterworth response from the opamp in unity-feedback configuration. Damping factor oriented compensation capacitor sizing rules were developed in [4]. These rules are useful to design the opamp with fast settling and low power. Design procedure for three stage opamp with NMC, suitable for pencil-and-paper design was given in [5] [6]. These procedures have not given much consideration to settling time parameter. Effect of load capacitor on design parameters is also not considered. Little work has been reported in literature [7] [8] for settling time analysis of multistage opamp. Pugliese [8] has developed a design procedure for three stage NMC amplifiers with a feature of fast settling and low power. An accurate analysis of Dynamic Settling Error (DSE) ( ( ) dyn t ξ ) is presented by Marques [7]. Work done in [7] has been extended in this paper to develop the new criterion for deciding the size of the compensation elements (capacitors and resistor). Power constraint is taken under consideration to decide the size of the compensation elements and values of transconductances for achieving minimum settling time. DSE parameters for three stage opamp In this section, accurate relationships between circuit parameters (transconductances of different stages, compensation capacitors and load capacitor) and DSE ( ( ) dyn t ξ ) parameters have been established. Parameters (damping factor, damping frequency and natural frequency of oscillation) of quasi-linear period of the settling time can be derived from the small signal model of the three-stage opamp with NMC. Block diagram and small signal model for three stage CMOS opamp with NMC are shown in figure 1 and figure 2 respectively [2][3]. A Design Technique based on Pole-zero Placements 283 Figure 1: Block diagram of three-stamge opamp with NMC. Figure 2: Small signal model for three-stage CMOS spamp with NMC. Here gm1, gm2 and gm3 are transconductances and ro1 , ro2 and ro3 are output resistances of the first, second and third stages of opamp. Rc, Cc1 and Cc2 are the compensation resistance and capacitors respectively. Co1 and Co2 are the parasitic capacitors at first and second stage respectively and CL is load capacitor. Figure 1 shows that Cc1 and Cc2 are connected across the gain stages, due to the miller effect, miller equivelent values of Cc1 and Cc2 will be in parallel to the Co1and Co2. Hence Co1 and Co2 can be neglected because of their low values as compared to miller equivalent of Cc1 and Cc2 . Transfer function of three stage opamp shown in figure 2 can be expressed as: