Miracle-dz/UniFAR-FTUs huggingface dataset:
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs

Making embedded memory symmetric provides the capability of memory access in both rows and columns, which brings new opportunities of significant energy and time savings if only a portion of data in the words need to be accessed. This work investigates the use of ferroelectric field-effect transistors (FeFETs), an emerging nonvolatile, low-power, deeply-scalable, CMOS-compatible transistor technology, and proposes a new 3transistor/cell symmetric nonvolatile memory (SymNVM). With $\sim 1.67\mathrm{x}$ higher density as compared with the prior FeFET design, significant benefits of energy and latency improvement have been achieved, as evaluated and discussed in depth in this paper.
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis

3D convolutional neural networks (CNN) are gaining popularity in action/activity analysis. Compared to 2D convolutions that share the filters in 2D spatial domain, 3D convolutions further reuse filters in the temporal dimension to capture time-domain features. Prior works on specialized 3D-CNN accelerators employ additional on-chip memories and multi-cluster architecture to reuse data among the process element (PE) arrays, which is too expensive for low-power chips. Instead of harvesting in-memory locality, we propose a 3D systolic cube architecture to exploit the spatial-and-temporal localities of 3D CNNs, which moves the reusable data in-between PEs connected via a 3D-cube Network-on-Chip. Evaluation shows that systolic-cube contributes to considerable energy-efficiency boost for activity-recognition benchmarks.
Multifaceted Stoichiometry Control of Bacterial Operons Revealed by Deep Proteome Quantification

More than half of the protein-coding genes in bacteria are organized in polycistronic operons composed of two or more genes. It remains under debate whether the operon organization maintains the stoichiometric expression of the genes within an operon. In this study, we performed a label-free data-independent acquisition hyper reaction monitoring mass-spectrometry (HRM-MS) experiment to quantify the Escherichia coli proteome in exponential phase and quantified 93.6% of the cytosolic proteins, covering 67.9% and 56.0% of the translating polycistronic operons in BW25113 and MG1655 strains, respectively. We found that the translational regulation contributes largely to the proteome complexity: the shorter operons tend to be more tightly controlled for stoichiometry than longer operons; the operons which mainly code for complexes is more tightly controlled for stoichiometry than the operons which mainly code for metabolic pathways. The gene interval (distance between adjacent genes in one operon) may serve as a regulatory factor for stoichiometry. The catalytic efficiency might be a driving force for differential expression of enzymes encoded in one operon. These results illustrated the multifaceted nature of the operon regulation: the operon unified transcriptional level and gene-specific translational level. This multi-level regulation benefits the host by optimizing the efficiency of the productivity of metabolic pathways and maintenance of different types of protein complexes.
Somatostatin‐receptor Scintigraphy in Gastroenteropancreatic Tumors

Somatostatin has been demonstrated in high concentrations in the hypothalamus, the cerebral cortex, the brain stem, the gastrointestinal tract, and the pancreas. In the central nervous system, it acts as a neurotransmitter, whereas its hormonal activities include the inhibition of the release of growth hormone, insulin, glucagon, and gastrin (for a review, see ref. 1). Also, antiproliferative effects have been reported, both in vitro on tumor cell lines, and in vivo on neuroendocrine human tumors. High-affinity somatostatin receptors have been identified in the brain and on many cells of neuroendocrine origin, like the somatotroph cells of the anterior pituitary and the pancreatic islet cell^. ^. ^ Also, cells not known classically as neuroendocrine, such as lymphocytes, may possess these receptor^. ^ Besides, somatostatin receptors have been demonstrated on a variety of human tumors by classical biochemical binding techniques, as well as by in vitro autoradiography. These tumors include those with APUD (amine precursor uptake and decarboxylation) characteristics (pituitary tumors, endocrine pancreatic tumors, carcinoids, paragangliomas, small cell lung cancers, medullary thyroid carcinomas, pheochromocytomas} as well as meningiomas, well-differentiated brain tumors (astrocytomas), neuroblastomas, and some human breast cancers. Because of the short plasma half-life of somatostatin (2-4 min), analogues more suitable for medical treatment have been developed. The somatostatin analogue, octreotide, has been shown to bind to somatostatin receptors on both tumorous and nontumorous tissues. An "'In-labeled somatostatin analogue ([DTPA-D-Phe'l-octreotide] was developed for its use in scintigraphy. [DTPA-D-Phe'l-octreotide was shown to bind "'In efficiently in a single-step labeling procedure. The binding as well as the biological
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization

Customizing embedded computing platforms to specific application domains often necessitates optimizing the firmware and/or the HW/SW interface under tight resource constraints. Such optimizations frequently alter the communication between the firmware and the peripheral devices, possibly compromising functional correctness of the input/output behavior of the embedded system. This paper proposes a formal HW/SW co-equivalence checking technique for verifying correct I/O behavior of peripherals under a modified firmware. We demonstrate the great promise of our approach on RTL implementations of several open-source peripherals. In our experiments we successfully prove or disprove correctness of firmware optimizations for an industrial driver software. In addition, we also found a subtle bug in one of the peripherals and several undocumented preconditions for correct device behavior.
Magma: A Monolithic 3D Vertical Heterogeneous Reram-Based Main Memory Architecture

3D vertical ReRAM (3DV-ReRAM) emerges as one of the most promising alternatives to DRAM due to its good scalability beyond $10 nm$. Monolithic 3D (M3D) integration enables 3DV-ReRAM to improve its array area efficiency by stacking peripheral circuits underneath an array. A 3DV-ReRAM array has to be large enough to fully cover the peripheral circuits, but such large array size significantly increases its access latency. In this paper, we propose Magma, a M3D stacked heterogeneous ReRAM array architecture, for future main memory systems by stacking a large unipolar 3DVReRAM array on the top of a small bipolar 3DV-ReRAM array and peripheral circuits shared by two arrays. We further architect the small bipolar array as a direct-mapped cache for the main memory system. Compared to homogeneous ReRAMs, on average, Magma improves the system performance by 11.4%, reduces the system energy by 24.3% and obtains $>5-$year lifetime.CCS Concepts• Hardware $\rightarrow 3\mathrm {D}$ integrated circuits; Memory & storage;ACM Reference Format:Farzaneh Zokaee, Mingzhe Zhang, Xiaochun Ye, Dongrui Fan, and Lei Jiang. 2019. Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture. In The 56th Annual Design Automation Conference2019 (DAC '19), June 2–6, 2019, Las Vegas, NV, USA. ACM, New York, NY, USA, 6 pages. https://doi.org/10.1145/3316781.3317858
L-MPC: A LUT based MuIti-LeveI Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network

A binary-weight hourglass network (B-HG) accelerator for landmark detection, built on the proposed look-up-table (LUT) based multi-level prediction-correction approach, is enabled for high-speed and energy-efficient processing on IoT edge devices. First, LUT with a unified mode is adopted to support convolutional neural network with fully variable weight bit precision to minimize operations of B-HG, which achieves $1.33\times-1.50\times$ speedup on multi-bit weight CNN relative to the similar solution. Second, multi-level prediction-correction model is proposed to achieve computational-efficient convolution with adaptive precision. The operations saved can be increase by about 30% than the two-stage model. Besides, nearly 77.4% of the operations in B-HG can be saved by using the combination of these two methods, yielding a 2.3× inference speedup. Third, block computing based pipeline is designed to improve the residual block deficiency in B-HG. It can not only reduce about 66.2% off-chip memory access than the baseline, but also save 60% and 31% on-chip memory space and access compared to the similar fused-layer accelerator. The proposed B-HG accelerator achieves 450 fps at 500MHz based on the simulation in TSMC 28 nm process. Meanwhile, the power efficiency is up to 8.5 TOPS/W, which is two orders of magnitude higher than the dedicated face landmark detection accelerator.
Reliability-Driven System-Level Synthesis of Embedded Systems

This paper proposes an enhanced system-level synthesis flow for the design of reliable embedded systems, extending the classical process to introduce fault mitigation properties in the design under consideration. The strategy first explores the adoption of hardening techniques that, given the initial task graph and the user's reliability requirements, introduce redundancies and mapping constraints on the available resources, which possibly expose fault detection/tolerance features. The reliability-aware task graph is then implemented by means of a classical mapping and scheduling approach thus obtaining the hardened implementation. Experimental results are reported to support the validity of the proposal.
Attending to Email

Email has become deeply embedded in many users’ daily lives. To investigate how email features in users lives, particularly how users attend to email, we ran a 2-week study that logged interactions with email and gathered diary entries related to individual sessions. Our study showed that the majority of attentional effort is around reading email and participating in conversations, as opposed to email management (deleting, moving, ﬂagging emails). We found that participants attended to email primarily based on notiﬁcations, instead of the number of unread messages in their inbox. We present our results through answering several questions, and leverage conversation analysis, particularly conversational openings, to explicate several issues. Our ﬁndings point to inefﬁciencies in email as a communication medium, mainly, around how summons are (or are not) issued. This results in an increased burden on email users to maintain engagement and determine (or construct) the appropriate moment for interruption.
A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC Circuits

The integration of more components into modern Systems-on-Chip (SoCs) has led to very large RLC parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.
Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading

Existing studies have uncovered that there exist significant Raw Bit Error Rates (RBERs) variations among different layers of 3D flash memories due to manufacture process variation. These RBER variations would cause significantly diversed read latencies when reading data with traditional Low-Density Parity-Check (LDPC) codes designed for planar flash memories, which induces sub-optimal read performance of flash-based Solid-State Drives (SSDs). To investigate the latency diversity, this paper first performs a preliminary experiment and observes that LDPC read levels proportional to latencies increase in diverse speeds along with data retention. Then, by exploiting the observation results, a Multi-Granularity LDPC (MG-LDPC) read method is proposed to adapt level increase speed for each layer. Five LDPC engines with varied increase granularity are designed to adapt RBER speed requirements. Finally, two implementations for MG-LDPC are applied to assign LDPC engines for each flash layer in a fixed way or dynamically according to prior read levels. Experimental results show that the proposed two implementations can reduce SSD read response time by 21% and 47% on average, respectively.CCS CONCEPTS• Hardware→Temperature optimization; Network on chip; 3D integrated circuits.
A Base Camp for Scaling

Modern statistical machine learning (SML) methods share a major limitation with the early approaches to AI: there is no scalable way to adapt them to new domains. Human learning solves this in part by leveraging a rich, shared, updateable world model. Such scalability requires modularity: updating part of the world model should not impact unrelated parts. We have argued that such modularity will require both “correctability” (so that errors can be corrected without introducing new errors) and “interpretability” (so that we can understand what components need correcting). To achieve this, one could attempt to adapt state of the art SML systems to be interpretable and correctable; or one could see how far the simplest possible interpretable, correctable learning methods can take us, and try to control the limitations of SML methods by applying them only where needed. Here we focus on the latter approach and we investigate two main ideas: “Teacher Assisted Learning”, which leverages crowd sourcing to learn language; and “Factored Dialog Learning”, which factors the process of application development into roles where the language competencies needed are isolated, enabling non-experts to quickly create new applications. We test these ideas in an “Automated Personal Assistant” (APA) setting, with two scenarios: that of detecting user intent from a user-APA dialog; and that of creating a class of event reminder applications, where a non-expert “teacher” can then create specific apps. For the intent detection task, we use a dataset of a thousand labeled utterances from user dialogs with Cortana, and we show that our approach matches state of the art SML methods, but in addition provides full transparency: the whole (editable) model can be summarized on one human-readable page. For the reminder app task, we ran small user studies to verify the efficacy of the approach. ∗Currently at Carnegie Mellon University. This work was done while Yang was an intern at MSR. 1 ar X iv :1 61 2. 07 89 6v 1 [ cs . A I] 2 3 D ec 2 01 6 A Base Camp for Scaling AI
Fabrication of nanopore arrays and ultrathin silicon nitride membranes by block-copolymer-assisted lithography

Here we show a method for patterning a thin metal film using self-assembled block-copolymer micelles monolayers as a template. The obtained metallic mask is transferred by reactive ion etching in silicon oxide, silicon and silicon nitride substrates, thus fabricating arrays of hexagonally packed nanopores with tunable diameters, interspacing and aspect ratios. This technology is compatible with integration into a standard microtechnology sequence for wafer-scale fabrication of ultrathin silicon nitride nanoporous membranes with 80 nm mean pore diameter.
Fast Performance Estimation and Design Space Exploration of Manycore-based Neural Processors

In the design of a neural processor, a cycle-accurate simulator is usually built to estimate the performance before hardware implementation. Since using the simulator to perform design space exploration (DSE) of hardware architecture is quite time consuming, we propose a novel method to use a high-level analytical model for fast DSE. In the model, non-deterministic execution delay is modeled with some parameters whose contribution to the performance is estimated statically by simulation. The viability of the proposed methodology is confirmed with two neural processors with different manycore architectures, achieving 2000 times speed-up within 3% accuracy error, compared with simulator-based DSE. CCS CONCEPTS •Computer systems organization → Multicore architectures;
LRPPRC: A Multifunctional Protein Involved in Energy Metabolism and Human Disease

The pentatricopeptide repeat (PPR) family plays a major role in RNA stability, regulation, processing, splicing, translation, and editing. Leucine-rich PPR-motif-containing protein (LRPPRC), a member of the PPR family, is a known gene mutation that causes Leigh syndrome French–Canadian. Recently, growing evidence has pointed out that LRPPRC dysregulation is related to various diseases ranging from tumors to viral infections. This review presents available published data on the LRPPRC protein function and its role in tumors and other diseases. As a multi-functional protein, LRPPRC regulates a myriad of biological processes, including energy metabolism and maturation and the export of nuclear mRNA. Overexpression of LRPPRC has been observed in various human tumors and is associated with poor prognosis. Downregulation of LRPPRC inhibits growth and invasion, induces apoptosis, and overcomes drug resistance in tumor cells. In addition, LRPPRC plays a potential role in Parkinson's disease, neurofibromatosis 1, viral infections, and venous thromboembolism. Further investigating these new functions of LRPPRC should provide novel opportunities for a better understanding of its pathological role in diseases from tumors to viral infections and as a potential biomarker and molecular target for disease treatment.
X-DeepSCA: Cross-Device Deep Learning Side Channel Attack*

This article, for the first time, demonstrates Cross-device Deep Learning Side-Channel Attack (X-DeepSCA), achieving an accuracy of > 99.9%, even in presence of significantly higher inter-device variations compared to the inter-key variations. Augmenting traces captured from multiple devices for training and with proper choice of hyper-parameters, the proposed 256-class Deep Neural Network (DNN) learns accurately from the power side-channel leakage of an AES-128 target encryption engine, and an N-trace (N ≤ 10) X-DeepSCA attack breaks different target devices within seconds compared to a few minutes for a correlational power analysis (CPA) attack, thereby increasing the threat surface for embedded devices significantly. Even for low SNR scenarios, the proposed X-DeepSCA attack achieves ~ 10× lower minimum traces to disclosure (MTD) compared to a traditional CPA. CCS Concepts • Security and privacy $\rightarrow $ Embedded systems security; Side-channel analysis and countermeasures.
Poly[[triaqua[μ4-N-(4-carboxylatophenyl)iminodiacetato]sodium(I)zinc(II)] dihydrate]

In the title coordination polymer, {[NaZn(C11H8NO6)(H2O)3]·2H2O}n, the Zn atom is coordinated in a distorted tetrahedral environment by three carboxylate O atoms from two (4-carboxylatophenylimino)diacetate ligands and one water molecule; the Na atom is in an distorted octahedral coordination environment formed by four carboxylate O atoms from three (4-carboxylatophenylimino)diacetate ligands and two water molecules. The Zn atoms and Na atoms are linked by (4-carboxylatophenylimino)diacetate ligands into a three-dimensional framework; the uncoordinated water molecules fill the voids of the skeleton and stabilize it by O—H⋯O hydrogen bonds.
A Fault-Tolerant Neural Network Architecture

New DNN accelerators based on emerging technologies, such as resistive random access memory (ReRAM), are gaining increasing research attention given their potential of “in-situ” data processing. Unfortunately, device-level physical limitations that are unique to these technologies may cause weight disturbance in memory and thus compromising the performance and stability of DNN accelerators. In this work, we propose a novel fault-tolerant neural network architecture to mitigate the weight disturbance problem without involving expensive retraining. Specifically, we propose a novel collaborative logistic classifier to enhance the DNN stability by redesigning the binary classifiers augmented from both traditional error correction output code (ECOC) and modern DNN training algorithm. We also develop an optimized variable-length “decodefree” scheme to further boost the accuracy under fewer number of classifiers. Experimental results on cutting-edge DNN models and complex datasets show that the proposed fault-tolerant neural network architecture can effectively rectify the accuracy degradation against weight disturbance for DNN accelerators with low cost, thus allowing for its deployment in a variety of mainstream DNNs.
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing *

As clock frequencies increase, topology-matching bus routing is desired to provide an initial routing result which facilitates the following buffer insertion to meet the timing constraints. Our algorithm consists of three main techniques: (1) a bus clustering method to reduce the routing complexity, (2) a DAG-based algorithm to connect a bus in the specific topology, and (3) a rip-up and re-route scheme to alleviate the routing congestion. Experimental results show that our proposed algorithm outperforms all the participating teams of the 2018 CAD Contest at ICCAD, where the top-3 routers result in 145%, 158%, and 420% higher costs than ours.CCS CONCEPTS. Hardware → Electronic design automation;
Rasch‐ionale for neurologists

Outcome measures are considered the most important tools to monitor patients' outcome in both clinical and research settings. Measuring the clinical state of patients is a fundamental part of our daily clinical practice and research that sometimes is taken for granted. In peripheral neuropathies, there are many scales available, but most of these are at the ordinal level. This paper will systematically address the types of scales available (being nominal, ordinal, interval, or ratio data‐based) in terms of their strengths and weaknesses. The differences between classical test theory‐based and modern test method‐based outcome measures will be addressed with emphasis on Rasch methodology. Various steps will be highlighted as part of the evaluation and construction of outcome measures using the Rasch method, with the aim to increase the knowledge and utility of this technique. We argue that Rasch‐built outcome measures should be used for future studies in neuromuscular disorders and their method of construction could be easily extrapolated to other neurological illnesses.