Unified Modeling Abstraction for Fast Simulation and Emulation

With the increasing design size of SoC’s and chip multiprocessors, simulation models are not sufficiently fast to a ccommodate performance evaluation with realistic benchmar ks. Emulating the performance models in programmable hardware (FPGA) is an attractive solution for speeding up performanc e analysis [1], [2], [9], [10], [11]. This poses the following requirements on the design of the performance model: (1) the simulation speed of the original HDL model needs to be high enough to allow fast functional verification and (2) the emulation speed of the design synthesized from this model should be acceptably high to support the simulation of large benchmarks. We briefly review some characteristics of good simulation and emulation models using the SystemC [7] modeling infrastructure and a commercial behavioral synthesis system such as AutoPilot [8]. The requirements of fast simulation models a re often different from those from which efficient hardware can be synthesized. Some typical mechanisms to describe fast SystemC simulation models are: (1) minimise architectural detail – behavi oral models (Figure 3) with algorithmic descriptions are 10x fas ter than those with architectural details (Figure 1); (2) minim ise the number of processes to reduce context switch overhead [3]; and (3) maximise the use of native C++ data types [4]. When the objective is efficient synthesis into hardware, HDL models are optimised along different criteria: (1) A SystemC process is essentially sequential code, and typica l behavioral synthesis algorithms in academia and industry h ave difficulties in automatic parallelisation of behavioral co de into parallel hardware, which results in performance-inefficie nt synthesized hardware. Thus having more number of processes per design, i.e., explicit specification of parallelism by t he programmer, is benefical for generating parallel hardware a nd hence higher emulation speeds. (2) Since the latency of gene rated hardware from a SystemC process is unpredictable befor e synthesis as it depends on factors such as target platform, technology, tool dependent optimizations, etc., the synch ronization between interacting processes needs to be handled explicitly by handshaking signals. Keeping synchronizati on to a minimum produces faster hardware. (3) Using appropriate data widths in the model (i.e., NOT using native C++ data types) results in more efficient hardware both in terms of are a and speed. From the above we observe that the requirements for a good simulation model and that of an efficient synthesis/emulati on model impose contradicting modeling constraints. Hence we need to identify an appropriate abstraction level at which t he simulation model should be described, so that it complies with most of the above guidelines. Such a modeling abstraction where simulation and synthesis models have a common origin, if found efficient, can lead to significant productiv ity improvement in processor and SoC design flows, as it would eliminate the need to manually maintain consistency across the different models, and the associated verification challeng es. Broadly there are two different levels of modeling abstraction that could be suitable for both simulation and synthesi s specification, and we limit our present discussion to these: Architectural Level and Behavioral Level. Levels lower tha n the above, such as RTL, are unsuitable because the detailed clock cycle level accuracy results in very slow simulation. Levels higher than these, such as transaction level, are not sufficiently accurate. TheArchitectural model is described by maintaining highlevel structural details of the hardware through explicit p arallel constructs. Consider an example of modeling an N-stage pipeline in SystemC as shown in Figure 1.