Test and Test Bench Generation by Algorithmic Models

Each circuit may be described at the algorithmic, behavioural or gate levels. Normally the tests are generated separately for each of the levels. We present here a technique of generating test patterns for faults by a simulation of descriptions of the circuits on the algorithmic level. The resultant tests are applicable for VHDL behavioural level as test bench. They give high fault coverage for the equivalent circuit on the gate level. The procedure of selecting the tests is based on the transmission of distorted signals to the outputs. Generation of the input stimuli is performed with respect to the distribution of the inputs. The application of test frames allows the sequential circuits to be treated as combinational ones. 1.Introduction Normally any design of an electronic circuit involves several stages. The first to be born is the idea, which is then checked by compiling an algorithmic model of the circuit. The prototype may be implemented by either a high level programming language, or by a special hardware description language, such as VHDL. An analysis of the prototype needs stimuli of input signals and demonstrates the behaviour of the circuit. This is in most cases the job of the circuit designer. Circuits with numerous inputs can suffer of a large number of input stimuli, and the task of the designer is to select the most important ones as specifications of the behaviour of the circuit under design. This is by no means a simple procedure, as it is never evident, that input stimuli selected reflect all behaviour modifications of the circuit. We recommend even at this early stage an automated generation of input stimuli, to have a possibility of checking the performance of the circuit designed in the presence of unexpected stimuli. In checking an algorithm, the role of Oracle is given to the circuit designer, as he is the one who decides upon a correct response of the algorithms to the given input stimuli. Making a decision demands certain efforts, therefore the designer is eager to have a possibly small number of input stimuli to be evaluated. Hence, it is always important to generate the smallest number of input stimuli for the evaluation of an algorithm. The next stage is to compile a description of the circuit in a language of the synthesis. Here an automated generation of input stimuli is even more important, as the adequacy between the model of the algorithm and the description intended for the synthesis must be checked. It is evident, that here input stimuli intended for the analysis of the model of the algorithm can be applied. The question is: is this sufficient? An adequacy between two descriptions is best proved in a formal approach but here the techniques are not quite reliable, yet. Certain inadequacies can be found by comparing the results of the input stimuli of the algorithmic description and the synthesis description. A dilemma arises here of insuring the sufficiency of the selected input stimuli in the evaluation of the descriptions. After the synthesis of the circuit has been completed, test stimuli should be generated to find the defects in the circuit manufactured. This is one more difficult solution. We face also a number of problems related to the model of the faults, and especially in integrated circuits, such as is it sufficient to use gate level models or switch level ones should be used. In any case test patterns for detecting defects are most efficient, when they have been generated on the lowest level. An assumption can be applied, that test patterns for faults on the gate level can be applied successfully in the analysis of the algorithmic description of the circuit, and in finding discrepancies between algorithmic and synthesis descriptions. The difficulty lies in that we have to perform an analysis of the algorithm, and to prove the adequacy between the algorithm and the synthesis description, before the circuit itself is synthesised . On the other hand, the situation can be exploited to evaluate the adaptability of the input stimuli in the analysis of the circuit algorithm, and in the comparison of the synthesis description with the algorithm as well as for test of the circuit synthesised. One of the modes of generating tests on the behavioural level is to use the models of behavioural faults [ 1 3]. So far, there are no popular fault models for behavioural descriptions that could insure proper testing of physical defects of a circuit. Also, there can be a large number of faults in descriptions on high levels abstraction. Our problem could be stated in the following way: generate test patterns according to a black box description of the circuit. The first thing to be asked is: if there exist any solutions. The algorithm description of the circuit gives no information on its structure, the solution must be based on input stimuli and output responses. We remind here, that each fault in a circuit can be tested by a number of input stimuli and can lead to different output responses. This is the basis of locating circuit faults by the observation of output responses only. The response of a diagnostic test gives suggestions on the type and location of the fault, and challenges the hopes of a possibility of judging about the coverage of internal faults from the test responses of the circuits. The disposition of only the description of the algorithm gives the possibility of operating only on the input faults, so that one more question must be answered: are they sufficient? The only way of finding this answer was the experiment. Therefore we have suggested an algorithm of evaluating the coverage of input stimuli that are generated for detecting inputs faults only[ 5]. We performed the experiment with selected 20 ISCAS85/89 circuits, and found the coverage of input stimuli just several per cent lower than a exhaustive testing of input. The selection evaluated only changes of the values of the inputs, and only responses of the outputs. The coverage of stimuli was evaluated after all internal stuck-at faults in a description at the gate level. The experiment included a generation of certain number of input stimuli, with not necessarily the largest coverage of the circuit by the tests. We present here a technique of generating the tests, based on the circuit description on the algorithmic level. What is the difference between a description on the algorithmic level and a behavioural VHDL description? Algorithmic descriptions are implemented in some high level programming language, say, C. They carry no information either on synchronization or on the initialization of the circuit. The model reflects only the function of the circuit. This paper is organised as follows. In section 2 we present a test generation method based on a transmission model. In section 3 we introduce the techniques for generating test patterns for sequential circuits. In section 4 we show how to use the generated test patterns as test bench. In section 5 we give experimental results. And we conclude in section 6. 2. Generation of Tests for Transmission Faults of Circuits Let us have a model of a circuit in a high level programming language. We treat it as a black box and consider only its inputs and outputs. Let the circuit have a set of inputs X = {x1, x2, . ,xi, . ,xn} and a set of outputs Y = {y1, y2, . ,yj, . ,ym}. We consider a change of the signal of an input xi and write xi ( xi) for a zero-to-one( one-to-zero) change of an input signal. A change of one signal in the input stimulus may lead to changes of several output signal values. Then write yj (yj) for the zeroto-one ( one-to-zero) change of the output yj. Couple (xi, yj) implies , that a zero-toone change of the signal of the input xi leads to a one-to-zero change of the signal of the output yj . There are four modifications of the relation between input xi and output yj: (xi, yj), (xi, yj), (xi, yj), (xi, yj). We treat these couples (xi, yj), where t=0,1 , k=0,1 as models of circuit faults and call them transmission faults. We assume, that the test pattern detects, say, the transmission fault (xi, yj) , if a zero-to-one change of the signal of the input xi of the test pattern leads to a one-to-zero change of the signal of the output yj . Each fault of transmission (xi, yj) is related to real defects of the circuit. No changes occur in a faulty circuit. In a general case, n inputs of a circuit are related to m outputs, and the circuit may have 4 x (n x m) transmission faults. The list of transmission faults may be written as a set: F = { (xi, yj) | i = 1, n ; y = 1, m ; t = 0,1, k=0,1; }, There may be no electric connections between some of the inputs and the outputs, and their transmission faults will not be detected. These faults are undetectable. In this manner the number of generated test patterns will not exceed the number of transmission faults in the circuit. There may be several input-output transmission paths. In the fault model suggested, the paths will be activated by no more than four test patterns. On the first sight, one cannot be sure, that test patterns which detect the suggested model of the faults will cover sufficiently the stuck-at faults at the gate level. The applicability of the procedure to large circuits of long transmissions paths is equally doubtful. But the experimental checking [ 5 ] has proved that the test patterns, by detecting transmission faults, also detect the major part of stuck-at faults at the gate level, including the largest Benchmark circuits. The general strategy of generating the test is: find for each couple (xi, yj) a relevant test pattern. The same test patterns can fit to several couples. The search is performed by a technique of a simulation. We simulate separately for the input stimuli generated all changes, and select the ones causing changes at the outputs as test patterns. Two input stimuli with the opposite signals of one input detect symmetric transmission faults (xi, yj). This feature