Circuit Technologies For A Single-1.8V Flash Memory

Introduction This paper proposes three circuit technologies, a Vpp switch, row decoder and charge pump circuit, to realize a single-1.W Flash memory. Unlike a D W S R A M , a Flash memory requires a voltage as high as 2OV to rewrite data [l]. For low-voltage operation, there are two serious problems which we should overcome; one is highvoltage (Vpp) switching and the other is its generation. Vpp switches composed of only high-voltage nMOSFET’s have been used in Flash memories [2,3]. Unlike CMOS switches with large parasitic capacitance of N-well for pMOSFET’s, this nMOS-only Vpp switch has small junction and wiring capacitance, resulting in a short Vppcharging time and high-speed programming. However, this switch also has disadvantage that the minimum operating Vcc is mainly limited by a threshold voltage of an enhancement transistor which prevents the leakage current from flowing in the Vpp switch during the inactive state (Fig.1). Another serious problem with a single low-voltage Flash memoly is that efficiency of charge pump circuits is drastically degraded with Vcc lowering. Area for charge pump circuits in a single low-voltage Flash memory will drastically increase for a constant Vpp-charging time (Fig.5). Focusing on Vpp switching and generation, this paper describes (1) a Vpp switch composed of only intrinsic high-voltage transistors without channel implantation, which flows no leakage current from Vpp, reduces the maximum voltage applied to the gate of the switchmg transistor and can operate even at a Vcc of 1.W, (2) a row decoder scheme such that all blocks are in selected state in standby, preventing the standby leak from flowing in the Vpp switches used in row decoders, and (3) a merged pump scheme enabling a charge pump circuit to output two voltage levels with an individually optimized efficiency while reducing the circuit area in comparison with the conventional scheme which requires two charge pump circuits for two voltage levels. Vpp Switch Figs.1 and 2 respectively illustrate the conventional [2,3] and proposed Vpp switches. In the conventional switch, an enhancement transistor M1 is used to prevent the leakage current from Vpp when unselected (Sw=L) and an intrinsic transistor without channel implantation M2 is used to improve the positive-feedback efficiency of the booster when selected (Sw=H). The switching operation is as follows. The source voltage Vcap of the M1 is equal to the gate voltage Vg of the M1 minus the threshold voltage Vt(E) of the M1 with the clock Clk high (Vcap=Vg-Vt(E)). After that, the Clk turns to low and the gate voltage of the M1 increases to Vg’=Vcap+Vcc-Vt(I), where Vt(1) is a threshold voltage of an intrinsic transistor. Thus the voltage gain per cycle is Vg’-Vg, i.e., Vcc-Vt(E)-Vt(1). When Vg reaches Vpp+Vt(E) due to this positive feedback, the M5 outputs Vpp. As descrived above, efficiency of the positive feedback for switching depends on Vcc-Vt(E)-Vt(I), so that the mini” operating Vcc is limited by Vt(E)+Vt(I). In case of a Vpp of 1 SV, a Vt(E) of l . W and a Vt(1) of 0.7V at a back bias of 18V, the maximum voltage for the switching gate and the minimum operating Vcc are respectively 19.W and 2.4V. A single-1.8V Flash memory requires further improved feedback efficiency of the booster. Only replacement of the M1 with an intrinsic transistor for efficiency improvement results in unallowable leakage current from internally generated Vpp. In case that this replacement is done in a 64M Flash chip [l], the Vpp leakage current is estimated as an order of 1 0 0 ~ 4 , whch is the same order as an output current of the charge pump circuit. The proposed Vpp switch can use intrinsic transistors for all ones. The M8 and MI5 bias Vcc to the source terminals of the M6 and M13 whose gates are biased to ground when the switch is unselected. As a result, the proposed switching circuit can change the leakage source from Vpp to Vcc. The operation current increases by no more than 10%. When the switch is selected, the operation is the same as the conventional one but the maximum gate voltage can be reduced to Vpp+Vt(I) by Vt(E)-Vt(1) (=1V). The feedback efficiency of the booster is also improved due to the low threshold voltage of the intrinsic M6,7. The transistors to be cut off, M8,10,11,15, are in state such that the gates are grounded and the sources are forced by Vcc. As shown in Fig.3, the minimum operating Vcc can be reduced by 1V compared with the conventional Vpp switch. As a result, the proposed switch operates even at a Vcc of 1.8V. Row Decoder In order to prevent the standby leak from flowing in Vpp switches, most of which are used in row decoders, we developed a scheme such that all blocks are in selected state in standby. In the conventional scheme such that all blocks are in unselected state in standby, the proposed Vpp switches will flow an unallowable standby current of an order of 1OuA. The standby leak path in that case is shown by the arrow in F i g 2 Fig.4 illustrates the new row decoder scheme using the proposed Vpp switch. All blocks are in selected state (PMP=H) independent of a block address (/RAm) in standby (CE=L), resulting in no standby leak. All word-lines WL’s are grounded through global word-lines GWL’s in standby. In active mode (CE=H), blocks are unselected (PMP=L) except for a selected block (/RAm=L). After that, the clock Clk boosts the gates of transfer transistors and connects the WL’s with the GWL’s. Thus, the combination of the proposed Vpp switch and all-block-selection-in-standby scheme makes it possible to eliminate both the standby and Vpp leak. Charge Pump Circuit A single-voltage Flash memory requires some charge pump circuits, one of which outputs 4.5V for read, 1OV for write and 20V for write and erase [l]. Fig3 indicates charge pump circuits will occupy large part of a low-voltage Flash chip unless the read/write/erase voltages are scaled down with Vcc. Fig.6 illustrates a merged pump scheme, which is based on the conventional pump proposed in [4] and enables to output 4.5V in read operation (RE=H) and 1OV in write operation (WE=H) with an individually optimized efficiency. A single fourstage charge pump in write operation is reorganized into two of a twostage charge pump connected in parallel with high efficiency in read operation. Fig.7 shows a measured output waveform of a proposed circuit at a Vcc of 1 . W. Capacitors in the PCl’s occupy most of the circuit area and thus the additional switches PC2’s lead to increase the circuit area by less than 10%. As a result, the proposed pump scheme reduces the area required for charge pump circuits in a Flash chip by 40%, as shown in Fig.5. Conclusion Three circuit technologies using only intrinsic high-voltage transistor without channel implantation have been developed for a low-voltage Flash memory. These technologies will realize a single-1.8V Flash memory eliminating fabrication steps for enhancementand depletionchannel implantation. Acknowledgment The authors wish to thank Drs. J. Miyamoto and K. Sakui for their encouragement. Reference [l] Kim, J. K. , VLSI Cir. Tech. Papers, pp.168-9, 1996. [2] Dahm, V.K. et al., ISSCC Tech. Papers, pp.166-7, 1983. [3] Donaldson, D.D. et al., ISSCC Tech. Papers, pp.168-9, 1983. [4] Umezawa, A. et al., IEEE-JSSC, vo1.27, pp. 1540-6, 1992.