Bitwidth Sensitive Code Generation in a Custom Embedded Accelerator Design System

An ever larger variety of embedded ASICs is being designed and deployed to satisfy an explosively growing demand for new electronic devices. Many of these devices are called upon for computationally demanding processing of multimedia data. In many such ASICs, specialized nonprogrammable hardware accelerators (NPAs) are used for parts of the application that would run too slowly if implemented in software on an embedded programmable processor. Rapid, low-cost design, low production cost, and high performance are all important in these designs. In order to reduce design time and design cost, the HP Labs Program-In-Chip-Out (PICO) project is focused on automating the design of NPAs from high-level specifications. Source code (in a subset of C) for a performance-critical loop nest is used as a behavioral specification of an NPA. The PICO system compiles the source code into a custom hardware design in the form of a parallel, special-purpose processor array. The user, or a design exploration tool, specifies the number of processing elements and their performance. The system produces a VHDL design for the array, its control logic, its interface to memory, and its interface to a host processor. In the multimedia application domain, integer data of various bitwidths is common (e.g., 8-bit and 16-bit data). The bitwidth is defined as the number of bits required to represent the range of possible values in two's complement. The complexity of automatically generated designs is an important issue, and it appears essential to produce cost-effective designs by taking advantage of operations with varying bitwidths. The width of hardware components, including registers, busses, and function units, can be minimized with knowledge of the maximum width of data processed by the component. Earlier research into the use of programmer annotation of and compiler inference of required bitwidths has shown this approach to be worthwhile [1, 2, 3]. In this paper, we investigate the exploitation of integer bitwidth in the code generation system of an NPA compiler. The code generation consists of two major parts. First, a bitwidth analysis phase is used to infer the bitwidth requirements for all program data. We allow users to define the bitwidth of selected variables through declarations in the source code. With this information as the starting point, the bitwidth analysis examines the data dependence structure of the application together with opcode semantics to derive the minimum width required for all program variables. While developed independently, our inference methods are hard to distinguish from those of the earlier efforts cited above. The second part of the NPA code generation system handles the mapping of operations to resources, a problem that has not yet been addressed adequately in the literature. More specifically, this part includes the allocation of hardware resources and scheduling where operations are assigned to those resources. With operations of varying bitwidths, the mapping must be done in a width-cognizant manner to achieve a cost-effective design. Intuitively, operations of similar width should be assigned to common hardware resources, so narrow resources are used for operations with narrow data and wide resources are used for operations with wide data. The goal is to minimize the overall cost of the hardware resources. We employ a technique referred to as width clustering, in which operations with similar bitwidths are grouped into clusters before scheduling. Hardware resources are then allocated separately for each cluster. During scheduling, operations are restricted in their binding to resources from their own cluster. In this manner, the operation binding choices are limited in order to encourage intelligent grouping of operations to resources based on bitwidth information. Operation clustering has traditionally addressed the problem of compiling programs for predefined hardware clusters of function units and register files [4]. In contrast, we use width clusters to intelligently create clustered hardware. The remainder of this paper provides an overview of the PICO NPA design system. Then, a description of the two major components of the code generation system that handle bitwidth specific issues are described. We then give some experimental results to illustrate the extent to which bitwidth annotation of variables and bitwidth inference allows PICO to reduce the cost of the hardware it generates.