Arbitrary Defects; Modeling and Applications Arbitrary Defects; Modeling and Applications

OF THE THESIS Arbitrary Defects; Modeling and Applications by Ankur Jain Thesis Director: Dr. Michael Hsiao Grading the true quality of a test set for arbitrary defects, improvement of accuracy of error and fault diagnosis, Boolean comparison for design veri cation in the presence of unknown or uninterpreted functions and automatic test pattern generation (ATPG) for intellectual property (IP) based designs are important problems in industry. In this thesis, we address all these problems and provide some e cient solutions to them. First, we present e cient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit. We use an abstract model that captures the erroneous behavior of all possible defects in a local region (region-based defect model) at the immediate outputs of the region. The fraction of these erroneous behaviors observed at the primary outputs of the circuit under the given test set is used to estimate the defect coverage of the region. Our defect coverage evaluation techniques rapidly estimate arbitrary defect coverage because they are independent of speci c, physical fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating multiple faults (of all types) simultaneously and by exploiting the local nature of defects. Our experiments show that a strong correlation exists between stuck-at fault coverage and defects whose behavior is independent of the input vectors. Our techniques are capable of identifying regions in the circuit where defects may escape the test set. ii We further discuss a method for test generation for our region-based defect model and show how it can be used to improve the accuracy of diagnosis targeting arbitrary defects. We show that the problems of improvement of error/fault diagnosis, Boolean comparison for design veri cation in presence of unknown constraints and ATPG for IP-based designs can be modeled as a general problem of solving Boolean satis ability under unknown constraints on a set of input variables. A SAT-based formulation to nd if a given formula in the conjunctive normal form (CNF) from the propositional logic is satis able under unknown constraints on some input variables, and a network modi cation-based solution to solve constrained Boolean satis ability have been proposed. Experimental results on improvement of the accuracy of error diagnosis, constrained Boolean comparison and ATPG for IP-based designs have been presented on the ISCAS 85 benchmark circuits. iii Acknowledgements I wish to express my gratitude to my advisor, Professor Michael Hsiao of Electrical and Computer Engineering Department of Rutgers University, for his guidance throughout this research project. I would also like to thank Dr. Vamsi Boppana from Fujitsu Labs of America, CA for all his immense help and suggestions during the project. Thanks are also in order for Dr. Rajarshi Mukherjee, Dr. Jawahar Jain, Dr. Masahiro Fujita and other members of the CAD research group at Fujitsu Labs for their help and support. My special thanks to Subodh Reddy of Fujitsu Labs for helping me with the tools used in this research. A part of this research was conducted when I worked at Fujitsu Labs of America, Sunnyvale, CA during summer' 98. iv Table of