Modelling and Simulation of Multilevel Inverter Using Switched Series / Parallel DC Voltage Sources

A novel switched-inverter is proposed. Theproposed inverter outputs voltage level is more byusing switching the DC voltage sources in series and in parallel. The maximumoutput voltage is determined by the number of the levels.The proposed inverter, using the same number of switches, but various switching combinations more number of levels are obtained. The number of gate driving circuits is reduced, which leads to the reduction of the size and power consumption in the driving circuits. The total harmonic of the output waveform is also reduced. The proposed inverter is driven by the hybrid modulation method. In this paper, the circuit configuration, theoretical operation, Fourier analysis, simulation results with MATLAB/SIMULINK, and experimental results are shown. The experimental results accorded with the simulation results. Keywords-Cascaded H-bridge (CHB), hybrid modulation (HM), multilevel inverter, switched series/parallel. I.INTRODUCTION A multilevel inverter is a power electronic system that synthe-sizes a desired output voltage from several levels of dc voltages asinputs. Recently, multilevel power conversion technology has been d e v e lo p i n g t h e a r e a o f p o we r e l ec t ro n ic s ve r y r ap id l y wi t h go o d p o te n t i a l fo r f u r t he r d ev e l o p me n t s . T he mo s t a t t r a c t i ve ap p l i ca tions of this technology are in the medium to high voltage ranges. The concept of utilizing multiple small voltage levels to performpower conversion was presented by a MIT researcher[1,2]. Advantages of this multilevel approach include good power quality, goode lec t ro ma g n e t i c co mp a t ib i l i t y , l o w s wi t c h i n g lo ss e s a nd h i g h voltage capability. The first introduced topology is the series H-bridge design[1]. This was followed by the diode-clamped inverter[2–4]which utilizes a bank of series capacitors to split the dc bus voltage. The flyingcapacitor (or capacitor clamped)[5] topology followeddiode-clamped after few years, instead of series connected capacitors,this topologyuses floating capacitors to clamp the voltage levels. Another multilevel design, slightly different from the previousone, involves parallel connection of inverter phases through inter-phase reactors[6]. In this design the semiconductors must blockthe entire voltage, but share the load current. Also, several combinatorial designs have emerged[7], implemented cascading th efundamental topologies[8–12]; they are called hybrid topologies. These designs can create power quality for a given number of semiconductor devices higher than the fundamental topol ogiesalone due to a multiplying effect of the number of levels. Also, some soft switching methods can be implemented for differentmultilev el inverters to reduce the switching loss and to increaseefficiency[14,15]. Recently, several multilevel inverter topologieshave been developed[16–19]. Unfortunately, multilevel inverters have some disadvantages.One particular disadvantage is the great number of power semi-conductor switches needed. Although low voltage rate switchescan be utilized in a multilevel inverter, each switch requires a re-lated gate driver circuits. This may cause the overall system to bemore expensive and complex. So, in practical implementation,reducing the number of switches and gate driver circuits is veryimportant.This paper suggests a new topology for cascaded multilevelinverters with a high number of steps associated with a low number of switches and gate driver circuits for switches. In addition, forproducing all levels (odd and even) at the output voltage, threeprocedures for calculating the required dc voltage sources are pro-posed. Finally, the paper includes simulation and experimental results to prove the feasibility of the proposed multilevel inverter Venkatesh Inti et al. / IJAIR ISSN: 2278-7844 © 2012 IJAIR. ALL RIGHTS RESERVED 276 II.CIRCUIT TOPOLOGY Fig. 1 shows the circuit topology of the proposed inverter.The inverter is driven by the hybrid modulation (HM) method[5], [10], [15]. DC voltage sources V0−Vn are independent of each other,and V0 :Vk= 1 : 2 (k = 1, 2, . . . , n) is assumed. SwitchesSa1−San−1, Sb1−Sbn−1, and Sc1−Scn−1 are the switcheswhich switch the dc voltage sources in series and in parallel.Fig. 2 shows this eries/parallel conversion of the proposed15-level (n = 3) inverter. When the switches Sa1−San−1become OFF and the switches Sb1−Sbn−1 and Sc1−Scn−1become ON, the current flows in switches Sb1−Sbn−1 andSc1−Scn−1, which connect voltage sources V1−Vn in parallel [Fig. 2(a)]. Then, when the switch Sa1 becomes ON and the switches Sb1 and Sc1 become OFF, the current flows in the switch Sa1, which connect the voltage sources V1 and V2 in series via the switch Sa1 [Fig. 2(b)]. Using this series/parallel conversion of dc voltage sources, the lower H-bridge outputs vbus2 in 2n + 1 levels, while the upper H-bridge outputs vbus1 = V0. The proposed inverter outputs 4n + 3 levels by vbus1 + vbus2 or vbus2 − vbus1. Fig. 1.Circuit topology of the proposed 4n + 3-level inverter.