A Survey on Power Management Techniques

he increasing demand for low power mobile computing and consumer electronics products has refocused VLSI design in the last two decades on lowering power and increasing energy efficiency. Power reduction is treated at all design levels of VLSI chips, from architecture through block and logic levels, down to gate-level, circuit and physical implementation. One of the major dynamic power consumers is the system‘s clock signal, typically responsible for up to 50% of the total dynamic power consumption [31]. Clock network design is a delicate procedure, and is therefore done in a very conservative manner under worst case assumptions. It incorporates many diverse aspects such as selection of sequential elements, controlling the clock skew, and decisions on the topology and physical implementation of the clock distribution network. Advances in CMOS technology have made possible the integration of millions of transistors onto a small area. CMOS technology scaling allowed the reduction of the gate delay and the increasing the operating frequency, the increase of the transistor density and, finally, the decrease of the energy per transistor. Technology trends show that, in every circuit generation, delay and supply voltage have scaled down by 30%, performance and transistor density have doubled every two years and, finally, transistor‘s threshold voltage has reduced by almost 15% [31],[34]. In this scenario, power consumption represents one of the most important concerns in modern systems, since the battery power increases by about 15% per year and the chip power requirements by about 35% [5]. For CMOS technologies down to 130nm, dynamic power was considered as the main source of circuit‘s power consumption. However, due to the CMOS scaling process, leakage power dissipation has become a significant contributor to the total power. Leakage power is dissipated during both active and standby mode. Different physical phenomena can contribute to the leakage currents causing static consumption when one or more transistors are in a steady state. The four main components of leakage current are sub-threshold leakage (ISUB), gate leakage (IGATE), gate induce drain leakage (IGIDL) and reverse bias junction leakage (IRB). However, in today‘s technologies, the major sources of leakage consumption are represented by the sub-threshold and gate currents, with the former that greatly dominates. For some classes of circuits manufactured with the 65nm process, dynamic and leakage power are equally important. And the situation is expected to worsen further as technology scaling will continue. In the last few years, several techniques have been proposed in order to reduce the main sources associated to the power consumption in CMOS circuits [7]. Regarding dynamic power consumption[6], [10], the clock distribution network represents around 40% of the total power budget of a CMOS circuit, since the clock nets operate at the highest switching frequency compared to any other signal and they drive a large capacitive load. A number of examples of handcrafted powermanagement schemes can be found in the literature [44] and are actually implemented in well-known commercial devices. Automatic detection of good power management opportunities and synthesis of the required circuitry is a relatively new discipline. The key idea in power management is that unused parts of a complex design can be shut down during system operation. Shut-down can be achieved by zeroing the voltage supply or, in static synchronous CMOS logic, by stopping the clock. From a technology standpoint, supply shutdown has several serious drawbacks, such as current spikes on power and ground lines, loss of information stored in memory cells, and power-up delays. In this context, Clock Gating (CG) [1,3.4,6,7] is considered as one of the most effective techniques to reduce dynamic power. Clock-gating has a reduced technological impact, and can be successfully employed in a wider range of cases. Regarding leakage power, the main contributor to overall leakage can be considered the drain-to-source leakage through transistors that are nominally off, even though a number of new leakage sources are emerging as transistors do shrink (e.g., gate tunneling currents, junction reverse currents). In this scenario, Power Gating (PG) represents one of the most popular approaches for leakage power reduction and relies on the introduction of sleep transistors which are placed between the logic circuit and the ground rail (i.e., gnd), thus creating an T