Design Flows and Run Time Systems For Heterogeneous Multiprocessor Systems on Programmable Chips ( MPSoPCs )

FPGA’s have rapidly progressed through four generations and have now reached a level of maturity that allows them to be viewed as a complete multiprocessor system on programmable chip. In this invited talk, we present our approach to enable developers to guide the construction and program a heterogeneous MPSoC using standard POSIX-compatible programming abstractions. The ability to use a standard programming model is achieved by using a hardware-based microkernel to provide OS services to all heterogeneous components. Integration densities of FPGA’s continue to follow Moore’s law with emerging platform FPGAs soon to contain over 1 million LUTs. This level of transistor density will be sufficient to enable the integration of hundreds of soft programmable cores, interconnection networks, distributed memories and soft IP support components within a single FPGA. Prior to the introduction of platform FPGA’s, limited integration densities prohibited the construction of a complete multiprocessor system on programmable chip. During these earlier generations, FPGA’s were predominately used as accelerator co-processors for computationally intensive sections of code extracted from a single execution thread. Platform FPGA’s represent an interesting enabling technology that can allow designers to switch focus from providing performance increases through tedious and platform specific accelerator point designs to constructing multiprocessor systems on programmable chip architectures that achieve performance increases through portable scalable parallel processing. As the sizes of each generation of FPGA’s follows Moore’s law, designers can start considering the processor instead of the transistor as least separable design unit [1]. Targeting processors instead of transistors as the lowest level design quantum promises many advantages for widening the use of FPGA technologies, lowering design costs and time to market, and increasing designer productivity. While this approach sacrifices peak performance for productivity, switching focus from low-level hardware circuit design to writing high-level parallel programs makes FPGAs accessible to the broad base of software developers who do not possess hardware design skills. Both software and hardware designers can benefit from adopting familiar software development tools and run time systems to reduce design times, and enable code portability and reuse. These should be welcome advantages within the FPGA design community that largely worked with tools and design flows that result in relatively inefficient designer productivity. This viewpoint also represents an interesting convergence with the general purpose communities movement towards multicore architectures. Three barriers must be overcome to make this vision a reality. First, the selection of available soft IP processor components must continue to expand, and with appropriate compiler support. Efforts such as eMIPS and Vespa [2], [3] are increasing the selection of customizable, and vector and array programmable processors that can be integrated into a MPSoPC platform FPGA. These efforts cannot be fully exploited until associated advancements in compiler technology for heterogeneous systems are also achieved. The second barrier is the inability to simply adopt our existing commodity operating systems, which themselves are undergoing a major paradigm shift to meet the needs of next generation homogeneous and heterogeneous multicores. The structure of our monolithic kernels were never created with scalability in mind, and integrating processors with different Instruction Set Architectures (ISA’s) breaks current operating systems’ abilities to provide a single uniform set of abstract services that efficiently execute across mixes of processor ISAs. Resolving this issue is pivotal for platform MPSoPCs as the operating system forms the foundation upon which higher level run time services and user code bases are built.services that efficiently execute across mixes of processor ISAs. Resolving this issue is pivotal for platform MPSoPCs as the operating system forms the foundation upon which higher level run time services and user code bases are built. The third barrier is the lack of a standard high level programming model. Within the commercial sector several new programming frameworks are emerging specifically for heterogeneous manycores. OpenMP [4] has enjoyed some success for Symmetric Multiprocessor (SMP) global memory systems. More recently OpenCL [5] has gained popularity and is now a standard for distributed memory heterogeneous architectures. For reconfigurable systems, we are interested in extending the capabilities of the high level programming model to additionally drive the generation of a semi-custom heterogeneous MPSoPC. Third generation system level synthesis approaches made strides in generating hardware accelerators from computationally intensive portions of a high level language, such as C. However, translating a series of ALU operations into a more efficient custom circuit is orthogonal to creating an overarching multiprocessor system on chip architecture. We believe this new challenge represents a next, or forth generation of system level synthesis. In this talk we first present the challenges that must be addressed to creating appropriate design flows and run-time systems for heterogeneous MPSoPC’s. To achieve true software-like levels of productivity, the design flow and development environment for heterogeneous MPSoCs must resemble that of standard homogeneous multiprocessor systems. In our prior work called hthreads [6], [7], we have targeted the pthreads asynchronous multithreaded programming model due to it’s wide acceptance and popularity. In addition to supporting standard pthreads programs, targeting pthreads allows us to support emerging models such as OpenCL that rely on an underlying pthreads implementation. We then present our approach to enable developers to guide the construction and program a heterogeneous MPSoC using OpenCL and standard POSIXcompatible programming abstractions. We have created a new capability that allows a complete multiprocessor system on chip to be automatically created from the high level program. This relieves the designer from having to create and integrate by hand a complete set of IP components such as bus structures, I/O devices, and memory hierarchies to form the multiprocessor architecture. The architecture generated is in the form of a generic template that can be used as is, or later tuned within vendor specific tools. Taken together, we believe a combined approach of enabling the use of high level programming models and supporting the automatic and transparent assembly of a multiprocessor system on programmable chip architecture is fundamental for the future use of dense and power FPGA’s. REFERENCES [1] S. Trimberger, “FPL 2007 Xilinx Keynote Talk Redefining the FPGA,” http://ce.et. tudelft.nl/FPL/trimbergerFPL2007.pdf, last accessed May 10, 2011. [2] R. N. Pittman, N. L. Lynch, and A. Forin, “eMIPS, A Dynamically Extensible Processor,” Microsoft Research, Tech. Rep. MSR-TR-2006-143, Oct. 2006. [3] P. Yiannacouras, J. G. Steffan, and J. Rose, “VESPA: Portable, Scalable, and Flexible FPGA-Based Vector Processors,” in CASES ’08: Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems. New York, NY, USA: ACM, 2008, pp. 61–70. [4] L. Dagum and R. Menon, “OpenMP: An Industry-Standard API for Shared-Memory Programming,” Computing in Science and Engineering, vol. 5, no. 1, pp. 46–55, 1998. [5] “OpenCL The open standard for parallel programming of heterogeneous systems,” http://www.khronos. org/opencl/, last accessed May 10, 2011. [6] D. Andrews, D. Niehaus, and P. J. Ashenden, “Programming Models for Hybrid CPU/FPGA Chips,” IEEE Computer, vol. 37(1), pp. 118–120, 2004. [7] D. Andrews, R. Sass, E. Anderson, J. Agron, W. Peck, J. Stevens, F. Baijot, and E. Komp, “Achieving Programming Model Abstractions For Reconfigurable Computing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 34–44, January 2008.