DVS-BCB adhesive bonding for silicon photonics

A new process for bonding of III-V dies to processed silicon-on-insulator waveguide circuits using divinylsiloxane-bis-benzocyclobutene (DVS-BCB) was developed using a commercial wafer bonder. High-quality bonding, with ultra-thin bonding layers (< 50 nm) is demonstrated, which is suitable for the fabrication of heterogeneously integrated photonic devices, specifically hybrid III-V/Si lasers and photodetectors. Introduction Silicon photonics, based on the silicon-on-insulator (SOI) material platform, is emerging as an important platform for the realization of high-speed optical transceivers. Moreover, standard complementary metal oxide semiconductor (CMOS) processing infrastructure can be used to process these optical components [1]. This allows high-yield fabrication and a reduction of the component cost through economies of scale. However, the fabrication of efficient light sources in silicon photonics is challenging due to silicon’s indirect bandgap. In order to create photonic integrated circuits comprising both optoelectronic and passive optical components, the heterogeneous integration of passive silicon-on-insulator waveguide circuits and active InP/InGaAsP components has been proposed [2-3], for applications in the telecommunication wavelength range. Semiconductor wafer bonding allows the integration of high-quality III-V epitaxial layers on top of the silicon platform by transferring the III-V layer stack from its original growth substrate to the SOI wafer. Full wafer bonding, multiple die-to-wafer bonding or single die bonding can be envisaged, depending on the application. In all cases, an unprocessed III-V semiconductor epitaxial layer stack is transferred, which reduces the time required to complete the integration process compared to a flip-chip process, as no stringent alignment accuracy is needed because of the absence of structures on the dies or wafers. After removal of the growth substrate, the optoelectronic components can be fabricated in the bonded epitaxial layer. DVS-BCB is a good candidate for hybrid bonding because of its excellent physical properties such as low dielectric constant, low moisture absorption, low curing temperature, high degree of planarization, low level of ionic contaminants, high optical clarity, good thermal stability, excellent chemical resistance, and good compatibility with various metallization systems [4]. In this paper we describe a new adhesive wafer bonding process scheme that involves partial curing of the DVS-BCB prior to bonding and attaching the III-V substrate at room temperature prior to curing in a vacuum atmosphere. This ‘cold bonding’ method significantly simplifies the bonding preparation for machine-based bonding both for die and wafer-scale bonding. This approach shows high yield for ultra-thin bonding thicknesses below 50 nm, as well as good uniformity of the DVS-BCB layer thickness after wafer bonding over the full wafer area. This process was applied to achieve ultrathin DVS-BCB bonding layers for the fabrication of several photonic devices, such as IIIV/SOI lasers and optical isolators. DVS-BCB wafer bonding processes The bonding process was developed for a wafer level epitaxial layer transfer; however, as will be shown later, it can also be applied to multiple die-to-wafer bonding and singledie bonding. A MicroTec ELAN CB6L wafer bonder was used for bonding experiments. Commercial DVS-BCB solutions are limited in available spin-coated layer thicknesses down to 1μm (for Cyclotene®TM 3022-35 from Dow Chemical). Since this work deals with bonding layer thicknesses that are an order of magnitude smaller, mesitylene is added to Cyclotene 3022-35 to reduce the spin-coated layer thickness substantially. The processing procedure is schematically illustrated in Figure. 1. The bonding process starts with the cleaning of the SOI substrate and III-V dies. The SOI cleaning is performed by immersing the substrate for 15 minutes into a Standard Clean 1 (SC-1) solution, comprising aqueous ammonia (NH4OH), hydrogen peroxide (H2O2) and deionized (DI) water in volume ratios of 1:1:5, respectively, which is heated to 70 °C. After this, the DVS-BCB:mesitylene solution is spin-coated onto the SOI substrate. The SOI substrate is then baked for 10 min at 150 °C, to let mesitylene evaporate, after which the substrate is slowly cooled down to room temperature. Finally, the SOI is mounted on a carrier wafer made of Pyrex glass (1200 um thick, 100 mm diameter). Meanwhile, prior to bonding, a sacricifial InP/InGaAs sacrificial layer pair on the III-V wafer/die is removed by selective wet etching using HCl:H2O and H2SO4:H2O2:H2O in volume ratios of 4:1 and 1:1:18 respectively. This procedure removes particles and contaminants from the III-V die surface. The III-V die is then rinsed with DI water, dried and mounted on the SOI die. Since in the presented method the dies are contacted at room temperature, individual dies can easily be pick-and-placed onto the silicon target wafer. They can be aligned manually with an accuracy of 500μm without any extra tools or can be placed more accurately using a flip-chip machine. After that, the SOI substrate on its carrier wafer is mounted on the transport fixture and is loaded into the processing chamber of the wafer bonding tool. The chamber is pumped-down (target pressure 10-3 mbar) and heated to 150°C with a ramp of 15 °C/min for 10 min, while applying pressure on the III-V/SOI stack. Figure 1: Developed bonding process, referred to as ‘cold bonding’. The actual bonding pressure (the applied force per area of the III-V die) is kept in the range of 200 to 400 KPa. After keeping the pressure on the dies for 10 min at 150 °C, temperature is increased up to 280 °C, with a ramp of 1.5 °C/min. Upon reaching 280 °C, the dies are kept at this temperature for 60 min in a nitrogen atmosphere. After the curing, the bonded samples are cooled down (at 6-10 °C/min) and unloaded from the processing chamber. The InP substrate of the III-V die is then removed by a selective wet etching using HCl, leaving a thin III-V film with the functional layers bonded to the SOI die, ready for further processing. An alternative method has been reported earlier by our group [5], in which adhesive die-to-wafer bonding was demonstrated in a commercial wafer bonder. In this method spacers are used to keep the die and substrate separate prior to loading the stack in the bonding tool. In this new method no carrier is required to load the top wafer/die into the machine and no vacuum or heating is required prior to contacting the wafers in the bonding chamber. This makes the process more straight forward. Moreover, with the previous recipe, it was not possible to perform multiple dieto-wafer bonding for dies with different thickness. Using this new method we demonstrate that multiple-die bonding with different die thickness is feasible [6].