ASIP Architecture for Future Wireless Systems: Flexibility and Customization

Processors for mobile handsets in 3G cellular systems [1] require: high speed, flexibility and low power dissipation. In addition, computationally very demanding algorithms are needed to remove high levels of multiuser interference especially in MIMO case. Traditional architecture solutions are ASIC and DSP processors. While computationally efficient, ASIC processors are often not flexible enough to support variations of implemented wireless algorithms. On the other hand, DSP processors, although flexible and fully programmable, often cannot achieve high performance with low power dissipation (limited level of instruction and data parallelism). Because of that, there is a recent interest in new flexible architectures with limited programmability [2] and possibility for customization that is targeted to a class of wireless applications with high levels of data and instruction parallelism. These architectures are called Application Specific Instruction set Processors (ASIPs) and can replace multiple chip designs implemented as an ASIC architecture [3]. The ultimate goal of designing flexible ASIPs for implementation of physical layer of cellular applications is the most optimal architecture solution in terms of power dissipation and area that can meet high-demanding real-time requirements defined by 3GPP standards ([1] and [4]) with reasonable clock frequency. The frequency range of up to 200MHz is proven to be a good tradeoff between clock speed and power dissipation. We propose the implementation of base-band wireless algorithms on the ASIP processors based on Transport Triggered Architecture (TTA) [5]. It can be shown that the application specific processor based on TTA is programmable and flexible enough in order to handle different modifications of wireless application, operate in broad range of channel environments defined by 3GPP standard (from two-paths Pedestrian A to five-paths Vehicular A channels, speed of mobile subscriber varies from 3km/h to 120 km/h) and can achieve real-time requirements in high data rate downlink with a frequency of up to 200MHz and low power dissipation. TTA software tools [6] are integral part of TTA design package and they are used to search for TTA processor with the most favorable cost/performance ratio. The integration of application-specific user-defined instructions and implementation of corresponding Special Function Units (SFUs) is achieved by modifying (recompiling) the existing TTA software tools. By implementing set of specialized operations some level of architecture flexibility is traded-off for smaller area occupation, lower dynamic power dissipation, and faster execution. VHDL representation of the processor core can be obtained by using processor generator software tool [6]. Generated processor cores together with the memory peripherals are synthesized for FPGA prototype implementation using Xilinx ISE Foundation synthesis tool [7] and also for CMOS gate-level analysis using Mentor Graphics [8] software tools. This hardware-software design flow, that is unique feature of ASIP architectures, provides fast and an efficient way to generate flexible hardware module directly from the High Level Language (HLL) description of the wireless application.