VERSATILE COMPLEX MARCH TEST PATTERN GENERATION FOR HIGH SPEED FAULT DIAGNOSIS IN FPGA BASED MEMORY BLOCKS

The memory blocks testing is a separate testing procedure followed in VLSI testing. The memory blocks testing involves writing a specific bit sequences in the memory locations and reading them again. This type of test is called March test. A particular March test consists of a sequence of writes followed by reads with increasing or decreasing address. For example the March Ctest has the following test pattern. There are several test circuits available for testing the memory chips. However no test setup is developed so far for testing the memory blocks inside the FPGA. The BRAM blocks of FPGA are designed to work at much higher frequency than the FPGA core logic. Hence testing the BRAMs at higher speed is essential. The conventional memory test circuits cannot be used for this purpose. Hence the proposed work develops a memory testing tool based on March tests for FPGA based BRAM (block RAM testing). The code modules for March test generator shall be developed in VHDL and shall be synthesized for Xilinx Spartan 3 Family device. A PC based GUI tool shall send command to FPGA using serial port for selecting the type of test. The FPGA core gets the command through UART and performs the appropriate and sends the test report back to PC. The results shall be verified in simulation with Xilinx ISE simulator and also in hardware by using Chip scope. Xilinx Spartan 3 family FPGA board shall be used for hardware verification of the developed March test generator. International Journal of Advances in Engineering Research http://www.ijaer. com (IJAER) 2013, Vol. No. 6, Issue No. II, Aug ISSN: 2231-5152 46 INTERNATIONAL JOURNAL OF ADVANCES IN ENGINEERING RESEARCH INTRODUCTION The cost of verification and test for nowadays circuits represents an important part of the total IC final price. Hence, the domain of test represents a cornerstone for the industry and consequently for the academic research and education. For this purpose, a series of lectures presents the main fault models encountered in modern technologies like stuck @, bridging, open. and the algorithms classically employed for test vectors generation (D-Algorithm, PODEM, etc.). The tangible aspects of the test are then studied throughpractical class by the use of the CAD tool for ATPG(Automatic Test Pattern Generation) TetraMAX, and the industrial ATE (Automatic Test Equipment) Verigy. While the test of the ASICs represents an important part of the efforts made in the domain, there is a family of components which requires a particular attention: memories. Indeed, the silicon area dedicated to memory elements is constantly growing in recent designs . Memory testing strongly differs from the test of conventional ASICs. Consequently, we underline the necessity of introducing this subject into a curriculum of our engineers in microelectronics. The University of Turin (Italy) [2] proposes a tool for learning memory testing. This very interesting working environment remains however very abstract and virtual because the test memory is not a real one, i.e. it does not actually exist, but its function is emulated. Furthermore, this tool implements only a single test algorithm. In this article, we present an original memory test framework: an SRAM memory test bench, roaming and programmable. This test bench allows not only to employ different commercial SRAM memories but also to apply various algorithms for test. With this new test bench, students can concretize the memories testing's lectures and enlighten the inherent properties of the various applied algorithms as well as the differences between the memory architectures and technologies VERSATILE MARCH TEST GENERATOR Memory testing may be considered as a full disciplinary subject. Commonly, test sequences or test algorithms for memories are known under the name of March tests. Every March test has specific capabilities that allow revealing the typical defects of memories [3]. A typical didactic test bench has to allow not only the implementation of March tests existing in the literature but also the creating of new test algorithms. A March test consists of a sequence of March elements. A March element has a certain number of operations (or March primitive) that must be applied to all memory cells of an array. Thus, ↑(r0;w1) is a March element and r0 and w1 are March primitives. The addressing order of a March element can be done in an up (↑), down (↓) way or (↕) if the order is not significant. A March primitive can be a write 1 (w1), write 0 (w0), read 1(r1) and read 0 (r0) that can be performed in a memory cell. Here, we introduce, for example, the March C: {↑(w0);↑(r0,w1);↑(r1,w0);↓(r0,w1);↓(r1,w0);↑(r0)} International Journal of Advances in Engineering Research http://www.ijaer. com (IJAER) 2013, Vol. No. 6, Issue No. II, Aug ISSN: 2231-5152 47 INTERNATIONAL JOURNAL OF ADVANCES IN ENGINEERING RESEARCH This well-known March test allows to detect all the stuck @ and transition fault of a memory cell array, as well as all address decoder faults and coupling (interaction between two cells) faults. A way to create a function allowing the implementation of any March test is to use the structure described on table 1. A 274 bits register is needed to memorize the March test data Table 1 gives for example the data -base implementation of the March test C-. TEST BENCH ARCHITECTURE Our test bench architecture for memories is composed of one computer, a versatile March test generator, a serial interface (for the communication between the programmable generator and the computer) and a deck containing 4 SRAM memories under test, Fig. 1. A user interface, presented in Fig. 2, allows students to choose or set a specific March test of the literature (March A, March C-, Matt, Matt +) or introduce a new one (Custom). The chosen March test is uploaded through the serial connection to the programmable test generator and then applied to each memory on the deck. International Journal of Advances in Engineering Research http://www.ijaer. com (IJAER) 2013, Vol. No. 6, Issue No. II, Aug ISSN: 2231-5152 48 INTERNATIONAL JOURNAL OF ADVANCES IN ENGINEERING RESEARCH If no fault is detected, the programmable generator returns a positive acknowledgement on the four memories. Whether the opposite case occurs, i.e. when a reading operation (r0 or r1) does not return the expected data, the test bench returns the following data: the failing memory, the failing address, the failing march element and operation. Only the knowledge of this information allows the identification of physical defects beside the observed fault, or at least to make reasonable suppositions. Fig. 3 depicts the test bench (with four memories under test) that is proposed to our students. A serial cable connects the test bench to a computer. The four memories (on the top of the picture) are tested in sequence (not simultaneously) following a scheduling that is fixed by the user. International Journal of Advances in Engineering Research http://www.ijaer. com (IJAER) 2013, Vol. No. 6, Issue No. II, Aug ISSN: 2231-5152 49 INTERNATIONAL JOURNAL OF ADVANCES IN ENGINEERING RESEARCH One or more than one memory can be replaced by a memory emulator, in which we can introduce any kind of fault model [4] such as stuck @, transition, address decoder, coupling faults, etc. The use of the fault injection through the memory emulator is important to make the student able to check the efficiency of March test algorithms to test specific fault models that may affect the memories. With the analysis of the test report the student obtains useful data to uncover the correlation between the detected fault and the sequence of read/write operations that allow the sensitization and observation of the fault itself. This analysis highly helps the student's knowledge of memory failing processes as well as his skill to generate appropriate March test algorithms to target specific pull of faults.