4H-SiC MOSFETs on C(000-,1) Face with Inversion Channel Mobility of 127cm2/Vs

SiC power MOSFETs is a promising candidate for the normally-off type fast switching device in the next generation. However, the on-resistance of SiC power MOSFETs is almost the same as that of Si IGBTs, which is much higher than the calculated value. This is caused by the low channel mobility due to high interface trap density. Large improvement of channel mobility is expected for SiC power MOSFETs with low on-resistance. We have already reported that the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face was 72cm 2 /Vs, which is higher than the Si(0001) face. In this paper, we have investigated the effects of gate-oxidation temperature and H2 post oxidation annealing on the Dit of n-type MOS capacitors and the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face. The Dit is reduced and the inversion channel mobility is improved as the gate-oxidation temperature decreases. The inversion channel mobility of 4H-SiC MOSFETs with the gate-oxide film grown at 900°C is 118cm 2 /Vs. Furthermore, using H2 POA, we have succeeded in the inversion channel mobility as high as 127cm 2 /Vs. This means that the C(000 _ ,1) face would be capable of SiC power MOSFETs with the high blocking voltage. Introduction SiC power MOSFETs is a promising candidate for the normally-off type fast switching device in the next generation. At present, the on-resistance of SiC power MOSFETs becomes the almost same as that of Si IGBT, which is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface trap density (Dit). Recently, we have reported that the inversion channel mobility as high as 198cm 2 /Vs for 4H-SiC MOSFETs fabricated on the (11 _ ,20) face were achieved using the pyrogenic oxidation and the H2 post oxidation annealing (POA)[1]. However, the breakdown field of the (11 _ ,20) face in 4H-SiC is approximately 75% of the Si(0001) face[2]. The (11 _ ,20) face might be disadvantageous for the high power MOSFETs. In contrast, the C(000 _ ,1)face has the largest oxidation ratio, which is approximately 70% of that of Si[3]. This enables large reduction of oxidation process time in SiC MOSFETs fabrication. Furthermore, the C(000 _ ,1) face has the same breakdown field as the Si(0001)face[4]. The C(000 _ ,1) face is considered to be suitable for power SiC MOSFETs. We Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1417-1420 doi:10.4028/www.scientific. net/MSF.457-460.1417 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific. net. (Semanticscholar.org-11/03/20,15:23:29) have already reported that the inversion channel mobility of 4H-SiC MOSFETs become 72cm 2 /Vs [5]. However, this value is insufficient for the theoretical on-resistance of SiC MOSFETs with the blocking voltage of 1kV. Much higher channel mobility is required. In this work, we have investigated the effect of the gate-oxidation temperature and H2 POA on the Dit of n-type MOS capacitors and inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(000 _ ,1) face. Experimental procedure The n-type C(000 _ ,1) face epitaxial SiC substrates for n-type capacitors and p-type C(000 _ ,1) face bulk substrates for n-channel MOSFETs were purchased from Cree corporation. The p-type epitaxial layer were grown by our group [6]. The Nd-Na and Na-Nd of epitaxial layers were 2.5×10 16 cm -3 and 5×10 15 cm -3 , respectively. In the case of n-type MOS capacitors, gate-oxide films were thermally grown from 900°C to 1100°C using a pyrogenic oxidation, which is performed in the atmosphere containing H2O created by the reaction of O2 and H2. The thickness of gate-oxide films was approximately 45nm. After oxidation, samples were annealed in Ar for 30 min at the same temperature as the oxidation. After oxidation, the sample with gate-oxidation at 900°C was annealed in H2 at 800°C for 30 min. The gate electrodes and ohmic contacts to MOS capacitors were formed by aluminum evaporation. The Dit estimations were carried out using high-low method in KI82 system. In the case of n-channel MOSFETs, the source and drain regions were formed by phosphorus ion implantation at 500°C with the dose of 7×10 15 cm -2 . Post-implantation annealing was performed at 1500°C for 5 min in Ar. The gate-oxidation was performed under the same condition as n-type MOS capacitors. Aluminum as the gate metal and the contact metals for source/drain and substrate was evaporated. Figure 1 shows the top view of MOSFETs used for measurement of the electrical properties for SiC MOSFETs. The channel length (L) and width (W) were 100μm and 150μm, respectively. Electrical properties of 4H-SiC MOSFETs were analysed using an HP4156B semiconductor parameter analyser. Fig.2 Effect of gate-oxidation temperature and H2 POA on Dit of the MOS capacitors fabricated on the C(000 _ ,1) face. Gate