Miracle-dz/UniFAR-FTUs huggingface dataset:
Low Power Extended Range Multi-Modulus Divider Using True-Single-Phase-Clock Logic

This paper presents a new optimized extended range Multi-Modulus Divider (MMD) for the low power and high speed frequency synthesis application. The proposed MMD architecture is designed for the 6-stages using the low power 2/3 prescalers, implemented with True-Single-Phase-Clock (TSPC) logic. An extended range of the MMD provides the seamless programmable divisions from 8 ~ 127. The proposed design is simulated in LP 65 nm CMOS process and the performance is analysed in terms of power and frequency. The results show the proposed 2/3 prescalers achieves more than 50% of power saving when compared to the conventional 2/3 prescaler. Also, the overall MMD architecture shows the maximum power consumption of 1.6 mW and minimum of 0.9 mW at 6 GHz with the supply voltage of 0.95 V.
Human-Exoskeleton Coupling Dynamics of a Multi-Mode Therapeutic Exoskeleton for Upper Limb Rehabilitation Training

The purpose of this study is to establish the human-exoskeleton coupling (HEC) dynamic model of the upper limb exoskeleton, overcome the difficulties of dynamic modeling caused by the differences of individual and disease conditions and the complexity of musculoskeletal system, to achieve early intervention and optimal assistance for stroke patients. This paper proposes a method of HEC dynamics modeling, and analyzes the HEC dynamics in the patient-active training (PAT) and patient-passive training (PPT) mode, and designs a step-by-step dynamic parameter identification method suitable for the PAT and PPT modes. Comparing the HEC torques obtained by the dynamic model with the real torques measured by torque sensors, the root mean square error (RMSE) can be kept within 13% in both PAT and PPT modes. A calibration experiment was intended to further verify the accuracy of dynamic parameter identification. The theoretical torque of the load calculated by the dynamic model, is compared with the difference calculated by parameter identification. The trends and peaks of the two curves are similar, and there are also errors caused by experimental measurements. Furthermore, this paper proposes a prediction model of the patient’s height and weight and HEC dynamics parameters in the PPT mode. The RMSE of the elbow and shoulder joints of the prediction model is 9.5% and 13.3%. The proposed HEC dynamic model is helpful to provide different training effects in the PAT and PPT mode and optimal training and assistance for stroke patients.
Impact of mechanical strain on wakeup of HfO2 ferroelectric memory

This work investigates the impact of mechanical strain on wake-up behavior of planar HfO2 ferroelectric capacitor-based memory. External in-plane strain was applied using a four-point bending tool and strain impact on remanent polarization and coercive voltage of the ferroelectric was monitored. It was established that compressive strain is beneficial for 2Pr improvement, while tensile strain leads to its degradation, with a sensitivity of -8.4 ± 0.5 % per 0.1 % of strain. Strain-induced polarization rotation is considered to be the most likely mechanism affecting 2Pr• At the same time, no strain impact on Vcwas observed in the investigated strain range. The results seen here can be utilized to undertake stress engineering of ferroelectric memory in order to improve its performance.
A Novel Economical Design of Multistage Decimators for Low Latency Audio Applications

The oversampling sigma-delta analog-to-digital converter (ADC) is widely used in digital audio systems for its low hardware cost and high precision. The digital filter part of the ADC is the primary source of the silicon and power cost. In this work, we proposed an economical multistage decimation filter architecture to meet the requirements of commercial ADC specifications with a further novel multi-objective optimization strategy. We took group delay and computational cost as objective functions and used annealing algorithm to readjust the stopband attenuation, stopband edge and passband ripple of each filter. Our multistage architecture combines cascaded integrator–comb (CIC) filters, compensating filters and equiripple finite impulse response (FIR) filters at the different stages to balance the overall performance. The experimental results showed that our design approach worked with multi-objective optimization strategy could achieve low group delay with lower cost compared to traditional designs.
Bendable Microwave AlGaN/GaN High-Electron-Mobility Transistor With Output Power Density of 2.65 W/mm

Flexible radio frequency (RF) devices are in high demand for wearable electronics; however, they currently do not offer sufficient output power for application in fifth-generation wireless communication systems. This paper reports a bendable gallium nitride (GaN) high-electron-mobility-transistor (HEMT) with state-of-the-art output power in the microwave band. In this study, a fabrication method is proposed, where HEMT is originally grown on silicon carbide (SiC) substrates. After thinning the SiC substrates down to $5~\mu \text{m}$ , HEMT is transferred using a copper film rather than flexible substrates used in other studies. The measurements indicated that the fabricated devices exhibited a saturation output power of 2.65 W, corresponding to a power density of 2.65 W/mm, which was associated with maximum power added efficiency (PAE) of 51% at 3 GHz. The performance of the fabricated device remained stable even with a bending radius of up to 0.6 cm. These results indicated that the proposed fabrication method can potentially be used to realize high-power flexible RF electronics.
Investigation of Arc Flash in Single-Phase Vertical Conductors in a Box

NFPA 70E and IEEE 1584 are defining standards for arc flash hazard analysis. Both assume three-phase faults for calculations since three-phase power distribution is predominant in utility and industrial applications; however, arc flash in single-phase systems is excluded. Single-phase faults to neutral or ground or single phase-to-phase faults can occur in a variety of circumstances. Such events may have the potential to produce arc flash and blast that would pose a significant safety concern. This paper describes a recent doctoral research investigation of arc flash in one single-phase configuration. Experiments were sponsored by UL and performed at the Schneider Electric High-Power Laboratory in Cedar Rapids, Iowa. This facility provided a test article; a full suite of voltage, current, and temperature instrumentation; and high-speed video recording. Experimental work revealed incident energy values less than 0.2 cal/cm2 for 240-volt single-phase arc fault events though there was still significant flash and splatter of molten wire residue. 480 V single-phase events produced an order of magnitude greater heat energy, and at 22 kA sustained arcing until interrupted by the test cell controller. Results suggest that 240 V single-phase panels and equipment common in residential and light commercial applications may be at very low risk of yielding arc flash burn-related injuries. However, 480 V single-phase faults can produce levels of incident heat energy known to cause burns, flash, and blast pressure at available fault currents between 10 and 22 kA.
A Study of Experiment-based Radio Frequency Electromagnetic Field Exposure Evidence on Stochastic Nature of A Massive MIMO System

In this paper, a massive multiple-input-multiple-output (mMIMO) testbed that is capable of mimicking realistic 5G new radio (NR) base station (BS) beamforming performance has been utilised to gather experimental-based evidence of 5G BS RF-EMF exposure within a real-world indoor environment. The mMIMO testbed has up to 128 RF channels with user-programmable software defined radio (SDR) capability. The stochastic nature of the 5G NR mMIMO system has been statistically assessed by evaluating the spatial variation of the RF-EMF exposure surrounding the mMIMO testbed when taking into account different beam profiles and data rates. Several other factors that influence the RF-EMF of mMIMO system have also being considered.
Gate Current Transport in Enhancement-Mode p-n Junction/AlGaN/GaN (PNJ) HEMT

In this work, we study the gate leakage mechanisms of E-mode <inline-formula> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> junction/AlGaN/GaN (PNJ) high electron mobility transistors (HEMTs), which have been shown to deliver low gate leakage and wide safe operating gate-bias range. The intrinsic gate leakage through the PNJ-gate was found to be limited by the transport of holes through the <inline-formula> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula>-GaN layer, which occurs via Poole-Frenkel emission and phonon-assisted tunneling in low and high gate bias region, respectively. In addition, lateral leakage current and the role of variable hopping process (VRH) are also discussed. Gate leakage current models based on the revealed mechanisms can quantitatively reproduce the gate-leakage behavior in the entire relevant range of gate biases and temperatures.
BB-PKI: Blockchain-Based Public Key Infrastructure Certificate Management

Recently, real-world attacks against the web Public Key Infrastructure (PKI) have arisen more frequently. The current PKI that use Registration Authorities/Certificate Authorities (RAs/CAs) model suffer from notorious security vulnerabilities. Most of these vulnerabilities are due to compromises of RAs, which lead to impersonation attacks resulting in CAs misbehaving to issue bogus certificates. To counter this problem, many approaches, such as Certificate Transparency (CT), ARPKI, and PoliCert, have been proposed. Nonetheless, no solution has yet gained widespread acceptance as a result of complexity and deployability issues. Moreover, existing approaches still require to satisfy complicated interactions and synchronisation among the entities that are involved during certificate issuance, updates, and revocations. In this paper, we propose a new Blockchain-Based PKI (BB-PKI) to address these vulnerabilities of CA misbehaviour caused by impersonation attacks against RAs. Certificate Issuance Request (CIR) should be vouched by manifold RAs. Multiple CAs shall sign and issue the certificate using an out-of-band secure communication channel. Any RA that contributes to the verification process of a user’s request can publish the certificate in the blockchain by creating a smart contract certificate transaction. BB-PKI offers strong security guarantees, compromising $n - 1$ of the RAs or CAs is not enough to launch impersonation attacks, meaning that attackers cannot compromise more than the threshold of the latter signatures to launch an attack.
Bandpass Negative Group Delay Theory of Fully Capacitive Δ-Network

A particularly original negative group delay (NGD) theory of <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-topology is developed in the present paper. The NGD three-port topology is a passive circuit purely constituted by capacitors network. The model of the proposed <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-topology impedance 3-D matrix is analytically established in function of the capacitor elements. Then, the S-matrix model is derived by using the Y-to-S transform. By considering the S-matrix frequency responses, a bandpass (BP) NGD analysis of the capacitive <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-topology is originally elaborated. It is theoretically demonstrated that the passive <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-topology is susceptible to behave as a BP NGD circuit under an analytical condition between the constituting capacitor values. The design feasibility of the BP NGD function is experimentally verified with lumped capacitor components-based <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-circuit proof of concept. An electronic circuit board constituted by purely capacitive-network <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-circuit is fabricated as an original <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>-circuit prototype. The tested board is constituted by arbitrary chosen capacitors, 100 nF, 10 nF and 0.1 nF. As expected, the calculation, simulation and measurement results, which are in very good agreement, confirm the BP NGD behavior. It is observed from measurement that it generates NGD of about −18.1 ns at a frequency of about 0.55 MHz and, lower and upper cut-off frequencies of about 0.33 MHz and 1.71 MHz. It is noteworthy that the transmission and reflection coefficients at very low frequency are independent of the capacitor values and analytically equal to 2/3 and 1/3, respectively.
SWIPT Model Adopting a PS Framework to Aid IoT Networks Inspired by the Emerging Cooperative NOMA Technique

We present the design for an ultra-low latency and low energy Internet of Things (IoT) network inspired by the emerging cooperative Non-Orthogonal Multiple Access (NOMA) wireless communication technique. The IoT network model consists of a source at the center of the network, a near device inside the network, and a far device outside the network. The far device is in the near proximity of the near device, however. We deploy the near device as a relay to assist the far device. The near device is assumed to be a low energy node. As a result, the near device cannot forward signals to the far device through its own power. We therefore design the IoT network to apply the Simultaneous Wireless Information and Power Transfer (SWIPT) technique so that the near device would be able to harvest energy and use it to forward signals. Two cooperative IoT network scenarios are examined: Half-Duplex (HD) and Full-Duplex (FD) relaying, each with and without eavesdroppers. The design also exploits Power Splitting (PS) factors for fairness in Quality of Service (QoS) for the devices. Novel analysis expressions are obtained accuracy and approximation of closed-forms for Outage Probability (OP), secrecy OP, system throughput and Jain’s fairness index. The analysis results are proved and verified by Monte Carlo simulation results.
Reliability of STT-MRAM for various embedded applications

Owing to tunability of MTJ stack characteristics based on perpendicular magnetic anisotropy control via sophisticated magnetic material engineering, STT-MRAM can meet a wide range of product specifications for various applications: 1) flash-type applications such as microcontroller and AI inferencing device and 2) SRAM-type applications such as frame buffer memory. However each application has different reliability challenges. In this paper, we discuss the reliability requirements for Flash-type and SRAM-type STT-MRAM, verifying superb reliability of highly tunable STT-MRAM technology.
An Improved Alpha Beta Filter Using a Deep Extreme Learning Machine

This paper introduces new learning to the prediction model to enhance the prediction algorithms’ performance in dynamic circumstances. We have proposed a novel technique based on the alpha-beta filter and deep extreme learning machine (DELM) algorithm named as learning to alpha-beta filter. The proposed method has two main components, namely the prediction unit and the learning unit. We have used the alpha-beta filter in the prediction unit, and the learning unit uses a DELM. The main problem with the conventional alpha-beta filter is that the values are generally selected via the trial-and-error technique. Once the alpha-beta values are chosen for a specific problem, they remain fixed for the entire data. It has been observed that different alpha-beta values for the same problem give different results. Hence it is essential to tune the alpha-beta values according to their historical behavior for certain values. Therefore, in the proposed method, we have addressed this problem and added the learning module to the conventional <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> filter to improve the <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> filter’s performance. The DELM algorithm has been used to enhance the conventional alpha-beta filter algorithm’s performance in dynamically changing conditions. The model performance has been measured using indoor environmental values of temperature and humidity. The relative improvement in the proposed learning prediction model’s accuracy was 7.72% and 16.47% in RMSE and MSE metrics. The results show that the proposed model outperforms in terms of the result as compared to the conventional alpha-beta filter.
Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm

Design margins are necessary to ensure reliable operation of integrated circuits over extreme ranges of environmental variations (Voltage, Temperature) and manufacturing Process variations. On top of these PVT variations, aging related parametric drift (e.g. due to BTI, HCI) also limits performance by requiring additional timing margin. In principle, corner based design methodology can be adopted. However, this approach is sub-optimal, because it applies margins which may be either too optimistic or pessimistic since it tends to ignore the correlation effects which exist inherently due to the circuit topology and the workload effects. In this paper, we propose a workload-dependent reliability aware optimization flow under the influence of NBTI aging by utilizing an optimal margining scheme. The proposed flow takes into account the relevant correlations in a design by modelling the degradation accurately and thus enables achieving the desired Power-Performance-Area (PPA) goals without severe reliability penalty.
A Theoretical Framework for Trap Generation and Passivation in NAND Flash Tunnel Oxide During Distributed Cycling and Retention Bake

MEmory Reliability Investigation Tool (MERIT) framework, with a generic Reaction-Diffusion-Drift (RDD) model is used to simulate the channel interface $(\Delta\mathrm{N}_{\mathrm{I}\mathrm{T}})$ and bulk oxide $(\Delta\mathrm{N}_{\mathrm{O}\mathrm{T}})$ traps time kinetics in the tunnel oxide (TO) of NAND Flash during Erase-Program (EP) cycling and retention bake after cycling. The generation and passivation of traps are calculated from cycle-to-cycle during distributed EP cycling, and trap passivation is calculated during bake. The framework can model multiple EP cycling phases with varying EP cycling delays, and EP cycling and bake temperature (T). The use of different EP cycling T to mimic the distributed cycling impact is analyzed. The Universal Detrapping Metric (UDM) for various inserted delays and cycling temperatures is verified.
Impacts of Depth and Lateral Profiles of Fluorine Atoms in Gate Oxide Films on Reliability

Fluorine (F) implantation into gate poly-Si was used to incorporate F atoms in gate oxide films. Different F profiles in depth direction of gate oxide films were prepared. Enhanced segregation of F atoms at SiO2/Si interfaces was important for improvement of time dependent dielectric breakdown (TDDB) lifetime and suppression of hot carrier degradation. TDDB and low frequency noise dependences on gate length suggested that F profiles in lateral direction of gate oxide films should be cared for reliability of short channel devices.
Machine-learned models for the performance of six different solar PV technologies under the tropical environment

Due to the recent environmental concerns and long-term challenges in energy security, the Global energy scenarios are shifting more towards sustainable and renewable energy resources. Brunei has planned to increase the use of cleaner energy technologies by contributing 10 percent or 954 GWh of renewable energy in its power generation mix by 2035. Out of the available renewable options, solar is the most promising one for Brunei, for example, the daily average solar installation is around 5kWh per day [1]. Though solar energy is an abundant resource, for optimally designing and successfully managing solar power projects, its availability in different time scales are to be analyzed and understood in a local context. In this paper, we present models for estimating the output of six different solar PV technologies using machine learning methods Performance data from the solar PV systems installed at the Tenaga Suria PV plant in Brunei are used to develop the models. Influence of relevant environmental parameters, such as irradiance, relative humidity, ambient temperature and wind speed on the power output has been analyzed for optimal feature selection. Performance models based on Support Vector Machine (SVM) and K-Nearest Neighbour (KNN) were developed and tested for predicting the PV system performance. Both the models could estimate the system performance with reasonably high level of accuracy.
A Multi-Objective Genetic GAN Oversampling: Application to Intelligent Transport Anomaly Detection\

The Internet of Things (IoT) enables the automation of data collection and processing functions but exposes a huge amount of data to the cyberattacks risk. To tackle this issue, anomaly detection allows to identify data points, events, and/or observations that deviate from a dataset’s normal behaviour indicating eventual critical incidents. In this paper, we focus on the imbalance data and the minority classes problem where the number of abnormal samples is much less than normal (secure) samples. In particular, this paper presents a new equilibrium model based on a Genetic Algorithm to improve Generative Adversarial networks (GANs). This model addresses the problem of class imbalance to anomaly detection system performance. The proposed approach use is illustrated by a case study: an intelligent transport system-based scenario.
Analysis of Sheet Dimension (W, L) Dependence of NBTI in GAA-SNS FETs

Ultra-fast (Iuus delay) measured threshold voltage shift (ΔVT) due to Negative Bias Temperature Instability (NBTI) in Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs) having various length (L) and width (W) are analyzed. An enhanced, fully physical BTI Analysis Tool (BAT) is used to model the measured ΔVT stress-recovery kinetics at multiple stress bias (VGSTR) and temperature (T), with only four process dependent parameters. The impact of L and W scaling on ΔVT magnitude and its Voltage Acceleration Factor (VAF) is explained by considering variation in mechanical stress.