Magnetic modelling, analysis and on-chip shielding of SFQ Circuits

Single Flux Quantum (SFQ) based electronic circuits are susceptible to failure if exposed to external magnetic fields, even in very small quantities. Operating margins of SFQ circuits have shown to decrease significantly in the presence of magnetic fields as small as 5 μT. This challenge makes SFQ circuits infeasible for the normal environment in which other technologies, such as CMOS, operate. Sources of magnetic fields include SFQ circuit’s own bias lines, the Earth, which can produce magnetic fields up to 65 μT and any other electromagnetic interference sources. Without protective measures, most SFQ circuits cannot work in the open environment. By using the tools available in the inductance extraction tool, InductEx, a method for projecting uniform magnetic fields, of varying orientations on SFQ cells, strides have been made to make SFQ circuits more tolerant to magnetic fields. On-chip analysis of SFQ cells was done in the presence of magnetic fields from the x, y and z orientations. In addition, by varying currents in 3-D coils, the orientation of the magnetic fields can be varied. This way, it is now possible to analyse bias, parameter and operating field margins of SFQ cells in any direction of the magnetic field. Two on-chip shielding solutions were analysed and developed. The conventional continuous superconductor layer shield, dubbed the solid shield, and the grid shield. The grid shield resembles a Faraday cage and it is implemented by laying out bars of 2.5 μm width using the topmost layer in the Hypres′ 4.5 kA/cm2 process. The solid shield is more effective against perpendicular (z-directed) magnetic fields than against those in-plain (x and y-directed). In addition, the solid shield’s inclusion in SFQ cells results in the reduction of circuit inductance by up to 25 %. The grid shield is a very effective approach against in-plane magnetic fields. However, its effectiveness is inversely proportional to the spacing between grid bars. Compared to the solid shield, the grid shield has less effect on circuit inductance with a typical reduction of 8 % at a grid bar spacing of 5 μm. The large reduction in inductance can be overcome by making the inductors thinner and shorter. Shielding effectiveness of on-chip shields is enhanced by making ground contact vias from the shield layer to the ground plane. So far, uniformly grounded shields have shown to be the most effective approach. The solid shield improved the operating field margin of a DFF cell against a z-directed magnetic field from 30 μT to 531 μT, while the grid shield, of 5 μm grid spacing, improved the margins from 68 μT to 290 μT against an x-directed magnetic field. In the DC-SFQ cell, the operating field margin was improved with a solid shield from 47 μT to 464 μT, against a z-directed magnetic field, while with a grid shield, the improvement was from 211 μT to 381 μT, against an x-directed fields. To further enhance the magnetic field tolerance of SFQ circuits, design tenets that target specific components, such as inductors, were analysed. Thin and narrow inductors have shown less coupling to external magnetic fields. In addition, moats have shown to influence OFM results depending on the orientation of magnetic fields. This work has delivered design and analysis methods for magnetic field tolerant SFQ circuits. iii Stellenbosch University https://scholar.sun.ac.za