Enabling 3D Monolithic Integration

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (<30nm) has been investigated. Ge pre-amorphization was performed prior to boron implantation followed by a 600°C, 2min anneal. Fig.4 displays the sheet resistance Rs junction depth Xj trade-off dopants thanks to SPE. Excellent results are obtained that are in line with the most advanced annealing obtained for p-techniques (SPE, Laser, Flash) [2,3] on bulk and clearly outperform conventional RTP results. Furthermore HfO2 integration as gate dielectrics leads to an overall budget limited to 600°C. However at this temperature, the classical NiSi agglomerates, leading to a strongly increased sheet resistance and possible encroachement. To stabilise the silicide, an original treatment based on platinum incorporation associated with fluorine and tungsten implantation is proposed. Fig.5 clearly highlights the benefits of this NiSi treatment which ensure its stability at 650°C. In addition, bi-layer contact realisation can be performed with a single lithography step as shown in fig.6. Finally, equal lithography alignment performance for top and bottom layers have been obtained (tab.1), this implies that no additional enclosure is needed for contact design rules leading to high vertical connection density. As a conclusion, we have demonstrated the technological breakthroughs (low temperature WB with thin ILD, low temperature dopant activation using SPE and stabilisation of silicide) that enable to process high performance transistors on top and bottom layer without any detrimental impact of top transistor realisation thus settling the main drawback in 3D monolithic processing. Acknowledgements This work was supported by the French National Research Agency (ANR) through Carnot funding. References [1] Topol et al, IEDM 2005 / [2] Pouydebasque et al, ESSDERC 2005 / [3] Sugoro et al, IWJT 2004/ [4] Strane et al, VLSI TSA 2007