Miracle-dz/UniFAR-FTUs huggingface dataset:
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography

Post Exposure Baking (PEB) has been widely utilized in advanced lithography. PEB simulation is critical in the lithography simulation flow, as it bridges the optical simulation result and the final developed profile in the photoresist. The process of PEB can be described by coupled partial differential equations (PDE) and corresponding boundary and initial conditions. Recent years have witnessed growing presence of machine learning algorithms in lithography simulation, while PEB simulation is often ignored or treated with compact models, considering the huge cost of solving PDEs exactly. In this work, based on the observation of the physical essence of PEB, we propose DeePEB: a neural PDE Solver for PEB simulation. This model is capable of predicting the PEB latent image with high accuracy and >100 × acceleration (compared to the commercial rigorous simulation tool), paving the way for efficient and accurate photoresist modeling in lithography simulation and layout optimization.
Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips

The demand for low-power, high-performance neuromorphic chips is increasing. However, conventional testing is not applicable to neuromorphic chips due to three reasons: (1) lack of scan DfT, (2) stochastic characteristic, and (3) configurable functionality. In this paper, we present an automatic test configuration and pattern generation (ATCPG) method for testing a configurable stochastic neuromorphic chip without using scan DfT. We use machine learning to generate test configurations. Then, we apply a modified fast gradient sign method to generate test patterns. Finally, we determine test repetitions with statistical power of test. We conduct experiments on one of the neuromorphic architectures, spiking neural network, to evaluate the effectiveness of our ATCPG. The experimental results show that our ATCPG can achieve 100% fault coverage for the five fault models we use. For testing a 3-layer model at 0.05 significant level, we produce 5 test configurations and 67 test patterns. The average test repetitions of neuron faults and synapse faults are 2,124 and 4,557, respectively. Besides, our simulation results show that the overkill matched our significance level perfectly.
Re2fresh: A Framework for Mitigating Read Disturbance in ReRAM-based DNN Accelerators

A severe read disturbance problem degrades the inference accuracy of a resistive RAM (ReRAM) based deep neural network (DNN) accelerator. Refresh, which reprograms the ReRAM cells, is the most obvious solution for the problem, but programming ReRAM consumes huge energy. To address the issue, we first analyze the resistance drift pattern of each conductance state and the actual read stress applied to the ReRAM array by considering the characteristics of ReRAM-based DNN accelerators. Based on the analysis, we cluster ReRAM cells into a few groups for each layer of DNN and generate a proper refresh cycle for each group in the oﬄine phase. The individual refresh cycles reduce energy consumption by reducing the number of unnecessary refresh operations. In the online phase, the refresh controller selectively launches refresh operations according to the generated refresh cycles. ReRAM cells are selectively refreshed by minimally modifying the conventional structure of the ReRAM-based DNN accelerator. The proposed work successfully resolves the read disturbance problem by reducing 97% of the energy consumption for the refresh operation while preserving inference accuracy.
Compositional Verification Using a Formal Component and Interface Specification

Property-based specification such a s SystemVerilog Assertions (SVA) uses mathematical logic to specify the temporal behavior of RTL designs which can then be formally verified using model checking algorithms. These properties are specified for a single component (which may contain other components in the design hierarchy). Composing design components that have already been verified requires additional verification since incorrect communication at their interface may invalidate the properties that have been checked for the individual components. This paper focuses on a specification for their interface which can be checked individually for each component, and which guarantees that refinement-based properties checked f or each component continue to hold after their composition. We do this in the setting of the Instruction-level Abstraction (ILA) specification and verification methodology. The ILA methodology provides a uniform specification f or processors, a ccelerators and general modules at the instruction-level, and the automatic generation of a complete set of correctness properties for checking that the RTL model is a refinement o f t he ILA specification. We add an interface specification to model the inter-ILA communication. Further, we use our interface specification to generate a set of interface checking properties that check that the communication between the RTL components is correct. This provides the following guarantee: if each RTL component is a refinement of its ILA specification and the interface checks pass, then the RTL composition is a refinement of the ILA composition. We have applied the proposed methodology to six case studies including parts of large-scale designs such as parts of the FlexASR and NVDLA machine learning accelerators, demonstrating the practical applicability of our method.
Quantitative Verification and Design Space Exploration Under Uncertainty with Parametric Stochastic Contracts

This paper proposes an automated framework for quantitative verification and design space exploration of cyber-physical systems in the presence of uncertainty, leveraging assume-guarantee contracts expressed in Stochastic Signal Temporal Logic (StSTL). We introduce quantitative semantics for StSTL and formulations of the quantitative verification and design space exploration problems as bi-level optimization problems. We show that these optimization problems can be effectively solved for a class of stochastic systems and a fragment of bounded-time StSTL formulas. Our algorithm searches for partitions of the upper-level design space such that the solutions of the lower-level problems satisfy the upper-level constraints. A set of optimal parameter values are then selected within these partitions. We illustrate the effectiveness of our framework on the design of a multi-sensor perception system and an automatic cruise control system.
Double through‐transmission bulk wave method for ultrasonic phase velocity measurement and determination of elastic constants of composite materials

This paper describes a modification of a nondestructive ultrasonic method for measurements of the phase velocity of bulk waves in arbitrary directions in generally anisotropic materials. In the conventional method the through‐transmission technique is used for velocity measurements at a specified angle of incidence. When this angle is changed by rotation of the sample, the transmitted beam changes position, and so the position of the receiving transducer must be changed. This leads to experimental difficulties and loss of precision. In the double‐transmission technique, the ultrasonic wave is reflected from reflector plates behind the sample and returns via the same path to the same position on the transmitter/receiver working in pulse‐echo mode, which eliminates the necessity of readjusting the receiver position. It is also shown that for arbitrary direction of measurement in anisotropic materials, time‐delay measurements give phase velocity regardless of the angle of deviation between phase and group ve.
Workload-Balanced Graph Attention Network Accelerator with Top-K Aggregation Candidates

Graph attention networks (GATs) are gaining attention for various transductive and inductive graph processing tasks due to their higher accuracy than conventional graph convolutional networks (GCNs). The power-law distribution of real-world graph-structured data, on the other hand, causes a severe workload imbalance problem for GAT accelerators. To reduce the degradation of PE utilization due to the workload imbalance, we present algorithm/hardware co-design results for a GAT accelerator that balances workload assigned to processing elements by allowing only K neighbor nodes to participate in aggregation phase. The proposed model selects the K neighbor nodes with high attention scores, which represent relevance between two nodes, to minimize accuracy drop. Experimental results show that our algorithm/hardware co-design of the GAT accelerator achieves higher processing speed and energy eﬃciency than the GAT accelerators using conventional workload balancing techniques. Furthermore, we demonstrate that the proposed GAT accelerators can be made faster than the GCN accelerators that typically process smaller number of computations.
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning

Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement.
ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation

In this paper, we propose a reconfigurable processing-in-DRAM architecture named ReD-LUT leveraging the high density of commodity main memory to enable a flexible, general-purpose, and massively parallel computation. ReD-LUT supports lookup table (LUT) queries to efficiently execute complex arithmetic operations (e.g., multiplication, division, etc.) via only memory read operation. In addition, ReD-LUT enables bulk bit-wise in-memory logic by elevating the analog operation of the DRAM sub-array to implement Boolean functions between operands stored in the same bit-line beyond the scope of prior DRAM-based proposals. We explore the efficacy of ReD-LUT in two computationally-intensive applications, i.e., low-precision deep learning acceleration, and the Advanced Encryption Standard (AES) computation. Our circuit-to-architecture simulation results show that for a quantized deep learning workload, ReD-LUT reduces the energy consumption per image by a factor of 21.4× compared with the GPU and achieves ~37.8× speedup and 2.1× energy-efficiency over the best in-DRAM bit-wise accelerators. As for AES data-encryption, it reduces energy consumption by a factor of ~2.2× compared to an ASIC implementation.
A Robust Global Routing Engine with High-accuracy Cell Movement under Advanced Constraints

Placement and routing are typically defined as two separate problems to reduce the design complexity. However, such a divide-and-conquer approach inevitably incurs the degradation of solution quality due to the correlation/objectives of placement and routing are not entirely consistent. Besides, with various constraints (e.g., timing, R/C characteristic, voltage area, etc.) imposed by advanced circuit designs, bridging the gap between placement and routing while satisfying the advanced constraints has become more challenging. In this paper, we develop a robust global routing engine with high-accuracy cell movement under advanced constraints to narrow the gap and improve the routing solution. We first present a routing refinement technique to obtain the convergent routing result based on fixed placement, which provides more accurate information for subsequent cell movement. To achieve fast and high-accuracy position prediction for cell movement, we construct a lookup table (LUT) considering complex constraints/objectives (e.g., routing direction and layer-based power consumption), and generate a timing-driven gain map for each cell based on the LUT. Finally, based on the prediction, we propose an alternating cell movement and cluster movement scheme followed by partial rip-up and reroute to optimize the routing solution. Experimental results on the ICCAD 2020 contest benchmarks show that our algorithm achieves the best total scores among all published works. Compared with the champion of the ICCAD 2021 contest, experimental results on the ICCAD 2021 contest benchmarks show that our algorithm achieves better solution quality in shorter runtime.
Towards High Performance and Accurate BNN Inference on FPGA with Structured Fine-grained Pruning

As the extreme case of quantization networks, Binary Neural Networks (BNNs) have received tremendous attention due to many hardware-friendly properties in terms of storage and computation. To reach the limit of compact models, we attempt to combine binarization with pruning techniques, further exploring the redundancy of BNNs. However, coarse-grained pruning methods may cause server accuracy drops, while traditional fine-grained ones induce irregular sparsity hard to be utilized by hardware. In this paper, we propose two advanced fine-grained BNN pruning modules, i.e., structured channel-wise kernel pruning and dynamic spatial pruning, from a joint perspective of algorithm and hardware. The pruned BNN models are trained from scratch and present not only a higher precision but also a high degree of parallelism. Then, we develop an accelerator architecture that can effectively exploit the sparsity caused by our algorithm. Finally, we implement the pruned BNN models on an embedded FPGA (Ultra96v2). The results show that our software and hardware codesign achieves 5.4x inference-speedup than the baseline BNN, with higher resource and energy efficiency compared with prior FPGA implemented BNN works.
WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning

As the demand for semiconductor products increases and the integrated circuits (IC) processes become more and more complex, wafer failure pattern classification is gaining more attention from manufacturers and researchers to improve yield. To further cope with the real-world scenario that there are only very limited labeled data and without any unlabeled data in the early manufacturing stage of new products, this work proposes an efficient human-like staged learning framework for wafer failure pattern classification named WaferHSL. Inspired by human’s knowledge acquisition process, a mutually reinforcing task fusion scheme is designed for guiding the deep learning model to simultaneously establish the knowledge of spatial relationships, geometry properties and semantics. Furthermore, a progressive stage controller is deployed to partition and control the learning process, so as to enable human-like progressive advancement in the model. Experimental results show that with only 10% labeled samples and no unlabeled samples, WaferHSL can achieve better results than previous SOTA methods trained with 60% labeled samples and a large number of unlabeled samples, while the improvement is even more significant when using the same size of labeled training set.
MiR-1236-3p Inhibits the Proliferation, Invasion, and Migration of Colon Cancer Cells and Hinders Epithelial-Mesenchymal Transition by Targeting DCLK3

Background Dysregulated microRNAs (miRNAs) are common in human cancer and are involved in the proliferation, promotion, and metastasis of tumor cells. Therefore, this study aimed to evaluate the expression and biological function of miR-1236-3p in colon cancer. Methods This study screened the miRNA in normal and colon cancer tissues through array analysis. In addition, quantitative Reverse Transcription–Polymerase Chain Reaction (qRT-PCR) analysis was performed to validate the expression of miR-1236-3p in normal and tumor tissues from colon cancer patients and cancer cell lines. Online predicting algorithms and luciferase reporter assays were also employed to confirm Doublecortin Like Kinase 3 (DCLK3) was the target for miR-1236-3p. Moreover, the impact of miR-1236-3p on the progression of colon cancer was evaluated in vitro and in vivo. Western blotting and qRT-PCR were also performed to investigate the interactions between miR-1236-3p and DCLK3. Results MiR-1236-3p was significantly downregulated in colon cancer tissues and its expression was associated with the TNM stage and metastasis of colon. In addition, the in vitro and in vivo experiments showed that miR-1236-3p significantly promoted cancer cell apoptosis and inhibited the proliferation, invasion, and migration of cancer cells. The results also showed that miR-1236-3p hindered Epithelial–mesenchymal Transition (EMT) by targeting DCLK3. Moreover, the expression of DCLK3 mediated the effects of miR-1236-3p on the progression of cancer. Conclusions MiR-1236-3p functions as a tumor suppressor in colon cancer by targeting DCLK3 and is therefore a promising therapeutic target for colon cancer.
Two-dimensional, finite-difference method of solving the Dirac equation for diatomic molecules revisited

Two-dimensional, fully numerical, finite-difference approach to the second-order Dirac equation for one-electron diatomics is revisited. Instead of using the transformation of variables to get rid of the singularities of σ-type spinors the Gaussian nuclear charge distribution model is employed. The approach is tested on the several lowest σ, π, δ and φ states of H, Kr and Th systems with the reference data of 12-digit accuracy provided by the GRASP and QRHF atomic codes. The method is also tested on H , Kr and Th systems. The energies of and states of H are converged to 9 significant figures and the relativistic correction to 6. In the case of the Th system the calculations for the state were performed for a range of internuclear separations a.u. and compared with the eXact 2-Component (X2C) and 4-component results. The agreement to within 1 milihartree or better is observed for all the separations greater than 0.2 a.u. Alas, the orbital energy of the system with a.u. , could only be calculated with 0.1% accuracy. This problem also seems to haunt Sundholm's implementation of the method and we indicate the reasons behind the low accuracy at extremely short internuclear distances. GRAPHICAL ABSTRACT
Human mutations in SLITRK3 implicated in GABAergic synapse development in mice

We report on biallelic homozygous and monoallelic de-novo variants in SLITRK3 in 3 unrelated families presenting with epileptic encephalopathy associated with a broad neurological involvement characterized by microcephaly, intellectual disability, seizures, and global developmental delay. SLITRK3 encodes for a transmembrane protein that is involved in controlling neurite outgrowth and inhibitory synapse development and that has an important role in brain function and neurological diseases. Using primary cultures of hippocampal neurons carrying patients’ SLITRK3 variants and in combination with electrophysiology, we demonstrate that recessive variants are loss-of-function alleles. By analyzing the development and phenotype of SLITRK3 KO (SLITRK3-/-) mice, we bring additional evidence of enhanced susceptibility to pentylenetetrazole-induced seizure with the appearance of spontaneous epileptiform EEG, as well as developmental deficits such as higher motor activities and reduced parvalbumin interneurons. Taken together, our results exhibit impaired development of peripheral and central nervous system and support a conserved role of this transmembrane protein in neurological function. Our study delineates an emerging spectrum of human core synaptopathies caused by variants in genes that encode SLITRK proteins and essential regulatory components of the synaptic machinery. The hallmark of these disorders is impaired postsynaptic neurotransmission at nerve terminals; an impaired neurotransmission resulting in a wide array of (often overlapping) clinical features, including neurodevelopmental impairment, weakness, seizures, and abnormal movements. The genetic synaptopathy caused by SLITRK3 mutations highlights the key roles of this gene in human brain development and function.
Intramolecular autoinhibition of human PEX13 modulates peroxisomal import

Targeting and import of peroxisomal proteins depends on PEX5, PEX14 and PEX13. We present a biochemical and structural characterization of the PEX13 C-terminal region. By combining NMR spectroscopy, X-ray crystallography and biochemical methods, we show that the PEX13 SH3 domain mediates intramolecular interactions with a newly identified proximal FxxxF motif and also binds to WxxxF peptide motifs from the PEX5 NTD, demonstrating evolutionary conservation of this interaction from yeast to human. Strikingly, the C-terminal FxxxF motif autoinhibits the WxxxF/Y binding surface on the PEX13 SH3 domain. This is supported by high-resolution crystal structures, which show FxxxF or WxxxF/Y binding to the same, non-canonical surface on the SH3 domain. The FxxxF motif also binds the PEX14 NTD with micromolar affinity. Surprisingly, the canonical binding surface for PxxP motifs on the human PEX13 SH3 fold does not recognize PxxP motifs in PEX14, distinct from the yeast ortholog. The dynamic network of PEX13, PEX14 and PEX5 interactions mediated by diaromatic peptide motifs fine-tunes and modulates peroxisomal matrix import in cells.
Dynamics and maintenance of categorical responses in primary auditory cortex during task engagement

Grouping sets of sounds into relevant categories is an important cognitive ability that facilitates the association of stimuli with appropriate goal-directed behavioral responses. In perceptual tasks, a prominent role of primary auditory cortex (A1) is to multiplex the encoding of sound sensory features and task variables. Here we investigated the involvement of A1 in initiating sound categorization. We trained ferrets to discriminate click trains of different rates in a Go/No-Go delayed categorization task and recorded neural activity during both active behavior and passive exposure to the same sounds. Purely categorical response components were extracted and analyzed separately from sensory responses to reveal their contributions to the overall population response throughout the trials. We found that population-level representation of Go/No-Go behavioral categories emerged during sound presentation and was present in both active behavioral and passive states. However, upon task engagement, categorical responses to the No-Go category became suppressed, leading to an asymmetrical representation of the Go stimuli relative to the No-Go sounds and prestimulus baseline. At stimulus offset, the population code changed abruptly but categorical representation was maintained during the delay period. Categorical responses extracted from the stimulus period correlated with the ones found in the delay epoch, suggesting an early contribution of A1 to stimulus categorization.