An Energy Efficient EdgeAI Autoencoder Accelerator for Reinforcement Learning

In EdgeAI embedded devices that exploit reinforcement learning (RL), it is essential to reduce the number of actions taken by the agent in the real world and minimize the compute-intensive policies learning process. Convolutional autoencoders (AEs) has demonstrated great improvement for speeding up the policy learning time when attached to the RL agent, by compressing the high dimensional input data into a small latent representation for feeding the RL agent. Despite reducing the policy learning time, AE adds a significant computational and memory complexity to the model which contributes to the increase in the total computation and the model size. In this article, we propose a model for speeding up the policy learning process of RL agent with the use of AE neural networks, which engages binary and ternary precision to address the high complexity overhead without deteriorating the policy that an RL agent learns. Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs) compress weights into 1 and 2 bits representations, which result in significant compression of the model size and memory as well as simplifying multiply-accumulate (MAC) operations. We evaluate the performance of our model in three RL environments including DonkeyCar, Miniworld sidewalk, and Miniworld Object Pickup, which emulate various real-world applications with different levels of complexity. With proper hyperparameter optimization and architecture exploration, TNN models achieve near the same average reward, Peak Signal to Noise Ratio (PSNR) and Mean Squared Error (MSE) performance as the full-precision model while reducing the model size by <inline-formula> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> compared to full-precision and <inline-formula> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> compared to BNNs. However, in BNN models the average reward drops up to 12% – 25% compared to the full-precision even after increasing its model size by <inline-formula> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula>. We designed and implemented a scalable hardware accelerator which is configurable in terms of the number of processing elements (PEs) and memory data width to achieve the best power, performance, and energy efficiency trade-off for EdgeAI embedded devices. The proposed hardware implemented on Artix-7 FPGA dissipates <inline-formula> <tex-math notation="LaTeX">$250~\mu \text{J}$ </tex-math></inline-formula> energy while meeting 30 frames per second (FPS) throughput requirements. The hardware is configurable to reach an efficiency of over 1 TOP/J on FPGA implementation. The proposed hardware accelerator is synthesized and placed-and-routed in 14 nm FinFET ASIC technology which brings down the power dissipation to <inline-formula> <tex-math notation="LaTeX">$3.9~\mu \text{J}$ </tex-math></inline-formula> and maximum throughput of 1,250 FPS. Compared to the state of the art TNN implementations on the same target platform, our hardware is <inline-formula> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$4.4\times $ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$2.2\times $ </tex-math></inline-formula> if technology scaled) more energy efficient on FPGA and ASIC, respectively.