Miracle-dz/UniFAR-FTUs huggingface dataset:
QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy

A 10+K qubit Quantum-Classical Interface (QCI) is essential to realize the quantum supremacy. However, it is extremely challenging to architect scalable QCIs due to the complex scalability trade-offs regarding operating temperatures, device and wire technologies, and microarchitecture designs. Therefore, architects need a modeling tool to evaluate various QCI design choices and lead to an optimal scalable QCI architecture. In this paper, we propose (1) QIsim, an open-source QCI simulation framework, and (2) novel architectural optimizations for designing 10+K qubit QCIs toward quantum supremacy. To achieve the goal, we first implement detailed QCI microarchitectures to model all the existing temperature and technology candidates. Next, based on the microarchitectures, we develop our scalability-analysis tool (QIsim) and thoroughly validate it using previous works, post-layout analyses, and real quantum-machine experiments. Finally, we successfully develop our 60,000+ qubit-scale QCI designs by applying eight architectural optimizations driven by QIsim.
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes

Microarchitectural side-channels enable an attacker to exfiltrate information via the observable side-effects of a victim's execution. Obfuscating mitigation schemes have recently gained in popularity for their appealing performance characteristics. These schemes, including randomized caches and DRAM traffic shapers, limit, but do not completely eliminate, side-channel leakage. An important (yet under-explored) research challenge is the quantitative study of the security effectiveness of these schemes, identifying whether these obfuscating schemes help increase the security level of a system, and if so, by how much. In this paper, we address this research challenge by presenting Metior, a comprehensive model to quantitatively evaluate the effectiveness of obfuscating side-channel mitigations. Metior offers a way to reason about the flow of information through obfuscating schemes. Metior builds upon existing information theoretic approaches, allowing for the comprehensive side-channel leakage evaluation of active attackers, real victim applications, and state-of-the-art microarchitectural obfuscation schemes. We demonstrate the use of Metior in the concrete leakage evaluation of three microarchitectural obfuscation schemes (fully-associative random replacement caches, CEASER-S, and Camouflage), identifying unintuitive leakage behaviours across all three schemes.
Comparative Evaluation of Different Lactation Curve Models in Prediction of Monthly Test-Day Milk Yields in Murrah Buffaloes

Present investigation was undertaken to compare the different lactation curve models for describing the shape of the lactation curve in Murrah buffaloes. Data for the present study included 9071 monthly test-day milk yield (MTDMY) from 965 Murrah buffaloes calved during 1977 to 2012 at the National Dairy Research Institute, Karnal. A total of 10 monthly test-day milk yield records were taken at an interval of 30 days. The data were used to estimate lactation curve parameters for four lactation curve models viz. Gamma type function (GF), Exponential function (EF), Mixed log function (MLF) and Polynomial regression function (MLF). The mean monthly test day milk yields (MTDMY) increased from 5.91±0.13 kg on TD1 to a peak yield of 7.41±0.12 kg on TD3. The estimates of coefficient of determination (R2) and root mean square error (RMSE) for GF, EF, MLF, and PRF were 96.42%, 98.65%, 98.48%, 99.86% and 0.077, 0.049, 0.052, 0.015, respectively. PRF fitted best to the test day data followed by EF on the basis of higher R2 and lower RMSE estimates, whereas GF fitted least.
A Survey of Design and Optimization for Systolic Array-based DNN Accelerators

In recent years, it has been witnessed that the systolic array is a successful architecture for DNN hardware accelerators. However, the design of systolic arrays also encountered many challenges. As DNN structures and applications become more complex, a DNN hardware accelerator based on the typical systolic array architecture suffers severe performance and efficiency penalties. So, it has motivated a significant amount of research on the redesign and optimization of the systolic array architecture. In this article, we survey these works on analyzing, redesigning, and improving the performance and efficiency of the systolic array architecture. These works are critical to the design flow of DNN accelerators based on systolic arrays. We also provide a technique classification of these works on the basis of their main research idea. Further, we attempt to compare the advantages and disadvantages of different designs and different technologies and provide quantitative results for reference. The aim of this survey is to provide researchers with knowledge of the state-of-the-art in the systolic array architecture and motivate them to design highly efficient DNN accelerators of tomorrow.
Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes

Speculative side-channel attacks have forced computer architects to rethink speculative execution. Effectively preventing microarchitectural state from leaking sensitive information will be a key requirement in future processor design. An important limitation of many secure speculation schemes is a reduction in the available memory parallelism, as unsafe loads (depending on the particular scheme) are blocked, as they might potentially leak information. Our contribution is to show that it is possible to recover some of this lost memory parallelism, by safely predicting the addresses of these loads in a threat-model transparent way, i.e., without worsening the security guarantees of the underlying secure scheme. To demonstrate the generality of the approach, we apply it to three different secure speculation schemes: Non-speculative Data Access (NDA), Speculative Taint Tracking (STT), and Delay-on-Miss (DoM). An address predictor is trained on non-speculative data, and can afterwards predict the addresses of unsafe slow-to-issue loads, preloading the target registers with speculative values, that can be released faster on correct predictions than starting the entire load process. This new perspective on speculative execution encompasses all loads, and gives speedups, separately from prefetching. We call the address-predicted counterparts of loads Doppelganger Loads. They give notable performance improvements for the three secure speculation schemes we evaluate, NDA, STT, and DoM. The Doppelganger Loads reduce the geometric mean slowdown by 42%, 48%, and 30% respectively, as compared to an unsafe baseline, for a wide variety of SPEC2006 and SPEC2017 benchmarks. Furthermore, Doppelganger Loads can be efficiently implemented with only minor core modifications, reusing existing resources such as a stride prefetcher, and most importantly, requiring no changes to the memory hierarchy outside the core.
Sets Expressible as Unions of Staircase n-Convex Polygons

Let k and n be fixed, k ≥ 1, n ≥ 1 ,a nd letS be a simply connected orthogonal polygon in the plane. For T ⊆ S, T lies in a staircase n-convex orthogonal polygon P in S if and only if every two points of T see each other via staircase n-paths in S. This leads to a characterization for those sets S expressible as a union of k staircase n-convex polygons Pi, 1 ≤ i ≤ k.
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC

Memory safety is a major security concern for unsafe programming languages, including C/C++ and CUDA/OpenACC. Hardware-accelerated memory tagging is an effective mechanism for detecting memory safety violations; however, its adoption is challenged by significant meta-data storage and memory traffic overheads. This paper proposes Implicit Memory Tagging (IMT), a novel approach that provides no-overhead hardware-accelerated memory tagging by leveraging the system error correcting code (ECC) to check for the equivalence of a memory tag in addition to its regular duties of detecting and correcting data errors. Implicit Memory Tagging relies on a new class of ECC codes called Alias-Free Tagged ECC (AFT-ECC) that can unambiguously identify tag mismatches in the absence of data errors, while maintaining the efficacy of ECC when data errors are present. When applied to GPUs, IMT addresses the increasing importance of GPU memory safety and the costs of adding meta-data to GPU memory. Ultimately, IMT detects memory safety violations without meta-data storage or memory access overheads. In practice, IMT can provide larger tag sizes than existing industry memory tagging implementations, enhancing security.
Decoupled SSD: Rethinking SSD Architecture through Network-based Flash Controllers

Modern NAND Flash memory-based Solid State Drives (SSDs) are designed to provide high-bandwidth for I/O requests through high-speed NVMe interface and increased internal flash memory bandwidth. In addition to providing high performance for incoming I/O requests, the flash translation layer (FTL) also handles other flash memory management processes including garbage collection that can negatively impact I/O performance. In this work, we address how the sharing of system resources (e.g., system-bus and DRAM) for I/O requests and garbage collection can cause interference and performance degradation. In particular, we propose to rethink SSD architecture through a Decoupled SSD (dSSD) system that decouples the front-end (i.e. cores, system-bus, DRAM) with the back-end (i.e. flash memory). A flash-controller network-on-chip (fNoC) that interconnects the flash controllers together is introduced to enable decoupling of the I/O path and garbage collection path to improve performance and reliability. dSSD enables advanced commands such as copyback command to be exploited for efficient garbage collection and we propose to extend copyback command with global copyback through the fNoC. To improve reliability, we propose to recycle superblocks through superblock recycle table within the flash controller. Without any modification to the FTL, a hardware-based offloading mechanism within the flash controller of the dSSD is proposed to dynamically re-organize a superblock. Our evaluations show that decoupled SSD results in up to 42.7% I/O bandwidth improvement and 63.8% GC performance improvement, while achieving approximately 31.4× improvement in tail-latency on average. Dynamic superblock management through the dSSD results in approximately 23% improvement in lifetime with minimal impact on performance and cost.
Business students’ experiences, perceptions, and motivations toward business research and information literacy: Ideas for better library practices

Abstract Based on a business student survey, this article explores students’ experiences, perceptions, attitudes, and motivation toward learning business information literacy (IL) skills. The survey received 413 responses and investigated topics including most encountered research tasks, use of research tools, most experienced feelings, self-rated research competencies, perceived research importance, interest to learn more, research scenarios, challenges, preferred learning settings and learning modes, motivational factors, the time commitment for learning, and preferred quality of a learning module. Incorporating students’ suggestions on improving their IL skills, the article proposes to create six dynamic learning opportunities for students and shares ideas for realizing these opportunities through collaboration, integration, and experimentation.
Factors affecting cross-language activation and language mixing in bilingual aphasia: A case study

ABSTRACT Background Some bilinguals with aphasia tend to mix languages within a single utterance. Two opposing views attribute this to difficulty with either language control or word retrieval. Aims This study investigated the influence of factors that increase activation of the non-target language on the occurrence of language mixing errors. This increased activation predicts more language mixing errors if there is a language control issue, but not if they stem from word retrieval difficulties. Methods and procedures A picture naming experiment was conducted with a bilingual individual with aphasia who showed language mixing. We investigated the influence of four factors likely to influence activation of representations of the non-target language on response accuracy, response latency and the occurrence of language selection errors: language, language mode, task, and phonological overlap between the target word and its translation equivalent. Outcomes and results The increased activation of the non-target language induced by language mode, task and phonological overlap with the translation equivalent did not lead to an increase in language selection errors when compared to correct responses. This is despite the fact that these factors affected accuracy and response latency, in the direction that is expected in unimpaired bilingual performance. Conclusions Results were not consistent with a disruption of the cognitive control needed to respond in the intended language. Instead, they highlight that language mixing in this individual, rather than being “pathological”, is instead used as a strategy to potentially improve communication when lexical retrieval difficulties occur. Language mixing behaviours in aphasia may not be due to issues of control and have a communicative value that should be recognised.
Student empowerment for internationalisation at a distance: enacting the students as partners approach in virtual mobility

ABSTRACT The popularisation of virtual mobility offers opportunities to reconsider power imbalances among different actors in higher education and to affirm the centrality of student agency and diversity. This article explores possibilities for applying the Students as Partners (SaP) approach to virtual mobility in order to empower students and foster reciprocal and ethical interactions. Drawing on interviews with students involved in an action research project, the article highlights the roles and perspectives of students in formulating authentic intercultural exchange experiences online. The findings suggest that application of the SaP framework reorganises students’ agentic capacities and allows them to flourish in a way which, in turn, shifts the power balance in international learning and contributes to the ongoing re-configuration of approaches to internationalisation beyond the educator/student binary.
Characterizing the Emotional Context Induced by Music Listening and its Effects on Gait Initiation: Exploiting Physiological and Biomechanical Data

The ability to initiate gait involves a complex coordination between posture and movement, known as anticipatory postural adjustments (APAs). The emotional context in which gait initiation occurs can impact several spatio-temporal parameters, particularly the duration of APAs. While previous studies have used biologically relevant stimuli to induce emotions, such as images of pleasant or unpleasant scenes, to the best of our knowledge, the impact of the emotional context induced by music on gait initiation has not been explored yet. This paper presents a new dataset collected to study this impact. Objective biomechanical and physiological data were collected from participants during and after music listening, and subjective emotional responses were assessed using questionnaires. We also focused on two factors, liking judgment and familiarity, known to modulate emotions. Our preliminary analyses shows the impact of the emotional context induced by music on gait initiation, and confirms the strong importance of liking judgment and familiarity on the emotional context.
DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory

Memory disaggregation is a promising solution to scale memory capacity and bandwidth shared by multiple server nodes in a flexible and cost-effective manner. DRAM power consumption, which is reported to be around 40% of the total system power in the datacenter server, will become an even more serious concern in this high-capacity environment. Exploiting the low average utilization of DRAM capacity in today's datacenters, it is appealing to put unallocated/cold DRAM ranks into a power-saving mode. However, the conventional DRAM address mapping with fine-grained interleaving to maximize rank-level parallelism is incompatible with such rank-level DRAM power management techniques. Furthermore, existing DRAM power-saving techniques often require intrusive changes to the system stack, including OS, memory controller (MC), or even DRAM devices, to pose additional challenges for deployment. Thus, we propose DRAM Translation Layer (DTL) for host software/MC-transparent DRAM power management with commodity DRAM devices. Inspired by Flash Translation Layer (FTL) in modern SSDs, DTL is placed in the CXL memory controller to provide (i) flexible address mappings between host physical address and DRAM device physical address and (ii) host-transparent memory page migration. Leveraging DTL, we propose two DRAM power-saving techniques with different temporal granularities to maximize the number of DRAM ranks that can enter low-power states while provisioning sufficient DRAM bandwidth: rank-level power-down and hotness-aware self-refresh. The first technique consolidates unallocated memory pages into a subset of ranks at deallocation of a virtual machine (VM) and turns them off transparently to both OS and host MC. Our evaluation with CloudSuite benchmarks demonstrates that this technique saves DRAM power by 31.6% on average at a 1.6% performance cost. The hotness-aware self-refresh scheme further reduces DRAM energy consumption by up to 14.9% with negligible performance loss via opportunistically migrating cold pages into a rank and making it enter self-refresh mode.
Implicit motor adaptation patterns in a redundant motor task manipulating a stick with both hands

The remarkable ability of the motor system to adapt to novel environments has traditionally been investigated using kinematically non-redundant tasks, such as planar reaching movements. Due to this limitation, it remains poorly understood how the motor system achieves adaptation by altering the movement patterns of our redundant body. To address this issue, we developed a redundant motor task in which participants reached for targets with the tip of a virtual stick held with both hands. Despite the redundancy of the task, participants consistently employed a stereotypical strategy of flexibly changing the tilt angle of the stick depending on the direction of tip movement. Thus, this baseline relationship between tip-movement direction and stick-tilt angle constrained both the physical and visual movement patterns of the redundant system. Our task allowed us to systematically investigate how the motor system implicitly changed both the tip-movement direction and the stick-tilt angle in response to imposed visual perturbations. Both types of perturbations, whether directly affecting the task (tip-movement direction) or not (stick-tilt angle around the tip), drove adaptation, and the patterns of implicit adaptation were guided by the baseline relationship. Consequently, tip-movement adaptation was associated with changes in stick-tilt angle, and intriguingly, even seemingly ignorable stick-tilt perturbations significantly influenced tip-movement adaptation, leading to tip-movement direction errors. These findings provide a new understanding that the baseline relationship plays a crucial role not only in how the motor system controls movement of the redundant system, but also in how it implicitly adapts to modify movement patterns.
PTEase: Objective Airway Examination for Pulmonary Telemedicine using Commodity Smartphones

Remote monitoring and evaluation of pulmonary diseases via tele-medicine are important to disease diagnosis and management, but current telemedicine solutions have limited capability of objectively examining the airway's internal physiological conditions that are crucial to pulmonary disease evaluation. Existing solutions based on smartphone sensing are also limited to externally monitoring breath rates, respiratory events, or lung function. In this paper, we present PTEase, a new system design that addresses these limitations and uses commodity smartphones to examine the airway's internal physiological conditions. PTEase uses active acoustic sensing to measure the internal changes of lower airway caliber, and then leverages machine learning to analyze the sensory data for pulmonary disease evaluation. We implemented PTEase as a smartphone app, and verified its measurement error in lab-controlled settings as <10%. Clinical studies further showed that PTEase reaches 75% accuracy on disease prediction and 11%-15% errors in estimating lung function indices. Given that such accuracy is comparable with that in clinical practice using spirometry, PTEase can be reliably used as an assistive telemedicine tool for disease evaluation and monitoring.
RAVER1 interconnects lethal EMT and miR/RISC activity by the control of alternative splicing

The RAVER1 protein was proposed to serve as a co-factor in guiding the PTBP-dependent control of alternative splicing (AS). Whether RAVER1 solely acts in concert with PTBPs and how it affects cancer cell fate remained elusive. Here we provide the first comprehensive investigation of RAVER1-controlled AS in cancer cell models and reveal a pro-oncogenic role of RAVER1 in tumor growth. This unravels that RAVER1 guides AS in synergy with PTBPs but more prominently serves PTBP1-independent roles in splicing. In cancer cells, one major function of RAVER1 is the control of proliferation and apoptosis, which involves the modulation of AS events within the miR/RISC pathway. Associated with this regulatory role, RAVER1 antagonizes lethal, TGFB-driven epithelial-mesenchymal-transition (EMT) by limiting TGFB signaling. RAVER1-modulated splicing events affect the insertion of protein interaction modules in factors guiding miR/RISC-dependent gene silencing. Most prominently, in all three human TNRC6 proteins, RAVER1 controls AS of GW-enriched motifs, which are essential for AGO2-binding. Disturbance of RAVER1-guided AS events in TNRC6 proteins and other facilitators of miR/RISC activity compromise miR/RISC activity which is essential to restrict TGFB signaling and lethal EMT.
Musashi-2 (MSI2) regulation of DNA damage response in lung cancer

Lung cancer is one of the most common types of cancers worldwide. Non-small cell lung cancer (NSCLC), typically caused by KRAS and TP53 driver mutations, represents the majority of all new lung cancer diagnoses. Overexpression of the RNA-binding protein (RBP) Musashi-2 (MSI2) has been associated with NSCLC progression. To investigate the role of MSI2 in NSCLC development, we compared the tumorigenesis in mice with lung-specific Kras-activating mutation and Trp53 deletion, with and without Msi2 deletion (KP versus KPM2 mice). KPM2 mice showed decreased lung tumorigenesis in comparison with KP mice what supports published data. In addition, using cell lines from KP and KPM2 tumors, and human NSCLC cell lines, we found that MSI2 directly binds ATM/Atm mRNA and regulates its translation. MSI2 depletion impaired DNA damage response (DDR) signaling and sensitized human and murine NSCLC cells to treatment with PARP inhibitors in vitro and in vivo. Taken together, we conclude that MSI2 supports lung tumorigenesis, in part, by direct positive regulation of ATM protein expression and DDR. This adds the knowledge of MSI2 function in lung cancer development. Targeting MSI2 may be a promising strategy to treat lung cancer. Significance This study shows the novel role of Musashi-2 as regulator of ATM expression and DDR in lung cancer.