Model-Based Program Debugging and Repair

Mo del-BasedProgramDebuggingandRepairMarkusStumptnerandFranzWotawaChristianDopplerLab oratoryforExp ertSystemsInstitutf urInformationssysteme,TechnischeUniversitatWienPaniglgasse16,1040Wien,Austria,Europ eEmail:fmst,wotawag@dbai.tuwien. ac.atAbstractThecurrentstateoftheartintegratedcircuitde-signisbasedontheuseofsp ecialhardwaredesignlanguagessuchasVHDL.Inthecontextofdevel-opmentofanintelligent,knowledge-baseddebuggingaidforVHDLprograms,wearedealingwithanalysisanddiagnosisofasubsetVHDL(whichissimilartoconventionalconcurrentprogramminglanguages). Wepresentanadaptationofconventionalmo del-baseddiagnosismetho dstothedebuggingofVHDLexpres-sionsandsignalassignments.Theexaminationofp os-siblefaultsinVHDLexpressionsleadstotheuseoffaultmo dels(i.e.,arepresentationoftypicalerrors)asanaidtofo cusing,andabasisforprop osingrepairactionsforsmallerrorsintheseprograms.1Intro ductionOverthelastdecade,mo del-basedapproachhasachievedwidespreaduseinhardwarediagno-sis[Rei87,dKW87]. Whilemo del-basedtechniqueshavealsofoundrecognitioninthe eldofdesigngeneral[Wil90],theirapplicationtosoftwaredesigninparticularhasremainedverylimited.Inmorere-centyears,di erenauthorshaveexaminedtheuseofmo del-baseddiagnosisfordebugginglogicpro-grams[CFD93],buttheire ortswerelimitedtosmallexamples.Theworkdescrib edinthispap erattemptstoextendthisbasiswardsamoregenerallyusableapproachfordiagnosingsoftware,whicisnotlim-itedtotheparticularlyb enevolentenvironmenofpurelogicprogramminglanguages,andalsoscalesuptomeaningfulerrorsearchinprogramsofamorerealis-ticsize.IntheDDV(DesignDiagnosisforVHDL)pro ject,Thisworkasco-sp onsoredbytheChristianDopplerLab-oratoryforExp ertSystemsandSiemensAustriatheauthorshaveappliedmo del-baseddiagnosistodebuggingofhardwaredesignswrittenintheVHDLlanguage[FSW95]. Hardwaresp eci cationlanguagessuchasVHDL(anIEEEstandardandthemostwide-spreadsuchlanguageincurrentuse)combinethesyn-taxandexpressivenessofafullconventionalprogram-minglanguagewithsp ecialparallelconstructs(tosim-ulatetheconcurrentinternalworkingsoftegratedcircuits),datatyp es(e.g.,themultivaluedlogicsusedbycircuitdesignerstodescrib edi erentstatesofsig-nallines). VHDLdevelopmentenvironmentsaredeliv-eredtogetherwithlargelibrariescontainingprede nedstandardcircuits,suchasthelogicalgatetyp es.Themainreasonfortheuseofdesignlanguagesistheattempttoavoid,bywhatevermeansp ossible,thesurfacingofdesignerrorsafteralotmoneyhasb eensp entonpro ductionofthe rstprototyp esb oardorchip.Circuitdesignsaresuccessivelyre nedtoadegreewheretheycanb eautomaticallytrans-formed("synthesized")intothe nalgate-levelrepre-sentation.Largehardwaredesigns(comprisingmulti-pleASIC'sandmicropro cessors)canreachdimensionsofseveral100.000linesVHDLco deandthousandsofcomp onentsandsignalsatthetoplevel.Forsuchdesigns,typicallywrittenbyalargeteamofdesign-ers,testing,faultdetectionandlo calizationb ecomeverytime-consumingactivities,b ecausetheyinolvesimulationsofanactualcircuitthatcantakehoursordays,scanningoftheresultingsignaltracesbyhand,andsubsequentidenti cationoftheerrorinalargeprogrampartsofwhichmayhaveb eenpro ducedboutsidesub contractors.Ine ect,thesedesignspresentalltheproblemsofsoftwaredebuggingwithad-ditionalproblemthattestrunsandactual ndingofmisb ehaviortakealotofmanp owerandrealtime.Anautomatedassistantforfault- ndingthuspresentsthep ossibilityforma jorcostsavingsinthedesignpro cess.Theto oldevelop edintheDDVpro jectisusedfortestinganddiagnosingpurp oses.Thetrace lespro-1