Synergism between single event effects and total ionising dose.

The space industry is continuing to use commercial off the shelf (COTS) devices in satellites where the ionising radiation environment poses a threat. For device qualification, their single event effects (SEE) and total ionising dose (TID) performances are normally assessed separately. However, it has been shown that there can be a synergistic relationship in static random-access memory (SRAM) between TID and SEEs, where by the single event upset (SEU) cross section increases with dose, with some devices showing a significant increase for doses less than those seen by low earth orbit (LEO) satellites. The mechanism behind this effect in older SRAM technologies is believed to be due to threshold voltage shift imbalances of the nMOS transistors of the cross coupled inverter within the cell. This is due to variations in the build up of trapped charge in the nMOS transistors when they are ON or OFF. This degrades the noise threshold of the cell making it more susceptible to upsets when holding the opposite state to which it was irradiated in. For more modern devices the gate oxide is too thin to hold enough trapped charge to cause a significant change in threshold voltage. The mechanism for these modern SRAMs is based on the potential between the gate of the ON nMOS transistor and its substrate, in this situation fringing fields are at their strongest ushering the charge created by ionising radiation towards the boundary of the field oxide and the gate channel. It is at this boundary that a significant amount of trapped charge can create a parasitic leakage current between the transistor's source and drain. This parasitic leakage current then reduces the voltage seen at its drain and hence degrades the cell's noise threshold. The main goal of this work is to determine if these mechanisms behind synergy still have a significant affect on the SEU cross section of modern six transistor (6T) SRAMs built on the 180 and 130 nm fabrication processes. Other non-volatile memory devices have also been tested to see if their memory cell or complex CMOS peripheral circuitry suffer any synergistic effects such as an increase in single event functional interrupt (SEFI) or single event latchup (SEL) with increasing dose. To do this test boards containing the devices were irradiated with Co-60 gamma-rays to 5, 10, 15, 25 krads. These boards, as well as the control group test boards, were then taken to be tested with 23.5, 60.9, 151 and 230 MeV protons to determine the SEE response of the various parts. To help assess these devices a highly adaptable test system was developed consisting of high level control software and a control board. The high level software offers an over-view of key data such as the device under test's (DUT) current consumption, SEFI and SEL notifications and a preview of the incoming results. The control board is based around Texas Instrument's microcontroller, the TMS570, and is capable of testing both serial and parallel devices while offering latchup protection via a selectable current limit. From the testing run carried out in this work it was found that the modern SRAM's tested did not exhibit any significant signs of synergy. However there are concerns over the accuracy of some of the data due to the SRAM's SEL response dominating behaviour. These results would benefit from further testing at lower proton energies and flux to ensure any synergy effect was not obscured by the SRAM's SEL response or being close to saturation at 23.5 MeV. The 110 and 65 nm NOR flash memories tested did not show any SEUs in their main memory sectors, while the 110 nm SONOS flash functionally failed at less than 25 krad. The serial ferroelectric random-access memory (FeRAM) suffered a few SEFI events at both 10 and 15 krad resulting in the device being non-responsive, while the device suffered a transient error where by two groups of four addresses were reported to contain errors. Lastly a new method for determining if a device is susceptible to synergy has been suggested, in addition to recommendations for improving the test methodology used in this work.