Correlation of silicon microroughness with electrical parameters of SOI-AS (silicon-on-insulator with active substrate)

A.5 gives information about the operation of the AFM used in this project, the Digital Instruments Nanoscope III Scanned Probe Microscope. 5.2. 5 Previous Work Done in AFM imaging of Silicon Surfaces Previous work has been done in imaging silicon surfaces using AFM [16]. The front silicon film in SIMOX wafers has been characterized [16]. For this project, the silicon interface is the bottom of the silicon film in the original SIMOX wafer. Previous work has been done in imaging the bottom interface by exposing the surface by etching away the buried oxide. It has been reported that the backside is quite a rough interface[ 16]. Guilhalmene et al. have discovered that the morphology of the back interface is a mosaic one due to recrystallization of the damaged silicon layer during the buried oxide formation[16]. They have also found that the roughness values of the upper buried oxide interface in SIMOX material is higher than for wafer bonded material due to the dependence between the BOX growth and the rearrangement of the implantation damaged silicon [16]. Methods have been proposed to improve the morphology of the back surface with annealing being the most common one. Annealing gives enough energy for the atoms at the interface to rearrange so as to reduce the surface roughness. It has been demonstrated that additional annealing of SIMOX wafers for 6 hours reduced the surface roughness by a factor of two [16]. The physical explanation behind that is that annealing gives the atoms enough energy to reconstruct the silicon surface. Guilhalmene et al. have found that additional anneals removed the square-rugged morphology due to solid-phase epitaxial growth, and that the new morphology becomes a square structure replaced by a spiral "step and terrace" morphology [16]. As was explained in the background, there are several methods of operating the AFM. Gilicinshki et al. [19] gives an overview of studying silicon surface roughness by using AFM. He has found that tapping mode AFM provides the best quality data for surface roughness determinations. Special care needs to be taken in imaging silicon surfaces since it has been found to be especially susceptible to damage by tip-sample interactions, hence causing artifacts in the image. That is why tapping mode is the best option to use. The other main option, contact mode, was found to be sensitive to the force applied in the experiment. On the other hand, tapping mode AFM features a decrease in lateral tip-surface interaction because the tip is not in continuous contact with the surface resulting in less artifacts in the image. An important concern in AFM is the quality of the tip. The resolution of the image is limited by the diameter of the stylus tip. It is important to image the tip to determine size and shape, since damage is possible during operation. Broken tips will give artifact-free data, with lower roughness than actually present, resulting in unreliable images of the surface. Tapping mode tips are single crystal etched silicon probes with diameters under 20 nm. Contact mode tips have diameters from 25-50 nm-giving lower values for roughness than tapping mode tips. There are three numerical techniques to quantify the morphology: 1. Average roughness (RA): Average of the absolute values of surface height variations. Ra = nI Zav (5.7) n 1 where: N 1 Zav = Zn (5.8) n= Zav is the average height of the surface. N is the number of data points. 2. RMS roughness: Square root of the mean of squares of distances from the mean surface level. LyLx RMS = L jf (x, y)dxdy (5.9) 00 where f(x, y) is the surface relative to center plane, and Lx and Ly are the length scales over which the surface calculation is being conducted in the x and y directions respectively. 5.2. 6 Measurement of SOIAS Wafers Using AFM Tapping mode AFM was done in air with a Digital Instruments multi-mode AFM using etched silicon crystal silicon tips. Figure 5.4 below shows a picture of the AFM used for this project: Figure 5.4: Dimension 3000 SPM With Motorized X-Y Stage Before performing the touch polish on the wafers to be used for the project, I first performed tests on dummy SIMOX wafers so as to optimize the process to the point where the surface roughness is reduced to a value comparable to bulk prime wafers, and at the same time, the silicon removal rate being controlled. Below are the AFM images before and after touch polish for the wafers used in this project. 1. P Scan sz . 00 o Setpoint 0.8742 U Scan rate 1.001IH Number of samples 256 Figure 5.5: AFM Image SOIAS2 Figure 5.6: AFM Image SOIAS3 Figure 5.7: AFM Image SOIAS4 2.84 nm-RMS