Parallel architectural simulations on shared-memory multiprocessors

The ever increasing size and complexity of computer systems made possible by the rapid advances in VLSI technology and computer architecture, have resulted in simulations which require excessive amounts of processing power and memory. One way to meet these requirements of detailed computer simulations is to execute them on multiprocessors. This dissertation focuses on the development of a parallel method for the fast and efficient execution of architectural simulations on shared-memory multiprocessors. We identify five issues which are important to the performance of a parallel simulator, and we address each of them separately as well as in coordination with one another. First, we study the behavior and examine the parallelism available in architectural and logic-level simulations. The results of our study show that such designs do contain significant inherent parallelism. However, for a synchronous method to be efficient in their simulations it needs to exploit the clock effect and to handle well the simulation steps with limited parallelism. In addition, traces of parallelism are shown to be important in describing the dynamic behavior of the simulation parallelism, and in identifying the limitations of parallel simulation methods. Second, we present a synchronous parallel simulation method (SPaDES) which improves upon existing synchronous methods in many ways, and performs well on both centralized memory and on NUMA multiprocessors. We also present AdvanCE SPaDES, in which an aggressive mechanism is combined with a nonblocking barrier to facilitate the extraction and exploitation of parallelism in situations where the simulation does not contain enough inherent parallelism for the processors to exploit. AdvanCE SPaDES improves the performance of the parallel simulator, especially when the original method may not perform so well. Third, we present sensitive partitioning, a method which accounts for the synchronous nature of a SPaDES simulator, as well as for characteristics of architectural and logic-level designs. Using several metrics we compare the performance of sensitive partitioning to other widely used partitioning methods in the parallel simulation of logic-level designs. The results of our study show that sensitive partitioning performs well in the partitioning of the examined designs, and that its performance can be further improved by utilizing more accurate estimations of the design characteristics. Fourth, we present a novel approach to processor self-scheduling which accounts for characteristics of the simulation method and of the target simulation area. The presented approach combines the advantages of an efficient data structure with inexpensive and easily accessible affinity information to achieve an efficient parallel execution. A study of the presented approach shows that it provides better performance than simpler approaches which utilize less affinity information. Finally, we discuss the importance of an optimizing compiler in improving the efficiency of a parallel simulator. We argue that information available to the compiler during the analysis of the simulated system can significantly improve the efficiency of the parallel simulator, and we present optimizations which are important in SPaDES simulations.