Direct communication and synchronization mechanisms in chip multiprocessors

The physical constraints of transistor integration have made chip multiproces sors (CMPs) a necessity, and increasing the number of cores (CPUs) th e best approach, yet, for the exploitation of more transistors. Already, the feasible number of cores per chip increases beyond our ability to utilize them for general purposes. Alth ough many important application domains can easily benefit from the use of more cores, scaling, in general, single-application performance with multiprocessing presents a tou gh milestone for computer science. The use of per core on-chip memories, managed in software with RDMA, ado pte in the IBM Cell processor, has challenged the mainstream approach of using c oherent caches for the on-chip memory hierarchy of CMPs. The two architectures have largely different implications for software and disunite researchers for the most suitable appr oach to multicore exploitation. We demonstrate the combination of the two approaches, with cache-in tegration of a network interface (NI) for explicit interprocessor communication, an d flexible dynamic allocation of on-chip memory to hardware-managed (cache) and software -managed parts. The network interface architecture combines messages and RDMA-based tr nsfers, with remote load-store access to the software-managed memories, and allows multipa th routing in the processor interconnection network. We propose the technique of e vent responses that efficiently exploits the normal cache access flow for network interfac functions, and prototype our combined approach in an FPGA-based multicore system, which shows reasonable logic overhead (less than 20%) in cache datapaths and controller s, f r the basic NI functionality. We also design and implement synchronization mechanisms in the network interfa ce (counters and queues), that take advantage of event responses and explo it the cache tag and data Thesis submitted to the Department of Computer Science of the University o f Crete in partial fulfillment of the requirements for the degree of Doctor of Philosophy. This work has been conducted at the Computer Architecture and VLSI Systems (CARV) laboratory of the Institute of Computer Science (ICS) of the Foundation for Research and Technology – Hellas (FORTH), and has been financially supported by a FORTH-ICS sc holarship, including funding by the European Commission through projects SIVSS (FP6 STREP #002075), Usenix (MarieCurie #509595), SARC (FP6 IP #27648), ICores (Marie-Curie #224759), and the HiPEAC Network of Excellence (NoE #0 044 8). arrays for synchronization state. We propose novel queues, that ef ficiently support multiple readers, providing hardware lock and job dispatching services, an d counters, that enable selective fences for explicit transfers, and can be synthesized to impleme nt barriers in the memory system. Evaluation of the cache-integrated NI on the hardware prototype, demons trates the flexibility of exploiting both cacheable and explicitly-managed data, and potential ad v ntages of NI transfer mechanism alternatives. Simulations of up to 128 core CMPs s how that our synchronization primitives provide significant benefits for contended loc ks and barriers, and can improve task scheduling efficiency in the Cilk [1] run-time system, for executions within the scalability limits of our benchmarks.