130 nm InP DHBTs with ft > 0 . 52 THz and fmax > 1 . 1 THz

We report results from a 130nm Indium Phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A 0.13x2m transistor exhibits a current gain cutoff frequency ft >520GHz, with a simultaneous extrapolated power gain cutoff frequency fmax>1.1THz. The HBTs exhibit these RF figures-of-merit while maintaining a common-emitter breakdown voltage BVCEO=3.5V (JE=10A/m). Additionally, scaling of the emitter junction length to 2m enables high device performance at low total power levels. Transistors in the InGaAs/InP material system have demonstrated the highest reported transistor RF figures-of-merit. Previous published results include strained-InGaAs channel high-electron mobility transistors (HEMTs) with fmax of >1THz [1,2], and InP DHBTs with fmax >800GHz [3]. High bandwidth DHBTs have applications in a number of RF and mixed-signal applications due to their high power handling and high levels of integration relative to HEMTs. The HBTs reported in this work are designed for transceiver applications at the lower end of the THz frequency band [0.3-3 THz]. General scaling laws for InP HBTs have been outlined in [4]. We perform aggressive lateral scaling of the emitter-base junction dimensions using an electroplated emitter post process with dielectric sidewall spacers. Details of the process for 250nm HBTs are reported in [5]. Critical features of the process are the use of electron beam lithography and an Au-based plating process to form an emitter post contact with a large height-to-width ratio and a vertical sidewall profile. These characteristics are advantageous for a self-aligned emitter-base HBT process flow. The 130nm process features lateral scaling of the junction and sidewall dimensions and vertical scaling of the HBT epitaxy relative to our 250nm process. The HBT epitaxy has a 25nm InGaAs base with high carbon doping (>5x10cm) to reduce base contact resistivity. A contact resistivity c <5 -m is extracted from TLM measurements on fabricated wafers. The base-collector heterojunction grade (33nm thickness) consists of an InGaAs setback layer, a InGaAs/InAlAs chirped-superlattice, and an InP pulse doping layer. The remaining Ncollector region is 67nm of InP doped at 5x10 cm, for a total collector thickness of 100nm. The emitter is InP and superlattice grading is also used at the base-emitter heterojunction. The emitter and grade layers are designed to support high current densities with low emitter access resistance. HBTs demonstrate a forward collector ideality factor nC = 1.1 and an extrinsic emitter resistance ex <4-m extracted from measurements of the low-frequency (500MHz) transconductance versus collector current. Fig. 1 shows a measurement of the HBT Gummel characteristics. The HBTs exhibit a peak current gain ~17. Measurements of versus emitter area and periphery show the current gain is limited by both bulk and surface recombination due to the high base doping level and aggressively scaled base-emitter spacing, respectively. The current gain is sufficient for our present application and we expect it could be improved with further process and epitaxy optimization. Common-emitter IV characteristics are shown in Fig. 2. The highly scaled emitter junction permits operation at high current (JE >30mA/m) and power (>50mW/m) densities. On-wafer S-parameter measurements are performed in thin-film microstrip test structures in order to reduce probe-to-probe coupling and unwanted mode propagation in the InP substrate that can corrupt the measurement of S12 in highly scaled HBTs. The microstrip is formed using the first layer metal as a ground plane, a 7um thick spinon-polymer (BCB, r =2.7) as the interlayer dielectric and an electroplated top metal level for the signal line. A multi-line Through-Reflect-Line (TRL) calibration is performed using on-wafer standards. Open and short circuit deembedding structures are used to remove the capacitive and inductive loading effects of vias through the 7um BCB layer. Total input and output capacitances of ~4fF are deembedded from the HBT measurements. Fig. 3 shows the measured transistor gains of a 0.13x2m HBT at IC=6.9mA and VCE=1.6V. Measurements were performed from 8-50GHz and 75-105GHz. The HBT figures-of-merit ft and fmax are extrapolated from least squares fits to single-pole transfer functions of the measured h21 and unilateral power gain (U), respectively. Fits are performed on the data to 50GHz, as measurements of U show considerable variation at high frequencies (>75GHz). The HBT exhibits an extrapolated ft/fmax of 521GHz/1.15THz. Fig. 4 shows the variation of ft and fmax versus collector current at varying values of VCE. At a total power dissipation of 1.2mW (IC=1.2mA and VCE=1.0V), the HBT exhibits an ft/fmax of 338GHz/639GHz. We note that the HBT fmax is enhanced at increasing values of VCE due to collector capacitance cancellation arising from electron velocity modulation [6]. A collector-base capacitance of 1.9 fF is extracted at peak RF bias. Fig. 5 and Fig. 6 show the variation of ft and fmax, respectively, versus current for varying emitter lengths. Peak ft increases for longer device lengths due to a decrease in the relative contribution of parasitic capacitance associated with the base via contact. A peak ft/fmax of 566GHz/875GHz is measured for a 4m long HBT. fmax is observed to decrease for longer devices due to contributions from the base metal resistance down the length of the narrow transistor mesa. To the best of our knowledge, these results represents the first bipolar technology with a simultaneous ft >500GHz and fmax> 1THz.