A Four-Phase Buck Converter With Capacitor-Current-Sensor Calibration for Load-Transient-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits

This paper presents a four-phase buck converter with capacitor-current-sensor (CCS) calibration for load-transient-response optimization that targets the theoretically minimal output-voltage undershoot <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {US}}$ </tex-math></inline-formula>, overshoot <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {OS}}$ </tex-math></inline-formula>, and settling time <inline-formula> <tex-math notation="LaTeX">$t_{S}$ </tex-math></inline-formula> when large and rapid load-current transients <inline-formula> <tex-math notation="LaTeX">$\Delta I_{\mathrm {load}}$ </tex-math></inline-formula> occur. The proposed CCS calibration calibrates the CCS’ equivalent impedance to emulate a scaled replica of the output capacitor’s impedance <inline-formula> <tex-math notation="LaTeX">$Z_{\mathrm {Co}}$ </tex-math></inline-formula>. Thus, the CCS can accurately sense the output-capacitor current <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {Co}}$ </tex-math></inline-formula> despite <inline-formula> <tex-math notation="LaTeX">$Z_{\mathrm {Co}}$ </tex-math></inline-formula> variations due to different output voltages, fabrication variations, and printed-circuit-board parasitics. Moreover, a load-transient optimizer is proposed to utilize the accurately sensed <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {Co}}$ </tex-math></inline-formula> to instantly detect the large and rapid <inline-formula> <tex-math notation="LaTeX">$\Delta I_{\mathrm {load}}$ </tex-math></inline-formula>, and synchronously control the charging and discharging durations of the output inductors in all four phases, resulting in small <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {US}}/\Delta V_{\mathrm {OS}}$ </tex-math></inline-formula> and short <inline-formula> <tex-math notation="LaTeX">$\text{t}_{S}$ </tex-math></inline-formula>. The converter is implemented in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process with 1.93-mm<sup>2</sup> chip area. For a 1.8-A/5-ns step-up (step-down) <inline-formula> <tex-math notation="LaTeX">$\Delta I_{\mathrm {load}}$ </tex-math></inline-formula>, the measured <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {US}}$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {OS}})$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\text{t}_{S}$ </tex-math></inline-formula> are 92 mV (75 mV) and 133 ns (110 ns), respectively. Compared with other state-of-the-arts, both the measured <inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{\mathrm {US}}$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {OS}})$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\text{t}_{S}$ </tex-math></inline-formula> in this paper are the closest to their respective theoretical limits, i.e., the fastest load-transient response with the smallest <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {US}}$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {OS}})$ </tex-math></inline-formula> and the shortest <inline-formula> <tex-math notation="LaTeX">$t_{S}$ </tex-math></inline-formula> under the same input voltage, output voltage, output inductance, and output capacitance.