Gate Dielectric Degradation Effects on nMOS Devices and Simple IC Building Blocks ( SICBBs )

Measurements using a pulse voltage stress (PVS) technique whereby dual pulse waveforms, differing in phase, gave rise to astonishing preliminary results: the lifetime of the devices were substantially reduced as compared to both constant voltage stress (CVS) and single waveform PVS. a ramped voltage stress (RVS) stress from 0 to –12V. The inverter was configured using an nMOSFET and pMOSFET device, both with a gate oxide area of 625μm and a thickness of 3.2nm. Test conditions: VIN=2V, F=2.5KHz, D.C.=50%, and VDD=2V. For both the dual waveform and SICBB experiments, the type of degradation and/or breakdown mechanism of the device was determined by preand post-stress I-V tests. The test voltage was low enough to avoid further degradation of the oxide. All experiments were performed in a Faraday cage using an Agilent 4156C. We also report on degradation mechanisms in nMOSFETs and their effect on inverter operation. We show for the first time the effect of limited hard breakdown (LHBD) [1,2] on inverter operation. Introduction Currently, the primary reliability stress test method for determining degradation mechanisms and lifetime of gate dielectrics is the CVS test[4, 5]. However, IC devices are operated in either digital or analog mode. CVS tests do not approximate either of these modes. An alternative method to better mimic digital and analog device operation is PVS. But our initial research on ultrathin gate oxides and work done by others indicates that PVS testing requires longer testing times than CVS testing [6-8]. However, experiments using a PVS technique whereby dual pulse width waveforms, differing in duty cycle and phase, resulted in a significant reduction of device lifetime as compared to both CVS and single waveform PVS. It is quite possible that dual waveforms can occur in digital and analog Ics. Results Dual waveform: Figure 2 shows the V-t output from the oscilloscope during a dual waveform experiment. Because of the superposition principle of waves, constructive interference occurs. Thus, during short time intervals, the amplitude of the original signal is doubled causing the voltage to increase to –10V. Figure 3 shows the Weibull distribution of failures versus time to breakdown (tbd) for CVS, single pulse PVS, and dual pulse PVS. The tbd for the dual pulse tests were about 2 orders of magnitude less than CVS or single pulse PVS. PostI-V results indicated that breakdown mode was LHBD. The deficiency in experimental studies examining the effect of oxide degradation and breakdown in MOSFETs on simple ICs have prompted several experts in the field to emphasize the need studies of the effects of both SILC[9], SBD[10-11], and LHBD on circuit reliability. Figure 2: Input signal to the DUT during dual waveform tests. Experimental Procedures Dual Waveform: nMOSCAPs were used with an oxide thickness and area of 3.2nm and 2.1x10cm, respectively. The configuration used to test these devices is shown in figure 1. Two waveform generators (WFGs) in parallel were configured to output 5KHz, 5-V peak-topeak, 50% duty cycle (D.C.) square wave pulse trains phase shifted by 90. The number of pulses, read by the counter, was used to determine the equivalent time to breakdown. The results were compared to time to breakdown data from single waveform PVS and CVS stress tests using the same applied voltage stress. Because dielectric breakdown occurs at lower voltages in accumulation [2,3], devices were tested in accumulation. 10 10 10 10 10 10 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 Cumulative Distribution or Failure Function, F: F = (nf-0.3)/(n+0.4) (median ranks) Knowlton Boise State University W eibulltddbAnalysis Anomalous 3_11_02. o 3/11/02 ln [-l n( 1F) ] tbd(s) Vgate: -5.5V CVS