Noise power modulation in dithered and undithered high-order sigma-delta modulators

This thesis describes theoretical and simulation-based work on digital-to-analog conversion for high resolution audio. The emphasis of the work has been exploration and clarification of issues of contention in previous art. The work has resulted in five scientific papers published in international peer-reviewed journals and conference proceedings, and these papers constitute the main contribution. The papers are included as appendixes, whereas the preceding monograph serves to provide the necessary background for understanding the results, and also their relevance in an audio context. It should be noted that although the research primarily treats DA conversion, the findings and conclusions are largely transferable also to AD conversion since audio ADC performance is often limited by its usually compulsory feedback DAC. The first paper, published in the Journal of the Audio Engineering Society, explores power modulation of the quantization error and the need for dithering in delta-sigma modulators.There has been a lot of dispute on this issue; previous publications having both argued that the DSM is self-dithering and that it has the same dither requirements as a regular REQ. By exploring noise power modulation in the baseband it is shown that even high order DSMs are not self-dithering in the true sense, but that the adverse effects of quantization are reduced when the loop filter is of high order. If the REQ is multi-bit the noise power modulation can be made negligible compared to any practical levels of circuit noise. The second paper, published in IEEE Transactions on Circuits and Systems Part II, explores a class of DSM called non-overloading or NOL modulators. Designing the DSM to be NOL is the only known way to guarantee stability for high order loops, and also the only way to guarantee no quantization noise power modulation. The paper proves that NOL design criteria are equivalent for OF and EF modulators, repudiating a claim of difference in a previous publication, and also their equivalence for rounding and truncating quantizers. Although the results are developed for a certain class of modulators, the methods are easily generalized to any DSM design. It is found desirable to use a many-bit REQ since a NOL DSM with good input swing is then allowed. The third paper, presented at the 31st Conference of the Audio Engineering Society, shows a useful utilization of the results developed in the second paper. Using a many-bit DSM is desirable for several reasons, but will in straightforward implementation require a DEM network of excessive complexity. A previously proposed method to circumvent this is to segment the DAC and DEM using a dedicated Segmentation-DSM. Previous art has used SDSMs with a FIR loop filter to ensure no DAC saturation, restricting the concept to very non-optimal designs. This publication utilizes the NOL method to design IIR SDSMs with significantly improved performance. The fourth paper, submitted to Analog Integrated Circuits and Signal Processing, describes the development of simplified estimates for DSM DAC errors. The mathematical treatment of high order DSMs is exceedingly difficult, but simplifications and rules of thumb have been developed that enable design engineers to make quite straightforward optimization of relevant DSM parameters. A major drawback is that these approximations do not account for analog error sources in the DAC and may therefore lead to unfortunate design choices. This paper explores how common DAC errors depend on the DSM transfer function, and presents extensions of known approximation methods to also include the impact the DSM has on DAC waveform distortion. Again it is confirmed that using a many-bit DSM is advantageous, and also that a conservative DSM design will make the DAC less susceptible to errors. The fifth and last paper, presented at the 124th Convention of the Audio Engineering Society, utilizes the methods presented in the fourth paper to optimize a DAC with regards to jitter noise. Clock jitter is one of the most critical performance bottlenecks in high resolution audio, and the paper proposes ways to minimize the DAC’s jitter susceptibility. The simplified approximation methods are employed and extended to show that a semidigital FIR DAC gives a more benign output waveform than a segmented DEM DAC of comparable complexity, and that it will be a preferable solution if jitter dominates the error budget. A simple method is also shown to estimate effects of implementation inaccuracies in the analog filter coefficients.