High-Level Synthesis for Nanoscale Integrated Circuits

Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call for a raised level of abstraction at which designs are specified. High-level synthesis is the process of generating register-transfer level (RTL) implementations from behavioral specifications, and it is the key enabler for a designing at a higher level beyond RTL. As IC manufacturing technology scales down to nanoscopic scale, the synthesis tools face a number of new challenges, including complexity, power and interconnect. In this dissertation, we propose a spectrum of new techniques in high-level synthesis to address the new challenges and to improve the quality of synthesis results. 1. Efficient and versatile scheduling engine using soft constraints. We present a scheduler that distinguishes soft constraints from hard constraints when exploring the design space, and identify a class of tractable scheduling problems with soft constraints. By exploiting the total unimodularity of the constraint matrix in an integer-linear programming formulation, we are able to solve the problem optimally in polynomial time. Compared to traditional methods, the proposed approach allows easier expression of various design intentions and optimization directions, and, at the same time, gives the scheduler freedom to make global trade-offs optimally. We show that this scheduling engine is flexible enough to support a variety of design considerations in high-level synthesis. 2. Behavior-level observability analysis and power optimization. We introduce the concept of behavior-level observability and its approximations in the context of high-level synthesis, and propose an efficient procedure to compute an approximated behavior-level observability of every operation in a dataflow graph. The algorithm exploits the observability-masking nature of some Boolean operations, as well as the select operation, and treats other operations as black boxes to allow efficient word-level analysis. The result is proven to be exact under the black-box abstraction. The behavior-level observability condition obtained by our analysis can be used to optimize operation gating in the scheduler. This leads to more opportunities in subsequent RTL synthesis for power reduction. To the best of our knowledge, this is the first time behavior-level observability analysis and optimization are performed in a systematic manner. 3. Layout-friendly high-level synthesis. We study a number of structural metrics for measuring the layout-friendliness of microarchitectures generated in high-level synthesis. For a piece of connected netlist, we introduce the spreading score to measures how far components can be spread from each other with bounded wire length in a graph embedding formulation. The intuition is that components in a layout-friendly netlist (e.g., a mesh) can spread over the layout region without introducing long interconnects. Spreading score can be approximated efficiently using a semidefinite programming relaxation. Another metric based on neighborhood population is also proposed. On a number of benchmarks, spreading score shows stronger bias in favor of interconnect structures that have shorter wire length after layout, compared to previous metrics based on cut size and total multiplexer inputs.