INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS

Computer-aided design in VLSI is a continuously evolving subject, with new alg orithms and solutions constantly modifying the established norms in order to accommodate effic i nt strategies to make CAD principles strong at an early phase of design abstraction. Th e same principle also applies to the routing phase in the physical design of VLSI circuits. There have been several attempts to innovate novel routing methodologies and make it parasitic aware. This awar eness in the routing paradigm is important in high-frequency designs, since inductive and ca pacitive crosstalk that often proved to be crucial in the performance of digital and analog circuits we re ignored in previous design attempts. We added an important flavor to make the interconnect-centric routing more eaningful. Realizing the importance of self and mutual inductance and coupling capacitance b etw en neighboring wires, we introduced a routing approach based on higher order moment me trics, which captures the inductive and capacitive parasitics to form a cost function comprising of a mathematical expression. Minimizing the cost allowed us not only to obtain routes that are inductive and c pacitive aware but also that produced the least ringing and delay during signal propagation . To make the route cost function even more robust and efficient, we introduced a concept of pa rasitic transformation on the universal RLC template required by the moment-driven cost function. Besides making the routing technique parasitic-aware, we also made the rou ting methodology suited towards faster convergence, in line with the requirement of an e ficient CAD tool. A constraint-driven non-linear algorithm that satisfies the design rule requ irements in addition to minimizing the moment-driven cost function using non-linear algorithm, has been d veloped to serve this purpose. Layout inclusive synthesis strategies have been present in the domain of Anal g and RF synthesis for quite some time. Introducing capacitive and on-chip inductor parasitic s helped to bring the parasitic awareness during synthesis and prevented the expensive r e-design loop between fabrication and design specification from happening. In order to give the synthes is technique a new dimension and a more refined approach, we implemented a quasi-static extraction strate gy in order to extract the resistive, self and mutual inductive parasitics of on-chip inductors a nd interconnects, within the synthesis flow. Previous attempts, which were ignorant of complete self a nd mutual inductive and capacitive parasitics of on-chip inductors and interconnects, ben efited from this full parasitic extraction technique, thereby giving a fruitful closure to RF circuit synth esis by making the design layout-aware. We also extended the moment-driven routing methodology to the RF circuit synth esis domain, in order to make the routing process at the layout inclusion stage intelligent in te rms of parasitic awareness, and efficient, by not transferring the burden of bad rou ting decisions to the synthesis engine. Coupled with this idea integration, we also included a proven fast an d accurate parasitic device modeling strategy to obviate complicated layout generation and extraction s teps required in the layout-inclusive RF circuit synthesis. The device parasitic extraction usin g this technique is based on multivariate interpolation strategy and led to faster convergence time for RF LNA synthesis. To them whom I love the most. Ma, Baba, Didi and Anu