TU 3 F-52 Microwave Characterization of Submicron nand p-channel MOSFETs Fabricated with Thin Film Silicon-On-Sapphire

Microwave characteristics are reported for nand pMOS transistors fabricated with thin-film Siiicon-on-Sapphire technology. The gates were defined with 1-line optical lithography, and ranged down to 0.5 u. /n (drawn dimension). The f, values of the transistors reach 22 GHz for the n-channel structures and 21 GHz for the pchannel devices. The PMOS results are significantly higher than found with other Si or lll-V technologies, and can potentially lead to high performance complementary microwave circuits. Small signal transistor models are similar to the ones for GaAs FETs. Dependence of model parameters on gate length were determined. Introduction The evolution of digital Si MOSFET technology has resulted in sub-micron gate length devices which exhibit high microwave gain.These devices may be considered for use in Si monolithic microwave integrated circuits (MMICs); however, the conductive properties of the bulk Si substrates and the high capacitance in some SOI technologies which use a thin isolation oxide on a conductive Si substrate prevent the realization of high-Q passive elements typically associated with MMICs. On the other hand, the sapphire substrate used in SOS is ideally suited for MMIC applications due to its insulating properties and high thermal conductivity as compared to the Si02 layers used in SIMOX or BESOI. Fully depleted thin-film SOS FETs exhibit well behaved l-V curves, good sub-threshold characteristics, reduced hot-electron effects] radiation hardness, and higher breakdown voltage than thickfilm SOS. We report here that digital thin-film SOS devices based on a 0.5 urn written gate length, exhibit f, > 20 GHz for both pand nchannel devices. These results are the highest ever shown for SOS FETs fabricated with optical lithography and are comparable to the best ever reported for electron-beam processed structures. Unlike typical devices fabricated by lll-V. bulk Si. or other SOI technologies, the f, of the thin-film SOS PMOS approaches the NMOS f, for short gate lengths. This opens up a new possibility for complementary microwave amplifiers. The technology is also promising for the cointegration of microwave and VLSI digital ICs. In this work, we characterize the microwave performance of digital thin-film SOS devices, determine the variation of the small signal model elements as a function of gate length for both the nand pchannel devices, and compare the thin-film SOS performance with competing lll-V and Si technologies. Fabrication Technology A cross section of an SOS MOSFET representative of those used for this work is diagrammed in fig. 1. Fabrication of the high quality single crystal Si films on sapphire is accomplished using an amphorization implant and solid phase re-growth process descnbed elsewhere. The Si films correspond to (100) planes, and are deposited on (11 02) sapphire surface. The result is a 100 nm Si film with low defect density despite the lattice mismatch between Si and sapphire at the interface. An 1-line stepper is used to define the 380 nm thick potysilicon gateon top of the 25 nm thick gate oxide, resulting in a minimum controlled gate length of 0.5 um. The effective gate length (Lg.e«) varies uniformly from the center to the edge and is about 0.15 ±0.05 urn smaller than the drawn gate length (Lg), as measured by the Moneda algorithm on adjacent test devices. Lg ef( is similar for adjacent nand pchannel devices in the same die. The gate length reduction is due to a combination of undercutting during the gate etch and diffusion of the source/drain implants under the-gate. The source/drain regions are formed by implantation, which is self-aligned to the gate. A 100 nm oxide sidewall spacer is formed next to the gate and TiSi2 is formed on all exposed silicon surfaces. In this process, the regions outside of the spacer become silicide. almost to the sapphire interface; this tends to reduce R<j and Rj. Oxide sidewall spacer . i