Accelerating Convolutional Neural Network With FFT on Embedded Hardware

Fueled by ImageNet Large Scale Visual Recognition Challenge and Common Objects in Context competitions, the convolutional neural network (CNN) has become important in computer vision and natural language processing. However, state-of-the-art CNNs are computationally memory-intensive, thus energy-efficient implementation on the embedded platform is challenging. Recently, VGGNet and ResNet showed that deep neural networks with more convolution layers and a few fully connected layers can achieve lower error rates, thus reducing the complexity of convolution layers is of utmost importance. In this paper, we evaluate three variations of convolutions, including direct convolution (Direct-Conv), fast Fourier transform (FFT)-based convolution (FFT-Conv), and FFT overlap and add convolution (FFT-OVA-Conv) in terms of computation complexity and memory storage requirements for popular CNN networks in embedded hardware. We implemented these three techniques for ResNet-20 with the CIFAR-10 data set on a low-power domain-specific many-core architecture called power-efficient nanoclusters (PENCs), NVIDIA Jetson TX1 graphics processing unit (GPU), ARM Cortex A53 CPU, and SPARse Convolutional NETwork (SPARCNet) accelerator on Zynq 7020 FPGA to explore the tradeoff between software and hardware implementation, domain-specific logic and instructions, as well as various parallelism across different architectures. Results are evaluated and compared with respect to throughput per layer, energy consumption, and execution time for the three methods. SPARCNet deployed on Zynq FPGA achieved 42-ms runtime with 135-mJ energy consumption with a 10.8-MB/s throughput per layer using FFT-Conv for ResNet-20. Using built-in FFT instruction in PENC, the FFT-OVA-Conv performs <inline-formula> <tex-math notation="LaTeX">$2.9\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.65\times $ </tex-math></inline-formula> faster and achieves <inline-formula> <tex-math notation="LaTeX">$6.8\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$2.5\times $ </tex-math></inline-formula> higher throughput per watt than Direct-Conv and FFT-Conv. In ARM A53 CPU, FFT-OVA-Conv achieves <inline-formula> <tex-math notation="LaTeX">$3.36\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.38\times $ </tex-math></inline-formula> improvement in execution time and <inline-formula> <tex-math notation="LaTeX">$2.72\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.32\times $ </tex-math></inline-formula> higher throughput than Direct-Conv and FFT-Conv. In TX1 GPU, FFT-Conv is <inline-formula> <tex-math notation="LaTeX">$1.9\times $ </tex-math></inline-formula> faster, <inline-formula> <tex-math notation="LaTeX">$2.2\times $ </tex-math></inline-formula> more energy-efficient, and achieves <inline-formula> <tex-math notation="LaTeX">$5.6\times $ </tex-math></inline-formula> higher throughput per layer than Direct-Conv. PENC is 10<inline-formula> <tex-math notation="LaTeX">$916\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.8\times $ </tex-math></inline-formula> faster and <inline-formula> <tex-math notation="LaTeX">$5053\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$4.3\times $ </tex-math></inline-formula> more energy-efficient and achieves <inline-formula> <tex-math notation="LaTeX">$7.5\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.2\times $ </tex-math></inline-formula> higher throughput per layer than ARM A53 CPU and TX1 GPU, respectively.