Efficient techniques for modeling and mitigation of soft errors in nanometer-scale static cmos logic circuits

Soft errors are changes in logic state resulting from the latching of single-event transients (SETs) caused by high-energy particle strikes or electrical noise. Due to scaling of minimum feature size, supply voltage, and clock frequency, soft error rate (SER) is expected to increase by several orders of magnitude in combinational and sequential logic circuits in the near future. In this dissertation, we address the following three important issues related to logic soft errors: (1) modeling of SETs generated in combinational logic blocks (CLBs), (2) efficient design techniques to reduce the SER of CLBs, and (3) analysis and design of soft-error hardened latches. Our main contributions in modeling and mitigation of soft errors in logic circuits are as follows. (1) A fast and accurate lookup-table (LUT) based approach to estimate SET width, which is necessary to gauge the effectiveness of time-redundancy based SER mitigation techniques. The LUT provides more than 1000 times speedup over HSPICE simulations and has less than 10% error compared to existing techniques which have 15% or more error, without significantly increasing LUT size. (2) An efficient and systematic error masking (EM) technique that samples selected noncritical primary outputs (POs) of a CLB three times using delay-chain-generated control signals and then majority votes on them within the slack available in a cycle to mask errors. Hence, it incurs no performance overhead, does not perform redundant computation, and can mask SETs of width less than half the slack available at a PO. The average SER reduction from EM on ISCAS85 circuits is 82.67%. Other significant features of this technique include: (a) efficient triple sampling and majority voting and (b) exploitation of circuit timing dependence upon input vector and using non-uniform slack passing/borrowing in pipelined circuits to further reduce SER. (3) A method that supports error masking plus efficient error detection and recovery (EM+EDR) and is suitable for CLBs with a small fraction of non-critical POs. In this case, EM is applied to POs with sufficient slack and EDR to critical or near-critical POs. EM+EDR can tolerate SETs with width up to half the clock period and provides an average SER reduction of 93.78% on ISCAS85 circuits. When a soft error occurs, a very low-likelihood event for an application run, and is detected, EM+EDR recovers from it within a single clock cycle. (4) Design of an efficient and robust delay chain to produce phase-shifted clock signals for use in our EM/EM+EDR techniques. (5) Finally, a comprehensive analysis of a number of existing soft-error hardened latch designs using a variety of metrics and some new designs, the best of which is vulnerable to only single-event multiple upsets, and which has a delay overhead of 12% and consumes only 70% power compared to a standard latch. Our SER mitigation work represents a significant advancement over previous approaches which, in contrast, rely on introducing explicit hardware or time redundancy or on redundant computation, often both. Consequently, our methods provide substantial energy and performance/hardware advantages while significantly reducing logic SER.