Single Contact-Material MESFETs on 4H-SiC

A novel processing technology for MESFETs is demonstrated on 4H-SiC for the first time in which the gate and source/drain contacts are simultaneously formed using a single contact material and without post-deposition annealing (PDA). Regulated DC Id-Vds characteristics clearly showing a linear region, a saturation region and a pinch-off state were obtained for the contact materials such as Ti and Ni. A TLM analysis revealed specific contact resistivity of ρC = 2.7×10 -7 Ωcm 2 for Ti and 2.0×10 -6 Ωcm 2 for Ni. This structure could have a direct impact on furthering the miniaturization of MESFETs. It could also shorten the device fabrication process by eliminating the fabrication step for the source/drain contacts. Introduction SiC metal semiconductor field effect transistors (MESFETs) for high power microwave applications require a gate contact showing a sharp rectifying (Schottky) property and source/drain contacts with very low specific contact resistivity. A widely used technique to form the source/drain contacts is to deposit the electrode material such as Ni in the heavily doped n-type region followed by post-deposition annealing (PDA) of the contacts at an elevated temperature as high as 1000°C. However, since Schottky contacts are unable to resist such high PDA temperatures, the conventional MESFET fabrication process is restricted in that gate contact formation must necessarily be preceded by source/drain contact formation [1,2]. Recently, the authors have combined different contact formation techniques without PDA as reported by Petit [3] and Teraji [4] and have used them to fabricate ohmic contacts of Ti and Al showing specific contact resistivity of less than 10 -5 Ωcm 2 in the n + region of 4H-SiC [5,6]. It is obvious that our contact formation technique can overcome the above-mentioned process restriction. In this paper, a novel processing technology for SiC MESFETs is demonstrated for the first time in which the gate and source/drain contacts are simultaneously formed using a single contact material Experimental Figure 1 shows the schematic cross-sectional structure of the MESFET proposed here. The major features of this MESFET are: both the gate and source/drain contacts use a single contact material formed without PDA; the contact material capped with Pt is defined precisely in the contact window opened in the field oxide; the n + source/drain region, which is fabricated by phosphorus ion hot-implantation followed by rapid activation annealing at 1700°C, has a doping level of more than ND = 10 20 cm -3 at the top surface; the active area including the source/drain region has a smooth surface free of plasma-etching damage [6]. MESFETs like that illustrated in Fig. 1 were actually fabricated using conductive 4H-SiC substrates on which a 4.9-μm-thick p buffer layer (NA = 5×10 15 cm -3 ) and a 0.4-μm-thick n-channel layer (ND = 1.7×10 17 cm -3 ) were epitaxially grown in succession. Resistivity of the bulk and the thickness and doping of the epilayers were determined by the wafer supplier, Cree Inc. Figure 2 shows a plan view photograph of a typical MESFET. The essential Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1221-1224 doi:10.4028/www.scientific. net/MSF.457-460.1221 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific. net. (Semanticscholar.org-11/03/20,15:23:55) 2 Title of Publication (to be inserted by the publisher) dimensions of the MESFETs discussed here were Lg = Lsg = Lgd = 2 μm and Wg = 100 μm. After the active area (n-channel) was mesa-isolated by reactive ion etching (RIE), the n + source/drain regions were formed as mentioned above. Then after sacrificial oxidization and its removal, about a 400-nm-thick field oxide was chemically vapor-deposited on the substrate with a 20-nm-thick thermal oxide. After all the contact windows for the gate and the source/drain were opened in the oxide, the 50-nm-thick contact material and 150-nm-thick cap Pt were selectively deposited in the same manner as is explained in Ref. 5. Finally, Al interconnects (pads) 300 nm in thickness were formed on the substrate by e-beam deposition and wet etching. Ti, Ni, Mo and Al were examined as contact materials. Unfortunately, the Mo and Al gates were significantly side-attacked during wet etching of the interconnect Al, which made it difficult to obtain reliable data on transistor operation. Thus, only the ohmic properties of the Mo and Al source/drain contacts are described here. The DC characteristics and contact properties of the MESFETs fabricated in this work were measured with a semiconductor parameter analyzer, Agilent HP4146B. The specific contact resistivity of the source/drain contacts, ρC, was estimated using transfer length method (TLM) contacts formed on a substrate identical to that of the MESFETs. The TLM contacts had the following dimensions: W = 200 μm and D = 100 μm, and the contact spacing was L= 6, 10, 15, 20, 25, and 30 μm. The limit for evaluating ρC seems to be around 10 -7 Ωcm 2 . The ρC values were determined on the basis of at least eight measurements. The reproducibility of the ρC data was within 22% of the average. Results and discussion The DC characteristics of several MESFETs with Ti or Ni contacts were measured. Figure 3 plots the typical Id−Vds characteristics for Ti with Vgs as a parameter. The MESFETs clearly show a linear region, a saturation region and a pinch-off state, suggesting that adequate Schottky and ohmic contacts were formed with the single contact material. Similar Id−Vds characteristics were also obtained for Ni. When Vgs = 0 V, the total resistance between the source and drain in the linear region is Ron = 40.5 Ωmm for Ti and Ron = 44.2 Ωmm for Ni. This discrepancy in Ron between Ti and Ni results from differences both in the Schottky barrier height at the gate contact, Φbn, and in ρC at the source/drain contacts. When 40 V is supplied to the drain, for both Ti and Ni, the Id value in the pinch-off state is about four orders of magnitude smaller than the maximum saturation Id value at Vgs = 0 V. The Id 1/2 −Vgs characteristics at Vds = 40 V are shown in Fig. 4. From these data, the pinch-off voltage and maximum transconductance were estimated Gate Source Drain Wg=100 μm Interconnect(Al) Ti Field } Pt Source Gate Drain 4H-SiC(n+) pn n+ CVD Thermal Fig. 1. Schematic cross-sectional structure of the proposed MESFETs with Ti contacts Fig. 2. A plan view photograph of a typical MESFET actually fabricated in this work