Guidelines for MOSFET Device Optimization accounting for L-dependent Mobility Degradation

This paper reports a new methodology to monitor L-dependent mobility degradation based on empirical modeling of experimental results. This method allows benchmarking the impact on mobility degradation of different technological modules, thus giving some guidelines for device optimization. Introduction As channel length L of MOSFETs is scaling down, carriers’ mobility μ is degraded by additional scattering mechanisms with a dramatic impact below 100nm. As reported by Andrieu et al. [1] and by Cros et al. [2] (Fig.1), this mobility crisis affects both electrons and holes. Moreover, this degradation has been measured for both poly-Si gate and metal gate [3], for both high-K and SiO2 [4], for strained and unstrained devices [1,3], for doped and undoped channel [2,4] and also whatever the device architecture: Bulk [1], SOI, [4,5], Gate-All-Around [2] or FinFET [6]. This μ(L) degradation was confirmed whatever the extraction method, i.e. Y-function, Split-CV or magneto-resistance [7], and cannot be solely explained by ballistic effects [8,9]. Unfortunately, mobility falls is a sign of a poor quality of the transport in the channel keeping us away from the ballistic regime. Whatever the conduction regime (ballistic or drift-diffusion), the on-state current will be limited by a maximum velocity that can be expressed as vlim = min(vsat,vinj) [10]. As shown in Fig.2, strong mobility degradation on short devices prevents from reaching the velocity limit, i.e. maximum on-current. Some authors [7,11] have identified those additional scattering mechanisms as impurity Coulomb scattering while neutral defects have been suggested by others [2,4]. This statement gives ground for a systematic examination of μ(L) degradation in order to establish guidelines for device optimization even if the precise origin of those additional scattering mechanisms is still not fully understood. Extraction Methodology & μ-Degradation Modeling A handy tool for extracting the mobility and monitoring its length dependence is the low field mobility μ0=μeff(Qinv≈0)=β0CoxLeffWeff. β0 at low VDS (<<VDsat) is extracted from the Y-function [12] Y(VGS)=ID/gm while effective channel length and width (resp. Leff and Weff) and gate oxide capacitance Cox are obtained independently from gate-to-channel CGC(VGS) measurements [13]. The notion of μ0 is illustrated by Fig.3. It is also worth noticing that classical Coulomb scattering and surface roughness terms do not significantly alter μ0 at 300K. Using first order θ1 and second order θ2 mobility attenuation parameters, μeff in strong inversion can be reconstructed, showing good agreement in Fig.4 with RSD-corrected split C-V extraction [14]. The use of μ0 as a mobility indicator has been validated in Fig.5 by comparing it to split C-V extraction for different Leff, clearly showing that μ0 and μeff are degraded in similar way as Leff is reduced. All our μ0 extraction have been performed vs. Leff to fairly compare the different technological splits. In order to construct our guidelines, we have introduced a new length dependent mobility degradation fitting model: 1/μ0(Leff)=1/μmax+αμ/Leff. The two fitting parameters are the maximum mobility μmax [cm.V. s], which is generally equal to the “long” channel mobility, and a mobility degradation factor αμ [nm.V. s.cm]. Fig.6 illustrates the different kinds of μ0(Leff) curves that can be obtained, αμ=0 meaning zero degradation and thus a constant μ0. However, it should be noted that αμ cannot be lower than its minimum value given by the ballistic mobility [15] αμbal= (2kT/q)/vinj, vinj being the injection velocity at source (αμbal =0.04 or 0.08 nm.V.s.cm for electron and hole respectively). Experimental Results Gate stack: Gate stack impact on μ0 was examined in Fig.7 & Fig.8. In Fig.7, two plasma nitrided SiON gate oxide thicknesses (12Å vs. 17Å) were compared for the same poly-Si gate, showing more degraded electron mobility for the thinner 12Å oxide. In Fig.8, we have found that nitrided metal gates (TiN, TaN) lead to more degraded electron mobility than the non-nitrided TaC metal gate. Those results are suggesting that N-species in the gate oxide and/or in the gate electrode lead to a lower long channel mobility in agreement with [16], but also to a higher αμ i.e. to stronger scattering mechanisms. Channel doping: Effect of channel doping was examined in Fig.9 using ultra thin body (UTB) structures in both cases (doped vs. undoped) for avoiding short channel effects disturbances. Devices fabricated using Silicon-On-Nothing (SON) technology have bulk S/D [17]. We found that increasing the channel doping is lowering the long channel electron mobility but has no significant effect on additional scattering mechanisms since close αμ values were found. Junction architecture: Since neutral defects introduction is likely related to the junction (S/D+LDD) ion implantation (I/I), S/D architecture appears as a key module for improving mobility degradation. Cros et al. have already shown in [2] that an increase of the temperature during the RTP activation anneal could cure partially the mobility degradation. Taking the problem differently, we have examined if it was possible to improve mobility degradation by changing I/I conditions (species, energy, dose). Results in Fig. 10 are demonstrating that S/D architecture optimization is possible even when reducing the RTP temperature. Mobility boosters: After having examined some possible causes of degradation, we have now investigating the effects of mobility boosters on mobility degradation. Local process induced stress (PIS) engineering by using eSiGe stressors is studied in Fig.11, while surface orientation is considered in Fig.12. Even if both strategies have an impact on holes’ μmax, only local PIS which is also L-dependent [18] significantly improves αμ. Discussion & Guidelines Seeing the strong degradation of the mobility, one could think that any mobility improvement is not relevant since all strategies will finally have the same mobility at very short gate length. Using our model, we have extrapolated from the measurements the resulting mobility at Leff=10nm in Fig.13. We can see that mobility improvement is still possible even at 10nm if well optimized. We have also investigated a possible link between μmax and αμ in Fig.14: no clear correlation was found between the two parameters meaning that they are needed to monitor the mobility degradation. Thus we have introduced a new figure of merit η=μmax/ αμ. Higher η is, higher the short channel mobility will be and closer to its limiting velocity the device will operate. Finally, we give some guidelines, based on this work in Fig.15 in order to limit μ(L) degradation. Conclusion Using a new monitoring method based on empirical modeling of μ(L) degradation, we have systematically examined the impact on μ(L) of the gate stack, channel doping, junction architecture and mobility boosters. It has been found that this degradation is not ineluctable and that working on key technological modules would help us to get closer to the ballistic regime. Acknowledgments The authors thank Process Integration teams and ST-LETI Advanced R&D for devices fabrication. This work was partially supported by IST-PULLNANO project. 0 50 100 150 200 250 300 350 400 450 0.01 0.1 1 Effective Channel Length Leff (μm) Lo w F ie ld M ob ili ty μ 0 ( cm 2 .V -1 .s -1 )