CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units

Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as an important threat to the reliability of synchronous digital circuits. To protect circuits from these timing errors, designers typically use a conservative timing margin, which leads to operational inefficiency. Existing adaptive approaches reduce such conservative margins by predicting the timing errors in advance and adjusting the timing margin adaptively. However, these error prediction approaches overlook the impact of input workload (i.e., operands) on path sensitization, thereby resulting in a loss of accuracy. The diversity of input operands leads to complex path sensitization behaviors, making them hard to represent in timing error modeling. In this paper, we propose <monospace> <bold>CLIM</bold></monospace>, a cross-level workload-aware timing error prediction model for functional units (FUs). <monospace><bold>CLIM</bold></monospace> predicts whether there are timing errors in FU at two levels: bit-level and value-level. At the bit level or value level, <monospace><bold>CLIM</bold></monospace> predicts each output bit or entire output value as one of two classes: <inline-formula><tex-math notation="LaTeX">$\lbrace$</tex-math> <alternatives><inline-graphic xlink:href="jiao-ieq1-2783333.gif"/></alternatives></inline-formula><italic>timing correct</italic>, <italic>timing erroneous</italic><inline-formula><tex-math notation="LaTeX">$\rbrace$</tex-math> <alternatives><inline-graphic xlink:href="jiao-ieq2-2783333.gif"/></alternatives></inline-formula> as a function of input workload and clock period, respectively. We apply supervised learning methods to construct <monospace><bold>CLIM </bold></monospace>, by using input operands, computation history and circuit toggling as input features, as well as outputs’ timing classes as labels. These training data are collected from gate-level simulations (GLS) of post place-and-route designs in TSMC 45nm process. We evaluate <monospace><bold>CLIM</bold></monospace> prediction accuracy for various FUs and compare it with baseline models. On average, <monospace><bold>CLIM</bold></monospace> exhibits 95 percent prediction accuracy at value-level, 97 percent at bit-level, and executes at a rate 173X faster than GLS. We utilize <monospace><bold>CLIM</bold></monospace> to analyze the value-level and bit-level reliability of FUs under random and real-world application workloads. At value-level, <monospace><bold>CLIM</bold> </monospace>-based reliability estimation is within 2.8 percent deviation on average of detailed GLS ground truth. At bit-level, we introduce the concept of <italic>bit-level reliability specification</italic> of error-tolerant applications and compare this with the <monospace><bold>CLIM</bold></monospace>-based bit-level reliability estimation. By comparison, <monospace><bold>CLIM</bold></monospace> will classify the application quality into two classes: <inline-formula><tex-math notation="LaTeX">$\lbrace$</tex-math><alternatives> <inline-graphic xlink:href="jiao-ieq3-2783333.gif"/></alternatives></inline-formula><italic>acceptable</italic>, <italic>non-acceptable</italic><inline-formula><tex-math notation="LaTeX">$\rbrace$</tex-math><alternatives> <inline-graphic xlink:href="jiao-ieq4-2783333.gif"/></alternatives></inline-formula>. On average, 97 percent application quality classification is consistent with GLS ground truth.