Solder Reliability Solutions: from Lcccs 1 to Area-array Assemblies

Advances in electronics packaging are placing more demand on solder interconnect reliability. For example, solder joints of leadless Ball Grid Array (BGA) and Chip-Scale Packaging (CSP) assemblies are more susceptible to early wear-out than solder joints in compliant, CTE2-matched leaded assemblies. Establishing the reliability of area-array assemblies requires robust design and assembly practices, including high yield and quality solder interconnects, characterization of package and board materials, evaluation of the structural response of the entire assembly. This paper reviews related historical trends and presents a new PC-based design-for-reliability model, Solder Reliability Solutions (SRS), that enables quick estimates of solder interconnect reliability and rapid “what-if” analysis of design parameters and material properties. The main features of the model and input data are presented in detail. The model is validated across a database of accelerated test results covering several generations of packaging and assembly technologies. Application to 225 I/O Plastic BGA (PBGA) assemblies is in good agreement with both experimental results and finite element modeling, thus enabling the rapid assessment and optimization of other area array designs. INTRODUCTION Area array packaging and assembly have created new solder reliability problems requiring new solutions. This paper presents engineering modeling techniques and a computer-aided design-for-reliability tool for upfront evaluation of attachment reliability for both conventional and area-array Surface Mount (SM) assemblies. Large populations of SM products have been deployed in the last five to ten years with few known instances of solder joint fatigue failures in commercial and industrial applications. High-yields, rigorous process controls, small size components, CTE matching techniques and compliant lead attachment have all contributed to the successful and reliable implementation of SM assemblies. Military, avionics, aerospace, automotive, telecommunication and other applications with extended design lives or stringent reliability requirements have required careful consideration of solder reliability issues at the design stage. The reliability challenges brought about by new assembly technology are made even more difficult by the shortening of engineering cycles. With growing trends toward larger packages for higher I/O count, increasing power dissipation, low-profile IC packages with shorter leads and large silicon content, and an increasing use of leadless area-array packages, solder reliability issues have resurfaced that must addressed at the design stage rather than as an after-thought. Modeling tools play an essential role in addressing these issues and in expediting the reliability assessment process. COMPONENT DESIGN AND ATTACHMENT RELIABILITY Figure 1 shows the impact of component design on attachment reliability and gives a relative ranking of attachment reliability for several classes of SM components on organic boards. This ranking is not absolute since reliability is application dependent and design parameters vary within a family of packages. Nevertheless, the following trends are fairly well established: • In general, LCCCs on organic boards have less attachment reliability because of solder creep-fatigue due to large cyclic strains and stresses in the solder joints under thermal cycling conditions [1, 2, 3]. Design parameters that may impede solder joint reliability are: low component stand-off, limited fillet size, large component size and the CTE mismatch between low expansivity LCCCs and high expansivity organic boards. • Discretes components such as SM capacitors and resistors also have a ceramic type body. Because of their small size, large solder attach areas and fillets, their attachment reliability has not been a concern in most environments except perhaps for automotive under-the-hood applications [4]. • Plastic leaded packages with copper leadframes and tall compliant leads have the highest attachment reliability. This includes packages like Plastic Leaded Chip Carriers (PLCCs) and Plastic Quad Flat Packs (PQFPs). The compliant leads act as elastic springs that provide strain relief and absorb the in-plane thermal expansion mismatch between components and boards. With adequate compliance built-in, stresses transmitted to the solder joints are low and, in most cases, the resulting creep strains do not lead to much creep-fatigue damage. Several methods are available to characterize lead compliance and spring constants [5, 6]. • Plastic and ceramic packages with shorter leads and Alloy42 or Kovar type leadframes have less attachment reliability. With low profile Alloy42 Thin Small Outline Packages (TSOPs) [7], the global mismatch problem is exacerbated by the low expansivity of a component with high silicon content, and short, stiff leads that do not provide sufficient strain relief. Low expansivity leadframe materials (about 6 ppm/°C for Alloy42) also create a large local expansion mismatch between the lead foot and the high expansivity solder (about 24 ppm/°C for near-eutectic Sn-Pb). Whether this is detrimental needs to be assessed on a case by case basis. 1LCCC = Leadless Ceramic Chip Carrier 2CTE = Coefficient of Thermal Expansion 2 of 14 • For BGA technology [8], reliable attachment and extended design lives can be achieved by optimizing package and joint design parameters [9-12] to decouple the stiff, low expansivity die from high expansivity organic boards. BGA attachment onto circuit boards is leadlesss as with LCCCs. However, package and board compliance, tall joints and large solder attach areas help reduce solder joint strains and stresses. Attachment reliability (or the lack of it) for competing SM miniaturization technologies is not well established yet [13, 14] except perhaps for Lead-On-Chip (LOC) [15] and flip-chip with underfill [16-20]. Design-for-reliability and optimization techniques that have been validated for other package and assembly types are expected to apply to CSP assemblies as well. The PBGA model described in the latter part of this paper applies directly to area-array assemblies such as miniand microBGAs. SOLDERED ASSEMBLY RELIABILITY MODELING Solder joints fail in a wear-out mode with component assembly failure rates increasing over time. Reliability modeling is required for upfront prediction of attachment failure rates or to extrapolate failure distributions from accelerated life tests to field conditions. Modeling also is a cost effective way to optimize package and assembly parameters. The end goal is to ensure that failure rates at the end of the intended design life meet customers’ reliability requirements. Solder interconnect reliability modeling has been the subject of intensive studies for over 25 years [1, 21, 22]. Predicting solder joint fatigue life and assembly failure rates is a difficult problem because of the complex mechanical behavior of solder, the three-dimensional (3D) structure of real electronic assemblies and the statistical nature of fatigue failures. A 1995 review of several solder reliability models is given in [23, 24]. All models have their own merit and trade-offs between different approaches are in terms of accuracy, applicability, validity, cost, availability, ease of use and skills required. Here, models are grouped into four categories based on the computational resources needed to run them: • Calculator models. These technology-specific models include temperature and frequency effects [1, 22]. Local mismatch is not included since global mismatch had a dominant effect in the assemblies these models were developed for. One example of a calculator model is the Norris-Landzberg (NL) model [22] which was developed for bare die flip-chip assemblies on ceramic substrates. The reliability of flip-chip solder joints, as supported by the NL model, has been proven by over 30 years of use in mainframe applications [25]. Recent data [9] suggests that the NL model may also apply to ceramic area-array assemblies on organic boards. • PC-based models. Two examples of PC-based models are the Comprehensive Surface Mount Reliability (CSMR) model [26, 27] and the SRS model -the latter model is presented in the next section of this paper. Both include plastic flow and creep of solder, as well as local CTE mismatches and failure statistics. Structural analysis is one-dimensional. The correlation of accelerated test data uses inelastic strain energy as a measure of cyclic damage. The CSMR and SRS models have been validated over a wide range of components and neareutectic Sn-Pb assembly technologies. • Workstation models. Two examples of models that are run on workstations are the Motorola model [28, 29] and Ford’s CAIR system [30]. Workstation power is needed for 3D non-linear, temperature and time-dependent Finite Element Analysis (FEA) in the Motorola model and others. Solder joint life is predicted using strain energy based statistical crack initiation and crack growth models that have been validated over a wide range of components and assembly technologies. In spite of some differences in the core of the Motorola and the above PC-based models, life predictions and trends derived from either model are similar. • Supercomputer models. 3D models intended to capture the intricate details of solder micro-structural evolution, crack initiation and crack growth have been developed [31, 32]. Specialized FEA codes are used and the size and complexity of the models requires super-computer resources. Many model development efforts are underway in industry and universities. The examples above do not constitute an exhaustive list and the reader is referred to [23, 24] for a more extensive review. PC-based and workstation models that have been validated for a wide range of technologies appear well suited for engineering applications. SRS MODEL The Solder Reliability Solutions (SRS) model build