Optimization of Random Telegraph Noise Non Uniformity in a CMOS Pixel with a pinned-photodiode

The main advantage of a 4T CMOS pixel (Figure 1a) which incorporates a pinned PD is the low reset noise and ultra low Dark Current (DC). In principle when the transfer of electrons from the PD to the FD is fully optimized, the reset noise can be eliminated completely by the Correlated Double Sampling (CDS) of the Reset and Signal (Figure1b). Moreover, by proper optimization of the diode and Transfer Gate the DC and DC distribution can be reduced significantly. In this case the limiting factor to the image quality in low light becomes the temporal noise associated with the Source Follower (SF) Transistor[1]. In fact, in state of the art sensors the mean value of the SF temporal noise is inherently low enough due to band-pass filter imposed by the CDS operation [2]. The main limit for good image quality in low illumination becomes the non-uniformity associated with this noise. In Figure 2 the cumulative population of two different arrays (each array contains 480x640 2.2um pixels). The first array contains pixel with optimized SF and the second array pixel with standard SF. It can be seen that while both arrays has similar mean temporal noise well below 10e, the distribution (noise non-uniformity) is completely different: for the optimized SF array only 1% of pixels has temporal noise >10e whereas for the STD SF array 10% of the pixels has temporal noise >15e. The wide distribution of temporal noise causes two main problems: in low illumination condition (assuming low dark current as shown in Figure2) it will set a limit for the maximum analog gain which can be applied to the picture before it becomes grainy; in video applications even at high illumination it will cause some pixel to blink in the darker area of the picture. In order to reveal the nature of this temporal noise non-uniformity and optimize our process and pixel layout we designed an engineering VGA array with 4um pitch. With this array along with is peripheral test board we could measure temporal noise as low as 150uV. Other features for this engineering array where complete control on pixel timing and voltages. For example one can choose quite simply not to open the TG in the read sequence. In that case the CDS operation should result zero with the uncorrelated SF noise; i.e. with this special timing we could distinguish between noise coming from incomplete transfer to the noise coming from the SF. Several pixels with different designs for their SF where placed on the engineering VGA array in smaller mini-arrays of 150x150 pixels. In Figure 3, the cumulative plots for the temporal noise of three different mini-arrays are shown. The only change between the pixels is the size of SF transistor channel: pixel (a) has W/L of 0.4/0.4 pixel (b) has W/L of 0.8/0.4 and pixel (c) has W/L of 0.4/0.8. The inner frame in figure three shows time distribution histogram of two individual pixels from the miniarray with pixel (a). The dotted line represent "quiet" pixel – pixel which his noise pattern is similar to 90% of array population. The bold line represent "noisy" pixel – pixel which only 0.1% of the population is similar or worse. The "quiet" pixel is clearly showing one main value with some distribution around it. This noise pattern is typical to