Influence of Smart CutTM process' technological steps on the thickness uniformity of SOI wafers: Multi-Scale approach

Fully-Depleted Silicon-On-Insulator (FD-SOI) wafers are promising substrates for new generations of CMOS transistors. A FD-SOI wafer consists of an ultrathin (~10 nm) silicon layer sitting on top of a buried oxide (BOx) layer itself on a thick (~750 µm) silicon handle wafer. Since final transistor characteristics dramatically fluctuate with thickness variations of the top layer, the capability of assessing and mastering thickness uniformity over a very large spatial bandwidth (from transistor to wafer scales, 10 nm - 300 mm) is a major challenge for this new application. In this work, a multi-scale metrology method, based on the use of the Power Spectral Density (PSD) functions allowing the treatment of data recorded from several experimental techniques is proposed. It is thus possible to characterize both surface roughness and thickness variations of thin layers over the bandwidth of interest. Using this method, the correlation between surface roughness and thickness variations of the silicon top layer has been addressed. It is found that depending on the spatial frequency, thickness variations can be larger, lower or similar to the surface topography. Furthermore, the impact of the main technological steps, involved in the fabrication of FD-SOI wafers, on the resulting thickness uniformity of the top silicon layer, is investigated. Fractal behaviors with different scaling exponents are observed, providing the spectral foot-prints of each step of the process, i.e., fracture propagation [from 1.10-5 to 2.10-3 µm-1], surface self-diffusion [from 0.3 to 1 µm-1] and thermal oxidation [from 1 to 10 µm-1]. The specific spectral contribution [from 0.03 to 1 µm-1], resulting from the depth and size-distribution of micro-cracks generated during the ion-implantation step, is established. Afterward, the influence of the implantation conditions on the post-fracture roughness is examined. Indeed, the surface roughness increases with the implanted dose in the case of H+-implantation. The impact of the order implantation in the case of He+-H+ co-implantation is treated. Besides, the underlying physical mechanisms involved in the thermally activated self-diffusion on silicon surfaces are investigated. We propose a parametric model, based on the Mullins-Herring diffusion equation, describing the surface topography evolution during thermal annealing. Two stochastic terms, corresponding to the thermal fluctuations at the surface and the oxidation-evaporation phenomenon are added. The extended model solved by spectral methods, allows predicting surface evolution during thermal annealing in reducing atmosphere for temperatures above that of roughening transition. A very good agreement between experimental and theoretical data describing roughness evolution and self-diffusion kinetics is obtained. The limitations of the silicon surface smoothening by rapid thermal annealing are explored and thus, the process parameters can be optimized. Finally, the evolution of the surface topography during thermal oxidation and chemical-mechanical polishing (CMP) has been studied. A fractal behavior is observed for the thermal oxidation influence. The value of the scaling exponent (α = -0.5) is in agreement with the Edward-Wilkinson growth model. Besides, the influence on the roughness evolution of several parameters of the CMP process is experimentally investigated. In conclusion, this work gives the necessary machinery to analyze both surface topography and thickness variations of thin films over a very large spectral bandwidth with an appropriated multi-scale approach. The extensive analysis of technological steps enhances their understanding and provides the necessary tools to improve the thickness uniformity of thin silicon layers.