human: Given a node-centered hypergraph: <hypergraph>, where nodes represent authors and hyperedges represent groups of authors who co-authored the same paper.

Details of the hypergraph:
Center node: "Cache configuration exploration on prototyping platforms"
  Abstract: We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself can be configured with respect to the total size, associativity, line size, and way prediction. The cache architecture includes an explorer component that efficiently searches the large space of possible configurations for the set of points representing meaningful tradeoffs between performance and energy - the Pareto-optimal set. We provide results of experiments showing that the architecture effectively finds a good set of Pareto points for numerous Powerstone and MediaBench embedded system benchmarks. Our architecture eliminates the need for time-consuming simulations to determine the best cache configuration, and imposes little power overhead and reasonable size overhead.

Connected through hyperedge HE-1 (induced by source paper "A highly configurable cache architecture for embedded systems"):
  with members:
    (none)

Question: Please tell me which research area the center author belongs to. The 4 classes are: Computer science, Mathematics, Engineering, Economics, Psychology, Business. Directly output the class name.

gpt: Computer science