human: Given a node-centered hypergraph: <hypergraph>, where nodes represent authors and hyperedges represent groups of authors who co-authored the same paper.

Details of the hypergraph:
Center node: "FPGA routing and routability estimation via Boolean satisfiability"
  Abstract: Guaranteeing or even estimating the routability of a portion of a placed field programmable gate array (FPGA) remains difficult or impossible in most practical applications. In this paper, we develop a novel formulation of both routing and routability estimation that relies on a rendering of the routing constraints as a single large Boolean equation. Any satisfying assignment to this equation specifies a complete detailed routing. By representing the equation as a binary decision diagram (BDD), we represent all possible routes for all nets simultaneously. Routability estimation is transformed to Boolean satisfiability, which is trivial for BDD's. We use the technique in the context of a perfect routability estimator for a global router. Experimental results from a standard FPGA benchmark suite suggest the technique is feasible for realistic circuits, but refinements are needed for very large designs.

Connected through hyperedge HE-1 (induced by source paper "SAT based solutions for detailed routing of island style FPGA architectures"):
  with members:
    (none)

Connected through hyperedge HE-2 (induced by source paper "Symbolic Boolean manipulation with ordered binary-decision diagrams"):
  with members:
    - "Planning via Model Checking: A Decision Procedure for AR"
    - "Symbolic protocol verification with queue BDDs"
    - "Learning visual representations for perception-action systems"
    - "Deriving Petri nets from finite transition systems"
    - "Using BDDs to verify multipliers"

Question: Please tell me which research area the center author belongs to. The 4 classes are: Computer science, Mathematics, Engineering, Economics, Psychology, Business. Directly output the class name.

gpt: Computer science