human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"
  Abstract: Recent developments in High Level Synthesis tools have attracted software programmers to accelerate their high-performance computing applications on FPGAs. Even though it has been shown that FPGAs can compete with GPUs in terms of performance for stencil computation, most previous work achieve this by avoiding spatial blocking and restricting input dimensions relative to FPGA on-chip memory. In this work we create a stencil accelerator using Intel FPGA SDK for OpenCL that achieves high performance without having such restrictions. We combine spatial and temporal blocking to avoid input size restrictions, and employ multiple FPGA-specific optimizations to tackle issues arisen from the added design complexity. Accelerator parameter tuning is guided by our performance model, which we also use to project performance for the upcoming Intel Stratix 10 devices. On an Arria 10 GX 1150 device, our accelerator can reach up to 760 and 375 GFLOP/s of compute performance, for 2D and 3D stencils, respectively, which rivals the performance of a highly-optimized GPU implementation. Furthermore, we estimate that the upcoming Stratix 10 devices can achieve a performance of up to 3.5 TFLOP/s and 1.6 TFLOP/s for 2D and 3D stencil computation, respectively.

Connected through hyperedge HE-1 (induced by source paper "an5d automated stencil framework for high degree temporal blocking on gpus"):
  with members:
    - "high performance high order stencil computation on fpgas using opencl"

Connected through hyperedge HE-2 (induced by source paper "a versatile software systolic execution model for gpu memory bound kernels"):
  with members:
    - "regdem increasing gpu performance via shared memory register spilling"
    - "stateful dataflow multigraphs a data centric model for performance portability on heterogeneous architectures"
    - "dissecting the nvidia turing t4 gpu via microbenchmarking"
    - "dissecting the nvidia volta gpu architecture via microbenchmarking"
    - "in datacenter performance analysis of a tensor processing unit"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "cudnn efficient primitives for deep learning"

Connected through hyperedge HE-3 (induced by source paper "streaming message interface high performance distributed memory programming on reconfigurable hardware"):
  with members:
    - "fblas streaming linear algebra on fpga"
    - "transformations of high level synthesis codes for high performance computing"
    - "finn a framework for fast scalable binarized neural network inference"

Connected through hyperedge HE-4 (induced by source paper "hlslib software engineering for hardware design"):
  with members:
    - "streaming message interface high performance distributed memory programming on reconfigurable hardware"
    - "stateful dataflow multigraphs a data centric model for performance portability on heterogeneous architectures"
    - "transformations of high level synthesis codes for high performance computing"

Connected through hyperedge HE-5 (induced by source paper "the memory controller wall benchmarking the intel fpga sdk for opencl memory interface"):
  with members:
    - "high performance computing with fpgas and opencl"
    - "high performance high order stencil computation on fpgas using opencl"

Connected through hyperedge HE-6 (induced by source paper "transformations of high level synthesis codes for high performance computing"):
  with members:
    - "graph processing on fpgas taxonomy survey challenges"
    - "parallel programming for fpgas"
    - "demystifying parallel and distributed deep learning an in depth concurrency analysis"
    - "finn a framework for fast scalable binarized neural network inference"
    - "programming heterogeneous systems from an image processing dsl"
    - "deep learning on fpgas past present and future"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "hitting the memory wall implications of the obvious"

Connected through hyperedge HE-7 (induced by source paper "high performance computing with fpgas and opencl"):
  with members:
    - "transformations of high level synthesis codes for high performance computing"
    - "high performance high order stencil computation on fpgas using opencl"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)