human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "microwalk a framework for finding side channels in binaries"
  Abstract: Microarchitectural side channels expose unprotected software to information leakage attacks where a software adversary is able to track runtime behavior of a benign process and steal secrets such as cryptographic keys. As suggested by incremental software patches for the RSA algorithm against variants of side-channel attacks within different versions of cryptographic libraries, protecting security-critical algorithms against side channels is an intricate task. Software protections avoid leakages by operating in constant time with a uniform resource usage pattern independent of the processed secret. In this respect, automated testing and verification of software binaries for leakage-free behavior is of importance, particularly when the source code is not available. In this work, we propose a novel technique based on Dynamic Binary Instrumentation and Mutual Information Analysis to efficiently locate and quantify memory based and control-flow based microarchitectural leakages. We develop a software framework named MicroWalk for side-channel analysis of binaries which can be extended to support new classes of leakage. For the first time, by utilizing MicroWalk, we perform rigorous leakage analysis of two widely-used closed-source cryptographic libraries: Intel IPP and Microsoft CNG. We analyze 15 different cryptographic implementations consisting of 112 million instructions in about 105 minutes of CPU time. By locating previously unknown leakages in hardened implementations, our results suggest that MicroWalk can efficiently find microarchitectural leakages in software binaries.

Connected through hyperedge HE-1 (induced by source paper "copycat controlled instruction level attacks on enclaves for maximal key extraction"):
  with members:
    - "tpm fail tpm meets timing and lattice attacks"
    - "dr sgx automated and adjustable side channel protection for sgx using data location randomization"
    - "sgxpectre stealing intel secrets from sgx enclaves via speculative execution"
    - "hybcache hybrid side channel resilient caches for trusted execution environments"
    - "mitigating branch shadowing attacks on intel sgx using control flow randomization"
    - "cachezoom how sgx amplifies the power of cache attacks"
    - "software grand exposure sgx cache attacks are practical"
    - "the heisenberg defense proactively defending sgx enclaves against page table based side channel attacks"

Connected through hyperedge HE-2 (induced by source paper "specusym speculative symbolic execution for cache timing leak detection"):
  with members:
    - "mitigating power side channels during compilation"
    - "specfuzz bringing spectre type vulnerabilities to the surface"
    - "identifying cache based side channels through secret augmented abstract interpretation"
    - "neural network model extraction attacks in edge devices by hearing architectural hints"
    - "abstract interpretation under speculative execution"
    - "ct fuzz fuzzing for timing leaks"
    - "savior towards bug driven hybrid testing"
    - "spoiler speculative load hazards boost rowhammer and cache attacks"

Connected through hyperedge HE-3 (induced by source paper "revisiting and evaluating software side channel vulnerabilities and countermeasures in cryptographic applications"):
  with members:
    - "when human cognitive modeling meets pins user independent inter keystroke timing attacks"
    - "identifying cache based side channels through secret augmented abstract interpretation"
    - "sgxpectre stealing intel secrets from sgx enclaves via speculative execution"
    - "spoiler speculative load hazards boost rowhammer and cache attacks"
    - "meltdownprime and spectreprime automatically synthesized attacks exploiting invalidation based coherence protocols"
    - "verifying and synthesizing constant resource implementations with types"
    - "spectre attacks exploiting speculative execution"
    - "robust website fingerprinting through the cache occupancy channel"

Connected through hyperedge HE-4 (induced by source paper "fortuneteller predicting microarchitectural attacks via unsupervised deep learning"):
  with members:
    - "fallout reading kernel writes from user space"
    - "zombieload cross privilege boundary data sampling"
    - "undermining user privacy on mobile devices using ai"
    - "tiresias predicting security events through deep learning"
    - "ret2spec speculative execution using return stack buffers"
    - "state of the art speech recognition with sequence to sequence models"
    - "generic black box end to end attack against state of the art api call based malware classifiers"
    - "flush flush a fast and stealthy cache attack"

Connected through hyperedge HE-5 (induced by source paper "binsec rel efficient relational symbolic execution for constant time at binary level"):
  with members:
    - "get rid of inline assembly through verification oriented lifting"
    - "symbolic verification of cache side channel freedom"
    - "eliminating timing side channel leaks using program repair"
    - "time protection the missing os abstraction"
    - "relational symbolic execution"
    - "a software approach to defeating side channels in last level caches"
    - "rigorous analysis of software countermeasures against cache attacks"

Connected through hyperedge HE-6 (induced by source paper "identifying cache based side channels through secret augmented abstract interpretation"):
  with members:
    - "adversarial symbolic execution for detecting concurrency related cache timing leaks"
    - "did we learn from llc side channel attacks a cache leakage detection tool for crypto libraries"
    - "malware guard extension using sgx to conceal cache attacks"
    - "rigorous analysis of software countermeasures against cache attacks"
    - "armageddon cache attacks on mobile devices"
    - "determinating timing channels in compute clouds"

Connected through hyperedge HE-7 (induced by source paper "a hybrid approach to secure function evaluation using sgx"):
  with members:
    - "spectre attacks exploiting speculative execution"
    - "software grand exposure sgx cache attacks are practical"
    - "securing application with software partitioning a case study using sgx"
    - "malware guard extension using sgx to conceal cache attacks"
    - "privacy preserving shortest path computation"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)