human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "transformations of high level synthesis codes for high performance computing"
  Abstract: Specialized hardware architectures promise a major step in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C/C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target specialized hardware, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes. Fast and efficient codes for reconfigurable platforms are thus still challenging to design. To alleviate this, we present a set of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. Our work provides a toolbox for developers, where we systematically identify classes of transformations, the characteristics of their effect on the HLS code and the resulting hardware (e.g., increases data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip streaming dataflow, allowing for massively parallel architectures. To quantify the effect of our transformations, we use them to optimize a set of throughput-oriented FPGA kernels, demonstrating that our enhancements are sufficient to scale up parallelism within the hardware constraints. With the transformations covered, we hope to establish a common framework for performance engineers, compiler developers, and hardware developers, to tap into the performance potential offered by specialized hardware architectures using HLS.

Connected through hyperedge HE-1 (induced by source paper "anyhls high level synthesis with partial evaluation"):
  with members:
    - "module per object a human driven methodology for c based high level synthesis design"
    - "automated accelerator generation and optimization with composable parallel and pipeline architecture"
    - "tiramisu a polyhedral compiler for expressing fast and portable code"
    - "programming heterogeneous systems from an image processing dsl"
    - "c templates as partial evaluation"

Connected through hyperedge HE-2 (induced by source paper "practice of streaming and dynamic graphs concepts models systems and parallelism"):
  with members:
    - "storing and querying large scale spatio temporal graphs with high throughput edge insertions"
    - "parallel batch dynamic graph connectivity"
    - "demystifying graph databases analysis and taxonomy of data organization system designs and graph queries"
    - "graph processing on fpgas taxonomy survey challenges"
    - "slim fly a cost effective low diameter network topology"
    - "red blue pebbling revisited near optimal parallel matrix matrix multiplication"
    - "dynamic algorithms for the massively parallel computation model"
    - "fatpaths routing in supercomputers data centers and clouds with low diameter networks when shortest paths fall short"

Connected through hyperedge HE-3 (induced by source paper "active access a mechanism for high performance distributed data centric computations"):
  with members:
    - "demystifying graph databases analysis and taxonomy of data organization system designs and graph queries"
    - "graph processing on fpgas taxonomy survey challenges"
    - "a modular benchmarking infrastructure for high performance and reproducible deep learning"
    - "network accelerated non contiguous memory transfers"
    - "spin high performance streaming processing in the network"
    - "scaling betweenness centrality using communication efficient sparse matrix multiplication"
    - "enabling highly scalable remote memory access programming with mpi 3 one sided"

Connected through hyperedge HE-4 (induced by source paper "stateful dataflow multigraphs a data centric model for performance portability on heterogeneous architectures"):
  with members:
    - "a data centric approach to extreme scale ab initio dissipative quantum transport simulations"
    - "tiramisu a code optimization framework for high performance systems"
    - "tiramisu a polyhedral compiler for expressing fast and portable code"
    - "tensorflow a system for large scale machine learning"

Connected through hyperedge HE-5 (induced by source paper "streaming message interface high performance distributed memory programming on reconfigurable hardware"):
  with members:
    - "fblas streaming linear algebra on fpga"
    - "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"
    - "finn a framework for fast scalable binarized neural network inference"

Connected through hyperedge HE-6 (induced by source paper "hlslib software engineering for hardware design"):
  with members:
    - "streaming message interface high performance distributed memory programming on reconfigurable hardware"
    - "stateful dataflow multigraphs a data centric model for performance portability on heterogeneous architectures"
    - "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"

Connected through hyperedge HE-7 (induced by source paper "high performance computing with fpgas and opencl"):
  with members:
    - "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"
    - "high performance high order stencil computation on fpgas using opencl"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)