human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "mobile machine learning hardware at arm a systems on chip soc perspective"
  Abstract: Machine learning is playing an increasingly significant role in emerging mobile application domains such as AR/VR, ADAS, etc. Accordingly, hardware architects have designed customized hardware for machine learning algorithms, especially neural networks, to improve compute efficiency. However, machine learning is typically just one processing stage in complex end-to-end applications, which involve multiple components in a mobile Systems-on-a-chip (SoC). Focusing on just ML accelerators loses bigger optimization opportunity at the system (SoC) level. This paper argues that hardware architects should expand the optimization scope to the entire SoC. We demonstrate one particular case-study in the domain of continuous computer vision where camera sensor, image signal processor (ISP), memory, and NN accelerator are synergistically co-designed to achieve optimal system-level efficiency.

Connected through hyperedge HE-1 (induced by source paper "flexibo cost aware multi objective optimization of deep neural networks"):
  with members:
    - "transfer learning for performance modeling of deep neural network systems"
    - "fixynn efficient hardware for mobile computer vision via transfer learning"
    - "learning software configuration spaces a systematic literature review"
    - "multi objective bayesian optimisation with preferences over objectives"
    - "a flexible framework for multi objective bayesian optimization using random scalarizations"
    - "ordered preference elicitation strategies for supporting multi objective decision making"
    - "towards automated deep learning efficient joint neural architecture and hyperparameter search"
    - "proxylessnas direct neural architecture search on target task and hardware"

Connected through hyperedge HE-2 (induced by source paper "asv accelerated stereo vision system"):
  with members:
    - "fixynn efficient hardware for mobile computer vision via transfer learning"
    - "packing sparse convolutional neural networks for efficient systolic array implementations column combining under joint optimization"
    - "dnn dataflow choice is overrated"
    - "morph flexible acceleration for 3d cnn based video understanding"
    - "on the importance of stereo for accurate depth estimation an efficient semi supervised deep neural network approach"
    - "euphrates algorithm soc co design for low power mobile continuous vision"
    - "scale sim systolic cnn accelerator simulator"
    - "eva 2 exploiting temporal redundancy in live computer vision"

Connected through hyperedge HE-3 (induced by source paper "high throughput cnn inference on embedded arm big little multi core processors"):
  with members:
    - "netadapt platform aware neural network adaptation for mobile applications"
    - "euphrates algorithm soc co design for low power mobile continuous vision"
    - "tvm end to end optimization stack for deep learning"
    - "ai benchmark running deep neural networks on android smartphones"
    - "scheduling computation graphs of deep learning models on manycore cpus"
    - "optimizing cnn model inference on cpus"
    - "toward low flying autonomous mav trail navigation using deep neural networks for environmental awareness"
    - "modeling the resource requirements of convolutional neural networks on mobile devices"

Connected through hyperedge HE-4 (induced by source paper "accelerating reduction and scan using tensor core units"):
  with members:
    - "nvidia tensor core programmability performance precision"
    - "modeling deep learning accelerator enabled gpus"
    - "culda_cgs solving large scale lda problems on gpus"
    - "highly scalable deep learning training system with mixed precision training imagenet in four minutes"
    - "dissecting the nvidia volta gpu architecture via microbenchmarking"
    - "in datacenter performance analysis of a tensor processing unit"
    - "scaling sgd batch size to 32k for imagenet training"
    - "mixed precision training"

Connected through hyperedge HE-5 (induced by source paper "a computational model for tensor core units"):
  with members:
    - "accelerating reduction and scan using tensor core units"
    - "nvidia tensor core programmability performance precision"
    - "modeling deep learning accelerator enabled gpus"
    - "in datacenter performance analysis of a tensor processing unit"
    - "benchmarking state of the art deep learning software tools"
    - "identity mappings in deep residual networks"
    - "powers of tensors and fast matrix multiplication"

Connected through hyperedge HE-6 (induced by source paper "euphrates algorithm soc co design for low power mobile continuous vision"):
  with members:
    - "in datacenter performance analysis of a tensor processing unit"
    - "fast yolo a fast you only look once system for real time embedded object detection in video"
    - "towards closing the energy gap between hog and cnn features for embedded vision"
    - "video classification with cnns using the codec as a spatio temporal activity sensor"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "reconfiguring the imaging pipeline for computer vision"
    - "exploring computation communication tradeoffs in camera systems"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.LG(Machine Learning)