human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "dla compiler and fpga overlay for neural network inference acceleration"
  Abstract: Overlays have shown significant promise for field-programmable gate-arrays (FPGAs) as they allow for fast development cycles and remove many of the challenges of the traditional FPGA hardware design flow. However, this often comes with a significant performance burden resulting in very little adoption of overlays for practical applications. In this paper, we tailor an overlay to a specific application domain, and we show how we maintain its full programmability without paying for the performance overhead traditionally associated with overlays. Specifically, we introduce an overlay targeted for deep neural network inference with only ~1% overhead to support the control and reprogramming logic using a lightweight very-long instruction word (VLIW) network. Additionally, we implement a sophisticated domain specific graph compiler that compiles deep learning languages such as Caffe or Tensorflow to easily target our overlay. We show how our graph compiler performs architecture-driven software optimizations to significantly boost performance of both convolutional and recurrent neural networks (CNNs/RNNs) - we demonstrate a 3x improvement on ResNet-101 and a 12x improvement for long short-term memory (LSTM) cells, compared to naive implementations. Finally, we describe how we can tailor our hardware overlay, and use our graph compiler to achieve ~900 fps on GoogLeNet on an Intel Arria 10 1150 - the fastest ever reported on comparable FPGAs.

Connected through hyperedge HE-1 (induced by source paper "ordering chaos memory aware scheduling of irregularly wired neural networks for edge devices"):
  with members:
    - "exploring randomly wired neural networks for image recognition"
    - "automatic model selection for neural networks"
    - "swiftnet using graph propagation as meta knowledge to search highly representative neural architectures"
    - "discovering neural wirings"
    - "pytorch an imperative style high performance deep learning library"
    - "learned step size quantization"
    - "amc automl for model compression and acceleration on mobile devices"
    - "glow graph lowering compiler techniques for neural networks"

Connected through hyperedge HE-2 (induced by source paper "fpga based accelerators of deep learning networks for learning and classification a review"):
  with members:
    - "deep learning for sentiment analysis a survey"
    - "deep learning based multiple object visual tracking on embedded system for iot and mobile edge computing applications"
    - "hardware for machine learning challenges and opportunities"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"
    - "finn a framework for fast scalable binarized neural network inference"
    - "parallel multi channel convolution using general matrix multiplication"
    - "ese efficient speech recognition engine with sparse lstm on fpga"

Connected through hyperedge HE-3 (induced by source paper "vargnet variable group convolutional neural network for efficient embedded computing"):
  with members:
    - "single path nas designing hardware efficient convnets in less than 4 hours"
    - "dnnvm end to end compiler leveraging heterogeneous optimizations on fpga based cnn accelerators"
    - "panoptic feature pyramid networks"
    - "igcv3 interleaved low rank group convolutions for efficient deep neural networks"
    - "bisenet bilateral segmentation network for real time semantic segmentation"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "tvm end to end optimization stack for deep learning"
    - "arcface additive angular margin loss for deep face recognition"

Connected through hyperedge HE-4 (induced by source paper "dnnvm end to end compiler leveraging heterogeneous optimizations on fpga based cnn accelerators"):
  with members:
    - "tvm end to end optimization stack for deep learning"
    - "yolov3 an incremental improvement"
    - "vta an open hardware software stack for deep learning"
    - "toolflows for mapping convolutional neural networks on fpgas a survey and future directions"
    - "intel ngraph an intermediate representation compiler and executor for deep learning"
    - "towards efficient convolutional neural network for domain specific applications on fpga"
    - "tensor comprehensions framework agnostic high performance machine learning abstractions"
    - "optimizing cnn model inference on cpus"

Connected through hyperedge HE-5 (induced by source paper "survey and benchmarking of machine learning accelerators"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "an analysis of deep neural network models for practical applications"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "mixed precision training"
    - "a survey of fpga based neural network accelerator"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "ssd single shot multibox detector"

Connected through hyperedge HE-6 (induced by source paper "fecaffe fpga enabled caffe with opencl for deep learning training and inference on intel stratix 10"):
  with members:
    - "a scalable framework for acceleration of cnn training on deeply pipelined fpga clusters with weight and workload balancing"
    - "caffeinated fpgas fpga framework for convolutional neural networks"
    - "efficient convolutional neural networks for pixelwise classification on heterogeneous hardware systems"
    - "going deeper with convolutions"
    - "very deep convolutional networks for large scale image recognition"
    - "caffe convolutional architecture for fast feature embedding"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)