human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "dissecting the nvidia volta gpu architecture via microbenchmarking"
  Abstract: Every year, novel NVIDIA GPU designs are introduced. This rapid architectural and technological progression, coupled with a reluctance by manufacturers to disclose low-level details, makes it difficult for even the most proficient GPU software designers to remain up-to-date with the technological advances at a microarchitectural level. To address this dearth of public, microarchitectural-level information on the novel NVIDIA GPUs, independent researchers have resorted to microbenchmarks-based dissection and discovery. This has led to a prolific line of publications that shed light on instruction encoding, and memory hierarchy's geometry and features at each level. Namely, research that describes the performance and behavior of the Kepler, Maxwell and Pascal architectures. In this technical report, we continue this line of research by presenting the microarchitectural details of the NVIDIA Volta architecture, discovered through microbenchmarks and instruction set disassembly. Additionally, we compare quantitatively our Volta findings against its predecessors, Kepler, Maxwell and Pascal.

Connected through hyperedge HE-1 (induced by source paper "gpu tensor cores for fast arithmetic reductions"):
  with members:
    - "accelerating reduction and scan using tensor core units"
    - "dissecting the nvidia turing t4 gpu via microbenchmarking"
    - "gpu parallel simulation algorithm of brownian particles with excluded volume using delaunay triangulations"
    - "nvidia tensor core programmability performance precision"
    - "exploration of low numeric precision deep learning inference using intel fpgas"
    - "deep learning in neural networks"

Connected through hyperedge HE-2 (induced by source paper "a data center fpga acceleration platform for convolutional neural networks"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "vta an open hardware software stack for deep learning"
    - "towards efficient convolutional neural network for domain specific applications on fpga"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "inception v4 inception resnet and the impact of residual connections on learning"

Connected through hyperedge HE-3 (induced by source paper "buddy compression enabling larger memory for deep learning and hpc workloads on gpus"):
  with members:
    - "delta gpu performance model for deep learning applications with in depth memory system traffic analysis"
    - "supporting very large models using automatic dataflow graph partitioning"
    - "high accuracy low precision training"
    - "pfdet 2nd place solution to open images challenge 2018 object detection track"
    - "dynamic sparse graph for efficient deep learning"
    - "measuring the effects of data parallelism on neural network training"
    - "megdet a large mini batch object detector"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"

Connected through hyperedge HE-4 (induced by source paper "accelerating reduction and scan using tensor core units"):
  with members:
    - "nvidia tensor core programmability performance precision"
    - "modeling deep learning accelerator enabled gpus"
    - "culda_cgs solving large scale lda problems on gpus"
    - "mobile machine learning hardware at arm a systems on chip soc perspective"
    - "highly scalable deep learning training system with mixed precision training imagenet in four minutes"
    - "in datacenter performance analysis of a tensor processing unit"
    - "scaling sgd batch size to 32k for imagenet training"
    - "mixed precision training"

Connected through hyperedge HE-5 (induced by source paper "a versatile software systolic execution model for gpu memory bound kernels"):
  with members:
    - "regdem increasing gpu performance via shared memory register spilling"
    - "stateful dataflow multigraphs a data centric model for performance portability on heterogeneous architectures"
    - "dissecting the nvidia turing t4 gpu via microbenchmarking"
    - "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"
    - "in datacenter performance analysis of a tensor processing unit"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "cudnn efficient primitives for deep learning"

Connected through hyperedge HE-6 (induced by source paper "dissecting the graphcore ipu architecture via microbenchmarking"):
  with members:
    - "scrambled linear pseudorandom number generators"
    - "aggregated residual transformations for deep neural networks"
    - "ssd single shot multibox detector"
    - "deep residual learning for image recognition"
    - "rethinking the inception architecture for computer vision"
    - "very deep convolutional networks for large scale image recognition"

Connected through hyperedge HE-7 (induced by source paper "instructions latencies characterization for nvidia gpgpus"):
  with members:
    - "holistic management of the gpgpu memory hierarchy to manage warp level latency tolerance"
    - "mixed precision training"
    - "dissecting gpu memory hierarchy through microbenchmarking"

Connected through hyperedge HE-8 (induced by source paper "low overhead instruction latency characterization for nvidia gpgpus"):
  with members:
    - "mixed precision training"
    - "dissecting gpu memory hierarchy through microbenchmarking"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)