human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "a time domain analog weighted sum calculation model for extremely low power vlsi implementation of multi layer neural networks"
  Abstract: A time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model. The proposed calculation model is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed in each layer and summation results are then fed into the next layers without their subtraction operation. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, the time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. However, they have to use very high resistance devices on the order of G$\rm \Omega$. We designed a proof-of-concept (PoC) CMOS VLSI chip to verify weighted-sum operation with the same weights and evaluated it by post-layout circuit simulation using 250-nm fabrication technology. High resistance operation was realized by using the subthreshold operation region of MOS transistors. Simulation results showed that energy efficiency for the weighted-sum calculation was 290~TOPS/W, more than one order of magnitude higher than that in state-of-the-art digital AI processors, even though the minimum width of interconnection used in the PoC chip was several times larger than that in such digital processors. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000~TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectric-gate FETs is necessary.

Connected through hyperedge HE-1 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design"):
  with members:
    - "biologically inspired alternatives to backpropagation through time for learning in recurrent neural nets"
    - "deep learning in spiking neural networks"
    - "temporal coding in spiking neural networks with alpha synaptic function"
    - "surrogate gradient learning in spiking neural networks"
    - "an energy efficient time domain analog vlsi neural network processor based on a pulse width modulation approach"
    - "supervised learning in spiking neural networks with phase change memory synapses"
    - "multiscale co design analysis of energy latency area and accuracy of a reram analog neural training accelerator"
    - "long short term memory and learning to learn in networks of spiking neurons"

Connected through hyperedge HE-2 (induced by source paper "3d acortex an ultra compact energy efficient neurocomputing platform based on commercial 3d nand flash memories"):
  with members:
    - "puma a programmable ultra efficient memristor based accelerator for machine learning inference"
    - "a behavioral compact model for static characteristics of 3d nand flash memory"
    - "alternating multi bit quantization for recurrent neural networks"
    - "discovering low precision networks close to full precision networks for efficient embedded inference"
    - "rapidnn in memory deep neural network acceleration framework"
    - "deep learning for iot big data and streaming analytics a survey"
    - "energy efficient time domain vector by matrix multiplier for neurocomputing and beyond"
    - "quantized neural networks training neural networks with low precision weights and activations"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.ET(Emerging Technologies)