human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
  Abstract: We propose a new DRAM-based true random number generator (TRNG) that leverages DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access timing parameters and use the resulting errors as the source of randomness. Our technique specifically decreases the DRAM row activation latency (timing parameter tRCD) below manufacturer-recommended specifications, to induce read errors, or activation failures, that exhibit true random behavior. We then aggregate the resulting data from multiple cells to obtain a TRNG capable of providing a high throughput of random numbers at low latency. #R##N#To demonstrate that our TRNG design is viable using commodity DRAM chips, we rigorously characterize the behavior of activation failures in 282 state-of-the-art LPDDR4 devices from three major DRAM manufacturers. We verify our observations using four additional DDR3 DRAM devices from the same manufacturers. Our results show that many cells in each device produce random data that remains robust over both time and temperature variation. We use our observations to develop D-RanGe, a methodology for extracting true random numbers from commodity DRAM devices with high throughput and low latency by deliberately violating the read access timing parameters. We evaluate the quality of our TRNG using the commonly-used NIST statistical test suite for randomness and find that D-RaNGe: 1) successfully passes each test, and 2) generates true random numbers with over two orders of magnitude higher throughput than the previous highest-throughput DRAM-based TRNG.

Connected through hyperedge HE-1 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram"):
  with members:
    - "generalized intersection over union a metric and a loss for bounding box regression"
    - "in dram bulk bitwise execution engine"
    - "analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator"
    - "amc automl for model compression and acceleration on mobile devices"
    - "high accuracy low precision training"
    - "nullanet training deep neural networks for reduced memory access inference"
    - "towards understanding the role of over parametrization in generalization of neural networks"
    - "tvm an automated end to end optimizing compiler for deep learning"

Connected through hyperedge HE-2 (induced by source paper "rowhammer a retrospective"):
  with members:
    - "processing data where it makes sense enabling in memory computation"
    - "rowhammer and beyond"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "nethammer inducing rowhammer faults through network requests"
    - "pointing in the right direction securing memory accesses in a faulty world"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "theory and practice of finding eviction sets"
    - "intrinsic rowhammer pufs leveraging the rowhammer effect for improved security"

Connected through hyperedge HE-3 (induced by source paper "large scale studies of memory storage and network failures in a modern data center"):
  with members:
    - "architectural techniques for improving nand flash memory reliability"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "nethammer inducing rowhammer faults through network requests"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "banshee bandwidth efficient dram caching via software hardware cooperation"
    - "another flip in the wall of rowhammer defenses"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"

Connected through hyperedge HE-4 (induced by source paper "rowhammer and beyond"):
  with members:
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "spectre attacks exploiting speculative execution"
    - "nethammer inducing rowhammer faults through network requests"
    - "another flip in the wall of rowhammer defenses"
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "can t touch this practical and generic software only defenses against rowhammer attacks"

Connected through hyperedge HE-5 (induced by source paper "in dram bulk bitwise execution engine"):
  with members:
    - "shouji a fast and efficient pre alignment filter for sequence alignment"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "neural cache bit serial in cache acceleration of deep neural networks"
    - "understanding reduced voltage operation in modern dram chips characterization analysis and mechanisms"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-6 (induced by source paper "understanding the interactions of workloads and dram types a comprehensive experimental study"):
  with members:
    - "in dram bulk bitwise execution engine"
    - "rowhammer a retrospective"
    - "memory centric characterization and analysis of spec cpu2017 suite"
    - "understanding and improving the latency of dram based memory systems"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "improving dram performance by parallelizing refreshes with accesses"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)