human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "design flow of accelerating hybrid extremely low bit width neural network in embedded fpga"
  Abstract: Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes. This flow covers both network training and FPGA-based network deployment, which facilitates the design space exploration and simplifies the tradeoff between network accuracy and computation efficiency. Using this flow helps hardware designers to deliver a network accelerator in edge devices under strict resource and power constraints. We present the proposed flow by supporting hybrid ELB settings within a neural network. Results show that our design can deliver very high performance peaking at 10.3 TOPS and classify up to 325.3 image/s/watt while running large-scale neural networks for less than 5W using embedded FPGA. To the best of our knowledge, it is the most energy efficient solution in comparison to GPU or other FPGA implementations reported so far in the literature.

Connected through hyperedge HE-1 (induced by source paper "autodnnchip an automated dnn chip predictor and builder for both fpgas and asics"):
  with members:
    - "e2 train training state of the art cnns with over 80 energy savings"
    - "skynet a hardware efficient method for object detection and tracking on embedded systems"
    - "dual dynamic inference enabling more efficient adaptive and controllable deep inference"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "deep k means re training and parameter sharing with harder cluster assignments for compressing deep convolutions"
    - "understanding reuse performance and hardware cost of dnn dataflows a data centric approach"
    - "face recognition with hybrid efficient convolution algorithms on fpgas"
    - "in datacenter performance analysis of a tensor processing unit"

Connected through hyperedge HE-2 (induced by source paper "skynet a hardware efficient method for object detection and tracking on embedded systems"):
  with members:
    - "accuracy vs efficiency achieving both through fpga implementation aware neural architecture search"
    - "got 10k a large high diversity benchmark for generic object tracking in the wild"
    - "skynet a champion model for dac sdc on low power object detection"
    - "single path nas device aware efficient convnet design"
    - "ternary hybrid neural tree networks for highly constrained iot applications"
    - "searching for mobilenetv3"
    - "fcos fully convolutional one stage object detection"
    - "scale aware trident networks for object detection"

Connected through hyperedge HE-3 (induced by source paper "full stack optimization for accelerating cnns with fpga validation"):
  with members:
    - "packing sparse convolutional neural networks for efficient systolic array implementations column combining under joint optimization"
    - "quantizing deep convolutional networks for efficient inference a whitepaper"
    - "from hashing to cnns training binaryweight networks via hashing"
    - "bi real net enhancing the performance of 1 bit cnns with improved representational capability and advanced training algorithm"
    - "pact parameterized clipping activation for quantized neural networks"
    - "block sparse recurrent neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "shift a zero flop zero parameter alternative to spatial convolutions"

Connected through hyperedge HE-4 (induced by source paper "hardware software co exploration of neural architectures"):
  with members:
    - "architecture search of dynamic cells for semantic video segmentation"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "haq hardware aware automated quantization with mixed precision"
    - "darts differentiable architecture search"
    - "horovod fast and easy distributed deep learning in tensorflow"
    - "mnasnet platform aware neural architecture search for mobile"
    - "large scale evolution of image classifiers"

Connected through hyperedge HE-5 (induced by source paper "fpga dnn co design an efficient design methodology for iot intelligence on the edge"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "dac sdc low power object detection challenge for uav applications"
    - "regularized evolution for image classifier architecture search"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "mnasnet platform aware neural architecture search for mobile"
    - "learning transferable architectures for scalable image recognition"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "neural architecture search with reinforcement learning"

Connected through hyperedge HE-6 (induced by source paper "a bi directional co design approach to enable deep learning on iot devices"):
  with members:
    - "pipe sgd a decentralized pipelined sgd framework for distributed deep net training"
    - "in datacenter performance analysis of a tensor processing unit"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "deep residual learning for image recognition"
    - "very deep convolutional networks for large scale image recognition"

Connected through hyperedge HE-7 (induced by source paper "pbgen partial binarization of deconvolution based generators for edge intelligence"):
  with members:
    - "efficient hybrid network architectures for extremely quantized neural networks enabling intelligence at the edge"
    - "pca driven hybrid network design for enabling intelligence at the edge"
    - "xnor neural engine a hardware accelerator ip for 21 6 fj op binary neural network inference"
    - "xnorbin a 95 top s w hardware accelerator for binary convolutional neural networks"
    - "lq nets learned quantization for highly accurate and compact deep neural networks"
    - "on the universal approximability and complexity bounds of quantized relu neural networks"
    - "hybrid binary networks optimizing for accuracy efficiency and memory"
    - "binary generative adversarial networks for image retrieval"

Connected through hyperedge HE-8 (induced by source paper "on the universal approximability and complexity bounds of quantized relu neural networks"):
  with members:
    - "amc automl for model compression and acceleration on mobile devices"
    - "syq learning symmetric quantization for efficient deep neural networks"
    - "attention is all you need"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "extremely low bit neural network squeeze the last bit out with admm"
    - "training quantized nets a deeper understanding"
    - "neural network with unbounded activation functions is universal approximator"
    - "learning discrete weights using the local reparameterization trick"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)