human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "optimizing cnn model inference on cpus"
  Abstract: The popularity of Convolutional Neural Network (CNN) models and the ubiquity of CPUs imply that better performance of CNN model inference on CPUs can deliver significant gain to a large number of users. To improve the performance of CNN inference on CPUs, current approaches like MXNet and Intel OpenVINO usually treat the model as a graph and use the high-performance libraries such as Intel MKL-DNN to implement the operations of the graph. While achieving reasonable performance on individual operations from the off-the-shelf libraries, this solution makes it inflexible to conduct optimizations at the graph level, as the local operation-level optimizations are predefined. Therefore, it is restrictive and misses the opportunity to optimize the end-to-end inference pipeline as a whole. This paper presents \emph{NeoCPU}, a comprehensive approach of CNN model inference on CPUs that employs a full-stack and systematic scheme of optimizations. \emph{NeoCPU} optimizes the operations as templates without relying on third-parties libraries, which enables further improvement of the performance via operation- and graph-level joint optimization. Experiments show that \emph{NeoCPU} achieves up to 3.45$\times$ lower latency for CNN model inference than the current state-of-the-art implementations on various kinds of popular CPUs.

Connected through hyperedge HE-1 (induced by source paper "the deep learning compiler a comprehensive survey"):
  with members:
    - "shredder learning noise distributions to protect inference privacy"
    - "fusionstitching boosting execution efficiency of memory intensive computations for dl workloads"
    - "stripe tensor compilation via the nested polyhedral model"
    - "tensorflow eager a multi stage python embedded dsl for machine learning"
    - "privacy for rescue a new testimony why privacy is vulnerable in deep models"
    - "dissecting the graphcore ipu architecture via microbenchmarking"
    - "benchmarking tpu gpu and cpu platforms for deep learning"
    - "a comprehensive survey on graph neural networks"

Connected through hyperedge HE-2 (induced by source paper "ordering chaos memory aware scheduling of irregularly wired neural networks for edge devices"):
  with members:
    - "exploring randomly wired neural networks for image recognition"
    - "automatic model selection for neural networks"
    - "swiftnet using graph propagation as meta knowledge to search highly representative neural architectures"
    - "discovering neural wirings"
    - "pytorch an imperative style high performance deep learning library"
    - "learned step size quantization"
    - "dla compiler and fpga overlay for neural network inference acceleration"
    - "amc automl for model compression and acceleration on mobile devices"

Connected through hyperedge HE-3 (induced by source paper "chameleon adaptive code optimization for expedited deep neural network compilation"):
  with members:
    - "ordering chaos memory aware scheduling of irregularly wired neural networks for edge devices"
    - "reinforced genetic algorithm learning for optimizing computation graphs"
    - "exploring randomly wired neural networks for image recognition"
    - "discovering neural wirings"
    - "active learning for regression using greedy sampling"
    - "meta gradient reinforcement learning"
    - "amc automl for model compression and acceleration on mobile devices"
    - "learning scheduling algorithms for data processing clusters"

Connected through hyperedge HE-4 (induced by source paper "optimizing memory access patterns for deep learning accelerators"):
  with members:
    - "tvm an automated end to end optimizing compiler for deep learning"
    - "parallel wavenet fast high fidelity speech synthesis"
    - "deep residual learning for image recognition"

Connected through hyperedge HE-5 (induced by source paper "high performance deep learning via a single building block"):
  with members:
    - "stripe tensor compilation via the nested polyhedral model"
    - "large batch training for lstm and beyond"
    - "nvidia tensor core programmability performance precision"
    - "high accuracy low precision training"
    - "glow graph lowering compiler techniques for neural networks"
    - "anatomy of high performance deep learning convolutions on simd architectures"
    - "tvm an automated end to end optimizing compiler for deep learning"
    - "bert pre training of deep bidirectional transformers for language understanding"

Connected through hyperedge HE-6 (induced by source paper "high throughput cnn inference on embedded arm big little multi core processors"):
  with members:
    - "netadapt platform aware neural network adaptation for mobile applications"
    - "euphrates algorithm soc co design for low power mobile continuous vision"
    - "tvm end to end optimization stack for deep learning"
    - "ai benchmark running deep neural networks on android smartphones"
    - "mobile machine learning hardware at arm a systems on chip soc perspective"
    - "scheduling computation graphs of deep learning models on manycore cpus"
    - "toward low flying autonomous mav trail navigation using deep neural networks for environmental awareness"
    - "modeling the resource requirements of convolutional neural networks on mobile devices"

Connected through hyperedge HE-7 (induced by source paper "dnnvm end to end compiler leveraging heterogeneous optimizations on fpga based cnn accelerators"):
  with members:
    - "dla compiler and fpga overlay for neural network inference acceleration"
    - "tvm end to end optimization stack for deep learning"
    - "yolov3 an incremental improvement"
    - "vta an open hardware software stack for deep learning"
    - "toolflows for mapping convolutional neural networks on fpgas a survey and future directions"
    - "intel ngraph an intermediate representation compiler and executor for deep learning"
    - "towards efficient convolutional neural network for domain specific applications on fpga"
    - "tensor comprehensions framework agnostic high performance machine learning abstractions"

Connected through hyperedge HE-8 (induced by source paper "a unified optimization approach for cnn model inference on integrated gpus"):
  with members:
    - "neurostream scalable and energy efficient deep learning with smart memory cubes"
    - "inference of quantized neural networks on heterogeneous all programmable devices"
    - "yolov3 an incremental improvement"
    - "learning to optimize tensor programs"
    - "mnasnet platform aware neural architecture search for mobile"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"
    - "embedded binarized neural networks"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)