human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "eliminating timing side channel leaks using program repair"
  Abstract: We propose a method, based on program analysis and transformation, for eliminating timing side channels in software code that implements security-critical applications. Our method takes as input the original program together with a list of secret variables (e.g., cryptographic keys, security tokens, or passwords) and returns the transformed program as output. The transformed program is guaranteed to be functionally equivalent to the original program and free of both instruction- and cache-timing side channels. Specifically, we ensure that the number of CPU cycles taken to execute any path is independent of the secret data, and the cache behavior of memory accesses, in terms of hits and misses, is independent of the secret data. We have implemented our method in LLVM and validated its effectiveness on a large set of applications, which are cryptographic libraries with 19,708 lines of C/C++ code in total. Our experiments show the method is both scalable for real applications and effective in eliminating timing side channels.

Connected through hyperedge HE-1 (induced by source paper "a compiler assisted scheduler for detecting and mitigating cache based side channel attacks"):
  with members:
    - "a fast analytical model of fully associative caches"
    - "identifying cache based side channels through secret augmented abstract interpretation"
    - "a survey of electromagnetic side channel attacks and discussion on their case progressing potential for digital forensics"
    - "a software approach to defeating side channels in last level caches"
    - "flush flush a fast and stealthy cache attack"
    - "flush flush a fast and stealthy cache attack"

Connected through hyperedge HE-2 (induced by source paper "specusym speculative symbolic execution for cache timing leak detection"):
  with members:
    - "mitigating power side channels during compilation"
    - "specfuzz bringing spectre type vulnerabilities to the surface"
    - "identifying cache based side channels through secret augmented abstract interpretation"
    - "neural network model extraction attacks in edge devices by hearing architectural hints"
    - "abstract interpretation under speculative execution"
    - "ct fuzz fuzzing for timing leaks"
    - "savior towards bug driven hybrid testing"
    - "spoiler speculative load hazards boost rowhammer and cache attacks"

Connected through hyperedge HE-3 (induced by source paper "towards constant time foundations for the new spectre era"):
  with members:
    - "abstract interpretation under speculative execution"
    - "spectre is here to stay an analysis of side channels and speculative execution"
    - "store to leak forwarding leaking data on meltdown resistant cpus"
    - "zombieload cross privilege boundary data sampling"
    - "spoiler speculative load hazards boost rowhammer and cache attacks"
    - "inspectre breaking and fixing microarchitectural vulnerabilities by formal analysis"
    - "speculative buffer overflows attacks and defenses"
    - "spectector principled detection of speculative information flows"

Connected through hyperedge HE-4 (induced by source paper "efficient detection and quantification of timing leaks with neural networks"):
  with members:
    - "mitigating power side channels during compilation"
    - "adversarial symbolic execution for detecting concurrency related cache timing leaks"
    - "data driven debugging for functional side channels"
    - "vuldeepecker a deep learning based system for vulnerability detection"
    - "canal a cache timing analysis framework via llvm transformation"
    - "discriminating traces with time"
    - "differential performance debugging with discriminant regression trees"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"

Connected through hyperedge HE-5 (induced by source paper "abstract interpretation under speculative execution"):
  with members:
    - "mitigating power side channels during compilation"
    - "adversarial symbolic execution for detecting concurrency related cache timing leaks"
    - "spectre attacks exploiting speculative execution"
    - "canal a cache timing analysis framework via llvm transformation"
    - "time protection the missing os abstraction"
    - "modular verification of interrupt driven software"
    - "thread modular static analysis for relaxed memory models"
    - "flow sensitive composition of thread modular abstract interpretation"

Connected through hyperedge HE-6 (induced by source paper "binsec rel efficient relational symbolic execution for constant time at binary level"):
  with members:
    - "get rid of inline assembly through verification oriented lifting"
    - "symbolic verification of cache side channel freedom"
    - "microwalk a framework for finding side channels in binaries"
    - "time protection the missing os abstraction"
    - "relational symbolic execution"
    - "a software approach to defeating side channels in last level caches"
    - "rigorous analysis of software countermeasures against cache attacks"

Connected through hyperedge HE-7 (induced by source paper "mitigating power side channels during compilation"):
  with members:
    - "quantitative verification of masked arithmetic programs against side channel attacks"
    - "identifying cache based side channels through secret augmented abstract interpretation"
    - "abstract interpretation under speculative execution"
    - "adversarial symbolic execution for detecting concurrency related cache timing leaks"
    - "canal a cache timing analysis framework via llvm transformation"
    - "diffuzz differential fuzzing for side channel analysis"
    - "compositional synthesis of leakage resilient programs"

Connected through hyperedge HE-8 (induced by source paper "debreach mitigating compression side channels via static analysis and transformation"):
  with members:
    - "mitigating power side channels during compilation"
    - "abstract interpretation under speculative execution"
    - "adversarial symbolic execution for detecting concurrency related cache timing leaks"
    - "datalog based scalable semantic diffing of concurrent programs"
    - "canal a cache timing analysis framework via llvm transformation"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)