human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "dnn dataflow choice is overrated"
  Abstract: Many DNN accelerators have been proposed and built using different microarchitectures and program mappings. To fairly compare these different approaches, we modified the Halide compiler to produce hardware as well as CPU and GPU code, and show that Halide's existing scheduling language has enough power to represent all existing dense DNN accelerators. Using this system we can show that the specific dataflow chosen for the accelerator is not critical to achieve good efficiency: many different dataflows yield similar energy efficiency with good performance. However, finding the best blocking and resource allocation is critical, and we achieve a 2.6X energy savings over Eyeriss system by reducing the size of the local register file. Adding an additional level in the memory hierarchy saves an additional 25%. Based on these observations, we develop an optimizer that automatically finds the optimal blocking and storage hierarchy. Compared with Eyeriss system, it achieves up to 4.2X energy improvement for Convolutional Neural Networks (CNNs), 1.6X and 1.8X improvement for Long Short-Term Memories (LSTMs) and multi-layer perceptrons (MLPs) respectively.

Connected through hyperedge HE-1 (induced by source paper "dnn chip predictor an analytical performance predictor for dnn accelerators with various dataflows and hardware architectures"):
  with members:
    - "skynet a champion model for dac sdc on low power object detection"
    - "e2 train training state of the art cnns with over 80 energy savings"
    - "dual dynamic inference enabling more efficient adaptive and controllable deep inference"
    - "scale sim systolic cnn accelerator simulator"
    - "deep k means re training and parameter sharing with harder cluster assignments for compressing deep convolutions"
    - "eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices"
    - "eie efficient inference engine on compressed deep neural network"
    - "the microsoft 2016 conversational speech recognition system"

Connected through hyperedge HE-2 (induced by source paper "cross channel intragroup sparsity neural network"):
  with members:
    - "parameter efficient training of deep convolutional neural networks by dynamic sparse reparameterization"
    - "igcv3 interleaved low rank group convolutions for efficient deep neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "understanding the disharmony between dropout and batch normalization by variance shift"
    - "shufflenet v2 practical guidelines for efficient cnn architecture design"
    - "channelnets compact and efficient convolutional neural networks via channel wise convolutions"
    - "block sparse recurrent neural networks"
    - "soft filter pruning for accelerating deep convolutional neural networks"

Connected through hyperedge HE-3 (induced by source paper "asv accelerated stereo vision system"):
  with members:
    - "fixynn efficient hardware for mobile computer vision via transfer learning"
    - "packing sparse convolutional neural networks for efficient systolic array implementations column combining under joint optimization"
    - "morph flexible acceleration for 3d cnn based video understanding"
    - "on the importance of stereo for accurate depth estimation an efficient semi supervised deep neural network approach"
    - "euphrates algorithm soc co design for low power mobile continuous vision"
    - "scale sim systolic cnn accelerator simulator"
    - "mobile machine learning hardware at arm a systems on chip soc perspective"
    - "eva 2 exploiting temporal redundancy in live computer vision"

Connected through hyperedge HE-4 (induced by source paper "gemmini an agile systolic array generator enabling systematic evaluations of deep learning architectures"):
  with members:
    - "integrating nvidia deep learning accelerator nvdla with risc v soc on firesim"
    - "fpsa a full system stack solution for reconfigurable reram based nn accelerator architecture"
    - "co design of deep neural nets and neural net accelerators for embedded vision applications"
    - "vta an open hardware software stack for deep learning"
    - "eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices"
    - "deep learning inference in facebook data centers characterization performance optimizations and hardware implications"
    - "in datacenter performance analysis of a tensor processing unit"
    - "deep gradient compression reducing the communication bandwidth for distributed training"

Connected through hyperedge HE-5 (induced by source paper "overwrite quantization opportunistic outlier handling for neural network accelerators"):
  with members:
    - "data free quantization through weight equalization and bias correction"
    - "synetgy algorithm hardware co design for convnet accelerators on embedded fpgas"
    - "improving neural network quantization without retraining using outlier channel splitting"
    - "same same but different recovering neural network quantization error through weight factorization"
    - "energy and policy considerations for deep learning in nlp"
    - "scalable methods for 8 bit training of neural networks"
    - "discovering low precision networks close to full precision networks for efficient embedded inference"
    - "bert pre training of deep bidirectional transformers for language understanding"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)