human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "automated instruction stream throughput prediction for intel and amd microarchitectures"
  Abstract: An accurate prediction of scheduling and execution of instruction streams is a necessary prerequisite for predicting the in-core performance behavior of throughput-bound loop kernels on out-of-order processor architectures. Such predictions are an indispensable component of analytical performance models, such as the Roofline and the Execution-Cache-Memory (ECM) model, and allow a deep understanding of the performance-relevant interactions between hardware architecture and loop code. We present the Open Source Architecture Code Analyzer (OSACA), a static analysis tool for predicting the execution time of sequential loops comprising x86 instructions under the assumption of an infinite first-level cache and perfect out-of-order scheduling. We show the process of building a machine model from available documentation and semi-automatic benchmarking, and carry it out for the latest Intel Skylake and AMD Zen micro-architectures. To validate the constructed models, we apply them to several assembly kernels and compare runtime predictions with actual measurements. Finally we give an outlook on how the method may be generalized to new architectures.

Connected through hyperedge HE-1 (induced by source paper "smotherspectre exploiting speculative execution through port contention"):
  with members:
    - "speculative buffer overflows attacks and defenses"
    - "netspectre read arbitrary memory over network"
    - "safespec banishing the spectre of a meltdown with leakage free speculation"
    - "spectre attacks exploiting speculative execution"
    - "spectre returns speculation attacks using the return stack buffer"
    - "ret2spec speculative execution using return stack buffers"
    - "a systematic evaluation of transient execution attacks and defenses"
    - "flush flush a fast and stealthy cache attack"

Connected through hyperedge HE-2 (induced by source paper "collecting and presenting reproducible intranode stencil performance inspect"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-3 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-4 (induced by source paper "automatic throughput and critical path analysis of x86 and arm assembly kernels"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "ithemal accurate portable and fast basic block throughput estimation using deep neural networks"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"

Connected through hyperedge HE-5 (induced by source paper "ithemal accurate portable and fast basic block throughput estimation using deep neural networks"):
  with members:
    - "learning memory access patterns"
    - "cross sentence n ary relation extraction with graph lstms"
    - "neural network based graph embedding for cross platform binary code similarity detection"
    - "linguistic knowledge as memory for recurrent neural networks"
    - "learning to represent programs with graphs"
    - "hierarchical boundary aware neural encoder for video captioning"
    - "hierarchical multiscale recurrent neural networks"
    - "learning phrase representations using rnn encoder decoder for statistical machine translation"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)