human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "concerted wire lifting enabling secure and cost effective split manufacturing"
  Abstract: Here we advance the protection of split manufacturing (SM)-based layouts through the judicious and well-controlled handling of interconnects. Initially, we explore the cost-security trade-offs of SM, which are limiting its adoption. Aiming to resolve this issue, we propose effective and efficient strategies to lift nets to the BEOL. Towards this end, we design custom "elevating cells" which we also provide to the community. Further, we define and promote a new metric, Percentage of Netlist Recovery (PNR), which can quantify the resilience against gate-level theft of intellectual property (IP) in a manner more meaningful than established metrics. Our extensive experiments show that we outperform the recent protection schemes regarding security. For example, we reduce the correct connection rate to 0% for commonly considered benchmarks, which is a first in the literature. Besides, we induce reasonably low and controllable overheads on power, performance, and area (PPA). At the same time, we also help to lower the commercial cost incurred by SM.

Connected through hyperedge HE-1 (induced by source paper "hardware security for and beyond cmos technology an overview on fundamentals applications and challenges"):
  with members:
    - "towards secure composition of integrated circuits and electronic systems on the role of eda"
    - "exploiting spin orbit torque devices as reconfigurable logic for circuit obfuscation"
    - "smart secure magnetoelectric antiferromagnet based tamper proof non volatile memory"
    - "a modern approach to ip protection and trojan prevention split manufacturing for 3d ics and obfuscation of vertical interconnects"
    - "a new paradigm in split manufacturing lock the feol unlock at the beol"
    - "spin orbit torque devices for hardware security from deterministic to probabilistic regime"
    - "protect your chip design intellectual property an overview"
    - "zombieload cross privilege boundary data sampling"

Connected through hyperedge HE-2 (induced by source paper "towards secure composition of integrated circuits and electronic systems on the role of eda"):
  with members:
    - "protect your chip design intellectual property an overview"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "processor hardware security vulnerabilities and their detection by unique program execution checking"
    - "rethinking split manufacturing an information theoretic approach with secure layout techniques"
    - "tpad hardware trojan prevention and detection for trusted integrated circuits"

Connected through hyperedge HE-3 (induced by source paper "protect your chip design intellectual property an overview"):
  with members:
    - "functional analysis attacks on logic locking"
    - "a new paradigm in split manufacturing lock the feol unlock at the beol"
    - "srclock sat resistant cyclic logic locking for protecting the hardware"
    - "best of both worlds integration of split manufacturing and camouflaging into a security driven cad flow for 3d ics"
    - "opening the doors to dynamic camouflaging harnessing the power of polymorphic devices"
    - "sat based reverse engineering of gate level schematics using fault injection and probing"
    - "advancing hardware security using polymorphic and stochastic spin hall effect devices"
    - "rethinking split manufacturing an information theoretic approach with secure layout techniques"

Connected through hyperedge HE-4 (induced by source paper "spin orbit torque devices for hardware security from deterministic to probabilistic regime"):
  with members:
    - "exploiting spin orbit torque devices as reconfigurable logic for circuit obfuscation"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "rethinking split manufacturing an information theoretic approach with secure layout techniques"
    - "obfuscating the interconnects low cost and resilient full chip layout camouflaging"
    - "physical design obfuscation of hardware a comprehensive investigation of device and logic level techniques"

Connected through hyperedge HE-5 (induced by source paper "a new paradigm in split manufacturing lock the feol unlock at the beol"):
  with members:
    - "rethinking split manufacturing an information theoretic approach with secure layout techniques"

Connected through hyperedge HE-6 (induced by source paper "best of both worlds integration of split manufacturing and camouflaging into a security driven cad flow for 3d ics"):
  with members:
    - "spectre attacks exploiting speculative execution"
    - "advancing hardware security using polymorphic and stochastic spin hall effect devices"
    - "rethinking split manufacturing an information theoretic approach with secure layout techniques"
    - "a novel interconnect camouflaging technique using transistor threshold voltage"
    - "obfuscating the interconnects low cost and resilient full chip layout camouflaging"
    - "physical design obfuscation of hardware a comprehensive investigation of device and logic level techniques"
    - "threshold dependent camouflaged cells to secure circuits against reverse engineering attacks"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)