human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "extended bit plane compression for convolutional neural network accelerators"
  Abstract: After the tremendous success of convolutional neural networks in image classification, object detection, speech recognition, etc., there is now rising demand for deployment of these compute-intensive ML models on tightly power constrained embedded and mobile systems at low cost as well as for pushing the throughput in data centers. This has triggered a wave of research towards specialized hardware accelerators. Their performance is often constrained by I/O bandwidth and the energy consumption is dominated by I/O transfers to off-chip memory. We introduce and evaluate a novel, hardware-friendly compression scheme for the feature maps present within convolutional neural networks. We show that an average compression ratio of 4.4x relative to uncompressed data and a gain of 60% over existing method can be achieved for ResNet-34 with a compression block requiring <300 bit of sequential cells and minimal combinational logic.

Connected through hyperedge HE-1 (induced by source paper "ebpc extended bit plane compression for deep neural network inference and training accelerators"):
  with members:
    - "and the bit goes down revisiting the quantization of neural networks"
    - "additive noise annealing and approximation properties of quantized neural networks"
    - "a 64 mw dnn based visual navigation engine for autonomous nano drones"
    - "rpr random partition relaxation for training binary and ternary weight neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "yolov3 an incremental improvement"
    - "shufflenet v2 practical guidelines for efficient cnn architecture design"
    - "multiposenet fast multi person pose estimation using pose residual network"

Connected through hyperedge HE-2 (induced by source paper "rpr random partition relaxation for training binary and ternary weight neural networks"):
  with members:
    - "ebpc extended bit plane compression for deep neural network inference and training accelerators"
    - "improving neural network quantization without retraining using outlier channel splitting"
    - "quantization networks"
    - "fann on mcu an open source toolkit for energy efficient neural network inference at the edge of the internet of things"
    - "hawq hessian aware quantization of neural networks with mixed precision"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "fbnet hardware aware efficient convnet design via differentiable neural architecture search"
    - "lq nets learned quantization for highly accurate and compact deep neural networks"

Connected through hyperedge HE-3 (induced by source paper "feature map transform coding for energy efficient cnn inference"):
  with members:
    - "dnnvm end to end compiler leveraging heterogeneous optimizations on fpga based cnn accelerators"
    - "regularizing activation distribution for training binarized deep networks"
    - "lutnet rethinking inference in fpga soft logic"
    - "low bit quantization of neural networks for efficient inference"
    - "same same but different recovering neural network quantization error through weight factorization"
    - "swalp stochastic weight averaging in low precision training"
    - "hawq hessian aware quantization of neural networks with mixed precision"
    - "faster gaze prediction with dense networks and fisher pruning"

Connected through hyperedge HE-4 (induced by source paper "additive noise annealing and approximation properties of quantized neural networks"):
  with members:
    - "a 64 mw dnn based visual navigation engine for autonomous nano drones"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "bi real net enhancing the performance of 1 bit cnns with improved representational capability and advanced training algorithm"
    - "yolov3 an incremental improvement"
    - "training compact neural networks with binary weights and low precision activations"
    - "soft to hard vector quantization for end to end learning compressible representations"
    - "towards accurate binary convolutional neural network"
    - "learning to fly by crashing"

Connected through hyperedge HE-5 (induced by source paper "constrained deep neural network architecture search for iot devices accounting hardware calibration"):
  with members:
    - "a survey on neural architecture search"
    - "efficient image dataset classification difficulty estimation for predicting deep learning accuracy"
    - "tapas train less accuracy predictor for architecture search"
    - "efficient neural architecture search via parameter sharing"
    - "mnasnet platform aware neural architecture search for mobile"
    - "learning transferable architectures for scalable image recognition"
    - "efficient architecture search by network transformation"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"

Connected through hyperedge HE-6 (induced by source paper "optimally scheduling cnn convolutions for efficient memory access"):
  with members:
    - "xnor neural engine a hardware accelerator ip for 21 6 fj op binary neural network inference"
    - "neurostream scalable and energy efficient deep learning with smart memory cubes"
    - "an iot endpoint system on chip for secure and energy efficient near sensor analytics"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "the power of sparsity in convolutional neural networks"
    - "a survey of model compression and acceleration for deep neural networks"
    - "a systematic approach to blocking convolutional neural networks"
    - "ristretto hardware oriented approximation of convolutional neural networks"

Connected through hyperedge HE-7 (induced by source paper "hyperdrive a multi chip systolically scalable binary weight cnn inference engine"):
  with members:
    - "mixed precision training of convolutional neural networks using integer operations"
    - "xnorbin a 95 top s w hardware accelerator for binary convolutional neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "yolov3 an incremental improvement"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"
    - "in datacenter performance analysis of a tensor processing unit"
    - "cas cnn a deep convolutional neural network for image compression artifact suppression"
    - "an iot endpoint system on chip for secure and energy efficient near sensor analytics"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CV(Computer Vision and Pattern Recognition)