human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "the parallel persistent memory model"
  Abstract: We consider a parallel computational model, the Parallel Persistent Memory model, comprised of P processors, each with a fast local ephemeral memory of limited size, and sharing a large persistent memory. The model allows for each processor to fault at any time (with bounded probability), and possibly restart. When a processor faults, all of its state and local ephemeral memory is lost, but the persistent memory remains. This model is motivated by upcoming non-volatile memories that are nearly as fast as existing random access memory, are accessible at the granularity of cache lines, and have the capability of surviving power outages. It is further motivated by the observation that in large parallel systems, failure of processors and their caches is not unusual. We present several results for the model, using an approach that breaks a computation into capsules, each of which can be safely run multiple times. For the single-processor version we describe how to simulate any program in the RAM, the external memory model, or the ideal-cache model with an expected constant factor overhead. For the multiprocessor version we describe how to efficiently implement a work-stealing scheduler within the model such that it handles both soft faults, with a processor restarting, and hard faults, with a processor permanently failing. For any multithreaded fork-join computation that is race free, write-after-read conflict free and has W work, D depth, and C maximum capsule work in the absence of faults, the scheduler guarantees a time bound on the model of $Oleft(\fracW P_A + \fracDP P_A leftlceillog_1/(C\f) W\right\rceil\right)$ in expectation, where P is the maximum number of processors, $P_A$ is the average number, and $\faultprob leq 1/(2C)$ is the probability a processor faults between successive persistent memory accesses. Within the model, and using the proposed methods, we develop efficient algorithms for parallel prefix sums, merging, sorting, and matrix multiply.

Connected through hyperedge HE-1 (induced by source paper "streamlining integrity tree updates for secure persistent non volatile memory"):
  with members:
    - "pangolin a fault tolerant persistent memory programming library"
    - "let the cloud watch over your iot file systems"
    - "triad nvm persistent security for integrity protected and encrypted non volatile memories nvms"

Connected through hyperedge HE-2 (induced by source paper "semi asymmetric parallel graph algorithms for nvrams"):
  with members:
    - "pangolin a fault tolerant persistent memory programming library"
    - "tracking in order to recover recoverable lock free data structures"
    - "write optimized and consistent rdma based nvm systems"
    - "single machine graph analytics on massive datasets using intel optane dc persistent memory"
    - "multiversion concurrency with bounded delay and precise garbage collection"
    - "persistent memory i o primitives"
    - "persistent buffer management with optimistic consistency"
    - "basic performance measurements of the intel optane dc persistent memory module"

Connected through hyperedge HE-3 (induced by source paper "improved parallel cache oblivious algorithms for dynamic programming and linear algebra"):
  with members:
    - "persistent memory i o primitives"
    - "parallel write efficient algorithms and data structures for computational geometry"
    - "algorithmic building blocks for asymmetric memories"
    - "resource oblivious sorting on multicores"
    - "implicit decomposition for write efficient connectivity algorithms"
    - "on the fine grained complexity of one dimensional dynamic programming"
    - "extending the nested parallel model to the nested dataflow model with provably efficient schedulers"
    - "parallel shortest paths using radius stepping"

Connected through hyperedge HE-4 (induced by source paper "delay free concurrency on faulty persistent memory"):
  with members:
    - "multiversion concurrency with bounded delay and precise garbage collection"
    - "efficient logging in non volatile memory by exploiting coherency protocols"
    - "flat combining and the synchronization parallelism tradeoff"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)