human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "vibnn hardware acceleration of bayesian neural networks"
  Abstract: Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number generators: 1) the RAM-based Linear Feedback Gaussian Random Number Generator (RLF-GRNG), which is inspired by the properties of binomial distribution and linear feedback logics; and 2) the Bayesian Neural Network-oriented Wallace Gaussian Random Number Generator. To achieve high scalability and efficient memory access, we propose a deep pipelined accelerator architecture with fast execution and good hardware utilization. Experimental results demonstrate that the proposed VIBNN implementations on an FPGA can achieve throughput of 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J while maintaining similar accuracy as its software counterpart.

Connected through hyperedge HE-1 (induced by source paper "exploiting oxide based resistive ram variability for bayesian neural network hardware design"):
  with members:
    - "puma a programmable ultra efficient memristor based accelerator for machine learning inference"
    - "all spin bayesian neural networks"
    - "vime variational information maximizing exploration"

Connected through hyperedge HE-2 (induced by source paper "non structured dnn weight pruning is it beneficial in any platform"):
  with members:
    - "synetgy algorithm hardware co design for convnet accelerators on embedded fpgas"
    - "adversarial robustness vs model compression or both"
    - "hypar towards hybrid parallelism for deep learning accelerator array"
    - "2pfpce two phase filter pruning based on conditional entropy"
    - "bag of tricks for image classification with convolutional neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "learning and generalization in overparameterized neural networks going beyond two layers"
    - "morph flexible acceleration for 3d cnn based video understanding"

Connected through hyperedge HE-3 (induced by source paper "hypar towards hybrid parallelism for deep learning accelerator array"):
  with members:
    - "supporting very large models using automatic dataflow graph partitioning"
    - "red a reram based deconvolution accelerator"
    - "mt spike a multilayer time based spiking neuromorphic architecture with temporal error backpropagation"
    - "pt spike a precise time dependent single spike neuromorphic architecture with efficient supervised learning"
    - "ucnn exploiting computational reuse in deep neural networks via weight repetition"
    - "revisiting small batch training for deep neural networks"
    - "unifying data model and hybrid parallelism in deep learning via tensor tiling"
    - "group scissor scaling neuromorphic computing design to large neural networks"

Connected through hyperedge HE-4 (induced by source paper "accelerating generalized linear models with mlweaving a one size fits all system for any precision learning technical report"):
  with members:
    - "high accuracy low precision training"
    - "adaptive communication strategies to achieve the best error runtime trade off in local update sgd"
    - "in rdbms hardware acceleration of advanced analytics"
    - "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing"
    - "e rnn design optimization for efficient recurrent neural networks in fpgas"
    - "neural cache bit serial in cache acceleration of deep neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "bridging the gap between neural networks and neuromorphic hardware with a neural network compiler"

Connected through hyperedge HE-5 (induced by source paper "puma a programmable ultra efficient memristor based accelerator for machine learning inference"):
  with members:
    - "group scissor scaling neuromorphic computing design to large neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "bridging the gap between neural networks and neuromorphic hardware with a neural network compiler"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "trannsformer n eural n etwork transform ation for memristive crossbar based neuromorphic system design"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "resparc a reconfigurable and energy efficient architecture with memristive crossbars for deep spiking neural networks"

Connected through hyperedge HE-6 (induced by source paper "all spin bayesian neural networks"):
  with members:
    - "puma a programmable ultra efficient memristor based accelerator for machine learning inference"
    - "implementing bayesian networks with embedded stochastic mram"
    - "stochastic spin orbit torque devices as elements for bayesian inference"
    - "encoding neural and synaptic functionalities in electron spin a pathway to efficient neuromorphic computing"
    - "resparc a reconfigurable and energy efficient architecture with memristive crossbars for deep spiking neural networks"
    - "probabilistic deep spiking neural systems enabled by magnetic tunnel junction"
    - "proposal for an all spin artificial neural network emulating neural and synaptic functionalities through domain wall motion in ferromagnets"
    - "vime variational information maximizing exploration"

Connected through hyperedge HE-7 (induced by source paper "a stochastic computing based deep learning framework using adiabatic quantum flux parametron superconducting technology"):
  with members:
    - "on the universal approximation property and equivalence of stochastic computing based neural networks and binary neural networks"
    - "energy efficient hybrid stochastic binary neural networks for near sensor computing"
    - "vlsi implementation of deep neural network using integral stochastic computing"
    - "finn a framework for fast scalable binarized neural network inference"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "eie efficient inference engine on compressed deep neural network"

Connected through hyperedge HE-8 (induced by source paper "exploiting oxide based resistive ram variability for probabilistic ai hardware design"):
  with members:
    - "puma a programmable ultra efficient memristor based accelerator for machine learning inference"
    - "all spin bayesian neural networks"
    - "vime variational information maximizing exploration"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.LG(Machine Learning)