human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing"
  Abstract: Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many matrix multiplication-dependent applications can use reduced-precision integer or fixed-point representations to increase their performance and energy efficiency while still offering adequate quality of results. However, precision requirements may vary between different application phases or depend on input data, rendering constant-precision solutions ineffective. We present BISMO, a vectorized bit-serial matrix multiplication overlay for reconfigurable computing. BISMO utilizes the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism. We characterize the resource usage and performance of BISMO across a range of parameters to build a hardware cost model, and demonstrate a peak performance of 6.5 TOPS on the Xilinx PYNQ-Z1 board.

Connected through hyperedge HE-1 (induced by source paper "efficient bitwidth search for practical mixed precision neural network"):
  with members:
    - "differentiable soft quantization bridging full precision and low bit neural networks"
    - "hawq hessian aware quantization of neural networks with mixed precision"
    - "regularized evolution for image classifier architecture search"
    - "lq nets learned quantization for highly accurate and compact deep neural networks"
    - "learning to quantize deep networks by optimizing quantization intervals with task loss"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "discrimination aware channel pruning for deep neural networks"
    - "releq an automatic reinforcement learning approach for deep quantization of neural networks"

Connected through hyperedge HE-2 (induced by source paper "qutibench benchmarking neural networks on heterogeneous hardware"):
  with members:
    - "analysis of dawnbench a time to accuracy machine learning performance benchmark"
    - "binareye an always on energy accuracy scalable binary cnn processor with all memory on chip in 28nm cmos"
    - "training and inference with integers in deep neural networks"
    - "tvm end to end optimization stack for deep learning"
    - "finn l library extensions and design trade off analysis for variable precision lstm networks on fpgas"
    - "tbd benchmarking and analyzing deep neural network training"
    - "in datacenter performance analysis of a tensor processing unit"
    - "toward computation and memory efficient neural network acoustic models with binary weights and activations"

Connected through hyperedge HE-3 (induced by source paper "adaptive precision training quantify back propagation in neural networks with fixed point numbers"):
  with members:
    - "differentiable quantization of deep neural networks"
    - "scalable methods for 8 bit training of neural networks"
    - "mixed precision training of convolutional neural networks using integer operations"
    - "a quantization friendly separable convolution for mobilenets"
    - "training and inference with integers in deep neural networks"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "training deep neural networks with 8 bit floating point numbers"
    - "haq hardware aware automated quantization with mixed precision"

Connected through hyperedge HE-4 (induced by source paper "accelerating generalized linear models with mlweaving a one size fits all system for any precision learning technical report"):
  with members:
    - "high accuracy low precision training"
    - "adaptive communication strategies to achieve the best error runtime trade off in local update sgd"
    - "in rdbms hardware acceleration of advanced analytics"
    - "vibnn hardware acceleration of bayesian neural networks"
    - "e rnn design optimization for efficient recurrent neural networks in fpgas"
    - "neural cache bit serial in cache acceleration of deep neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "bridging the gap between neural networks and neuromorphic hardware with a neural network compiler"

Connected through hyperedge HE-5 (induced by source paper "design automation for efficient deep learning computing"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "amc automl for model compression and acceleration on mobile devices"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "haq hardware aware automated quantization with mixed precision"
    - "pact parameterized clipping activation for quantized neural networks"
    - "mnasnet platform aware neural architecture search for mobile"
    - "learning transferable architectures for scalable image recognition"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"

Connected through hyperedge HE-6 (induced by source paper "optimizing bit serial matrix multiplication for reconfigurable computing"):
  with members:
    - "haq hardware aware automated quantization with mixed precision"
    - "generic and universal parallel matrix summation with a flexible compression goal for xilinx fpgas"
    - "streamlined deployment for quantized neural networks"
    - "finn a framework for fast scalable binarized neural network inference"
    - "espresso efficient forward propagation for bcnns"
    - "quantized neural networks training neural networks with low precision weights and activations"

Connected through hyperedge HE-7 (induced by source paper "haq hardware aware automated quantization with mixed precision"):
  with members:
    - "netadapt platform aware neural network adaptation for mobile applications"
    - "quantizing deep convolutional networks for efficient inference a whitepaper"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "amc automl for model compression and acceleration on mobile devices"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "path level network transformation for efficient architecture search"
    - "pact parameterized clipping activation for quantized neural networks"
    - "efficient neural architecture search via parameter sharing"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)