human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices"
  Abstract: A recent trend in DNN development is to extend the reach of deep learning applications to platforms that are more resource and energy constrained, e.g., mobile devices. These endeavors aim to reduce the DNN model size and improve the hardware processing efficiency, and have resulted in DNNs that are much more compact in their structures and/or have high data sparsity. These compact or sparse models are different from the traditional large ones in that there is much more variation in their layer shapes and sizes, and often require specialized hardware to exploit sparsity for performance improvement. Thus, many DNN accelerators designed for large DNNs do not perform well on these models. In this work, we present Eyeriss v2, a DNN accelerator architecture designed for running compact and sparse DNNs. To deal with the widely varying layer shapes and sizes, it introduces a highly flexible on-chip network, called hierarchical mesh, that can adapt to the different amounts of data reuse and bandwidth requirements of different data types, which improves the utilization of the computation resources. Furthermore, Eyeriss v2 can process sparse data directly in the compressed domain for both weights and activations, and therefore is able to improve both processing speed and energy efficiency with sparse models. Overall, with sparse MobileNet, Eyeriss v2 in a 65nm CMOS process achieves a throughput of 1470.6 inferences/sec and 2560.3 inferences/J at a batch size of 1, which is 12.6x faster and 2.5x more energy efficient than the original Eyeriss running MobileNet. We also present an analysis methodology called Eyexam that provides a systematic way of understanding the performance limits for DNN processors as a function of specific characteristics of the DNN model and accelerator design; it applies these characteristics as sequential steps to increasingly tighten the bound on the performance limits.

Connected through hyperedge HE-1 (induced by source paper "pre defined sparsity for low complexity convolutional neural networks"):
  with members:
    - "pre defined sparse neural networks with hardware acceleration"
    - "scienet deep learning with spike assisted contextual information extraction"
    - "pconv the missing but desirable sparsity in dnn weight pruning for real time execution on mobile devices"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "admm nn an algorithm hardware co design framework of dnns using alternating direction method of multipliers"
    - "a systematic dnn weight pruning framework using alternating direction method of multipliers"
    - "rethinking the value of network pruning"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"

Connected through hyperedge HE-2 (induced by source paper "marvel a decoupled model driven approach for efficiently mapping convolutions on spatial dnn accelerators"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "tvm an automated end to end optimizing compiler for deep learning"
    - "in datacenter performance analysis of a tensor processing unit"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "a systematic approach to blocking convolutional neural networks"
    - "aggregated residual transformations for deep neural networks"

Connected through hyperedge HE-3 (induced by source paper "improving efficiency in neural network accelerator using operands hamming distance optimization"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "deep learning inference in facebook data centers characterization performance optimizations and hardware implications"
    - "mnasnet platform aware neural architecture search for mobile"
    - "in datacenter performance analysis of a tensor processing unit"
    - "hello edge keyword spotting on microcontrollers"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"

Connected through hyperedge HE-4 (induced by source paper "dnn chip predictor an analytical performance predictor for dnn accelerators with various dataflows and hardware architectures"):
  with members:
    - "skynet a champion model for dac sdc on low power object detection"
    - "e2 train training state of the art cnns with over 80 energy savings"
    - "dual dynamic inference enabling more efficient adaptive and controllable deep inference"
    - "dnn dataflow choice is overrated"
    - "scale sim systolic cnn accelerator simulator"
    - "deep k means re training and parameter sharing with harder cluster assignments for compressing deep convolutions"
    - "eie efficient inference engine on compressed deep neural network"
    - "the microsoft 2016 conversational speech recognition system"

Connected through hyperedge HE-5 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram"):
  with members:
    - "generalized intersection over union a metric and a loss for bounding box regression"
    - "in dram bulk bitwise execution engine"
    - "analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator"
    - "amc automl for model compression and acceleration on mobile devices"
    - "high accuracy low precision training"
    - "nullanet training deep neural networks for reduced memory access inference"
    - "towards understanding the role of over parametrization in generalization of neural networks"
    - "tvm an automated end to end optimizing compiler for deep learning"

Connected through hyperedge HE-6 (induced by source paper "rigging the lottery making all tickets winners"):
  with members:
    - "deconstructing lottery tickets zeros signs and the supermask"
    - "parameter efficient training of deep convolutional neural networks by dynamic sparse reparameterization"
    - "the state of sparsity in deep neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "scalable training of artificial neural networks with adaptive sparse connectivity inspired by network science"
    - "the lottery ticket hypothesis finding sparse trainable neural networks"
    - "efficient neural audio synthesis"
    - "snip single shot network pruning based on connection sensitivity"

Connected through hyperedge HE-7 (induced by source paper "gemmini an agile systolic array generator enabling systematic evaluations of deep learning architectures"):
  with members:
    - "integrating nvidia deep learning accelerator nvdla with risc v soc on firesim"
    - "fpsa a full system stack solution for reconfigurable reram based nn accelerator architecture"
    - "co design of deep neural nets and neural net accelerators for embedded vision applications"
    - "dnn dataflow choice is overrated"
    - "vta an open hardware software stack for deep learning"
    - "deep learning inference in facebook data centers characterization performance optimizations and hardware implications"
    - "in datacenter performance analysis of a tensor processing unit"
    - "deep gradient compression reducing the communication bandwidth for distributed training"

Connected through hyperedge HE-8 (induced by source paper "training dnn iot applications for deployment on analog nvm crossbars"):
  with members:
    - "sparse sparse architecture search for cnns on resource constrained microcontrollers"
    - "differentiable quantization of deep neural networks"
    - "accurate deep neural network inference using computational phase change memory"
    - "fixynn efficient hardware for mobile computer vision via transfer learning"
    - "quantizing deep convolutional networks for efficient inference a whitepaper"
    - "haq hardware aware automated quantization with mixed precision"
    - "discovering low precision networks close to full precision networks for efficient embedded inference"
    - "mixed precision quantization of convnets via differentiable neural architecture search"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)