human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "bridging the gap between neural networks and neuromorphic hardware with a neural network compiler"
  Abstract: Different from training common neural networks (NNs) for inference on general-purpose processors, the development of NNs for neuromorphic chips is usually faced with a number of hardware-specific restrictions, including the limited precision of network signals and parameters, constrained computation scale and limited types of non-linear functions. This paper proposes a general methodology to address the challenge. It can transform an existing trained, unrestricted NN (usually for software execution substrate) into an equivalent network that meets the given hardware constraints, which decouples NN applications from target hardware. Formally, the original NN is expressed as a computational graph (CG) that would be fine-tuned part by part according to a topological ordering to become the target CG. Quite a few techniques, including the multilayer-perceptron(MLP)-based universal approximator, a data re-encoding method, a split-and-merge network reconstruction method and a multi-phase weight-tuning algorithm, are proposed to conquer the above restrictions respectively. We have built such a software tool that supports both spiking neural networks (SNNs) and traditional artificial neural networks (ANNs). Its effectiveness has been demonstrated with a real neuromorphic chip and a processing-in-memory (PIM) design. Tests show that the extra inference error caused by this solution is very limited and the transformation time is much less than the retraining time. In addition, quite a few parameter-sensitivity evaluations have been completed to explore the tradeoff between network error, resource consumption and different transformation strategies, which could provide insights for co-design optimization of neuromorphic hardware and software.

Connected through hyperedge HE-1 (induced by source paper "compiling neural networks for a computational memory accelerator"):
  with members:
    - "puma a programmable ultra efficient memristor based accelerator for machine learning inference"
    - "stripe tensor compilation via the nested polyhedral model"
    - "a fast analytical model of fully associative caches"
    - "automated derivation of parametric data movement lower bounds for affine programs"
    - "quantizing deep convolutional networks for efficient inference a whitepaper"
    - "glow graph lowering compiler techniques for neural networks"
    - "rxnn a framework for evaluating deep neural networks on resistive crossbars"
    - "a hardware software blueprint for flexible deep learning specialization"

Connected through hyperedge HE-2 (induced by source paper "non structured dnn weight pruning is it beneficial in any platform"):
  with members:
    - "synetgy algorithm hardware co design for convnet accelerators on embedded fpgas"
    - "adversarial robustness vs model compression or both"
    - "hypar towards hybrid parallelism for deep learning accelerator array"
    - "2pfpce two phase filter pruning based on conditional entropy"
    - "bag of tricks for image classification with convolutional neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "learning and generalization in overparameterized neural networks going beyond two layers"
    - "morph flexible acceleration for 3d cnn based video understanding"

Connected through hyperedge HE-3 (induced by source paper "accelerating generalized linear models with mlweaving a one size fits all system for any precision learning technical report"):
  with members:
    - "high accuracy low precision training"
    - "adaptive communication strategies to achieve the best error runtime trade off in local update sgd"
    - "in rdbms hardware acceleration of advanced analytics"
    - "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing"
    - "vibnn hardware acceleration of bayesian neural networks"
    - "e rnn design optimization for efficient recurrent neural networks in fpgas"
    - "neural cache bit serial in cache acceleration of deep neural networks"
    - "in datacenter performance analysis of a tensor processing unit"

Connected through hyperedge HE-4 (induced by source paper "puma a programmable ultra efficient memristor based accelerator for machine learning inference"):
  with members:
    - "vibnn hardware acceleration of bayesian neural networks"
    - "group scissor scaling neuromorphic computing design to large neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "trannsformer n eural n etwork transform ation for memristive crossbar based neuromorphic system design"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "resparc a reconfigurable and energy efficient architecture with memristive crossbars for deep spiking neural networks"

Connected through hyperedge HE-5 (induced by source paper "crossbar aware neural network pruning"):
  with members:
    - "mec memory efficient convolution for deep neural network"
    - "trannsformer n eural n etwork transform ation for memristive crossbar based neuromorphic system design"
    - "learning intrinsic sparse structures within long short term memory"
    - "thinet a filter level pruning method for deep neural network compression"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "gxnor net training deep neural networks with ternary weights and activations without full precision memory under a unified discretization framework"
    - "channel pruning for accelerating very deep neural networks"
    - "learning structured sparsity in deep neural networks"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.NE(Neural and Evolutionary Computing)