human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "simultaneous multi layer access a high bandwidth and low cost 3d stacked memory interface"
  Abstract: Limited memory bandwidth is a critical bottleneck in modern systems. 3D-stacked DRAM enables higher bandwidth by leveraging wider Through-Silicon-Via (TSV) channels, but today’s systems cannot fully exploit them due to the limited internal bandwidth of DRAM. DRAM reads a whole row simultaneously from the cell array to a row buffer, but can transfer only a fraction of the data from the row buffer to peripheral IO circuit, through a limited and expensive set of wires referred to as global bitlines. In presence of wider memory channels, the major bottleneck becomes the limited data transfer capacity through these global bitlines. Our goal in this work is to enable higher bandwidth in 3D-stacked DRAM without the increased cost of adding more global bitlines. We instead exploit otherwise-idle resources, such as global bitlines, already existing within the multiple DRAM layers by accessing the layers simultaneously. Our architecture, Simultaneous Multi Layer Access (SMLA), provides higher bandwidth by aggregating the internal bandwidth of multiple layers and transferring the available data at a higher IO frequency. To implement SMLA, simultaneous data transfer from multiple layers through the same IO TSVs requires coordination between layers to avoid channel conflict. We first study coordination by static partitioning, which we call Dedicated-IO, that assigns groups of TSVs to each layer. We then provide a simple, yet sophisticated mechanism, called Cascaded-IO, which enables simultaneous access to each layer by time-multiplexing the IOs, while also reducing design effort. By operating at a frequency proportional to the number of layers, SMLA provides a higher bandwidth (4X for a four-layer stacked DRAM). Our evaluations show that SMLA provides significant performance improvement and energy reduction (55%/18% on average for multi-programmed workloads, respectively) over a baseline 3D-stacked DRAM with very low area overhead.

Connected through hyperedge HE-1 (induced by source paper "what your dram power models are not telling you lessons from a detailed experimental study"):
  with members:
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "understanding and improving the latency of dram based memory systems"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"
    - "bigdatabench a big data benchmark suite from internet services"

Connected through hyperedge HE-2 (induced by source paper "the rowhammer problem and other issues we may face as memory becomes denser"):
  with members:
    - "rowhammer reliability analysis and security implications"
    - "reducing dram latency by exploiting design induced latency variation in modern dram chips"
    - "rowhammer js a remote software induced fault attack in javascript"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-3 (induced by source paper "understanding reduced voltage operation in modern dram chips characterization analysis and mechanisms"):
  with members:
    - "understanding and improving the latency of dram based memory systems"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)