human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "a high throughput energy efficient implementation of successive cancellation decoder for polar codes using combinational logic"
  Abstract: This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favorable tradeoff between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.

Connected through hyperedge HE-1 (induced by source paper "a multi kernel multi code polar decoder architecture"):
  with members:
    - "on puncturing strategies for polar codes"
    - "fast and flexible successive cancellation list decoders for polar codes"
    - "low complexity puncturing and shortening of polar codes"
    - "minimum distance based construction of multi kernel polar codes"
    - "multi mode unrolled architectures for polar decoders"
    - "multi kernel construction of polar codes"
    - "tc throughput centric successive cancellation decoder hardware implementation for polar codes"
    - "fast polar decoders algorithm and implementation"

Connected through hyperedge HE-2 (induced by source paper "fast low complexity decoders for low rate polar codes"):
  with members:
    - "fast polar decoders algorithm and implementation"
    - "enabling complexity performance trade offs for successive cancellation decoding of polar codes"
    - "how to construct polar codes"
    - "hardware architectures for successive cancellation decoding of polar codes"
    - "performance and construction of polar codes on symmetric binary input memoryless channels"
    - "channel polarization a method for constructing capacity achieving codes for symmetric binary input memoryless channels"

Connected through hyperedge HE-3 (induced by source paper "comparison of polar decoders with existing low density parity check and turbo decoders"):
  with members:
    - "fast low complexity decoders for low rate polar codes"
    - "llr based successive cancellation list decoder for polar codes with multibit decision"
    - "partitioned successive cancellation list decoding of polar codes"
    - "multi mode unrolled architectures for polar decoders"
    - "a high throughput list decoder architecture for polar codes"
    - "hardware decoders for polar codes an overview"
    - "fast list decoders for polar codes"
    - "symbol decision successive cancellation list decoder for polar codes"

Connected through hyperedge HE-4 (induced by source paper "channel capacity of polar coding with a given polar mismatched successive cancellation decoder"):
  with members:
    - "a simple proof of fast polarization"
    - "on the scaling exponent of polar codes for binary input energy harvesting channels"
    - "a split reduced successive cancellation list decoder for polar codes"
    - "a low latency list successive cancellation decoding implementation for polar codes"
    - "a high throughput list decoder architecture for polar codes"
    - "fast list decoders for polar codes"
    - "symbol decision successive cancellation list decoder for polar codes"
    - "polar coding for processes with memory"

Connected through hyperedge HE-5 (induced by source paper "a low latency list successive cancellation decoding implementation for polar codes"):
  with members:
    - "symbol decision successive cancellation list decoder for polar codes"
    - "on metric sorting for successive cancellation list decoding of polar codes"
    - "llr based successive cancellation list decoding of polar codes"
    - "low latency list decoding of polar codes with double thresholding"
    - "symbol based successive cancellation list decoder for polar codes"
    - "fast polar decoders algorithm and implementation"
    - "finite length scaling for polar codes"
    - "increasing the speed of polar list decoders"

Connected through hyperedge HE-6 (induced by source paper "hardware decoders for polar codes an overview"):
  with members:
    - "symbol decision successive cancellation list decoder for polar codes"
    - "237 gbit s unrolled hardware polar decoder"
    - "on metric sorting for successive cancellation list decoding of polar codes"
    - "llr based successive cancellation list decoding of polar codes"
    - "unrolled polar decoders part i hardware architectures"
    - "low latency list decoding of polar codes with double thresholding"
    - "low complexity belief propagation polar code decoders"
    - "fast polar decoders algorithm and implementation"

Connected through hyperedge HE-7 (induced by source paper "on scaling rules for energy of vlsi polar encoders and decoders"):
  with members:
    - "information friction and its implications on minimum energy required for communication"
    - "towards approaching total power capacity transmit and decoding power minimization for ldpc codes"
    - "finite length scaling for polar codes"
    - "energy consumption of vlsi decoders"
    - "polar codes speed of polarization and polynomial gap to capacity"
    - "improved bounds on the finite length scaling of polar codes"
    - "hardware architectures for successive cancellation decoding of polar codes"
    - "channel polarization a method for constructing capacity achieving codes for symmetric binary input memoryless channels"

Connected through hyperedge HE-8 (induced by source paper "multi mode unrolled architectures for polar decoders"):
  with members:
    - "fast low complexity decoders for low rate polar codes"
    - "flexible and low complexity encoding and decoding of systematic polar codes"
    - "237 gbit s unrolled hardware polar decoder"
    - "fast polar decoders algorithm and implementation"
    - "a scalable successive cancellation decoder for polar codes"
    - "hardware implementation of successive cancellation decoders for polar codes"
    - "how to construct polar codes"
    - "channel polarization a method for constructing capacity achieving codes for symmetric binary input memoryless channels"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)