human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "energy efficient time domain vector by matrix multiplier for neurocomputing and beyond"
  Abstract: We propose an extremely energy-efficient mixed-signal approach for performing vector-by-matrix multiplication in a time domain. In such implementation, multi-bit values of the input and output vector elements are represented with time-encoded digital signals, while multi-bit matrix weights are realized with current sources, e.g. transistors biased in subthreshold regime. With our approach, multipliers can be chained together to implement large-scale circuits completely in a time domain. Multiplier operation does not rely on energy-taxing static currents, which are typical for peripheral and input/output conversion circuits of the conventional mixed-signal implementations. As a case study, we have designed a multilayer perceptron, based on two layers of 10x10 four-quadrant vector-by-matrix multipliers, in 55-nm process with embedded NOR flash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based on memory cell measurements, shows that at high computing speed the drain-induced barrier lowering is a major factor limiting multiplier precision to ~6 bit. Post-layout estimates for a conservative 6-bit digital input/output NxN multiplier designed in 55 nm process, including I/O circuitry for converting between digital and time domain representations, show ~7 fJ/Op for N>200, which can be further lowered well below 1 fJ/Op for more optimal and aggressive design.

Connected through hyperedge HE-1 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design"):
  with members:
    - "biologically inspired alternatives to backpropagation through time for learning in recurrent neural nets"
    - "deep learning in spiking neural networks"
    - "temporal coding in spiking neural networks with alpha synaptic function"
    - "surrogate gradient learning in spiking neural networks"
    - "an energy efficient time domain analog vlsi neural network processor based on a pulse width modulation approach"
    - "supervised learning in spiking neural networks with phase change memory synapses"
    - "a time domain analog weighted sum calculation model for extremely low power vlsi implementation of multi layer neural networks"
    - "multiscale co design analysis of energy latency area and accuracy of a reram analog neural training accelerator"

Connected through hyperedge HE-2 (induced by source paper "benchmarking physical performance of neural inference circuits"):
  with members:
    - "enabling spike based backpropagation in state of the art deep neural network architectures"
    - "large scale neuromorphic spiking array processors a quest to mimic the brain"
    - "multiscale co design analysis of energy latency area and accuracy of a reram analog neural training accelerator"
    - "benchmarking inverse rashba edelstein magnetoelectric devices for neuromorphic computing"
    - "benchmarking keyword spotting efficiency on neuromorphic hardware"
    - "an analysis of deep neural network models for practical applications"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "a survey of neuromorphic computing and neural networks in hardware"

Connected through hyperedge HE-3 (induced by source paper "3d acortex an ultra compact energy efficient neurocomputing platform based on commercial 3d nand flash memories"):
  with members:
    - "puma a programmable ultra efficient memristor based accelerator for machine learning inference"
    - "a behavioral compact model for static characteristics of 3d nand flash memory"
    - "a time domain analog weighted sum calculation model for extremely low power vlsi implementation of multi layer neural networks"
    - "alternating multi bit quantization for recurrent neural networks"
    - "discovering low precision networks close to full precision networks for efficient embedded inference"
    - "rapidnn in memory deep neural network acceleration framework"
    - "deep learning for iot big data and streaming analytics a survey"
    - "quantized neural networks training neural networks with low precision weights and activations"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)