human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "synthesis of fault tolerant reversible logic circuits"
  Abstract: Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

Connected through hyperedge HE-1 (induced by source paper "designing parity preserving reversible circuits"):
  with members:
    - "synthesis and optimization of reversible circuits a survey"
    - "design of parity preserving logic based fault tolerant reversible arithmetic logic unit"

Connected through hyperedge HE-2 (induced by source paper "fault tolerant variable block carry skip logic vbcsl using parity preserving reversible gates"):
  with members:
    - "variable block carry skip logic using reversible gates"
    - "reversible logic synthesis of fault tolerant carry skip bcd adder"
    - "fault tolerant reversible logic synthesis carry look ahead and carry skip adders"

Connected through hyperedge HE-3 (induced by source paper "efficient approaches for designing fault tolerant reversible carry look ahead and carry skip adders"):
  with members:
    - "variable block carry skip logic using reversible gates"

Connected through hyperedge HE-4 (induced by source paper "fault tolerant reversible logic synthesis carry look ahead and carry skip adders"):
  with members:
    - "variable block carry skip logic using reversible gates"
    - "reversible logic synthesis of fault tolerant carry skip bcd adder"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)