human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "introducing a performance model for bandwidth limited loop kernels"
  Abstract: We present a performance model for bandwidth limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.

Connected through hyperedge HE-1 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-2 (induced by source paper "a mechanism for balancing accuracy and scope in cross machine black box gpu performance modeling"):
  with members:
    - "learning to optimize tensor programs"
    - "opencl performance prediction using architecture independent features"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "loo py from fortran to performance via transformation and substitution rules"
    - "loo py transformation based code generation for gpus and cpus"

Connected through hyperedge HE-3 (induced by source paper "an ecm based energy efficiency optimization approach for bandwidth limited streaming kernels on recent intel xeon processors"):
  with members:
    - "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "exploring performance and power properties of modern multicore chips via simple machine models"

Connected through hyperedge HE-4 (induced by source paper "performance analysis of the kahan enhanced scalar product on current multi and manycore processors"):
  with members:
    - "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"

Connected through hyperedge HE-5 (induced by source paper "multi dimensional intra tile parallelization for memory starved stencil computations"):
  with members:
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "optimizing the performance of streaming numerical kernels on the ibm blue gene p powerpc 450 processor"
    - "efficient multicore aware parallelization strategies for iterative stencil computations"
    - "leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters"

Connected through hyperedge HE-6 (induced by source paper "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"):
  with members:
    - "execution cache memory performance model introduction and validation"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "exploring performance and power properties of modern multicore chips via simple machine models"

Connected through hyperedge HE-7 (induced by source paper "quantifying performance bottlenecks of stencil computations using the execution cache memory model"):
  with members:
    - "exploring performance and power properties of modern multicore chips via simple machine models"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-8 (induced by source paper "execution cache memory performance model introduction and validation"):
  with members:
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)