human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "unrolled polar decoders part i hardware architectures"
  Abstract: This is the first in a two-part series of papers on unrolled polar decoders. In this paper (Part I), we present a family of architectures for hardware polar decoders using a reduced-complexity successive-cancellation decoding algorithm. The resulting fully-unrolled architectures are capable of achieving a coded throughput in excess of 400 Gbps on an FPGA, two orders of magnitude greater than current state-of-the-art polar decoders. Moreover, the proposed architectures are flexible in a way that makes it possible to explore the trade-off between resource usage and throughput.

Connected through hyperedge HE-1 (induced by source paper "hardware decoders for polar codes an overview"):
  with members:
    - "symbol decision successive cancellation list decoder for polar codes"
    - "237 gbit s unrolled hardware polar decoder"
    - "on metric sorting for successive cancellation list decoding of polar codes"
    - "llr based successive cancellation list decoding of polar codes"
    - "low latency list decoding of polar codes with double thresholding"
    - "low complexity belief propagation polar code decoders"
    - "fast polar decoders algorithm and implementation"
    - "a reduced latency list decoding algorithm for polar codes"

Connected through hyperedge HE-2 (induced by source paper "a high throughput energy efficient implementation of successive cancellation decoder for polar codes using combinational logic"):
  with members:
    - "soft decision decoding of reed muller codes recursive lists"
    - "llr based successive cancellation list decoding of polar codes"
    - "fast polar decoders algorithm and implementation"
    - "a scalable successive cancellation decoder for polar codes"
    - "list decoding of polar codes"
    - "reduced latency sc polar decoder architectures"
    - "hardware architectures for successive cancellation decoding of polar codes"
    - "channel polarization a method for constructing capacity achieving codes for symmetric binary input memoryless channels"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)