human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "simple dram and virtual memory abstractions to enable highly efficient memory systems"
  Abstract: In most modern systems, the memory subsystem is managed and accessed at multiple different granularities at various resources. We observe that such multi-granularity management results in significant inefficiency in the memory subsystem. Specifically, we observe that 1) page-granularity virtual memory unnecessarily triggers large memory operations, and 2) existing cache-line granularity memory interface is inefficient for performing bulk data operations and operations that exhibit poor spatial locality. To address these problems, we present a series of techniques in this thesis. #R##N#First, we propose page overlays, a framework augments the existing virtual memory framework with the ability to track a new version of a subset of cache lines within each virtual page. We show that this extension is powerful by demonstrating its benefits on a number of applications. #R##N#Second, we show that DRAM can be used to perform more complex operations than just store data. We propose RowClone, a mechanism to perform bulk data copy and initialization completely inside DRAM, and Buddy RAM, a mechanism to perform bulk bitwise operations using DRAM. Both these techniques achieve an order-of-magnitude improvement in the efficiency of the respective operations. #R##N#Third, we propose Gather-Scatter DRAM, a technique that exploits DRAM organization to effectively gather/scatter values with a power-of-2 strided access patterns. For these access patterns, GS-DRAM achieves near-ideal bandwidth and cache utilization, without increasing the latency of fetching data from memory. #R##N#Finally, we propose the Dirty-Block Index, a new way of tracking dirty blocks. In addition to improving the efficiency of bulk data coherence, DBI has several applications including high-performance memory scheduling, efficient cache lookup bypassing, and enabling heterogeneous ECC.

Connected through hyperedge HE-1 (induced by source paper "processing data where it makes sense enabling in memory computation"):
  with members:
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "architectural techniques for improving nand flash memory reliability"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "techniques for shared resource management in systems with throughput processors"
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "using ecc dram to adaptively increase memory capacity"

Connected through hyperedge HE-2 (induced by source paper "large scale studies of memory storage and network failures in a modern data center"):
  with members:
    - "architectural techniques for improving nand flash memory reliability"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "nethammer inducing rowhammer faults through network requests"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "banshee bandwidth efficient dram caching via software hardware cooperation"
    - "another flip in the wall of rowhammer defenses"
    - "the rowhammer problem and other issues we may face as memory becomes denser"

Connected through hyperedge HE-3 (induced by source paper "in dram bulk bitwise execution engine"):
  with members:
    - "shouji a fast and efficient pre alignment filter for sequence alignment"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "neural cache bit serial in cache acceleration of deep neural networks"
    - "understanding reduced voltage operation in modern dram chips characterization analysis and mechanisms"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-4 (induced by source paper "enabling the adoption of processing in memory challenges mechanisms future research directions"):
  with members:
    - "using ecc dram to adaptively increase memory capacity"
    - "lazypim efficient support for cache coherence in processing in memory architectures"
    - "understanding and improving the latency of dram based memory systems"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "rowhammer reliability analysis and security implications"
    - "buddy ram improving the performance and efficiency of bulk bitwise operations using dram"
    - "the processing using memory paradigm in dram bulk copy initialization bitwise and and or"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-5 (induced by source paper "what your dram power models are not telling you lessons from a detailed experimental study"):
  with members:
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "understanding and improving the latency of dram based memory systems"
    - "simultaneous multi layer access a high bandwidth and low cost 3d stacked memory interface"
    - "improving dram performance by parallelizing refreshes with accesses"
    - "bigdatabench a big data benchmark suite from internet services"

Connected through hyperedge HE-6 (induced by source paper "d range using commodity dram devices to generate true random numbers with low latency and high throughput"):
  with members:
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "nano intrinsic true random number generation"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "improving dram performance by parallelizing refreshes with accesses"
    - "ensuring high quality randomness in cryptographic key generation"

Connected through hyperedge HE-7 (induced by source paper "understanding reduced voltage operation in modern dram chips characterization analysis and mechanisms"):
  with members:
    - "understanding and improving the latency of dram based memory systems"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "simultaneous multi layer access a high bandwidth and low cost 3d stacked memory interface"
    - "improving dram performance by parallelizing refreshes with accesses"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)