human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "logic locking for secure outsourced chip fabrication a new attack and provably secure defense mechanism"
  Abstract: Chip designers outsource chip fabrication to external foundries, but at the risk of IP theft. Logic locking, a promising solution to mitigate this threat, adds extra logic gates (key gates) and inputs (key bits) to the chip so that it functions correctly only when the correct key, known only to the designer but not the foundry, is applied. In this paper, we identify a new vulnerability in all existing logic locking schemes. Prior attacks on logic locking have assumed that, in addition to the design of the locked chip, the attacker has access to a working copy of the chip. Our attack does not require a working copy and yet we successfully recover a significant fraction of key bits from the design of the locked chip only. Empirically, we demonstrate the success of our attack on eight large benchmark circuits from a benchmark suite that has been tailored specifically for logic synthesis research, for two different logic locking schemes. Then, to address this vulnerability, we initiate the study of provably secure logic locking mechanisms. We formalize, for the first time to our knowledge, a precise notion of security for logic locking. We establish that any locking procedure that is secure under our definition is guaranteed to counter our desynthesis attack, and all other such known attacks. We then devise a new logic locking procedure, Meerkat, that guarantees that the locked chip reveals no information about the key or the designer's intended functionality. A main insight behind Meerkat is that canonical representations of boolean functionality via Reduced Ordered Binary Decision Diagrams (ROBDDs) can be leveraged effectively to provide security. We analyze Meerkat with regards to its security properties and the overhead it incurs. As such, our work is a contribution to both the foundations and practice of securing digital ICs.

Connected through hyperedge HE-1 (induced by source paper "hardware security for and beyond cmos technology an overview on fundamentals applications and challenges"):
  with members:
    - "towards secure composition of integrated circuits and electronic systems on the role of eda"
    - "exploiting spin orbit torque devices as reconfigurable logic for circuit obfuscation"
    - "smart secure magnetoelectric antiferromagnet based tamper proof non volatile memory"
    - "a modern approach to ip protection and trojan prevention split manufacturing for 3d ics and obfuscation of vertical interconnects"
    - "a new paradigm in split manufacturing lock the feol unlock at the beol"
    - "spin orbit torque devices for hardware security from deterministic to probabilistic regime"
    - "protect your chip design intellectual property an overview"
    - "zombieload cross privilege boundary data sampling"

Connected through hyperedge HE-2 (induced by source paper "defense in depth a recipe for logic locking to prevail"):
  with members:
    - "functional analysis attacks on logic locking"
    - "taal tampering attack on any key based logic locked circuits"
    - "threats on logic locking a decade later"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "physical design obfuscation of hardware a comprehensive investigation of device and logic level techniques"
    - "threshold based obfuscated keys with quantifiable security against invasive readout"

Connected through hyperedge HE-3 (induced by source paper "opening the doors to dynamic camouflaging harnessing the power of polymorphic devices"):
  with members:
    - "advancing hardware security using polymorphic and stochastic spin hall effect devices"
    - "a proposal for energy efficient cellular neural network based on spintronic devices"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)