human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "matic learning around errors for efficient low voltage neural network accelerators"
  Abstract: As a result of the increasing demand for deep neural network (DNN)-based services, efforts to develop dedicated hardware accelerators for DNNs are growing rapidly. However,while accelerators with high performance and efficiency on convolutional deep neural networks (Conv-DNNs) have been developed, less progress has been made with regards to fully-connected DNNs (FC-DNNs). In this paper, we propose MATIC (Memory Adaptive Training with In-situ Canaries), a methodology that enables aggressive voltage scaling of accelerator weight memories to improve the energy-efficiency of DNN accelerators. To enable accurate operation with voltage overscaling, MATIC combines the characteristics of destructive SRAM reads with the error resilience of neural networks in a memory-adaptive training process. Furthermore, PVT-related voltage margins are eliminated using bit-cells from synaptic weights as in-situ canaries to track runtime environmental variation. Demonstrated on a low-power DNN accelerator that we fabricate in 65 nm CMOS, MATIC enables up to 60-80 mV of voltage overscaling (3.3x total energy reduction versus the nominal voltage), or 18.6x application error reduction.

Connected through hyperedge HE-1 (induced by source paper "automated design of error resilient and hardware efficient deep neural networks"):
  with members:
    - "understanding and robustifying differentiable architecture search"
    - "auto deeplab hierarchical neural architecture search for semantic image segmentation"
    - "autodispnet improving disparity estimation with automl"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "dpp net device aware progressive search for pareto optimal neural architectures"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "methods for interpreting and understanding deep neural networks"
    - "path level network transformation for efficient architecture search"

Connected through hyperedge HE-2 (induced by source paper "ft clipact resilience analysis of deep neural networks and improving their fault tolerance using clipped activation"):
  with members:
    - "in datacenter performance analysis of a tensor processing unit"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "eie efficient inference engine on compressed deep neural network"
    - "deep compression compressing deep neural networks with pruning trained quantization and huffman coding"
    - "very deep convolutional networks for large scale image recognition"

Connected through hyperedge HE-3 (induced by source paper "evaluating built in ecc of fpga on chip memories for the mitigation of undervolting faults"):
  with members:
    - "thundervolt enabling aggressive voltage underscaling and timing error resilience for energy efficient deep neural network accelerators"
    - "a survey of fpga based neural network accelerator"
    - "deep learning with limited numerical precision"

Connected through hyperedge HE-4 (induced by source paper "exploiting errors for efficiency a survey from circuits to algorithms"):
  with members:
    - "incremental color quantization for color vision deficient observers using mobile gaming data"
    - "probabilistic value deviation bounded integer codes for approximate communication"
    - "in datacenter performance analysis of a tensor processing unit"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"
    - "reconfiguring the imaging pipeline for computer vision"
    - "sound mixed precision optimization with rewriting"
    - "energy reliability limits in nanoscale circuits"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.NE(Neural and Evolutionary Computing)