human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "origami a 803 gop s w convolutional network accelerator"
  Abstract: An ever-increasing number of computer vision and image/video processing challenges are being approached using deep convolutional neural networks, obtaining state-of-the-art results in object recognition and detection, semantic segmentation, action recognition, optical flow, and super resolution. Hardware acceleration of these algorithms is essential to adopt these improvements in embedded and mobile computer vision systems. We present a new architecture, design, and implementation, as well as the first reported silicon measurements of such an accelerator, outperforming previous work in terms of power, area, and I/O efficiency. The manufactured device provides up to 196 GOp/s on 3.09    $\text {mm}^{2}$    of silicon in UMC 65-nm technology and can achieve a power efficiency of 803 GOp/s/W. The massively reduced bandwidth requirements make it the first architecture scalable to TOp/s performance.

Connected through hyperedge HE-1 (induced by source paper "pulp nn accelerating quantized neural networks on parallel ultra low power risc v processors"):
  with members:
    - "a 64 mw dnn based visual navigation engine for autonomous nano drones"
    - "memory driven mixed low precision quantization for enabling deep network inference on microcontrollers"
    - "xnor neural engine a hardware accelerator ip for 21 6 fj op binary neural network inference"
    - "haq hardware aware automated quantization with mixed precision"
    - "neura ghe exploiting cpu fpga synergies for efficient and flexible cnn inference acceleration on zynq socs"
    - "pact parameterized clipping activation for quantized neural networks"
    - "cmsis nn efficient neural network kernels for arm cortex m cpus"
    - "minimum energy quantized neural networks"

Connected through hyperedge HE-2 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram"):
  with members:
    - "generalized intersection over union a metric and a loss for bounding box regression"
    - "in dram bulk bitwise execution engine"
    - "analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator"
    - "amc automl for model compression and acceleration on mobile devices"
    - "high accuracy low precision training"
    - "nullanet training deep neural networks for reduced memory access inference"
    - "towards understanding the role of over parametrization in generalization of neural networks"
    - "tvm an automated end to end optimizing compiler for deep learning"

Connected through hyperedge HE-3 (induced by source paper "ebpc extended bit plane compression for deep neural network inference and training accelerators"):
  with members:
    - "and the bit goes down revisiting the quantization of neural networks"
    - "additive noise annealing and approximation properties of quantized neural networks"
    - "a 64 mw dnn based visual navigation engine for autonomous nano drones"
    - "rpr random partition relaxation for training binary and ternary weight neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "yolov3 an incremental improvement"
    - "shufflenet v2 practical guidelines for efficient cnn architecture design"
    - "multiposenet fast multi person pose estimation using pose residual network"

Connected through hyperedge HE-4 (induced by source paper "rpr random partition relaxation for training binary and ternary weight neural networks"):
  with members:
    - "ebpc extended bit plane compression for deep neural network inference and training accelerators"
    - "improving neural network quantization without retraining using outlier channel splitting"
    - "quantization networks"
    - "fann on mcu an open source toolkit for energy efficient neural network inference at the edge of the internet of things"
    - "hawq hessian aware quantization of neural networks with mixed precision"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "fbnet hardware aware efficient convnet design via differentiable neural architecture search"
    - "lq nets learned quantization for highly accurate and compact deep neural networks"

Connected through hyperedge HE-5 (induced by source paper "mapping high performance rnns to in memory neuromorphic chips"):
  with members:
    - "an ultra low power sigma delta neuron circuit"
    - "a 0 086 mm 2 12 7 pj sop 64k synapse 256 neuron online learning digital spiking neuromorphic processor in 28 nm cmos"
    - "independently recurrent neural network indrnn building a longer and deeper rnn"
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "overcoming the vanishing gradient problem in plain recurrent networks"
    - "speech commands a dataset for limited vocabulary speech recognition"
    - "an empirical evaluation of generic convolutional and recurrent networks for sequence modeling"
    - "a scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors dynaps"

Connected through hyperedge HE-6 (induced by source paper "tuning algorithms and generators for efficient edge inference"):
  with members:
    - "synetgy algorithm hardware co design for convnet accelerators on embedded fpgas"
    - "fully learnable group convolution for acceleration of deep neural networks"
    - "bridging the accuracy gap for 2 bit quantized neural networks qnn"
    - "learning grouped convolution for efficient domain adaptation"
    - "mpdcompress matrix permutation decomposition algorithm for deep neural network compression"
    - "chamnet towards efficient network design through platform aware model adaptation"
    - "block sparse recurrent neural networks"
    - "in datacenter performance analysis of a tensor processing unit"

Connected through hyperedge HE-7 (induced by source paper "a neuromorphic boost to rnns using low pass filters"):
  with members:
    - "an ultra low power sigma delta neuron circuit"
    - "a neuromorphic systems approach to in memory computing with non ideal memristive devices from mitigation to exploitation"
    - "independently recurrent neural network indrnn building a longer and deeper rnn"
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "overcoming the vanishing gradient problem in plain recurrent networks"
    - "speech commands a dataset for limited vocabulary speech recognition"
    - "an empirical evaluation of generic convolutional and recurrent networks for sequence modeling"
    - "a scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors dynaps"

Connected through hyperedge HE-8 (induced by source paper "benchmarking physical performance of neural inference circuits"):
  with members:
    - "enabling spike based backpropagation in state of the art deep neural network architectures"
    - "large scale neuromorphic spiking array processors a quest to mimic the brain"
    - "multiscale co design analysis of energy latency area and accuracy of a reram analog neural training accelerator"
    - "benchmarking inverse rashba edelstein magnetoelectric devices for neuromorphic computing"
    - "benchmarking keyword spotting efficiency on neuromorphic hardware"
    - "an analysis of deep neural network models for practical applications"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "a survey of neuromorphic computing and neural networks in hardware"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CV(Computer Vision and Pattern Recognition)