human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "kerncraft a tool for analytic performance modeling of loop kernels"
  Abstract: Achieving optimal program performance requires deep insight into the interaction between hardware and software. For software developers without an in-depth background in computer architecture, understanding and fully utilizing modern architectures is close to impossible. Analytic loop performance modeling is a useful way to understand the relevant bottlenecks of code execution based on simple machine models. The Roofline Model and the Execution-Cache-Memory (ECM) model are proven approaches to performance modeling of loop nests. In comparison to the Roofline model, the ECM model can also describes the single-core performance and saturation behavior on a multicore chip.We give an introduction to the Roofline and ECM models, and to stencil performance modeling using layer conditions (LC). We then present Kerncraft, a tool that can automatically construct Roofline and ECM models for loop nests by performing the required code, data transfer, and LC analysis. The layer condition analysis allows to predict optimal spatial blocking factors for loop nests. Together with the models it enables an ab-initio estimate of the potential benefits of loop blocking optimizations and of useful block sizes. In cases where LC analysis is not easily possible, Kerncraft supports a cache simulator as a fallback option. Using a 25-point long-range stencil we demonstrate the usefulness and predictive power of the Kerncraft tool.

Connected through hyperedge HE-1 (induced by source paper "collecting and presenting reproducible intranode stencil performance inspect"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-2 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-3 (induced by source paper "bridging the architecture gap abstracting performance relevant properties of modern server processors"):
  with members:
    - "analytic performance modeling and analysis of detailed neuron simulations"
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "an ecm based energy efficiency optimization approach for bandwidth limited streaming kernels on recent intel xeon processors"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-4 (induced by source paper "a mechanism for balancing accuracy and scope in cross machine black box gpu performance modeling"):
  with members:
    - "learning to optimize tensor programs"
    - "opencl performance prediction using architecture independent features"
    - "loo py from fortran to performance via transformation and substitution rules"
    - "loo py transformation based code generation for gpus and cpus"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-5 (induced by source paper "automatic throughput and critical path analysis of x86 and arm assembly kernels"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "ithemal accurate portable and fast basic block throughput estimation using deep neural networks"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"

Connected through hyperedge HE-6 (induced by source paper "dynamic load balancing techniques for particulate flow simulations"):
  with members:
    - "lattice boltzmann benchmark kernels as a testbed for performance analysis"
    - "extreme scale block structured adaptive mesh refinement"
    - "a comparative study of fluid particle coupling methods for fully resolved lattice boltzmann simulations"
    - "massively parallel algorithms for the lattice boltzmann method on nonuniform grids"
    - "ultrascale simulations of non smooth granular dynamics"
    - "recent advances in graph partitioning"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-7 (induced by source paper "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"):
  with members:
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "the energy frequency convexity rule modeling and experimental validation on mobile devices"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"
    - "exploring performance and power properties of modern multicore chips via simple machine models"

Connected through hyperedge HE-8 (induced by source paper "automated instruction stream throughput prediction for intel and amd microarchitectures"):
  with members:
    - "ithemal accurate portable and fast basic block throughput estimation using deep neural networks"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)