human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "a survey of fpga based neural network accelerator"
  Abstract: Recent researches on neural network have shown significant advantage in machine learning over traditional algorithms based on handcrafted features and models. Neural network is now widely adopted in regions like image, speech and video recognition. But the high computation and storage complexity of neural network inference poses great difficulty on its application. CPU platforms are hard to offer enough computation capacity. GPU platforms are the first choice for neural network process because of its high computation capacity and easy to use development frameworks. #R##N#On the other hand, FPGA-based neural network inference accelerator is becoming a research topic. With specifically designed hardware, FPGA is the next possible solution to surpass GPU in speed and energy efficiency. Various FPGA-based accelerator designs have been proposed with software and hardware optimization techniques to achieve high speed and energy efficiency. In this paper, we give an overview of previous work on neural network inference accelerators based on FPGA and summarize the main techniques used. An investigation from software to hardware, from circuit level to system level is carried out to complete analysis of FPGA-based neural network inference accelerator design and serves as a guide to future work.

Connected through hyperedge HE-1 (induced by source paper "the deep learning compiler a comprehensive survey"):
  with members:
    - "shredder learning noise distributions to protect inference privacy"
    - "fusionstitching boosting execution efficiency of memory intensive computations for dl workloads"
    - "stripe tensor compilation via the nested polyhedral model"
    - "tensorflow eager a multi stage python embedded dsl for machine learning"
    - "privacy for rescue a new testimony why privacy is vulnerable in deep models"
    - "dissecting the graphcore ipu architecture via microbenchmarking"
    - "benchmarking tpu gpu and cpu platforms for deep learning"
    - "a comprehensive survey on graph neural networks"

Connected through hyperedge HE-2 (induced by source paper "lutnet learning fpga configurations for highly efficient neural network inference"):
  with members:
    - "lutnet rethinking inference in fpga soft logic"
    - "focused quantization for sparse cnns"
    - "deep neural network approximation for custom hardware where we ve been where we re going"
    - "toolflows for mapping convolutional neural networks on fpgas a survey and future directions"
    - "in datacenter performance analysis of a tensor processing unit"
    - "towards accurate binary convolutional neural network"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "rebnet residual binarized neural network"

Connected through hyperedge HE-3 (induced by source paper "puma a programmable ultra efficient memristor based accelerator for machine learning inference"):
  with members:
    - "vibnn hardware acceleration of bayesian neural networks"
    - "group scissor scaling neuromorphic computing design to large neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "bridging the gap between neural networks and neuromorphic hardware with a neural network compiler"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "trannsformer n eural n etwork transform ation for memristive crossbar based neuromorphic system design"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"

Connected through hyperedge HE-4 (induced by source paper "mixed precision dnns all you need is a good parametrization"):
  with members:
    - "understanding straight through estimator in training activation quantized neural nets"
    - "learning low precision neural networks without straight through estimator ste"
    - "learned step size quantization"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "proxquant quantized neural networks via proximal operators"
    - "relaxed quantization for discretized neural networks"
    - "iteratively training look up tables for network quantization"
    - "incremental network quantization towards lossless cnns with low precision weights"

Connected through hyperedge HE-5 (induced by source paper "survey and benchmarking of machine learning accelerators"):
  with members:
    - "dla compiler and fpga overlay for neural network inference acceleration"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "an analysis of deep neural network models for practical applications"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "mixed precision training"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "ssd single shot multibox detector"

Connected through hyperedge HE-6 (induced by source paper "evaluating built in ecc of fpga on chip memories for the mitigation of undervolting faults"):
  with members:
    - "thundervolt enabling aggressive voltage underscaling and timing error resilience for energy efficient deep neural network accelerators"
    - "matic learning around errors for efficient low voltage neural network accelerators"
    - "deep learning with limited numerical precision"

Connected through hyperedge HE-7 (induced by source paper "intermediate deep feature compression the next battlefield of intelligent sensing"):
  with members:
    - "yolov3 an incremental improvement"
    - "deep feature compression for collaborative object detection"
    - "effective multi query expansions collaborative deep networks for robust landmark retrieval"
    - "stack captioning coarse to fine learning for image captioning"
    - "compact descriptors for video analysis the emerging mpeg standard"
    - "ai oriented large scale video management for smart city technologies standards and beyond"
    - "deep image retrieval learning global representations for image search"
    - "end to end learning for self driving cars"

Connected through hyperedge HE-8 (induced by source paper "a survey of fpga based deep learning accelerators challenges and opportunities"):
  with members:
    - "finn l library extensions and design trade off analysis for variable precision lstm networks on fpgas"
    - "towards efficient convolutional neural network for domain specific applications on fpga"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "ternary weight networks"
    - "trained ternary quantization"
    - "deep compression compressing deep neural networks with pruning trained quantization and huffman coding"
    - "deep residual learning for image recognition"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)