human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "the arm scalable vector extension"
  Abstract: This article describes the ARM Scalable Vector Extension (SVE). Several goals guided the design of the architecture. First was the need to extend the vector processing capability associated with the ARM AArch64 execution state to better address the computational requirements in domains such as high-performance computing, data analytics, computer vision, and machine learning. Second was the desire to introduce an extension that can scale across multiple implementations, both now and into the future, allowing CPU designers to choose the vector length most suitable for their power, performance, and area targets. Finally, the architecture should avoid imposing a software development cost as the vector length changes and where possible reduce it by improving the reach of compiler auto-vectorization technologies. SVE achieves these goals. It allows implementations to choose a vector register length between 128 and 2,048 bits. It supports a vector-length agnostic programming model that lets code run and scale automatically across all vector lengths without recompilation. Finally, it introduces several innovative features that begin to overcome some of the traditional barriers to autovectorization.

Connected through hyperedge HE-1 (induced by source paper "base64 encoding and decoding at almost the speed of a memory copy"):
  with members:
    - "faster base64 encoding and decoding using avx2 instructions"

Connected through hyperedge HE-2 (induced by source paper "partial sums on the ultra wide word ram"):
  with members:
    - "succinct partial sums and fenwick trees"
    - "algorithms in the ultra wide word model"
    - "i o efficient data structures for colored range and prefix reporting"
    - "radix sorting with no extra space"
    - "an o 1 solution to the prefix sum problem on a specialized memory architecture"
    - "logarithmic lower bounds in the cell probe model"

Connected through hyperedge HE-3 (induced by source paper "ara a 1 ghz scalable and energy efficient risc v vector processor with multi precision floating point support in 22 nm fd soi"):
  with members:
    - "the cost of application class processing energy and performance analysis of a linux ready 1 7 ghz 64 bit risc v core in 22 nm fdsoi technology"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "end to end learning for self driving cars"
    - "going deeper with convolutions"

Connected through hyperedge HE-4 (induced by source paper "hierarchical block multi color ordering a new parallel ordering method for vectorization and parallelization of the sparse triangular solver in the iccg method"):
  with members:
    - "implementation and evaluation of data compression algorithms for irregular grid iterative methods on the pezy sc processor"
    - "a unified sparse matrix data format for efficient general sparse matrix vector multiplication on modern processors with wide simd units"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)