human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "enabling high dimensional hierarchical uncertainty quantification by anova and tensor train decomposition"
  Abstract: Hierarchical uncertainty quantification can reduce the computational cost of stochastic circuit simulation by employing spectral methods at different levels. This paper presents an efficient framework to simulate hierarchically some challenging stochastic circuits/systems that include high-dimensional subsystems. Due to the high parameter dimensionality, it is challenging to both extract surrogate models at the low level of the design hierarchy and to handle them in the high-level simulation. In this paper, we develop an efficient analysis of variance-based stochastic circuit/microelectromechanical systems simulator to efficiently extract the surrogate models at the low level. In order to avoid the curse of dimensionality, we employ tensor-train decomposition at the high level to construct the basis functions and Gauss quadrature points. As a demonstration, we verify our algorithm on a stochastic oscillator with four MEMS capacitors and 184 random parameters. This challenging example is efficiently simulated by our simulator at the cost of only 10min in MATLAB on a regular personal computer.

Connected through hyperedge HE-1 (induced by source paper "pasta a parallel sparse tensor algorithm benchmark suite"):
  with members:
    - "load balanced sparse mttkrp on gpus"
    - "tensor train decomposition on tensorflow t3f"
    - "a practical randomized cp tensor decomposition"
    - "software for sparse tensor decomposition on emerging computing architectures"
    - "spartan scalable parafac2 for large sparse data"
    - "tensor regression meets gaussian processes"
    - "tensor computation a new framework for high dimensional problems in eda"
    - "a unified optimization approach for sparse tensor operations on gpus"

Connected through hyperedge HE-2 (induced by source paper "prediction of multi dimensional spatial variation data via bayesian tensor completion"):
  with members:
    - "uncertainty quantification of electronic and photonic ics with non gaussian correlated process variations"
    - "tensor computation a new framework for high dimensional problems in eda"
    - "bayesian cp factorization of incomplete tensors with automatic rank determination"
    - "stochastic testing simulator for integrated circuits and mems hierarchical and sparse techniques"
    - "stochastic testing method for transistor level uncertainty quantification based on generalized polynomial chaos"

Connected through hyperedge HE-3 (induced by source paper "uncertainty quantification of electronic and photonic ics with non gaussian correlated process variations"):
  with members:
    - "tensor computation a new framework for high dimensional problems in eda"
    - "stochastic testing simulator for integrated circuits and mems hierarchical and sparse techniques"
    - "calculation of generalized polynomial chaos basis functions and gauss quadrature rules in hierarchical uncertainty quantification"
    - "stochastic testing method for transistor level uncertainty quantification based on generalized polynomial chaos"
    - "sequential compressed sensing"

Connected through hyperedge HE-4 (induced by source paper "tensor computation a new framework for high dimensional problems in eda"):
  with members:
    - "a big data approach to handle process variations uncertainty quantification by tensor recovery"
    - "a big data approach to handle many process variations tensor recovery and applications"
    - "tensorizing neural networks"
    - "bayesian sparse tucker models for dimension reduction and tensor completion"
    - "tensor decompositions for signal processing applications from two way to multiway component analysis"
    - "bayesian cp factorization of incomplete tensors with automatic rank determination"
    - "uncertainty quantification for integrated circuits stochastic spectral methods"
    - "stochastic testing simulator for integrated circuits and mems hierarchical and sparse techniques"

Connected through hyperedge HE-5 (induced by source paper "sobol tensor trains for global sensitivity analysis"):
  with members:
    - "tensor networks for dimensionality reduction and large scale optimization part 1 low rank tensor decompositions"
    - "cltune a generic auto tuner for opencl kernels"

Connected through hyperedge HE-6 (induced by source paper "tensor networks for dimensionality reduction and large scale optimization part 1 low rank tensor decompositions"):
  with members:
    - "randomized single view algorithms for low rank matrix approximation"
    - "group component analysis for multiblock data common and individual feature extraction"
    - "convolutional rectifier networks as generalized tensor decompositions"
    - "tensor networks for latent variable analysis part i algorithms for tensor train decomposition"
    - "linked component analysis from matrices to high order tensors applications to biomedical data"
    - "parallel tensor compression for large scale scientific data"
    - "tensor ring decomposition"
    - "smooth parafac decomposition for tensor completion"

Connected through hyperedge HE-7 (induced by source paper "a big data approach to handle process variations uncertainty quantification by tensor recovery"):
  with members:
    - "probabilistic power flow computation via low rank and sparse tensor recovery"
    - "stochastic testing simulator for integrated circuits and mems hierarchical and sparse techniques"
    - "efficient uncertainty quantification for the periodic steady state of forced and autonomous circuits"
    - "stochastic testing method for transistor level uncertainty quantification based on generalized polynomial chaos"

Connected through hyperedge HE-8 (induced by source paper "a big data approach to handle many process variations tensor recovery and applications"):
  with members:
    - "stochastic testing simulator for integrated circuits and mems hierarchical and sparse techniques"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CE(Computational Engineering, Finance, and Science)