human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "reducing performance impact of dram refresh by parallelizing refreshes with accesses"
  Abstract: 1. Summary 1.1. The Problem DRAM requires periodic refresh to prevent data loss from charge leakage. There exists two main refresh methods employed in the majority of today’s DRAM systems. The first method is to carry out refresh operations at the rank level, called all-bank refresh (REFab), which is mainly used by commodity DDR DRAM [6]. Because all-bank refresh prevents all banks within an entire DRAM rank from serving memory requests, it significantly degrades performance. The second method is to perform refreshes at the bank level, called per-bank refresh (REFpb), which is currently supported in LPDDR DRAM used in mobile platforms [7]. In contrast to REFab, REFpb enables a bank to be accessed while another bank is being refreshed, alleviating part of the negative performance impact of refresh. Unfortunately, there are two shortcomings of per-bank refresh. First, refreshes to different banks are scheduled in a strict round-robin order as specified by the LPDDR standard [7]. Using this static policy may force a busy bank to be refreshed, delaying the memory requests queued in that bank, while other idle banks are available to be refreshed. Second, refreshing banks cannot concurrently serve memory requests. Furthermore, the negative performance impact of DRAM refresh becomes exacerbated as DRAM density increases in the future. Figure 1 shows the average performance degradation of allbank/per-bank refresh compared to ideal baseline without any refreshes. 1 Although REFpb performs slightly better than REFab, the performance loss is still significant, especially as the density grows (16.6% loss at 32Gb). Therefore, the goal of our paper [1] is to provide practical mechanisms to overcome these two shortcomings to mitigate the performance overhead of DRAM refresh.

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)