human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "neuromorphic hardware in the loop training a deep spiking network on the brainscales wafer scale system"
  Abstract: Emulating spiking neural networks on analog neuromorphic hardware offers several advantages over simulating them on conventional computers, particularly in terms of speed and energy consumption. However, this usually comes at the cost of reduced control over the dynamics of the emulated networks. In this paper, we demonstrate how iterative training of a hardware-emulated network can compensate for anomalies induced by the analog substrate. We first convert a deep neural network trained in software to a spiking network on the BrainScaleS wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10000 compared to the biological time domain. This mapping is followed by the in-the-loop training, where in each training step, the network activity is first recorded in hardware and then used to compute the parameter updates in software via backpropagation. An essential finding is that the parameter updates do not have to be precise, but only need to approximately follow the correct gradient, which simplifies the computation of updates. Using this approach, after only several tens of iterations, the spiking network shows an accuracy close to the ideal software-emulated prototype. The presented techniques show that deep spiking networks emulated on analog neuromorphic devices can attain good computational performance despite the inherent variations of the analog substrate.

Connected through hyperedge HE-1 (induced by source paper "fast and deep neuromorphic learning with time to first spike coding"):
  with members:
    - "biologically plausible deep learning but how far can we go with shallow networks"
    - "deep spiking neural network with spike count based learning rule"
    - "biologically inspired alternatives to backpropagation through time for learning in recurrent neural nets"
    - "deep learning in spiking neural networks"
    - "spinnaker 2 a 10 million core processor system for brain simulation and machine learning"
    - "temporal coding in spiking neural networks with alpha synaptic function"
    - "surrogate gradient learning in spiking neural networks"
    - "s4nn temporal backpropagation for spiking neural networks with one spike per neuron"

Connected through hyperedge HE-2 (induced by source paper "efficient reward based structural plasticity on a spinnaker 2 prototype"):
  with members:
    - "a 0 086 mm 2 12 7 pj sop 64k synapse 256 neuron online learning digital spiking neuromorphic processor in 28 nm cmos"
    - "an fpga based massively parallel neuromorphic cortex simulator"
    - "large scale neuromorphic spiking array processors a quest to mimic the brain"
    - "a scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors dynaps"
    - "learning both weights and connections for efficient neural networks"
    - "a biological realtime neuromorphic system in 28 nm cmos using low leakage switched capacitor circuits"

Connected through hyperedge HE-3 (induced by source paper "scaling of a large scale simulation of synchronous slow wave and asynchronous awake like activity of a cortical model with long range interconnections"):
  with members:
    - "real time cortical simulations energy and interconnect scaling on distributed systems"
    - "distributed simulation of polychronous and plastic spiking neural networks strong and weak scaling of a representative mini application benchmark executed on a small scale commodity cluster"

Connected through hyperedge HE-4 (induced by source paper "dynamic power management for neuromorphic many core systems"):
  with members:
    - "a 0 086 mm 2 12 7 pj sop 64k synapse 256 neuron online learning digital spiking neuromorphic processor in 28 nm cmos"

Connected through hyperedge HE-5 (induced by source paper "gaussian and exponential lateral connectivity on distributed spiking neural network simulation"):
  with members:
    - "power energy and speed of embedded and server multi cores applied to distributed simulation of spiking neural networks arm in nvidia tegra vs intel xeon quad cores"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.NE(Neural and Evolutionary Computing)