human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "scaling binarized neural networks on reconfigurable logic"
  Abstract: Binarized neural networks (BNNs) are gaining interest in the deep learning community due to their significantly lower computational and memory cost. They are particularly well suited to reconfigurable logic devices, which contain an abundance of fine-grained compute resources and can result in smaller, lower power implementations, or conversely in higher classification rates. Towards this end, the Finn framework was recently proposed for building fast and flexible field programmable gate array (FPGA) accelerators for BNNs. Finn utilized a novel set of optimizations that enable efficient mapping of BNNs to hardware and implemented fully connected, non-padded convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements. However, FINN was not evaluated on larger topologies due to the size of the chosen FPGA, and exhibited decreased accuracy due to lack of padding. In this paper, we improve upon Finn to show how padding can be employed on BNNs while still maintaining a 1-bit datapath and high accuracy. Based on this technique, we demonstrate numerous experiments to illustrate flexibility and scalability of the approach. In particular, we show that a large BNN requiring 1.2 billion operations per frame running on an ADM-PCIE-8K5 platform can classify images at 12 kFPS with 671 us latency while drawing less than 41 W board power and classifying CIFAR-10 images at 88.7% accuracy. Our implementation of this network achieves 14.8 trillion operations per second. We believe this is the fastest classification rate reported to date on this benchmark at this level of accuracy.

Connected through hyperedge HE-1 (induced by source paper "qutibench benchmarking neural networks on heterogeneous hardware"):
  with members:
    - "analysis of dawnbench a time to accuracy machine learning performance benchmark"
    - "binareye an always on energy accuracy scalable binary cnn processor with all memory on chip in 28nm cmos"
    - "training and inference with integers in deep neural networks"
    - "tvm end to end optimization stack for deep learning"
    - "finn l library extensions and design trade off analysis for variable precision lstm networks on fpgas"
    - "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing"
    - "tbd benchmarking and analyzing deep neural network training"
    - "in datacenter performance analysis of a tensor processing unit"

Connected through hyperedge HE-2 (induced by source paper "toolflows for mapping convolutional neural networks on fpgas a survey and future directions"):
  with members:
    - "approximate fpga based lstms under computation time constraints"
    - "in datacenter performance analysis of a tensor processing unit"
    - "toward low flying autonomous mav trail navigation using deep neural networks for environmental awareness"
    - "fpgaconvnet a toolflow for mapping diverse convolutional neural networks on embedded fpgas"
    - "show and tell lessons learned from the 2015 mscoco image captioning challenge"
    - "fpga based cnn inference accelerator synthesized from multi threaded c software"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "learning to fly by crashing"

Connected through hyperedge HE-3 (induced by source paper "syq learning symmetric quantization for efficient deep neural networks"):
  with members:
    - "deep learning with low precision by half wave gaussian quantization"
    - "compressing low precision deep neural networks using sparsity induced regularization in ternary networks"
    - "ternary neural networks with fine grained quantization"
    - "finn a framework for fast scalable binarized neural network inference"
    - "projectionnet learning efficient on device deep networks using neural projections"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "ternary weight networks"
    - "accelerating deep convolutional networks using low precision and sparsity"

Connected through hyperedge HE-4 (induced by source paper "finn r an end to end deep learning framework for fast exploration of quantized neural networks"):
  with members:
    - "accuracy to throughput trade offs for reduced precision neural networks on reconfigurable logic"
    - "streaming architecture for large scale quantized neural networks on an fpga based dataflow platform"
    - "in datacenter performance analysis of a tensor processing unit"
    - "wrpn wide reduced precision networks"
    - "generic and universal parallel matrix summation with a flexible compression goal for xilinx fpgas"
    - "streamlined deployment for quantized neural networks"
    - "deep learning with low precision by half wave gaussian quantization"
    - "tactics to directly map cnn graphs on embedded fpgas"

Connected through hyperedge HE-5 (induced by source paper "accuracy to throughput trade offs for reduced precision neural networks on reconfigurable logic"):
  with members:
    - "deep learning with low precision by half wave gaussian quantization"
    - "finn a framework for fast scalable binarized neural network inference"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "resiliency of deep neural networks under quantization"
    - "quantized convolutional neural networks for mobile devices"
    - "compressing neural networks with the hashing trick"

Connected through hyperedge HE-6 (induced by source paper "design flow of accelerating hybrid extremely low bit width neural network in embedded fpga"):
  with members:
    - "face recognition with hybrid efficient convolution algorithms on fpgas"
    - "extremely low bit neural network squeeze the last bit out with admm"
    - "finn a framework for fast scalable binarized neural network inference"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "hardware oriented approximation of convolutional neural networks"
    - "ternary weight networks"
    - "eie efficient inference engine on compressed deep neural network"

Connected through hyperedge HE-7 (induced by source paper "fixed point optimization of deep neural networks with adaptive step size retraining"):
  with members:
    - "fpga based low power speech recognition with recurrent neural networks"
    - "eie efficient inference engine on compressed deep neural network"
    - "fpga based implementation of deep neural networks using on chip memory only"
    - "resiliency of deep neural networks under quantization"
    - "binaryconnect training deep neural networks with binary weights during propagations"
    - "deep compression compressing deep neural networks with pruning trained quantization and huffman coding"
    - "fixed point quantization of deep convolutional networks"
    - "fixed point performance analysis of recurrent neural networks"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CV(Computer Vision and Pattern Recognition)