human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "generic and universal parallel matrix summation with a flexible compression goal for xilinx fpgas"
  Abstract: Bit matrix compression is a highly relevant operation in computer arithmetic. Essentially being a multi-operand addition, it is the key operation behind fast multiplication and many higher-level operations such as multiply-accumulate, the computation of the dot product or the implementation of FIR filters. Compressor implementations have been constantly evolving for greater efficiency both in general and in the context of concrete applications or specific implementation technologies. This paper is building on this history and describes a generic implementation of a bit matrix compressor for Xilinx FPGAs, which does not require a generator tool. It contributes FPGA-oriented metrics for the evaluation of elementary parallel bit counters, a systematic analysis and partial decomposition of previously proposed counters and a fully implemented construction heuristic with a flexible compression target matching the device capabilities. The generic implementation is agnostic of the aspect ratio of the input matrix and can be used for multiplication the same way as it can be for single-column population count operations.

Connected through hyperedge HE-1 (induced by source paper "luxor an fpga logic cell architecture for efficient compressor tree implementations"):
  with members:
    - "finn a framework for fast scalable binarized neural network inference"
    - "xnor net imagenet classification using binary convolutional neural networks"

Connected through hyperedge HE-2 (induced by source paper "optimizing bit serial matrix multiplication for reconfigurable computing"):
  with members:
    - "haq hardware aware automated quantization with mixed precision"
    - "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing"
    - "streamlined deployment for quantized neural networks"
    - "finn a framework for fast scalable binarized neural network inference"
    - "espresso efficient forward propagation for bcnns"
    - "quantized neural networks training neural networks with low precision weights and activations"

Connected through hyperedge HE-3 (induced by source paper "finn r an end to end deep learning framework for fast exploration of quantized neural networks"):
  with members:
    - "accuracy to throughput trade offs for reduced precision neural networks on reconfigurable logic"
    - "streaming architecture for large scale quantized neural networks on an fpga based dataflow platform"
    - "in datacenter performance analysis of a tensor processing unit"
    - "wrpn wide reduced precision networks"
    - "streamlined deployment for quantized neural networks"
    - "deep learning with low precision by half wave gaussian quantization"
    - "tactics to directly map cnn graphs on embedded fpgas"
    - "incremental network quantization towards lossless cnns with low precision weights"

Connected through hyperedge HE-4 (induced by source paper "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing"):
  with members:
    - "streamlined deployment for quantized neural networks"
    - "finn a framework for fast scalable binarized neural network inference"
    - "espresso efficient forward propagation for bcnns"
    - "quantized neural networks training neural networks with low precision weights and activations"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)