human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "a fault tolerance improved majority voter for tmr system architectures"
  Abstract: For digital system designs, triple modular redundancy (TMR), which is a 3-tuple version of N-modular redundancy is widely preferred for many mission-control and safety-critical applications. The TMR scheme involves two-times duplication of the simplex system hardware, with a majority voter ensuring correctness provided at least two out of three copies of the system remain operational. Thus the majority voter plays a pivotal role in ensuring the correct operation of the system. The fundamental assumption implicit in the TMR scheme is that the majority voter does not become faulty, which may not hold well for implementations based on latest technology nodes with dimensions of the order of just tens of nanometers. To overcome the drawbacks of the classical majority voter some new voter designs were put forward in the literature with the aim of enhancing the fault tolerance. However, these voter designs generally ensure the correct system operation in the presence of either a faulty function module or the faulty voter, considered only in isolation. Since multiple faults may no longer be excluded in the nanoelectronics regime, simultaneous fault occurrences on both the function module and the voter should be considered, and the fault tolerance of the voters have to be analyzed under such a scenario. In this context, this article proposes a new fault-tolerant majority voter which is found to be more robust to faults than the existing voters in the presence of faults occurring internally and/or externally to the voter. Moreover, the proposed voter features less power dissipation, delay, and area metrics based on the simulation results obtained by using a 32/28nm CMOS process.

Connected through hyperedge HE-1 (induced by source paper "dependability modeling and optimization of triple modular redundancy partitioning for sram based fpgas"):
  with members:
    - "formal analysis of seu mitigation for early dependability and performability analysis of fpga based space applications"

Connected through hyperedge HE-2 (induced by source paper "performance comparison of some synchronous adders"):
  with members:
    - "power delay and area comparisons of majority voters relevant to tmr architectures"
    - "design of synchronous section carry based carry lookahead adders with improved figure of merit"

Connected through hyperedge HE-3 (induced by source paper "mathematical estimation of logical masking capability of majority minority gates used in nanoelectronic circuits"):
  with members:
    - "redundant logic insertion and fault tolerance improvement in combinational circuits"
    - "power delay and area comparisons of majority voters relevant to tmr architectures"
    - "fpga based implementation of distributed minority and majority voting based redundancy for mission and safety critical applications"

Connected through hyperedge HE-4 (induced by source paper "redundant logic insertion and fault tolerance improvement in combinational circuits"):
  with members:
    - "fpga based implementation of distributed minority and majority voting based redundancy for mission and safety critical applications"
    - "system reliability fault tolerance and design metrics tradeoffs in the distributed minority and majority voting based redundancy scheme"

Connected through hyperedge HE-5 (induced by source paper "system reliability fault tolerance and design metrics tradeoffs in the distributed minority and majority voting based redundancy scheme"):
  with members:
    - "power delay and area comparisons of majority voters relevant to tmr architectures"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)