human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "an iot endpoint system on chip for secure and energy efficient near sensor analytics"
  Abstract: Near-sensor data analytics is a promising direction for internet-of-things endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data are stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose  Fulmine , a system-on-chip (SoC) based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The  Fulmine  SoC, fabricated in 65-nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep convolutional neural network (CNN) consuming 3.16pJ per equivalent reduced instruction set computer operation, local CNN-based face detection with secured remote recognition in 5.74pJ/op, and seizure detection with encrypted data collection from electroencephalogram within 12.7pJ/op.

Connected through hyperedge HE-1 (induced by source paper "pulp nn accelerating quantized neural networks on parallel ultra low power risc v processors"):
  with members:
    - "a 64 mw dnn based visual navigation engine for autonomous nano drones"
    - "memory driven mixed low precision quantization for enabling deep network inference on microcontrollers"
    - "xnor neural engine a hardware accelerator ip for 21 6 fj op binary neural network inference"
    - "haq hardware aware automated quantization with mixed precision"
    - "neura ghe exploiting cpu fpga synergies for efficient and flexible cnn inference acceleration on zynq socs"
    - "pact parameterized clipping activation for quantized neural networks"
    - "cmsis nn efficient neural network kernels for arm cortex m cpus"
    - "minimum energy quantized neural networks"

Connected through hyperedge HE-2 (induced by source paper "regularizing activation distribution for training binarized deep networks"):
  with members:
    - "adascale towards real time video object detection using adaptive scaling"
    - "understanding the impact of label granularity on cnn based image classification"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "amc automl for model compression and acceleration on mobile devices"
    - "model compression via distillation and quantization"
    - "bi real net enhancing the performance of 1 bit cnns with improved representational capability and advanced training algorithm"
    - "syq learning symmetric quantization for efficient deep neural networks"
    - "intelligence beyond the edge inference on intermittent embedded systems"

Connected through hyperedge HE-3 (induced by source paper "optimally scheduling cnn convolutions for efficient memory access"):
  with members:
    - "xnor neural engine a hardware accelerator ip for 21 6 fj op binary neural network inference"
    - "neurostream scalable and energy efficient deep learning with smart memory cubes"
    - "extended bit plane compression for convolutional neural network accelerators"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "the power of sparsity in convolutional neural networks"
    - "a survey of model compression and acceleration for deep neural networks"
    - "a systematic approach to blocking convolutional neural networks"
    - "ristretto hardware oriented approximation of convolutional neural networks"

Connected through hyperedge HE-4 (induced by source paper "a 64 mw dnn based visual navigation engine for autonomous nano drones"):
  with members:
    - "cmsis nn efficient neural network kernels for arm cortex m cpus"
    - "learning to fly by crashing"
    - "aggressive quadrotor flight through narrow gaps with onboard sensing and computing using active vision"
    - "efficient optical flow and stereo vision for velocity estimation and obstacle avoidance on an autonomous pocket drone"
    - "cad2rl real single image flight without a single real image"
    - "local histogram matching for efficient optical flow computation applied to velocity estimation on pocket drones"
    - "quantized neural networks training neural networks with low precision weights and activations"
    - "deep residual learning for image recognition"

Connected through hyperedge HE-5 (induced by source paper "hyperdrive a multi chip systolically scalable binary weight cnn inference engine"):
  with members:
    - "mixed precision training of convolutional neural networks using integer operations"
    - "xnorbin a 95 top s w hardware accelerator for binary convolutional neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "yolov3 an incremental improvement"
    - "extended bit plane compression for convolutional neural network accelerators"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"
    - "in datacenter performance analysis of a tensor processing unit"
    - "cas cnn a deep convolutional neural network for image compression artifact suppression"

Connected through hyperedge HE-6 (induced by source paper "xnor neural engine a hardware accelerator ip for 21 6 fj op binary neural network inference"):
  with members:
    - "xnorbin a 95 top s w hardware accelerator for binary convolutional neural networks"
    - "cmsis nn efficient neural network kernels for arm cortex m cpus"
    - "minimum energy quantized neural networks"
    - "towards accurate binary convolutional neural network"
    - "incremental network quantization towards lossless cnns with low precision weights"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"
    - "nullhop a flexible convolutional neural network accelerator based on sparse representations of feature maps"
    - "design automation for binarized neural networks a quantum leap opportunity"

Connected through hyperedge HE-7 (induced by source paper "neura ghe exploiting cpu fpga synergies for efficient and flexible cnn inference acceleration on zynq socs"):
  with members:
    - "neurostream scalable and energy efficient deep learning with smart memory cubes"
    - "squeezejet high level synthesis accelerator design for deep convolutional neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"
    - "origami a 803 gop s w convolutional network accelerator"
    - "finn a framework for fast scalable binarized neural network inference"
    - "dialog based language learning"
    - "binaryconnect training deep neural networks with binary weights during propagations"

Connected through hyperedge HE-8 (induced by source paper "the internet of things fog and cloud continuum integration and challenges"):
  with members:
    - "fog computing a taxonomy survey and future directions"
    - "network slicing based 5g and future mobile networks mobility resource management and challenges"
    - "mathbb echo an adaptive orchestration platform for hybrid dataflows across cloud and edge"
    - "energy efficient resource allocation for mobile edge computation offloading"
    - "from network sharing to multi tenancy the 5g network slice broker"
    - "an internet of things framework for smart energy in buildings designs prototype and experiments"
    - "internet of things iot a vision architectural elements and future directions"
    - "optimal power cost management using stored energy in data centers"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)