human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "programming heterogeneous systems from an image processing dsl"
  Abstract: Specialized image processing accelerators are necessary to deliver the performance and energy efficiency required by important applications in computer vision, computational photography, and augmented reality. But creating, "programming,"and integrating this hardware into a hardware/software system is difficult. We address this problem by extending the image processing language, Halide, so users can specify which portions of their applications should become hardware accelerators, and then we provide a compiler that uses this code to automatically create the accelerator along with the "glue" code needed for the user's application to access this hardware. Starting with Halide not only provides a very high-level functional description of the hardware, but also allows our compiler to generate the complete software program including the sequential part of the workload, which accesses the hardware for acceleration. Our system also provides high-level semantics to explore different mappings of applications to a heterogeneous system, with the added flexibility of being able to map at various throughput rates. #R##N#We demonstrate our approach by mapping applications to a Xilinx Zynq system. Using its FPGA with two low-power ARM cores, our design achieves up to 6x higher performance and 8x lower energy compared to the quad-core ARM CPU on an NVIDIA Tegra K1, and 3.5x higher performance with 12x lower energy compared to the K1's 192-core GPU.

Connected through hyperedge HE-1 (induced by source paper "anyhls high level synthesis with partial evaluation"):
  with members:
    - "module per object a human driven methodology for c based high level synthesis design"
    - "transformations of high level synthesis codes for high performance computing"
    - "automated accelerator generation and optimization with composable parallel and pipeline architecture"
    - "tiramisu a polyhedral compiler for expressing fast and portable code"
    - "c templates as partial evaluation"

Connected through hyperedge HE-2 (induced by source paper "a unified optimization approach for cnn model inference on integrated gpus"):
  with members:
    - "neurostream scalable and energy efficient deep learning with smart memory cubes"
    - "inference of quantized neural networks on heterogeneous all programmable devices"
    - "yolov3 an incremental improvement"
    - "learning to optimize tensor programs"
    - "optimizing cnn model inference on cpus"
    - "mnasnet platform aware neural architecture search for mobile"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"
    - "embedded binarized neural networks"

Connected through hyperedge HE-3 (induced by source paper "instruction level abstraction ila a uniform specification for system on chip soc verification"):
  with members:
    - "tricheck memory model verification at the trisection of software hardware and isa"
    - "herding cats modelling simulation testing and data mining for weak memory"

Connected through hyperedge HE-4 (induced by source paper "dnn dataflow choice is overrated"):
  with members:
    - "in datacenter performance analysis of a tensor processing unit"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "a systematic approach to blocking convolutional neural networks"
    - "recurrent highway networks"
    - "eie efficient inference engine on compressed deep neural network"
    - "deep residual learning for image recognition"
    - "going deeper with convolutions"

Connected through hyperedge HE-5 (induced by source paper "transformations of high level synthesis codes for high performance computing"):
  with members:
    - "graph processing on fpgas taxonomy survey challenges"
    - "parallel programming for fpgas"
    - "demystifying parallel and distributed deep learning an in depth concurrency analysis"
    - "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"
    - "finn a framework for fast scalable binarized neural network inference"
    - "deep learning on fpgas past present and future"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "hitting the memory wall implications of the obvious"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.SE(Software Engineering)