human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "reducing dram latency by exploiting design induced latency variation in modern dram chips"
  Abstract: Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several prior forms of this variation, such as manufacturing-process- or temperature-induced variation. We empirically observe a new form of variation that exists within a DRAM chip, induced by the design and placement of different components in the DRAM chip, where different regions in DRAM, based on their relative distance from the peripheral structures, require different minimum access latencies for reliable operation. In particular, cells closer to the peripheral structures can be accessed much faster than cells that are farther. We call this phenomenon design-induced variation in DRAM. Our goal, in this work, is to understand and exploit design-induced variation to develop low-cost mechanisms to dynamically find and use the lowest latency a DRAM chip can reliably operate at and thus improve overall system performance while ensuring reliable system operation. #R##N#To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Based on our experimental analysis, we develop two mechanisms that reliably reduce DRAM latency.

Connected through hyperedge HE-1 (induced by source paper "rowhammer a retrospective"):
  with members:
    - "processing data where it makes sense enabling in memory computation"
    - "rowhammer and beyond"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "nethammer inducing rowhammer faults through network requests"
    - "pointing in the right direction securing memory accesses in a faulty world"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "theory and practice of finding eviction sets"

Connected through hyperedge HE-2 (induced by source paper "large scale studies of memory storage and network failures in a modern data center"):
  with members:
    - "architectural techniques for improving nand flash memory reliability"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "nethammer inducing rowhammer faults through network requests"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "banshee bandwidth efficient dram caching via software hardware cooperation"
    - "another flip in the wall of rowhammer defenses"
    - "the rowhammer problem and other issues we may face as memory becomes denser"

Connected through hyperedge HE-3 (induced by source paper "the rowhammer problem and other issues we may face as memory becomes denser"):
  with members:
    - "rowhammer reliability analysis and security implications"
    - "rowhammer js a remote software induced fault attack in javascript"
    - "simultaneous multi layer access a high bandwidth and low cost 3d stacked memory interface"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-4 (induced by source paper "understanding and exploiting design induced latency variation in modern dram chips"):
  with members:
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "improving dram performance by parallelizing refreshes with accesses"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)