human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "variable block carry skip logic using reversible gates"
  Abstract: Reversible circuits have applications in digital signal processing, computer graphics, quantum computation and cryptography. In this paper, a generalized k*k reversible gate family is proposed and a 3*3 gate of the family is discussed. Inverter, AND, OR, NAND, NOR, and EXOR gates can be realized by this gate. Implementation of a full-adder circuit using two such 3*3 gates is given. This full-adder circuit contains only two reversible gates and produces no extra garbage outputs. The proposed full-adder circuit is efficient in terms of gate count, garbage outputs and quantum cost. A 4-bit carry skip adder is designed using this full-adder circuit and a variable block carry skip adder is discussed. Necessary equations required to evaluate these adder are presented.

Connected through hyperedge HE-1 (induced by source paper "quantum cost efficient reversible bcd adder for nanotechnology based systems"):
  with members:
    - "novel bcd adders and their reversible logic implementation for ieee 754r format"

Connected through hyperedge HE-2 (induced by source paper "fault tolerant variable block carry skip logic vbcsl using parity preserving reversible gates"):
  with members:
    - "reversible logic synthesis of fault tolerant carry skip bcd adder"
    - "synthesis of fault tolerant reversible logic circuits"
    - "fault tolerant reversible logic synthesis carry look ahead and carry skip adders"

Connected through hyperedge HE-3 (induced by source paper "efficient approaches for designing fault tolerant reversible carry look ahead and carry skip adders"):
  with members:
    - "synthesis of fault tolerant reversible logic circuits"

Connected through hyperedge HE-4 (induced by source paper "a novel quantum cost efficient reversible full adder gate in nanotechnology"):
  with members:
    - "bsssn bit string swapping sorting network for reversible logic synthesis"

Connected through hyperedge HE-5 (induced by source paper "fault tolerant reversible logic synthesis carry look ahead and carry skip adders"):
  with members:
    - "reversible logic synthesis of fault tolerant carry skip bcd adder"
    - "synthesis of fault tolerant reversible logic circuits"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)