human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "fpga based implementation of deep neural networks using on chip memory only"
  Abstract: Deep neural networks (DNNs) demand a very large amount of computation and weight storage, and thus efficient implementation using special purpose hardware is highly desired. In this work, we have developed an FPGA based fixed-point DNN system using only on-chip memory not to access external DRAM. The execution time and energy consumption of the developed system is compared with a GPU based implementation. Since the capacity of memory in FPGA is limited, only 3-bit weights are used for this implementation, and training based fixed-point weight optimization is employed. The implementation using Xilinx XC7Z045 is tested for the MNIST handwritten digit recognition benchmark and a phoneme recognition task on TIMIT corpus. The obtained speed is about one quarter of a GPU based implementation and much better than that of a PC based one. The power consumption is less than 5 Watt at the full speed operation resulting in much higher efficiency compared to GPU based systems.

Connected through hyperedge HE-1 (induced by source paper "spring a sparsity aware reduced precision monolithic 3d cnn accelerator architecture for training and inference"):
  with members:
    - "software defined design space exploration for an efficient ai accelerator architecture"
    - "mixed precision training of convolutional neural networks using integer operations"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "image classification at supercomputer scale"
    - "ucnn exploiting computational reuse in deep neural networks via weight repetition"
    - "highly scalable deep learning training system with mixed precision training imagenet in four minutes"
    - "deep learning inference in facebook data centers characterization performance optimizations and hardware implications"
    - "progressive neural architecture search"

Connected through hyperedge HE-2 (induced by source paper "software defined design space exploration for an efficient ai accelerator architecture"):
  with members:
    - "ucnn exploiting computational reuse in deep neural networks via weight repetition"
    - "learning transferable architectures for scalable image recognition"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "rethinking atrous convolution for semantic image segmentation"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "wide deep learning for recommender systems"
    - "eie efficient inference engine on compressed deep neural network"

Connected through hyperedge HE-3 (induced by source paper "2l 3w 2 level 3 way hardware software co verification for the mapping of deep learning architecture dla onto fpga boards"):
  with members:
    - "detecting sybil attacks using proofs of work and location in vanets"
    - "privacy preserving smart parking system using blockchain and private information retrieval"
    - "b ride ride sharing with privacy preservation trust and fair payment atop public blockchain"
    - "privacy preserving and collusion resistant charging coordination schemes for smart grid"
    - "on sharing models instead of data using mimic learning for smart health applications"
    - "mimic learning to generate a shareable network intrusion detection model"
    - "a stealthy hardware trojan exploiting the architectural vulnerability of deep learning architectures input interception attack iia"
    - "a scalable multilabel classification to deploy deep learning architectures for edge devices"

Connected through hyperedge HE-4 (induced by source paper "evolutionary cell aided design for neural network architectures"):
  with members:
    - "regularized evolution for image classifier architecture search"
    - "toolflows for mapping convolutional neural networks on fpgas a survey and future directions"
    - "exploration of low numeric precision deep learning inference using intel fpgas"
    - "large scale evolution of image classifiers"
    - "an analysis of deep neural network models for practical applications"
    - "learning transferable architectures for scalable image recognition"
    - "hierarchical representations for efficient architecture search"
    - "finn a framework for fast scalable binarized neural network inference"

Connected through hyperedge HE-5 (induced by source paper "packing sparse convolutional neural networks for efficient systolic array implementations column combining under joint optimization"):
  with members:
    - "design flow of accelerating hybrid extremely low bit width neural network in embedded fpga"
    - "block sparse recurrent neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "learning efficient convolutional networks through network slimming"
    - "shift a zero flop zero parameter alternative to spatial convolutions"
    - "mean teachers are better role models weight averaged consistency targets improve semi supervised deep learning results"
    - "chain nn an energy efficient 1d chain architecture for accelerating deep convolutional neural networks"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"

Connected through hyperedge HE-6 (induced by source paper "finn r an end to end deep learning framework for fast exploration of quantized neural networks"):
  with members:
    - "accuracy to throughput trade offs for reduced precision neural networks on reconfigurable logic"
    - "streaming architecture for large scale quantized neural networks on an fpga based dataflow platform"
    - "in datacenter performance analysis of a tensor processing unit"
    - "wrpn wide reduced precision networks"
    - "generic and universal parallel matrix summation with a flexible compression goal for xilinx fpgas"
    - "streamlined deployment for quantized neural networks"
    - "deep learning with low precision by half wave gaussian quantization"
    - "tactics to directly map cnn graphs on embedded fpgas"

Connected through hyperedge HE-7 (induced by source paper "finn a framework for fast scalable binarized neural network inference"):
  with members:
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "planet photo geolocation with convolutional neural networks"
    - "bitwise neural networks"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "yodann an ultra low power convolutional neural network accelerator based on binary weights"
    - "convolutional networks for fast energy efficient neuromorphic computing"

Connected through hyperedge HE-8 (induced by source paper "structured sparse ternary weight coding of deep neural networks for efficient hardware implementations"):
  with members:
    - "fixed point optimization of deep neural networks with adaptive step size retraining"
    - "ternary weight networks"
    - "eie efficient inference engine on compressed deep neural network"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "weight normalization a simple reparameterization to accelerate training of deep neural networks"
    - "trained ternary quantization"
    - "resiliency of deep neural networks under quantization"
    - "deep compression compressing deep neural networks with pruning trained quantization and huffman coding"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)