human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
  Abstract: Stencil algorithms on regular lattices appear in many fields of computational science, and much effort has been put into optimized implementations. Such activities are usually not guided by performance models that provide estimates of expected speedup. Understanding the performance properties and bottlenecks by performance modeling enables a clear view on promising optimization opportunities. In this work we refine the recently developed Execution-Cache-Memory (ECM) model and use it to quantify the performance bottlenecks of stencil algorithms on a contemporary Intel processor. This includes applying the model to arrive at single-core performance and scalability predictions for typical "corner case" stencil loop kernels. Guided by the ECM model we accurately quantify the significance of "layer conditions," which are required to estimate the data traffic through the memory hierarchy, and study the impact of typical optimization approaches such as spatial blocking, strength reduction, and temporal blocking for their expected benefits. We also compare the ECM model to the widely known Roofline model.

Connected through hyperedge HE-1 (induced by source paper "desynchronization and wave pattern formation in mpi parallel and hybrid memory bound programs"):
  with members:
    - "bridging the architecture gap abstracting performance relevant properties of modern server processors"
    - "propagation and decay of injected one off delays on clusters a case study"
    - "chebyshev filter diagonalization on modern manycore processors and gpgpus"
    - "performance engineering of the kernel polynomal method on large scale cpu gpu systems"

Connected through hyperedge HE-2 (induced by source paper "stencil scaling for vector valued pdes on hybrid grids with applications to generalized newtonian fluids"):
  with members:
    - "understanding hpc benchmark performance on intel broadwell and cascade lake processors"

Connected through hyperedge HE-3 (induced by source paper "collecting and presenting reproducible intranode stencil performance inspect"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-4 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-5 (induced by source paper "bridging the architecture gap abstracting performance relevant properties of modern server processors"):
  with members:
    - "analytic performance modeling and analysis of detailed neuron simulations"
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "an ecm based energy efficiency optimization approach for bandwidth limited streaming kernels on recent intel xeon processors"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-6 (induced by source paper "automatic throughput and critical path analysis of x86 and arm assembly kernels"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "ithemal accurate portable and fast basic block throughput estimation using deep neural networks"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "kerncraft a tool for analytic performance modeling of loop kernels"

Connected through hyperedge HE-7 (induced by source paper "delay propagation and overlapping mechanisms on clusters a case study of idle periods based on workload communication and delay granularity"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "idle period propagation in message passing applications"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-8 (induced by source paper "propagation and decay of injected one off delays on clusters a case study"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)