human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "fft based deep learning deployment in embedded systems"
  Abstract: Deep learning has delivered its powerfulness in many application domains, especially in image and speech recognition. As the backbone of deep learning, deep neural networks (DNNs) consist of multiple layers of various types with hundreds to thousands of neurons. Embedded platforms are now becoming essential for deep learning deployment due to their portability, versatility, and energy efficiency. The large model size of DNNs, while providing excellent accuracy, also burdens the embedded platforms with intensive computation and storage. Researchers have investigated on reducing DNN model size with negligible accuracy loss. This work proposes a Fast Fourier Transform (FFT)-based DNN training and inference model suitable for embedded platforms with reduced asymptotic complexity of both computation and storage, making our approach distinguished from existing approaches. We develop the training and inference algorithms based on FFT as the computing kernel and deploy the FFT-based inference model on embedded platforms achieving extraordinary processing speed.

Connected through hyperedge HE-1 (induced by source paper "deploying customized data representation and approximate computing in machine learning applications"):
  with members:
    - "a hardware friendly algorithm for scalable training and deployment of dimensionality reduction models on fpga"
    - "deep convolutional neural network inference with floating point weights and fixed point activations"
    - "mixed low precision deep learning inference using dynamic fixed point"
    - "high performance fpga implementation of equivariant adaptive separation via independence algorithm for independent component analysis"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "hardware oriented approximation of convolutional neural networks"
    - "ternary weight networks"

Connected through hyperedge HE-2 (induced by source paper "an area and energy efficient design of domain wall memory based deep convolutional neural networks using stochastic computing"):
  with members:
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "hardware driven nonlinear activation for stochastic computing based deep convolutional neural networks"
    - "yodann an architecture for ultra low power binary weight cnn acceleration"
    - "sc dcnn highly scalable deep convolutional neural network using stochastic computing"
    - "yodann an ultra low power convolutional neural network accelerator based on binary weights"
    - "deep learning in neural networks"

Connected through hyperedge HE-3 (induced by source paper "towards budget driven hardware optimization for deep convolutional neural networks using stochastic computing"):
  with members:
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "hardware driven nonlinear activation for stochastic computing based deep convolutional neural networks"
    - "very deep convolutional networks for large scale image recognition"

Connected through hyperedge HE-4 (induced by source paper "scalable noc based neuromorphic hardware learning and inference"):
  with members:
    - "towards ultra high performance and energy efficiency of deep learning systems an algorithm hardware co optimization framework"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "hardware driven nonlinear activation for stochastic computing based deep convolutional neural networks"

Connected through hyperedge HE-5 (induced by source paper "a hardware friendly algorithm for scalable training and deployment of dimensionality reduction models on fpga"):
  with members:
    - "high performance fpga implementation of equivariant adaptive separation via independence algorithm for independent component analysis"
    - "experiments with random projection"

Connected through hyperedge HE-6 (induced by source paper "dig enabling out of band scalable high resolution monitoring for data center analytics automation and control extended"):
  with members:
    - "deep residual learning for image recognition"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.LG(Machine Learning)