human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "exploring performance and power properties of modern multicore chips via simple machine models"
  Abstract: Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the single- and multi-core performance of streaming kernels. The model refines the well-known roofline model, since it can predict the scaling and the saturation behavior of bandwidth-limited loop kernels on a multicore chip. The saturation point is especially relevant for considerations of energy consumption. From power dissipation measurements of benchmark programs with vastly different requirements to the hardware, we derive a simple, phenomenological power model for the Sandy Bridge processor. Together with the ECM model, we are able to explain many peculiarities in the performance and power behavior of multicore processors, and derive guidelines for energy-efficient execution of parallel programs. Finally, we show that the ECM and power models can be successfully used to describe the scaling and power behavior of a lattice-Boltzmann flow solver code.

Connected through hyperedge HE-1 (induced by source paper "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"):
  with members:
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "the energy frequency convexity rule modeling and experimental validation on mobile devices"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-2 (induced by source paper "an analysis of core and chip level architectural features in four generations of intel server processors"):
  with members:
    - "an ecm based energy efficiency optimization approach for bandwidth limited streaming kernels on recent intel xeon processors"
    - "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "comparing the performance of different x86 simd instruction sets for a medical imaging application on modern multi and manycore chips"
    - "pushing the limits for medical image reconstruction on recent standard multicore processors"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-3 (induced by source paper "an ecm based energy efficiency optimization approach for bandwidth limited streaming kernels on recent intel xeon processors"):
  with members:
    - "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-4 (induced by source paper "automatic loop kernel analysis and performance modeling with kerncraft"):
  with members:
    - "execution cache memory performance model introduction and validation"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "performance patterns and hardware metrics on modern multicore processors best practices for performance engineering"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-5 (induced by source paper "parameter sensitivity analysis of the energy frequency convexity rule for nanometer scale application processors"):
  with members:
    - "modeling the temperature bias of power consumption for nanometer scale cpus in application processors"
    - "the energy frequency convexity rule modeling and experimental validation on mobile devices"
    - "beebs open benchmarks for energy measurements on embedded platforms"
    - "some observations on optimal frequency selection in dvfs based energy consumption minimization"

Connected through hyperedge HE-6 (induced by source paper "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"):
  with members:
    - "execution cache memory performance model introduction and validation"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-7 (induced by source paper "quantifying performance bottlenecks of stencil computations using the execution cache memory model"):
  with members:
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-8 (induced by source paper "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"):
  with members:
    - "comparison of different propagation steps for lattice boltzmann methods"
    - "pushing the limits for medical image reconstruction on recent standard multicore processors"
    - "leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters"
    - "introducing a performance model for bandwidth limited loop kernels"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)