human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "banshee bandwidth efficient dram caching via software hardware cooperation"
  Abstract: Putting the DRAM on the same package with a processor enables several times higher memory bandwidth than conventional off-package DRAM. Yet, the latency of in-package DRAM is not appreciably lower than that of off-package DRAM. A promising use of in-package DRAM is as a large cache. Unfortunately, most previous DRAM cache designs mainly optimize for hit latency and do not consider off-chip bandwidth efficiency as a first-class design constraint. Hence, as we show in this paper, these designs are suboptimal for use with in-package DRAM. #R##N#We propose a new DRAM cache design, Banshee, that optimizes for both in- and off-package DRAM bandwidth efficiency without degrading access latency. The key ideas are to eliminate the in-package DRAM bandwidth overheads due to costly tag accesses through virtual memory mechanism and to incorporate a bandwidth-aware frequency-based replacement policy that is biased to reduce unnecessary traffic to off-package DRAM. Our extensive evaluation shows that Banshee provides significant performance improvement and traffic reduction over state-of-the-art latency-optimized DRAM cache designs.

Connected through hyperedge HE-1 (induced by source paper "large scale studies of memory storage and network failures in a modern data center"):
  with members:
    - "architectural techniques for improving nand flash memory reliability"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "nethammer inducing rowhammer faults through network requests"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "another flip in the wall of rowhammer defenses"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"

Connected through hyperedge HE-2 (induced by source paper "an analytical model for performance and lifetime estimation of hybrid dram nvm main memories"):
  with members:
    - "an operating system level data migration scheme in hybrid dram nvm memory architecture"
    - "eci cache a high endurance and cost efficient i o caching scheme for virtualized platforms"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "a unified approach to the performance analysis of caching systems"
    - "a versatile and accurate approximation for lru cache performance"

Connected through hyperedge HE-3 (induced by source paper "to update or not to update bandwidth efficient intelligent replacement policies for dram caches"):
  with members:
    - "basic performance measurements of the intel optane dc persistent memory module"
    - "the gap benchmark suite"

Connected through hyperedge HE-4 (induced by source paper "tictoc enabling bandwidth efficient dram caching for both hits and misses in hybrid memory systems"):
  with members:
    - "basic performance measurements of the intel optane dc persistent memory module"
    - "the gap benchmark suite"

Connected through hyperedge HE-5 (induced by source paper "a memory controller with row buffer locality awareness for hybrid memory systems"):
  with members:
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-6 (induced by source paper "die stacked dram memory cache or memcache"):
  with members:
    - "the gap benchmark suite"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)