human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "buddy ram improving the performance and efficiency of bulk bitwise operations using dram"
  Abstract: Bitwise operations are an important component of modern day programming. Many widely-used data structures (e.g., bitmap indices in databases) rely on fast bitwise operations on large bit vectors to achieve high performance. Unfortunately, in existing systems, regardless of the underlying architecture (e.g., CPU, GPU, FPGA), the throughput of such bulk bitwise operations is limited by the available memory bandwidth. #R##N#We propose Buddy, a new mechanism that exploits the analog operation of DRAM to perform bulk bitwise operations completely inside the DRAM chip. Buddy consists of two components. First, simultaneous activation of three DRAM rows that are connected to the same set of sense amplifiers enables us to perform bitwise AND and OR operations. Second, the inverters present in each sense amplifier enables us to perform bitwise NOT operations, with modest changes to the DRAM array. These two components make Buddy functionally complete. Our implementation of Buddy largely exploits the existing DRAM structure and interface, and incurs low overhead (1% of DRAM chip area). #R##N#Our evaluations based on SPICE simulations show that, across seven commonly-used bitwise operations, Buddy provides between 10.9X---25.6X improvement in raw throughput and 25.1X---59.5X reduction in energy consumption. We evaluate three real-world data-intensive applications that exploit bitwise operations: 1) bitmap indices, 2) BitWeaving, and 3) bitvector-based implementation of sets. Our evaluations show that Buddy significantly outperforms the state-of-the-art.

Connected through hyperedge HE-1 (induced by source paper "mixed precision deep learning based on computational memory"):
  with members:
    - "long short term memory networks in memristor crossbar arrays"
    - "neuromorphic computing with multi memristive synapses"
    - "mixed precision in memory computing"
    - "training lstm networks with resistive cross point devices"
    - "bridging the accuracy gap for 2 bit quantized neural networks qnn"
    - "training and inference with integers in deep neural networks"
    - "an analysis of neural language modeling at multiple scales"
    - "an improved evaluation framework for generative adversarial networks"

Connected through hyperedge HE-2 (induced by source paper "eva cim a system level performance and energy evaluation framework for computing in memory architectures"):
  with members:
    - "x sram enabling in memory boolean computations in cmos static random access memories"
    - "computing in memory with spin transfer torque magnetic ram"

Connected through hyperedge HE-3 (induced by source paper "processing data where it makes sense enabling in memory computation"):
  with members:
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "architectural techniques for improving nand flash memory reliability"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "techniques for shared resource management in systems with throughput processors"
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "using ecc dram to adaptively increase memory capacity"

Connected through hyperedge HE-4 (induced by source paper "a workload and programming ease driven perspective of processing in memory"):
  with members:
    - "processing data where it makes sense enabling in memory computation"
    - "in dram bulk bitwise execution engine"
    - "rowhammer a retrospective"
    - "accelerating bulk bit wise x n or operation in processing in dram platform"
    - "shouji a fast and efficient pre alignment filter for sequence alignment"
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "memristive devices for computation in memory"
    - "what your dram power models are not telling you lessons from a detailed experimental study"

Connected through hyperedge HE-5 (induced by source paper "enabling practical processing in and near memory for data intensive computing"):
  with members:
    - "processing data where it makes sense enabling in memory computation"
    - "rowhammer a retrospective"
    - "shouji a fast and efficient pre alignment filter for sequence alignment"
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "using ecc dram to adaptively increase memory capacity"
    - "understanding and improving the latency of dram based memory systems"

Connected through hyperedge HE-6 (induced by source paper "enabling the adoption of processing in memory challenges mechanisms future research directions"):
  with members:
    - "using ecc dram to adaptively increase memory capacity"
    - "lazypim efficient support for cache coherence in processing in memory architectures"
    - "understanding and improving the latency of dram based memory systems"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "rowhammer reliability analysis and security implications"
    - "the processing using memory paradigm in dram bulk copy initialization bitwise and and or"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-7 (induced by source paper "in memory computing on a photonic platform"):
  with members:
    - "mixed precision in memory computing"
    - "superconducting optoelectronic circuits for neuromorphic computing"
    - "temporal correlation detection using computational phase change memory"
    - "mixed precision memcomputing"
    - "universal memcomputing machines"
    - "the parallel approach"

Connected through hyperedge HE-8 (induced by source paper "mixed precision training of deep neural networks using computational memory"):
  with members:
    - "mixed precision in memory computing"
    - "analog cmos based resistive processing unit for deep neural network training"
    - "deep neural networks are robust to weight binarization and other non linear distortions"
    - "acceleration of deep neural network training with resistive cross point devices design considerations"
    - "binaryconnect training deep neural networks with binary weights during propagations"
    - "rounding methods for neural networks with low resolution synaptic weights"
    - "deep learning with limited numerical precision"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)