human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "area latency optimized early output asynchronous full adders and relative timed ripple carry adders"
  Abstract: This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.

Connected through hyperedge HE-1 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders"):
  with members:
    - "performance comparison of some synchronous adders"
    - "asynchronous ripple carry adder based on area optimized early output dual bit full adder"
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "a critique on asynchronous logic implementation based on factorized dims"
    - "asynchronous early output section carry based carry lookahead adder with alias carry logic"
    - "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding"
    - "comments on dual rail asynchronous logic multi level implementation"
    - "an asynchronous early output full adder and a relative timed ripple carry adder"

Connected through hyperedge HE-2 (induced by source paper "indicating asynchronous array multipliers"):
  with members:
    - "indicating asynchronous multipliers"
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "a critique on asynchronous logic implementation based on factorized dims"
    - "an asynchronous early output full adder and a relative timed ripple carry adder"

Connected through hyperedge HE-3 (induced by source paper "speed and energy optimised quasi delay insensitive block carry lookahead adder"):
  with members:
    - "asynchronous early output section carry based carry lookahead adder with alias carry logic"
    - "comments on dual rail asynchronous logic multi level implementation"

Connected through hyperedge HE-4 (induced by source paper "indicating asynchronous multipliers"):
  with members:
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "a critique on asynchronous logic implementation based on factorized dims"

Connected through hyperedge HE-5 (induced by source paper "a critique on asynchronous logic implementation based on factorized dims"):
  with members:
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "asynchronous early output section carry based carry lookahead adder with alias carry logic"
    - "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding"
    - "global versus local weak indication self timed function blocks a comparative analysis"
    - "comments on dual rail asynchronous logic multi level implementation"
    - "early output hybrid input encoded asynchronous full adder and relative timed ripple carry adder"
    - "an asynchronous early output full adder and a relative timed ripple carry adder"

Connected through hyperedge HE-6 (induced by source paper "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"):
  with members:
    - "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding"
    - "comments on dual rail asynchronous logic multi level implementation"
    - "early output hybrid input encoded asynchronous full adder and relative timed ripple carry adder"
    - "an asynchronous early output full adder and a relative timed ripple carry adder"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)