human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "polarbear a 28 nm fd soi asic for decoding of polar codes"
  Abstract: Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explicit construction. Their recent inclusion in a 5G communication standard will only spur more research. However, only a couple of ASICs featuring decoders for polar codes were fabricated, and none of them implements a list-based decoding algorithm. In this paper, we present ASIC measurement results for a fabricated 28-nm CMOS chip that implements two different decoders: the first decoder is tailored toward error-correction performance and flexibility. It supports any code rate as well as three different decoding algorithms: successive cancellation (SC), SC flip, and SC list (SCL). The flexible decoder can also decode both non-systematic and systematic polar codes. The second decoder targets speed and energy efficiency. We present measurement results for the first silicon-proven SCL decoder, where its coded throughput is shown to be of 306.8 Mbps with a latency of 3.34 us and an energy per bit of 418.3 pJ/b at a clock frequency of 721 MHz for a supply of 1.3 V. The energy per bit drops down to 178.1 pJ/b with a more modest clock frequency of 308 MHz, lower throughput of 130.9 Mbps and a reduced supply voltage of 0.9 V. For the other two operating modes, the energy per bit is shown to be of approximately 95 pJ/b. The less flexible high-throughput unrolled decoder can achieve a coded throughput of 9.2 Gbps and a latency of 628 ns for a measured energy per bit of 1.15 pJ/b at 451 MHz.

Connected through hyperedge HE-1 (induced by source paper "ternary quantized polar code decoders analysis and design"):
  with members:
    - "quantized polar code decoders analysis and design"
    - "hardware decoders for polar codes an overview"
    - "llr based successive cancellation list decoding of polar codes"
    - "list decoding of polar codes"
    - "polar codes robustness of the successive cancellation decoder with respect to quantization"
    - "hardware architectures for successive cancellation decoding of polar codes"
    - "performance and construction of polar codes on symmetric binary input memoryless channels"

Connected through hyperedge HE-2 (induced by source paper "improved bit flipping algorithm for successive cancellation decoding of polar codes"):
  with members:
    - "partitioned successive cancellation flip decoding of polar codes"
    - "improved successive cancellation flip decoding of polar codes based on error distribution"
    - "dynamic scflip decoding of polar codes"
    - "an improved scflip decoder for polar codes"
    - "partitioned list decoding of polar codes analysis and improvement of finite length performance"
    - "on error correction performance and implementation of polar code list decoders for 5g"
    - "fast and flexible successive cancellation list decoders for polar codes"
    - "progressive bit flipping decoding of polar codes over layered critical sets"

Connected through hyperedge HE-3 (induced by source paper "a 5 16gbps decoder asic for polar code in 16nm finfet"):
  with members:
    - "parity check polar coding for 5g and beyond"
    - "fast and flexible successive cancellation list decoders for polar codes"
    - "a high throughput list decoder architecture for polar codes"
    - "llr based successive cancellation list decoding of polar codes"
    - "a decision aided parallel sc list decoder for polar codes"
    - "an efficient list decoder architecture for polar codes"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)