human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "yodann an ultra low power convolutional neural network accelerator based on binary weights"
  Abstract: Convolutional Neural Networks (CNNs) have revolutionized the world of image classification over the last few years, pushing the computer vision close beyond human accuracy. The required computational effort of CNNs today requires power-hungry parallel processors and GP-GPUs. Recent efforts in designing CNN Application-Specific Integrated Circuits (ASICs) and accelerators for System-On-Chip (SoC) integration have achieved very promising results. Unfortunately, even these highly optimized engines are still above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. On the algorithmic side, highly competitive classification accuracy can be achieved by properly training CNNs with binary weights. This novel algorithm approach brings major optimization opportunities in the arithmetic core by removing the need for the expensive multiplications as well as in the weight storage and I/O costs. In this work, we present a HW accelerator optimized for BinaryConnect CNNs that achieves 1510 GOp/s on a core area of only 1.33 MGE and with a power dissipation of 153 mW in UMC 65 nm technology at 1.2 V. Our accelerator outperforms state-of-the-art performance in terms of ASIC energy efficiency as well as area efficiency with 61.2 TOp/s/W and 1135 GOp/s/MGE, respectively.

Connected through hyperedge HE-1 (induced by source paper "improving efficiency in neural network accelerator using operands hamming distance optimization"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices"
    - "deep learning inference in facebook data centers characterization performance optimizations and hardware implications"
    - "mnasnet platform aware neural architecture search for mobile"
    - "in datacenter performance analysis of a tensor processing unit"
    - "hello edge keyword spotting on microcontrollers"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"

Connected through hyperedge HE-2 (induced by source paper "ebpc extended bit plane compression for deep neural network inference and training accelerators"):
  with members:
    - "and the bit goes down revisiting the quantization of neural networks"
    - "additive noise annealing and approximation properties of quantized neural networks"
    - "a 64 mw dnn based visual navigation engine for autonomous nano drones"
    - "rpr random partition relaxation for training binary and ternary weight neural networks"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "yolov3 an incremental improvement"
    - "shufflenet v2 practical guidelines for efficient cnn architecture design"
    - "multiposenet fast multi person pose estimation using pose residual network"

Connected through hyperedge HE-3 (induced by source paper "spiking neural networks for inference and learning a memristor based design perspective"):
  with members:
    - "on resistive memories one step row readout technique and sensing circuitry"
    - "biologically inspired alternatives to backpropagation through time for learning in recurrent neural nets"
    - "surrogate gradient learning in spiking neural networks"
    - "contrastive hebbian learning with random feedback weights"
    - "mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse"
    - "synaptic plasticity dynamics for deep continuous local learning"
    - "slayer spike layer error reassignment in time"
    - "deep supervised learning using local errors"

Connected through hyperedge HE-4 (induced by source paper "mixed signal charge domain acceleration of deep neural networks through interleaved bit partitioned arithmetic"):
  with members:
    - "development of a sensory neural network for medical diagnosing"
    - "yolov3 an incremental improvement"
    - "lq nets learned quantization for highly accurate and compact deep neural networks"
    - "ucnn exploiting computational reuse in deep neural networks via weight repetition"
    - "low latency neural speech translation"
    - "recogym a reinforcement learning environment for the problem of product recommendation in online advertising"
    - "safedrive enhancing lane appearance for autonomous and assisted driving under limited visibility"
    - "caterpillar coarse grain reconfigurable architecture for accelerating the training of deep neural networks"

Connected through hyperedge HE-5 (induced by source paper "benchmarking physical performance of neural inference circuits"):
  with members:
    - "enabling spike based backpropagation in state of the art deep neural network architectures"
    - "large scale neuromorphic spiking array processors a quest to mimic the brain"
    - "multiscale co design analysis of energy latency area and accuracy of a reram analog neural training accelerator"
    - "benchmarking inverse rashba edelstein magnetoelectric devices for neuromorphic computing"
    - "benchmarking keyword spotting efficiency on neuromorphic hardware"
    - "an analysis of deep neural network models for practical applications"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "a survey of neuromorphic computing and neural networks in hardware"

Connected through hyperedge HE-6 (induced by source paper "tentaclenet a pseudo ensemble template for accurate binary convolutional neural networks"):
  with members:
    - "pulp nn accelerating quantized neural networks on parallel ultra low power risc v processors"
    - "coopnet cooperative convolutional neural network for low power mcus"
    - "binary ensemble neural network more bits per network or more networks per bit"
    - "xnorbin a 95 top s w hardware accelerator for binary convolutional neural networks"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "finn a framework for fast scalable binarized neural network inference"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "eie efficient inference engine on compressed deep neural network"

Connected through hyperedge HE-7 (induced by source paper "distributed deep convolutional neural networks for the internet of things"):
  with members:
    - "distributed deep neural networks over the cloud the edge and end devices"
    - "origami a 803 gop s w convolutional network accelerator"
    - "deep compression compressing deep neural networks with pruning trained quantization and huffman coding"
    - "deep residual learning for image recognition"
    - "exploiting linear structure within convolutional networks for efficient evaluation"
    - "how transferable are features in deep neural networks"

Connected through hyperedge HE-8 (induced by source paper "processing in memory acceleration of convolutional neural networks for energy efficiency and power intermittency resilience"):
  with members:
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "tensorflow large scale machine learning on heterogeneous distributed systems"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)