human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "reducing dram latency at low cost by exploiting heterogeneity"
  Abstract: In modern systems, DRAM-based main memory is significantly slower than the processor. Consequently, processors spend a long time waiting to access data from main memory, making the long main memory access latency one of the most critical bottlenecks to achieving high system performance. Unfortunately, the latency of DRAM has remained almost constant in the past decade. This is mainly because DRAM has been optimized for cost-per-bit, rather than access latency. As a result, DRAM latency is not reducing with technology scaling, and continues to be an important performance bottleneck in modern and future systems. #R##N#This dissertation seeks to achieve low latency DRAM-based memory systems at low cost in three major directions. First, based on the observation that long bitlines in DRAM are one of the dominant sources of DRAM latency, we propose a new DRAM architecture, Tiered-Latency DRAM (TL-DRAM), which divides the long bitline into two shorter segments using an isolation transistor, allowing one segment to be accessed with reduced latency. Second, we propose a fine-grained DRAM latency reduction mechanism, Adaptive-Latency DRAM, which optimizes DRAM latency for the common operating conditions for individual DRAM module. Third, we propose a new technique, Architectural-Variation-Aware DRAM (AVA-DRAM), which reduces DRAM latency at low cost, by profiling and identifying only the inherently slower regions in DRAM to dynamically determine the lowest latency DRAM can operate at without causing failures. #R##N#This dissertation provides a detailed analysis of DRAM latency by using both circuit-level simulation with a detailed DRAM model and FPGA-based profiling of real DRAM modules. Our latency analysis shows that our low latency DRAM mechanisms enable significant latency reductions, leading to large improvement in both system performance and energy efficiency.

Connected through hyperedge HE-1 (induced by source paper "processing data where it makes sense enabling in memory computation"):
  with members:
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "architectural techniques for improving nand flash memory reliability"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "techniques for shared resource management in systems with throughput processors"
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "using ecc dram to adaptively increase memory capacity"

Connected through hyperedge HE-2 (induced by source paper "large scale studies of memory storage and network failures in a modern data center"):
  with members:
    - "architectural techniques for improving nand flash memory reliability"
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "nethammer inducing rowhammer faults through network requests"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "banshee bandwidth efficient dram caching via software hardware cooperation"
    - "another flip in the wall of rowhammer defenses"
    - "the rowhammer problem and other issues we may face as memory becomes denser"

Connected through hyperedge HE-3 (induced by source paper "in dram bulk bitwise execution engine"):
  with members:
    - "shouji a fast and efficient pre alignment filter for sequence alignment"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "neural cache bit serial in cache acceleration of deep neural networks"
    - "understanding reduced voltage operation in modern dram chips characterization analysis and mechanisms"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-4 (induced by source paper "understanding the interactions of workloads and dram types a comprehensive experimental study"):
  with members:
    - "in dram bulk bitwise execution engine"
    - "rowhammer a retrospective"
    - "memory centric characterization and analysis of spec cpu2017 suite"
    - "d range using commodity dram devices to generate true random numbers with low latency and high throughput"
    - "understanding and improving the latency of dram based memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-5 (induced by source paper "enabling the adoption of processing in memory challenges mechanisms future research directions"):
  with members:
    - "using ecc dram to adaptively increase memory capacity"
    - "lazypim efficient support for cache coherence in processing in memory architectures"
    - "understanding and improving the latency of dram based memory systems"
    - "rowhammer reliability analysis and security implications"
    - "buddy ram improving the performance and efficiency of bulk bitwise operations using dram"
    - "the processing using memory paradigm in dram bulk copy initialization bitwise and and or"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-6 (induced by source paper "d range using commodity dram devices to generate true random numbers with low latency and high throughput"):
  with members:
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "nano intrinsic true random number generation"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"
    - "ensuring high quality randomness in cryptographic key generation"

Connected through hyperedge HE-7 (induced by source paper "flexible latency dram understanding and exploiting latency variation in modern dram chips"):
  with members:
    - "adaptive latency dram reducing dram latency by exploiting timing margins"
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "understanding and improving the latency of dram based memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-8 (induced by source paper "exploiting row level temporal locality in dram to reduce the memory access latency"):
  with members:
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "understanding and improving the latency of dram based memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)