human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters"
  Abstract: Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling.

Connected through hyperedge HE-1 (induced by source paper "multi dimensional intra tile parallelization for memory starved stencil computations"):
  with members:
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "optimizing the performance of streaming numerical kernels on the ibm blue gene p powerpc 450 processor"
    - "efficient multicore aware parallelization strategies for iterative stencil computations"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-2 (induced by source paper "multicore optimized wavefront diamond blocking for optimizing stencil updates"):
  with members:
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "towards energy efficiency and maximum computational intensity for stencil algorithms using wavefront diamond temporal blocking"

Connected through hyperedge HE-3 (induced by source paper "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"):
  with members:
    - "comparison of different propagation steps for lattice boltzmann methods"
    - "pushing the limits for medical image reconstruction on recent standard multicore processors"
    - "exploring performance and power properties of modern multicore chips via simple machine models"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-4 (induced by source paper "optimizing the performance of streaming numerical kernels on the ibm blue gene p powerpc 450 processor"):
  with members:
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-5 (induced by source paper "efficient multicore aware parallelization strategies for iterative stencil computations"):
  with members:
    - "multicore aware parallel temporal blocking of stencil codes for shared and distributed memory"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "introducing a performance model for bandwidth limited loop kernels"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)