human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "tactics to directly map cnn graphs on embedded fpgas"
  Abstract: Deep convolutional neural networks (CNNs) are the state-of-the-art in image classification. Since CNN feed forward propagation involves highly regular parallel computation, it benefits from a significant speed-up when running on fine grain parallel programmable logic devices. As a consequence, several studies have proposed field-programmable gate array (FPGA)-based accelerators for CNNs. However, because of the large computational power required by CNNs, none of the previous studies has proposed a  direct  mapping of the CNN onto the physical resources of an FPGA, allocating each processing actor to its own hardware instance. In this letter, we demonstrate the feasibility of the so called direct hardware mapping (DHM) and discuss several tactics we explore to make DHM usable in practice. As a proof of concept, we introduce the HADDOC2 open source tool, that automatically transforms a CNN description into a synthesizable hardware description with platform-independent DHM.

Connected through hyperedge HE-1 (induced by source paper "the deep learning compiler a comprehensive survey"):
  with members:
    - "shredder learning noise distributions to protect inference privacy"
    - "fusionstitching boosting execution efficiency of memory intensive computations for dl workloads"
    - "stripe tensor compilation via the nested polyhedral model"
    - "tensorflow eager a multi stage python embedded dsl for machine learning"
    - "privacy for rescue a new testimony why privacy is vulnerable in deep models"
    - "dissecting the graphcore ipu architecture via microbenchmarking"
    - "benchmarking tpu gpu and cpu platforms for deep learning"
    - "a comprehensive survey on graph neural networks"

Connected through hyperedge HE-2 (induced by source paper "toolflows for mapping convolutional neural networks on fpgas a survey and future directions"):
  with members:
    - "approximate fpga based lstms under computation time constraints"
    - "in datacenter performance analysis of a tensor processing unit"
    - "toward low flying autonomous mav trail navigation using deep neural networks for environmental awareness"
    - "fpgaconvnet a toolflow for mapping diverse convolutional neural networks on embedded fpgas"
    - "show and tell lessons learned from the 2015 mscoco image captioning challenge"
    - "fpga based cnn inference accelerator synthesized from multi threaded c software"
    - "scnn an accelerator for compressed sparse convolutional neural networks"
    - "learning to fly by crashing"

Connected through hyperedge HE-3 (induced by source paper "finn r an end to end deep learning framework for fast exploration of quantized neural networks"):
  with members:
    - "accuracy to throughput trade offs for reduced precision neural networks on reconfigurable logic"
    - "streaming architecture for large scale quantized neural networks on an fpga based dataflow platform"
    - "in datacenter performance analysis of a tensor processing unit"
    - "wrpn wide reduced precision networks"
    - "generic and universal parallel matrix summation with a flexible compression goal for xilinx fpgas"
    - "streamlined deployment for quantized neural networks"
    - "deep learning with low precision by half wave gaussian quantization"
    - "incremental network quantization towards lossless cnns with low precision weights"

Connected through hyperedge HE-4 (induced by source paper "the challenge of multi operand adders in cnns on fpgas how not to solve it"):
  with members:
    - "yolov3 an incremental improvement"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "quantized convolutional neural networks for mobile devices"
    - "deep learning with limited numerical precision"
    - "fully convolutional networks for semantic segmentation"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)