human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "rethinking split manufacturing an information theoretic approach with secure layout techniques"
  Abstract: Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network flow-based proximity attack, proposed by Wang et al. (DAC'16) [1], has demonstrated that most prior art on split manufacturing is highly vulnerable. Here in this work, we present two practical layout techniques towards secure split manufacturing: (i) gate-level graph coloring and (ii) clustering of same-type gates. Our approach shows promising results against the advanced proximity attack, lowering its success rate by 5.27x, 3.19x, and 1.73x on average compared to the unprotected layouts when splitting at metal layers M1, M2, and M3, respectively. Also, it largely outperforms previous defense efforts; we observe on average 8x higher resilience when compared to representative prior art. At the same time, extensive simulations on ISCAS'85 and MCNC benchmarks reveal that our techniques incur an acceptable layout overhead. Apart from this empirical study, we provide — for the first time — a theoretical framework for quantifying the layout-level resilience against any proximity-induced information leakage. Towards this end, we leverage the notion of mutual information and provide extensive results to validate our model.

Connected through hyperedge HE-1 (induced by source paper "hardware security for and beyond cmos technology an overview on fundamentals applications and challenges"):
  with members:
    - "towards secure composition of integrated circuits and electronic systems on the role of eda"
    - "exploiting spin orbit torque devices as reconfigurable logic for circuit obfuscation"
    - "smart secure magnetoelectric antiferromagnet based tamper proof non volatile memory"
    - "a modern approach to ip protection and trojan prevention split manufacturing for 3d ics and obfuscation of vertical interconnects"
    - "a new paradigm in split manufacturing lock the feol unlock at the beol"
    - "spin orbit torque devices for hardware security from deterministic to probabilistic regime"
    - "protect your chip design intellectual property an overview"
    - "zombieload cross privilege boundary data sampling"

Connected through hyperedge HE-2 (induced by source paper "towards secure composition of integrated circuits and electronic systems on the role of eda"):
  with members:
    - "protect your chip design intellectual property an overview"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "concerted wire lifting enabling secure and cost effective split manufacturing"
    - "processor hardware security vulnerabilities and their detection by unique program execution checking"
    - "tpad hardware trojan prevention and detection for trusted integrated circuits"

Connected through hyperedge HE-3 (induced by source paper "protect your chip design intellectual property an overview"):
  with members:
    - "functional analysis attacks on logic locking"
    - "a new paradigm in split manufacturing lock the feol unlock at the beol"
    - "srclock sat resistant cyclic logic locking for protecting the hardware"
    - "best of both worlds integration of split manufacturing and camouflaging into a security driven cad flow for 3d ics"
    - "concerted wire lifting enabling secure and cost effective split manufacturing"
    - "opening the doors to dynamic camouflaging harnessing the power of polymorphic devices"
    - "sat based reverse engineering of gate level schematics using fault injection and probing"
    - "advancing hardware security using polymorphic and stochastic spin hall effect devices"

Connected through hyperedge HE-4 (induced by source paper "spin orbit torque devices for hardware security from deterministic to probabilistic regime"):
  with members:
    - "exploiting spin orbit torque devices as reconfigurable logic for circuit obfuscation"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "concerted wire lifting enabling secure and cost effective split manufacturing"
    - "obfuscating the interconnects low cost and resilient full chip layout camouflaging"
    - "physical design obfuscation of hardware a comprehensive investigation of device and logic level techniques"

Connected through hyperedge HE-5 (induced by source paper "a new paradigm in split manufacturing lock the feol unlock at the beol"):
  with members:
    - "concerted wire lifting enabling secure and cost effective split manufacturing"

Connected through hyperedge HE-6 (induced by source paper "best of both worlds integration of split manufacturing and camouflaging into a security driven cad flow for 3d ics"):
  with members:
    - "spectre attacks exploiting speculative execution"
    - "concerted wire lifting enabling secure and cost effective split manufacturing"
    - "advancing hardware security using polymorphic and stochastic spin hall effect devices"
    - "a novel interconnect camouflaging technique using transistor threshold voltage"
    - "obfuscating the interconnects low cost and resilient full chip layout camouflaging"
    - "physical design obfuscation of hardware a comprehensive investigation of device and logic level techniques"
    - "threshold dependent camouflaged cells to secure circuits against reverse engineering attacks"

Connected through hyperedge HE-7 (induced by source paper "concerted wire lifting enabling secure and cost effective split manufacturing"):
  with members:
    - "obfuscating the interconnects low cost and resilient full chip layout camouflaging"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)