human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "tricheck memory model verification at the trisection of software hardware and isa"
  Abstract: Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are defined at the various layers of the hardware-software stack, requiring thoroughly verified specifications, compilers, and implementations at the interfaces between layers. Current verification techniques evaluate segments of the system stack in isolation, such as proving compiler mappings from a high-level language (HLL) to an ISA or proving validity of a microarchitectural implementation of an ISA.   This paper makes a case for full-stack MCM verification and provides a toolflow, TriCheck, capable of verifying that the HLL, compiler, ISA, and implementation collectively uphold MCM requirements. The work showcases TriCheck's ability to evaluate a proposed ISA MCM in order to ensure that each layer and each mapping is correct and complete. Specifically, we apply TriCheck to the open source RISC-V ISA [55], seeking to verify accurate, efficient, and legal compilations from C11. We uncover under-specifications and potential inefficiencies in the current RISC-V ISA documentation and identify possible solutions for each. As an example, we find that a RISC-V-compliant microarchitecture allows 144 outcomes forbidden by C11 to be observed out of 1,701 litmus tests examined. Overall, this paper demonstrates the necessity of full-stack verification for detecting MCM-related bugs in the hardware-software stack.

Connected through hyperedge HE-1 (induced by source paper "realitycheck bringing modularity hierarchy and abstraction to automated microarchitectural memory consistency verification"):
  with members:
    - "constructing a weak memory model"
    - "herding cats modelling simulation testing and data mining for weak memory"

Connected through hyperedge HE-2 (induced by source paper "instruction level abstraction ila a uniform specification for system on chip soc verification"):
  with members:
    - "programming heterogeneous systems from an image processing dsl"
    - "herding cats modelling simulation testing and data mining for weak memory"

Connected through hyperedge HE-3 (induced by source paper "constructing a weak memory model"):
  with members:
    - "weak memory models with matching axiomatic and operational definitions"
    - "weak memory models balancing definitional simplicity and implementation flexibility"
    - "overhauling sc atomics in c11 and opencl"
    - "herding cats modelling simulation testing and data mining for weak memory"

Connected through hyperedge HE-4 (induced by source paper "when a patch is not enough hardfails software exploitable hardware bugs"):
  with members:
    - "spectre attacks exploiting speculative execution"
    - "towards vulnerability discovery using staged program analysis"

Connected through hyperedge HE-5 (induced by source paper "meltdownprime and spectreprime automatically synthesized attacks exploiting invalidation based coherence protocols"):
  with members:
    - "herding cats modelling simulation testing and data mining for weak memory"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)