human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "using ecc dram to adaptively increase memory capacity"
  Abstract: Modern DRAM modules are often equipped with hardware error correction capabilities, especially for DRAM deployed in large-scale data centers, as process technology scaling has increased the susceptibility of these devices to errors. To provide fast error detection and correction, error-correcting codes (ECC) are placed on an additional DRAM chip in a DRAM module. This additional chip expands the raw capacity of a DRAM module by 12.5%, but the applications are unable to use any of this extra capacity, as it is used exclusively to provide reliability for all data. In reality, there are a number of applications that do not need such strong reliability for all their data regions (e.g., some user batch jobs executing on a public cloud), and can instead benefit from using additional DRAM capacity to store extra data. Our goal in this work is to provide the additional capacity within an ECC DRAM module to applications when they do not need the high reliability of error correction. #R##N#In this paper, we propose Capacity- and Reliability-Adaptive Memory (CREAM), a hardware mechanism that adapts error correcting DRAM modules to offer multiple levels of error protection, and provides the capacity saved from using weaker protection to applications. For regions of memory that do not require strong error correction, we either provide no ECC protection or provide error detection using multibit parity. We evaluate several layouts for arranging the data within ECC DRAM in these reduced-protection modes, taking into account the various trade-offs exposed from exploiting the extra chip. Our experiments show that the increased capacity provided by CREAM improves performance by 23.0% for a memory caching workload, and by 37.3% for a commercial web search workload executing production query traces. In addition, CREAM can increase bank-level parallelism within DRAM, offering further performance improvements.

Connected through hyperedge HE-1 (induced by source paper "processing data where it makes sense enabling in memory computation"):
  with members:
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "architectural techniques for improving nand flash memory reliability"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "techniques for shared resource management in systems with throughput processors"
    - "errors in flash memory based solid state drives analysis mitigation and recovery"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "lazypim efficient support for cache coherence in processing in memory architectures"

Connected through hyperedge HE-2 (induced by source paper "enabling practical processing in and near memory for data intensive computing"):
  with members:
    - "processing data where it makes sense enabling in memory computation"
    - "rowhammer a retrospective"
    - "shouji a fast and efficient pre alignment filter for sequence alignment"
    - "enabling the adoption of processing in memory challenges mechanisms future research directions"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "understanding and improving the latency of dram based memory systems"
    - "buddy ram improving the performance and efficiency of bulk bitwise operations using dram"

Connected through hyperedge HE-3 (induced by source paper "enabling the adoption of processing in memory challenges mechanisms future research directions"):
  with members:
    - "lazypim efficient support for cache coherence in processing in memory architectures"
    - "understanding and improving the latency of dram based memory systems"
    - "reducing dram latency at low cost by exploiting heterogeneity"
    - "rowhammer reliability analysis and security implications"
    - "buddy ram improving the performance and efficiency of bulk bitwise operations using dram"
    - "the processing using memory paradigm in dram bulk copy initialization bitwise and and or"
    - "simple dram and virtual memory abstractions to enable highly efficient memory systems"
    - "improving dram performance by parallelizing refreshes with accesses"

Connected through hyperedge HE-4 (induced by source paper "architectural techniques for improving nand flash memory reliability"):
  with members:
    - "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation"
    - "what your dram power models are not telling you lessons from a detailed experimental study"
    - "another flip in the wall of rowhammer defenses"
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "channel models for multi level cell flash memories based on empirical error analysis"
    - "rowhammer js a remote software induced fault attack in javascript"

Connected through hyperedge HE-5 (induced by source paper "error characterization mitigation and recovery in flash memory based solid state drives"):
  with members:
    - "the rowhammer problem and other issues we may face as memory becomes denser"
    - "understanding and improving the latency of dram based memory systems"
    - "rowhammer js a remote software induced fault attack in javascript"
    - "improving dram performance by parallelizing refreshes with accesses"
    - "enhanced precision through multiple reads for ldpc decoding in flash memories"

Connected through hyperedge HE-6 (induced by source paper "errors in flash memory based solid state drives analysis mitigation and recovery"):
  with members:
    - "another flip in the wall of rowhammer defenses"
    - "error characterization mitigation and recovery in flash memory based solid state drives"
    - "understanding and improving the latency of dram based memory systems"
    - "enhanced precision through multiple reads for ldpc decoding in flash memories"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)