human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "a gpu outperforming fpga accelerator architecture for binary convolutional neural networks"
  Abstract: FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. A key advantage of the FPGA accelerator is that its performance is insensitive to data batch size, while the performance of GPU acceleration varies largely depending on the batch size of the data. Experiment results show that the proposed accelerator architecture for binary CNNs running on a Virtex-7 FPGA is 8.3x faster and 75x more energy-efficient than a Titan X GPU for processing online individual requests in small batch sizes. For processing static data in large batch sizes, the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5x higher energy efficiency.

Connected through hyperedge HE-1 (induced by source paper "progressive stochastic binarization of deep networks"):
  with members:
    - "deep convolutional sum product networks for probabilistic image representations"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "a quantization friendly separable convolution for mobilenets"
    - "bi real net enhancing the performance of 1 bit cnns with improved representational capability and advanced training algorithm"
    - "probabilistic binary neural networks"
    - "tractable querying and learning in hybrid domains via sum product networks"
    - "learning to train a binary neural network"
    - "bnn improved binary network training"

Connected through hyperedge HE-2 (induced by source paper "batch size influence on performance of graphic and tensor processing units during training and inference phases"):
  with members:
    - "a disciplined approach to neural network hyper parameters part 1 learning rate batch size momentum and weight decay"
    - "recent advances in efficient computation of deep convolutional neural networks"
    - "revisiting small batch training for deep neural networks"
    - "in datacenter performance analysis of a tensor processing unit"
    - "comparative performance analysis of neural networks architectures on h2o platform for various activation functions"
    - "comparative analysis of open source frameworks for machine learning with use case in single threaded and multi threaded modes"
    - "fashion mnist a novel image dataset for benchmarking machine learning algorithms"
    - "performance analysis of open source machine learning frameworks for various parameters in single threaded and multi threaded modes"

Connected through hyperedge HE-3 (induced by source paper "accelerating deterministic and stochastic binarized neural networks on fpgas using opencl"):
  with members:
    - "on the origin of deep learning"
    - "binarized convolutional neural networks with separable filters for efficient hardware acceleration"
    - "binaryconnect training deep neural networks with binary weights during propagations"
    - "very deep convolutional networks for large scale image recognition"

Connected through hyperedge HE-4 (induced by source paper "a survey of fpga based neural network accelerator"):
  with members:
    - "design flow of accelerating hybrid extremely low bit width neural network in embedded fpga"
    - "mnasnet platform aware neural architecture search for mobile"
    - "skipnet learning dynamic routing in convolutional networks"
    - "shufflenet an extremely efficient convolutional neural network for mobile devices"
    - "mobilenets efficient convolutional neural networks for mobile vision applications"
    - "squeezenet alexnet level accuracy with 50x fewer parameters and 0 5mb model size"
    - "c ir cnn accelerating and compressing deep neural networks using block circulant weight matrices"
    - "finn a framework for fast scalable binarized neural network inference"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)