human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "an asynchronous early output full adder and a relative timed ripple carry adder"
  Abstract: This article presents the design of a new asynchronous early output full adder which when cascaded leads to a relative-timed ripple carry adder (RCA). The relative-timed RCA requires imposing a very small relative-timing assumption to overcome the problem of gate orphans associated with internal carry propagation. The relative-timing assumption is however independent of the RCA size. The primary benefits of the relative-timed RCA are processing of valid data incurs data-dependent forward latency, while the processing of spacer involves a very fast constant time reverse latency of just 1 full adder delay which represents the ultimate in the design of an asynchronous RCA with the fastest reset. The secondary benefits of the relative-timed RCA are it achieves good optimization of power and area metrics simultaneously. A 32-bit relative-timed RCA constructed using the proposed early output full adder achieves respective reductions in forward latency by 67%, 10% and 3.5% compared to the optimized strong-indication, weak-indication, and early output 32-bit asynchronous RCAs existing in the literature. Based on a similar comparison, the proposed 32-bit relative-timed RCA achieves corresponding reductions in cycle time by 83%, 12.7% and 6.4%. In terms of area, the proposed 32-bit relative-timed RCA occupies 27% less Silicon than its optimized strong-indication counterpart and 17% less Silicon than its optimized weak-indication counterpart, and features increased area occupancy by a meager 1% compared to the optimized early output 32-bit asynchronous RCA. The average power dissipation of all the asynchronous 32-bit RCAs are found to be comparable since they all satisfy the monotonic cover constraint. The simulation results obtained correspond to a 32/28nm CMOS process.

Connected through hyperedge HE-1 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders"):
  with members:
    - "performance comparison of some synchronous adders"
    - "asynchronous ripple carry adder based on area optimized early output dual bit full adder"
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "a critique on asynchronous logic implementation based on factorized dims"
    - "asynchronous early output section carry based carry lookahead adder with alias carry logic"
    - "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding"
    - "comments on dual rail asynchronous logic multi level implementation"
    - "area latency optimized early output asynchronous full adders and relative timed ripple carry adders"

Connected through hyperedge HE-2 (induced by source paper "indicating asynchronous array multipliers"):
  with members:
    - "indicating asynchronous multipliers"
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "a critique on asynchronous logic implementation based on factorized dims"
    - "area latency optimized early output asynchronous full adders and relative timed ripple carry adders"

Connected through hyperedge HE-3 (induced by source paper "a critique on asynchronous logic implementation based on factorized dims"):
  with members:
    - "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"
    - "asynchronous early output section carry based carry lookahead adder with alias carry logic"
    - "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding"
    - "global versus local weak indication self timed function blocks a comparative analysis"
    - "comments on dual rail asynchronous logic multi level implementation"
    - "area latency optimized early output asynchronous full adders and relative timed ripple carry adders"
    - "early output hybrid input encoded asynchronous full adder and relative timed ripple carry adder"

Connected through hyperedge HE-4 (induced by source paper "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding"):
  with members:
    - "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding"
    - "comments on dual rail asynchronous logic multi level implementation"
    - "area latency optimized early output asynchronous full adders and relative timed ripple carry adders"
    - "early output hybrid input encoded asynchronous full adder and relative timed ripple carry adder"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)