human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "reversible logic synthesis of fault tolerant carry skip bcd adder"
  Abstract: USER   11.9999      Normal   0         false   false   false                             MicrosoftInternetExplorer4             #R##N#st1\:*{behavior:url(#ieooui) }#R##N#       #R##N# /* Style Definitions */#R##N# table.MsoNormalTable#R##N##TAB#{mso-style-name:"Table Normal";#R##N##TAB#mso-tstyle-rowband-size:0;#R##N##TAB#mso-tstyle-colband-size:0;#R##N##TAB#mso-style-noshow:yes;#R##N##TAB#mso-style-parent:"";#R##N##TAB#mso-padding-alt:0cm 5.4pt 0cm 5.4pt;#R##N##TAB#mso-para-margin:0cm;#R##N##TAB#mso-para-margin-bottom:.0001pt;#R##N##TAB#mso-pagination:widow-orphan;#R##N##TAB#font-size:10.0pt;#R##N##TAB#font-family:"Times New Roman";#R##N##TAB#mso-ansi-language:#0400;#R##N##TAB#mso-fareast-language:#0400;#R##N##TAB#mso-bidi-language:#0400;}#R##N#     Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.    Keywords:  Reversible Logic, Parity Preserving Reversible Gate, IG Gate, FTFA and Carry Skip Logic.   doi: 10.3329/jbas.v32i2.2431    Journal of Bangladesh Academy of Sciences  Vol.32(2) 2008 234-250

Connected through hyperedge HE-1 (induced by source paper "fault tolerant variable block carry skip logic vbcsl using parity preserving reversible gates"):
  with members:
    - "variable block carry skip logic using reversible gates"
    - "synthesis of fault tolerant reversible logic circuits"
    - "fault tolerant reversible logic synthesis carry look ahead and carry skip adders"

Connected through hyperedge HE-2 (induced by source paper "fault tolerant reversible logic synthesis carry look ahead and carry skip adders"):
  with members:
    - "variable block carry skip logic using reversible gates"
    - "synthesis of fault tolerant reversible logic circuits"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)