human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "vlsi implementation of deep neural network using integral stochastic computing"
  Abstract: The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing (SC) has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral SC. The proposed architecture has been implemented on a Virtex7 field-programmable gate array, resulting in 45% and 62% average reductions in area and latency compared with the best reported architecture in the literature. We also synthesize the circuits in a 65-nm CMOS technology, and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared with the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a  quasi-synchronous  implementation that yields 33% reduction in energy consumption with respect to the binary radix implementation without any compromise on performance.

Connected through hyperedge HE-1 (induced by source paper "progressive stochastic binarization of deep networks"):
  with members:
    - "deep convolutional sum product networks for probabilistic image representations"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "a quantization friendly separable convolution for mobilenets"
    - "bi real net enhancing the performance of 1 bit cnns with improved representational capability and advanced training algorithm"
    - "probabilistic binary neural networks"
    - "tractable querying and learning in hybrid domains via sum product networks"
    - "learning to train a binary neural network"
    - "bnn improved binary network training"

Connected through hyperedge HE-2 (induced by source paper "energy efficient stochastic computing with superparamagnetic tunnel junctions"):
  with members:
    - "low barrier magnet design for efficient hardware binary stochastic neurons"
    - "p bits for probabilistic spin logic"
    - "voltage driven building block for hardware belief networks"
    - "implementing bayesian networks with embedded stochastic mram"
    - "efficient processing of deep neural networks a tutorial and survey"
    - "reservoir computing using stochastic p bits"
    - "hardware driven nonlinear activation for stochastic computing based deep convolutional neural networks"
    - "dorefa net training low bitwidth convolutional neural networks with low bitwidth gradients"

Connected through hyperedge HE-3 (induced by source paper "p bits for probabilistic spin logic"):
  with members:
    - "weighted p bits for fpga implementation of probabilistic circuits"
    - "low energy deep belief networks using intrinsic sigmoidal spintronic based probabilistic neurons"
    - "voltage driven building block for hardware belief networks"
    - "perspective memcomputing leveraging memory and physics to compute efficiently"
    - "stochastic spin orbit torque devices as elements for bayesian inference"
    - "stochastic spiking neural networks enabled by magnetic tunnel junctions from nontelegraphic to telegraphic switching regimes"
    - "hardware emulation of stochastic p bits for invertible logic"
    - "polynomial time solution of prime factorization and np complete problems with digital memcomputing machines"

Connected through hyperedge HE-4 (induced by source paper "stochastic computing for hardware implementation of binarized neural networks"):
  with members:
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "in memory and error immune differential rram implementation of binarized deep neural networks"
    - "an analysis of deep neural network models for practical applications"
    - "towards accurate binary convolutional neural network"
    - "fashion mnist a novel image dataset for benchmarking machine learning algorithms"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "xnor net imagenet classification using binary convolutional neural networks"
    - "quantized neural networks training neural networks with low precision weights and activations"

Connected through hyperedge HE-5 (induced by source paper "a stochastic computing based deep learning framework using adiabatic quantum flux parametron superconducting technology"):
  with members:
    - "on the universal approximation property and equivalence of stochastic computing based neural networks and binary neural networks"
    - "vibnn hardware acceleration of bayesian neural networks"
    - "energy efficient hybrid stochastic binary neural networks for near sensor computing"
    - "finn a framework for fast scalable binarized neural network inference"
    - "ese efficient speech recognition engine with sparse lstm on fpga"
    - "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1"
    - "eie efficient inference engine on compressed deep neural network"

Connected through hyperedge HE-6 (induced by source paper "composable probabilistic inference networks using mram based stochastic neurons"):
  with members:
    - "low energy deep belief networks using intrinsic sigmoidal spintronic based probabilistic neurons"
    - "stochastic spiking neural networks enabled by magnetic tunnel junctions from nontelegraphic to telegraphic switching regimes"
    - "probabilistic deep spiking neural systems enabled by magnetic tunnel junction"
    - "hybrid spintronic cmos spiking neural network with on chip learning devices circuits and systems"
    - "training a probabilistic graphical model with resistive switching electronic synapses"
    - "binaryconnect training deep neural networks with binary weights during propagations"
    - "magnetic tunnel junction mimics stochastic cortical spiking neurons"

Connected through hyperedge HE-7 (induced by source paper "low barrier magnet design for efficient hardware binary stochastic neurons"):
  with members:
    - "composable probabilistic inference networks using mram based stochastic neurons"
    - "voltage driven building block for hardware belief networks"
    - "stochastic spiking neural networks enabled by magnetic tunnel junctions from nontelegraphic to telegraphic switching regimes"
    - "hardware emulation of stochastic p bits for invertible logic"

Connected through hyperedge HE-8 (induced by source paper "snra a spintronic neuromorphic reconfigurable array for in circuit training and evaluation of deep belief networks"):
  with members:
    - "exploiting spin orbit torque devices as reconfigurable logic for circuit obfuscation"
    - "low energy deep belief networks using intrinsic sigmoidal spintronic based probabilistic neurons"
    - "hybrid spintronic cmos spiking neural network with on chip learning devices circuits and systems"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.NE(Neural and Evolutionary Computing)