human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "an analysis of core and chip level architectural features in four generations of intel server processors"
  Abstract: This paper presents a survey of architectural features among four generations of Intel server processors (Sandy Bridge, Ivy Bridge, Haswell, and Broad- well) with a focus on performance with floating point workloads. Starting on the core level and going down the memory hierarchy we cover instruction throughput for floating-point instructions, L1 cache, address generation capabilities, core clock speed and its limitations, L2 and L3 cache bandwidth and latency, the impact of Cluster on Die (CoD) and cache snoop modes, and the Uncore clock speed. Using microbenchmarks we study the influence of these factors on code performance. This insight can then serve as input for analytic performance models. We show that the energy efficiency of the LINPACK and HPCG benchmarks can be improved considerably by tuning the Uncore clock speed without sacrificing performance, and that the Graph500 benchmark performance may profit from a suitable choice of cache snoop mode settings.

Connected through hyperedge HE-1 (induced by source paper "understanding hpc benchmark performance on intel broadwell and cascade lake processors"):
  with members:
    - "a recursive algebraic coloring technique for hardware efficient symmetric sparse matrix vector multiplication"
    - "analysis of intel s haswell microarchitecture using the ecm model and microbenchmarks"

Connected through hyperedge HE-2 (induced by source paper "collecting and presenting reproducible intranode stencil performance inspect"):
  with members:
    - "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-3 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "introducing a performance model for bandwidth limited loop kernels"

Connected through hyperedge HE-4 (induced by source paper "delay propagation and overlapping mechanisms on clusters a case study of idle periods based on workload communication and delay granularity"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "idle period propagation in message passing applications"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-5 (induced by source paper "propagation and decay of injected one off delays on clusters a case study"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"

Connected through hyperedge HE-6 (induced by source paper "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"):
  with members:
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "the energy frequency convexity rule modeling and experimental validation on mobile devices"
    - "chip level and multi node analysis of energy optimized lattice boltzmann cfd simulations"
    - "exploring performance and power properties of modern multicore chips via simple machine models"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)