human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "dissecting the nvidia turing t4 gpu via microbenchmarking"
  Abstract: In 2019, the rapid rate at which GPU manufacturers refresh their designs, coupled with their reluctance to disclose microarchitectural details, is still a hurdle for those software designers who want to extract the highest possible performance. Last year, these very reasons motivated us to dissect the Volta GPU architecture using microbenchmarks. #R##N#The introduction in August 2018 of Turing, NVidia's latest architecture, pressed us to update our study. In this report, we examine Turing and compare it quantitatively against previous NVidia GPU generations. Specifically, we study the T4 GPU: a low-power board aiming at inference applications. We describe its improvements against its inference-oriented predecessor: the P4 GPU based on the Pascal architecture. Both T4 and P4 GPUs achieve significantly higher frequency-per-Watt figures than their full-size counterparts. #R##N#We study the performance of the T4's TensorCores, finding a much higher throughput on low-precision operands than on the P4 GPU. We reveal that Turing introduces new instructions that express matrix math more succinctly. We map Turing's instruction space, finding the same encoding as Volta, and additional instructions. We reveal that the Turing TU104 chip has the same memory hierarchy depth as the Volta GV100; cache levels sizes on the TU104 are frequently twice as large as those found on the Pascal GP104. We benchmark each constituent of the T4 memory hierarchy and find substantial overall performance improvements over its P4 predecessor. We studied how clock throttling affects compute-intensive workloads that hit power or thermal limits. #R##N#Many of our findings are novel, published here for the first time. All of them can guide high-performance software developers get closer to the GPU's peak performance.

Connected through hyperedge HE-1 (induced by source paper "gpu tensor cores for fast arithmetic reductions"):
  with members:
    - "accelerating reduction and scan using tensor core units"
    - "gpu parallel simulation algorithm of brownian particles with excluded volume using delaunay triangulations"
    - "nvidia tensor core programmability performance precision"
    - "exploration of low numeric precision deep learning inference using intel fpgas"
    - "dissecting the nvidia volta gpu architecture via microbenchmarking"
    - "deep learning in neural networks"

Connected through hyperedge HE-2 (induced by source paper "accurate deep neural network inference using computational phase change memory"):
  with members:
    - "improving noise tolerance of mixed signal neural networks"
    - "mixed precision in memory computing"
    - "discovering low precision networks close to full precision networks for efficient embedded inference"
    - "in datacenter performance analysis of a tensor processing unit"
    - "training deep convolutional neural networks with resistive cross point devices"
    - "improved regularization of convolutional neural networks with cutout"
    - "deep neural networks are robust to weight binarization and other non linear distortions"
    - "quantized neural networks training neural networks with low precision weights and activations"

Connected through hyperedge HE-3 (induced by source paper "a versatile software systolic execution model for gpu memory bound kernels"):
  with members:
    - "regdem increasing gpu performance via shared memory register spilling"
    - "stateful dataflow multigraphs a data centric model for performance portability on heterogeneous architectures"
    - "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl"
    - "dissecting the nvidia volta gpu architecture via microbenchmarking"
    - "in datacenter performance analysis of a tensor processing unit"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "cudnn efficient primitives for deep learning"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)