human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "uops info characterizing latency throughput and port usage of instructions on intel microarchitectures"
  Abstract: Modern microarchitectures are some of the world's most complex man-made systems. As a consequence, it is increasingly difficult to predict, explain, let alone optimize the performance of software running on such microarchitectures. As a basis for performance predictions and optimizations, we would need faithful models of their behavior, which are, unfortunately, seldom available.    In this paper, we present the design and implementation of a tool to construct faithful models of the latency, throughput, and port usage of x86 instructions. To this end, we first discuss common notions of instruction throughput and port usage, and introduce a more precise definition of latency that, in contrast to previous definitions, considers dependencies between different pairs of input and output operands. We then develop novel algorithms to infer the latency, throughput, and port usage based on automatically-generated microbenchmarks that are more accurate and precise than existing work.    To facilitate the rapid construction of optimizing compilers and tools for performance prediction, the output of our tool is provided in a machine-readable format. We provide experimental results for processors of all generations of Intel's Core architecture, i.e., from Nehalem to Coffee Lake, and discuss various cases where the output of our tool differs considerably from prior work.

Connected through hyperedge HE-1 (induced by source paper "collecting and presenting reproducible intranode stencil performance inspect"):
  with members:
    - "on the accuracy and usefulness of analytic energy models for contemporary multicore processors"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "an analysis of core and chip level architectural features in four generations of intel server processors"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"
    - "multicore optimized wavefront diamond blocking for optimizing stencil updates"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-2 (induced by source paper "nanobench a low overhead tool for running microbenchmarks on x86 systems"):
  with members:
    - "cachequery learning replacement policies from hardware caches"
    - "reload refresh abusing cache replacement policies to perform stealthy cache attacks"
    - "spectre attacks exploiting speculative execution"
    - "efficient characterization of hidden processor memory hierarchies"
    - "theory and practice of finding eviction sets"
    - "dissecting gpu memory hierarchy through microbenchmarking"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"
    - "likwid a lightweight performance oriented tool suite for x86 multicore environments"

Connected through hyperedge HE-3 (induced by source paper "cachequery learning replacement policies from hardware caches"):
  with members:
    - "reload refresh abusing cache replacement policies to perform stealthy cache attacks"
    - "reverse engineering x86 processor microcode"
    - "nanobench a low overhead tool for running microbenchmarks on x86 systems"
    - "on the incomparability of cache algorithms in terms of timing leakage"
    - "theory and practice of finding eviction sets"
    - "rowhammer js a remote software induced fault attack in javascript"
    - "drama exploiting dram addressing for cross cpu attacks"

Connected through hyperedge HE-4 (induced by source paper "automatic throughput and critical path analysis of x86 and arm assembly kernels"):
  with members:
    - "ithemal accurate portable and fast basic block throughput estimation using deep neural networks"
    - "automated instruction stream throughput prediction for intel and amd microarchitectures"
    - "kerncraft a tool for analytic performance modeling of loop kernels"
    - "quantifying performance bottlenecks of stencil computations using the execution cache memory model"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)