human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "dnnvm end to end compiler leveraging heterogeneous optimizations on fpga based cnn accelerators"
  Abstract: The convolutional neural network (CNN) has become a state-of-the-art method for several artificial intelligence domains in recent years. The increasingly complex CNN models are both computation-bound and I/O-bound. FPGA-based accelerators driven by custom instruction set architecture (ISA) achieve a balance between generality and efficiency, but there is much on them left to be optimized. We propose the full-stack compiler DNNVM, which is an integration of optimizers for graphs, loops and data layouts, and an assembler, a runtime supporter and a validation environment. The DNNVM works in the context of deep learning frameworks and transforms CNN models into the directed acyclic graph: XGraph. Based on XGraph, we transform the optimization challenges for both the data layout and pipeline into graph-level problems. DNNVM enumerates all potentially profitable fusion opportunities by a heuristic subgraph isomorphism algorithm to leverage pipeline and data layout optimizations, and searches for the optimal execution strategies of the whole computing graph. On the Xilinx ZU2 @330 MHz and ZU9 @330 MHz, we achieve equivalently state-of-the-art performance on our benchmarks by naive implementations without optimizations, and the throughput is further improved up to 1.26x by leveraging heterogeneous optimizations in DNNVM. Finally, with ZU9 @330 MHz, we achieve state-of-the-art performance for VGG and ResNet50. We achieve a throughput of 2.82 TOPs/s and an energy efficiency of 123.7 GOPs/s/W for VGG. Additionally, we achieve 1.38 TOPs/s for ResNet50.

Connected through hyperedge HE-1 (induced by source paper "vargnet variable group convolutional neural network for efficient embedded computing"):
  with members:
    - "single path nas designing hardware efficient convnets in less than 4 hours"
    - "panoptic feature pyramid networks"
    - "dla compiler and fpga overlay for neural network inference acceleration"
    - "igcv3 interleaved low rank group convolutions for efficient deep neural networks"
    - "bisenet bilateral segmentation network for real time semantic segmentation"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "tvm end to end optimization stack for deep learning"
    - "arcface additive angular margin loss for deep face recognition"

Connected through hyperedge HE-2 (induced by source paper "feature map transform coding for energy efficient cnn inference"):
  with members:
    - "regularizing activation distribution for training binarized deep networks"
    - "lutnet rethinking inference in fpga soft logic"
    - "low bit quantization of neural networks for efficient inference"
    - "same same but different recovering neural network quantization error through weight factorization"
    - "swalp stochastic weight averaging in low precision training"
    - "hawq hessian aware quantization of neural networks with mixed precision"
    - "faster gaze prediction with dense networks and fisher pruning"
    - "uniq uniform noise injection for the quantization of neural networks"

Connected through hyperedge HE-3 (induced by source paper "vargfacenet an efficient variable group convolutional neural network for lightweight face recognition"):
  with members:
    - "vargnet variable group convolutional neural network for efficient embedded computing"
    - "shrinkteanet million scale lightweight face recognition via shrinking teacher student networks"
    - "retinaface single stage dense face localisation in the wild"
    - "mobilenetv2 inverted residuals and linear bottlenecks"
    - "arcface additive angular margin loss for deep face recognition"
    - "shufflenet v2 practical guidelines for efficient cnn architecture design"
    - "mobilefacenets efficient cnns for accurate real time face verification on mobile devices"
    - "knowledge transfer via distillation of activation boundaries formed by hidden neurons"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)