human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "functional analysis attacks on logic locking"
  Abstract: Logic locking refers to a set of techniques that can protect integrated circuits (ICs) from counterfeiting, piracy and malicious functionality changes by an untrusted foundry. It achieves these goals by introducing new inputs, called key inputs, and additional logic to an IC such that the circuit produces the correct output only when the key inputs are set to specific values. The correct values of the key inputs are kept secret from the untrusted foundry and programmed after manufacturing and before distribution, thus rendering piracy, counterfeiting and malicious design changes infeasible. The security of logic locking relies on the assumption that the untrusted foundry cannot infer the correct values of the key inputs by analysis of the circuit. In this paper, we introduce a new attack on state-of-the-art logic locking schemes which invalidates the above assumption. We propose  F unctional  A nalysis attacks on  L ogic  L ocking algorithms (abbreviated as FALL attacks). FALL attacks have two stages. Their first stage is dependent on the locking algorithm and involves analyzing structural and functional properties of locked circuits to identify a list of potential locking keys. The second stage is algorithm agnostic and introduces a powerful addition to SAT-based attacks called  key confirmation . Key confirmation can identify the correct key from a list of alternatives and works even on circuits that are resilient to the SAT attack. In comparison to past work, the FALL attack is more practical as it can often succeed (90% of successful attempts in our experiments) by only analyzing the locked netlist,  without requiring oracle access  to an unlocked circuit. Our experimental evaluation shows that FALL attacks are able to defeat 65 out of 80 (81%) circuits locked using Stripped-Functionality Logic Locking (SFLL-HD).

Connected through hyperedge HE-1 (induced by source paper "dfssd deep faults and shallow state duality a provably strong obfuscation solution for circuits with restricted access to scan chain"):
  with members:
    - "sat hard cyclic logic obfuscation for protecting the ip in the manufacturing supply chain"
    - "is robust design for security robust enough attack on locked circuits with restricted scan chain access"
    - "coma communication and obfuscation management architecture"
    - "threats on logic locking a decade later"
    - "benchmarking the capabilities and limitations of sat solvers in defeating obfuscation schemes"
    - "lut lock a novel lut based logic obfuscation for fpga bitstream and asic hardware protection"
    - "encrypt flip flop a novel logic encryption technique for sequential circuits"

Connected through hyperedge HE-2 (induced by source paper "sat hard cyclic logic obfuscation for protecting the ip in the manufacturing supply chain"):
  with members:
    - "coma communication and obfuscation management architecture"
    - "threats on logic locking a decade later"
    - "srclock sat resistant cyclic logic locking for protecting the hardware"
    - "benchmarking the capabilities and limitations of sat solvers in defeating obfuscation schemes"
    - "lut lock a novel lut based logic obfuscation for fpga bitstream and asic hardware protection"

Connected through hyperedge HE-3 (induced by source paper "protect your chip design intellectual property an overview"):
  with members:
    - "a new paradigm in split manufacturing lock the feol unlock at the beol"
    - "srclock sat resistant cyclic logic locking for protecting the hardware"
    - "best of both worlds integration of split manufacturing and camouflaging into a security driven cad flow for 3d ics"
    - "concerted wire lifting enabling secure and cost effective split manufacturing"
    - "opening the doors to dynamic camouflaging harnessing the power of polymorphic devices"
    - "sat based reverse engineering of gate level schematics using fault injection and probing"
    - "advancing hardware security using polymorphic and stochastic spin hall effect devices"
    - "rethinking split manufacturing an information theoretic approach with secure layout techniques"

Connected through hyperedge HE-4 (induced by source paper "defense in depth a recipe for logic locking to prevail"):
  with members:
    - "taal tampering attack on any key based logic locked circuits"
    - "threats on logic locking a decade later"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "logic locking for secure outsourced chip fabrication a new attack and provably secure defense mechanism"
    - "physical design obfuscation of hardware a comprehensive investigation of device and logic level techniques"
    - "threshold based obfuscated keys with quantifiable security against invasive readout"

Connected through hyperedge HE-5 (induced by source paper "coma communication and obfuscation management architecture"):
  with members:
    - "threats on logic locking a decade later"
    - "srclock sat resistant cyclic logic locking for protecting the hardware"
    - "sail machine learning guided structural analysis attack on hardware obfuscation"
    - "benchmarking the capabilities and limitations of sat solvers in defeating obfuscation schemes"
    - "lut lock a novel lut based logic obfuscation for fpga bitstream and asic hardware protection"

Connected through hyperedge HE-6 (induced by source paper "threats on logic locking a decade later"):
  with members:
    - "srclock sat resistant cyclic logic locking for protecting the hardware"
    - "benchmarking the capabilities and limitations of sat solvers in defeating obfuscation schemes"
    - "lut lock a novel lut based logic obfuscation for fpga bitstream and asic hardware protection"

Connected through hyperedge HE-7 (induced by source paper "is robust design for security robust enough attack on locked circuits with restricted scan chain access"):
  with members:
    - "encrypt flip flop a novel logic encryption technique for sequential circuits"

Connected through hyperedge HE-8 (induced by source paper "scansat unlocking static and dynamic scan obfuscation"):
  with members:
    - "encrypt flip flop a novel logic encryption technique for sequential circuits"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)