human: Given a node-centered hypergraph: <hypergraph>, where nodes represent papers and hyperedges represent sets of papers co-cited by a source paper.

Details of the hypergraph:
Center node: "achieving super linear speedup across multi fpga for real time dnn inference"
  Abstract: Real-time Deep Neural Network (DNN) inference with low-latency requirement has become increasingly important for numerous applications in both cloud computing (e.g., Apple's Siri) and edge computing (e.g., Google/Waymo's driverless car). FPGA-based DNN accelerators have demonstrated both superior flexibility and performance; in addition, for real-time inference with low batch size, FPGA is expected to achieve further performance improvement. However, the performance gain from the single-FPGA design is obstructed by the limited on-chip resource. In this paper, we employ multiple FPGAs to cooperatively run DNNs with the objective of achieving super-linear speed-up against single-FPGA design. In implementing such systems, we found two barriers that hinder us from achieving the design goal: (1) the lack of a clear partition scheme for each DNN layer to fully exploit parallelism, and (2) the insufficient bandwidth between the off-chip memory and the accelerator due to the growing size of DNNs. To tackle these issues, we propose a general framework, "Super-LIP", which can support different kinds of DNNs. In this paper, we take Convolutional Neural Network (CNN) as a vehicle to illustrate Super-LIP. We first formulate an accurate system-level model to support the exploration of best partition schemes. Then, we develop a novel design methodology to effectively alleviate the heavy loads on memory bandwidth by moving traffic from memory bus to inter-FPGA links. We implement Super-LIP based on ZCU102 FPGA boards. Results demonstrate that Super-LIP with 2 FPGAs can achieve 3.48x speedup, compared to the state-of-the-art single-FPGA design. What is more, as the number of FPGAs scales up, the system latency can be further reduced while maintaining high energy efficiency.

Connected through hyperedge HE-1 (induced by source paper "co exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks"):
  with members:
    - "nass optimizing secure inference via neural architecture search"
    - "hardware software co exploration of neural architectures"
    - "herald optimizing heterogeneous dnn accelerators for edge devices"
    - "on neural architecture search for resource constrained hardware platforms"
    - "proxylessnas direct neural architecture search on target task and hardware"
    - "darts differentiable architecture search"
    - "mnasnet platform aware neural architecture search for mobile"
    - "scnn an accelerator for compressed sparse convolutional neural networks"

Connected through hyperedge HE-2 (induced by source paper "low overhead online data flow tracking for intermittently powered non volatile fpgas"):
  with members:
    - "accuracy vs efficiency achieving both through fpga implementation aware neural architecture search"

Connected through hyperedge HE-3 (induced by source paper "device circuit architecture co exploration for computing in memory neural accelerators"):
  with members:
    - "video action recognition via neural architecture searching"
    - "hardware software co exploration of neural architectures"
    - "accuracy vs efficiency achieving both through fpga implementation aware neural architecture search"
    - "auto deeplab hierarchical neural architecture search for semantic image segmentation"
    - "on neural architecture search for resource constrained hardware platforms"
    - "architecture search of dynamic cells for semantic video segmentation"
    - "fbnet hardware aware efficient convnet design via differentiable neural architecture search"
    - "yolov3 an incremental improvement"

Connected through hyperedge HE-4 (induced by source paper "when single event upset meets deep neural networks observations explorations and remedies"):
  with members:
    - "accuracy vs efficiency achieving both through fpga implementation aware neural architecture search"
    - "learning phase competition for traffic signal control"
    - "intrinsic image transformation via scale space decomposition"
    - "neural color transfer between images"
    - "on the robustness of convolutional neural networks to internal architecture and weight perturbations"
    - "deep residual learning for image recognition"
    - "very deep convolutional networks for large scale image recognition"
    - "network in network"

Question: Please tell me which class the center node belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)