human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "what your dram power models are not telling you lessons from a detailed experimental study"):
  Abstract: Main memory (DRAM) consumes as much as half of the total system power in a computer today, resulting in a growing need to develop new DRAM architectures and systems that consume less power. Researchers have long relied on DRAM power models that are based off of standardized current measurements provided by vendors, called IDD values. Unfortunately, we find that these models are highly inaccurate, and do not reflect the actual power consumed by real DRAM devices. #R##N#We perform the first comprehensive experimental characterization of the power consumed by modern real-world DRAM modules. Our extensive characterization of 50 DDR3L DRAM modules from three major vendors yields four key new observations about DRAM power consumption: (1) across all IDD values that we measure, the current consumed by real DRAM modules varies significantly from the current specified by the vendors; (2) DRAM power consumption strongly depends on the data value that is read or written; (3) there is significant structural variation, where the same banks and rows across multiple DRAM modules from the same model consume more power than other banks or rows; and (4) over successive process technology generations, DRAM power consumption has not decreased by as much as vendor specifications have indicated. #R##N#Based on our detailed analysis and characterization data, we develop the Variation-Aware model of Memory Power Informed by Real Experiments (VAMPIRE). We show that VAMPIRE has a mean absolute percentage error of only 6.8% compared to actual measured DRAM power. VAMPIRE enables a wide range of studies that were not possible using prior DRAM power models. As an example, we use VAMPIRE to evaluate a new power-aware data encoding mechanism, which can reduce DRAM energy consumption by an average of 12.2%. We plan to open-source both VAMPIRE and our extensive raw data collected during our experimental characterization.

Includes members:
  Member "improving 3d nand flash memory lifetime by tolerating early retention loss and process variation":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "rowhammer a retrospective")
  Member "the rowhammer problem and other issues we may face as memory becomes denser":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "are we susceptible to rowhammer an end to end methodology for cloud providers")
  Member "error characterization mitigation and recovery in flash memory based solid state drives":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "processing data where it makes sense enabling in memory computation")
  Member "understanding and improving the latency of dram based memory systems":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram")
  Member "simple dram and virtual memory abstractions to enable highly efficient memory systems":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "processing data where it makes sense enabling in memory computation")
  Member "simultaneous multi layer access a high bandwidth and low cost 3d stacked memory interface":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "the rowhammer problem and other issues we may face as memory becomes denser")
  Member "improving dram performance by parallelizing refreshes with accesses":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "are we susceptible to rowhammer an end to end methodology for cloud providers")
  Member "bigdatabench a big data benchmark suite from internet services":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "tlb and pagewalk performance in multicore architectures with large die stacked dram cache")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)