human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "haq hardware aware automated quantization with mixed precision"):
  Abstract: Model quantization is a widely used technique to compress and accelerate deep neural network (DNN) inference. Emergent DNN hardware accelerators begin to support mixed precision (1-8 bits) to further improve the computation efficiency, which raises a great challenge to find the optimal bitwidth for each layer: it requires domain experts to explore the vast design space trading off among accuracy, latency, energy, and model size, which is both time-consuming and sub-optimal. Conventional quantization algorithm ignores the different hardware architectures and quantizes all the layers in a uniform way. In this paper, we introduce the Hardware-Aware Automated Quantization (HAQ) framework which leverages the reinforcement learning to automatically determine the quantization policy, and we take the hardware accelerator's feedback in the design loop. Rather than relying on proxy signals such as FLOPs and model size, we employ a hardware simulator to generate direct feedback signals (latency and energy) to the RL agent. Compared with conventional methods, our framework is fully automated and can specialize the quantization policy for different neural network architectures and hardware architectures. Our framework effectively reduced the latency by 1.4-1.95x and the energy consumption by 1.9x with negligible loss of accuracy compared with the fixed bitwidth (8 bits) quantization. Our framework reveals that the optimal policies on different hardware architectures (i.e., edge and cloud architectures) under different resource constraints (i.e., latency, energy and model size) are drastically different. We interpreted the implication of different quantization policies, which offer insights for both neural network architecture design and hardware architecture design.

Includes members:
  Member "netadapt platform aware neural network adaptation for mobile applications":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "quantizing deep convolutional networks for efficient inference a whitepaper":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "post training piecewise linear quantization for deep neural networks")
  Member "mobilenetv2 inverted residuals and linear bottlenecks":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "amc automl for model compression and acceleration on mobile devices":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "proxylessnas direct neural architecture search on target task and hardware":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "gan compression efficient architectures for interactive conditional gans")
  Member "path level network transformation for efficient architecture search":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "autoemb automated embedding dimensionality search in streaming recommendations")
  Member "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "efficient bitwidth search for practical mixed precision neural network")
  Member "pact parameterized clipping activation for quantized neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "discrimination aware network pruning for deep model compression")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CV(Computer Vision and Pattern Recognition)