human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "xcel ram accelerating binary neural networks in high throughput sram compute arrays"):
  Abstract: Deep neural networks are a biologically-inspired class of algorithms that have recently demonstrated state-of-the-art accuracies involving large-scale classification and recognition tasks. Indeed, a major landmark that enables efficient hardware accelerators for deep networks is the recent advances from the machine learning community that have demonstrated aggressively scaled deep binary networks with state-of-the-art accuracies. In this paper, we demonstrate how deep binary networks can be accelerated in modified von-Neumann machines by enabling binary convolutions within the SRAM array. In general, binary convolutions consist of bit-wise XNOR followed by a population-count (popcount). We present a charge sharing XNOR and popcount operation in 10 transistor SRAM cells. We have employed multiple circuit techniques including dual-read-worldines (Dual-RWL) along with a dual-stage ADC that overcomes the inaccuracies of a low precision ADC, to achieve a fairly accurate popcount. In addition, a key highlight of the present work is the fact that we propose sectioning of the SRAM array by adding switches onto the read-bitlines, thereby achieving improved parallelism. This is beneficial for deep networks, where the kernel size grows and requires to be stored in multiple sub-banks. As such, one needs to evaluate the partial popcount from multiple sub-banks and sum them up for achieving the final popcount. For n-sections per sub-array, we can perform n convolutions within one particular sub-bank, thereby improving overall system throughput as well as the energy efficiency. Our results at the array level show that the energy consumption and delay per-operation was 1.914pJ and 45ns, respectively. Moreover, an energy improvement of 2.5x, and a performance improvement of 4x was achieved by using the proposed sectioned-SRAM, compared to a non-sectioned SRAM design.

Includes members:
  Member "8t sram cell as a multi bit dot product engine for beyond von neumann computing":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "x changr changing memristive crossbar mapping for mitigating line resistance induced accuracy degradation in deep neural networks")
  Member "resparc a reconfigurable and energy efficient architecture with memristive crossbars for deep spiking neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "reinforcement co learning of deep and spiking neural networks for energy efficient mapless navigation with neuromorphic hardware")
  Member "computing in memory with spin transfer torque magnetic ram":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "a new mram based process in memory accelerator for efficient neural network training with floating point precision")
  Member "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "lossless compression of deep neural networks")
  Member "xnor net imagenet classification using binary convolutional neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "deep residual learning for image recognition":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "going deeper with convolutions":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "discrimination aware network pruning for deep model compression")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.ET(Emerging Technologies)