human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "transformations of high level synthesis codes for high performance computing"):
  Abstract: Specialized hardware architectures promise a major step in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C/C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target specialized hardware, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes. Fast and efficient codes for reconfigurable platforms are thus still challenging to design. To alleviate this, we present a set of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. Our work provides a toolbox for developers, where we systematically identify classes of transformations, the characteristics of their effect on the HLS code and the resulting hardware (e.g., increases data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip streaming dataflow, allowing for massively parallel architectures. To quantify the effect of our transformations, we use them to optimize a set of throughput-oriented FPGA kernels, demonstrating that our enhancements are sufficient to scale up parallelism within the hardware constraints. With the transformations covered, we hope to establish a common framework for performance engineers, compiler developers, and hardware developers, to tap into the performance potential offered by specialized hardware architectures using HLS.

Includes members:
  Member "graph processing on fpgas taxonomy survey challenges":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "practice of streaming and dynamic graphs concepts models systems and parallelism")
  Member "parallel programming for fpgas":
    also connected through other hyperedges:
      (none)
  Member "demystifying parallel and distributed deep learning an in depth concurrency analysis":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "communication optimization strategies for distributed deep learning a survey")
  Member "combined spatial and temporal blocking for high performance stencil computation on fpgas using opencl":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "an5d automated stencil framework for high degree temporal blocking on gpus")
  Member "finn a framework for fast scalable binarized neural network inference":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "sqwa stochastic quantized weight averaging for improving the generalization capability of low precision deep neural networks")
  Member "programming heterogeneous systems from an image processing dsl":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "anyhls high level synthesis with partial evaluation")
  Member "deep learning on fpgas past present and future":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "poet bin power efficient tiny binary neurons")
  Member "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "lossless compression of deep neural networks")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)