human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "slim simultaneous logic in memory computing exploiting bilayer analog oxram devices"):
  Abstract: Von Neumann architecture based computers isolate/physically separate computation and storage units i.e. data is shuttled between computation unit (processor) and memory unit to realize logic/ arithmetic and storage functions. This to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the memory wall. Logic in-Memory (LIM) approaches aim to address this bottleneck by computing inside the memory units and thereby eliminating the energy-intensive and time-consuming data movement. However, most LIM approaches reported in literature are not truly "simultaneous" as during LIM operation the bitcell can be used only as a Memory cell or only as a Logic cell. The bitcell is not capable of storing both the Memory/Logic outputs simultaneously. Here, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology that allows to implement both Memory and Logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state. Through extensive experiments we demonstrate the SLIM methodology using non-filamentary bilayer analog OxRAM devices with NMOS transistors (2T-1R bitcell). Detailed programming scheme, array level implementation and controller architecture are also proposed. Furthermore, to study the impact of introducing SLIM array in the memory hierarchy, a simple image processing application (edge detection) is also investigated. It has been estimated that by performing all computations inside the SLIM array, the total Energy Delay Product (EDP) reduces by ~ 40x in comparison to a modern-day computer. EDP saving owing to reduction in data transfer between CPU Memory is observed to be ~ 780x.

Includes members:
  Member "mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "spiking neural networks for inference and learning a memristor based design perspective")
  Member "x sram enabling in memory boolean computations in cmos static random access memories":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "eva cim a system level performance and energy evaluation framework for computing in memory architectures")
  Member "minimum energy quantized neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "pulp nn accelerating quantized neural networks on parallel ultra low power risc v processors")
  Member "efficient processing of deep neural networks a tutorial and survey":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "searching for winograd aware quantized networks")
  Member "memory and information processing in neuromorphic systems":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "precise neural network computation with imprecise analog devices")
  Member "hitting the memory wall implications of the obvious":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "flexible communication avoiding matrix multiplication on fpga with high level synthesis")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.ET(Emerging Technologies)