human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "multi dimensional intra tile parallelization for memory starved stencil computations"):
  Abstract: Optimizing the performance of stencil algorithms has been the subject of intense research over the last two decades. Since many stencil schemes have low arithmetic intensity, most optimizations focus on increasing the temporal data access locality, thus reducing the data traffic through the main memory interface with the ultimate goal of decoupling from this bottleneck. There are, however, only few approaches that explicitly leverage the shared cache feature of modern multicore chips. If every thread works on its private, separate cache block, the available cache space can become too small, and sufficient temporal locality may not be achieved. #R##N#We propose a flexible multi-dimensional intra-tile parallelization method for stencil algorithms on multicore CPUs with a shared outer-level cache. This method leads to a significant reduction in the required cache space without adverse effects from hardware prefetching or TLB shortage. Our \emph{Girih} framework includes an auto-tuner to select optimal parameter configurations on the target hardware. We conduct performance experiments on two contemporary Intel processors and compare with the state-of-the-art stencil frameworks PLUTO and Pochoir, using four corner-case stencil schemes and a wide range of problem sizes. \emph{Girih} shows substantial performance advantages and best arithmetic intensity at almost all problem sizes, especially on low-intensity stencils with variable coefficients. We study in detail the performance behavior at varying grid size using phenomenological performance modeling. Our analysis of energy consumption reveals that our method can save energy by reduced DRAM bandwidth usage even at marginal performance gain. It is thus well suited for future architectures that will be strongly challenged by the cost of data movement, be it in terms of performance or energy consumption.

Includes members:
  Member "quantifying performance bottlenecks of stencil computations using the execution cache memory model":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "desynchronization and wave pattern formation in mpi parallel and hybrid memory bound programs")
  Member "multicore optimized wavefront diamond blocking for optimizing stencil updates":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "collecting and presenting reproducible intranode stencil performance inspect")
  Member "optimizing the performance of streaming numerical kernels on the ibm blue gene p powerpc 450 processor":
    also connected through other hyperedges:
      (none)
  Member "efficient multicore aware parallelization strategies for iterative stencil computations":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "tight bounds for low dimensional star stencils in the parallel external memory model")
  Member "leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "multicore optimized wavefront diamond blocking for optimizing stencil updates")
  Member "introducing a performance model for bandwidth limited loop kernels":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)