human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "a critique on asynchronous logic implementation based on factorized dims"):
  Abstract: This paper comments on "Asynchronous Logic Implementation Based on Factorized DIMS" [Jour. of Circuits, Systems, and Computers, vol. 26, no. 5, 1750087, pages 9, May 2017] with respect to two problematic issues: i) the gate orphan problem implicit in the factorized DIMS approach discussed in the referenced article which affects the strong-indication, and ii) how the enumeration of product terms to represent the synthesis cost is skewed in the referenced article because the logic expression contains sum of products and also product of sums. It is observed that the referenced article has not provided a general logic synthesis algorithm excepting only an example illustration involving a 3-input AND gate function. The absence of a general logic synthesis algorithm would make it difficult to reproduce the research described in the referenced article. Moreover, the example illustration in the referenced article describes an unsafe logic decomposition which is not suitable for strong-indication asynchronous circuit synthesis. Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize strong-indication asynchronous circuits is already available in the existing literature, which was neither cited nor taken up for comparison in the referenced article, which is another drawback. Subsequently, it is concluded that the referenced article has not advanced existing knowledge in the field but has caused confusions. Hence, in the interest of avid readers, this paper additionally highlights some important and relevant literature which provide valuable information about robust asynchronous circuit synthesis techniques which employ delay-insensitive codes for data representation and processing and the 4-phase return-to-zero handshake protocol for data communication.

Includes members:
  Member "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders")
  Member "asynchronous early output section carry based carry lookahead adder with alias carry logic":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders")
  Member "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders")
  Member "global versus local weak indication self timed function blocks a comparative analysis":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding")
  Member "comments on dual rail asynchronous logic multi level implementation":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders")
  Member "area latency optimized early output asynchronous full adders and relative timed ripple carry adders":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders")
  Member "early output hybrid input encoded asynchronous full adder and relative timed ripple carry adder":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding")
  Member "an asynchronous early output full adder and a relative timed ripple carry adder":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)