human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "a technique for write endurance aware management of resistive ram last level caches"):
  Abstract: Due to increasing cache sizes and large leakage consumption of SRAM device, conventional SRAM caches contribute significantly to the processor power consumption. Recently researchers have used non-volatile memory devices to design caches, since they provide high density, comparable read latency and low leakage power dissipation. However, their high write latency may increase the execution time and hence, leakage energy consumption. Also, since their write endurance is small, a conventional energy saving technique may further aggravate the problem of write-variations, thus reducing their lifetime. In this paper, we present a cache energy saving technique for non-volatile caches, which also attempts to improve their lifetime by making writes equally distributed to the cache. Our technique uses dynamic cache reconfiguration to adjust the cache size to meet program requirement and turns off the remaining cache to save energy. Microarchitectural simulations performed using an x86-64 simulator, SPEC2006 benchmarks and a resistive-RAM LLC (last level cache) show that over an 8MB baseline cache, our technique saves 17.55% memory subsystem (last level cache + main memory) energy and improves the lifetime by 1.33X. Over the same resistive-RAM baseline, an SRAM of similar area with no cache reconfiguration leads to an energy loss of 186.13%.

Includes members:
  Member "a cache reconfiguration approach for saving leakage and refresh energy in embedded dram caches":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "a technique for efficiently managing sram nvm hybrid cache")
  Member "domain decomposition based high performance parallel computing":
    also connected through other hyperedges:
      (none)

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)