human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "sparce sparsity aware general purpose core extensions to accelerate deep neural networks"):
  Abstract: Deep Neural Networks (DNNs) have emerged as the method of choice for solving a wide range of machine learning tasks. The enormous computational demands posed by DNNs have most commonly been addressed through the design of custom accelerators. However, these accelerators are prohibitive in many design scenarios (e.g., wearable devices and IoT sensors), due to stringent area/cost constraints. Accelerating DNNs on these low-power systems, comprising of mainly the general-purpose processor (GPP) cores, requires new approaches. We improve the performance of DNNs on GPPs by exploiting a key attribute of DNNs, i.e., sparsity. We propose Sparsity aware Core Extensions (SparCE)- a set of micro-architectural and ISA extensions that leverage sparsity and are minimally intrusive and low-overhead. We dynamically detect zero operands and skip a set of future instructions that use it. Our design ensures that the instructions to be skipped are prevented from even being fetched, as squashing instructions comes with a penalty. SparCE consists of 2 key micro-architectural enhancements- a Sparsity Register File (SpRF) that tracks zero registers and a Sparsity aware Skip Address (SASA) table that indicates instructions to be skipped. When an instruction is fetched, SparCE dynamically pre-identifies whether the following instruction(s) can be skipped and appropriately modifies the program counter, thereby skipping the redundant instructions and improving performance. We model SparCE using the gem5 architectural simulator, and evaluate our approach on 6 image-recognition DNNs in the context of both training and inference using the Caffe framework. On a scalar microprocessor, SparCE achieves 19%-31% reduction in application-level. We also evaluate SparCE on a 4-way SIMD ARMv8 processor using the OpenBLAS library, and demonstrate that SparCE achieves 8%-15% reduction in the application-level execution time.

Includes members:
  Member "in datacenter performance analysis of a tensor processing unit":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "train large then compress rethinking model size for efficient training and inference of transformers")
  Member "scnn an accelerator for compressed sparse convolutional neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "sparse weight activation training")
  Member "a persona based neural conversation model":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "non autoregressive neural dialogue generation")
  Member "learning structured sparsity in deep neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "vdnn virtualized deep neural networks for scalable memory efficient neural network design":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "an empirical evaluation of perturbation based defenses")
  Member "eie efficient inference engine on compressed deep neural network":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "cluster pruning an efficient filter pruning method for edge ai vision applications")
  Member "znn a fast and scalable algorithm for training 3d convolutional networks on multi core and many core shared memory machines":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "high throughput cnn inference on embedded arm big little multi core processors")
  Member "trained ternary quantization":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "gan compression efficient architectures for interactive conditional gans")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)