human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "energy efficient time domain vector by matrix multiplier for neurocomputing and beyond"):
  Abstract: We propose an extremely energy-efficient mixed-signal approach for performing vector-by-matrix multiplication in a time domain. In such implementation, multi-bit values of the input and output vector elements are represented with time-encoded digital signals, while multi-bit matrix weights are realized with current sources, e.g. transistors biased in subthreshold regime. With our approach, multipliers can be chained together to implement large-scale circuits completely in a time domain. Multiplier operation does not rely on energy-taxing static currents, which are typical for peripheral and input/output conversion circuits of the conventional mixed-signal implementations. As a case study, we have designed a multilayer perceptron, based on two layers of 10x10 four-quadrant vector-by-matrix multipliers, in 55-nm process with embedded NOR flash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based on memory cell measurements, shows that at high computing speed the drain-induced barrier lowering is a major factor limiting multiplier precision to ~6 bit. Post-layout estimates for a conservative 6-bit digital input/output NxN multiplier designed in 55 nm process, including I/O circuitry for converting between digital and time domain representations, show ~7 fJ/Op for N>200, which can be further lowered well below 1 fJ/Op for more optimal and aggressive design.

Includes members:
  Member "multiscale co design analysis of energy latency area and accuracy of a reram analog neural training accelerator":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")
  Member "in datacenter performance analysis of a tensor processing unit":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "train large then compress rethinking model size for efficient training and inference of transformers")
  Member "temperature insensitive analog vector by matrix multiplier based on 55 nm nor flash memory cells":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "fq conv fully quantized convolution for efficient and accurate inference")
  Member "sub 1 us sub 20 nj pattern classification in a mixed signal circuit based on embedded 180 nm floating gate memory cell arrays":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "towards ultra high performance and energy efficiency of deep learning systems an algorithm hardware co optimization framework")
  Member "quantized neural networks training neural networks with low precision weights and activations":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "switchable precision neural networks")
  Member "precise deep neural network computation on imprecise low power analog hardware":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "noisy machines understanding noisy neural networks and enhancing robustness to analog hardware errors using distillation")
  Member "jpeg image compression using discrete cosine transform a survey":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "an efficient pre processing method to eliminate adversarial effects")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)