human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "portability analysis for axiomatic memory models porthos one tool for all models"):
  Abstract: We present PORTHOS, the first tool that discovers porting bugs in performance-critical code. PORTHOS takes as input a program, the memory model of the source architecture for which the program has been developed, and the memory model of the targeted architecture. If the code is not portable, PORTHOS finds a porting bug in the form of an unexpected execution - an execution that is consistent with the target but inconsistent with the source memory model. #R##N#Technically, PORTHOS implements a bounded model checking method that reduces portability analysis to the satisfiability modulo theories (SMT) problem with integer difference logic. There are two problems in the reduction that are unique to portability and that we present novel and efficient solutions for. First, the formulation of portability contains a quantifier alternation (consistent + inconsistent). We encode inconsistency as an existential query. Second, the memory models may contain recursive definitions. We compute the corresponding least fixed points efficiently in SMT. #R##N#Interestingly, we are able to prove that our execution-based notion of portability is the most liberal one that admits an efficient algorithmic analysis: for state-based portability, a polynomial SAT encoding cannot exist. #R##N#Experimentally, we applied PORTHOS to a number of case studies. It is able to check portability of non-trivial programs between interesting architectures. Notably, we present the first algorithmic analysis of portability from TSO to Power.

Includes members:
  Member "stateless model checking for power":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "dynamic verification with observational equivalence of c c concurrency")
  Member "herding cats modelling simulation testing and data mining for weak memory":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "realitycheck bringing modularity hierarchy and abstraction to automated microarchitectural memory consistency verification")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PL(Programming Languages)