human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "efficient multicore aware parallelization strategies for iterative stencil computations"):
  Abstract: Abstract   Stencil computations consume a major part of runtime in many scientific simulation codes. As prototypes for this class of algorithms we consider the iterative Jacobi and Gauss-Seidel smoothers and aim at highly efficient parallel implementations for cache-based multicore architectures. Temporal cache blocking is a known advanced optimization technique, which can reduce the pressure on the memory bus significantly. We apply and refine this optimization for a recently presented temporal blocking strategy designed to explicitly utilize multicore characteristics. Especially for the case of Gauss-Seidel smoothers we show that simultaneous multi-threading (SMT) can yield substantial performance improvements for our optimized algorithm on some architectures.

Includes members:
  Member "multicore aware parallel temporal blocking of stencil codes for shared and distributed memory":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "likwid a lightweight performance oriented tool suite for x86 multicore environments")
  Member "likwid a lightweight performance oriented tool suite for x86 multicore environments":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "lbmpy a flexible code generation toolkit for highly efficient lattice boltzmann simulations")
  Member "likwid a lightweight performance oriented tool suite for x86 multicore environments":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "lbmpy a flexible code generation toolkit for highly efficient lattice boltzmann simulations")
  Member "leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "multi dimensional intra tile parallelization for memory starved stencil computations")
  Member "introducing a performance model for bandwidth limited loop kernels":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "analytic performance modeling and analysis of detailed neuron simulations")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.PF(Performance)