human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "memjam a false dependency attack against constant time crypto implementations"):
  Abstract: Cache attacks exploit memory access patterns of cryptographic implementations. Constant-time implementation techniques have become an indispensable tool in fighting cache timing attacks. These techniques engineer the memory accesses of cryptographic operations to follow a uniform key independent pattern. However, the constant-time behavior is dependent on the underlying architecture, which can be highly complex and often incorporates unpublished features. The CacheBleed attack targets cache bank conflicts and thereby invalidates the assumption that microarchitectural side-channel adversaries can only observe memory with cache line granularity. In this work, we propose MemJam, which utilizes 4K Aliasing to establish a side-channel attack that exploits false dependency of memory read-after-write events and provides a high quality intra cache line timing channel. As a proof of concept, we demonstrate the first key recovery attacks on constant-time implementations of all symmetric block ciphers supported in the current intel integrated performance primitives (Intel IPP) cryptographic library: triple DES, AES and SM4. Further, we demonstrate the first intra cache level timing attack on SGX by reproducing the AES key recovery results on an enclave that performs encryption using the aforementioned constant-time implementation of AES. Our results show that we can not only use this side channel to efficiently attack memory dependent cryptographic operations but also to bypass proposed protections. Compared to CacheBleed, which is limited to older processor generations, MemJam is the first intra cache level attack applicable to all major Intel processors including the latest generations and also applies to the SGX extension.

Includes members:
  Member "ozone efficient execution with zero timing leakage for modern microarchitectures":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "microwalk a framework for finding side channels in binaries")
  Member "cachezoom how sgx amplifies the power of cache attacks":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "copycat controlled instruction level attacks on enclaves for maximal key extraction")
  Member "cacheshield protecting legacy processes against cache attacks":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "deepcloak adversarial crafting as a defensive measure to cloak processes")
  Member "software grand exposure sgx cache attacks are practical":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "distributed systems and trusted execution environments trade offs and challenges")
  Member "did we learn from llc side channel attacks a cache leakage detection tool for crypto libraries":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "revisiting and evaluating software side channel vulnerabilities and countermeasures in cryptographic applications")
  Member "a software approach to defeating side channels in last level caches":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "a compiler assisted scheduler for detecting and mitigating cache based side channel attacks")
  Member "inferring fine grained control flow inside sgx enclaves with branch shadowing":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "copycat controlled instruction level attacks on enclaves for maximal key extraction")
  Member "rigorous analysis of software countermeasures against cache attacks":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "specusym speculative symbolic execution for cache timing leak detection")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.CR(Cryptography and Security)