human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "training dnn iot applications for deployment on analog nvm crossbars"):
  Abstract: Deep Neural Networks (DNN) applications are increasingly being deployed in always-on IoT devices. However, the limited resources in tiny microcontroller units (MCUs) limit the deployment of the required Machine Learning (ML) models. Therefore alternatives to traditional architectures such as Computation-In-Memory based on resistive nonvolatile memories (NVM), promising high integration density, low power consumption and massively-parallel computation capabilities, are under study. However, these technologies are still immature and suffer from intrinsic analog nature problems --noise, non-linearities, inability to represent negative values, and limited-precision per device. Consequently, mapping DNNs to NVM crossbars requires the full-custom design of each one of the DNN layers, involving finely tuned blocks such as ADC/DACs or current subtractors/adders, and thus limiting the chip reconfigurability. This paper presents an NVM-aware framework to efficiently train and map the DNN to the NVM hardware. We propose the first method that trains the NN weights while ensuring uniformity across layer weights/activations, improving HW blocks re-usability. Firstly, this quantization algorithm obtains uniform scaling across the DNN layers independently of their characteristics, removing the need of per-layer full-custom design while reducing the peripheral HW. Secondly, for certain applications we make use of Network Architecture Search, to avoid using negative weights. Unipolar weight matrices translate into simpler analog periphery and lead to $67 \%$ area improvement and up to $40 \%$ power reduction. We validate our idea with CIFAR10 and HAR applications by mapping to crossbars using $4$-bit and $2$-bit devices. Up to $92.91\%$ accuracy ($95\%$ floating-point) can be achieved using $2$-bit only-positive weights for HAR.

Includes members:
  Member "sparse sparse architecture search for cnns on resource constrained microcontrollers":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "searching for winograd aware quantized networks")
  Member "differentiable quantization of deep neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "bitpruning learning bitlengths for aggressive and accurate quantization")
  Member "accurate deep neural network inference using computational phase change memory":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "noisy machines understanding noisy neural networks and enhancing robustness to analog hardware errors using distillation")
  Member "fixynn efficient hardware for mobile computer vision via transfer learning":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "searching for winograd aware quantized networks")
  Member "quantizing deep convolutional networks for efficient inference a whitepaper":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "post training piecewise linear quantization for deep neural networks")
  Member "haq hardware aware automated quantization with mixed precision":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "gan compression efficient architectures for interactive conditional gans")
  Member "discovering low precision networks close to full precision networks for efficient embedded inference":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "sparse weight activation training")
  Member "mixed precision quantization of convnets via differentiable neural architecture search":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "learning architectures for binary networks")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.LG(Machine Learning)