human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "gemmini an agile systolic array generator enabling systematic evaluations of deep learning architectures"):
  Abstract: Advances in deep learning and neural networks have resulted in the rapid development of hardware accelerators that support them. A large majority of ASIC accelerators, however, target a single hardware design point to accelerate the main computational kernels of deep neural networks such as convolutions or matrix multiplication. On the other hand, the spectrum of use-cases for neural network accelerators, ranging from edge devices to cloud, presents a prime opportunity for agile hardware design and generator methodologies. We present Gemmini -- an open source and agile systolic array generator enabling systematic evaluations of deep-learning architectures. Gemmini generates a custom ASIC accelerator for matrix multiplication based on a systolic array architecture, complete with additional functions for neural network inference. Gemmini runs with the RISC-V ISA, and is integrated with the Rocket Chip System-on-Chip generator ecosystem, including Rocket in-order cores and BOOM out-of-order cores. Through an elaborate design space exploration case study, this work demonstrates the selection processes of various parameters for the use-case of inference on edge devices. Selected design points achieve two to three orders of magnitude speedup in deep neural network inference compared to the baseline execution on a host processor. Gemmini-generated accelerators were used in the fabrication of test systems-on-chip in TSMC 16nm and Intel 22FFL process technologies.

Includes members:
  Member "integrating nvidia deep learning accelerator nvdla with risc v soc on firesim":
    also connected through other hyperedges:
      (none)
  Member "fpsa a full system stack solution for reconfigurable reram based nn accelerator architecture":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "mitigate parasitic resistance in resistive crossbar based convolutional neural networks")
  Member "co design of deep neural nets and neural net accelerators for embedded vision applications":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "synetgy algorithm hardware co design for convnet accelerators on embedded fpgas")
  Member "dnn dataflow choice is overrated":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "dnn chip predictor an analytical performance predictor for dnn accelerators with various dataflows and hardware architectures")
  Member "vta an open hardware software stack for deep learning":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "the deep learning compiler a comprehensive survey")
  Member "eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "pre defined sparsity for low complexity convolutional neural networks")
  Member "deep learning inference in facebook data centers characterization performance optimizations and hardware implications":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "improving efficiency in neural network accelerator using operands hamming distance optimization")
  Member "in datacenter performance analysis of a tensor processing unit":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "train large then compress rethinking model size for efficient training and inference of transformers")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)