human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "smash co designing software compression and hardware accelerated indexing for efficient sparse matrix operations"):
  Abstract: Important workloads, such as machine learning and graph analytics applications, heavily involve sparse linear algebra operations. These operations use sparse matrix compression as an effective means to avoid storing zeros and performing unnecessary computation on zero elements. However, compression techniques like Compressed Sparse Row (CSR) that are widely used today introduce significant instruction overhead and expensive pointer-chasing operations to discover the positions of the non-zero elements. In this paper, we identify the discovery of the positions (i.e., indexing) of non-zero elements as a key bottleneck in sparse matrix-based workloads, which greatly reduces the benefits of compression.   We propose SMASH, a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of SMASH is to explicitly enable the hardware to recognize and exploit sparsity in data. To this end, we devise a novel software encoding based on a hierarchy of bitmaps. This encoding can be used to efficiently compress any sparse matrix, regardless of the extent and structure of sparsity. At the same time, the bitmap encoding can be directly interpreted by the hardware. We design a lightweight hardware unit, the Bitmap Management Unit (BMU), that buffers and scans the bitmap hierarchy to perform highly-efficient indexing of sparse matrices. SMASH exposes an expressive and rich ISA to communicate with the BMU, which enables its use in accelerating any sparse matrix computation.   We demonstrate the benefits of SMASH on four use cases that include sparse matrix kernels and graph analytics applications. Our evaluations show that SMASH provides average performance improvements of 38% for Sparse Matrix Vector Multiplication and 44% for Sparse Matrix Matrix Multiplication, over a state-of-the-art CSR implementation, on a wide variety of matrices with different characteristics. SMASH incurs a very modest hardware area overhead of up to 0.076% of an out-of-order CPU core.

Includes members:
  Member "the architectural implications of facebook s dnn based personalized recommendation":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "deeprecsys a system for optimizing end to end at scale neural recommendation inference")
  Member "deep learning recommendation model for personalization and recommendation systems":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "strength from weakness fast learning using weak supervision")
  Member "sparse matrix multiplication on cam based accelerator":
    also connected through other hyperedges:
      (none)
  Member "performance analysis and optimization of sparse matrix vector multiplication on modern multi and many core processors":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "quenn quantization engine for low power neural networks")
  Member "graphr accelerating graph processing using reram":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "a survey on graph processing accelerators challenges and opportunities")
  Member "snap a general purpose network analysis and graph mining library":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "adaptive low level storage of very large knowledge graphs")
  Member "sparse 3d convolutional neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "differentiable volumetric rendering learning implicit 3d representations without 3d supervision")
  Member "a framework for general sparse matrix matrix multiplication on gpus and heterogeneous processors":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "a systematic survey of general sparse matrix matrix multiplication")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)