human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "achieving super linear speedup across multi fpga for real time dnn inference"):
  Abstract: Real-time Deep Neural Network (DNN) inference with low-latency requirement has become increasingly important for numerous applications in both cloud computing (e.g., Apple's Siri) and edge computing (e.g., Google/Waymo's driverless car). FPGA-based DNN accelerators have demonstrated both superior flexibility and performance; in addition, for real-time inference with low batch size, FPGA is expected to achieve further performance improvement. However, the performance gain from the single-FPGA design is obstructed by the limited on-chip resource. In this paper, we employ multiple FPGAs to cooperatively run DNNs with the objective of achieving super-linear speed-up against single-FPGA design. In implementing such systems, we found two barriers that hinder us from achieving the design goal: (1) the lack of a clear partition scheme for each DNN layer to fully exploit parallelism, and (2) the insufficient bandwidth between the off-chip memory and the accelerator due to the growing size of DNNs. To tackle these issues, we propose a general framework, "Super-LIP", which can support different kinds of DNNs. In this paper, we take Convolutional Neural Network (CNN) as a vehicle to illustrate Super-LIP. We first formulate an accurate system-level model to support the exploration of best partition schemes. Then, we develop a novel design methodology to effectively alleviate the heavy loads on memory bandwidth by moving traffic from memory bus to inter-FPGA links. We implement Super-LIP based on ZCU102 FPGA boards. Results demonstrate that Super-LIP with 2 FPGAs can achieve 3.48x speedup, compared to the state-of-the-art single-FPGA design. What is more, as the number of FPGAs scales up, the system latency can be further reduced while maintaining high energy efficiency.

Includes members:
  Member "hardware software co exploration of neural architectures":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "nass optimizing secure inference via neural architecture search")
  Member "accuracy vs efficiency achieving both through fpga implementation aware neural architecture search":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "nass optimizing secure inference via neural architecture search")
  Member "on the universal approximability and complexity bounds of quantized relu neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "dlbc a deep learning based consensus in blockchains for deep learning services")
  Member "quantization of fully convolutional networks for accurate biomedical image segmentation":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "device circuit architecture co exploration for computing in memory neural accelerators")
  Member "an unsupervised learning model for deformable medical image registration":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "when deep learning meets data alignment a review on deep registration networks drns")
  Member "in datacenter performance analysis of a tensor processing unit":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "train large then compress rethinking model size for efficient training and inference of transformers")
  Member "recent trends in deep learning based natural language processing":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "sqwa stochastic quantized weight averaging for improving the generalization capability of low precision deep neural networks")
  Member "maximizing cnn accelerator efficiency through resource partitioning":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "an energy efficient fpga based deconvolutional neural networks accelerator for single image super resolution")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)