human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "performance comparison of quasi delay insensitive asynchronous adders"):
  Abstract: In this technical note, we provide a comparison of the design metrics of various quasi-delay-insensitive (QDI) asynchronous adders, where the adders correspond to diverse architectures. QDI adders are robust, and the objective of this technical note is to point to those QDI adders which are suitable for low power/energy and less area. This information could be valuable for a resource-constrained low power VLSI design scenario. Non-QDI adders are excluded from the comparison since they are not robust although they may have optimized design metrics. All the QDI adders were realized using a 32/28nm CMOS process.

Includes members:
  Member "performance comparison of some synchronous adders":
    also connected through other hyperedges:
      (none)
  Member "asynchronous ripple carry adder based on area optimized early output dual bit full adder":
    also connected through other hyperedges:
      (none)
  Member "latency optimized asynchronous early output ripple carry adder based on delay insensitive dual rail data encoding":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "indicating asynchronous array multipliers")
  Member "a critique on asynchronous logic implementation based on factorized dims":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "indicating asynchronous array multipliers")
  Member "asynchronous early output section carry based carry lookahead adder with alias carry logic":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "speed and energy optimised quasi delay insensitive block carry lookahead adder")
  Member "asynchronous early output dual bit full adders based on homogeneous and heterogeneous delay insensitive data encoding":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "a critique on asynchronous logic implementation based on factorized dims")
  Member "comments on dual rail asynchronous logic multi level implementation":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "speed and energy optimised quasi delay insensitive block carry lookahead adder")
  Member "area latency optimized early output asynchronous full adders and relative timed ripple carry adders":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "indicating asynchronous array multipliers")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)