human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "understanding the interactions of workloads and dram types a comprehensive experimental study"):
  Abstract: It has become increasingly difficult to understand the complex interaction between modern applications and main memory, composed of DRAM chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, the memory access patterns of prevalent and emerging workloads are rapidly diverging, as these applications manipulate larger data sets in very different ways. As a result, the combined DRAM-workload behavior is often difficult to intuitively determine today, which can hinder memory optimizations in both hardware and software.  In this work, we identify important families of workloads, as well as prevalent types of DRAM chips, and rigorously analyze the combined DRAM--workload behavior. To this end, we perform a comprehensive experimental study of the interaction between nine different DRAM types and 115 modern applications and multiprogrammed workloads. We draw 12 key observations from our characterization, enabled in part by our development of new metrics that take into account contention between memory requests due to hardware design. Notably, we find that (1) newer DRAM types such as DDR4 and HMC often do not outperform older types such as DDR3, due to higher access latencies and, in the case of HMC, poor exploitation of locality; (2) there is no single DRAM type that can cater to all components of a heterogeneous system (e.g., GDDR5 significantly outperforms other memories for multimedia acceleration, while HMC significantly outperforms other memories for network acceleration); and (3) there is still a strong need to lower DRAM latency, but unfortunately the current design trend of commodity DRAM is toward higher latencies to obtain other benefits. We hope that the trends we identify can drive optimizations in both hardware and software design.

Includes members:
  Member "in dram bulk bitwise execution engine":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram")
  Member "rowhammer a retrospective":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "are we susceptible to rowhammer an end to end methodology for cloud providers")
  Member "memory centric characterization and analysis of spec cpu2017 suite":
    also connected through other hyperedges:
      (none)
  Member "d range using commodity dram devices to generate true random numbers with low latency and high throughput":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram")
  Member "understanding and improving the latency of dram based memory systems":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram")
  Member "reducing dram latency at low cost by exploiting heterogeneity":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "processing data where it makes sense enabling in memory computation")
  Member "improving dram performance by parallelizing refreshes with accesses":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "are we susceptible to rowhammer an end to end methodology for cloud providers")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)