human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "autodnnchip an automated dnn chip predictor and builder for both fpgas and asics"):
  Abstract: Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for DNN chips. However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millions of parameters and operations; (2) the large design space due to the numerous design choices of dataflows, processing elements, memory hierarchy, etc.; and (3) an algorithm/hardware co-design is needed to allow the same DNN functionality to have a different decomposition, which would require different hardware IPs to meet the application specifications. Therefore, DNN chips take a long time to design and require cross-disciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip - a DNN chip generator that can automatically generate both FPGA- and ASIC-based DNN chip implementation given DNNs from machine learning frameworks (e.g., PyTorch) for a designated application and dataset. Specifically, AutoDNNchip consists of two integrated enablers: (1) a Chip Predictor, built on top of a graph-based accelerator representation, which can accurately and efficiently predict a DNN accelerator's energy, throughput, and area based on the DNN model parameters, hardware configuration, technology-based IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selection, block configuration, resource balancing, etc.), optimize chip design via the Chip Predictor, and then generate optimized synthesizable RTL to achieve the target design metrics. Experimental results show that our Chip Predictor's predicted performance differs from real-measured ones by < 10% when validated using 15 DNN models and 4 platforms (edge-FPGA/TPU/GPU and ASIC). Furthermore, accelerators generated by our AutoDNNchip can achieve better (up to 3.86X improvement) performance than that of expert-crafted state-of-the-art accelerators.

Includes members:
  Member "e2 train training state of the art cnns with over 80 energy savings":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "towards byzantine resilient learning in decentralized systems")
  Member "skynet a hardware efficient method for object detection and tracking on embedded systems":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "agriculture vision a large aerial image database for agricultural pattern analysis")
  Member "dual dynamic inference enabling more efficient adaptive and controllable deep inference":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "triple wins boosting accuracy robustness and efficiency together by enabling input adaptive inference")
  Member "design flow of accelerating hybrid extremely low bit width neural network in embedded fpga":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "skynet a hardware efficient method for object detection and tracking on embedded systems")
  Member "mobilenetv2 inverted residuals and linear bottlenecks":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "deep k means re training and parameter sharing with harder cluster assignments for compressing deep convolutions":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "triple wins boosting accuracy robustness and efficiency together by enabling input adaptive inference")
  Member "understanding reuse performance and hardware cost of dnn dataflows a data centric approach":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "deep learning without weight transport")
  Member "face recognition with hybrid efficient convolution algorithms on fpgas":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "design flow of accelerating hybrid extremely low bit width neural network in embedded fpga")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)