human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "3d acortex an ultra compact energy efficient neurocomputing platform based on commercial 3d nand flash memories"):
  Abstract: The first contribution of this paper is the development of extremely dense, energy-efficient mixed-signal vector-by-matrix-multiplication (VMM) circuits based on the existing 3D-NAND flash memory blocks, without any need for their modification. Such compatibility is achieved using time-domain-encoded VMM design. Our detailed simulations have shown that, for example, the 5-bit VMM of 200-element vectors, using the commercially available 64-layer gate-all-around macaroni-type 3D-NAND memory blocks designed in the 55-nm technology node, may provide an unprecedented area efficiency of 0.14 um2/byte and energy efficiency of ~10 fJ/Op, including the input/output and other peripheral circuitry overheads. Our second major contribution is the development of 3D-aCortex, a multi-purpose neuromorphic inference processor that utilizes the proposed 3D-VMM blocks as its core processing units. We have performed rigorous performance simulations of such a processor on both circuit and system levels, taking into account non-idealities such as drain-induced barrier lowering, capacitive coupling, charge injection, parasitics, process variations, and noise. Our modeling of the 3D-aCortex performing several state-of-the-art neuromorphic-network benchmarks has shown that it may provide the record-breaking storage efficiency of 4.34 MB/mm2, the peak energy efficiency of 70.43 TOps/J, and the computational throughput up to 10.66 TOps/s. The storage efficiency can be further improved seven-fold by aggressively sharing VMM peripheral circuits at the cost of slight decrease in energy efficiency and throughput.

Includes members:
  Member "puma a programmable ultra efficient memristor based accelerator for machine learning inference":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "compiling neural networks for a computational memory accelerator")
  Member "a behavioral compact model for static characteristics of 3d nand flash memory":
    also connected through other hyperedges:
      (none)
  Member "a time domain analog weighted sum calculation model for extremely low power vlsi implementation of multi layer neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")
  Member "alternating multi bit quantization for recurrent neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "quantized neural network inference with precision batching")
  Member "discovering low precision networks close to full precision networks for efficient embedded inference":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "sparse weight activation training")
  Member "rapidnn in memory deep neural network acceleration framework":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram")
  Member "deep learning for iot big data and streaming analytics a survey":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "a survey on machine learning based performance improvement of wireless networks phy mac and network layer")
  Member "energy efficient time domain vector by matrix multiplier for neurocomputing and beyond":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.ET(Emerging Technologies)