human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "tuning algorithms and generators for efficient edge inference"):
  Abstract: A surge in artificial intelligence and autonomous technologies have increased the demand toward enhanced edge-processing capabilities. Computational complexity and size of state-of-the-art Deep Neural Networks (DNNs) are rising exponentially with diverse network models and larger datasets. This growth limits the performance scaling and energy-efficiency of both distributed and embedded inference platforms. Embedded designs at the edge are constrained by energy and speed limitations of available processor substrates and processor to memory communication required to fetch the model coefficients. While many hardware accelerator and network deployment frameworks have been in development, a framework is needed to allow the variety of existing architectures, and those in development, to be expressed in critical parts of the flow that perform various optimization steps. Moreover, premature architecture-blind network selection and optimization diminish the effectiveness of schedule optimizations and hardware-specific mappings. In this paper, we address these issues by creating a cross-layer software-hardware design framework that encompasses network training and model compression that is aware of and tuned to the underlying hardware architecture. This approach leverages the available degrees of DNN structure and sparsity to create a converged network that can be partitioned and efficiently scheduled on the target hardware platform, minimizing data movement, and improving the overall throughput and energy. To further streamline the design, we leverage the high-level, flexible SoC generator platform based on RISC-V ROCC framework. This integration allows seamless extensions of the RISC-V instruction set and Chisel-based rapid generator design. Utilizing this approach, we implemented a silicon prototype in a 16 nm TSMC process node achieving record processing efficiency of up to 18 TOPS/W.

Includes members:
  Member "synetgy algorithm hardware co design for convnet accelerators on embedded fpgas":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "performance oriented neural architecture search")
  Member "fully learnable group convolution for acceleration of deep neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "model agnostic structured sparsification with learnable channel shuffle")
  Member "bridging the accuracy gap for 2 bit quantized neural networks qnn":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "sparse weight activation training")
  Member "learning grouped convolution for efficient domain adaptation":
    also connected through other hyperedges:
      (none)
  Member "mpdcompress matrix permutation decomposition algorithm for deep neural network compression":
    also connected through other hyperedges:
      (none)
  Member "chamnet towards efficient network design through platform aware model adaptation":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "metapruning meta learning for automatic neural network channel pruning")
  Member "block sparse recurrent neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "block wise dynamic sparseness")
  Member "in datacenter performance analysis of a tensor processing unit":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "train large then compress rethinking model size for efficient training and inference of transformers")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)