human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "design space exploration of hardware spiking neurons for embedded artificial intelligence"):
  Abstract: Abstract   Machine learning is yielding unprecedented interest in research and industry, due to recent success in many applied contexts such as image classification and object recognition. However, the deployment of these systems requires huge computing capabilities, thus making them unsuitable for embedded systems. To deal with this limitation, many researchers are investigating brain-inspired computing, which would be a perfect alternative to the conventional Von Neumann architecture based computers (CPU/GPU) that meet the requirements for computing performance, but not for energy-efficiency. Therefore, neuromorphic hardware circuits that are adaptable for both parallel and distributed computations need to be designed. In this paper, we focus on Spiking Neural Networks (SNNs) with a comprehensive study of neural coding methods and hardware exploration. In this context, we propose a framework for neuromorphic hardware design space exploration, which allows to define a suitable architecture based on application-specific constraints and starting from a wide variety of possible architectural choices. For this framework, we have developed a behavioral level simulator for neuromorphic hardware architectural exploration named NAXT. Moreover, we propose modified versions of the standard Rate Coding technique to make trade-offs with the Time Coding paradigm, which is characterized by the low number of spikes propagating in the network. Thus, we are able to reduce the number of spikes while keeping the same neuron’s model, which results in an SNN with fewer events to process. By doing so, we seek to reduce the amount of power consumed by the hardware. Furthermore, we present three neuromorphic hardware architectures in order to quantitatively study the implementation of SNNs. One of these architectures integrates a novel hybrid structure: a highly-parallel computation core for most solicited layers, and time-multiplexed computation units for deeper layers. These architectures are derived from a novel funnel-like Design Space Exploration framework for neuromorphic hardware.

Includes members:
  Member "deep learning in spiking neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")
  Member "spyketorch efficient simulation of convolutional spiking neural networks with at most one spike per neuron":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "a deep unsupervised feature learning spiking neural network with binarized classification layers for emnist classification")
  Member "stdp based spiking deep convolutional neural networks for object recognition":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "a deep unsupervised feature learning spiking neural network with binarized classification layers for emnist classification")
  Member "efficient processing of deep neural networks a tutorial and survey":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "searching for winograd aware quantized networks")
  Member "a scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors dynaps":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")
  Member "a survey of neuromorphic computing and neural networks in hardware":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")
  Member "supervised learning based on temporal coding in spiking neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "a deep unsupervised feature learning spiking neural network with binarized classification layers for emnist classification")
  Member "hfirst a temporal approach to object recognition":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "matrix lstm a differentiable recurrent surface for asynchronous event based data")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.NE(Neural and Evolutionary Computing)