human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "qutibench benchmarking neural networks on heterogeneous hardware"):
  Abstract: Neural Networks have become one of the most successful universal machine learning algorithms. They play a key role in enabling machine vision and speech recognition for example. Their computational complexity is enormous and comes along with equally challenging memory requirements, which limits deployment in particular within energy constrained, embedded environments. In order to address these implementation challenges, a broad spectrum of new customized and heterogeneous hardware architectures have emerged, often accompanied with co-designed algorithms to extract maximum benefit out of the hardware. Furthermore, numerous optimization techniques are being explored for neural networks to reduce compute and memory requirements while maintaining accuracy. This results in an abundance of algorithmic and architectural choices, some of which fit specific use cases better than others. #R##N#For system level designers, there is currently no good way to compare the variety of hardware, algorithm and optimization options. While there are many benchmarking efforts in this field, they cover only subsections of the embedded design space. None of the existing benchmarks support essential algorithmic optimizations such as quantization, an important technique to stay on chip, or specialized heterogeneous hardware architectures. We propose a novel benchmark suite, QuTiBench, that addresses this need. QuTiBench is a novel multi-tiered benchmarking methodology that supports algorithmic optimizations such as quantization and helps system developers understand the benefits and limitations of these novel compute architectures in regard to specific neural networks and will help drive future innovation. We invite the community to contribute to QuTiBench in order to support the full spectrum of choices in implementing machine learning systems.

Includes members:
  Member "analysis of dawnbench a time to accuracy machine learning performance benchmark":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "towards the systematic reporting of the energy and carbon footprints of machine learning")
  Member "binareye an always on energy accuracy scalable binary cnn processor with all memory on chip in 28nm cmos":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "precise neural network computation with imprecise analog devices")
  Member "training and inference with integers in deep neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "sparse weight activation training")
  Member "tvm end to end optimization stack for deep learning":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "torch struct deep structured prediction library")
  Member "finn l library extensions and design trade off analysis for variable precision lstm networks on fpgas":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "recurrent neural networks an embedded computing perspective")
  Member "bismo a scalable bit serial matrix multiplication overlay for reconfigurable computing":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "efficient bitwidth search for practical mixed precision neural network")
  Member "tbd benchmarking and analyzing deep neural network training":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "aibench an agile domain specific benchmarking methodology and an ai benchmark suite")
  Member "in datacenter performance analysis of a tensor processing unit":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "train large then compress rethinking model size for efficient training and inference of transformers")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)