human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "co exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks"):
  Abstract: Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs). However, it remains an open problem, how to integrate NAS with Application-Specific Integrated Circuits (ASICs), despite them being the most powerful AI accelerating platforms. The major bottleneck comes from the large design freedom associated with ASIC designs. Moreover, with the consideration that multiple DNNs will run in parallel for different workloads with diverse layer operations and sizes, integrating heterogeneous ASIC sub-accelerators for distinct DNNs in one design can significantly boost performance, and at the same time further complicate the design space. To address these challenges, in this paper we build ASIC template set based on existing successful designs, described by their unique dataflows, so that the design space is significantly reduced. Based on the templates, we further propose a framework, namely NASAIC, which can simultaneously identify multiple DNN architectures and the associated heterogeneous ASIC accelerator design, such that the design specifications (specs) can be satisfied, while the accuracy can be maximized. Experimental results show that compared with successive NAS and ASIC design optimizations which lead to design spec violations, NASAIC can guarantee the results to meet the design specs with 17.77%, 2.49x, and 2.32x reductions on latency, energy, and area and with 0.76% accuracy loss. To the best of the authors' knowledge, this is the first work on neural architecture and ASIC accelerator design co-exploration.

Includes members:
  Member "nass optimizing secure inference via neural architecture search":
    also connected through other hyperedges:
      (none)
  Member "hardware software co exploration of neural architectures":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "nass optimizing secure inference via neural architecture search")
  Member "achieving super linear speedup across multi fpga for real time dnn inference":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "low overhead online data flow tracking for intermittently powered non volatile fpgas")
  Member "herald optimizing heterogeneous dnn accelerators for edge devices":
    also connected through other hyperedges:
      (none)
  Member "on neural architecture search for resource constrained hardware platforms":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "nass optimizing secure inference via neural architecture search")
  Member "proxylessnas direct neural architecture search on target task and hardware":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "gan compression efficient architectures for interactive conditional gans")
  Member "darts differentiable architecture search":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "gan compression efficient architectures for interactive conditional gans")
  Member "mnasnet platform aware neural architecture search for mobile":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "automl zero evolving machine learning algorithms from scratch")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.LG(Machine Learning)