human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "eden enabling energy efficient high performance deep neural network inference using approximate dram"):
  Abstract: The effectiveness of deep neural networks (DNN) in vision, speech, and language processing has prompted a tremendous demand for energy-efficient high-performance DNN inference systems. Due to the increasing memory intensity of most DNN workloads, main memory can dominate the system's energy consumption and stall time. One effective way to reduce the energy consumption and increase the performance of DNN inference systems is by using approximate memory, which operates with reduced supply voltage and reduced access latency parameters that violate standard specifications. Using approximate memory reduces reliability, leading to higher bit error rates. Fortunately, neural networks have an intrinsic capacity to tolerate increased bit errors. This can enable energy-efficient and high-performance neural network inference using approximate DRAM devices. #R##N#Based on this observation, we propose EDEN, a general framework that reduces DNN energy consumption and DNN evaluation latency by using approximate DRAM devices, while strictly meeting a user-specified target DNN accuracy. EDEN relies on two key ideas: 1) retraining the DNN for a target approximate DRAM device to increase the DNN's error tolerance, and 2) efficient mapping of the error tolerance of each individual DNN data type to a corresponding approximate DRAM partition in a way that meets the user-specified DNN accuracy requirements. #R##N#We evaluate EDEN on multi-core CPUs, GPUs, and DNN accelerators with error models obtained from real approximate DRAM devices. For a target accuracy within 1% of the original DNN, our results show that EDEN enables 1) an average DRAM energy reduction of 21%, 37%, 31%, and 32% in CPU, GPU, and two DNN accelerator architectures, respectively, across a variety of DNNs, and 2) an average (maximum) speedup of 8% (17%) and 2.7% (5.5%) in CPU and GPU architectures, respectively, when evaluating latency-bound DNNs.

Includes members:
  Member "generalized intersection over union a metric and a loss for bounding box regression":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "siamese box adaptive network for visual tracking")
  Member "in dram bulk bitwise execution engine":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "a workload and programming ease driven perspective of processing in memory")
  Member "analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "in place zero space memory protection for cnn")
  Member "amc automl for model compression and acceleration on mobile devices":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "discrimination aware network pruning for deep model compression")
  Member "high accuracy low precision training":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "sparse weight activation training")
  Member "nullanet training deep neural networks for reduced memory access inference":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "karnet an efficient boolean function simplifier")
  Member "towards understanding the role of over parametrization in generalization of neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "the implicit and explicit regularization effects of dropout")
  Member "tvm an automated end to end optimizing compiler for deep learning":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "the deep learning compiler a comprehensive survey")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)