human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "processing data where it makes sense enabling in memory computation"):
  Abstract: Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks: (1) data access from memory is already a key bottleneck as applications become more data-intensive and memory bandwidth and energy do not scale well, (2) energy consumption is a key constraint in especially mobile and server systems, (3) data movement is very expensive in terms of bandwidth, energy and latency, much more so than computation. #R##N#At the same time, conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of higher cost. The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside DRAM chips, and the necessity for designing new solutions to serious reliability and security issues, such as the RowHammer phenomenon, are an evidence of this trend. #R##N#Recent research aims to practically enable computation close to data. We discuss at least two promising directions for processing-in-memory (PIM): (1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes, (2) exploiting the logic layer in 3D-stacked memory technology to accelerate important data-intensive applications. In both approaches, we describe and tackle relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, and programming models. Our focus is on the development of in-memory processing designs that can be adopted in real computing platforms at low cost.

Includes members:
  Member "enabling the adoption of processing in memory challenges mechanisms future research directions":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "machine learning systems for highly distributed and rapidly growing data")
  Member "architectural techniques for improving nand flash memory reliability":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "large scale studies of memory storage and network failures in a modern data center")
  Member "what your dram power models are not telling you lessons from a detailed experimental study":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "rowhammer a retrospective")
  Member "techniques for shared resource management in systems with throughput processors":
    also connected through other hyperedges:
      (none)
  Member "errors in flash memory based solid state drives analysis mitigation and recovery":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "rowhammer a retrospective")
  Member "the rowhammer problem and other issues we may face as memory becomes denser":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "are we susceptible to rowhammer an end to end methodology for cloud providers")
  Member "error characterization mitigation and recovery in flash memory based solid state drives":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "rowhammer a retrospective")
  Member "using ecc dram to adaptively increase memory capacity":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "enabling practical processing in and near memory for data intensive computing")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.AR(Hardware Architecture)