human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "flexible communication avoiding matrix multiplication on fpga with high level synthesis"):
  Abstract: Data movement is the dominating factor affecting performance and energy in modern computing systems. Consequently, many algorithms have been developed to minimize the number of I/O operations for common computing patterns. Matrix multiplication is no exception, and lower bounds have been proven and implemented both for shared and distributed memory systems. Reconfigurable hardware platforms are a lucrative target for I/O minimizing algorithms, as they offer full control of memory accesses to the programmer. While bounds developed in the context of fixed architectures still apply to these platforms, the spatially distributed nature of their computational and memory resources requires a decentralized approach to optimize algorithms for maximum hardware utilization. We present a model to optimize matrix multiplication for FPGA platforms, simultaneously targeting maximum performance and minimum off-chip data movement, within constraints set by the hardware. We map the model to a concrete architecture using a high-level synthesis tool, maintaining a high level of abstraction, allowing us to support arbitrary data types, and enables maintainability and portability across FPGA devices. Kernels generated from our architecture are shown to offer competitive performance in practice, scaling with both compute and memory resources. We offer our design as an open source project to encourage the open development of linear algebra and I/O minimizing algorithms on reconfigurable hardware platforms.

Includes members:
  Member "red blue pebbling revisited near optimal parallel matrix matrix multiplication":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "practice of streaming and dynamic graphs concepts models systems and parallelism")
  Member "hlslib software engineering for hardware design":
    also connected through other hyperedges:
      (none)
  Member "demystifying parallel and distributed deep learning an in depth concurrency analysis":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "communication optimization strategies for distributed deep learning a survey")
  Member "communication optimal convolutional neural nets":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "improving strong scaling of cnn training by exploiting finer grained parallelism")
  Member "integrated model batch and domain parallelism in training neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "checkmate breaking the memory wall with optimal tensor rematerialization")
  Member "communication lower bounds for distributed memory computations":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "equivalence classes and conditional hardness in massively parallel computations")
  Member "communication lower bounds for distributed memory computations":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "equivalence classes and conditional hardness in massively parallel computations")
  Member "hitting the memory wall implications of the obvious":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "achieving multi port memory performance on single port memory with coding techniques")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)