human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "architecture aware high performance transaction for persistent memory"):
  Abstract: Byte-addressable non-volatile main memory (NVM) demands transactional mechanisms to access and manipulate data on NVM atomically. Those transaction mechanisms often employ a logging mechanism (undo logging or redo logging). However, the logging mechanisms can bring large runtime overhead (8%-49% in our evaluation), and 41%-78% of the overhead attributes to the frequent cache-line flushing. Such large overhead significantly diminishes the performance benefits offered by NVM. In this paper, we introduce a new method to reduce the overhead of cache-line flushing for logging-based transactions. Different from the traditional method that works at the program level and leverages program semantics to reduce the logging overhead, we introduce architecture awareness. In particular, we do not flush certain cache blocks, as long as they are estimated to be eliminated out of the cache because of the hardware caching mechanism (e.g., the cache replacement algorithm). Furthermore, we coalesce those cache blocks with low dirtiness to improve the efficiency of cache-line flushing. We implement an architecture-aware, high performance transaction runtime system for persistent memory, Archapt. Our results show that comparing with an undo logging (PMDK) and a redo logging (Mnemosyne), Archapt reduces cache-line flushing by 66% and improves system throughput by 19% on average (42% at most). Our crash tests with four hardware caching policies show that Archapt provides a strong guarantee on crash consistency.

Includes members:
  Member "basic performance measurements of the intel optane dc persistent memory module":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "demystifying the performance of hpc scientific applications on nvm based memory systems")
  Member "persistent memory transactions":
    also connected through other hyperedges:
      (none)
  Member "algorithm directed crash consistence in non volatile memory for hpc":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "easycrash exploring non volatility of non volatile memory for high performance computing under failures")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.DC(Distributed, Parallel, and Cluster Computing)