human: Given a hyperedge-centered hypergraph: <hypergraph>, where the center hyperedge is induced by one source paper and its member nodes are the cited papers.

Details of the hypergraph:
Center hyperedge (induced by source paper "morphic a 65 nm 738k synapse mm 2 quad core binary weight digital neuromorphic processor with stochastic spike driven online learning"):
  Abstract: Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient SNNs still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this paper, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86 mm  $^2$   in 65-nm CMOS, achieving a high density of 738k synapses/mm  $^2$  . MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.

Includes members:
  Member "a 0 086 mm 2 12 7 pj sop 64k synapse 256 neuron online learning digital spiking neuromorphic processor in 28 nm cmos":
    also connected through other hyperedges:
      - Hyperedge HE-1 (induced by source paper "an internal clock based space time neural network for motion speed recognition")
  Member "a neuromorphic systems approach to in memory computing with non ideal memristive devices from mitigation to exploitation":
    also connected through other hyperedges:
      - Hyperedge HE-2 (induced by source paper "a neuromorphic boost to rnns using low pass filters")
  Member "binareye an always on energy accuracy scalable binary cnn processor with all memory on chip in 28nm cmos":
    also connected through other hyperedges:
      - Hyperedge HE-3 (induced by source paper "precise neural network computation with imprecise analog devices")
  Member "minimum energy quantized neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-4 (induced by source paper "pulp nn accelerating quantized neural networks on parallel ultra low power risc v processors")
  Member "a scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors dynaps":
    also connected through other hyperedges:
      - Hyperedge HE-5 (induced by source paper "a supervised learning algorithm for multilayer spiking neural networks based on temporal coding toward energy efficient vlsi processor design")
  Member "event driven random back propagation enabling neuromorphic deep learning machines":
    also connected through other hyperedges:
      - Hyperedge HE-6 (induced by source paper "a deep unsupervised feature learning spiking neural network with binarized classification layers for emnist classification")
  Member "binarized neural networks training deep neural networks with weights and activations constrained to 1 or 1":
    also connected through other hyperedges:
      - Hyperedge HE-7 (induced by source paper "lossless compression of deep neural networks")
  Member "supervised learning based on temporal coding in spiking neural networks":
    also connected through other hyperedges:
      - Hyperedge HE-8 (induced by source paper "a deep unsupervised feature learning spiking neural network with binarized classification layers for emnist classification")

Question: Please tell me which class the source paper belongs to. The 40 classes are: cs.NA(Numerical Analysis), cs.MM(Multimedia), cs.LO(Logic in Computer Science), cs.CY(Computers and Society), cs.CR(Cryptography and Security), cs.DC(Distributed, Parallel, and Cluster Computing), cs.HC(Human-Computer Interaction), cs.CE(Computational Engineering, Finance, and Science), cs.NI(Networking and Internet Architecture), cs.CC(Computational Complexity), cs.AI(Artificial Intelligence), cs.MA(Multiagent Systems), cs.GL(General Literature), cs.NE(Neural and Evolutionary Computing), cs.SC(Symbolic Computation), cs.AR(Hardware Architecture), cs.CV(Computer Vision and Pattern Recognition), cs.GR(Graphics), cs.ET(Emerging Technologies), cs.SY(Systems and Control), cs.CG(Computational Geometry), cs.OH(Other Computer Science), cs.PL(Programming Languages), cs.SE(Software Engineering), cs.LG(Machine Learning), cs.SD(Sound), cs.SI(Social and Information Networks), cs.RO(Robotics), cs.IT(Information Theory), cs.PF(Performance), cs.CL(Computation and Language), cs.IR(Information Retrieval), cs.MS(Mathematical Software), cs.FL(Formal Languages and Automata Theory), cs.DS(Data Structures and Algorithms), cs.OS(Operating Systems), cs.GT(Computer Science and Game Theory), cs.DB(Databases), cs.DL(Digital Libraries), cs.DM(Discrete Mathematics). Directly output the class name.

gpt: cs.NE(Neural and Evolutionary Computing)