Task: Formula-prediction-context (source dataset: ti-random)

You are given an table region extracted from a real Excel spreadsheet, which is centered around a cell called "Target Cell" (labeled as "[Target Cell]" shown in the table below). The table region below includes up to 10 rows above/below the Target Cell, and 10 columns to the left/right of the Target Cell. 

Your task is to analyze the table context surrounding the Target Cell, and predict the most likely Excel formula that should go in the Target Cell. If multiple formulas are possible, choose the most reasonable or commonly used based on context.

1. Please follow the standard formula syntax in Excel, e.g. always begins with an equal sign (=).
2. Base your predicted formula on the surrounding table context, e.g., column headers, annotations, and data values in nearby cells.
3. No explanation — just output the formula itself in a JSON format: {"formula": "your_formula_here"}.

Input Excel Snippet in Markdown format:
|    | A         | B                                                                                | C                   | D     | E   | F   | G   | H   | I   | J   | K   | L   | M   |
|---:|:----------|:---------------------------------------------------------------------------------|:--------------------|:------|:----|:----|:----|:----|:----|:----|:----|:----|:----|
| 63 | Rdson     | FET Rdson @ Tj max(start with ~100C)                                             | 1.4605              | m-Ω   |     |     |     |     |     |     |     |     |     |
| 64 |           | FET Gate Charge to reach Vgs > Vta (single FET)                                  | 2.7e-08             | C     |     |     |     |     |     |     |     |     |     |
| 65 | # FETs    | Number of parallel FETs                                                          | 1                   |       |     |     |     |     |     |     |     |     |     |
| 66 | Retry?    | Is this configured in retry mode? (Yes or No)                                    | No                  |       |     |     |     |     |     |     |     |     |     |
| 67 | dV/dT?    | Gate Slew Rate Control? (Yes or No)                                              | No                  |       |     |     |     |     |     |     |     |     |     |
| 68 | Iramp     | Choose output capacitor charge current (<Plim/Vccmax)                            | 0.2                 | A     |     |     |     |     |     |     |     |     |     |
| 69 |           |                                                                                  |                     |       |     |     |     |     |     |     |     |     |     |
| 70 | Results   |                                                                                  |                     |       |     |     |     |     |     |     |     |     |     |
| 71 | Parameter | Description                                                                      | Value               | Units |     |     |     |     |     |     |     |     |     |
| 72 | Tcap      | Time to charge output cap under Power Limiting                                   | 0.6800713099773825  | ms    |     |     |     |     |     |     |     |     |     |
| 73 | T_FET     | Time to charge Vgs to Vt, and Vt to Vta once Vout is up                          | [Target Cell]       | ms    |     |     |     |     |     |     |     |     |     |
| 74 | T_dVdT    | Time for Vgate = Vbus+Vta, when using dv/dt start-up                             | 0                   | ms    |     |     |     |     |     |     |     |     |     |
| 75 | T_total   | Typical Start Time                                                               | 1.5800713099773827  | ms    |     |     |     |     |     |     |     |     |     |
| 76 | T_margin  | Timer Margin (Accounts for tolerance of QFET, I_timer, I_source, P_LIM, C_timer) | 50                  | %     |     |     |     |     |     |     |     |     |     |
| 77 | T_fault   | Programmed Fault time                                                            | 2.370106964966074   | ms    |     |     |     |     |     |     |     |     |     |
| 78 | PDCFET    | Maximum steady state FET power dissipation (per FET)                             | 0.10695172500000003 | W     |     |     |     |     |     |     |     |     |     |
| 79 | TJDCMAX   | Maximum Steady State Junction temperature                                        | 48.20855175         | ˚C    |     |     |     |     |     |     |     |     |     |
| 80 | SOA_25C   | Power FET can handle for T_fault @ 25C                                           | 477.0047937111712   | W     |     |     |     |     |     |     |     |     |     |
| 81 | SOA_der   | derate above for the elevated junction temperature                               | 388.4400701924209   | W     |     |     |     |     |     |     |     |     |     |
| 82 | SOA_mrg   | SOA margin                                                                       | 74.35897899239352   | %     |     |     |     |     |     |     |     |     |     |
| 83 |           | Minimum Recommended SOA margin                                                   | 10                  | %     |     |     |     |     |     |     |     |     |     |



min_row: 63
max_row: 83
min_col: 1
max_col: 13
target_cell_row_idx: 73
target_cell_col_idx: 3
target_cell_value: 0.9
formula: =(No_of_FETs*FET_Gate_Charge_to_reach_Vgs_5.9V/I_gate)*1000