Task: Data-Imputation (source dataset: tablib)

Please fill in the missing value in the input table. The missing value is denoted by '[MISSING]'. Please only return the value filled in. Do not return the whole table.

No explanation, return the value filled in JSON format: {"value": "filled_value"}. 

Input Table:
| Signal Name                        | Interface   | I/O   | Initial   | Description                            |
|                                    |             |       | State     |                                        |
|:-----------------------------------|:------------|:------|:----------|:---------------------------------------|
| System Signals                     | None        | None  | None      | None                                   |
| Interrupt                          |             | O     | 0         | Interrupt from UART                    |
| Debug_SYS_Rst                      |             | O     | 0         | Debug system reset                     |
| Ext_BRK                            |             | O     | 0         | External break                         |
| Ext_NM_BRK                         |             | O     | 0         | External non-maskable break            |
| PLB Interface Signals              | None        | None  | None      | None                                   |
| SPLB_Clk                           | SPLB        | I     | -         | PLB clock                              |
| SPLB_Rst                           | SPLB        | I     | -         | PLB reset                              |
| PLB_ABus[0:31]                     | SPLB        | I     | -         | PLB address bus                        |
| PLB_UABus[0:31]                    | SPLB        | I     | -         | PLB upper address bus                  |
| PLB_PAValid                        | SPLB        | I     | -         | PLB primary address valid              |
| PLB_SAValid                        | SPLB        | I     | -         | PLB secondary address valid            |
| PLB_rdPrim                         | SPLB        | I     | -         | PLB secondary to primary read request  |
|                                    |             |       |           | indicator                              |
| PLB_wrPrim                         | SPLB        | I     | -         | PLB secondary to primary write request |
|                                    |             |       |           | indicator                              |
| PLB_MasterID[0:C_SPLB_MID_WIDTH-1] | SPLB        | I     | -         | PLB current master identifier          |
| PLB_busLock                        | SPLB        | I     | -         | PLB bus lock                           |
| PLB_abort                          | SPLB        | I     | -         | PLB abort                              |
| PLB_RNW                            | SPLB        | I     | -         | PLB read not write                     |
| PLB_BE[0:C_SPLB_DWIDTH/8 - 1]      | SPLB        | I     | -         | PLB byte enables                       |
| PLB_MSize[0:1]                     | SPLB        | I     | -         | PLB data bus width indicator           |
| PLB_size[0:3]                      | SPLB        | I     | -         | PLB size of requested transfer         |
| PLB_type[0"2]                      | SPLB        | I     | -         | PLB transfer type                      |
| PLB_lockErr                        | SPLB        | I     | -         | PLB lock error                         |
| PLB_wrDBus[0:C_SPLB_DWIDTH-1]      | SPLB        | I     | -         | [MISSING]                              |
| PLB_wrBurst                        | SPLB        | I     | -         | PLB burst write transfer               |
| PLB_rdBurst                        | SPLB        | I     | -         | PLB burst read transfer                |
| PLB_wrPendReq                      | SPLB        | I     | -         | PLB pending bus write request          |
| PLB_rdPendReq                      | SPLB        | I     | -         | PLB pending bus read request           |
| PLB_wrPendPri[0:1]                 | SPLB        | I     | -         | PLB pending write request priority     |
| PLB_rdPendPri[0:1]                 | SPLB        | I     | -         | PLB pending read request priority      |
| PLB_reqPri[0:1]                    | SPLB        | I     | -         | PLB current request priority           |
| PLB_TAttribute[0:15]               | SPLB        | I     | -         | PLB transfer attribute                 |
| Sl_addrAck                         | SPLB        | O     | -         | Slave address acknowledge              |
| Sl_SSize[0:1]                      | SPLB        | O     | -         | Slave data bus size                    |



row_idx: 23
col_idx: 4
col_name: Description
label: PLB write data bus
output: value: PLB write data bus
tablib_key: tables/job=github_000005/batch=008354/ufPclpuxEnOje2NT3FDi8a0itd6WAN61tMnHx24vztE=