Task: Formula-prediction-context (source dataset: ti-random)

You are given an table region extracted from a real Excel spreadsheet, which is centered around a cell called "Target Cell" (labeled as "[Target Cell]" shown in the table below). The table region below includes up to 10 rows above/below the Target Cell, and 10 columns to the left/right of the Target Cell. 

Your task is to analyze the table context surrounding the Target Cell, and predict the most likely Excel formula that should go in the Target Cell. If multiple formulas are possible, choose the most reasonable or commonly used based on context.

1. Please follow the standard formula syntax in Excel, e.g. always begins with an equal sign (=).
2. Base your predicted formula on the surrounding table context, e.g., column headers, annotations, and data values in nearby cells.
3. No explanation — just output the formula itself in a JSON format: {"formula": "your_formula_here"}.

Input Excel Snippet in Markdown format:
|    | A   | B                                                                                                                                                                                                                                                                                                                                    | C                               | D                 | E                                      | F                                  | G   |
|---:|:----|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|:--------------------------------|:------------------|:---------------------------------------|:-----------------------------------|:----|
|  8 |     | DDR3 Output Clock Period                                                                                                                                                                                                                                                                                                             | 2.5                             | ns                |                                        |                                    |     |
|  9 |     | Device                                                                                                                                                                                                                                                                                                                               | MT41K256M16 125 (1600)          |                   |                                        |                                    |     |
| 10 |     | Speed Grade                                                                                                                                                                                                                                                                                                                          | 1600                            | MT/s              |                                        |                                    |     |
| 11 |     |                                                                                                                                                                                                                                                                                                                                      |                                 |                   |                                        |                                    |     |
| 12 |     | Note that the DDR3 PLL on KeyStone-II devices will need to output half of the DDR3 clock frequency.  The DDR3 PLL output frequency will be a quarter of the DDR3 data rate.  We recommend configuring the VCO of the PLL (using PLLD and PLLM) to operate at the DDR3 data rate and then programming the OD field for a divide by 4. |                                 |                   |                                        |                                    |     |
| 13 |     |                                                                                                                                                                                                                                                                                                                                      |                                 |                   |                                        |                                    |     |
| 14 |     |                                                                                                                                                                                                                                                                                                                                      |                                 |                   |                                        |                                    |     |
| 15 |     | SDRAM and PHY Configuration                                                                                                                                                                                                                                                                                                          |                                 |                   |                                        |                                    |     |
| 16 |     |                                                                                                                                                                                                                                                                                                                                      |                                 |                   |                                        |                                    |     |
| 17 |     |                                                                                                                                                                                                                                                                                                                                      | Register                        | Recommended Value | Corresponding Register Value (decimal) | Corresponding Register Value (hex) |     |
|    |     |                                                                                                                                                                                                                                                                                                                                      | Settings Selected               |                   |                                        |                                    |     |
| 18 |     | IBANK_POS                                                                                                                                                                                                                                                                                                                            | 8 banks open for interleaving   |                   | 0                                      | [Target Cell]                      |     |
| 19 |     | DDR_TERM                                                                                                                                                                                                                                                                                                                             | RZQ/4                           | RZQ/4             | 1                                      | 1                                  |     |
| 20 |     | DYN_ODT                                                                                                                                                                                                                                                                                                                              | Disable ODT                     | Disable           | 0                                      | 0                                  |     |
| 21 |     | SDRAM_DRIVE                                                                                                                                                                                                                                                                                                                          | RZQ/7                           | RZQ/7             | 1                                      | 1                                  |     |
| 22 |     | CAS_WRITE_LATENCY                                                                                                                                                                                                                                                                                                                    | CWL = 8                         |                   | 3                                      | 3                                  |     |
| 23 |     | Narrow Mode                                                                                                                                                                                                                                                                                                                          | 64-bit bus width                |                   | 0                                      | 0                                  |     |
| 24 |     | ECC Byte                                                                                                                                                                                                                                                                                                                             | Enable                          |                   | 1                                      | 1                                  |     |
| 25 |     | CAS_LATENCY                                                                                                                                                                                                                                                                                                                          | CAS = 9                         |                   | 10                                     | A                                  |     |
| 26 |     | IBANK                                                                                                                                                                                                                                                                                                                                | 8 bank SDRAM                    |                   | 3                                      | 3                                  |     |
| 27 |     | EBANK                                                                                                                                                                                                                                                                                                                                | Single Rank - only use CE0      |                   | 0                                      | 0                                  |     |
| 28 |     | PAGESIZE                                                                                                                                                                                                                                                                                                                             | 1024-word page - 10 column bits |                   | 2                                      | 2                                  |     |



min_row: 8
max_row: 28
min_col: 1
max_col: 7
target_cell_row_idx: 18
target_cell_col_idx: 6
target_cell_value: 0
formula: =DEC2HEX(E18)