Task: Formula-prediction-context (source dataset: ti-random)

You are given an table region extracted from a real Excel spreadsheet, which is centered around a cell called "Target Cell" (labeled as "[Target Cell]" shown in the table below). The table region below includes up to 10 rows above/below the Target Cell, and 10 columns to the left/right of the Target Cell. 

Your task is to analyze the table context surrounding the Target Cell, and predict the most likely Excel formula that should go in the Target Cell. If multiple formulas are possible, choose the most reasonable or commonly used based on context.

1. Please follow the standard formula syntax in Excel, e.g. always begins with an equal sign (=).
2. Base your predicted formula on the surrounding table context, e.g., column headers, annotations, and data values in nearby cells.
3. No explanation — just output the formula itself in a JSON format: {"formula": "your_formula_here"}.

Input Excel Snippet in Markdown format:
|    | A   | B                                                                                           | C                  | D             | E                   | F      | G   | H   | I              | J                  | K                  | L             | M                   | N      | O   |
|---:|:----|:--------------------------------------------------------------------------------------------|:-------------------|:--------------|:--------------------|:-------|:----|:----|:---------------|:-------------------|:-------------------|:--------------|:--------------------|:-------|:----|
|  2 |     | U4 is the first DDR3 chip and the rest in row is U5, U8, U16, U17                           |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  3 |     |                                                                                             |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  4 |     | The rule on DSP0_DDR3_ECK is matched in 20mils to each RAM chips.                           |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  5 |     | CK[p/n] ≦ 20 mils ( <=5pS)                                                                  |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  6 |     |                                                                                             |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  7 |     | The rule on CMD and CTL is skew-matched of DSP0_DDR3_ECK[p/n] in 20mils to each DDR3 chips. |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  8 |     | CMD/CTL ≦ CLK ± 20mils                                                                      |                    |               |                     |        |     |     |                |                    |                    |               |                     |        |     |
|  9 |     |                                                                                             |                    |               |                     |        |     |     | BANK A         |                    |                    |               |                     |        |     |
| 10 |     | R_DDR_ADD_U4 (27)                                                                           | Rule               | Length (mils) | skew (mils)         | Check  |     |     | DDDR_ADDR (11) |                    | Rule               | Length (mils) | Skew (mils)         | Check  |     |
| 11 |     | DSP1.A12:U4.J7 [DSP0_DDR3_ECKP_0]                                                           | TARGET             | 2315.91       |                     | Target |     |     | DDR0_CK_P_CPU  | U3200.A12:U3400.J7 | TARGET             | 1849.338      | 0                   | Target |     |
| 12 |     | DSP1.B12:U4.K7 [DSP0_DDR3_ECKN_0]                                                           | 0.00 MIL:20.00 MIL | 2315.16       | [Target Cell]       | Pass   |     |     | DDR0_CK_N_CPU  | U3200.B12:U3400.K7 | 0.00 MIL:2.00 MIL  | 1848.127      | 1.2110000000000127  | Pass   |     |
| 13 |     | DSP1.A14:U4.N3 [DSP0_DDR3_EA0]                                                              | 0.00 MIL:20.00 MIL | 2329.05       | -13.140000000000327 | Pass   |     |     | A0             | U3200.E8:U3400.N3  | 0.00 MIL:10.00 MIL | 1855.307      | -5.969000000000051  | Pass   |     |
| 14 |     | DSP1.B14:U4.P7 [DSP0_DDR3_EA1]                                                              | 0.00 MIL:20.00 MIL | 2315.69       | 0.2199999999997999  | Pass   |     |     | A1             | U3200.G9:U3400.P7  | 0.00 MIL:10.00 MIL | 1855.023      | -5.684999999999945  | Pass   |     |
| 15 |     | DSP1.F14:U4.P3 [DSP0_DDR3_EA2]                                                              | 0.00 MIL:20.00 MIL | 2318.68       | -2.769999999999982  | Pass   |     |     | A2             | U3200.G8:U3400.P3  | 0.00 MIL:10.00 MIL | 1845.652      | 3.685999999999922   | Pass   |     |
| 16 |     | DSP1.F13:U4.N2 [DSP0_DDR3_EA3]                                                              | 0.00 MIL:20.00 MIL | 2321.2        | -5.289999999999964  | Pass   |     |     | A3             | U3200.G10:U3400.N2 | 0.00 MIL:10.00 MIL | 1847.942      | 1.3959999999999582  | Pass   |     |
| 17 |     | DSP1.A15:U4.P8 [DSP0_DDR3_EA4]                                                              | 0.00 MIL:20.00 MIL | 2312.56       | 3.349999999999909   | Pass   |     |     | A4             | U3200.F9:U3400.P8  | 0.00 MIL:10.00 MIL | 1854.657      | -5.31899999999996   | Pass   |     |
| 18 |     | DSP1.C15:U4.P2 [DSP0_DDR3_EA5]                                                              | 0.00 MIL:20.00 MIL | 2303.57       | 12.33999999999969   | Pass   |     |     | A5             | U3200.F8:U3400.P2  | 0.00 MIL:10.00 MIL | 1850.488      | -1.150000000000091  | Pass   |     |
| 19 |     | DSP1.B15:U4.R8 [DSP0_DDR3_EA6]                                                              | 0.00 MIL:20.00 MIL | 2332.99       | -17.079999999999927 | Pass   |     |     | A6             | U3200.C9:U3400.R8  | 0.00 MIL:10.00 MIL | 1853.146      | -3.8079999999999927 | Pass   |     |
| 20 |     | DSP1.D15:U4.R2 [DSP0_DDR3_EA7]                                                              | 0.00 MIL:20.00 MIL | 2333.28       | -17.370000000000346 | Pass   |     |     | A7             | U3200.D9:U3400.R2  | 0.00 MIL:10.00 MIL | 1845.957      | 3.380999999999858   | Pass   |     |
| 21 |     | DSP1.F15:U4.T8 [DSP0_DDR3_EA8]                                                              | 0.00 MIL:20.00 MIL | 2335.84       | -19.93000000000029  | Pass   |     |     | A8             | U3200.B9:U3400.T8  | 0.00 MIL:10.00 MIL | 1854.87       | -5.531999999999925  | Pass   |     |
| 22 |     | DSP1.E15:U4.R3 [DSP0_DDR3_EA9]                                                              | 0.00 MIL:20.00 MIL | 2312.01       | 3.899999999999636   | Pass   |     |     | A9             | U3200.D8:U3400.R3  | 0.00 MIL:10.00 MIL | 1845.623      | 3.714999999999918   | Pass   |     |



min_row: 2
max_row: 22
min_col: 1
max_col: 15
target_cell_row_idx: 12
target_cell_col_idx: 5
target_cell_value: 0.75
formula: =$D$11-D12