may please the court good morning this case requires the court to decide a fundamental dispute between the parties what is the invention we contend that the invention is a novel interface circuit and that interface circuit maps requests from one bus to a second bus and it also solves what was known in the art of the time as a cache coherency problem and it solved that problem by using a conventional snoop signal process at pelleas in contrast argue that the invention is a new snoop signal that provides an intelligence new process and that was not known in the our at the time what we're asking this court to do is to enter an order that does two things first to tell the  clarify what a snoop signal is and second what he snooped signal is not as to what is snoop signal is we're asking this court to make a ruling that  signal is what it always been in the art at the time of this invention a signal that directs a process supes snoops signal signal have to know data is in the ca it exactly your honor what we're asking this court to do is to enter an order that the snoop signal doesn't have to know the data is in cash but simply that the device r davis considerable revisions to conclude from the specification and from the language of the claim that it does need to know that the data is in the cache it your honor the portions that of the specification of the district court relied on we think actually teach something different the first thing that the quirk placed most reliance on is the abstract and we agree that the abstract does support the district court's construction but it was a mistake and as the district court said twice that neither the abstract nor anything else in the patent enables a smart snoop signal the other language that the district court relied on in the in the specification was language that says that a snoop signal reference is a caching data storage location but in that regard the district court only focused on two words cash data and essentially read that as a verb cached modifying location a noun or data and what the court didn't do was read the entire phrase which says that this new signal references a cached data storage location and i think the example we gave in our reply brief is dead on in that phrase references is the verb and cash data storage location is a noun it's a place so if i say that i have very treasure yes there is treasure buried in a location and that's the way the district court read cache data but if i say x references a buried structure storage location then that x still references the location whether data is there or not and that's why a snoop signal is asserted when ever the device issuing that signal receives a request for an address that is within the range of addresses that can be put into cache memory but it simply does not have the intelligence to know whether the data is actually there or not the third thing that the district court relied on was the claim language itself that that says that the stoop signal indicates a second data storage location requests from a second data storage of it i'm sorry a subset of the second data storage location so the question is that the district court really never answered is what is a subset of the second data storage location in our reply brief we explain why we believe that the subset refers to the entire subset of main memory that can be put into cache memory as opposed to just a sub subset of that main memory that already is in cash so those are the reasons that the district court gave in we believe that that all of them when examined closely and importantly from the standpoint of a person of ordinary skill in the art lead to two conclusions one is that this invention used a conventional snoop signal that only knows whether the data request is within a cashable range and secondly that as a result of issuing the soup signal the processor does what processors always do and that is look they snoop just as does not appear in the specification but again that's not the issue the only claims or in the claims what the what both the claims and the specification cock about is a signal that references a cash to data storage location and we've explained why i'm referencing a catch data storage location is a reference to a place and not a reference to specific data that is somehow known to be in cache and what the statement in when to write cached data to the address it doesn't sound like the location data that that language deals with what the snoop signal communicates to the processor and it's undisputed that conventional snoop signals at the time communicated it to the processor in a way that when the processor received the snoops signal that the processor would then look in the cache memory see if the data was there at the request of address and then only update if the data was dirty what the district court did was read that statement as basically right it effectively turned a snoop signal a signal it sesno into a signal th director writing whether the data is clean or dirty there is no system that worked that way at the time there's no system even today that works at the time it would have been completely illogical for the inventors to say write back no matter what whether the data is clean dirty as opposed to just write back the dirty data mr hadley in column two lines twenty six and three there's a reference to this new signal and the retry function that is triggered by this new signal and you have the snoops signal it triggers the retry which permits the cache to which signals the computer to move the cache memory into the memory but the only way that could happen is if the snoop signal knew in advance that the cache contained the data no you mustn't this police confirm with the district court said no your honor the way that snooping worked in it conventionally at the time and the way that the inventor is used the term scoop signal here is that when the snoop signal is received by a processor that has cache memory the first thing that the processor does is it looks in its catch to see if the data is there or not because it doesn't know from the soup signal if it finds that data is there then it asserts the retry signal and what the retry signal does is that it places a hold on the transaction it tells the processor that issued that s signal to wait because and that what that does is it allows the computer time to then go and look but with this passage says it's the snoop signal finds a cache a location then it triggers the retry signal but the only reason it would do that is if it knows the data isn't there right that seems to be indicated by judge white and seems pretty consistent with both the language of the claim and as you point out the the what this complete specification itself particularly in the abstract what this language says is that it responds to the soup signal with the retry it doesn't say that it always responds and our position is that a person skilled in the art reading this language who is familiar with the way snooping work would have understood that the retry is asserted if there is data at the location it's not asserted if there is not data at the location that the language in this summ doesn't say whether you always assert the retried or you don't always assert the retries has the sense that what the district court did was read this is saying the retry is always asserted but let me take you there anything that says otherwise i believe there is you honor and let me take you back to say so you saying and this appears this was a concern of my to say if i could just follow up this appears not just on column two but also i guess the same or similar language in column twelve you know the passage mediately proceeding the one you just read if it has the same language that the processor in the future of us controlling the cache responds to the snoop signal with a retry signal which is the response to and your suggestion i take it is that that means person skilled in the art would understand that what this means is that if the retry signal is asserted then there will be a response or if if it let me make a like that i understand which is saying that there may or there may not be a retry but here's what a person skilled in the art would really have done a person skilled the art would have read the entire specification and we focused on the summary language we've seen what's in the abstract and column twelve is sort of a and get a summing up but in the specification the paragraphs that really deal with how snooping occurs in this invention begin at column nine at about wind forty seven and what that says the first year it consists of two forty seven that talk about in the preferred embodiment house grouping works and this is the place where a person skilled in the art would have lived where they would have got to find out how snooping works actually in the preferred embodiment of the invention and there's no forty yes ok two to ensure cache coherency and the first thing it talks about is what happens in the invention when a computer on the second bus is making the request for data and that's the bus that has the main memory and other computers with the cache memory and there's complete agreement between the parties in the district court that what this per graph says is that it uses conventional snooping that it sends a signal if there is a request for an address that is anywhere within the range of addresses that can be played in placing cache memory there's nothing in here that suggests that the signal somehow knows or has the intelligence to know that the data is actually in cache memory and then it says that the processor may respond with a retry and it also then indicates that the appropriate data is written back namely the dirty data so if the processor maintaining cache finds dirty data in the process or it writes that back let me see if i understand the use of the word may here because i found this to be somewhat difficult to parse but the in the simple signal does not it may assert a snoop signal if the address is within the range of addresses that can be placed in cache memory if the requested address is outside if it's in the portion of the addresses that never go into the second paragraph bin deals with ok now what happened this would be something that the would be determined i take it by the interface circuits table of addresses this is this is what he determined this is what happened yes that's absolutely right  and and remember if it's on the table that goes the soup signal if it's not knows the signal is if the table keeps track it's not really a table it's a word keeps track of what addresses can be put in cash and what addresses cannot and now the second paragraph then talks about ok now what are we going to do when the request for an address is coming not from a computer on the second bus from but from a computer on the first bus and it tells you two things one is ok now instead of the computer issuing the soup signal that snoop signal is going to be issued by the interface circuit the second thing that it tells that thing i'm having trouble with here is the  the interface circuit issues this new signal in the invention it's when the computers issuing this new signal less the prior are right well it did not exist is talking about the prior arms and it it i talking about the invention and it's making clear that in fact if you look at figure one your honor this may be the easiest way to visualize this what it is saying is that like this you can can i get you just kind of a yes or no on that this is really addressing the prior art this is addressing the conventional snoo process that is used in the invention when it is a computer on the second bus that's not in there why are our had the computer issuing the new signal in your invention the interface doesn't write in our invention the interface issues the soup signal when the request for an address comes from computer to in figure one in our invention when computer four issues the request for an address then the snoop signal comes from computer four and the interesting thing here is that in both instances it's computer sets that receives the wrists new request if the courts construction is correct and if a pelleas are correct what that means is that computer six has to be programmed to respond to a snoop signal in two completely different ways it responds in the conventional way if the request comes from computer for on the one bus but now all of a sudden if the request is coming from computer two on the second bus and the soup signals issued through the interface now the sun computer six has to do something completely different when the request comes from the interface circuit now listen this computer somehow knows that the address is in cash and is going to right back where the data is complete is clean or dirty it's going to operate completely different than if it receives the requests from computer for so essentially the court and the pelleas read in two different soup signals into this invention even though there is no disclosure and certainly no enabling disclosure of true different and completely gets time right plus five oh i see you've got it figured out now who's pretty i'm a little slow today thank you i'd like to begin by going straight to generated by a computer on the bus but the claim snoop signal must be generated by the interface circuit itself and in fact the paragraph that column nine hundred forty seven i think we just went over that with mr hadley i think he's told us claimed what does define the invention that's claimed in the patent here is the very lengthy claim itself and there's plenty plenty of interesting enemy before you move on let me make sure i understand the significance of the word may even in the context of the one bus it's not even an embodiment the one bus operation is it correct to say that in that paragraph the may refers to what mr hadley described as referring to which is a determination that the snub signal will be issued if the address is a cashable address i believe the may in that paragraph means that the computer is permitted to issue a snoop signal but not a flier then you won't automatically not but seeking to read a made memory address in other words is there a circumstance in which computer four is seeking to read a main memory three address but does not assert when computer four is seeking to read from main memory address that mean memory main memory three it depends on whether the computers that determine that there is data cached in their in their cache memories and not just the in that situation the computer processor is making the determination of whether data is cached as opposed to in the invention when the interface circuit itself is making the determined determination  cached and that's that the difference and what force he claims to be the novelty of the interface circuit was that it took some of that intelligence about whether data is cached in cash memories that are associated with a different processors and moves that  information into the interface or that's the the snoop data that's held in the ram two fourteen of the interface circuit that's moved that information is moved into the interface circuit so that the claimed invention plan generate a snoop signal that indicates whether or not data is cached and foresee it concedes that the abstract of the porton abstract of the pattern supports the district court's construction and contends that perhaps the abstract is a mistake but there is no way that the public would be aware that the inventors view the abstract as a mistake think the pattern needs to be read as a whole and the claim to be interpreted in light of the entire specification as written including the abstract mr hadley is saying if you read the patent is a ho you would recognise yourself that it meant cash all cash well throughout the claims and the patent the baton refers to cached data storage locations and cache memory the starts in the abstract which describes this new signal as telling the second bus master to copy data from cache memory into the main memory and describes the snoop signal there as indicating which memory addresses contained data cached in the cache memory then the claim language also the case that the data must memory the preamble states that the snoop signal must tell one of the second  masters when to write cached data the only way the smoke signal can tell of the vice on the second bus when to write cached data is if that data is already contained in the cache memory to judge white even  name judge white did express some reservations about enablement but he didn't actually find that the patent was not enabled and i don't think this is a case where enablement needs to be reached the question before the court is claimed also he's raising it in the sense that you know in general you want to construe a claim so that it does something and he's saying this one might not did express some concern about that but the patent does in fact describe in unable the cleaned snoop signal where the snoop signal indicates whether data is caching the cache memory and the description of that comes in the figure showing the interface circuit figure five which illustrates the ram to fourteen and then figure seven which shows how the snoop data bit is stored in ram to fourteen in foresees reply brief they suggested that the snoop data bit in the tell within the ram would not be able to indicate whether data is cache for all addresses but the pattern actually explains that there's this new data bit for each address in memory and at the bottom of column made line sixty illustrates the data were stored at each location of ram to fourteen so there is a snoop data bit for each memory location which will indicate whether that particular memory memory location has dana cached at it that's the entire table keeping track of whether data is in cash or not it describes the replicating meaning tire cache it doesn't have to store the data itself that's maintain brain and the snoop it is just a single bit her address that indicates whether or not data is cache so it will be smaller than the cache memory itself doesn't need to contain all of the the data that is within the cache other portions the specification also are consistent with the claim language and the abstract for example at column two starting at line twenty one the summary of the invention expressly describes this new signal as indicating whether the future bus address reference is a cached data storage location again this means that the address on the bus refers to a location in cache memory where data is cached the second portion of that paragraph  that the summary of the invention also describes what happens if the snoop signal does in fact indicate the data is cash in cash memory it say it states if this new signal indicates the future bus address reference is a cached data storage location another computer processor on the future bus controlling the cache response to the snoop signal with the retry signal and what this means is that the processor searched the retry signal so that it can take control of the bus and write the data from ca snoop signal as indicating whether data is in fact cached in the cache memory there for those reasons that this report was correct to construe the snoop signal as requiring the signal to indicate whether data is cached in cash memory and not merely cashable under that correct construction of snoop signal there's no dispute that these sixty three of sixty four intel's accuse chipsets do not infringe the second limitation which is related to this new signal limitation is this new single telling and the non infringement ruling from the district court with respect to this limitation applies to all of intel's accused chipsets the district courts construction for th correctly construe this limitation is requiring this new signal to tell a processor when to write cache to data again this is the interpretation this supported throughout the patent in the abstract a column two and a column twelve at the foresee relied on a some link in their reply brief in particular and i think it could use some some clarification this paragraph describes the v f translation circuit made a sort of snoops signal when generating any particular future bus address and foresee says well what this tells us is that that the snoop signal cannot say that it is cash because it's doing this for any particular future of us address we have to keep in mind of course is that what the invention does is translate a set of addresses there are a set of the emmy bus addresses they translate into future bus addresses and the claimed interface can provide the translation for those addresses now the devices on the future bus control both the translation information and the snippet so what this tells us is that for a given address that is to be translated the translation circuit made a sort of soup signal that is if the data is cached or may not assert the snoop signal if the data is not ca so that's all really that that paragraph means it doesn't mean it's optional with respect to the interface or that the skip signal is optional with respect to the interface or certainly that the retry is optional with respect to the interface the other point i would like to has to do with enablement just very briefly in column ten here at lorne's nine through fourteen this describes how the devices that are on the future bus are able to adjust the translation information and the snoop data so as to dynamically keep track of the information so what ram to fourteen years is in fact exactly what force he says required a dynamic table that keeps track of address translation information and for each such address the required snippet and the single bit hold all that information there's a single bit per address your honor that's the significant phone at the bottom of column eight the the statement that figure seven illustrates the data word stored at each location of ram two fourteen will be multiple locations one for each address and similar language appears in column ten at line eleven each ramp to fourteen so the ram is not simply a single register would shown in figure seven is one entry for the ram a typical location holding the address bits the snoop that and other information in the basically it always has except that all the device has to do is write back and skip the cache coherence check so it makes the device a bit simpler and that's the reason for doing it to the bench because computer six has to receive snoop signals in the invention from both computer to and computer report so to find that the district court was right that computer has to understand that there are two different snoop signals in this invention a conventional one and a novel one and a novel snoop signal is just not described or disclosed anywhere in this invention there is no passages that teach how you would provide a snoop signal that knows the data is in cash and indiscriminately writes back both in and dirty data the appellee have come and suggested that it says ram to fourteen but there is no evidence in the record that shows  fourteen would be capable of doing anything other than telling the computer whether an address was subject to being in cash or not subject to being in cash so that it could issue the snoop signal or not issue the snoop signal there is no evidence whatsoever in the record that the snooping operates in any other way and if there is evidence in the record from our expert that in fact that ramp to fourteen is not capable of operating in the way of hell he suggests and want to coordinate that's what the district court found it found that under its construction a sense that there was no enabling disclosure it didn't rule on enabling because able and because the issue wasn't presented but twice the district court said i'm concerned about this construction because it doesn't seem to be enabled and not only that there is no disclosure of two separate snoop signals in this invention anywhere that's why we think a person skilled in the art would read snoop signal for what it is it tells to snoop and in fact at the since it was going to do w appellee say it does it wouldn't be a snoop signal at all it would be a signal that said just right because i know what's there and i don't care if it's clean or dirty so just right well you know there's a name for a signal like that in the prior art it's called a right signal why would you assert snoop signal when all you're going to do is say right for those reasons we think that the district court erred in construing soup signal there is only one stoops signal described in this patent subscribe consistently throughout and there is no enabling disclosure of either to snoop signals or more importantly some kind of smart intelligent snoop signal that knows that data is intact it's not there and in fact it wasn't invented for another ten years and it wasn't adopted by the defendants or at least intel intil after that it was invented by sun microsystems about ten years later and our expert described in detail in a report that the district court  credible that such a signal would require a complex set of tables to track the millions of bits going in and out of cash memory and main memory and that is something that just can't be done in a ram that's disclosed in this invention there's no other questions thank you mr headley are a final case