good morning everyone there is simply no plausible dispute that the prior art tachyon a reference discloses each of the elements of the twenty seven dollars for patent issues in this appeal to start with claim ten the claim requires that the differential amplifier has an output driven by an emitter or a source of a transistor the two hundred and seventy four patent shows one transistor generating the output and providing it to another transistor where it's driven through the emitter to a level the board thought it mattered the tachyon a label is that driving transistor as part of the level converter while the patent labels it as part of the differential amplifier but it doesn't matter neither northstar nor the board has offered a basis on which to impose that requirement on cl ication then you already have a living tissue which avoids touching but that's their argument your honor but there's no support for that in the specification and the board didn't identify any either all that the specification gives are examples that include an element driving an output to another element but there's absolutely nothing in the specification that suggests that that's limiting on the contrary the specification understanding the term driven by playing and as meaning something on the order of conveying like an emitter of the transistor somehow conveying the differential amplifier output but i would think there's another way of understanding driven by and that something like generated by where the emitter of the transistor as claimed of the differential amplifier providing that output it starts to make sense to me at least why you would think that driven by is using claim ten w be really under best understood as meaning generated by just as the matter is disclosed in the specification are generating the differential amplifiers output so in that sense can you explain what's wrong about that thinking for me certainly your honor the patent makes clear and on about it expert testimony is that the generation of the output is separate from the driving of the output and that there are different circuit elements that are performing each function i think to understand this it's very helpful to compare figure  which is at appendix two hundred and seven and figure fifteen of touching on a which is among other places at page ten of our opening brief and to do so by reference to dr baker's explanation of how these circuits work which again i cents those are the transistors that generate the differential output and that's that's the output of the differential amplifier what happens next is that that output goes to another transistor in the two and so whether you think about this is a matter of claim construction or a matter of anticipation there's no dispute here that these two circuits are operating the same way and the board just got it wrong and that's also true for claims to owner agreed with your expert that clock delayed circuit has a plane well defined meaning i would side the context of th i know you were emphasizing that hence heavily in your briefs what evidence do you have in the record to point to that clock delay circuit as that term is used in claim to as a plain ordinary meaning statement that your expert makes that in his opinion a circuit that is designed to delay a clock signal in some manner and i guess what i'm wondering is why is that so clear that that is is it's very simple straightforward and candidly broad plain language and that's what north stars expert agreed that this is as a very broad meaning that's it appendix nine well it wasn't for the moment that and i don't think it's then surprising that the expert would say yeah this is it's a circuit that delays the clock signal comes nd if we were to go down this road with you and try to imagine what clock delay circuit means in some ordinary sense outside the context of the patent why wouldn't it necessarily why wouldn't the best guess be you take an actual clock signal from a clock a clock signal but it's important to remember is that clock signal is being used in a particular way in the spot we have a construction of that term from the board that north star does not dispute this is the appendix forty one the board construe the only context i can find for the meaning of the late circuit in the seventy four is the description in figure two of the timing circuit which is the circuit having a clock depicted as a timing circuit if you take what the board found the board thought that this was not the embodiment showing a cause delays circuit they said that the figure two embodiment is rather the specific circuit that's claimed separately independent claim thirteen and i would i would point your honor to call them five of the specification in which with reference to figure two it repeatedly states this is one in body mind of the president vention and that the two clock signals are not required in the present invention the reverse order of what my colleague argued i will start with claim two and i will start st of all with the part of the board's construction that requires that the clock delay circuits receive a clock signal is therefore necessary to resort to the specification for a person of ordinary skill to have understood what that what that term clock delay circuit means to the extent that anything can be gleaned from the clean language itself though a clock delay circuit suggests that it is a circuit and i don't think that this is disputed by my colleague it is a circuit that the lays a clock meeting that a clock has to be input into it inverters and other intervening logic and then he came back in his reply declaration although he was now vacating a broader construction but even in his reply declaration he makes crystal clear in his opinion that a clock delay circuit is a circuit designed to to lay a clock signal the only way you can be designed to delay clock signals the clock signal is input to so  to that's the st part of the board's construction as to whether or not the clock delay circuit has to receive a clock as an input as to the portion of the construction that requires two different versions with one version  two different versions of the input signal with one version delayed compared to the other version the board's construction does not as micron would argue limit the clock delay circuit to the specific and vadim and describ the specifications to the contrary the board rejected nor stars proposed construction that page two clock delay circuit to not only provide two different versions of the input but abandon the specification altogether and the board did not abandon the specification altogether under philips you never abandon the specification and then looking to the entirety of the specification the board said understanding how the circuit works and understanding the purpose of the invention that although it doesn't have to be delayed precisely in the way shown in figure two the output of a clock delay circuit does have to be two different versions of the input that are in some way delayed compared to one another and contrary to microns argument the board did provide affirmative rationale in support of that construction equated to the specification allows the selective unable ment of the circuit components that allows a reduction in power consumption and allows increased speed and the board understood that these two different versions of the inputs that are delayed counselor just getting to that point my understanding of reading the pattern of closure was the purpose of this patented invention is to avoid the problems of using two separate clocks and using just the single clock clocks that right yes that's exactly right when we're talking about the timing relationship the advantage of being able to use bach is an input into the circuit that then outputs two versions of the clock that avoids the timing on how the board construed clock signal which is i think something to do with some kind of control signal that enables disables either a differential amplifier or a level converter and and in your disclosure of the clock signal seventy eight that's getting input into your disclosed timing circuit lines up with your disclosure no your honor because the output of the clock delay circuit in the two hundred and seventy four path are versions of two different versions of that same clock signal so seventy eight clock seventy goes in and what comes out are just two different versions of that same clock they are both inverted and one of them is delayed from the other but they are both versions of the clock seventy eight they are not to avoid these timing relationship problems and it is true that the clock three latch which also obviate the need for separate clocks to clock the latch help to avoid those timing relationship problems and that is as described as one of the advantages of the two hundred and seventy four dollars pass but it's not the only advantage is not the only purpose and it's not the only thing that avoids those timing relationship problems having two different versions of the input clock signal to selectively enable and disable the circuit elements that to add to the advantage of being able to avoid the time of relationship problems and all of the a vantages that the board pointed to in its decision are directly from the patent so that the specification doesn't deede explain that all of these advantages of avoiding timing relationship should problems increasing speed reducing power  consumption that was all spelled out in the specification and specifically tied into the clock the lay circuit limitation could you get to claim ten and the  and i don't know that those are those are just labels isn't it more important that we focus on how these components function and whether the plain language is smith well to some extent  ask a quick question relative to this point because what seems to be the problem is that we have claimed limitations which on their face seem to be stated quite broadly to you go through the specification and the details and the kind of discussion we're having here and he said no it really needs to be limited because and then we have the printing right we have this is closure was there any proposal during this procedure to amend the claims to limit the definition of these two limitations and claims to particularly the board look to all of the different various aspects of the age to seventy four specifications that revealed what the patentee men talked about driving by or driven by and revealed various  to we continue to believe in the board's construction was wrong arguments are in the briefs but if the court agrees with the board's construction then there's still no substantial evidentiary support for it finding of no anticipation by touchy donna i want to take the two parts of the board's construction st the input then the output the input has to be a clock signal and again i want to remind the court that the board's unchallenged construction of a clock signal in this pattern is a control signal finding that the patterns input signal is a clock signal and tachyon is aren't other than the labels given to those signals the fact that they get manipulated through different logic gates it happens in in both just the same and mr flynn has no basis for saying well it's th same signal in figure two of the two some for pattern and it's a different signal in touching bonna as to the output that the two clock signal outputs are delayed with respect to one another the board one another it then says without citation that this doesn't make them different versions of each other but again they don't have to be different versions of each other they have to be delayed with respect to one another under the board's construction  tomorrow outputting two signals that will be used as clock signals in which they are those two output signals are both different version of the same input signal if you're talking about the exact same signal no but that's that's not required by the board's construction and there's no basis for imposing that limitation this is at this point we are purely talking about an embodiment that the repeatedly says is not required in the present invention but even within the world that there's the the clock signal outputs of touchy bonus timing circuit are all combinations of the same group of input signals again whose only function is to be used to create these output clock signals and they are delayed with respect to one another