Position: UVM Verification Engineer
Company: DataJob
Experience required: 5y
English level: intermediate

Required skills:

- RTL verification;

- Linux; 

- UVM.

Preferred skill:

- Matlab Simulink

You should have extensive experience of architecting and implementing Verification test benches for complex IP & module level design.

Ideal candidates should have following skills:

• Previous experience of SystemVerilog and UVM Methodology for RTL verification (test case creation and/or testbench creation).

• Datapath verification of signal processing desings in Linux environment.

• Previous experience in Matlab simulink is not manadatory but is seen as big advantage.

Allocation is 100 % and work can be done remotely.