// File: /workspace/github_cpp_makefile_star2_O2/estwings57[P]CasHMC/sources/CommandQueue.cpp
// Function: CasHMC::CommandQueue::isIssuable(CasHMC::DRAMCommand*)
bool CommandQueue::isIssuable(DRAMCommand *issueCMD)
{
	switch(issueCMD->commandType) {
		case REFRESH:
			break;
		case ACTIVATE:
			if((BANKSTATE(issueCMD->bank)->currentBankState == IDLE || BANKSTATE(issueCMD->bank)->currentBankState == REFRESHING) 
			&& BANKSTATE(issueCMD->bank)->nextActivate <= currentClockCycle 
			&& tFAWCountdown.size() < 4) {
				return true;
			}
			else {
				return false;
			}
			break;
		case WRITE:
		case WRITE_P:
			if(BANKSTATE(issueCMD->bank)->currentBankState == ROW_ACTIVE 
			&& BANKSTATE(issueCMD->bank)->nextWrite <= currentClockCycle
			&& BANKSTATE(issueCMD->bank)->openRowAddress == issueCMD->row
			&& !(!issueCMD->atomic && rowAccessCounter[issueCMD->bank] >= MAX_ROW_ACCESSES)) {
				//Check the available buffer space of the vault controller with regard to read/write return data
				if(issueCMD->atomic) {
					return true;
				}
				else if(issueCMD->posted == false) {
					if(vaultContP->pendingDataSize+(issueCMD->dataSize/16)+1 <= (vaultContP->upBufferMax)-(vaultContP->upBuffers.size())) {
						return true;
					}
					else{
						return false;
					}
				}
				else {
					return true;
				}
			}
			else {
				return false;
			}
			break;
		case READ:
		case READ_P:
			if(BANKSTATE(issueCMD->bank)->currentBankState == ROW_ACTIVE
			&& BANKSTATE(issueCMD->bank)->nextRead <= currentClockCycle
			&& BANKSTATE(issueCMD->bank)->openRowAddress == issueCMD->row
			&& rowAccessCounter[issueCMD->bank] < MAX_ROW_ACCESSES) {
				//Check the available buffer space of the vault controller with regard to read/write return data
				if(vaultContP->pendingDataSize+(issueCMD->dataSize/16)+1 <= (vaultContP->upBufferMax)-(vaultContP->upBuffers.size())) {
					return true;
				}
				else{
					return false;
				}
			}
			else {
				return false;
			}
			break;
		case PRECHARGE:
			if(BANKSTATE(issueCMD->bank)->currentBankState == ROW_ACTIVE
			&& BANKSTATE(issueCMD->bank)->nextPrecharge <= currentClockCycle) {
				return true;
			}
			else {
				return false;
			}
			break;
		default:
			ERROR(header<<"  == Error - Trying to issue a unknown bus packet type : "<<*issueCMD<<"  (CurrentClock : "<<currentClockCycle<<")");
			exit(0);
	}
	return false;
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x10(%rsi), %eax
cmpq $0x8, %rax
ja 0x1090c
leaq 0x15204(%rip), %rcx     # 0x25948
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x1d8(%rbx), %rax
movq 0x210(%rax), %rdx
movl 0x18(%r14), %ecx
movq 0x1d8(%rdx), %rdx
movq (%rdx,%rcx,8), %rdx
cmpl $0x1, 0x4(%rdx)
jne 0x10902
movq 0x18(%rdx), %rsi
cmpq 0x8(%rbx), %rsi
ja 0x10902
movl 0x8(%rdx), %edx
cmpl 0x20(%r14), %edx
jne 0x10902
movq 0x268(%rbx), %rdx
movl (%rdx,%rcx,4), %ecx
leaq 0x20df4(%rip), %rdx     # 0x31594
cmpl (%rdx), %ecx
jae 0x10902
movl 0x234(%rax), %ecx
movl 0x24(%r14), %edx
shrl $0x4, %edx
addl %edx, %ecx
incl %ecx
movslq 0x1cc(%rax), %rdx
movq 0x1f0(%rax), %rsi
subq 0x1e8(%rax), %rsi
sarq $0x3, %rsi
subq %rsi, %rdx
cmpq %rcx, %rdx
setae %al
jmp 0x10904
movq 0x1d8(%rbx), %rcx
movq 0x210(%rcx), %rax
movl 0x18(%r14), %edx
movq 0x1d8(%rax), %rax
movq (%rax,%rdx,8), %rax
cmpl $0x1, 0x4(%rax)
jne 0x10902
movq 0x20(%rax), %rsi
cmpq 0x8(%rbx), %rsi
ja 0x10902
movl 0x8(%rax), %eax
cmpl 0x20(%r14), %eax
jne 0x10902
movb $0x1, %al
cmpb $0x0, 0x30(%r14)
jne 0x10904
movq 0x268(%rbx), %rsi
movl (%rsi,%rdx,4), %edx
leaq 0x20d54(%rip), %rsi     # 0x31594
cmpl (%rsi), %edx
jae 0x10902
cmpb $0x0, 0x28(%r14)
jne 0x10904
movl 0x234(%rcx), %eax
movl 0x24(%r14), %edx
shrl $0x4, %edx
addl %edx, %eax
incl %eax
movslq 0x1cc(%rcx), %rdx
movq 0x1f0(%rcx), %rsi
subq 0x1e8(%rcx), %rsi
sarq $0x3, %rsi
subq %rsi, %rdx
cmpq %rax, %rdx
jmp 0x107d8
movq 0x1d8(%rbx), %rax
movq 0x210(%rax), %rax
movl 0x18(%r14), %ecx
movq 0x1d8(%rax), %rax
movq (%rax,%rcx,8), %rax
movl 0x4(%rax), %ecx
cmpl $0x3, %ecx
je 0x108b1
testl %ecx, %ecx
jne 0x10902
movq 0x10(%rax), %rax
cmpq 0x8(%rbx), %rax
ja 0x10902
movq 0x258(%rbx), %rcx
subq 0x250(%rbx), %rcx
movb $0x1, %al
cmpq $0x10, %rcx
jae 0x10902
jmp 0x10904
movq 0x1d8(%rbx), %rax
movq 0x210(%rax), %rax
movl 0x18(%r14), %ecx
movq 0x1d8(%rax), %rax
movq (%rax,%rcx,8), %rax
cmpl $0x1, 0x4(%rax)
jne 0x10902
movq 0x28(%rax), %rcx
movb $0x1, %al
cmpq 0x8(%rbx), %rcx
jbe 0x10904
xorl %eax, %eax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
movq 0x206dd(%rip), %rdi     # 0x30ff0
leaq 0x13708(%rip), %rsi     # 0x24022
callq 0x4300
leaq 0x150ba(%rip), %rsi     # 0x259e0
movq %rax, %rdi
callq 0x4300
leaq 0x13f42(%rip), %rsi     # 0x24877
movq %rax, %rdi
callq 0x4300
movq %rax, %rdi
movl $0x203, %esi            # imm = 0x203
callq 0x44f0
leaq 0x136f0(%rip), %rsi     # 0x24041
movq %rax, %rdi
callq 0x4300
leaq 0x20(%rbx), %rsi
movq %rax, %rdi
callq 0x42b0
leaq 0x1508d(%rip), %rsi     # 0x259f9
movq %rax, %rdi
callq 0x4300
movq %rax, %rdi
movq %r14, %rsi
callq 0x15274
leaq 0x17375(%rip), %rsi     # 0x27cfb
movq %rax, %rdi
callq 0x4300
movq 0x8(%rbx), %rsi
movq %rax, %rdi
callq 0x40d0
leaq 0x16b30(%rip), %rsi     # 0x274d1
movq %rax, %rdi
callq 0x4300
movq %rax, %rdi
callq 0x4180
xorl %edi, %edi
callq 0x4370