// File: NishadSaraf[P]Championship-Simulator/src/cache.cc
// Function: CACHE::handle_prefetch()
void CACHE::handle_prefetch()
{
    // handle prefetch
    uint32_t prefetch_cpu = PQ.entry[PQ.head].cpu;
    if (prefetch_cpu == NUM_CPUS)
        return;

    for (uint32_t i=0; i<MAX_READ; i++) {

        // handle the oldest entry
        if ((PQ.entry[PQ.head].event_cycle <= current_core_cycle[prefetch_cpu]) && (PQ.occupancy > 0)) {
            int index = PQ.head;

            // access cache
            uint32_t set = get_set(PQ.entry[index].address);
            int way = check_hit(&PQ.entry[index]);
            
            if (way >= 0) { // prefetch hit

                // update replacement policy
                if (cache_type == IS_LLC) {
                    llc_update_replacement_state(prefetch_cpu, set, way, block[set][way].full_addr, PQ.entry[index].ip, 0, PQ.entry[index].type, 1);

                }
                else
                    update_replacement_state(prefetch_cpu, set, way, block[set][way].full_addr, PQ.entry[index].ip, 0, PQ.entry[index].type, 1);

                // COLLECT STATS
                sim_hit[prefetch_cpu][PQ.entry[index].type]++;
                sim_access[prefetch_cpu][PQ.entry[index].type]++;

                // check fill level
                if (PQ.entry[index].fill_level < fill_level) {

                    if (PQ.entry[index].instruction) 
                        upper_level_icache[prefetch_cpu]->return_data(&PQ.entry[index]);
                    else // data
                        upper_level_dcache[prefetch_cpu]->return_data(&PQ.entry[index]);
                }

                HIT[PQ.entry[index].type]++;
                ACCESS[PQ.entry[index].type]++;
                
                // remove this entry from PQ
                PQ.remove_queue(&PQ.entry[index]);
            }
            else { // prefetch miss

                DP ( if (warmup_complete[prefetch_cpu]) {
                cout << "[" << NAME << "] " << __func__ << " prefetch miss";
                cout << " instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
                cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << PQ.entry[index].fill_level;
                cout << " cycle: " << PQ.entry[index].event_cycle << endl; });

                // check mshr
                uint8_t miss_handled = 1;
                int mshr_index = check_mshr(&PQ.entry[index]);

                if ((mshr_index == -1) && (MSHR.occupancy < MSHR_SIZE)) { // this is a new miss

                    DP ( if (warmup_complete[PQ.entry[index].cpu]) {
                    cout << "[" << NAME << "_PQ] " <<  __func__ << " want to add instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
                    cout << " full_addr: " << PQ.entry[index].full_addr << dec;
                    cout << " occupancy: " << lower_level->get_occupancy(3) << " SIZE: " << lower_level->get_size(3) << endl; });

                    // first check if the lower level PQ is full or not
                    // this is possible since multiple prefetchers can exist at each level of caches
                    if (lower_level) {
                        if (cache_type == IS_LLC) {
                            if (lower_level->get_occupancy(1) == lower_level->get_size(1))
                                miss_handled = 0;
                            else {
                                // add it to MSHRs if this prefetch miss will be filled to this cache level
                                if (PQ.entry[index].fill_level <= fill_level)
                                    add_mshr(&PQ.entry[index]);
                                
                                lower_level->add_rq(&PQ.entry[index]); // add it to the DRAM RQ
                            }
                        }
                        else {
                            if (lower_level->get_occupancy(3) == lower_level->get_size(3))
                                miss_handled = 0;
                            else {
                                // add it to MSHRs if this prefetch miss will be filled to this cache level
                                if (PQ.entry[index].fill_level <= fill_level)
                                    add_mshr(&PQ.entry[index]);

                                lower_level->add_pq(&PQ.entry[index]); // add it to the DRAM RQ
                            }
                        }
                    }
                }
                else {
                    if ((mshr_index == -1) && (MSHR.occupancy == MSHR_SIZE)) { // not enough MSHR resource

                        // TODO: should we allow prefetching with lower fill level at this case?
                        
                        // cannot handle miss request until one of MSHRs is available
                        miss_handled = 0;
                        STALL[PQ.entry[index].type]++;
                    }
                    else if (mshr_index != -1) { // already in-flight miss

                        // no need to update request except fill_level
                        // update fill_level
                        if (PQ.entry[index].fill_level < MSHR.entry[mshr_index].fill_level)
                            MSHR.entry[mshr_index].fill_level = PQ.entry[index].fill_level;

                        MSHR_MERGED[PQ.entry[index].type]++;

                        DP ( if (warmup_complete[prefetch_cpu]) {
                        cout << "[" << NAME << "] " << __func__ << " mshr merged";
                        cout << " instr_id: " << PQ.entry[index].instr_id << " prior_id: " << MSHR.entry[mshr_index].instr_id; 
                        cout << " address: " << hex << PQ.entry[index].address;
                        cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << MSHR.entry[mshr_index].fill_level;
                        cout << " cycle: " << MSHR.entry[mshr_index].event_cycle << endl; });
                    }
                    else { // WE SHOULD NOT REACH HERE
                        cerr << "[" << NAME << "] MSHR errors" << endl;
                        assert(0);
                    }
                }

                if (miss_handled) {

                    DP ( if (warmup_complete[prefetch_cpu]) {
                    cout << "[" << NAME << "] " << __func__ << " prefetch miss handled";
                    cout << " instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
                    cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << PQ.entry[index].fill_level;
                    cout << " cycle: " << PQ.entry[index].event_cycle << endl; });

                    MISS[PQ.entry[index].type]++;
                    ACCESS[PQ.entry[index].type]++;

                    // remove this entry from PQ
                    PQ.remove_queue(&PQ.entry[index]);
                }
            }
        }
    }
}

// Assembly:
subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq 0x50(%rsp), %rcx
movq %rcx, 0x28(%rsp)
movq 0xad80(%rcx), %rax
movl 0xad14(%rcx), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movl 0x330(%rax), %eax
movl %eax, 0x4c(%rsp)
cmpl $0x1, 0x4c(%rsp)
jne 0x7750
jmp 0x7ee1
movl $0x0, 0x48(%rsp)
movq 0x28(%rsp), %rcx
movl 0x48(%rsp), %eax
cmpl 0x739c(%rcx), %eax
jae 0x7ee1
movq 0x28(%rsp), %rcx
movq 0xad80(%rcx), %rax
movl 0xad14(%rcx), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
movl 0x4c(%rsp), %ecx
movl %ecx, %edx
leaq 0x88723(%rip), %rcx     # 0x8fec0
cmpq (%rcx,%rdx,8), %rax
ja 0x7ecf
movq 0x28(%rsp), %rax
cmpl $0x0, 0xad1c(%rax)
jbe 0x7ecf
movq 0x28(%rsp), %rdi
movl 0xad14(%rdi), %eax
movl %eax, 0x44(%rsp)
movq 0xad80(%rdi), %rax
movslq 0x44(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rsi
callq 0x49b0
movq 0x28(%rsp), %rdi
movl %eax, 0x40(%rsp)
movq 0xad80(%rdi), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x6150
movl %eax, 0x3c(%rsp)
cmpl $0x0, 0x3c(%rsp)
jl 0x7aee
movq 0x28(%rsp), %rax
movzbl 0x73a4(%rax), %eax
cmpl $0x6, %eax
jne 0x78be
movq 0x28(%rsp), %rdi
movl 0x4c(%rsp), %esi
movl 0x40(%rsp), %edx
movl 0x3c(%rsp), %ecx
movq 0x7390(%rdi), %rax
movl 0x40(%rsp), %r8d
movq (%rax,%r8,8), %rax
movslq 0x3c(%rsp), %r8
imulq $0x50, %r8, %r8
addq %r8, %rax
movq 0x20(%rax), %r8
movq 0xad80(%rdi), %rax
movslq 0x44(%rsp), %r9
imulq $0x380, %r9, %r9        # imm = 0x380
addq %r9, %rax
movq 0x370(%rax), %r9
movq 0xad80(%rdi), %rax
movslq 0x44(%rsp), %r10
imulq $0x380, %r10, %r10      # imm = 0x380
addq %r10, %rax
movzbl 0x32f(%rax), %eax
xorl %r10d, %r10d
movq $0x0, (%rsp)
movl %eax, 0x8(%rsp)
movl $0x1, 0x10(%rsp)
callq 0x22750
jmp 0x7945
movq 0x28(%rsp), %rdi
movl 0x4c(%rsp), %esi
movl 0x40(%rsp), %edx
movl 0x3c(%rsp), %ecx
movq 0x7390(%rdi), %rax
movl 0x40(%rsp), %r8d
movq (%rax,%r8,8), %rax
movslq 0x3c(%rsp), %r8
imulq $0x50, %r8, %r8
addq %r8, %rax
movq 0x20(%rax), %r8
movq 0xad80(%rdi), %rax
movslq 0x44(%rsp), %r9
imulq $0x380, %r9, %r9        # imm = 0x380
addq %r9, %rax
movq 0x370(%rax), %r9
movq 0xad80(%rdi), %rax
movslq 0x44(%rsp), %r10
imulq $0x380, %r10, %r10      # imm = 0x380
addq %r10, %rax
movzbl 0x32f(%rax), %eax
xorl %r10d, %r10d
movq $0x0, (%rsp)
movl %eax, 0x8(%rsp)
movl $0x1, 0x10(%rsp)
callq 0x22510
movq 0x28(%rsp), %rcx
movq %rcx, %rax
addq $0x10308, %rax          # imm = 0x10308
movl 0x4c(%rsp), %edx
shlq $0x5, %rdx
addq %rdx, %rax
movq 0xad80(%rcx), %rdx
movslq 0x44(%rsp), %rsi
imulq $0x380, %rsi, %rsi      # imm = 0x380
addq %rsi, %rdx
movzbl 0x32f(%rdx), %edx
movq (%rax,%rdx,8), %rsi
addq $0x1, %rsi
movq %rsi, (%rax,%rdx,8)
movq %rcx, %rax
addq $0x102e8, %rax          # imm = 0x102E8
movl 0x4c(%rsp), %edx
shlq $0x5, %rdx
addq %rdx, %rax
movq 0xad80(%rcx), %rdx
movslq 0x44(%rsp), %rsi
imulq $0x380, %rsi, %rsi      # imm = 0x380
addq %rsi, %rdx
movzbl 0x32f(%rdx), %edx
movq (%rax,%rdx,8), %rsi
addq $0x1, %rsi
movq %rsi, (%rax,%rdx,8)
movq 0xad80(%rcx), %rax
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movl 0x8(%rax), %eax
cmpl 0x7398(%rcx), %eax
jge 0x7a5d
movq 0x28(%rsp), %rax
movq 0xad80(%rax), %rax
movslq 0x44(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
cmpb $0x0, (%rax)
je 0x7a31
movq 0x28(%rsp), %rax
movl 0x4c(%rsp), %ecx
movq 0x8(%rax,%rcx,8), %rdi
movq 0xad80(%rax), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
movq (%rdi), %rax
callq *0x18(%rax)
jmp 0x7a5b
movq 0x28(%rsp), %rax
movl 0x4c(%rsp), %ecx
movq 0x10(%rax,%rcx,8), %rdi
movq 0xad80(%rax), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
movq (%rdi), %rax
callq *0x18(%rax)
jmp 0x7a5d
movq 0x28(%rsp), %rax
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movzbl 0x32f(%rcx), %ecx
movq 0x72c8(%rax,%rcx,8), %rdx
addq $0x1, %rdx
movq %rdx, 0x72c8(%rax,%rcx,8)
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movzbl 0x32f(%rcx), %ecx
movq 0x72a8(%rax,%rcx,8), %rdx
addq $0x1, %rdx
movq %rdx, 0x72a8(%rax,%rcx,8)
movq %rax, %rdi
addq $0xace8, %rdi           # imm = 0xACE8
movq 0xad80(%rax), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x150e0
jmp 0x7ecd
movq 0x28(%rsp), %rdi
movb $0x1, 0x3b(%rsp)
movq 0xad80(%rdi), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x6370
movl %eax, 0x34(%rsp)
cmpl $-0x1, 0x34(%rsp)
jne 0x7cbf
movq 0x28(%rsp), %rcx
movl 0xc9bc(%rcx), %eax
cmpl 0x7388(%rcx), %eax
jae 0x7cbf
movq 0x28(%rsp), %rax
cmpq $0x0, 0x18(%rax)
je 0x7cba
movq 0x28(%rsp), %rax
movzbl 0x73a4(%rax), %eax
cmpl $0x6, %eax
jne 0x7c0c
movq 0x28(%rsp), %rax
movq 0x18(%rax), %rdi
movq (%rdi), %rax
movl $0x1, %esi
callq *0x30(%rax)
movl %eax, %ecx
movq 0x28(%rsp), %rax
movl %ecx, 0x24(%rsp)
movq 0x18(%rax), %rdi
movq (%rdi), %rax
movl $0x1, %esi
callq *0x38(%rax)
movl %eax, %ecx
movl 0x24(%rsp), %eax
cmpl %ecx, %eax
jne 0x7b9d
movb $0x0, 0x3b(%rsp)
jmp 0x7c07
movq 0x28(%rsp), %rcx
movq 0xad80(%rcx), %rax
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movl 0x8(%rax), %eax
cmpl 0x7398(%rcx), %eax
jg 0x7be3
movq 0x28(%rsp), %rdi
movq 0xad80(%rdi), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x6400
movq 0x28(%rsp), %rax
movq 0x18(%rax), %rdi
movq 0xad80(%rax), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
movq (%rdi), %rax
callq *(%rax)
jmp 0x7cb8
movq 0x28(%rsp), %rax
movq 0x18(%rax), %rdi
movq (%rdi), %rax
movl $0x3, %esi
callq *0x30(%rax)
movl %eax, %ecx
movq 0x28(%rsp), %rax
movl %ecx, 0x20(%rsp)
movq 0x18(%rax), %rdi
movq (%rdi), %rax
movl $0x3, %esi
callq *0x38(%rax)
movl %eax, %ecx
movl 0x20(%rsp), %eax
cmpl %ecx, %eax
jne 0x7c4b
movb $0x0, 0x3b(%rsp)
jmp 0x7cb6
movq 0x28(%rsp), %rcx
movq 0xad80(%rcx), %rax
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movl 0x8(%rax), %eax
cmpl 0x7398(%rcx), %eax
jg 0x7c91
movq 0x28(%rsp), %rdi
movq 0xad80(%rdi), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x6400
movq 0x28(%rsp), %rax
movq 0x18(%rax), %rdi
movq 0xad80(%rax), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
movq (%rdi), %rax
callq *0x10(%rax)
jmp 0x7cb8
jmp 0x7cba
jmp 0x7e34
cmpl $-0x1, 0x34(%rsp)
jne 0x7d19
movq 0x28(%rsp), %rcx
movl 0xc9bc(%rcx), %eax
cmpl 0x7388(%rcx), %eax
jne 0x7d19
movq 0x28(%rsp), %rax
movb $0x0, 0x3b(%rsp)
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movzbl 0x32f(%rcx), %ecx
movq 0x7328(%rax,%rcx,8), %rdx
addq $0x1, %rdx
movq %rdx, 0x7328(%rax,%rcx,8)
jmp 0x7e32
cmpl $-0x1, 0x34(%rsp)
je 0x7dcc
movq 0x28(%rsp), %rcx
movq 0xad80(%rcx), %rax
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movl 0x8(%rax), %eax
movq 0xca20(%rcx), %rcx
movslq 0x34(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
cmpl 0x8(%rcx), %eax
jge 0x7d94
movq 0x28(%rsp), %rax
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movl 0x8(%rcx), %ecx
movq 0xca20(%rax), %rax
movslq 0x34(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movl %ecx, 0x8(%rax)
movq 0x28(%rsp), %rax
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movzbl 0x32f(%rcx), %ecx
movq 0x7308(%rax,%rcx,8), %rdx
addq $0x1, %rdx
movq %rdx, 0x7308(%rax,%rcx,8)
jmp 0x7e30
movq 0x2121d(%rip), %rdi     # 0x28ff0
leaq 0x1b253(%rip), %rsi     # 0x2302d
callq 0x3220
movq 0x28(%rsp), %rsi
movq %rax, %rdi
addq $0x7350, %rsi           # imm = 0x7350
callq 0x31c0
movq %rax, %rdi
leaq 0x1b232(%rip), %rsi     # 0x2302f
callq 0x3220
movq %rax, %rdi
movq 0x211ac(%rip), %rsi     # 0x28fb8
callq 0x3250
leaq 0x1b1ec(%rip), %rdi     # 0x23004
leaq 0x1b1e7(%rip), %rsi     # 0x23006
movl $0x302, %edx            # imm = 0x302
leaq 0x1b278(%rip), %rcx     # 0x230a3
callq 0x3160
jmp 0x7e32
jmp 0x7e34
cmpb $0x0, 0x3b(%rsp)
je 0x7ecb
movq 0x28(%rsp), %rax
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movzbl 0x32f(%rcx), %ecx
movq 0x72e8(%rax,%rcx,8), %rdx
addq $0x1, %rdx
movq %rdx, 0x72e8(%rax,%rcx,8)
movq 0xad80(%rax), %rcx
movslq 0x44(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movzbl 0x32f(%rcx), %ecx
movq 0x72a8(%rax,%rcx,8), %rdx
addq $0x1, %rdx
movq %rdx, 0x72a8(%rax,%rcx,8)
movq %rax, %rdi
addq $0xace8, %rdi           # imm = 0xACE8
movq 0xad80(%rax), %rsi
movslq 0x44(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x150e0
jmp 0x7ecd
jmp 0x7ecf
jmp 0x7ed1
movl 0x48(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x48(%rsp)
jmp 0x7758
addq $0x58, %rsp
retq
nopw %cs:(%rax,%rax)