// File: /workspace/github_cpp_makefile_star2_O1/CMU-SAFARI[P]MQSim/src/ssd/NVM_PHY_ONFI_NVDDR2.cpp
// Function: SSD_Components::NVM_PHY_ONFI_NVDDR2::Execute_simulator_event(MQSimEngine::Sim_Event*)
void NVM_PHY_ONFI_NVDDR2::Execute_simulator_event(MQSimEngine::Sim_Event* ev)
	{
		DieBookKeepingEntry* dieBKE = (DieBookKeepingEntry*)ev->Parameters;
		flash_channel_ID_type channel_id = dieBKE->ActiveTransactions.front()->Address.ChannelID;
		ONFI_Channel_NVDDR2* targetChannel = channels[channel_id];
		NVM::FlashMemory::Flash_Chip* targetChip = targetChannel->Chips[dieBKE->ActiveTransactions.front()->Address.ChipID];
		ChipBookKeepingEntry *chipBKE = &bookKeepingTable[channel_id][targetChip->ChipID];

		switch ((NVDDR2_SimEventType)ev->Type) {
			case NVDDR2_SimEventType::READ_CMD_ADDR_TRANSFERRED:
				//DEBUG2("Chip " << targetChip->ChannelID << ", " << targetChip->ChipID << ", " << dieBKE->ActiveTransactions.front()->Address.DieID << ": READ_CMD_ADDR_TRANSFERRED ")
				targetChip->EndCMDXfer(dieBKE->ActiveCommand);
				for (auto tr : dieBKE->ActiveTransactions) {
					tr->STAT_execution_time = dieBKE->Expected_finish_time - Simulator->Time();
				}
				chipBKE->OngoingDieCMDTransfers.pop();
				chipBKE->No_of_active_dies++;
				if (chipBKE->OngoingDieCMDTransfers.size() > 0) {
					perform_interleaved_cmd_data_transfer(targetChip, chipBKE->OngoingDieCMDTransfers.front());
					return;
				} else {
					chipBKE->Status = ChipStatus::READING;
					targetChannel->SetStatus(BusChannelStatus::IDLE, targetChip);
				}
				break;
			case NVDDR2_SimEventType::ERASE_SETUP_COMPLETED:
				//DEBUG2("Chip " << targetChip->ChannelID << ", " << targetChip->ChipID << ", " << dieBKE->ActiveTransactions.front()->Address.DieID << ": ERASE_SETUP_COMPLETED ")
				targetChip->EndCMDXfer(dieBKE->ActiveCommand);
				for (auto &tr : dieBKE->ActiveTransactions) {
					tr->STAT_execution_time = dieBKE->Expected_finish_time - Simulator->Time();
				}
				chipBKE->OngoingDieCMDTransfers.pop();
				chipBKE->No_of_active_dies++;
				if (chipBKE->OngoingDieCMDTransfers.size() > 0) {
					perform_interleaved_cmd_data_transfer(targetChip, chipBKE->OngoingDieCMDTransfers.front());
					return;
				} else {
					chipBKE->Status = ChipStatus::ERASING;
					targetChannel->SetStatus(BusChannelStatus::IDLE, targetChip);
				}
				break;
			case NVDDR2_SimEventType::PROGRAM_CMD_ADDR_DATA_TRANSFERRED:
			case NVDDR2_SimEventType::PROGRAM_COPYBACK_CMD_ADDR_TRANSFERRED:
				//DEBUG2("Chip " << targetChip->ChannelID << ", " << targetChip->ChipID << ", " << dieBKE->ActiveTransactions.front()->Address.DieID <<  ": PROGRAM_CMD_ADDR_DATA_TRANSFERRED " )
				targetChip->EndCMDDataInXfer(dieBKE->ActiveCommand);
				for (auto &tr : dieBKE->ActiveTransactions) {
					tr->STAT_execution_time = dieBKE->Expected_finish_time - Simulator->Time();
				}
				chipBKE->OngoingDieCMDTransfers.pop();
				chipBKE->No_of_active_dies++;
				if (chipBKE->OngoingDieCMDTransfers.size() > 0)
				{
					perform_interleaved_cmd_data_transfer(targetChip, chipBKE->OngoingDieCMDTransfers.front());
					return;
				} else {
					chipBKE->Status = ChipStatus::WRITING;
					targetChannel->SetStatus(BusChannelStatus::IDLE, targetChip);
				}
				break;
			case NVDDR2_SimEventType::READ_DATA_TRANSFERRED:
				//DEBUG2("Chip " << targetChip->ChannelID << ", " << targetChip->ChipID << ", " << dieBKE->ActiveTransactions.front()->Address.DieID << ": READ_DATA_TRANSFERRED ")
				targetChip->EndDataOutXfer(dieBKE->ActiveCommand);
				copy_read_data_to_transaction((NVM_Transaction_Flash_RD*)dieBKE->ActiveTransfer, dieBKE->ActiveCommand);
	#if 0
				if (tr->ExecutionMode != ExecutionModeType::COPYBACK)
	#endif
				broadcastTransactionServicedSignal(dieBKE->ActiveTransfer);

				for (std::list<NVM_Transaction_Flash*>::iterator it = dieBKE->ActiveTransactions.begin();
					it != dieBKE->ActiveTransactions.end(); it++) {
					if ((*it) == dieBKE->ActiveTransfer) {
						dieBKE->ActiveTransactions.erase(it);
						break;
					}
				}
				dieBKE->ActiveTransfer = NULL;
				if (dieBKE->ActiveTransactions.size() == 0) {
					dieBKE->ClearCommand();
				}

				chipBKE->WaitingReadTXCount--;
				if (chipBKE->No_of_active_dies == 0) {
					if (chipBKE->WaitingReadTXCount == 0) {
						chipBKE->Status = ChipStatus::IDLE;
					} else {
						chipBKE->Status = ChipStatus::WAIT_FOR_DATA_OUT;
					}
				}
				if (chipBKE->Status == ChipStatus::IDLE) {
					if (dieBKE->Suspended) {
						send_resume_command_to_chip(targetChip, chipBKE);
					}
				}
				targetChannel->SetStatus(BusChannelStatus::IDLE, targetChip);
				break;
			default:
				PRINT_ERROR("Unknown simulation event specified for NVM_PHY_ONFI_NVDDR2!")
		}

		/* Copyback requests are prioritized over other type of requests since they need very short transfer time.
		In addition, they are just used for GC purpose. */
		if (WaitingCopybackWrites[channel_id].size() > 0) {
			DieBookKeepingEntry* waitingBKE = WaitingCopybackWrites[channel_id].front();
			targetChip = channels[channel_id]->Chips[waitingBKE->ActiveTransactions.front()->Address.ChipID];
			ChipBookKeepingEntry* waitingChipBKE = &bookKeepingTable[channel_id][targetChip->ChipID];
			if (waitingBKE->ActiveTransactions.size() > 1) {
				Stats::IssuedMultiplaneCopybackProgramCMD++;
				waitingBKE->ActiveCommand->CommandCode = CMD_PROGRAM_PAGE_COPYBACK_MULTIPLANE;
			} else {
				Stats::IssuedCopybackProgramCMD++;
				waitingBKE->ActiveCommand->CommandCode = CMD_PROGRAM_PAGE_COPYBACK;
			}
			targetChip->StartCMDXfer();
			waitingChipBKE->Status = ChipStatus::CMD_IN;
			Simulator->Register_sim_event(Simulator->Time() + this->channels[channel_id]->ProgramCommandTime[waitingBKE->ActiveTransactions.size()],
				this, waitingBKE, (int)NVDDR2_SimEventType::PROGRAM_COPYBACK_CMD_ADDR_TRANSFERRED);
			waitingChipBKE->OngoingDieCMDTransfers.push(waitingBKE);

			waitingBKE->Expected_finish_time = Simulator->Time() + this->channels[channel_id]->ProgramCommandTime[waitingBKE->ActiveTransactions.size()]
				+ targetChip->Get_command_execution_latency(waitingBKE->ActiveCommand->CommandCode, waitingBKE->ActiveCommand->Address[0].PageID);
			if (waitingChipBKE->Expected_command_exec_finish_time < waitingBKE->Expected_finish_time) {
				waitingChipBKE->Expected_command_exec_finish_time = waitingBKE->Expected_finish_time;
			}

			WaitingCopybackWrites[channel_id].pop_front();
			channels[channel_id]->SetStatus(BusChannelStatus::BUSY, targetChip);

			return;
		} else if (WaitingMappingRead_TX[channel_id].size() > 0) {
			NVM_Transaction_Flash_RD* waitingTR = (NVM_Transaction_Flash_RD*)WaitingMappingRead_TX[channel_id].front();
			WaitingMappingRead_TX[channel_id].pop_front();
			transfer_read_data_from_chip(&bookKeepingTable[channel_id][waitingTR->Address.ChipID],
				&(bookKeepingTable[channel_id][waitingTR->Address.ChipID].Die_book_keeping_records[waitingTR->Address.DieID]), waitingTR);

			return;
		} else if (WaitingReadTX[channel_id].size() > 0) {
			NVM_Transaction_Flash_RD* waitingTR = (NVM_Transaction_Flash_RD*)WaitingReadTX[channel_id].front();
			WaitingReadTX[channel_id].pop_front();
			transfer_read_data_from_chip(&bookKeepingTable[channel_id][waitingTR->Address.ChipID],
				&(bookKeepingTable[channel_id][waitingTR->Address.ChipID].Die_book_keeping_records[waitingTR->Address.DieID]), waitingTR);

			return;
		} else if (WaitingGCRead_TX[channel_id].size() > 0) {
			NVM_Transaction_Flash_RD* waitingTR = (NVM_Transaction_Flash_RD*)WaitingGCRead_TX[channel_id].front();
			WaitingGCRead_TX[channel_id].pop_front();
			transfer_read_data_from_chip(&bookKeepingTable[channel_id][waitingTR->Address.ChipID],
				&(bookKeepingTable[channel_id][waitingTR->Address.ChipID].Die_book_keeping_records[waitingTR->Address.DieID]), waitingTR);
			return;
		}

		//If the execution reaches here, then the bus channel became idle
		broadcastChannelIdleSignal(channel_id);
	}

	inline void NVM_PHY_ONFI_NVDDR2::handle_ready_signal_from_chip(NVM::FlashMemory::Flash_Chip* chip, NVM::FlashMemory::Flash_Command* command)
	{
		ChipBookKeepingEntry *chipBKE = &_my_instance->bookKeepingTable[chip->ChannelID][chip->ChipID];
		DieBookKeepingEntry *dieBKE = &(chipBKE->Die_book_keeping_records[command->Address[0].DieID]);

		switch (command->CommandCode)
		{
		case CMD_READ_PAGE:
		case CMD_READ_PAGE_MULTIPLANE:
			DEBUG("Chip " << chip->ChannelID << ", " << chip->ChipID << ": finished  read command")
			chipBKE->No_of_active_dies--;
			if (chipBKE->No_of_active_dies == 0)//After finishing the last command, the chip state is changed
				chipBKE->Status = ChipStatus::WAIT_FOR_DATA_OUT;

			for (std::list<NVM_Transaction_Flash*>::iterator it = dieBKE->ActiveTransactions.begin();
				it != dieBKE->ActiveTransactions.end(); it++)
			{
				chipBKE->WaitingReadTXCount++;
				if (_my_instance->channels[chip->ChannelID]->GetStatus() == BusChannelStatus::IDLE)
					_my_instance->transfer_read_data_from_chip(chipBKE, dieBKE, (*it));
				else
				{
					switch (dieBKE->ActiveTransactions.front()->Source)
					{
					case Transaction_Source_Type::CACHE:
					case Transaction_Source_Type::USERIO:
						_my_instance->WaitingReadTX[chip->ChannelID].push_back((*it));
						break;
					case Transaction_Source_Type::GC_WL:
						_my_instance->WaitingGCRead_TX[chip->ChannelID].push_back((*it));
						break;
					case Transaction_Source_Type::MAPPING:
						_my_instance->WaitingMappingRead_TX[chip->ChannelID].push_back((*it));
						break;
					}
				}
			}
			break;
		case CMD_READ_PAGE_COPYBACK:
		case CMD_READ_PAGE_COPYBACK_MULTIPLANE:
			chipBKE->No_of_active_dies--;
			if (chipBKE->No_of_active_dies == 0)
				chipBKE->Status = ChipStatus::WAIT_FOR_COPYBACK_CMD;
			if (_my_instance->channels[chip->ChannelID]->GetStatus() == BusChannelStatus::IDLE)
			{
				if (dieBKE->ActiveTransactions.size() > 1)
				{
					Stats::IssuedMultiplaneCopybackProgramCMD++;
					dieBKE->ActiveCommand->CommandCode = CMD_PROGRAM_PAGE_COPYBACK_MULTIPLANE;
				}
				else
				{
					Stats::IssuedCopybackProgramCMD++;
					dieBKE->ActiveCommand->CommandCode = CMD_PROGRAM_PAGE_COPYBACK;
				}

				for (std::list<NVM_Transaction_Flash*>::iterator it = dieBKE->ActiveTransactions.begin();
					it != dieBKE->ActiveTransactions.end(); it++)
				{
					(*it)->STAT_transfer_time += _my_instance->channels[chip->ChannelID]->ProgramCommandTime[dieBKE->ActiveTransactions.size()];
				}
				chip->StartCMDXfer();
				chipBKE->Status = ChipStatus::CMD_IN;
				Simulator->Register_sim_event(Simulator->Time() + _my_instance->channels[chip->ChannelID]->ProgramCommandTime[dieBKE->ActiveTransactions.size()],
					_my_instance, dieBKE, (int)NVDDR2_SimEventType::PROGRAM_COPYBACK_CMD_ADDR_TRANSFERRED);
				chipBKE->OngoingDieCMDTransfers.push(dieBKE);
				_my_instance->channels[chip->ChannelID]->SetStatus(BusChannelStatus::BUSY, chip);

				dieBKE->Expected_finish_time = Simulator->Time() + _my_instance->channels[chip->ChannelID]->ProgramCommandTime[dieBKE->ActiveTransactions.size()]
					+ chip->Get_command_execution_latency(dieBKE->ActiveCommand->CommandCode, dieBKE->ActiveCommand->Address[0].PageID);
				if (chipBKE->Expected_command_exec_finish_time < dieBKE->Expected_finish_time)
					chipBKE->Expected_command_exec_finish_time = dieBKE->Expected_finish_time;
#if 0	
				//Copyback data should be read out in order to get rid of bit error propagation
				Simulator->RegisterEvent(Simulator->Time() + channels[targetChip->ChannelID]->ProgramCommandTime + NVDDR2DataOutTransferTime(targetTransaction->SizeInByte, channels[targetChip->ChannelID]),
					this, targetTransaction, (int)NVDDR2_SimEventType::READ_DATA_TRANSFERRED);
				targetTransaction->STAT_TransferTime += NVDDR2DataOutTransferTime(targetTransaction->SizeInByte, channels[targetChip->ChannelID]);
#endif
			}
			else _my_instance->WaitingCopybackWrites->push_back(dieBKE);
			break;
		case CMD_PROGRAM_PAGE:
		case CMD_PROGRAM_PAGE_MULTIPLANE:
		case CMD_PROGRAM_PAGE_COPYBACK:
		case CMD_PROGRAM_PAGE_COPYBACK_MULTIPLANE:
		{
			DEBUG("Chip " << chip->ChannelID << ", " << chip->ChipID << ": finished program command")
			int i = 0;
			for (std::list<NVM_Transaction_Flash*>::iterator it = dieBKE->ActiveTransactions.begin();
				it != dieBKE->ActiveTransactions.end(); it++, i++)
			{
				((NVM_Transaction_Flash_WR*)(*it))->Content = command->Meta_data[i].LPA;
				_my_instance->broadcastTransactionServicedSignal(*it);
			}
			dieBKE->ActiveTransactions.clear();
			dieBKE->ClearCommand();

			chipBKE->No_of_active_dies--;
			if (chipBKE->No_of_active_dies == 0 && chipBKE->WaitingReadTXCount == 0)
				chipBKE->Status = ChipStatus::IDLE;
			//Since the time required to send the resume command is very small, we ignore it
			if (chipBKE->Status == ChipStatus::IDLE)
				if (chipBKE->HasSuspend)
					_my_instance->send_resume_command_to_chip(chip, chipBKE);
			break;
		}
		case CMD_ERASE_BLOCK:
		case CMD_ERASE_BLOCK_MULTIPLANE:
			DEBUG("Chip " << chip->ChannelID << ", " << chip->ChipID << ": finished erase command")
			for (std::list<NVM_Transaction_Flash*>::iterator it = dieBKE->ActiveTransactions.begin();
				it != dieBKE->ActiveTransactions.end(); it++)
				_my_instance->broadcastTransactionServicedSignal(*it);
			dieBKE->ActiveTransactions.clear();
			dieBKE->ClearCommand();

			chipBKE->No_of_active_dies--;
			if (chipBKE->No_of_active_dies == 0 && chipBKE->WaitingReadTXCount == 0)
				chipBKE->Status = ChipStatus::IDLE;
			//Since the time required to send the resume command is very small, we ignore it
			if (chipBKE->Status == ChipStatus::IDLE)
				if (chipBKE->HasSuspend)
					_my_instance->send_resume_command_to_chip(chip, chipBKE);
			break;
		default:
			break;
		}

		if (_my_instance->channels[chip->ChannelID]->GetStatus() == BusChannelStatus::IDLE)
			_my_instance->broadcastChannelIdleSignal(chip->ChannelID);
		else if (chipBKE->Status == ChipStatus::IDLE)
			_my_instance->broadcastChipIdleSignal(chip);
	}

	inline void NVM_PHY_ONFI_NVDDR2::transfer_read_data_from_chip(ChipBookKeepingEntry* chipBKE, DieBookKeepingEntry* dieBKE, NVM_Transaction_Flash* tr)
	{
		//DEBUG2("Chip " << tr->Address.ChannelID << ", " << tr->Address.ChipID << ": transfer read data started for LPA: " << tr->LPA)
		dieBKE->ActiveTransfer = tr;
		channels[tr->Address.ChannelID]->Chips[tr->Address.ChipID]->StartDataOutXfer();
		chipBKE->Status = ChipStatus::DATA_OUT;
		Simulator->Register_sim_event(Simulator->Time() + NVDDR2DataOutTransferTime(tr->Data_and_metadata_size_in_byte, channels[tr->Address.ChannelID]),
			this, dieBKE, (int)NVDDR2_SimEventType::READ_DATA_TRANSFERRED);

		tr->STAT_transfer_time += NVDDR2DataOutTransferTime(tr->Data_and_metadata_size_in_byte, channels[tr->Address.ChannelID]);
		channels[tr->Address.ChannelID]->SetStatus(BusChannelStatus::BUSY, channels[tr->Address.ChannelID]->Chips[tr->Address.ChipID]);
	}

	void NVM_PHY_ONFI_NVDDR2::perform_interleaved_cmd_data_transfer(NVM::FlashMemory::Flash_Chip* chip, DieBookKeepingEntry* bookKeepingEntry)
	{
		ONFI_Channel_NVDDR2* target_channel = channels[bookKeepingEntry->ActiveTransactions.front()->Address.ChannelID];
		/*if (target_channel->Status == BusChannelStatus::BUSY)
			PRINT_ERROR("Requesting communication on a busy bus!")*/

		switch (bookKeepingEntry->ActiveTransactions.front()->Type)
		{
			case Transaction_Type::READ:
				chip->StartCMDXfer();
				bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_IN;
				Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime,
					this, bookKeepingEntry, (int)NVDDR2_SimEventType::READ_CMD_ADDR_TRANSFERRED);
				break;
			case Transaction_Type::WRITE:
				if (((NVM_Transaction_Flash_WR*)bookKeepingEntry->ActiveTransactions.front())->RelatedRead == NULL) {
					chip->StartCMDDataInXfer();
					bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_DATA_IN;
					Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime,
						this, bookKeepingEntry, (int)NVDDR2_SimEventType::PROGRAM_CMD_ADDR_DATA_TRANSFERRED);
				} else {
					chip->StartCMDXfer();
					bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_IN;
					Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime, this,
						bookKeepingEntry, (int)NVDDR2_SimEventType::READ_CMD_ADDR_TRANSFERRED);
				}
				break;
			case Transaction_Type::ERASE:
				chip->StartCMDXfer();
				bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_IN;
				Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime,
					this, bookKeepingEntry, (int)NVDDR2_SimEventType::ERASE_SETUP_COMPLETED);
				break;
			default:
				PRINT_ERROR("NVMController_NVDDR2: Uknown flash transaction type!")
		}
		target_channel->SetStatus(BusChannelStatus::BUSY, chip);
	}

	inline void NVM_PHY_ONFI_NVDDR2::send_resume_command_to_chip(NVM::FlashMemory::Flash_Chip* chip, ChipBookKeepingEntry* chipBKE)
	{
		//DEBUG2("Chip " << chip->ChannelID << ", " << chip->ChipID << ": resume command " )
		for (unsigned int i = 0; i < die_no_per_chip; i++) {
			DieBookKeepingEntry *dieBKE = &chipBKE->Die_book_keeping_records[i];
			//Since the time required to send the resume command is very small, MQSim ignores it to simplify the simulation
			dieBKE->PrepareResume();
			chipBKE->PrepareResume();
			chip->Resume(dieBKE->ActiveCommand->Address[0].DieID);
			switch (dieBKE->ActiveCommand->CommandCode) {
				case CMD_READ_PAGE:
				case CMD_READ_PAGE_MULTIPLANE:
				case CMD_READ_PAGE_COPYBACK:
				case CMD_READ_PAGE_COPYBACK_MULTIPLANE:
					chipBKE->Status = ChipStatus::READING;
					break;
				case CMD_PROGRAM_PAGE:
				case CMD_PROGRAM_PAGE_MULTIPLANE:
				case CMD_PROGRAM_PAGE_COPYBACK:
				case CMD_PROGRAM_PAGE_COPYBACK_MULTIPLANE:
					chipBKE->Status = ChipStatus::WRITING;
					break;
				case CMD_ERASE_BLOCK:
				case CMD_ERASE_BLOCK_MULTIPLANE:
					chipBKE->Status = ChipStatus::ERASING;
					break;
			}

		}
	}
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movl 0x18(%rsi), %eax
cmpq $0x4, %rax
ja 0x473e7
movq %rdi, %r15
movq 0x10(%rsi), %r13
movq 0x8(%r13), %rcx
movq 0x10(%rcx), %rcx
movl 0x38(%rcx), %ebx
movl 0x3c(%rcx), %ecx
movq 0x88(%rdi), %rdx
movq 0x90(%rdi), %rsi
movq (%rdx,%rbx,8), %rbp
movq 0x8(%rbp), %rdx
movq (%rdx,%rcx,8), %rdi
movl 0x30(%rdi), %r12d
shlq $0x7, %r12
addq (%rsi,%rbx,8), %r12
leaq 0x8(%r13), %r14
leaq 0x13701(%rip), %rcx     # 0x5a3b0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
movq %rbx, 0x18(%rsp)
movq %rdi, (%rsp)
movq %rbp, 0x10(%rsp)
jmpq *%rax
movq (%r13), %rsi
callq 0x47f4e
movq 0x8(%r13), %rbp
cmpq %r14, %rbp
je 0x46cfa
movq 0x50(%r13), %rbx
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
subq %rax, %rbx
movq 0x10(%rbp), %rax
movq %rbx, 0x28(%rax)
movq (%rbp), %rbp
jmp 0x46cd3
leaq 0x28(%r12), %rdi
callq 0x488ee
incl 0x7c(%r12)
movq 0x70(%r12), %rax
movq %rax, %rcx
subq 0x50(%r12), %rcx
shrq $0x3, %rcx
cmpq $0x1, %rax
adcq $-0x1, %rcx
shlq $0x6, %rcx
movq 0x58(%r12), %rdx
subq 0x60(%r12), %rdx
sarq $0x3, %rdx
addq %rcx, %rdx
movq 0x38(%r12), %rcx
movq 0x48(%r12), %rsi
subq %rcx, %rsi
sarq $0x3, %rsi
movl $0x5, %eax
jmp 0x46dd9
movq (%r13), %rsi
callq 0x47ec0
movq 0x8(%r13), %rbp
cmpq %r14, %rbp
je 0x46d86
movq 0x50(%r13), %rbx
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
subq %rax, %rbx
movq 0x10(%rbp), %rax
movq %rbx, 0x28(%rax)
movq (%rbp), %rbp
jmp 0x46d5f
leaq 0x28(%r12), %rdi
callq 0x488ee
incl 0x7c(%r12)
movq 0x70(%r12), %rax
movq %rax, %rcx
subq 0x50(%r12), %rcx
shrq $0x3, %rcx
cmpq $0x1, %rax
adcq $-0x1, %rcx
shlq $0x6, %rcx
movq 0x58(%r12), %rdx
subq 0x60(%r12), %rdx
sarq $0x3, %rdx
addq %rcx, %rdx
movq 0x38(%r12), %rcx
movq 0x48(%r12), %rsi
subq %rcx, %rsi
sarq $0x3, %rsi
movl $0x6, %eax
addq %rdx, %rsi
jne 0x47297
movl %eax, (%r12)
jmp 0x46f70
movq (%r13), %rsi
callq 0x47fdc
movq (%r13), %rax
movq 0x40(%r13), %rsi
movq 0x8(%rax), %rcx
movq 0x10(%rax), %rdx
cmpq %rdx, %rcx
je 0x46e33
movl 0x44(%rsi), %edi
xorl %r8d, %r8d
cmpl %edi, 0xc(%rcx)
jne 0x46e26
movq 0x20(%rax), %r9
movq (%r9,%r8), %r9
cmpq $-0x1, %r9
je 0x46e26
movq %r9, 0x58(%rsi)
addq $0x18, %rcx
addq $0x8, %r8
cmpq %rdx, %rcx
jne 0x46e0f
movq %r15, %rdi
callq 0x457f2
movq %r14, %rbp
movq (%rbp), %rbp
cmpq %r14, %rbp
je 0x46e65
movq 0x10(%rbp), %rax
cmpq 0x40(%r13), %rax
jne 0x46e3e
decq 0x18(%r13)
movq %rbp, %rdi
callq 0x7580
movq %rbp, %rdi
callq 0x7370
movq $0x0, 0x40(%r13)
cmpq $0x0, 0x18(%r13)
jne 0x46e7c
movq %r13, %rdi
callq 0x4805e
movl 0x78(%r12), %eax
decl %eax
movl %eax, 0x78(%r12)
cmpl $0x0, 0x7c(%r12)
jne 0x46e9e
testl %eax, %eax
movl $0x7, %ecx
cmovel %eax, %ecx
movl %ecx, (%r12)
cmpl $0x0, (%r12)
jne 0x46f70
cmpb $0x1, 0x49(%r13)
jne 0x46f70
cmpl $0x0, 0x34(%r15)
je 0x46f70
xorl %r14d, %r14d
movabsq $0x25000000000000, %r13 # imm = 0x25000000000000
xorl %ebp, %ebp
movq 0x8(%r12), %rbx
leaq (%rbx,%r14), %rdi
callq 0x48544
movb $0x0, 0x20(%r12)
movq (%rbx,%r14), %rax
movq 0x8(%rax), %rax
movl 0x8(%rax), %esi
movq (%rsp), %rdi
callq 0x2717a
movq (%rbx,%r14), %rax
movq (%rax), %rax
cmpq $0x800f, %rax           # imm = 0x800F
jg 0x46f24
movl $0x4, %ecx
cmpq $0x35, %rax
jbe 0x46f48
leaq -0x60d0(%rax), %rdx
cmpq $0x2, %rdx
jae 0x46f50
movl $0x6, %ecx
jmp 0x46f58
leaq -0x8010(%rax), %rcx
cmpq $0x2, %rcx
jb 0x46f41
cmpq $0x85111, %rax          # imm = 0x85111
je 0x46f41
cmpq $0x8510, %rax           # imm = 0x8510
jne 0x46f5c
movl $0x5, %ecx
jmp 0x46f58
btq %rax, %r13
jb 0x46f58
jmp 0x46f10
cmpq $0x321, %rax            # imm = 0x321
jne 0x46f5c
movl %ecx, (%r12)
incq %rbp
movl 0x34(%r15), %eax
addq $0x68, %r14
cmpq %rax, %rbp
jb 0x46ece
movq 0x10(%rsp), %rdi
movl $0x1, %esi
movq (%rsp), %rdx
callq 0x47e24
movq 0xb0(%r15), %rax
movq 0x18(%rsp), %r13
leaq (,%r13,2), %r14
addq %r13, %r14
cmpq $0x0, 0x10(%rax,%r14,8)
je 0x470b9
leaq (%rax,%r14,8), %rax
movq (%rax), %rax
movq 0x10(%rax), %rax
movq %rax, 0x8(%rsp)
movq 0x88(%r15), %rcx
movq 0x90(%r15), %rdx
movq (%rcx,%r13,8), %rcx
movq 0x8(%rcx), %rcx
movq 0x8(%rax), %rsi
movq 0x10(%rsi), %rsi
movl 0x3c(%rsi), %esi
movq %r15, %rbx
movq (%rcx,%rsi,8), %r12
movq %r13, %r15
movl 0x30(%r12), %ebp
shlq $0x7, %rbp
cmpq $0x2, 0x18(%rax)
leaq 0x286fa(%rip), %rcx     # 0x6f6f0
cmovaeq 0x27fa2(%rip), %rcx     # 0x6efa0
movl $0x85111, %esi          # imm = 0x85111
movl $0x8510, %edi           # imm = 0x8510
cmovaeq %rsi, %rdi
movq (%rdx,%r13,8), %r13
incq (%rcx)
movq %r13, %rcx
addq %rbp, %rcx
movq %rcx, 0x10(%rsp)
movq (%rax), %rax
movq %rdi, (%rax)
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
movq %r12, (%rsp)
movq %rax, 0x98(%r12)
movl $0x1, (%r13,%rbp)
callq 0x281b4
movq %rax, %r12
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
movq 0x88(%rbx), %rcx
movq (%rcx,%r15,8), %rdx
movq 0x8(%rsp), %rcx
movq 0x18(%rcx), %rsi
addq 0x78(%rdx,%rsi,8), %rax
movq %r12, %rdi
movq %rax, %rsi
movq %rbx, %r15
movq %rbx, %rdx
movl $0x3, %r8d
callq 0x285aa
movq 0x58(%r13,%rbp), %rax
movq 0x68(%r13,%rbp), %rcx
addq $-0x8, %rcx
cmpq %rcx, %rax
je 0x472b4
movq 0x8(%rsp), %rcx
movq %rcx, (%rax)
movq 0x10(%rsp), %rbp
addq $0x8, 0x58(%rbp)
jmp 0x472c7
movq 0xa8(%r15), %rdi
movq %r13, %rax
shlq $0x8, %rax
leaq (%rax,%r13,8), %rax
cmpq $0x0, 0x18(%rdi,%rax)
jne 0x470e6
movq 0x98(%r15), %rdi
cmpq $0x0, 0x18(%rdi,%rax)
je 0x47368
leaq (%rdi,%rax), %rcx
addq $0x8, %rcx
movq (%rcx), %rcx
movq 0x10(%rcx), %r12
addq %rax, %rdi
callq 0x3ea8c
movq 0x90(%r15), %rax
movq (%rax,%r13,8), %rbx
movl 0x3c(%r12), %eax
movl 0x40(%r12), %ecx
movq %r15, %rbp
movq %rax, %r15
shlq $0x7, %r15
movq 0x8(%rbx,%r15), %rdx
imulq $0x68, %rcx, %rcx
leaq (%rdx,%rcx), %r14
movq %r12, 0x40(%rdx,%rcx)
movq 0x88(%rbp), %rcx
movl 0x38(%r12), %edx
movq (%rcx,%rdx,8), %rcx
movq 0x8(%rcx), %rcx
movq (%rcx,%rax,8), %r13
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
movq %rax, 0x98(%r13)
movl $0x3, (%rbx,%r15)
callq 0x281b4
movq %rax, %r15
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
movq %rax, %rsi
movl 0x38(%r12), %ecx
movl 0x50(%r12), %eax
movq 0x88(%rbp), %rdx
movq (%rdx,%rcx,8), %rcx
xorl %edx, %edx
divl 0xd8(%rcx)
shrl %eax
imulq 0x20(%rcx), %rax
addq %rax, %rsi
movq %r15, %rdi
movq %rbp, %rdx
movq %r14, %rcx
xorl %r8d, %r8d
callq 0x285aa
movl 0x50(%r12), %eax
movq 0x88(%rbp), %rcx
movl 0x38(%r12), %edx
movl 0x3c(%r12), %esi
movq (%rcx,%rdx,8), %rdi
xorl %edx, %edx
divl 0xd8(%rdi)
shrl %eax
imulq 0x20(%rdi), %rax
addq %rax, 0x30(%r12)
movq 0x8(%rdi), %rax
movq (%rax,%rsi,8), %rdx
xorl %esi, %esi
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x47e24
movq %r15, 0x20(%rsp)
movq (%r13), %rsi
callq 0x47ec0
movq 0x8(%r13), %rbp
cmpq %r14, %rbp
je 0x47236
movq 0x10(%rbp), %r15
movq 0x50(%r13), %rbx
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
subq %rax, %rbx
movq %rbx, 0x28(%r15)
movq (%rbp), %rbp
jmp 0x4720f
leaq 0x28(%r12), %rdi
callq 0x488ee
incl 0x7c(%r12)
movq 0x70(%r12), %rax
movq %rax, %rcx
subq 0x50(%r12), %rcx
shrq $0x3, %rcx
cmpq $0x1, %rax
adcq $-0x1, %rcx
shlq $0x6, %rcx
movq 0x58(%r12), %rdx
subq 0x60(%r12), %rdx
sarq $0x3, %rdx
addq %rcx, %rdx
movq 0x38(%r12), %rcx
movq 0x48(%r12), %rsi
subq %rcx, %rsi
sarq $0x3, %rsi
movl $0x4, %eax
addq %rdx, %rsi
movq 0x20(%rsp), %r15
je 0x46de2
movq (%rcx), %rdx
movq %r15, %rdi
movq (%rsp), %rsi
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x4742a
movq 0x10(%rsp), %rbp
leaq 0x28(%rbp), %rdi
leaq 0x8(%rsp), %rsi
callq 0x486f6
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
movq %rax, %r12
movq 0x88(%r15), %rax
movq 0x18(%rsp), %rbx
movq (%rax,%rbx,8), %rax
movq 0x8(%rsp), %rcx
movq 0x18(%rcx), %rdx
addq 0x78(%rax,%rdx,8), %r12
movq (%rcx), %rax
movq (%rax), %rsi
movq 0x8(%rax), %rax
movl 0x14(%rax), %edx
movq (%rsp), %r13
movq %r13, %rdi
callq 0x27e7c
addq %r12, %rax
movq 0x8(%rsp), %rcx
movq %rax, 0x50(%rcx)
cmpq %rax, 0x10(%rbp)
jae 0x47324
movq %rax, 0x10(%rbp)
movq 0xb0(%r15), %rax
movq (%rax,%r14,8), %r12
decq 0x10(%rax,%r14,8)
movq %r12, %rdi
callq 0x7580
movq %r12, %rdi
callq 0x7370
movq 0x88(%r15), %rax
movq (%rax,%rbx,8), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq 0x47e24
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0xa0(%r15), %rdi
cmpq $0x0, 0x18(%rdi,%rax)
je 0x473ce
leaq (%rdi,%rax), %rcx
addq $0x8, %rcx
movq (%rcx), %rcx
movq %r15, %rbx
movq 0x10(%rcx), %r15
addq %rax, %rdi
callq 0x3ea8c
movq 0x90(%rbx), %rax
movq (%rax,%r13,8), %rax
movl 0x3c(%r15), %ecx
movl 0x40(%r15), %edx
shlq $0x7, %rcx
leaq (%rax,%rcx), %rsi
imulq $0x68, %rdx, %rdx
addq 0x8(%rax,%rcx), %rdx
movq %rbx, %rdi
movq %r15, %rcx
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x480d0
movq %r15, %rdi
movl %r13d, %esi
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x4585a
movq 0x27c02(%rip), %rbx     # 0x6eff0
leaq 0xf1b3(%rip), %rsi      # 0x565a8
movq %rbx, %rdi
callq 0x7390
leaq 0x13071(%rip), %rsi     # 0x5a475
movq %rbx, %rdi
callq 0x7390
movq %rax, %rdi
callq 0x71c0
movq 0x27bb5(%rip), %rdi     # 0x6efd0
callq 0x7430
movl $0x1, %edi
callq 0x7440