// File: /workspace/github_cpp_makefile_star2_O3/akshayrajput[P]ARMV8_Simulator/./SUBS.cpp
// Function: SUBS()
void SUBS()
{
    int sf = IR.getLowerData() & 0x80000000;
    int op = IR.getLowerData() & 0x40000000;
    int S =  IR.getLowerData() & 0x20000000;
    int mod = (IR.getLowerData() & 0x1f000000) >> 24;
    int shift = (IR.getLowerData() & 0x00c00000) >> 22;
    int imm12 = (IR.getLowerData() & 0x003ffc00) >>10;
    int imm6 = (IR.getLowerData() & 0x0000fc00) >>10;
    int rm = (IR.getLowerData() & 0x001f0000) >> 16;
    int rn = (IR.getLowerData() & 0x000003e0) >> 5;
    int rd = (IR.getLowerData() & 0x0000001f);
    bool sub_op = false;
    uint64_t imm;
    int amount =1;

    if(rd == 31)
    {
	    CMP();
	    return;
    }	
    if(op)  sub_op = true;

    printf("[log] - SUBS instruction\n");

    if(shift == 0)
    {
        if (sf)
        {
             imm = (uint64_t)imm12;
        }
        else
        {
             imm = imm12;
        }
    }
    
    else if(shift == 1)
    {
        if(sf)
        {
            imm = (uint64_t)imm12;
            imm = imm << 12;
        }
        else
        {
            imm = imm12;
            imm = imm << 12;
        }
    }
    bool setFlag = false;
    if(S == 1) setFlag = true;
    if(mod == 17) // SUBS immediate
    {
	printf("[log]- SUBS immediate\n");
        if(sf)  //64 bit
        {
            int carry = 0;
            if(sub_op)
            {
                imm = ~imm;
                carry = 1;   
            }
            uint64_t rn_data = R[rn].getData();
            uint64_t dat = rn_data + imm + carry;
            
            
                if(rn_data > 0 && imm < 0 && dat < 0)
                    OFLAG = true;
                
                if(rn_data < 0 && imm > 0 && dat > 0)
                    OFLAG = true;
                
                ZFLAG = (dat == 0);
                NFLAG = (dat < 0);
                
                CFLAG = rn_data > (0xffffffffffffffff - (imm + carry));
                
            if(rd == 31 && !S)
                R[31].setData(dat);
            else
                R[rd].setData(dat);
        }
        
        else//32 bit
        {
            int carry = 0;
            if(sub_op)
            {
                imm = ~imm;
                carry = 1;   
            }
            
            int rn_data = R[rn].getLowerData();
            int dat = rn_data + imm + carry;
            
            
            if(rn_data > 0 && imm < 0 && dat < 0)
                OFLAG = true;
            
            if(rn_data < 0 && imm > 0 && dat > 0)
                OFLAG = true;
             
            
            if(dat == 0)
                ZFLAG = true;
            
            if(dat < 0)
                NFLAG = true;
            
            CFLAG = rn_data > (0xffffffff - (imm + carry));
            
            if(rd == 31 && !S)
                R[31].setLowerData(dat);
            else
                R[rd].setLowerData(dat);
        }
    }
    
    if(mod == 11)   //shifted register
    {
	printf("[log]- SUBS register\n");
        if(sf)      //64 bit registers
        {
            uint64_t op1 = R[rn].getData();
            
            uint64_t op2 = R[rm].getData();
            if(shift == 0)
                op2 = op2 << amount;
            else if(shift == 1 && shift == 2)
                op2 = op2 >> amount;
            uint64_t carry = 0;
            if(sub_op)
            {
                op2 = ~op2;
                carry = 1;
            }
            
            uint64_t dat = op1 + op2 + carry;
            if(rd == 31 && !S)
                R[31].setData(dat);
            else
                R[rd].setData(dat);
           
            if(op1 > 0 && op2 < 0 && dat < 0)
	    {
                OFLAG = true;
		printf("[log] -Carry flag set \n");

            }
            if(op1 < 0 && op2 > 0 && dat > 0)
	    {
                OFLAG = true;
		printf("[log] -Overflow flag set \n");

            }

            if(dat == 0)
	    {
                ZFLAG = true;
		printf("[log] -Zero flag set \n");
	    }
            
            if(dat < 0)
	    {
                NFLAG = true;
		printf("[log] -Negative flag set \n");
	    }
                
            CFLAG = op1 > (0xffffffffffffffff - (op2 + carry));
	    if(CFLAG)
		    printf("[log] -Carry flag set \n");

        }
       
        else     //32 bit registers
        {
            int op1 = R[rn].getLowerData();
            
            int op2 = R[rm].getLowerData();
            if(shift == 0)
                op2 = op2 << amount;
            else if(shift == 1 && shift == 2)
                op2 = op2 >> amount;
            int carry = 0;
            if(sub_op)
            {
                op2 = ~op2;
                carry = 1;
            }
            
            int dat = op1 + op2 + carry;
            if(rd == 31 && !S)
                R[31].setLowerData(dat);
            else
                R[rd].setLowerData(dat);
           
            if(op1 > 0 && op2 < 0 && dat < 0)
	    {
                OFLAG = true;
		printf("[log] -Carry flag set \n");

            }
            if(op1 < 0 && op2 > 0 && dat > 0 )
	    {
                OFLAG = true;
		printf("[log] - Overflow flag set \n");

            }
            ZFLAG = (dat == 0);
	    if(ZFLAG)
		    printf("[log] - Zero flag set\n");
            NFLAG = (dat < 0); 
	    if(NFLAG)
                printf("[log] - Negative flag set\n");
 
            CFLAG = op1 > (0xffffffff - (op2 + carry));
            if(CFLAG)
		    printf("[log] - Carry flag set \n");
        }
       
    }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
leaq 0x17973(%rip), %rbx     # 0x1a1f0
movq %rbx, %rdi
callq 0x5cb2
movl %eax, 0x4(%rsp)
movq %rbx, %rdi
callq 0x5cb2
movl %eax, (%rsp)
movq %rbx, %rdi
callq 0x5cb2
movq %rbx, %rdi
callq 0x5cb2
movl %eax, %r15d
movq %rbx, %rdi
callq 0x5cb2
movl %eax, %r13d
movq %rbx, %rdi
callq 0x5cb2
movl %eax, %r14d
movq %rbx, %rdi
callq 0x5cb2
movq %rbx, %rdi
callq 0x5cb2
movl %eax, %ebp
movq %rbx, %rdi
callq 0x5cb2
movl %eax, %r12d
movq %rbx, %rdi
callq 0x5cb2
movl %eax, %ebx
andl $0x1f, %ebx
cmpl $0x1f, %ebx
jne 0x28ff
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1f79
shrl $0x18, %r15d
andl $0x1f, %r15d
shrl $0x16, %r13d
andl $0x3, %r13d
shrl $0xa, %r14d
andl $0xfff, %r14d           # imm = 0xFFF
shrl $0x5, %r12d
leaq 0x3dcd(%rip), %rdi      # 0x66f2
callq 0x1140
testl %r13d, %r13d
je 0x293e
cmpl $0x1, %r13d
movl (%rsp), %eax
jne 0x2944
shll $0xc, %r14d
jmp 0x2944
movl %r14d, %r14d
movl (%rsp), %eax
andl $0x1f, %r12d
andl $0x40000000, %eax       # imm = 0x40000000
cmpl $0xb, %r15d
je 0x29cd
cmpl $0x11, %r15d
jne 0x2c2b
leaq 0x3da7(%rip), %rdi      # 0x670b
movl %eax, %ebp
callq 0x1140
movl %ebp, %edx
movl %ebp, %r15d
shrl $0x1e, %r15d
btl $0x1f, 0x4(%rsp)
jb 0x2aa6
xorl %ebp, %ebp
negl %edx
sbbq %rbp, %rbp
movq %r14, %r13
xorq %rbp, %r13
movl %r12d, %eax
leaq 0x7759(%rip), %r12      # 0xa0f0
leaq (%r12,%rax,8), %rdi
callq 0x5cb2
cltq
leal (%r15,%r13), %esi
addl %eax, %esi
testl %eax, %eax
jns 0x2b77
cmpq %rbp, %r14
je 0x2b77
testl %esi, %esi
jle 0x2b77
leaq 0x771a(%rip), %rcx      # 0xa0e2
jmp 0x2b8d
shrl $0x10, %ebp
andl $0x1f, %ebp
leaq 0x3d47(%rip), %rdi      # 0x6721
movl %eax, %r14d
callq 0x1140
movl %r14d, (%rsp)
shrl $0x1e, %r14d
btl $0x1f, 0x4(%rsp)
movl %r12d, %eax
leaq 0x76f6(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
movl %ebp, %eax
leaq (%rcx,%rax,8), %r15
jb 0x2afd
testl %r13d, %r13d
sete %bpl
callq 0x5cb2
movl %eax, %r12d
movq %r15, %rdi
callq 0x5cb2
movl %ebp, %ecx
shll %cl, %eax
xorl %r15d, %r15d
negl (%rsp)
sbbl %r15d, %r15d
xorl %eax, %r15d
addl %r15d, %r14d
leal (%r14,%r12), %ebp
movl %ebx, %eax
leaq 0x76af(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
movl %ebp, %esi
callq 0x5cbc
testl %r12d, %r12d
jle 0x2bb9
movl %ebp, %eax
andl %r15d, %eax
jns 0x2bb9
movb $0x1, 0x767b(%rip)      # 0xa0e2
leaq 0x3d41(%rip), %rdi      # 0x67af
callq 0x1140
testl %ebp, %ebp
sete 0x7665(%rip)            # 0xa0e1
je 0x2bef
movl %ebp, %eax
shrl $0x1f, %eax
movb %al, 0x7656(%rip)       # 0xa0e3
testl %ebp, %ebp
jns 0x2c05
leaq 0x3ccb(%rip), %rdi      # 0x6767
callq 0x1140
jmp 0x2c05
movl %r15d, %eax
xorl %ecx, %ecx
negl %edx
sbbq %rcx, %rcx
xorq %rcx, %r14
addq %rax, %r14
movl %r12d, %eax
leaq 0x7630(%rip), %r15      # 0xa0f0
leaq (%r15,%rax,8), %rdi
callq 0x5cae
addq %rax, %r14
sete 0x760e(%rip)            # 0xa0e1
movb $0x0, 0x7609(%rip)      # 0xa0e3
setb 0x7603(%rip)            # 0xa0e4
movl %ebx, %eax
leaq (%r15,%rax,8), %rdi
movq %r14, %rsi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x5cb6
testl %r13d, %r13d
sete %bpl
callq 0x5cae
movq %rax, %r12
movq %r15, %rdi
callq 0x5cae
movl %ebp, %ecx
shlq %cl, %rax
xorl %ecx, %ecx
negl (%rsp)
sbbq %rcx, %rcx
xorq %rax, %rcx
movl %r14d, %r14d
addq %rcx, %r14
movl %ebx, %eax
leaq 0x75bd(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
leaq (%r14,%r12), %rsi
callq 0x5cb6
movq %r14, %rax
addq %r12, %rax
jne 0x2b5b
movb $0x1, 0x7592(%rip)      # 0xa0e1
leaq 0x3c43(%rip), %rdi      # 0x6799
callq 0x1140
addq %r12, %r14
setb 0x757f(%rip)            # 0xa0e4
jae 0x2c2b
leaq 0x3c3d(%rip), %rdi      # 0x67af
jmp 0x2c18
leaq 0x7563(%rip), %rdx      # 0xa0e1
leaq 0x755e(%rip), %rcx      # 0xa0e3
testl %esi, %esi
cmoveq %rdx, %rcx
jg 0x2b90
movb $0x1, (%rcx)
notl %r15d
subq %r13, %r15
cmpq %rax, %r15
setb 0x7544(%rip)            # 0xa0e4
movl %ebx, %eax
leaq (%r12,%rax,8), %rdi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x5cbc
testl %r12d, %r12d
jns 0x2a73
testl %r15d, %r15d
jle 0x2a73
testl %ebp, %ebp
jle 0x2a73
movb $0x1, 0x7508(%rip)      # 0xa0e2
leaq 0x3b55(%rip), %rdi      # 0x6736
callq 0x1140
movb $0x0, 0x74f4(%rip)      # 0xa0e1
jmp 0x2bfb
leaq 0x3b5b(%rip), %rdi      # 0x6751
callq 0x1140
shrl $0x1f, %ebp
movb %bpl, 0x74de(%rip)      # 0xa0e3
addl %r12d, %r14d
setb 0x74d5(%rip)            # 0xa0e4
jae 0x2c2b
leaq 0x3b69(%rip), %rdi      # 0x6781
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1140
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq