// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/ssd/NVM_PHY_ONFI_NVDDR2.cpp
// Function: SSD_Components::NVM_PHY_ONFI_NVDDR2::perform_interleaved_cmd_data_transfer(NVM::FlashMemory::Flash_Chip*, SSD_Components::DieBookKeepingEntry*)
void NVM_PHY_ONFI_NVDDR2::perform_interleaved_cmd_data_transfer(NVM::FlashMemory::Flash_Chip* chip, DieBookKeepingEntry* bookKeepingEntry)
	{
		ONFI_Channel_NVDDR2* target_channel = channels[bookKeepingEntry->ActiveTransactions.front()->Address.ChannelID];
		/*if (target_channel->Status == BusChannelStatus::BUSY)
			PRINT_ERROR("Requesting communication on a busy bus!")*/

		switch (bookKeepingEntry->ActiveTransactions.front()->Type)
		{
			case Transaction_Type::READ:
				chip->StartCMDXfer();
				bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_IN;
				Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime,
					this, bookKeepingEntry, (int)NVDDR2_SimEventType::READ_CMD_ADDR_TRANSFERRED);
				break;
			case Transaction_Type::WRITE:
				if (((NVM_Transaction_Flash_WR*)bookKeepingEntry->ActiveTransactions.front())->RelatedRead == NULL) {
					chip->StartCMDDataInXfer();
					bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_DATA_IN;
					Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime,
						this, bookKeepingEntry, (int)NVDDR2_SimEventType::PROGRAM_CMD_ADDR_DATA_TRANSFERRED);
				} else {
					chip->StartCMDXfer();
					bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_IN;
					Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime, this,
						bookKeepingEntry, (int)NVDDR2_SimEventType::READ_CMD_ADDR_TRANSFERRED);
				}
				break;
			case Transaction_Type::ERASE:
				chip->StartCMDXfer();
				bookKeepingTable[chip->ChannelID][chip->ChipID].Status = ChipStatus::CMD_IN;
				Simulator->Register_sim_event(Simulator->Time() + bookKeepingEntry->DieInterleavedTime,
					this, bookKeepingEntry, (int)NVDDR2_SimEventType::ERASE_SETUP_COMPLETED);
				break;
			default:
				PRINT_ERROR("NVMController_NVDDR2: Uknown flash transaction type!")
		}
		target_channel->SetStatus(BusChannelStatus::BUSY, chip);
	}

// Assembly:
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r12
movq 0x88(%rdi), %rdx
movq 0x8(%r15), %rax
movq 0x10(%rax), %rax
movl 0x8(%rax), %ecx
movl 0x38(%rax), %esi
movq (%rdx,%rsi,8), %r14
cmpl $0x2, %ecx
je 0x38bb5
cmpl $0x1, %ecx
je 0x38b62
testl %ecx, %ecx
je 0x38b70
movq 0x294c8(%rip), %rbx     # 0x61ff0
leaq 0xba59(%rip), %rsi      # 0x44588
movq %rbx, %rdi
callq 0x7360
leaq 0xf843(%rip), %rsi      # 0x48381
movq %rbx, %rdi
callq 0x7360
movq %rax, %rdi
callq 0x71a0
movq 0x2947b(%rip), %rdi     # 0x61fd0
callq 0x73d0
pushq $0x1
popq %rdi
callq 0x73e0
cmpq $0x0, 0x88(%rax)
je 0x38bf7
movq %rbx, %rdi
callq 0x3918e
movq 0x90(%r12), %rax
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
movq (%rax,%rcx,8), %rax
shlq $0x7, %rdx
movl $0x1, (%rax,%rdx)
callq 0x1f784
movq %rax, %r13
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
addq 0x60(%r15), %rax
pushq $0x1
jmp 0x38c37
movq %rbx, %rdi
callq 0x3918e
movq 0x90(%r12), %rax
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
movq (%rax,%rcx,8), %rax
shlq $0x7, %rdx
movl $0x1, (%rax,%rdx)
callq 0x1f784
movq %rax, %r13
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
addq 0x60(%r15), %rax
pushq $0x4
jmp 0x38c37
movq %rbx, %rdi
callq 0x391a8
movq 0x90(%r12), %rax
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
movq (%rax,%rcx,8), %rax
shlq $0x7, %rdx
movl $0x2, (%rax,%rdx)
callq 0x1f784
movq %rax, %r13
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
addq 0x60(%r15), %rax
pushq $0x2
popq %r8
movq %r13, %rdi
movq %rax, %rsi
movq %r12, %rdx
movq %r15, %rcx
callq 0x1fb00
movq %r14, %rdi
xorl %esi, %esi
movq %rbx, %rdx
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
jmp 0x391c2