// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/dram_controller.cc
// Function: MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE*)
void MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE *queue)
{
    for (uint32_t i=0; i<queue->SIZE; i++) {
        if (queue->entry[i].scheduled) {

            uint64_t op_addr = queue->entry[i].address;
            uint32_t op_cpu = queue->entry[i].cpu,
                     op_channel = dram_get_channel(op_addr), 
                     op_rank = dram_get_rank(op_addr), 
                     op_bank = dram_get_bank(op_addr), 
                     op_row = dram_get_row(op_addr);

#ifdef DEBUG_PRINT
            //uint32_t op_column = dram_get_column(op_addr);
#endif

            // update open row
            if ((bank_request[op_channel][op_rank][op_bank].cycle_available - tCAS) <= current_core_cycle[op_cpu])
                bank_request[op_channel][op_rank][op_bank].open_row = op_row;
            else
                bank_request[op_channel][op_rank][op_bank].open_row = UINT32_MAX;

            // this bank is ready for another DRAM request
            bank_request[op_channel][op_rank][op_bank].request_index = -1;
            bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0;
            bank_request[op_channel][op_rank][op_bank].working = 0;
            bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu];
            if (bank_request[op_channel][op_rank][op_bank].is_write) {
                scheduled_writes--;
                bank_request[op_channel][op_rank][op_bank].is_write = 0;
            }
            else if (bank_request[op_channel][op_rank][op_bank].is_read) {
                scheduled_reads--;
                bank_request[op_channel][op_rank][op_bank].is_read = 0;
            }

            queue->entry[i].scheduled = 0;
            queue->entry[i].event_cycle = current_core_cycle[op_cpu];

            DP ( if (warmup_complete[op_cpu]) {
            cout << queue->NAME << " instr_id: " << queue->entry[i].instr_id << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads << endl; });

        }
    }
    
    update_schedule_cycle(&RQ);
    update_schedule_cycle(&WQ);
    update_process_cycle(&RQ);
    update_process_cycle(&WQ);

#ifdef SANITY_CHECK
    if (queue->is_WQ) {
        if (scheduled_writes != 0)
            assert(0);
    }
    else {
        if (scheduled_reads != 0)
            assert(0);
    }
#endif
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdi, %rbx
movq %rsi, 0x10(%rsp)
movl 0x20(%rsi), %eax
leaq 0x7858(%rdi), %rcx
movq %rcx, 0x20(%rsp)
movl 0xf161(%rip), %ecx      # 0x1820c
movq %rcx, 0x18(%rsp)
movl 0x7848(%rdi), %ecx
movl %ecx, 0xc(%rsp)
movl 0x784c(%rdi), %edi
pushq $0x2
popq %r8
xorl %r9d, %r9d
leaq 0x73de2(%rip), %rdx     # 0x7ceb0
xorl %r15d, %r15d
cmpq %rax, %r15
jae 0x91bd
movq 0x10(%rsp), %rcx
movq 0x98(%rcx), %r12
cmpb $0x0, (%r12,%r8)
je 0x91ae
movq %rbx, %r10
movq 0x33e(%r12,%r8), %r11
movl 0x32e(%r12,%r8), %r13d
movl %r11d, %ebp
shrl $0x8, %ebp
andl $0x7, %ebp
movl %r11d, %esi
andl $0x7, %esi
imulq $0x140, %rbp, %rbx      # imm = 0x140
addq 0x20(%rsp), %rbx
imulq $0x28, %rsi, %rsi
leaq (%rbx,%rsi), %rbp
movq (%rsi,%rbx), %rcx
subq 0x18(%rsp), %rcx
movq %rdx, %r14
movq (%rdx,%r13,8), %rdx
shrl $0xb, %r11d
andl $0x7fff, %r11d          # imm = 0x7FFF
cmpq %rdx, %rcx
pushq $-0x1
popq %rcx
cmoval %ecx, %r11d
movl %r11d, 0x18(%rsi,%rbx)
orl $-0x1, 0x24(%rsi,%rbx)
movb %r9b, 0x1e(%rsi,%rbx)
movb %r9b, 0x1c(%rsi,%rbx)
movq %rdx, (%rsi,%rbx)
cmpb %r9b, 0x20(%rsi,%rbx)
je 0x917d
decl %edi
movq %r10, %rbx
movl %edi, 0x784c(%r10)
movb $0x0, 0x20(%rbp)
jmp 0x919a
cmpb $0x0, 0x21(%rbp)
movq %r10, %rbx
je 0x919a
movl 0xc(%rsp), %ecx
decl %ecx
movl %ecx, 0xc(%rsp)
movl %ecx, 0x7848(%rbx)
movb $0x0, 0x21(%rbp)
movq %r14, %rdx
movb $0x0, (%r12,%r8)
movq (%r14,%r13,8), %rcx
movq %rcx, 0x376(%r12,%r8)
incq %r15
addq $0x380, %r8             # imm = 0x380
jmp 0x90d1
leaq 0x9ef8(%rbx), %r15
movq %r15, %rsi
callq 0x9270
leaq 0x8258(%rbx), %r12
movq %r12, %rsi
callq 0x9270
movq %r15, %rsi
callq 0x92c4
movq %r12, %rsi
callq 0x92c4
movq 0x10(%rsp), %rax
cmpb $0x0, 0x25(%rax)
je 0x9218
cmpl $0x0, 0x784c(%rbx)
je 0x9221
leaq 0x6e61(%rip), %rdi      # 0x10067
leaq 0x788d(%rip), %rsi      # 0x10a9a
leaq 0x789d(%rip), %rcx      # 0x10ab1
pushq $0x3c
jmp 0x9247
cmpl $0x0, 0x7848(%rbx)
jne 0x9230
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x6e30(%rip), %rdi      # 0x10067
leaq 0x785c(%rip), %rsi      # 0x10a9a
leaq 0x786c(%rip), %rcx      # 0x10ab1
pushq $0x40
popq %rdx
callq 0x2160
nop