// File: /workspace/github_cpp_makefile_star2_O3/NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE*)
void DRC_MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE *queue)
{
    for (uint32_t i=0; i<queue->SIZE; i++) {
        if (queue->entry[i].scheduled) {

            uint64_t op_addr = queue->entry[i].address;
            uint32_t op_cpu = queue->entry[i].cpu,
                     op_channel = drc_get_channel(op_addr), 
                     op_rank = drc_get_rank(op_addr), 
                     op_bank = drc_get_bank(op_addr), 
                     op_row = drc_get_row(op_addr);

#ifdef DEBUG_PRINT
            //uint32_t op_column = drc_get_column(op_addr);
#endif

            // update open row
            if ((bank_request[op_channel][op_rank][op_bank].cycle_available - tCAS) <= current_core_cycle[op_cpu])
                bank_request[op_channel][op_rank][op_bank].open_row = op_row;
            else
                bank_request[op_channel][op_rank][op_bank].open_row = UINT32_MAX;

            // this bank is ready for another DRC request
            bank_request[op_channel][op_rank][op_bank].request_index = -1;
            bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0;
            bank_request[op_channel][op_rank][op_bank].working = 0;
            bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu];
            if (bank_request[op_channel][op_rank][op_bank].is_write) {
                scheduled_writes--;
                bank_request[op_channel][op_rank][op_bank].is_write = 0;
            }
            else if (bank_request[op_channel][op_rank][op_bank].is_read) {
                scheduled_reads--;
                bank_request[op_channel][op_rank][op_bank].is_read = 0;
            }

            queue->entry[i].scheduled = 0;
            queue->entry[i].event_cycle = current_core_cycle[op_cpu];

            DP ( if (warmup_complete[op_cpu]) {
            cout << queue->NAME << " instr_id: " << queue->entry[i].instr_id << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads << endl; });

        }
    }
    
    update_schedule_cycle(&RQ);
    update_schedule_cycle(&WQ);
    update_process_cycle(&RQ);
    update_process_cycle(&WQ);

#ifdef SANITY_CHECK
    if (queue->is_WQ) {
        if (scheduled_writes != 0)
            assert(0);
    }
    else {
        if (scheduled_reads != 0)
            assert(0);
    }
#endif
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsi, (%rsp)
movl 0x20(%rsi), %edi
testq %rdi, %rdi
je 0x11832
movq (%rsp), %rax
movq 0x98(%rax), %rax
leaq 0x409470(%rbx), %rcx
movl 0x409464(%rbx), %edx
movl 0x409468(%rbx), %esi
imulq $0x380, %rdi, %rdi      # imm = 0x380
xorl %r8d, %r8d
leaq 0x6f777(%rip), %r10     # 0x80ec0
movl $0xffffffff, %r11d      # imm = 0xFFFFFFFF
xorl %r15d, %r15d
cmpb $0x0, 0x2(%rax,%r15)
je 0x11822
movl 0x330(%rax,%r15), %r12d
movl 0x340(%rax,%r15), %ebp
movl %ebp, %r13d
shrl $0x5, %r13d
andl $0x3, %r13d
movl %ebp, %r14d
shrl $0xb, %r14d
andl $0x1, %r14d
movl %ebp, %r9d
shrl $0x7, %r9d
andl $0xf, %r9d
leaq (%r13,%r13,4), %r13
shll $0x8, %r13d
addq %rcx, %r13
leaq (%r14,%r14,4), %r14
shll $0x7, %r14d
addq %r13, %r14
leaq (%r9,%r9,4), %r9
leaq (%r14,%r9,8), %r13
movq (%r13), %r9
leaq 0xaa63(%rip), %r14      # 0x1c21c
movl (%r14), %r14d
subq %r14, %r9
movq (%r10,%r12,8), %r14
shrl $0xc, %ebp
andl $0xfff, %ebp            # imm = 0xFFF
cmpq %r14, %r9
cmoval %r11d, %ebp
movl %ebp, 0x18(%r13)
movl %r11d, 0x24(%r13)
movb %r8b, 0x1e(%r13)
movb %r8b, 0x1c(%r13)
movq %r14, (%r13)
cmpb %r8b, 0x20(%r13)
je 0x117fc
decl %esi
movl %esi, 0x409468(%rbx)
movb $0x0, 0x20(%r13)
jmp 0x11810
cmpb $0x0, 0x21(%r13)
je 0x11810
decl %edx
movl %edx, 0x409464(%rbx)
movb $0x0, 0x21(%r13)
movb $0x0, 0x2(%rax,%r15)
movq (%r10,%r12,8), %r9
movq %r9, 0x378(%rax,%r15)
addq $0x380, %r15            # imm = 0x380
cmpq %r15, %rdi
jne 0x11752
leaq 0x40c510(%rbx), %rsi
callq 0x11996
leaq 0x40a870(%rbx), %rsi
callq 0x11996
movl 0x40c530(%rbx), %edx
xorl %ecx, %ecx
movq $-0x1, %rax
movq $-0x1, %rsi
movl $0x0, %r8d
testq %rdx, %rdx
je 0x118a2
movq 0x40c5a8(%rbx), %rdi
addq $0x2, %rdi
xorl %r9d, %r9d
movl %edx, %r8d
cmpb $0x0, (%rdi)
je 0x11893
movq 0x376(%rdi), %r10
cmpq %rsi, %r10
cmovbq %r10, %rsi
cmovbl %r9d, %r8d
incq %r9
addq $0x380, %rdi            # imm = 0x380
cmpq %r9, %rdx
jne 0x1187c
movq %rsi, 0x40c568(%rbx)
movl %r8d, 0x40c554(%rbx)
movl 0x40a890(%rbx), %edx
testq %rdx, %rdx
je 0x118f6
movq 0x40a908(%rbx), %rsi
addq $0x2, %rsi
movq $-0x1, %rax
xorl %edi, %edi
movl %edx, %ecx
cmpb $0x0, (%rsi)
je 0x118e7
movq 0x376(%rsi), %r8
cmpq %rax, %r8
cmovbq %r8, %rax
cmovbl %edi, %ecx
incq %rdi
addq $0x380, %rsi            # imm = 0x380
cmpq %rdi, %rdx
jne 0x118d1
movq %rax, 0x40a8c8(%rbx)
movl %ecx, 0x40a8b4(%rbx)
movq (%rsp), %rax
cmpb $0x0, 0x25(%rax)
je 0x11935
cmpl $0x0, 0x409468(%rbx)
je 0x1193e
leaq 0x274a(%rip), %rdi      # 0x14067
leaq 0x37ac(%rip), %rsi      # 0x150d0
leaq 0x37bb(%rip), %rcx      # 0x150e6
movl $0x3d, %edx
callq 0x3160
cmpl $0x0, 0x409464(%rbx)
jne 0x1194d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x2713(%rip), %rdi      # 0x14067
leaq 0x3775(%rip), %rsi      # 0x150d0
leaq 0x3784(%rip), %rcx      # 0x150e6
movl $0x41, %edx
callq 0x3160