// File: NishadSaraf[P]Championship-Simulator/src/ooo_cpu.cc
// Function: O3_CPU::add_load_queue(unsigned int, unsigned int)
void O3_CPU::add_load_queue(uint32_t rob_index, uint32_t data_index)
{
    // search for an empty slot 
    uint32_t lq_index = LQ.SIZE;
    for (uint32_t i=0; i<LQ.SIZE; i++) {
        if (LQ.entry[i].virtual_address == 0) {
            lq_index = i;
            break;
        }
    }

    // sanity check
    if (lq_index == LQ.SIZE) {
        cerr << "instr_id: " << ROB.entry[rob_index].instr_id << " no empty slot in the load queue!!!" << endl;
        assert(0);
    }

    // add it to the load queue
    ROB.entry[rob_index].lq_index[data_index] = lq_index;
    LQ.entry[lq_index].instr_id = ROB.entry[rob_index].instr_id;
    LQ.entry[lq_index].virtual_address = ROB.entry[rob_index].source_memory[data_index];
    LQ.entry[lq_index].ip = ROB.entry[rob_index].ip;
    LQ.entry[lq_index].data_index = data_index;
    LQ.entry[lq_index].rob_index = rob_index;
    LQ.entry[lq_index].asid[0] = ROB.entry[rob_index].asid[0];
    LQ.entry[lq_index].asid[1] = ROB.entry[rob_index].asid[1];
    LQ.entry[lq_index].event_cycle = current_core_cycle[cpu] + SCHEDULING_LATENCY;
    LQ.occupancy++;

    // check RAW dependency
    int prior = rob_index - 1;
    if (prior < 0)
        prior = ROB.SIZE - 1;

    if (rob_index != ROB.head) {
        if ((int)ROB.head <= prior) {
            for (int i=prior; i>=(int)ROB.head; i--) {
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
        }
        else {
            for (int i=prior; i>=0; i--) {
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
            for (int i=ROB.SIZE-1; i>=(int)ROB.head; i--) { 
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
        }
    }

    // check
    // 1) if store-to-load forwarding is possible
    // 2) if there is WAR that are not correctly executed
    uint32_t forwarding_index = SQ.SIZE;
    for (uint32_t i=0; i<SQ.SIZE; i++) {

        // skip empty slot
        if (SQ.entry[i].virtual_address == 0)
            continue;

        // forwarding should be done by the SQ entry that holds the same producer_id from RAW dependency check
        if (SQ.entry[i].virtual_address == LQ.entry[lq_index].virtual_address) { // store-to-load forwarding check

            // forwarding store is in the SQ
            if ((rob_index != ROB.head) && (LQ.entry[lq_index].producer_id == SQ.entry[i].instr_id)) { // RAW
                forwarding_index = i;
                break; // should be break
            }

            if ((LQ.entry[lq_index].producer_id == UINT64_MAX) && (LQ.entry[lq_index].instr_id <= SQ.entry[i].instr_id)) { // WAR 
                // a load is about to be added in the load queue and we found a store that is 
                // "logically later in the program order but already executed" => this is not correctly executed WAR
                // due to out-of-order execution, this case is possible, for example
                // 1) application is load intensive and load queue is full
                // 2) we have loads that can't be added in the load queue
                // 3) subsequent stores logically behind in the program order are added in the store queue first

                // thanks to the store buffer, data is not written back to the memory system until retirement
                // also due to in-order retirement, this "already executed store" cannot be retired until we finish the prior load instruction 
                // if we detect WAR when a load is added in the load queue, just let the load instruction to access the memory system
                // no need to mark any dependency because this is actually WAR not RAW

                // do not forward data from the store queue since this is WAR
                // just read correct data from data cache

                LQ.entry[lq_index].physical_address = 0;
                LQ.entry[lq_index].translated = 0;
                LQ.entry[lq_index].fetched = 0;
                
                DP(if(warmup_complete[cpu]) {
                cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " reset fetched: " << +LQ.entry[lq_index].fetched;
                cout << " to obey WAR store instr_id: " << SQ.entry[i].instr_id << " cycle: " << current_core_cycle[cpu] << endl; });
            }
        }
    }

    if (forwarding_index != SQ.SIZE) { // we have a store-to-load forwarding

        if ((SQ.entry[forwarding_index].fetched == COMPLETED) && (SQ.entry[forwarding_index].event_cycle <= current_core_cycle[cpu])) {
            LQ.entry[lq_index].physical_address = (SQ.entry[forwarding_index].physical_address & ~(uint64_t) ((1 << LOG2_BLOCK_SIZE) - 1)) | (LQ.entry[lq_index].virtual_address & ((1 << LOG2_BLOCK_SIZE) - 1));
            LQ.entry[lq_index].translated = COMPLETED;
            LQ.entry[lq_index].fetched = COMPLETED;

            uint32_t fwr_rob_index = LQ.entry[lq_index].rob_index;
            ROB.entry[fwr_rob_index].num_mem_ops--;
            ROB.entry[fwr_rob_index].event_cycle = current_core_cycle[cpu];
            if (ROB.entry[fwr_rob_index].num_mem_ops < 0) {
                cerr << "instr_id: " << ROB.entry[fwr_rob_index].instr_id << endl;
                assert(0);
            }
            if (ROB.entry[fwr_rob_index].num_mem_ops == 0)
                inflight_mem_executions++;

            DP(if(warmup_complete[cpu]) {
            cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << hex;
            cout << " full_addr: " << LQ.entry[lq_index].physical_address << dec << " is forwarded by store instr_id: ";
            cout << SQ.entry[forwarding_index].instr_id << " remain_num_ops: " << ROB.entry[fwr_rob_index].num_mem_ops << " cycle: " << current_core_cycle[cpu] << endl; });

            release_load_queue(lq_index);
        }
        else
            ; // store is not executed yet, forwarding will be handled by execute_store()
    }

    // succesfully added to the load queue
    ROB.entry[rob_index].source_added[data_index] = 1;

    if (LQ.entry[lq_index].virtual_address && (LQ.entry[lq_index].producer_id == UINT64_MAX)) { // not released and no forwarding
        RTL0[RTL0_tail] = lq_index;
        RTL0_tail++;
        if (RTL0_tail == LQ_SIZE)
            RTL0_tail = 0;

        DP (if (warmup_complete[cpu]) {
        cout << "[RTL0] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " rob_index: " << LQ.entry[lq_index].rob_index << " is added to RTL0";
        cout << " head: " << RTL0_head << " tail: " << RTL0_tail << endl; }); 
    }

    DP(if(warmup_complete[cpu]) {
    cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id;
    cout << " is added in the LQ address: " << hex << LQ.entry[lq_index].virtual_address << dec << " translated: " << +LQ.entry[lq_index].translated;
    cout << " fetched: " << +LQ.entry[lq_index].fetched << " index: " << lq_index << " occupancy: " << LQ.occupancy << " cycle: " << current_core_cycle[cpu] << endl; });
}

// Assembly:
subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movl %esi, 0x3c(%rsp)
movl %edx, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x9e0(%rax), %eax
movl %eax, 0x34(%rsp)
movl $0x0, 0x30(%rsp)
movq 0x8(%rsp), %rcx
movl 0x30(%rsp), %eax
cmpl 0x9e0(%rcx), %eax
jae 0x18578
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x30(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $0x0, 0x10(%rax)
jne 0x18569
movl 0x30(%rsp), %eax
movl %eax, 0x34(%rsp)
jmp 0x18578
jmp 0x1856b
movl 0x30(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x30(%rsp)
jmp 0x1852d
movq 0x8(%rsp), %rcx
movl 0x34(%rsp), %eax
cmpl 0x9e0(%rcx), %eax
jne 0x185fe
movq 0x10a60(%rip), %rdi     # 0x28ff0
leaq 0xb889(%rip), %rsi      # 0x23e20
callq 0x3220
movq %rax, %rdi
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movq (%rax), %rsi
callq 0x3080
movq %rax, %rdi
leaq 0xb756(%rip), %rsi      # 0x23d21
callq 0x3220
movq %rax, %rdi
movq 0x109de(%rip), %rsi     # 0x28fb8
callq 0x3250
leaq 0xaa1e(%rip), %rdi      # 0x23004
leaq 0xb5c8(%rip), %rsi      # 0x23bb5
movl $0x369, %edx            # imm = 0x369
leaq 0xb74c(%rip), %rcx      # 0x23d45
callq 0x3160
movq 0x8(%rsp), %rax
movl 0x34(%rsp), %esi
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movl 0x38(%rsp), %edx
movl %esi, 0x728(%rcx,%rdx,4)
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movq (%rcx), %rdx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, (%rcx)
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movl 0x38(%rsp), %edx
movq 0x5c8(%rcx,%rdx,8), %rdx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x10(%rcx)
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movq 0x8(%rcx), %rdx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x20(%rcx)
movl 0x38(%rsp), %edx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movl %edx, 0x34(%rcx)
movl 0x3c(%rsp), %edx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movl %edx, 0x30(%rcx)
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movb 0x5b(%rcx), %dl
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movb %dl, 0x3e(%rcx)
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movb 0x5c(%rcx), %dl
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movb %dl, 0x3f(%rcx)
movl (%rax), %ecx
movl %ecx, %edx
leaq 0x7775a(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movl 0x77760(%rip), %ecx     # 0x8fed0
addq %rcx, %rdx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x28(%rcx)
movl 0x9e4(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x9e4(%rax)
movl 0x3c(%rsp), %eax
subl $0x1, %eax
movl %eax, 0x2c(%rsp)
cmpl $0x0, 0x2c(%rsp)
jge 0x187bf
movq 0x8(%rsp), %rax
movl 0x950(%rax), %eax
subl $0x1, %eax
movl %eax, 0x2c(%rsp)
movq 0x8(%rsp), %rcx
movl 0x3c(%rsp), %eax
cmpl 0x958(%rcx), %eax
je 0x1891a
movq 0x8(%rsp), %rax
movl 0x958(%rax), %eax
cmpl 0x2c(%rsp), %eax
jg 0x1884e
movl 0x2c(%rsp), %eax
movl %eax, 0x28(%rsp)
movq 0x8(%rsp), %rcx
movl 0x28(%rsp), %eax
cmpl 0x958(%rcx), %eax
jl 0x18849
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $-0x1, 0x8(%rax)
je 0x18821
jmp 0x18849
movq 0x8(%rsp), %rdi
movl 0x28(%rsp), %esi
movl 0x3c(%rsp), %edx
movl 0x38(%rsp), %ecx
movl 0x34(%rsp), %r8d
callq 0x19060
movl 0x28(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x28(%rsp)
jmp 0x187ed
jmp 0x18918
movl 0x2c(%rsp), %eax
movl %eax, 0x24(%rsp)
cmpl $0x0, 0x24(%rsp)
jl 0x188a8
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $-0x1, 0x8(%rax)
je 0x18880
jmp 0x188a8
movq 0x8(%rsp), %rdi
movl 0x24(%rsp), %esi
movl 0x3c(%rsp), %edx
movl 0x38(%rsp), %ecx
movl 0x34(%rsp), %r8d
callq 0x19060
movl 0x24(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x24(%rsp)
jmp 0x18856
movq 0x8(%rsp), %rax
movl 0x950(%rax), %eax
subl $0x1, %eax
movl %eax, 0x20(%rsp)
movq 0x8(%rsp), %rcx
movl 0x20(%rsp), %eax
cmpl 0x958(%rcx), %eax
jl 0x18916
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $-0x1, 0x8(%rax)
je 0x188ee
jmp 0x18916
movq 0x8(%rsp), %rdi
movl 0x20(%rsp), %esi
movl 0x3c(%rsp), %edx
movl 0x38(%rsp), %ecx
movl 0x34(%rsp), %r8d
callq 0x19060
movl 0x20(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x20(%rsp)
jmp 0x188ba
jmp 0x18918
jmp 0x1891a
movq 0x8(%rsp), %rax
movl 0xa18(%rax), %eax
movl %eax, 0x1c(%rsp)
movl $0x0, 0x18(%rsp)
movq 0x8(%rsp), %rcx
movl 0x18(%rsp), %eax
cmpl 0xa18(%rcx), %eax
jae 0x18ac3
movq 0x8(%rsp), %rax
movq 0xa28(%rax), %rax
movl 0x18(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $0x0, 0x10(%rax)
jne 0x1896c
jmp 0x18ab3
movq 0x8(%rsp), %rcx
movq 0xa28(%rcx), %rax
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movq 0x10(%rax), %rax
movq 0x9f0(%rcx), %rcx
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
cmpq 0x10(%rcx), %rax
jne 0x18ab1
movq 0x8(%rsp), %rcx
movl 0x3c(%rsp), %eax
cmpl 0x958(%rcx), %eax
je 0x189ff
movq 0x8(%rsp), %rcx
movq 0x9f0(%rcx), %rax
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movq 0x8(%rax), %rax
movq 0xa28(%rcx), %rcx
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
cmpq (%rcx), %rax
jne 0x189ff
movl 0x18(%rsp), %eax
movl %eax, 0x1c(%rsp)
jmp 0x18ac3
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $-0x1, 0x8(%rax)
jne 0x18aaf
movq 0x8(%rsp), %rcx
movq 0x9f0(%rcx), %rax
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movq (%rax), %rax
movq 0xa28(%rcx), %rcx
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
cmpq (%rcx), %rax
ja 0x18aaf
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movq $0x0, 0x18(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movb $0x0, 0x3c(%rcx)
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movb $0x0, 0x3d(%rax)
jmp 0x18ab1
jmp 0x18ab3
movl 0x18(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x18(%rsp)
jmp 0x18931
movq 0x8(%rsp), %rcx
movl 0x1c(%rsp), %eax
cmpl 0xa18(%rcx), %eax
je 0x18cea
movq 0x8(%rsp), %rax
movq 0xa28(%rax), %rax
movl 0x1c(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movzbl 0x3d(%rax), %eax
cmpl $0x2, %eax
jne 0x18ce6
movq 0x8(%rsp), %rcx
movq 0xa28(%rcx), %rax
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movq 0x28(%rax), %rax
movl (%rcx), %ecx
movl %ecx, %edx
leaq 0x77398(%rip), %rcx     # 0x8fec0
cmpq (%rcx,%rdx,8), %rax
ja 0x18ce6
movq 0x8(%rsp), %rax
movq 0xa28(%rax), %rcx
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movq 0x18(%rcx), %rdx
andq $-0x40, %rdx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq 0x10(%rcx), %rcx
andq $0x3f, %rcx
orq %rcx, %rdx
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x18(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movb $0x2, 0x3c(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movb $0x2, 0x3d(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x34(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x30(%rcx), %ecx
movl %ecx, 0x14(%rsp)
movq 0x9b8(%rax), %rcx
movl 0x14(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movl 0x70(%rcx), %edx
addl $-0x1, %edx
movl %edx, 0x70(%rcx)
movl (%rax), %ecx
movl %ecx, %edx
leaq 0x772bc(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movq 0x9b8(%rax), %rcx
movl 0x14(%rsp), %esi
imulq $0x758, %rsi, %rsi      # imm = 0x758
addq %rsi, %rcx
movq %rdx, 0x40(%rcx)
movq 0x9b8(%rax), %rax
movl 0x14(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpl $0x0, 0x70(%rax)
jge 0x18ca2
movq 0x103ad(%rip), %rdi     # 0x28ff0
leaq 0xb1d6(%rip), %rsi      # 0x23e20
callq 0x3220
movq %rax, %rdi
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x14(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movq (%rax), %rsi
callq 0x3080
movq %rax, %rdi
movq 0x1033a(%rip), %rsi     # 0x28fb8
callq 0x3250
leaq 0xa37a(%rip), %rdi      # 0x23004
leaq 0xaf24(%rip), %rsi      # 0x23bb5
movl $0x3d0, %edx            # imm = 0x3D0
leaq 0xb0a8(%rip), %rcx      # 0x23d45
callq 0x3160
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x14(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpl $0x0, 0x70(%rax)
jne 0x18cd6
movq 0x8(%rsp), %rax
movl 0x924(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x924(%rax)
movq 0x8(%rsp), %rdi
movl 0x34(%rsp), %esi
callq 0x191c0
jmp 0x18ce8
jmp 0x18ce8
jmp 0x18cea
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rcx
movl 0x3c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movl 0x38(%rsp), %edx
movb $0x1, 0x4e(%rcx,%rdx)
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $0x0, 0x10(%rax)
je 0x18d89
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
cmpq $-0x1, 0x8(%rax)
jne 0x18d89
movq 0x8(%rsp), %rax
movl 0x34(%rsp), %edx
movl 0x3374(%rax), %ecx
movl %edx, 0x3250(%rax,%rcx,4)
movl 0x3374(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x3374(%rax)
cmpl $0x48, 0x3374(%rax)
jne 0x18d87
movq 0x8(%rsp), %rax
movl $0x0, 0x3374(%rax)
jmp 0x18d89
addq $0x48, %rsp
retq
nop