// File: luooofan[P]hblzbd_compiler/src/Pass/generate_arm_from_ssa.cpp
// Function: GenerateArmFromSSA::ConvertDiv2Shift(ArmBasicBlock*, arm::Reg*, Value*, int)
bool GenerateArmFromSSA::ConvertDiv2Shift(ArmBasicBlock* armbb, Reg* rd, Value* val, int imm) {
  // 如果除数是0 应该生成报错
  if (0 == imm) {
    MyAssert(0);
  }
  auto eval_n = [](int imm) {
    int n = 0;
    while (imm > 1) {
      imm >>= 1;
      ++n;
    }
    return n;
  };
  auto cal = [](int b) {
    if (b < 0) b = -b;
    long long k = std::log2(b);
    long long m = (1.0 * (1ll << (k + 32)) / b + 1);
    return std::make_pair(k, m);
  };
  // 如果除数是2的幂次方 生成一条mov rd rm A(L)SR n的指令 允许1-32位
  // FIXME: 这样做并不适用于被除数是负数的情况
  // if (0 == (imm & (imm - 1))) {
  //   std::cout << "Warning Div" << std::endl;
  //   auto op2 = new Operand2(ResolveValue2Reg(armbb, val), new Shift(Shift::OpCode::ASR, eval_n(imm)));
  //   new Move(rd, op2, armbb);
  //   return true;
  // }
  // 考虑负数情况
  if (0 == (imm & (imm - 1))) {
    // 1. asr vreg, rn, #31;  i.e. mov vreg, rn, ASR #31;
    auto vreg = NewVirtualReg();
    auto rn = ResolveValue2Reg(armbb, val);
    new Move(vreg, new Operand2(rn, new Shift(Shift::OpCode::ASR, 31)), armbb);
    // 2. add vreg2, rn, vreg, lsr #(32-n);
    auto vreg2 = NewVirtualReg();
    auto n = eval_n(imm);
    auto op2 = new Operand2(vreg, new Shift(Shift::OpCode::LSR, 32 - n));
    new BinaryInst(BinaryInst::OpCode::ADD, vreg2, rn, op2, armbb);
    // 3. asr rd, vreg2, #n;  i.e. mov rd, vreg2, ASR #n;
    new Move(rd, new Operand2(vreg2, new Shift(Shift::OpCode::ASR, n)), armbb);
    return true;
  }
  // 除其他常数优化
  // a/b的情况下，b为常数
  // (sub t0 0 a)   // b<0则有，b>0则无
  // smmul t1 t0/a m // t0和a看有无上一句
  // mov t2 t1 asr k
  // add t2 t2 t1 lsr 31
  else {
    return false;
    auto [k, m] = cal(imm);
    std::cout << "除常数优化" << imm << " " << k << " " << m << std::endl;
    if (imm == 30) {
      k = 4;
      m = 2290649225;
    } else if (imm == 998244353) {
      k = 26;
      m = 288737297;
    } else {
      return false;
    }
    Reg* vreg0;
    if (imm < 0) {
      vreg0 = NewVirtualReg();
      new BinaryInst(BinaryInst::OpCode::RSB, vreg0, ResolveValue2Reg(armbb, val), new Operand2(0), armbb);
    } else {
      vreg0 = ResolveValue2Reg(armbb, val);
    }
    auto vreg1 = NewVirtualReg();
    new BinaryInst(BinaryInst::OpCode::SMMUL, vreg1, vreg0, ResolveImm2Operand2(armbb, m), armbb);
    auto vreg3 = NewVirtualReg();
    if (imm == 30) {
      new BinaryInst(BinaryInst::OpCode::ADD, vreg3, vreg0, new Operand2(vreg1), armbb);
    }
    auto vreg2 = NewVirtualReg();
    if (imm == 30) {
      new Move(vreg2, new Operand2(vreg3, new Shift(Shift::OpCode::ASR, k)), armbb);
    } else {
      new Move(vreg2, new Operand2(vreg1, new Shift(Shift::OpCode::ASR, k)), armbb);
    }
    new BinaryInst(BinaryInst::OpCode::ADD, rd, vreg2, new Operand2(vreg1, new Shift(Shift::OpCode::LSR, 31)), armbb);
    return true;
  }
  return false;
}

// Assembly:
subq $0x128, %rsp            # imm = 0x128
movq %rdi, 0x118(%rsp)
movq %rsi, 0x110(%rsp)
movq %rdx, 0x108(%rsp)
movq %rcx, 0x100(%rsp)
movl %r8d, 0xfc(%rsp)
movq 0x118(%rsp), %rax
movq %rax, 0x78(%rsp)
xorl %eax, %eax
cmpl 0xfc(%rsp), %eax
jne 0xac61e
movq 0x9fa1a(%rip), %rdi     # 0x14bfe8
leaq 0x4db23(%rip), %rsi     # 0xfa0f8
callq 0x8330
movq %rax, %rdi
leaq 0x513e5(%rip), %rsi     # 0xfd9c9
callq 0x8330
movq %rax, %rdi
leaq 0x4edf7(%rip), %rsi     # 0xfb3ea
callq 0x8330
movq %rax, %rdi
movl $0xa0, %esi
callq 0x8650
movq %rax, %rdi
movq 0x9f971(%rip), %rsi     # 0x14bf80
callq 0x8380
movl $0xff, %edi
callq 0x8460
movl 0xfc(%rsp), %ecx
movl 0xfc(%rsp), %eax
subl $0x1, %eax
andl %eax, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jne 0xac9e7
movq 0x78(%rsp), %rdi
callq 0xaaf80
movq 0x78(%rsp), %rdi
movq %rax, 0xf0(%rsp)
movq 0x110(%rsp), %rsi
movq 0x100(%rsp), %rdx
callq 0xabf80
movq %rax, 0xe8(%rsp)
movl $0x28, %edi
callq 0x8340
movq %rax, 0x60(%rsp)
movq 0xf0(%rsp), %rax
movq %rax, 0x68(%rsp)
movl $0x18, %edi
callq 0x8340
movq %rax, 0x70(%rsp)
jmp 0xac69c
movq 0xe8(%rsp), %rax
movq %rax, 0x50(%rsp)
movl $0x18, %edi
callq 0x8340
movq %rax, 0x58(%rsp)
jmp 0xac6ba
movq 0x58(%rsp), %rdi
xorl %esi, %esi
movl $0x1f, %edx
callq 0xb2340
jmp 0xac6cd
movq 0x58(%rsp), %rdx
movq 0x50(%rsp), %rsi
movq 0x70(%rsp), %rdi
callq 0xb2370
jmp 0xac6e3
movq 0x70(%rsp), %rdx
movq 0x68(%rsp), %rsi
movq 0x60(%rsp), %rdi
movq 0x110(%rsp), %rcx
xorl %r8d, %r8d
movl $0x1, %r9d
callq 0xb2060
jmp 0xac70a
movq 0x78(%rsp), %rdi
callq 0xaaf80
movq %rax, 0xd0(%rsp)
movl 0xfc(%rsp), %esi
leaq 0xfb(%rsp), %rdi
callq 0xaca10
movl %eax, 0xcc(%rsp)
movl $0x18, %edi
movq %rdi, 0x30(%rsp)
callq 0x8340
movq 0x30(%rsp), %rdi
movq %rax, 0x38(%rsp)
movq 0xf0(%rsp), %rax
movq %rax, 0x40(%rsp)
callq 0x8340
movq %rax, 0x48(%rsp)
jmp 0xac769
movq 0x48(%rsp), %rdi
movl 0xcc(%rsp), %eax
movl $0x20, %edx
subl %eax, %edx
movl $0x2, %esi
callq 0xb2340
jmp 0xac788
movq 0x48(%rsp), %rdx
movq 0x40(%rsp), %rsi
movq 0x38(%rsp), %rdi
callq 0xb2370
jmp 0xac79e
movq 0x38(%rsp), %rax
movq %rax, 0xc0(%rsp)
movl $0x38, %edi
callq 0x8340
movq %rax, %rdi
movq %rdi, %rax
movq %rax, 0x28(%rsp)
movq 0xd0(%rsp), %rdx
movq 0xe8(%rsp), %rcx
movq 0xc0(%rsp), %r8
movq 0x110(%rsp), %r9
xorl %esi, %esi
callq 0xb23b0
jmp 0xac7e9
movl $0x28, %edi
callq 0x8340
movq %rax, 0x10(%rsp)
movq 0x108(%rsp), %rax
movq %rax, 0x18(%rsp)
movl $0x18, %edi
callq 0x8340
movq %rax, 0x20(%rsp)
jmp 0xac816
movq 0xd0(%rsp), %rax
movq %rax, (%rsp)
movl $0x18, %edi
callq 0x8340
movq %rax, 0x8(%rsp)
jmp 0xac833
movq 0x8(%rsp), %rdi
movl 0xcc(%rsp), %edx
xorl %esi, %esi
callq 0xb2340
jmp 0xac848
movq 0x8(%rsp), %rdx
movq (%rsp), %rsi
movq 0x20(%rsp), %rdi
callq 0xb2370
jmp 0xac85d
movq 0x20(%rsp), %rdx
movq 0x18(%rsp), %rsi
movq 0x10(%rsp), %rdi
movq 0x110(%rsp), %rcx
xorl %r8d, %r8d
movl $0x1, %r9d
callq 0xb2060
jmp 0xac884
movb $0x1, 0x127(%rsp)
jmp 0xac9ef
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
jmp 0xac8ef
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
jmp 0xac8e0
movq 0x58(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
movl $0x18, %esi
callq 0x8350
movq 0x70(%rsp), %rdi
movl $0x18, %esi
callq 0x8350
movq 0x60(%rsp), %rdi
movl $0x28, %esi
callq 0x8350
jmp 0xaca00
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
jmp 0xac93c
movq 0x48(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
movl $0x18, %esi
callq 0x8350
movq 0x38(%rsp), %rdi
movl $0x18, %esi
callq 0x8350
jmp 0xaca00
movq 0x28(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
movl $0x38, %esi
callq 0x8350
jmp 0xaca00
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
jmp 0xac9d6
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
jmp 0xac9c7
movq 0x8(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0xe0(%rsp)
movl %eax, 0xdc(%rsp)
movl $0x18, %esi
callq 0x8350
movq 0x20(%rsp), %rdi
movl $0x18, %esi
callq 0x8350
movq 0x10(%rsp), %rdi
movl $0x28, %esi
callq 0x8350
jmp 0xaca00
movb $0x0, 0x127(%rsp)
movb 0x127(%rsp), %al
andb $0x1, %al
addq $0x128, %rsp            # imm = 0x128
retq
movq 0xe0(%rsp), %rdi
callq 0x8670
nopl (%rax)