// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/ssd/Data_Cache_Manager_Flash_Simple.cpp
// Function: SSD_Components::Data_Cache_Manager_Flash_Simple::write_to_destage_buffer(SSD_Components::User_Request*)
void Data_Cache_Manager_Flash_Simple::write_to_destage_buffer(User_Request* user_request)
	{
		//To eliminate race condition, MQSim assumes the management information and user data are stored in separate DRAM modules
		unsigned int cache_eviction_read_size_in_sectors = 0;//The size of data evicted from cache
		unsigned int flash_written_back_write_size_in_sectors = 0;//The size of data that is both written back to flash and written to DRAM
		unsigned int dram_write_size_in_sectors = 0;//The size of data written to DRAM (must be >= flash_written_back_write_size_in_sectors)
		std::list<NVM_Transaction*>* evicted_cache_slots = new std::list<NVM_Transaction*>;
		std::list<NVM_Transaction*> writeback_transactions;
		auto it = user_request->Transaction_list.begin();

		while (it != user_request->Transaction_list.end()
			&& (back_pressure_buffer_depth + cache_eviction_read_size_in_sectors + flash_written_back_write_size_in_sectors) < back_pressure_buffer_max_depth) {
			NVM_Transaction_Flash_WR* tr = (NVM_Transaction_Flash_WR*)(*it);
			if (data_cache->Exists(tr->Stream_id, tr->LPA))//If the logical address already exists in the cache
			{
				/*MQSim should get rid of writting stale data to the cache.
				* This situation may result from out-of-order transaction execution*/
				Data_Cache_Slot_Type slot = data_cache->Get_slot(tr->Stream_id, tr->LPA);
				sim_time_type timestamp = slot.Timestamp;
				NVM::memory_content_type content = slot.Content;
				if (tr->DataTimeStamp > timestamp) {
					timestamp = tr->DataTimeStamp;
					content = tr->Content;
				}
				data_cache->Update_data(tr->Stream_id, tr->LPA, content, timestamp, tr->write_sectors_bitmap | slot.State_bitmap_of_existing_sectors);
			} else { //the logical address is not in the cache
				if (!data_cache->Check_free_slot_availability()) {
					Data_Cache_Slot_Type evicted_slot = data_cache->Evict_one_slot_lru();
					if (evicted_slot.Status == Cache_Slot_Status::DIRTY_NO_FLASH_WRITEBACK) {
						evicted_cache_slots->push_back(new NVM_Transaction_Flash_WR(Transaction_Source_Type::CACHE,
							tr->Stream_id, count_sector_no_from_status_bitmap(evicted_slot.State_bitmap_of_existing_sectors) * SECTOR_SIZE_IN_BYTE,
							evicted_slot.LPA, NULL, IO_Flow_Priority_Class::URGENT, evicted_slot.Content, evicted_slot.State_bitmap_of_existing_sectors, evicted_slot.Timestamp));
						cache_eviction_read_size_in_sectors += count_sector_no_from_status_bitmap(evicted_slot.State_bitmap_of_existing_sectors);
						//DEBUG2("Evicting page" << evicted_slot.LPA << " from write buffer ")
					}
				}
				data_cache->Insert_write_data(tr->Stream_id, tr->LPA, tr->Content, tr->DataTimeStamp, tr->write_sectors_bitmap);
			}
			dram_write_size_in_sectors += count_sector_no_from_status_bitmap(tr->write_sectors_bitmap);

			//hot/cold data separation
			if (bloom_filter[0].find(tr->LPA) == bloom_filter[0].end()) {
				data_cache->Change_slot_status_to_writeback(tr->Stream_id, tr->LPA); //Eagerly write back cold data
				flash_written_back_write_size_in_sectors += count_sector_no_from_status_bitmap(tr->write_sectors_bitmap);
				bloom_filter[0].insert(tr->LPA);
				writeback_transactions.push_back(tr);
			}
			user_request->Transaction_list.erase(it++);
		}

		user_request->Sectors_serviced_from_cache += dram_write_size_in_sectors;//This is very important update. It is used to decide when all data sectors of a user request are serviced
		back_pressure_buffer_depth += cache_eviction_read_size_in_sectors + flash_written_back_write_size_in_sectors;

		//Issue memory read for cache evictions
		if (evicted_cache_slots->size() > 0) {
			Memory_Transfer_Info* read_transfer_info = new Memory_Transfer_Info;
			read_transfer_info->Size_in_bytes = cache_eviction_read_size_in_sectors * SECTOR_SIZE_IN_BYTE;
			read_transfer_info->Related_request = evicted_cache_slots;
			read_transfer_info->next_event_type = Data_Cache_Simulation_Event_Type::MEMORY_READ_FOR_CACHE_EVICTION_FINISHED;
			read_transfer_info->Stream_id = user_request->Stream_id;
			service_dram_access_request(read_transfer_info);
		}

		//Issue memory write to write data to DRAM
		if (dram_write_size_in_sectors) {
			Memory_Transfer_Info* write_transfer_info = new Memory_Transfer_Info;
			write_transfer_info->Size_in_bytes = dram_write_size_in_sectors * SECTOR_SIZE_IN_BYTE;
			write_transfer_info->Related_request = user_request;
			write_transfer_info->next_event_type = Data_Cache_Simulation_Event_Type::MEMORY_WRITE_FOR_USERIO_FINISHED;
			write_transfer_info->Stream_id = user_request->Stream_id;
			service_dram_access_request(write_transfer_info);
		}

		//If any writeback should be performed, then issue flash write transactions
		if (writeback_transactions.size() > 0) {
			static_cast<FTL*>(nvm_firmware)->Address_Mapping_Unit->Translate_lpa_to_ppa_and_dispatch(writeback_transactions);
		}

		//Reset control data structures used for hot/cold separation 
		if (Simulator->Time() > next_bloom_filter_reset_milestone) {
			bloom_filter[0].clear();
			next_bloom_filter_reset_milestone = Simulator->Time() + bloom_filter_reset_step;
		}
	}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rsi, %r14
movq %rdi, %rbx
pushq $0x18
popq %rdi
callq 0x7370
movq %rax, 0x8(%rax)
movq %rax, (%rax)
movq %rax, 0x10(%rsp)
andq $0x0, 0x10(%rax)
leaq 0x70(%rsp), %rax
movq %rax, 0x8(%rax)
movq %rax, (%rax)
andq $0x0, 0x10(%rax)
leaq 0x40(%r14), %r12
movq %r14, 0x58(%rsp)
movq 0x40(%r14), %r14
xorl %r13d, %r13d
movq $0x0, 0x18(%rsp)
movq $0x0, 0x8(%rsp)
movq %r12, 0x60(%rsp)
movq 0x8(%rsp), %rax
movq 0x18(%rsp), %rcx
addl %ecx, %eax
addl 0xe0(%rbx), %eax
cmpq %r12, %r14
je 0x2bf4a
cmpl 0xdc(%rbx), %eax
jae 0x2bf4a
movq %r13, 0x20(%rsp)
movq 0x10(%r14), %r13
movq 0xc0(%rbx), %rdi
movzwl (%r13), %esi
movq 0x58(%r13), %rdx
callq 0x287ce
testb %al, %al
je 0x2bdb7
movq 0xc0(%rbx), %rsi
movzwl (%r13), %edx
movq 0x58(%r13), %rcx
leaq 0x28(%rsp), %rdi
callq 0x28822
movq 0x40(%rsp), %r8
movq 0xa0(%r13), %rax
cmpq %r8, %rax
jbe 0x2be7e
movq 0x80(%r13), %rcx
movq %rax, %r8
jmp 0x2be83
movq 0xc0(%rbx), %rdi
callq 0x288ba
testb %al, %al
jne 0x2be52
movq 0xc0(%rbx), %rsi
leaq 0x28(%rsp), %rdi
callq 0x28994
cmpl $0x2, 0x48(%rsp)
jne 0x2be52
movl $0xb0, %edi
callq 0x7370
movq %rax, %r15
movzwl (%r13), %ebp
movq 0x28(%rsp), %rdi
callq 0x2661d
shll $0x9, %eax
movq 0x30(%rsp), %r8
movq %r15, %rdi
pushq $0x1
popq %rsi
movl %ebp, %edx
movl %eax, %ecx
xorl %r9d, %r9d
pushq 0x40(%rsp)
pushq 0x30(%rsp)
pushq 0x48(%rsp)
pushq $0x0
callq 0x3a310
addq $0x20, %rsp
movq %r15, 0x68(%rsp)
movq 0x10(%rsp), %rdi
leaq 0x68(%rsp), %rsi
callq 0x2ab40
movq 0x28(%rsp), %rdi
callq 0x2661d
addl 0x8(%rsp), %eax
movq %rax, 0x8(%rsp)
movq 0xc0(%rbx), %rdi
movzwl (%r13), %esi
movq 0x58(%r13), %rdx
movq 0x80(%r13), %rcx
movq 0xa0(%r13), %r8
movq 0x98(%r13), %r9
callq 0x28b60
jmp 0x2bea4
movq 0x38(%rsp), %rcx
movq 0xc0(%rbx), %rdi
movzwl (%r13), %esi
movq 0x58(%r13), %rdx
movq 0x28(%rsp), %r9
orq 0x98(%r13), %r9
callq 0x28c6e
leaq 0x58(%r13), %r15
movq 0x98(%r13), %rdi
callq 0x2661d
movl %eax, %r12d
movq 0xe8(%rbx), %rdi
movq %r15, %rsi
callq 0x275aa
movq 0xe8(%rbx), %rcx
addq $0x8, %rcx
cmpq %rcx, %rax
jne 0x2bf27
movq 0xc0(%rbx), %rdi
movzwl (%r13), %esi
movq 0x58(%r13), %rdx
callq 0x28a0c
movq 0x98(%r13), %rdi
callq 0x2661d
movl %eax, %ebp
movq 0xe8(%rbx), %rdi
movq %r15, %rsi
callq 0x1c49c
movq %r13, 0x28(%rsp)
leaq 0x70(%rsp), %rdi
leaq 0x28(%rsp), %rsi
callq 0x2ab40
addl 0x18(%rsp), %ebp
movl %ebp, %eax
movq %rax, 0x18(%rsp)
movq 0x20(%rsp), %r13
addl %r12d, %r13d
movq (%r14), %r15
movq 0x60(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
callq 0x2ab26
movq %r15, %r14
jmp 0x2bd30
movq 0x58(%rsp), %r14
addl %r13d, 0x58(%r14)
movl %eax, 0xe0(%rbx)
movq 0x10(%rsp), %rax
cmpq $0x0, 0x10(%rax)
je 0x2bf98
pushq $0x18
popq %rdi
callq 0x7370
movq 0x8(%rsp), %rcx
shll $0x9, %ecx
movl %ecx, (%rax)
movq 0x10(%rsp), %rcx
movq %rcx, 0x8(%rax)
andl $0x0, 0x10(%rax)
movzwl 0x68(%r14), %ecx
movw %cx, 0x14(%rax)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x2bc20
testl %r13d, %r13d
je 0x2bfcb
pushq $0x18
popq %rdi
callq 0x7370
shll $0x9, %r13d
movl %r13d, (%rax)
movq %r14, 0x8(%rax)
movl $0x3, 0x10(%rax)
movzwl 0x68(%r14), %ecx
movw %cx, 0x14(%rax)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x2bc20
cmpq $0x0, 0x80(%rsp)
je 0x2bfe9
movq 0x38(%rbx), %rax
movq 0x38(%rax), %rdi
movq (%rdi), %rax
leaq 0x70(%rsp), %rsi
callq *0x60(%rax)
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
cmpq 0xf8(%rbx), %rax
jbe 0x2c026
movq 0xe8(%rbx), %rdi
callq 0x2b1e0
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
addq 0xf0(%rbx), %rax
movq %rax, 0xf8(%rbx)
leaq 0x70(%rsp), %rdi
callq 0x2adc4
addq $0x88, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
jmp 0x2c061
jmp 0x2c061
jmp 0x2c061
movq %rax, %rbx
movq %r15, %rdi
callq 0x7340
jmp 0x2c064
jmp 0x2c061
jmp 0x2c061
jmp 0x2c061
jmp 0x2c061
jmp 0x2c061
jmp 0x2c061
movq %rax, %rbx
leaq 0x70(%rsp), %rdi
callq 0x2adc4
movq %rbx, %rdi
callq 0x75d0