// File: /workspace/github_cpp_makefile_star2_O3/CMU-SAFARI[P]MQSim/src/ssd/TSU_OutofOrder.cpp
// Function: SSD_Components::TSU_OutOfOrder::Schedule()
void TSU_OutOfOrder::Schedule()
{
	opened_scheduling_reqs--;
	if (opened_scheduling_reqs > 0)
	{
		return;
	}

	if (opened_scheduling_reqs < 0)
	{
		PRINT_ERROR("TSU_OutOfOrder: Illegal status!");
	}

	if (transaction_receive_slots.size() == 0)
	{
		return;
	}

	for (std::list<NVM_Transaction_Flash *>::iterator it = transaction_receive_slots.begin(); it != transaction_receive_slots.end(); it++)
	{
		switch ((*it)->Type)
		{
		case Transaction_Type::READ:
			switch ((*it)->Source)
			{
			case Transaction_Source_Type::CACHE:
			case Transaction_Source_Type::USERIO:
				UserReadTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
				break;
			case Transaction_Source_Type::MAPPING:
				MappingReadTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
				break;
			case Transaction_Source_Type::GC_WL:
				GCReadTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
				break;
			default:
				PRINT_ERROR("TSU_OutOfOrder: unknown source type for a read transaction!")
			}
			break;
		case Transaction_Type::WRITE:
			switch ((*it)->Source)
			{
			case Transaction_Source_Type::CACHE:
			case Transaction_Source_Type::USERIO:
				UserWriteTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
				break;
			case Transaction_Source_Type::MAPPING:
				MappingWriteTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
				break;
			case Transaction_Source_Type::GC_WL:
				GCWriteTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
				break;
			default:
				PRINT_ERROR("TSU_OutOfOrder: unknown source type for a write transaction!")
			}
			break;
		case Transaction_Type::ERASE:
			GCEraseTRQueue[(*it)->Address.ChannelID][(*it)->Address.ChipID].push_back((*it));
			break;
		default:
			break;
		}
	}

	for (flash_channel_ID_type channelID = 0; channelID < channel_count; channelID++)
	{
		if (_NVMController->Get_channel_status(channelID) == BusChannelStatus::IDLE)
		{
			for (unsigned int i = 0; i < chip_no_per_channel; i++)
			{
				NVM::FlashMemory::Flash_Chip *chip = _NVMController->Get_chip(channelID, Round_robin_turn_of_channel[channelID]);
				//The TSU does not check if the chip is idle or not since it is possible to suspend a busy chip and issue a new command
				process_chip_requests(chip);
				Round_robin_turn_of_channel[channelID] = (flash_chip_ID_type)(Round_robin_turn_of_channel[channelID] + 1) % chip_no_per_channel;
				if (_NVMController->Get_channel_status(chip->ChannelID) != BusChannelStatus::IDLE)
				{
					break;
				}
			}
		}
	}
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movl 0xa8(%rdi), %eax
leal -0x1(%rax), %ecx
movl %ecx, 0xa8(%rdi)
cmpl $0x1, %eax
jg 0x4d5bb
jne 0x4d5ca
movq %rdi, %rbx
cmpq $0x0, 0x88(%rdi)
je 0x4d5bb
leaq 0x78(%rbx), %r14
movq (%r14), %r15
cmpq %r14, %r15
je 0x4d52e
leaq 0xd0(%rbx), %r12
leaq 0xc8(%rbx), %rax
movq %rax, 0x20(%rsp)
leaq 0xe0(%rbx), %rax
movq %rax, 0x10(%rsp)
leaq 0xb8(%rbx), %rbp
leaq 0xc0(%rbx), %rax
movq %rax, 0x18(%rsp)
leaq 0xd8(%rbx), %rax
movq %rax, 0x8(%rsp)
leaq 0xb0(%rbx), %r13
movq 0x10(%r15), %rax
movl 0x8(%rax), %edx
movq %r12, %rcx
cmpl $0x2, %edx
je 0x4d501
cmpl $0x1, %edx
je 0x4d4e1
testl %edx, %edx
jne 0x4d522
movl 0x4(%rax), %edx
movq %r13, %rcx
cmpl $0x2, %edx
jb 0x4d501
movq 0x18(%rsp), %rcx
je 0x4d501
movq 0x8(%rsp), %rcx
cmpl $0x3, %edx
je 0x4d501
jmp 0x4d5e9
movl 0x4(%rax), %edx
movq %rbp, %rcx
cmpl $0x2, %edx
jb 0x4d501
movq 0x20(%rsp), %rcx
je 0x4d501
movq 0x10(%rsp), %rcx
cmpl $0x3, %edx
jne 0x4d608
leaq 0x10(%r15), %rsi
movq (%rcx), %rcx
movl 0x38(%rax), %edx
movl 0x3c(%rax), %eax
movq %rax, %rdi
shlq $0x8, %rdi
leaq (%rdi,%rax,8), %rdi
addq (%rcx,%rdx,8), %rdi
callq 0x3df04
movq (%r15), %r15
cmpq %r14, %r15
jne 0x4d4a8
cmpl $0x0, 0x44(%rbx)
je 0x4d5bb
xorl %r14d, %r14d
movq 0x38(%rbx), %rdi
movq (%rdi), %rax
movl %r14d, %esi
callq *0x28(%rax)
cmpl $0x1, %eax
jne 0x4d5b0
cmpl $0x0, 0x48(%rbx)
je 0x4d5b0
movl $0x1, %r12d
movq 0x38(%rbx), %rdi
movq 0x70(%rbx), %rax
movl (%rax,%r14,4), %edx
movq (%rdi), %rax
movl %r14d, %esi
callq *0x30(%rax)
movq %rax, %r15
movq %rbx, %rdi
movq %rax, %rsi
callq 0x4aa06
movq 0x70(%rbx), %rcx
movl (%rcx,%r14,4), %eax
incl %eax
xorl %edx, %edx
divl 0x48(%rbx)
movl %edx, (%rcx,%r14,4)
movq 0x38(%rbx), %rdi
movl 0x2c(%r15), %esi
movq (%rdi), %rax
callq *0x28(%rax)
cmpl $0x1, %eax
jne 0x4d5b0
leal 0x1(%r12), %eax
cmpl 0x48(%rbx), %r12d
movl %eax, %r12d
jb 0x4d559
incq %r14
movl 0x44(%rbx), %eax
cmpq %rax, %r14
jb 0x4d53b
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0x21a1f(%rip), %rbx     # 0x6eff0
leaq 0x8fd0(%rip), %rsi      # 0x565a8
movq %rbx, %rdi
callq 0x7390
leaq 0xd157(%rip), %rsi      # 0x5a73e
jmp 0x4d625
movq 0x21a00(%rip), %rbx     # 0x6eff0
leaq 0x8fb1(%rip), %rsi      # 0x565a8
movq %rbx, %rdi
callq 0x7390
leaq 0xd158(%rip), %rsi      # 0x5a75e
jmp 0x4d625
movq 0x219e1(%rip), %rbx     # 0x6eff0
leaq 0x8f92(%rip), %rsi      # 0x565a8
movq %rbx, %rdi
callq 0x7390
leaq 0xd175(%rip), %rsi      # 0x5a79a
movq %rbx, %rdi
callq 0x7390
movq %rax, %rdi
callq 0x71c0
movq 0x21994(%rip), %rdi     # 0x6efd0
callq 0x7430
movl $0x1, %edi
callq 0x7440
nop