// File: NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE*)
void DRC_MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE *queue)
{
    for (uint32_t i=0; i<queue->SIZE; i++) {
        if (queue->entry[i].scheduled) {

            uint64_t op_addr = queue->entry[i].address;
            uint32_t op_cpu = queue->entry[i].cpu,
                     op_channel = drc_get_channel(op_addr), 
                     op_rank = drc_get_rank(op_addr), 
                     op_bank = drc_get_bank(op_addr), 
                     op_row = drc_get_row(op_addr);

#ifdef DEBUG_PRINT
            //uint32_t op_column = drc_get_column(op_addr);
#endif

            // update open row
            if ((bank_request[op_channel][op_rank][op_bank].cycle_available - tCAS) <= current_core_cycle[op_cpu])
                bank_request[op_channel][op_rank][op_bank].open_row = op_row;
            else
                bank_request[op_channel][op_rank][op_bank].open_row = UINT32_MAX;

            // this bank is ready for another DRC request
            bank_request[op_channel][op_rank][op_bank].request_index = -1;
            bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0;
            bank_request[op_channel][op_rank][op_bank].working = 0;
            bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu];
            if (bank_request[op_channel][op_rank][op_bank].is_write) {
                scheduled_writes--;
                bank_request[op_channel][op_rank][op_bank].is_write = 0;
            }
            else if (bank_request[op_channel][op_rank][op_bank].is_read) {
                scheduled_reads--;
                bank_request[op_channel][op_rank][op_bank].is_read = 0;
            }

            queue->entry[i].scheduled = 0;
            queue->entry[i].event_cycle = current_core_cycle[op_cpu];

            DP ( if (warmup_complete[op_cpu]) {
            cout << queue->NAME << " instr_id: " << queue->entry[i].instr_id << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads << endl; });

        }
    }
    
    update_schedule_cycle(&RQ);
    update_schedule_cycle(&WQ);
    update_process_cycle(&RQ);
    update_process_cycle(&WQ);

#ifdef SANITY_CHECK
    if (queue->is_WQ) {
        if (scheduled_writes != 0)
            assert(0);
    }
    else {
        if (scheduled_reads != 0)
            assert(0);
    }
#endif
}

// Assembly:
subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x8(%rsp)
movl $0x0, 0x34(%rsp)
movl 0x34(%rsp), %eax
movq 0x38(%rsp), %rcx
cmpl 0x20(%rcx), %eax
jae 0x1e56d
movq 0x38(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
cmpb $0x0, 0x2(%rax)
je 0x1e55b
movq 0x8(%rsp), %rdi
movq 0x38(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x28(%rsp)
movq 0x38(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movl 0x330(%rax), %eax
movl %eax, 0x24(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e630
movq 0x8(%rsp), %rdi
movl %eax, 0x20(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e660
movq 0x8(%rsp), %rdi
movl %eax, 0x1c(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e690
movq 0x8(%rsp), %rdi
movl %eax, 0x18(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e6c0
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x14(%rsp)
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x18(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
movq (%rax), %rax
leaq 0xcf82(%rip), %rcx      # 0x2b21c
movl (%rcx), %ecx
subq %rcx, %rax
movl 0x24(%rsp), %ecx
movl %ecx, %edx
leaq 0x71c14(%rip), %rcx     # 0x8fec0
cmpq (%rcx,%rdx,8), %rax
ja 0x1e2ed
movq 0x8(%rsp), %rax
movl 0x14(%rsp), %ecx
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rax
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rax
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rax
movl %ecx, 0x18(%rax)
jmp 0x1e326
movq 0x8(%rsp), %rax
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x18(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
movl $0xffffffff, 0x18(%rax) # imm = 0xFFFFFFFF
movq 0x8(%rsp), %rax
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movl $0xffffffff, 0x24(%rcx) # imm = 0xFFFFFFFF
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x0, 0x1e(%rcx)
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x0, 0x1c(%rcx)
movl 0x24(%rsp), %ecx
movl %ecx, %edx
leaq 0x71ae6(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %esi
imulq $0x500, %rsi, %rsi      # imm = 0x500
addq %rsi, %rcx
movl 0x1c(%rsp), %esi
imulq $0x280, %rsi, %rsi      # imm = 0x280
addq %rsi, %rcx
movl 0x18(%rsp), %esi
imulq $0x28, %rsi, %rsi
addq %rsi, %rcx
movq %rdx, (%rcx)
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x18(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
cmpb $0x0, 0x20(%rax)
je 0x1e48c
movq 0x8(%rsp), %rax
movl 0x409468(%rax), %ecx
addl $-0x1, %ecx
movl %ecx, 0x409468(%rax)
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x18(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
movb $0x0, 0x20(%rax)
jmp 0x1e50b
movq 0x8(%rsp), %rax
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x18(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
cmpb $0x0, 0x21(%rax)
je 0x1e509
movq 0x8(%rsp), %rax
movl 0x409464(%rax), %ecx
addl $-0x1, %ecx
movl %ecx, 0x409464(%rax)
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x18(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
movb $0x0, 0x21(%rax)
jmp 0x1e50b
movq 0x38(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x34(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movb $0x0, 0x2(%rax)
movl 0x24(%rsp), %eax
movl %eax, %ecx
leaq 0x7198a(%rip), %rax     # 0x8fec0
movq (%rax,%rcx,8), %rcx
movq 0x38(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x34(%rsp), %edx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movq %rcx, 0x378(%rax)
jmp 0x1e55d
movl 0x34(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x34(%rsp)
jmp 0x1e190
movq 0x8(%rsp), %rdi
movq %rdi, %rsi
addq $0x40c510, %rsi         # imm = 0x40C510
callq 0x1e6f0
movq 0x8(%rsp), %rdi
movq %rdi, %rsi
addq $0x40a870, %rsi         # imm = 0x40A870
callq 0x1e6f0
movq 0x8(%rsp), %rdi
movq %rdi, %rsi
addq $0x40c510, %rsi         # imm = 0x40C510
callq 0x1e810
movq 0x8(%rsp), %rdi
movq %rdi, %rsi
addq $0x40a870, %rsi         # imm = 0x40A870
callq 0x1e810
movq 0x38(%rsp), %rax
cmpb $0x0, 0x25(%rax)
je 0x1e5f7
movq 0x8(%rsp), %rax
cmpl $0x0, 0x409468(%rax)
je 0x1e5f5
leaq 0x4a27(%rip), %rdi      # 0x23004
leaq 0x598b(%rip), %rsi      # 0x23f6f
movl $0x3d, %edx
leaq 0x5995(%rip), %rcx      # 0x23f85
callq 0x3160
jmp 0x1e626
movq 0x8(%rsp), %rax
cmpl $0x0, 0x409464(%rax)
je 0x1e624
leaq 0x49f8(%rip), %rdi      # 0x23004
leaq 0x595c(%rip), %rsi      # 0x23f6f
movl $0x41, %edx
leaq 0x5966(%rip), %rcx      # 0x23f85
callq 0x3160
jmp 0x1e626
addq $0x48, %rsp
retq
nopl (%rax,%rax)