// File: Sooryakiran[P]dotV/src/verilog.cpp
// Function: Chip::auto_gen(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
string Chip::auto_gen(string head){
    /*------------------------------------------------------------------------------------------
    Automatically generates the chip module header definition

    Param : head (string), a module name.
    Returns : head_def

    Example if head = "module MY_CHIP"
    ------------------------------------------------------------------------------------------*/

    string head_def = head + " (";

    /*------------------------------------------------------------------------------------------
    head_def will be "module MY_CHIP("

    The next stage checks for any input declarations and head def will be appended
    ------------------------------------------------------------------------------------------*/

    for(vector<string>::iterator i = this->input_names.begin(); i != this->input_names.end(); i++){
        if(i!=this->input_names.begin()){
            head_def += ", ";
        }
        string input = *i;
        head_def += wire_name(input);
    }

    /*------------------------------------------------------------------------------------------
    The next stage checks for any output declarations and head def will be appended
    ------------------------------------------------------------------------------------------*/
    for(vector<string>::iterator i = this->output_names.begin(); i != this->output_names.end(); i++){
        string input = *i;
        head_def += ", " + wire_name(input);
    }
    head_def += ");";

    /*------------------------------------------------------------------------------------------
    At this stage head_def will be "module MY_CHIP(my_input_1, my_input_2, my_output);"
    ------------------------------------------------------------------------------------------*/

    // string pre = "";
    // if(this->n_bits > 1){
    //     pre = "[" + to_string(this->n_bits -1) + ": 0] ";
    // } 
    
    head_def += "\n\t// Transistor count : " + to_string(this->num_transistors()) + "\n";
    /*------------------------------------------------------------------------------------------
    In the next stage we again write these inputs and outputs inside the module. We also checked
    for the bit width to make appropriate declarations.
    ------------------------------------------------------------------------------------------*/
    head_def += "\n\t// Inputs\n\n";

    for(int i=0; i < this->input_names.size(); i++){
        if(this->is_input_reg.at(i))
            head_def += "\tinput reg "  + this->input_names.at(i) + ";\n";
        else
            head_def += "\tinput "  + this->input_names.at(i) + ";\n";
    }

    head_def += "\n\t// Outputs\n\n";
    for(int i=0; i < this->output_names.size(); i++){
        if(this->is_output_reg.at(i))
            head_def += "\toutput reg "  + this->output_names.at(i) + ";\n";
        else
            head_def += "\toutput "  + this->output_names.at(i) + ";\n";
    }

    /*------------------------------------------------------------------------------------------
    At this stage head_def will be assuming 8 bit width
    """
    module MY_CHIP(my_input_1, my_input_2, my_output);
        // Inputs
        input [7:0] my_input_1;
        input [7:0] my_input_2;
        // Outputs
        output [7:0] my_output;
    """
    ------------------------------------------------------------------------------------------*/

    /*------------------------------------------------------------------------------------------
    Now we add any wires and reg declared.
    ------------------------------------------------------------------------------------------*/
    head_def += "\n\t// Wires\n\n";
    for(vector<string>::iterator i = this->wires.begin(); i != this->wires.end(); i++){
        head_def += "\twire " + *i + ";\n";
    }

    head_def += "\n\t// Regs\n\n";
    for(vector<string>::iterator i = this->regs.begin(); i != this->regs.end(); i++){
        head_def += "\treg " + *i + ";\n";
    }

    /*------------------------------------------------------------------------------------------
    Embed any verilog codes.
    ------------------------------------------------------------------------------------------*/
    head_def += "\n\t// Extras\n\n";
    for(vector<string>::iterator i = this->extras.begin(); i != this->extras.end(); i++){
        head_def += "\t"+ *i + "\n";
    }

    /*------------------------------------------------------------------------------------------
    At this stage head_def will be something like
    """
    module MY_CHIP(my_input_1, my_input_2, my_output);
        // Inputs
        input [7:0] my_input_1;
        input [7:0] my_input_2;

        // Outputs
        output [7:0] my_output;

        // Wires
        wire my_wire_1;
        wire my_wire_2;
        wire [7:0] my_wide_wire;

        // Extras
        assign my_wire_1 = 0;

    """
    ------------------------------------------------------------------------------------------*/

    /*------------------------------------------------------------------------------------------
    Now add submodule instances.
    ------------------------------------------------------------------------------------------*/

    head_def += "\n\t// Sub Modules\n\n";
    for(vector<Chip>::iterator i = this->submodules.begin(); i != this->submodules.end(); i++){
        head_def += "\t" + i->generate + "\n";
    }

    /*------------------------------------------------------------------------------------------
    Now we add the behaviours specified
    ------------------------------------------------------------------------------------------*/

    head_def += "\n\t// Behaviours\n\n";
    for(vector<BehaviourModel>::iterator i = this->behaviours.begin(); i != this->behaviours.end(); i++){
        string code = i->code();
        size_t index = 0;
        while(string::npos != (index = code.find('\n', index))){
            code.replace(index, 1, "\n\t");
            index +=2;
        }
        

        head_def += "\t" + code + "\n";
    }

    head_def += "\nendmodule\n";

    /*------------------------------------------------------------------------------------------
    At this stage head_def will be something like
    """
    module MY_CHIP(my_input_1, my_input_2, my_output);
        // Inputs
        input [7:0] my_input_1;
        input [7:0] my_input_2;

        // Outputs
        output [7:0] my_output;

        // Wires
        wire my_wire_1;
        wire my_wire_2;
        wire [7:0] my_wide_wire;

        // Regs
        reg a;

        // Extras
        assign my_wire_1 = 0;

        // Submodules
        AND_GATE my_and_1(my_input_1[0], my_input_2[0], my_wire_1);
        ...

        // Behaviours
        
        always @(posedge my_input_1);
        begin;
            a <= ~my_input_2;
        end;

        ...

    endmodule
    """
    ------------------------------------------------------------------------------------------*/
    return head_def;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0x530, %rsp            # imm = 0x530
movq %rdx, -0x4d8(%rbp)
movq %rsi, %rax
movq -0x4d8(%rbp), %rsi
movq %rdi, -0x4d0(%rbp)
movq %rdi, %rcx
movq %rcx, -0x4c8(%rbp)
movq %rdi, -0x8(%rbp)
movq %rax, -0x10(%rbp)
movq %rsi, -0x18(%rbp)
movq -0x10(%rbp), %rax
movq %rax, -0x4c0(%rbp)
movb $0x0, -0x19(%rbp)
leaq 0x27fce(%rip), %rdx     # 0x4704d
callq 0x1ce60
movq -0x4c0(%rbp), %rdi
addq $0xe0, %rdi
callq 0x1d760
movq %rax, -0x28(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0xe0, %rdi
callq 0x1d800
movq %rax, -0x30(%rbp)
leaq -0x28(%rbp), %rdi
leaq -0x30(%rbp), %rsi
callq 0x1cf30
testb $0x1, %al
jne 0x1f0c8
jmp 0x1f1f3
movq -0x4c0(%rbp), %rdi
addq $0xe0, %rdi
callq 0x1d760
movq %rax, -0x38(%rbp)
leaq -0x28(%rbp), %rdi
leaq -0x38(%rbp), %rsi
callq 0x1cf30
testb $0x1, %al
jne 0x1f0f2
jmp 0x1f11a
movq -0x4d0(%rbp), %rdi
leaq 0x27f50(%rip), %rsi     # 0x47050
callq 0x1c730
jmp 0x1f107
jmp 0x1f11a
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1ff92
leaq -0x28(%rbp), %rdi
callq 0x1ddc0
movq %rax, %rsi
leaq -0x68(%rbp), %rdi
callq 0x1ba40
jmp 0x1f131
leaq -0xa8(%rbp), %rdi
leaq -0x68(%rbp), %rsi
callq 0x1ba40
jmp 0x1f143
leaq -0x88(%rbp), %rdi
leaq -0xa8(%rbp), %rsi
callq 0x1c3a0
jmp 0x1f158
movq -0x4d0(%rbp), %rdi
leaq -0x88(%rbp), %rsi
callq 0x1ce20
jmp 0x1f16d
leaq -0x88(%rbp), %rdi
callq 0x1bea0
leaq -0xa8(%rbp), %rdi
callq 0x1bea0
leaq -0x68(%rbp), %rdi
callq 0x1bea0
leaq -0x28(%rbp), %rdi
xorl %esi, %esi
callq 0x1b860
movq %rax, -0xb0(%rbp)
jmp 0x1f09b
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f1e5
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f1d9
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x88(%rbp), %rdi
callq 0x1bea0
leaq -0xa8(%rbp), %rdi
callq 0x1bea0
leaq -0x68(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4c0(%rbp), %rdi
addq $0x120, %rdi            # imm = 0x120
callq 0x1d760
movq %rax, -0xb8(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0x120, %rdi            # imm = 0x120
callq 0x1d800
movq %rax, -0xc0(%rbp)
leaq -0xb8(%rbp), %rdi
leaq -0xc0(%rbp), %rsi
callq 0x1cf30
testb $0x1, %al
jne 0x1f243
jmp 0x1f370
leaq -0xb8(%rbp), %rdi
callq 0x1ddc0
movq %rax, %rsi
leaq -0xe0(%rbp), %rdi
callq 0x1ba40
jmp 0x1f260
leaq -0x140(%rbp), %rdi
leaq -0xe0(%rbp), %rsi
callq 0x1ba40
jmp 0x1f275
leaq -0x120(%rbp), %rdi
leaq -0x140(%rbp), %rsi
callq 0x1c3a0
jmp 0x1f28a
leaq 0x27dbf(%rip), %rsi     # 0x47050
leaq -0x100(%rbp), %rdi
leaq -0x120(%rbp), %rdx
callq 0x1d820
jmp 0x1f2a6
movq -0x4d0(%rbp), %rdi
leaq -0x100(%rbp), %rsi
callq 0x1ce20
jmp 0x1f2bb
leaq -0x100(%rbp), %rdi
callq 0x1bea0
leaq -0x120(%rbp), %rdi
callq 0x1bea0
leaq -0x140(%rbp), %rdi
callq 0x1bea0
leaq -0xe0(%rbp), %rdi
callq 0x1bea0
leaq -0xb8(%rbp), %rdi
xorl %esi, %esi
callq 0x1b860
movq %rax, -0x148(%rbp)
jmp 0x1f20d
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f35f
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f353
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f347
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x100(%rbp), %rdi
callq 0x1bea0
leaq -0x120(%rbp), %rdi
callq 0x1bea0
leaq -0x140(%rbp), %rdi
callq 0x1bea0
leaq -0xe0(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4d0(%rbp), %rdi
leaq 0x28373(%rip), %rsi     # 0x476f1
callq 0x1c730
jmp 0x1f385
movq -0x4c0(%rbp), %rdi
callq 0x1c8c0
movl %eax, -0x4dc(%rbp)
jmp 0x1f399
movl -0x4dc(%rbp), %esi
leaq -0x1a8(%rbp), %rdi
callq 0x1ced0
jmp 0x1f3ad
leaq 0x27c9f(%rip), %rsi     # 0x47053
leaq -0x188(%rbp), %rdi
leaq -0x1a8(%rbp), %rdx
callq 0x1d820
jmp 0x1f3c9
leaq 0x27d18(%rip), %rdx     # 0x470e8
leaq -0x168(%rbp), %rdi
leaq -0x188(%rbp), %rsi
callq 0x1b430
jmp 0x1f3e5
movq -0x4d0(%rbp), %rdi
leaq -0x168(%rbp), %rsi
callq 0x1ce20
jmp 0x1f3fa
leaq -0x168(%rbp), %rdi
callq 0x1bea0
leaq -0x188(%rbp), %rdi
callq 0x1bea0
leaq -0x1a8(%rbp), %rdi
callq 0x1bea0
movq -0x4d0(%rbp), %rdi
leaq 0x27c40(%rip), %rsi     # 0x4706c
callq 0x1c730
jmp 0x1f433
movl $0x0, -0x1ac(%rbp)
movq -0x4c0(%rbp), %rdi
movslq -0x1ac(%rbp), %rax
movq %rax, -0x4e8(%rbp)
addq $0xe0, %rdi
callq 0x1dbe0
movq %rax, %rcx
movq -0x4e8(%rbp), %rax
cmpq %rcx, %rax
jae 0x1f6b8
movq -0x4c0(%rbp), %rdi
addq $0xf8, %rdi
movslq -0x1ac(%rbp), %rsi
callq 0x1df00
movq %rdx, -0x4f8(%rbp)
movq %rax, -0x4f0(%rbp)
jmp 0x1f49b
movq -0x4f8(%rbp), %rax
movq -0x4f0(%rbp), %rcx
movq %rcx, -0x1c0(%rbp)
movq %rax, -0x1b8(%rbp)
leaq -0x1c0(%rbp), %rdi
callq 0x1b3f0
testb $0x1, %al
jne 0x1f4cc
jmp 0x1f5e1
movq -0x4c0(%rbp), %rdi
addq $0xe0, %rdi
movslq -0x1ac(%rbp), %rsi
callq 0x1b640
movq %rax, -0x500(%rbp)
jmp 0x1f4ef
movq -0x500(%rbp), %rdx
leaq 0x27b7d(%rip), %rsi     # 0x4707a
leaq -0x200(%rbp), %rdi
callq 0x1c5a0
jmp 0x1f50b
leaq 0x27b74(%rip), %rdx     # 0x47086
leaq -0x1e0(%rbp), %rdi
leaq -0x200(%rbp), %rsi
callq 0x1b430
jmp 0x1f527
movq -0x4d0(%rbp), %rdi
leaq -0x1e0(%rbp), %rsi
callq 0x1ce20
jmp 0x1f53c
leaq -0x1e0(%rbp), %rdi
callq 0x1bea0
leaq -0x200(%rbp), %rdi
callq 0x1bea0
jmp 0x1f6a2
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f599
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f58d
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x168(%rbp), %rdi
callq 0x1bea0
leaq -0x188(%rbp), %rdi
callq 0x1bea0
leaq -0x1a8(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f5d0
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x1e0(%rbp), %rdi
callq 0x1bea0
leaq -0x200(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4c0(%rbp), %rdi
addq $0xe0, %rdi
movslq -0x1ac(%rbp), %rsi
callq 0x1b640
movq %rax, -0x508(%rbp)
jmp 0x1f604
movq -0x508(%rbp), %rdx
leaq 0x27a77(%rip), %rsi     # 0x47089
leaq -0x240(%rbp), %rdi
callq 0x1c5a0
jmp 0x1f620
leaq 0x27a5f(%rip), %rdx     # 0x47086
leaq -0x220(%rbp), %rdi
leaq -0x240(%rbp), %rsi
callq 0x1b430
jmp 0x1f63c
movq -0x4d0(%rbp), %rdi
leaq -0x220(%rbp), %rsi
callq 0x1ce20
jmp 0x1f651
leaq -0x220(%rbp), %rdi
callq 0x1bea0
leaq -0x240(%rbp), %rdi
callq 0x1bea0
jmp 0x1f6a2
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f691
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x220(%rbp), %rdi
callq 0x1bea0
leaq -0x240(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
jmp 0x1f6a4
movl -0x1ac(%rbp), %eax
addl $0x1, %eax
movl %eax, -0x1ac(%rbp)
jmp 0x1f43d
movq -0x4d0(%rbp), %rdi
leaq 0x279cb(%rip), %rsi     # 0x47091
callq 0x1c730
jmp 0x1f6cd
movl $0x0, -0x244(%rbp)
movq -0x4c0(%rbp), %rdi
movslq -0x244(%rbp), %rax
movq %rax, -0x510(%rbp)
addq $0x120, %rdi            # imm = 0x120
callq 0x1dbe0
movq %rax, %rcx
movq -0x510(%rbp), %rax
cmpq %rcx, %rax
jae 0x1f901
movq -0x4c0(%rbp), %rdi
addq $0x138, %rdi            # imm = 0x138
movslq -0x244(%rbp), %rsi
callq 0x1df00
movq %rdx, -0x520(%rbp)
movq %rax, -0x518(%rbp)
jmp 0x1f735
movq -0x520(%rbp), %rax
movq -0x518(%rbp), %rcx
movq %rcx, -0x258(%rbp)
movq %rax, -0x250(%rbp)
leaq -0x258(%rbp), %rdi
callq 0x1b3f0
testb $0x1, %al
jne 0x1f766
jmp 0x1f82a
movq -0x4c0(%rbp), %rdi
addq $0x120, %rdi            # imm = 0x120
movslq -0x244(%rbp), %rsi
callq 0x1b640
movq %rax, -0x528(%rbp)
jmp 0x1f789
movq -0x528(%rbp), %rdx
leaq 0x27909(%rip), %rsi     # 0x470a0
leaq -0x298(%rbp), %rdi
callq 0x1c5a0
jmp 0x1f7a5
leaq 0x278da(%rip), %rdx     # 0x47086
leaq -0x278(%rbp), %rdi
leaq -0x298(%rbp), %rsi
callq 0x1b430
jmp 0x1f7c1
movq -0x4d0(%rbp), %rdi
leaq -0x278(%rbp), %rsi
callq 0x1ce20
jmp 0x1f7d6
leaq -0x278(%rbp), %rdi
callq 0x1bea0
leaq -0x298(%rbp), %rdi
callq 0x1bea0
jmp 0x1f8eb
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f819
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x278(%rbp), %rdi
callq 0x1bea0
leaq -0x298(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4c0(%rbp), %rdi
addq $0x120, %rdi            # imm = 0x120
movslq -0x244(%rbp), %rsi
callq 0x1b640
movq %rax, -0x530(%rbp)
jmp 0x1f84d
movq -0x530(%rbp), %rdx
leaq 0x27852(%rip), %rsi     # 0x470ad
leaq -0x2d8(%rbp), %rdi
callq 0x1c5a0
jmp 0x1f869
leaq 0x27816(%rip), %rdx     # 0x47086
leaq -0x2b8(%rbp), %rdi
leaq -0x2d8(%rbp), %rsi
callq 0x1b430
jmp 0x1f885
movq -0x4d0(%rbp), %rdi
leaq -0x2b8(%rbp), %rsi
callq 0x1ce20
jmp 0x1f89a
leaq -0x2b8(%rbp), %rdi
callq 0x1bea0
leaq -0x2d8(%rbp), %rdi
callq 0x1bea0
jmp 0x1f8eb
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1f8da
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x2b8(%rbp), %rdi
callq 0x1bea0
leaq -0x2d8(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
jmp 0x1f8ed
movl -0x244(%rbp), %eax
addl $0x1, %eax
movl %eax, -0x244(%rbp)
jmp 0x1f6d7
movq -0x4d0(%rbp), %rdi
leaq 0x277a7(%rip), %rsi     # 0x470b6
callq 0x1c730
jmp 0x1f916
movq -0x4c0(%rbp), %rdi
addq $0xb0, %rdi
callq 0x1d760
movq %rax, -0x2e0(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0xb0, %rdi
callq 0x1d800
movq %rax, -0x2e8(%rbp)
leaq -0x2e0(%rbp), %rdi
leaq -0x2e8(%rbp), %rsi
callq 0x1cf30
testb $0x1, %al
jne 0x1f966
jmp 0x1fa24
leaq -0x2e0(%rbp), %rdi
callq 0x1ddc0
movq %rax, %rdx
leaq 0x27747(%rip), %rsi     # 0x470c3
leaq -0x328(%rbp), %rdi
callq 0x1c5a0
jmp 0x1f98a
leaq 0x276f5(%rip), %rdx     # 0x47086
leaq -0x308(%rbp), %rdi
leaq -0x328(%rbp), %rsi
callq 0x1b430
jmp 0x1f9a6
movq -0x4d0(%rbp), %rdi
leaq -0x308(%rbp), %rsi
callq 0x1ce20
jmp 0x1f9bb
leaq -0x308(%rbp), %rdi
callq 0x1bea0
leaq -0x328(%rbp), %rdi
callq 0x1bea0
leaq -0x2e0(%rbp), %rdi
xorl %esi, %esi
callq 0x1b860
movq %rax, -0x330(%rbp)
jmp 0x1f930
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1fa13
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x308(%rbp), %rdi
callq 0x1bea0
leaq -0x328(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4d0(%rbp), %rdi
leaq 0x27698(%rip), %rsi     # 0x470ca
callq 0x1c730
jmp 0x1fa39
movq -0x4c0(%rbp), %rdi
addq $0x160, %rdi            # imm = 0x160
callq 0x1d760
movq %rax, -0x338(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0x160, %rdi            # imm = 0x160
callq 0x1d800
movq %rax, -0x340(%rbp)
leaq -0x338(%rbp), %rdi
leaq -0x340(%rbp), %rsi
callq 0x1cf30
testb $0x1, %al
jne 0x1fa89
jmp 0x1fb47
leaq -0x338(%rbp), %rdi
callq 0x1ddc0
movq %rax, %rdx
leaq 0x27637(%rip), %rsi     # 0x470d6
leaq -0x380(%rbp), %rdi
callq 0x1c5a0
jmp 0x1faad
leaq 0x275d2(%rip), %rdx     # 0x47086
leaq -0x360(%rbp), %rdi
leaq -0x380(%rbp), %rsi
callq 0x1b430
jmp 0x1fac9
movq -0x4d0(%rbp), %rdi
leaq -0x360(%rbp), %rsi
callq 0x1ce20
jmp 0x1fade
leaq -0x360(%rbp), %rdi
callq 0x1bea0
leaq -0x380(%rbp), %rdi
callq 0x1bea0
leaq -0x338(%rbp), %rdi
xorl %esi, %esi
callq 0x1b860
movq %rax, -0x388(%rbp)
jmp 0x1fa53
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1fb36
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x360(%rbp), %rdi
callq 0x1bea0
leaq -0x380(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4d0(%rbp), %rdi
leaq 0x27587(%rip), %rsi     # 0x470dc
callq 0x1c730
jmp 0x1fb5c
movq -0x4c0(%rbp), %rdi
addq $0xc8, %rdi
callq 0x1d760
movq %rax, -0x390(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0xc8, %rdi
callq 0x1d800
movq %rax, -0x398(%rbp)
leaq -0x390(%rbp), %rdi
leaq -0x398(%rbp), %rsi
callq 0x1cf30
testb $0x1, %al
jne 0x1fbac
jmp 0x1fc6a
leaq -0x390(%rbp), %rdi
callq 0x1ddc0
movq %rax, %rdx
leaq 0x2754e(%rip), %rsi     # 0x47110
leaq -0x3d8(%rbp), %rdi
callq 0x1c5a0
jmp 0x1fbd0
leaq 0x27511(%rip), %rdx     # 0x470e8
leaq -0x3b8(%rbp), %rdi
leaq -0x3d8(%rbp), %rsi
callq 0x1b430
jmp 0x1fbec
movq -0x4d0(%rbp), %rdi
leaq -0x3b8(%rbp), %rsi
callq 0x1ce20
jmp 0x1fc01
leaq -0x3b8(%rbp), %rdi
callq 0x1bea0
leaq -0x3d8(%rbp), %rdi
callq 0x1bea0
leaq -0x390(%rbp), %rdi
xorl %esi, %esi
callq 0x1b860
movq %rax, -0x3e0(%rbp)
jmp 0x1fb76
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1fc59
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x3b8(%rbp), %rdi
callq 0x1bea0
leaq -0x3d8(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4d0(%rbp), %rdi
leaq 0x27472(%rip), %rsi     # 0x470ea
callq 0x1c730
jmp 0x1fc7f
movq -0x4c0(%rbp), %rdi
addq $0x68, %rdi
callq 0x1bce0
movq %rax, -0x3e8(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0x68, %rdi
callq 0x1bbc0
movq %rax, -0x3f0(%rbp)
leaq -0x3e8(%rbp), %rdi
leaq -0x3f0(%rbp), %rsi
callq 0x1b7a0
testb $0x1, %al
jne 0x1fcc9
jmp 0x1fd8b
leaq -0x3e8(%rbp), %rdi
callq 0x1b2a0
movq %rax, %rdx
addq $0x40, %rdx
leaq 0x2742d(%rip), %rsi     # 0x47110
leaq -0x430(%rbp), %rdi
callq 0x1c5a0
jmp 0x1fcf1
leaq 0x273f0(%rip), %rdx     # 0x470e8
leaq -0x410(%rbp), %rdi
leaq -0x430(%rbp), %rsi
callq 0x1b430
jmp 0x1fd0d
movq -0x4d0(%rbp), %rdi
leaq -0x410(%rbp), %rsi
callq 0x1ce20
jmp 0x1fd22
leaq -0x410(%rbp), %rdi
callq 0x1bea0
leaq -0x430(%rbp), %rdi
callq 0x1bea0
leaq -0x3e8(%rbp), %rdi
xorl %esi, %esi
callq 0x1ba70
movq %rax, -0x438(%rbp)
jmp 0x1fc96
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1fd7a
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x410(%rbp), %rdi
callq 0x1bea0
leaq -0x430(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4d0(%rbp), %rdi
leaq 0x27364(%rip), %rsi     # 0x470fd
callq 0x1c730
jmp 0x1fda0
movq -0x4c0(%rbp), %rdi
addq $0x178, %rdi            # imm = 0x178
callq 0x1c710
movq %rax, -0x440(%rbp)
movq -0x4c0(%rbp), %rdi
addq $0x178, %rdi            # imm = 0x178
callq 0x1dc10
movq %rax, -0x448(%rbp)
leaq -0x440(%rbp), %rdi
leaq -0x448(%rbp), %rsi
callq 0x1bbe0
testb $0x1, %al
jne 0x1fdf0
jmp 0x1ff57
leaq -0x440(%rbp), %rdi
callq 0x1dbc0
movq %rax, %rsi
leaq -0x468(%rbp), %rdi
callq 0x1bff0
jmp 0x1fe0d
movq $0x0, -0x470(%rbp)
movq -0x470(%rbp), %rdx
leaq -0x468(%rbp), %rdi
movl $0xa, %esi
callq 0x1cec0
movq %rax, %rcx
movq %rcx, -0x470(%rbp)
movq $-0x1, %rax
cmpq %rcx, %rax
je 0x1fe8c
movq -0x470(%rbp), %rsi
leaq 0x272bb(%rip), %rcx     # 0x4710f
leaq -0x468(%rbp), %rdi
movl $0x1, %edx
callq 0x1be60
jmp 0x1fe67
movq -0x470(%rbp), %rax
addq $0x2, %rax
movq %rax, -0x470(%rbp)
jmp 0x1fe18
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1ff49
leaq 0x2727d(%rip), %rsi     # 0x47110
leaq -0x4b0(%rbp), %rdi
leaq -0x468(%rbp), %rdx
callq 0x1c5a0
jmp 0x1fea8
leaq 0x27239(%rip), %rdx     # 0x470e8
leaq -0x490(%rbp), %rdi
leaq -0x4b0(%rbp), %rsi
callq 0x1b430
jmp 0x1fec4
movq -0x4d0(%rbp), %rdi
leaq -0x490(%rbp), %rsi
callq 0x1ce20
jmp 0x1fed9
leaq -0x490(%rbp), %rdi
callq 0x1bea0
leaq -0x4b0(%rbp), %rdi
callq 0x1bea0
leaq -0x468(%rbp), %rdi
callq 0x1bea0
leaq -0x440(%rbp), %rdi
xorl %esi, %esi
callq 0x1c2c0
movq %rax, -0x4b8(%rbp)
jmp 0x1fdba
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
jmp 0x1ff3d
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x40(%rbp)
movl %eax, -0x44(%rbp)
leaq -0x490(%rbp), %rdi
callq 0x1bea0
leaq -0x4b0(%rbp), %rdi
callq 0x1bea0
leaq -0x468(%rbp), %rdi
callq 0x1bea0
jmp 0x1ff92
movq -0x4d0(%rbp), %rdi
leaq 0x271ad(%rip), %rsi     # 0x47112
callq 0x1c730
jmp 0x1ff6c
movb $0x1, -0x19(%rbp)
testb $0x1, -0x19(%rbp)
jne 0x1ff82
movq -0x4d0(%rbp), %rdi
callq 0x1bea0
movq -0x4c8(%rbp), %rax
addq $0x530, %rsp            # imm = 0x530
popq %rbp
retq
movq -0x4d0(%rbp), %rdi
callq 0x1bea0
movq -0x40(%rbp), %rdi
callq 0x1da60
nopw (%rax,%rax)