// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/ssd/TSU_OutofOrder.cpp
// Function: SSD_Components::TSU_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip*)
bool TSU_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip *chip)
{
	Flash_Transaction_Queue *sourceQueue1 = NULL, *sourceQueue2 = NULL;

	//If flash transactions related to GC are prioritzed (non-preemptive execution mode of GC), then GC queues are checked first
	if (ftl->GC_and_WL_Unit->GC_is_in_urgent_mode(chip))
	{
		if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
			if (UserWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
			{
				sourceQueue2 = &UserWriteTRQueue[chip->ChannelID][chip->ChipID];
			}
		}
		else if (GCEraseTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			return false;
		}
		else if (UserWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &UserWriteTRQueue[chip->ChannelID][chip->ChipID];
		}
		else
		{
			return false;
		}
	}
	else
	{
		//If GC is currently executed in the preemptive mode, then user IO transaction queues are checked first
		if (UserWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &UserWriteTRQueue[chip->ChannelID][chip->ChipID];
			if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
			{
				sourceQueue2 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
			}
		}
		else if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
		}
		else
		{
			return false;
		}
	}

	bool suspensionRequired = false;
	ChipStatus cs = _NVMController->GetChipStatus(chip);
	switch (cs)
	{
	case ChipStatus::IDLE:
		break;
	case ChipStatus::ERASING:
		if (!eraseSuspensionEnabled || _NVMController->HasSuspendedCommand(chip))
			return false;
		if (_NVMController->Expected_finish_time(chip) - Simulator->Time() < eraseReasonableSuspensionTimeForWrite)
			return false;
		suspensionRequired = true;
	default:
		return false;
	}

	issue_command_to_chip(sourceQueue1, sourceQueue2, Transaction_Type::WRITE, suspensionRequired);

	return true;
}

// Assembly:
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x30(%rdi), %rax
movq 0x48(%rax), %rdi
movq (%rdi), %rax
callq *0x20(%rax)
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
testb %al, %al
je 0x3da0a
movq 0xc8(%r14), %rax
movq (%rax,%rcx,8), %r15
imulq $0x108, %rdx, %rax      # imm = 0x108
cmpq $0x0, 0x18(%r15,%rax)
je 0x3da44
addq %rax, %r15
movq 0xb8(%r14), %rdx
jmp 0x3da2e
movq 0xb8(%r14), %rax
movq (%rax,%rcx,8), %r15
imulq $0x108, %rdx, %rax      # imm = 0x108
cmpq $0x0, 0x18(%r15,%rax)
je 0x3da60
addq %rax, %r15
movq 0xc8(%r14), %rdx
movq (%rdx,%rcx,8), %rcx
leaq (%rcx,%rax), %r12
movq 0x18(%rcx,%rax), %rax
testq %rax, %rax
cmoveq %rax, %r12
jmp 0x3da79
movq 0xd0(%r14), %rdx
movq (%rdx,%rcx,8), %rdx
cmpq $0x0, 0x18(%rdx,%rax)
jne 0x3dac1
movq 0xb8(%r14), %rdx
jmp 0x3da67
movq 0xc8(%r14), %rdx
movq (%rdx,%rcx,8), %r15
cmpq $0x0, 0x18(%r15,%rax)
je 0x3dac1
addq %rax, %r15
xorl %r12d, %r12d
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x48(%rax)
testl %eax, %eax
je 0x3dac5
cmpl $0x6, %eax
jne 0x3dac1
cmpb $0x1, 0x54(%r14)
jne 0x3dac1
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x40(%rax)
testb %al, %al
jne 0x3dac1
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x50(%rax)
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
xorl %eax, %eax
jmp 0x3dadb
pushq $0x1
popq %rcx
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
xorl %r8d, %r8d
callq 0x3c064
movb $0x1, %al
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop