// File: /workspace/github_cpp_makefile_star2_O2/pollow[P]MIPSClide/instruction.cpp
// Function: Instruction::compile()
unsigned int Instruction::compile() {
    unsigned long result = 0;
    if ( !opcode.count(command) ) {
        throw invalid_argument("No such command"); 
    }
    switch ( type ) {
        case 'R':
            result += opcode[command] << 26;
            if (reg_num == 1) {
                if ( !regs.count(reg1) ) {
                    throw invalid_argument("No such register"); 
                }
                if ( command == "mfhi" || command == "mflo" ) {
                    result += regs[reg1] << 11;
                } else {
                    result += regs[reg1] << 21;
                }
            } else if ( reg_num == 2 ) {
                if ( !(regs.count(reg1) && regs.count(reg2)) ) {
                    throw invalid_argument("No such register"); 
                }
                if(has_shamt) {
                    result += (regs[reg1] << 11) + (regs[reg2] << 16);
                    result += shamt << 6;
                } else if ( command == "jarl" ) {
                    result += (regs[reg1] << 21) + (regs[reg2] << 11);
                } else if ( command == "clo" || command == "clz" ) {
                    result += (regs[reg1] << 11) + (regs[reg2] << 21);
                } else {
                    result += (regs[reg1] << 21) + (regs[reg2] << 16);
                }
            } else {
                if ( !(regs.count(reg1) && regs.count(reg2) && regs.count(reg3)) ) {
                    throw invalid_argument("No such register"); 
                }
                result += (regs[reg1] << 11) + (regs[reg2] << 21) + (regs[reg3] << 16);
            }
            result += func[command];
            break;
        case 'I':
            result += opcode[command] << 26;
            if (reg_num == 1) {
                if (command == "lui") result += regs[reg1] << 16;
                else result += regs[reg1] << 21;
            }
            if (reg_num == 2) {
                if (command == "beq" || command == "bne") {
                    result += regs[reg2] << 16;
                    result += regs[reg1] << 21;
                } else {
                    result += regs[reg1] << 16;
                    result += regs[reg2] << 21;
                }
            }
            result += imm;
            break;
        case 'J':
            result += opcode[command] << 26;
            result += imm;
            break;
    }

    return result;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0x10f0c(%rip), %rdi     # 0x2a980
movq %rbx, %rsi
callq 0x1b0e0
testq %rax, %rax
je 0x19e61
movzbl 0x90(%rbx), %eax
cmpl $0x49, %eax
je 0x19b60
cmpl $0x4a, %eax
je 0x19b3c
xorl %r14d, %r14d
cmpl $0x52, %eax
jne 0x19e4f
leaq 0x10ecf(%rip), %rdi     # 0x2a980
movq %rbx, %rsi
callq 0x1b104
movl (%rax), %r13d
shll $0x1a, %r13d
movl 0x80(%rbx), %r15d
leaq 0x20(%rbx), %r14
leaq 0x1105e(%rip), %rdi     # 0x2ab30
movq %r14, %rsi
callq 0x1b0e0
cmpl $0x2, %r15d
je 0x19bea
cmpl $0x1, %r15d
jne 0x19c65
testq %rax, %rax
je 0x19ec9
leaq 0x3846(%rip), %rsi      # 0x1d344
movq %rbx, %rdi
callq 0xbdb1
testb %al, %al
jne 0x19b21
leaq 0x3838(%rip), %rsi      # 0x1d349
movq %rbx, %rdi
callq 0xbdb1
testb %al, %al
je 0x19d9f
leaq 0x11008(%rip), %rdi     # 0x2ab30
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r14d
shll $0xb, %r14d
jmp 0x19db5
leaq 0x10e3d(%rip), %rdi     # 0x2a980
movq %rbx, %rsi
callq 0x1b104
movl (%rax), %eax
shll $0x1a, %eax
movzwl 0x88(%rbx), %r14d
orl %eax, %r14d
jmp 0x19e4f
leaq 0x10e19(%rip), %rdi     # 0x2a980
movq %rbx, %rsi
callq 0x1b104
movl (%rax), %r12d
shll $0x1a, %r12d
movl 0x80(%rbx), %eax
cmpl $0x1, %eax
jne 0x19bbe
leaq 0x37f2(%rip), %rsi      # 0x1d37a
movq %rbx, %rdi
callq 0xbdb1
movl %eax, %r14d
leaq 0x20(%rbx), %rsi
leaq 0x10f92(%rip), %rdi     # 0x2ab30
callq 0x1b104
movl (%rax), %eax
xorl %ecx, %ecx
testb %r14b, %r14b
sete %cl
leal (%rcx,%rcx,4), %ecx
orl $0x10, %ecx
shll %cl, %eax
addl %eax, %r12d
movl 0x80(%rbx), %eax
cmpl $0x2, %eax
jne 0x19d4e
leaq 0x3726(%rip), %rsi      # 0x1d2f4
movq %rbx, %rdi
callq 0xbdb1
testb %al, %al
je 0x19cf1
pushq $0x20
popq %r14
pushq $0x40
popq %rsi
jmp 0x19d1a
testq %rax, %rax
je 0x19ead
leaq 0x40(%rbx), %r15
leaq 0x10f32(%rip), %rdi     # 0x2ab30
movq %r15, %rsi
callq 0x1b0e0
testq %rax, %rax
je 0x19ead
cmpb $0x1, 0x91(%rbx)
jne 0x19d5e
leaq 0x10f0d(%rip), %r12     # 0x2ab30
movq %r12, %rdi
movq %r14, %rsi
callq 0x1b104
movl %r13d, %r14d
movl (%rax), %r13d
shll $0xb, %r13d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1b104
movl (%rax), %eax
shll $0x10, %eax
addl %r14d, %r13d
addl %eax, %r13d
movl 0x86(%rbx), %r14d
andl $0x1f, %r14d
shll $0x6, %r14d
orl %r13d, %r14d
jmp 0x19e3d
movl %r13d, -0x2c(%rbp)
testq %rax, %rax
je 0x19e91
leaq 0x40(%rbx), %r15
leaq 0x10eb3(%rip), %rdi     # 0x2ab30
movq %r15, %rsi
callq 0x1b0e0
testq %rax, %rax
je 0x19e91
leaq 0x60(%rbx), %r12
leaq 0x10e97(%rip), %rdi     # 0x2ab30
movq %r12, %rsi
callq 0x1b0e0
testq %rax, %rax
je 0x19e91
leaq 0x10e7f(%rip), %r13     # 0x2ab30
movq %r13, %rdi
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r14d
shll $0xb, %r14d
movq %r13, %rdi
movq %r15, %rsi
callq 0x1b104
movl (%rax), %r15d
shll $0x15, %r15d
movq %r13, %rdi
movq %r12, %rsi
callq 0x1b104
movl (%rax), %eax
shll $0x10, %eax
addl %r15d, %eax
addl -0x2c(%rbp), %r14d
jmp 0x19e3a
leaq 0x3600(%rip), %rsi      # 0x1d2f8
movq %rbx, %rdi
callq 0xbdb1
movzbl %al, %eax
movl %eax, %esi
shll $0x5, %esi
addq $0x20, %rsi
xorb $0x1, %al
movzbl %al, %r14d
shll $0x5, %r14d
addq $0x20, %r14
addq %rbx, %rsi
leaq 0x10e0c(%rip), %r15     # 0x2ab30
movq %r15, %rdi
callq 0x1b104
movl (%rax), %r13d
shll $0x10, %r13d
addl %r12d, %r13d
addq %rbx, %r14
movq %r15, %rdi
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r12d
shll $0x15, %r12d
addl %r13d, %r12d
movzwl 0x88(%rbx), %r14d
addl %r12d, %r14d
jmp 0x19e4f
leaq 0x371c(%rip), %rsi      # 0x1d481
movq %rbx, %rdi
callq 0xbdb1
testb %al, %al
je 0x19dbd
leaq 0x10db8(%rip), %r12     # 0x2ab30
movq %r12, %rdi
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r14d
shll $0x15, %r14d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1b104
movl (%rax), %eax
shll $0xb, %eax
jmp 0x19e37
leaq 0x10d8a(%rip), %rdi     # 0x2ab30
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r14d
shll $0x15, %r14d
addl %r13d, %r14d
jmp 0x19e3d
leaq 0x3598(%rip), %rsi      # 0x1d35c
movq %rbx, %rdi
callq 0xbdb1
testb %al, %al
jne 0x19de3
leaq 0x3589(%rip), %rsi      # 0x1d360
movq %rbx, %rdi
callq 0xbdb1
testb %al, %al
je 0x19e0e
leaq 0x10d46(%rip), %r12     # 0x2ab30
movq %r12, %rdi
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r14d
shll $0xb, %r14d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1b104
movl (%rax), %eax
shll $0x15, %eax
jmp 0x19e37
leaq 0x10d1b(%rip), %r12     # 0x2ab30
movq %r12, %rdi
movq %r14, %rsi
callq 0x1b104
movl (%rax), %r14d
shll $0x15, %r14d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1b104
movl (%rax), %eax
shll $0x10, %eax
addl %r13d, %r14d
addl %eax, %r14d
leaq 0x10cbc(%rip), %rdi     # 0x2ab00
movq %rbx, %rsi
callq 0x1b104
addl (%rax), %r14d
movl %r14d, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
pushq $0x10
popq %rdi
callq 0x5190
movq %rax, %rbx
leaq 0x35ed(%rip), %rsi      # 0x1d460
movq %rax, %rdi
callq 0x55c0
movq 0x1014e(%rip), %rsi     # 0x29fd0
movq 0x1012f(%rip), %rdx     # 0x29fb8
movq %rbx, %rdi
callq 0x5510
pushq $0x10
popq %rdi
callq 0x5190
movq %rax, %rbx
leaq 0x35cd(%rip), %rsi      # 0x1d470
movq %rax, %rdi
callq 0x55c0
jmp 0x19e7b
pushq $0x10
popq %rdi
callq 0x5190
movq %rax, %rbx
leaq 0x35b1(%rip), %rsi      # 0x1d470
movq %rax, %rdi
callq 0x55c0
jmp 0x19e7b
pushq $0x10
popq %rdi
callq 0x5190
movq %rax, %rbx
leaq 0x3595(%rip), %rsi      # 0x1d470
movq %rax, %rdi
callq 0x55c0
jmp 0x19e7b
jmp 0x19eeb
jmp 0x19eeb
jmp 0x19eeb
movq %rax, %r14
movq %rbx, %rdi
callq 0x5260
movq %r14, %rdi
callq 0x5560