// File: luooofan[P]hblzbd_compiler/src/Pass/generate_arm_from_ssa.cpp
// Function: GenerateArmFromSSA::ResolveImm2Reg(ArmBasicBlock*, int, bool)
Reg* GenerateArmFromSSA::ResolveImm2Reg(ArmBasicBlock* armbb, int imm, bool record) {
  auto vreg = NewVirtualReg();
  Instruction* inst = nullptr;
  if (Operand2::CheckImm8m(imm)) {
    // NOTE: 寄存器分配后立即数值可能会变
    inst = new Move(vreg, new Operand2(imm), armbb);
  } else {
    if (imm < 0 && Operand2::CheckImm8m(-imm - 1)) {  // mvn
      inst = new Move(vreg, new Operand2(-imm - 1), armbb, true);
    } else {  // use ldr pseudo-inst instead of mov.
      inst = new LdrPseudo(vreg, imm, armbb);
    }
  }
  MyAssert(nullptr != inst);
  if (record) {
    this->sp_fixup.insert(inst);
  }
  return vreg;
}

// Assembly:
subq $0x88, %rsp
movb %cl, %al
movq %rdi, 0x80(%rsp)
movq %rsi, 0x78(%rsp)
movl %edx, 0x74(%rsp)
andb $0x1, %al
movb %al, 0x73(%rsp)
movq 0x80(%rsp), %rdi
movq %rdi, 0x38(%rsp)
callq 0xaaf80
movq %rax, 0x68(%rsp)
movq $0x0, 0x60(%rsp)
movl 0x74(%rsp), %edi
callq 0xa450
testb $0x1, %al
jne 0xab042
jmp 0xab0f0
movl $0x28, %edi
callq 0x8340
movq %rax, 0x20(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x28(%rsp)
movl $0x18, %edi
callq 0x8340
movq %rax, 0x30(%rsp)
jmp 0xab06c
movq 0x30(%rsp), %rdi
movl 0x74(%rsp), %esi
callq 0x77f00
jmp 0xab07c
movq 0x30(%rsp), %rdx
movq 0x28(%rsp), %rsi
movq 0x20(%rsp), %rdi
movq 0x78(%rsp), %rcx
xorl %r8d, %r8d
movl $0x1, %r9d
callq 0xb2060
jmp 0xab0a0
movq 0x20(%rsp), %rax
movq %rax, 0x60(%rsp)
jmp 0xab21f
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
jmp 0xab0dc
movq 0x30(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
movl $0x18, %esi
callq 0x8350
movq 0x20(%rsp), %rdi
movl $0x28, %esi
callq 0x8350
jmp 0xab2b2
cmpl $0x0, 0x74(%rsp)
jge 0xab1c2
xorl %edi, %edi
subl 0x74(%rsp), %edi
subl $0x1, %edi
callq 0xa450
testb $0x1, %al
jne 0xab112
jmp 0xab1c2
movl $0x28, %edi
callq 0x8340
movq %rax, 0x8(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x18, %edi
callq 0x8340
movq %rax, 0x18(%rsp)
jmp 0xab13c
movq 0x18(%rsp), %rdi
movl 0x74(%rsp), %esi
notl %esi
callq 0x77f00
jmp 0xab14e
movq 0x18(%rsp), %rdx
movq 0x10(%rsp), %rsi
movq 0x8(%rsp), %rdi
movq 0x78(%rsp), %rcx
movl $0x1, %r9d
movl %r9d, %r8d
callq 0xb2060
jmp 0xab172
movq 0x8(%rsp), %rax
movq %rax, 0x60(%rsp)
jmp 0xab21d
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
jmp 0xab1ae
movq 0x18(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
movl $0x18, %esi
callq 0x8350
movq 0x8(%rsp), %rdi
movl $0x28, %esi
callq 0x8350
jmp 0xab2b2
movl $0x48, %edi
callq 0x8340
movq %rax, %rdi
movq %rdi, %rax
movq %rax, (%rsp)
movq 0x68(%rsp), %rsi
movl 0x74(%rsp), %edx
movq 0x78(%rsp), %rcx
movl $0x1, %r8d
callq 0xb2140
jmp 0xab1f1
movq (%rsp), %rax
movq %rax, 0x60(%rsp)
jmp 0xab21d
movq (%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
movl $0x48, %esi
callq 0x8350
jmp 0xab2b2
jmp 0xab21f
xorl %eax, %eax
cmpq 0x60(%rsp), %rax
jne 0xab27f
movq 0xa0db9(%rip), %rdi     # 0x14bfe8
leaq 0x4eec2(%rip), %rsi     # 0xfa0f8
callq 0x8330
movq %rax, %rdi
leaq 0x52784(%rip), %rsi     # 0xfd9c9
callq 0x8330
movq %rax, %rdi
leaq 0x50196(%rip), %rsi     # 0xfb3ea
callq 0x8330
movq %rax, %rdi
movl $0x4e, %esi
callq 0x8650
movq %rax, %rdi
movq 0xa0d10(%rip), %rsi     # 0x14bf80
callq 0x8380
movl $0xff, %edi
callq 0x8460
testb $0x1, 0x73(%rsp)
je 0xab2a5
movq 0x38(%rsp), %rdi
addq $0xd0, %rdi
leaq 0x60(%rsp), %rsi
callq 0xd470
movq %rax, 0x40(%rsp)
movb %dl, 0x48(%rsp)
movq 0x68(%rsp), %rax
addq $0x88, %rsp
retq
movq 0x58(%rsp), %rdi
callq 0x8670
nopl (%rax)