// File: /workspace/github_cpp_makefile_star2_O3/NishadSaraf[P]Championship-Simulator/src/dram_controller.cc
// Function: MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE*)
void MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE *queue)
{
    for (uint32_t i=0; i<queue->SIZE; i++) {
        if (queue->entry[i].scheduled) {

            uint64_t op_addr = queue->entry[i].address;
            uint32_t op_cpu = queue->entry[i].cpu,
                     op_channel = dram_get_channel(op_addr), 
                     op_rank = dram_get_rank(op_addr), 
                     op_bank = dram_get_bank(op_addr), 
                     op_row = dram_get_row(op_addr);

#ifdef DEBUG_PRINT
            //uint32_t op_column = dram_get_column(op_addr);
#endif

            // update open row
            if ((bank_request[op_channel][op_rank][op_bank].cycle_available - tCAS) <= current_core_cycle[op_cpu])
                bank_request[op_channel][op_rank][op_bank].open_row = op_row;
            else
                bank_request[op_channel][op_rank][op_bank].open_row = UINT32_MAX;

            // this bank is ready for another DRAM request
            bank_request[op_channel][op_rank][op_bank].request_index = -1;
            bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0;
            bank_request[op_channel][op_rank][op_bank].working = 0;
            bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu];
            if (bank_request[op_channel][op_rank][op_bank].is_write) {
                scheduled_writes--;
                bank_request[op_channel][op_rank][op_bank].is_write = 0;
            }
            else if (bank_request[op_channel][op_rank][op_bank].is_read) {
                scheduled_reads--;
                bank_request[op_channel][op_rank][op_bank].is_read = 0;
            }

            queue->entry[i].scheduled = 0;
            queue->entry[i].event_cycle = current_core_cycle[op_cpu];

            DP ( if (warmup_complete[op_cpu]) {
            cout << queue->NAME << " instr_id: " << queue->entry[i].instr_id << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads << endl; });

        }
    }
    
    update_schedule_cycle(&RQ);
    update_schedule_cycle(&WQ);
    update_process_cycle(&RQ);
    update_process_cycle(&WQ);

#ifdef SANITY_CHECK
    if (queue->is_WQ) {
        if (scheduled_writes != 0)
            assert(0);
    }
    else {
        if (scheduled_reads != 0)
            assert(0);
    }
#endif
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movq %rsi, 0x10(%rsp)
movl 0x20(%rsi), %r8d
testq %r8, %r8
je 0xb6eb
movq 0x10(%rsp), %rax
movq 0x98(%rax), %rax
leaq 0x7858(%rbx), %rcx
movl 0x10c20(%rip), %edx     # 0x1c21c
movl 0x7848(%rbx), %esi
movl %esi, 0xc(%rsp)
movl 0x784c(%rbx), %edi
imulq $0x380, %r8, %r8        # imm = 0x380
xorl %r9d, %r9d
leaq 0x758a3(%rip), %r10     # 0x80ec0
movl $0xffffffff, %r11d      # imm = 0xFFFFFFFF
xorl %r15d, %r15d
cmpb $0x0, 0x2(%rax,%r15)
je 0xb6db
movq 0x340(%rax,%r15), %rbp
movl 0x330(%rax,%r15), %r12d
movl %ebp, %r13d
shrl $0x8, %r13d
andl $0x7, %r13d
movl %ebp, %r14d
andl $0x7, %r14d
leaq (%r13,%r13,4), %r13
shll $0x6, %r13d
addq %rcx, %r13
leaq (%r14,%r14,4), %r14
leaq (%r13,%r14,8), %r13
movq (%r13), %r14
subq %rdx, %r14
movq (%r10,%r12,8), %rsi
shrl $0xb, %ebp
andl $0x7fff, %ebp           # imm = 0x7FFF
cmpq %rsi, %r14
cmoval %r11d, %ebp
movl %ebp, 0x18(%r13)
movl %r11d, 0x24(%r13)
movb %r9b, 0x1e(%r13)
movb %r9b, 0x1c(%r13)
movq %rsi, (%r13)
cmpb %r9b, 0x20(%r13)
je 0xb6ad
decl %edi
movl %edi, 0x784c(%rbx)
movb $0x0, 0x20(%r13)
jmp 0xb6c9
cmpb $0x0, 0x21(%r13)
je 0xb6c9
movl 0xc(%rsp), %esi
decl %esi
movl %esi, 0xc(%rsp)
movl %esi, 0x7848(%rbx)
movb $0x0, 0x21(%r13)
movb $0x0, 0x2(%rax,%r15)
movq (%r10,%r12,8), %rsi
movq %rsi, 0x378(%rax,%r15)
addq $0x380, %r15            # imm = 0x380
cmpq %r15, %r8
jne 0xb626
leaq 0x9ef8(%rbx), %rsi
callq 0xb848
leaq 0x8258(%rbx), %rsi
callq 0xb848
movl 0x9f18(%rbx), %edx
xorl %ecx, %ecx
movq $-0x1, %rax
movq $-0x1, %rsi
movl $0x0, %r8d
testq %rdx, %rdx
je 0xb75b
movq 0x9f90(%rbx), %rdi
addq $0x2, %rdi
xorl %r9d, %r9d
movl %edx, %r8d
cmpb $0x0, (%rdi)
je 0xb74c
movq 0x376(%rdi), %r10
cmpq %rsi, %r10
cmovbq %r10, %rsi
cmovbl %r9d, %r8d
incq %r9
addq $0x380, %rdi            # imm = 0x380
cmpq %r9, %rdx
jne 0xb735
movq %rsi, 0x9f50(%rbx)
movl %r8d, 0x9f3c(%rbx)
movl 0x8278(%rbx), %edx
testq %rdx, %rdx
je 0xb7af
movq 0x82f0(%rbx), %rsi
addq $0x2, %rsi
movq $-0x1, %rax
xorl %edi, %edi
movl %edx, %ecx
cmpb $0x0, (%rsi)
je 0xb7a0
movq 0x376(%rsi), %r8
cmpq %rax, %r8
cmovbq %r8, %rax
cmovbl %edi, %ecx
incq %rdi
addq $0x380, %rsi            # imm = 0x380
cmpq %rdi, %rdx
jne 0xb78a
movq %rax, 0x82b0(%rbx)
movl %ecx, 0x829c(%rbx)
movq 0x10(%rsp), %rax
cmpb $0x0, 0x25(%rax)
je 0xb7ef
cmpl $0x0, 0x784c(%rbx)
je 0xb7f8
leaq 0x8890(%rip), %rdi      # 0x14067
leaq 0x9316(%rip), %rsi      # 0x14af4
leaq 0x9326(%rip), %rcx      # 0x14b0b
movl $0x3c, %edx
callq 0x3160
cmpl $0x0, 0x7848(%rbx)
jne 0xb807
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x8859(%rip), %rdi      # 0x14067
leaq 0x92df(%rip), %rsi      # 0x14af4
leaq 0x92ef(%rip), %rcx      # 0x14b0b
movl $0x40, %edx
callq 0x3160