// File: /workspace/github_c_makefile_star2_O3/hamsternz[P]emulate-risc-v/riscv.c
// Function: op_unified
static int op_unified(void) {
  uint32_t op1, op2, res, csr_res; 
  uint32_t pc_next_i, pc_cond_jump, pc_rel_jump, pc_indirect; 

  /*******************************************************
   * Build local variables based on global state 
   ******************************************************/
  /* Options for next PC value */
  pc_next_i    = pc + 4;
  pc_cond_jump = pc + broffset;
  pc_rel_jump  = pc + jmpoffset;
  pc_indirect  = (regs[rs1] + imm12) & (~1);

  /* Operands */
  op1 = regs[rs1];
  op2 = op->op2_immediate ? imm12 : regs[rs2];

  /* Find the results */
  switch(op->alu_mode) {
    case ALU_ADD:    res = op1 + op2;                                               break;
    case ALU_SUB:    res = op1 - op2;                                               break;
    case ALU_SLL:    res = op1 << (op2 & 0x1f);                                     break;
    case ALU_XOR:    res = op1 ^ op2;                                               break;
    case ALU_SRL:    res = (uint32_t)op1 >> (op2 & 0x1f);                           break;
    case ALU_SRA:    res =  (int32_t)op1 >> (op2 & 0x1f);                           break;
    case ALU_OR:     res = op1 | op2;                                               break;
    case ALU_AND:    res = op1 & op2;                                               break;
  
    case ALU_SEQ:    res = (op1 == op2)                     ? 1 : 0;                break;
    case ALU_SLT:    res = ((int32_t)  op1 <  (int32_t)op2) ? 1 : 0;                break;
    case ALU_SLTU:   res = ((uint32_t) op1 < (uint32_t)op2) ? 1 : 0;                break;

    case ALU_MUL:    res = ((uint64_t)op1 * (uint64_t)op2);                         break;
    case ALU_MULH:   res = ( (int64_t)op1 *  (int64_t)op2) >> 32;                   break;
    case ALU_MULHSU: res = ( (int64_t)op1 * (uint64_t)op2) >> 32;                   break;
    case ALU_MULHU:  res = ((uint64_t)op1 * (uint64_t)op2) >> 32;                   break;
    case ALU_DIV:    res = (op2 == 0) ? 0xFFFFFFFF : (int32_t)op1 / (int32_t)op2;   break;
    case ALU_DIVU:   res = (op2 == 0) ? 0xFFFFFFFF : (uint32_t)op1 / (uint32_t)op2; break;
    case ALU_REM:    res = (op2 == 0) ? 0xFFFFFFFF : (int32_t)op1 % (int32_t)op2;   break;
    case ALU_REMU:   res = (op2 == 0) ? 0xFFFFFFFF : (uint32_t)op1 % (uint32_t)op2; break;

    // Maybe seperate
    case ALU_NEXT_I: res = pc_next_i;                                             break;
    case ALU_PC_U20: res = pc + upper20;                                          break;
    case ALU_U20:    res = upper20;                                               break;
    case ALU_CSR:    res = csr[csrid];                                            break;
    default:         res = 0;                                                     break; 
  }

  switch(op->csr_mode) {
    case CSR_RW:  csr_res = regs[rs1];               break;
    case CSR_RS:  csr_res = csr[csrid] | regs[rs1];  break;
    case CSR_RC:  csr_res = csr[csrid] & ~regs[rs1]; break;
    case CSR_RWI: csr_res = uimm;                    break;
    case CSR_RSI: csr_res = csr[csrid] | uimm;       break;
    case CSR_RCI: csr_res = csr[csrid] & ~uimm;      break;
    default:      csr_res = 0;                       break;
  }

  if(op->csr_mode != CSR_NOP) { 
    char buffer[100];
    sprintf(buffer,"CSR 0x%03x accessed",csrid);
    display_log(buffer);
  }

  /* And now do the write */
  if(op->memory_mode == MEM_STORE) {
    if(memory_write_full()) {
      stalled = 1;
    } else {
      uint32_t addr;
      int unaligned = 0;
      addr = regs[rs1]+imm12wr;
      stalled = 0;

      switch(addr & 3) {
        case 1:
          if(op->memory_mask  == 0xFFFFFFFF) {
            unaligned = 1;
          }
          break;
        case 2:
          if(op->memory_mask  == 0xFFFFFFFF) {
            unaligned = 1;
          }
          break;
        case 3:
          if(op->memory_mask  != 0xFF) {
            unaligned = 1;
          }
          break;
      }
      if(unaligned) {
        char buffer[100];
        sprintf(buffer,"Unaligned write at %08x %08x",addr, op->memory_mask);
        display_log(buffer);
      }

      if(!memory_write_request(addr, op->memory_mask, regs[rs2])) {
        return 0;
      }
    }
  }
  
  /* do we need to do a load? */
  if(op->memory_mode == MEM_LOAD) {
    if(rd != 0) {
      if(!read_dispatched) {
        uint32_t addr;
        int unaligned = 0;
        addr = regs[rs1]+imm12;
        stalled = 1;

        switch(addr & 3) {
          case 1:
            if(op->memory_mask  == 0xFFFFFFFF) {
              unaligned = 1;
            }
            break;
          case 2:
            if(op->memory_mask  == 0xFFFFFFFF) {
              unaligned = 1;
            }
            break;
          case 3:
            if(op->memory_mask  != 0xFF) {
              unaligned = 1;
            }
            break;
        }
        if(unaligned) {
          char buffer[100];
          sprintf(buffer,"Unaligned read at %08x %08x",addr, op->memory_mask);
          display_log(buffer);
        }

        if(memory_read_request(regs[rs1]+imm12)) {
          read_dispatched = 1;
        } 
        /* Unable to queue request -  will retry */
      } else {
        /* To get here we are stalled waiting for data */
        if(!memory_read_data_empty())  {
          stalled = 0;
          res = memory_read_data() & op->memory_mask;
          /* Sign extend */
          res |= (res & op->load_sign_check) ? ~op->memory_mask : 0;
        }
      }
    }
  }

  /******************************************************************
   * All assignments from local to global state variables below here
   *****************************************************************/

  /* Store the results? */
  if(!stalled) {
    if(op->store_result && rd != 0)
      regs[rd] = res;

    /* Any CSR updates? */
    switch(op->csr_mode) {
      case CSR_RW:  if(rs1 != 0) csr[csrid] = csr_res;  break;
      case CSR_RS:  if(rs1 != 0) csr[csrid] = csr_res;  break;
      case CSR_RC:  if(rs1 != 0) csr[csrid] = csr_res;  break;
      case CSR_RWI: csr[csrid] = csr_res;               break;
      case CSR_RSI: csr[csrid] = csr_res;               break;
      case CSR_RCI: csr[csrid] = csr_res;               break;
      default:                                          break;
    }

    /* Which instruction next? */
    switch(op->pc_mode) {
      case PC_NEXT_I:        pc = pc_next_i;                      break;
      case PC_COND_JUMP:     pc = res ? pc_cond_jump : pc_next_i; break;
      case PC_COND_JUMP_INV: pc = res ? pc_next_i : pc_cond_jump; break;
      case PC_REL_JUMP:      pc = pc_rel_jump;                    break;
      case PC_INDIRECT:      pc = pc_indirect;                    break;
      default:                                                    break;
    }
  }
  return 1;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movl 0x977b(%rip), %eax      # 0xca10
movzbl 0xd838(%rip), %edx      # 0x10ad4
leaq 0xd78d(%rip), %rdi      # 0x10a30
movl 0xd82f(%rip), %ebp      # 0x10ad8
movq 0xd808(%rip), %rsi      # 0x10ab8
cmpb $0x0, 0x10(%rsi)
movl %ebp, %ecx
jne 0x32c2
movzbl 0xd81d(%rip), %ecx      # 0x10adc
movl (%rdi,%rcx,4), %ecx
movl (%rdi,%rdx,4), %r9d
leal 0x4(%rax), %r8d
movl 0xd7fb(%rip), %r12d     # 0x10acc
addl %eax, %r12d
movl 0xd7f5(%rip), %r13d     # 0x10ad0
addl %eax, %r13d
movzbl 0x11(%rsi), %edx
cmpq $0x16, %rdx
ja 0x33e6
leaq 0x3db9(%rip), %rdi      # 0x70ac
movslq (%rdi,%rdx,4), %rdx
addq %rdi, %rdx
movl %r8d, %r14d
jmpq *%rdx
movl %ecx, %r14d
imulq %r9, %r14
shrq $0x20, %r14
jmp 0x33e9
imull %r9d, %ecx
jmp 0x3386
andl %r9d, %ecx
jmp 0x3386
xorl %r14d, %r14d
cmpl %ecx, %r9d
sete %r14b
jmp 0x33e9
addl 0xd795(%rip), %eax      # 0x10ac4
movl %eax, %r14d
jmp 0x33e9
movl %r9d, %r14d
sarl %cl, %r14d
jmp 0x33e9
movl %r9d, %r14d
subl %ecx, %r14d
jmp 0x33e9
movl %r9d, %r14d
shll %cl, %r14d
jmp 0x33e9
xorl %r9d, %ecx
jmp 0x3386
addl %r9d, %ecx
jmp 0x3386
xorl %r14d, %r14d
cmpl %ecx, %r9d
setl %r14b
jmp 0x33e9
movl 0xd74f(%rip), %r14d     # 0x10ac4
jmp 0x33e9
xorl %r14d, %r14d
cmpl %ecx, %r9d
setb %r14b
jmp 0x33e9
orl %r9d, %ecx
movl %ecx, %r14d
jmp 0x33e9
movl %r9d, %r14d
shrl %cl, %r14d
jmp 0x33e9
testl %ecx, %ecx
je 0x33de
movl %r9d, %eax
cltd
idivl %ecx
jmp 0x33aa
testl %ecx, %ecx
je 0x33de
movl %r9d, %eax
xorl %edx, %edx
divl %ecx
movl %edx, %r14d
jmp 0x33e9
testl %ecx, %ecx
je 0x33de
movl %r9d, %eax
cltd
idivl %ecx
jmp 0x33d9
movl 0xd71f(%rip), %eax      # 0x10ae0
leaq 0x9658(%rip), %rcx      # 0xca20
movl (%rcx,%rax,4), %r14d
jmp 0x33e9
testl %ecx, %ecx
je 0x33de
movl %r9d, %eax
xorl %edx, %edx
divl %ecx
movl %eax, %r14d
jmp 0x33e9
movl $0xffffffff, %r14d      # imm = 0xFFFFFFFF
jmp 0x33e9
xorl %r14d, %r14d
movl %r8d, 0x4(%rsp)
movzbl 0x14(%rsi), %eax
leal -0x1(%rax), %ecx
cmpl $0x5, %ecx
movq %r9, 0x8(%rsp)
ja 0x3478
leaq 0x3d02(%rip), %rax      # 0x7108
movslq (%rax,%rcx,4), %rcx
addq %rax, %rcx
movl %r9d, %ebx
jmpq *%rcx
movl 0xd6c8(%rip), %eax      # 0x10ae0
leaq 0x9601(%rip), %rcx      # 0xca20
movl (%rcx,%rax,4), %ebx
orl 0x8(%rsp), %ebx
jmp 0x347e
movl 0xd6b2(%rip), %eax      # 0x10ae0
leaq 0x95eb(%rip), %rcx      # 0xca20
movl 0xd6a9(%rip), %ebx      # 0x10ae4
orl (%rcx,%rax,4), %ebx
jmp 0x347e
movl 0xd69a(%rip), %eax      # 0x10ae0
leaq 0x95d3(%rip), %rcx      # 0xca20
movq 0x8(%rsp), %rdx
movl %edx, %ebx
jmp 0x3471
movl 0xd688(%rip), %ebx      # 0x10ae4
jmp 0x347e
movl 0xd67c(%rip), %eax      # 0x10ae0
leaq 0x95b5(%rip), %rcx      # 0xca20
movl 0xd673(%rip), %ebx      # 0x10ae4
notl %ebx
andl (%rcx,%rax,4), %ebx
jmp 0x347e
xorl %ebx, %ebx
testb %al, %al
je 0x34a9
movl 0xd65c(%rip), %edx      # 0x10ae0
leaq 0x446f(%rip), %rsi      # 0x78fa
leaq 0x10(%rsp), %r15
movq %r15, %rdi
xorl %eax, %eax
callq 0x2210
movq %r15, %rdi
callq 0x4d36
movq 0xd60f(%rip), %rsi      # 0x10ab8
cmpb $0x2, 0x15(%rsi)
jne 0x3570
callq 0x6113
testl %eax, %eax
je 0x34c8
movb $0x1, 0xd605(%rip)      # 0x10ac8
jmp 0x3570
movl %ebp, %r15d
movzbl 0xd602(%rip), %eax      # 0x10ad4
movl 0xd610(%rip), %ebp      # 0x10ae8
leaq 0xd551(%rip), %rdx      # 0x10a30
addl (%rdx,%rax,4), %ebp
movb $0x0, 0xd5df(%rip)      # 0x10ac8
movl %ebp, %eax
andl $0x3, %eax
leaq 0x3c2b(%rip), %rcx      # 0x7120
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0xd5b3(%rip), %rax      # 0x10ab8
cmpl $-0x1, 0x18(%rax)
jne 0x354a
movl $0xffffffff, %ecx       # imm = 0xFFFFFFFF
jmp 0x3524
movq 0xd59f(%rip), %rax      # 0x10ab8
movl 0x18(%rax), %ecx
cmpl $0xff, %ecx
je 0x354a
leaq 0x43e3(%rip), %rsi      # 0x790e
leaq 0x10(%rsp), %rdi
movl %ebp, %edx
xorl %eax, %eax
callq 0x2210
leaq 0x10(%rsp), %rdi
callq 0x4d36
leaq 0xd4e6(%rip), %rdx      # 0x10a30
movq 0xd567(%rip), %rax      # 0x10ab8
movl 0x18(%rax), %esi
movzbl 0xd581(%rip), %eax      # 0x10adc
movl (%rdx,%rax,4), %edx
movl %ebp, %edi
callq 0x6120
testl %eax, %eax
movl %r15d, %ebp
je 0x3612
movq 0xd541(%rip), %rax      # 0x10ab8
cmpb $0x1, 0x15(%rax)
jne 0x366b
cmpb $0x0, 0xd538(%rip)      # 0x10ac0
je 0x366b
cmpb $0x0, 0xd557(%rip)      # 0x10aec
je 0x35d2
callq 0x6065
testl %eax, %eax
jne 0x366b
movb $0x0, 0xd51d(%rip)      # 0x10ac8
callq 0x607f
movq 0xd501(%rip), %rcx      # 0x10ab8
movl 0x18(%rcx), %r14d
andl %r14d, %eax
movl 0x1c(%rcx), %ecx
andl %eax, %ecx
notl %r14d
cmovel %ecx, %r14d
orl %eax, %r14d
jmp 0x366b
movzbl 0xd4fb(%rip), %ecx      # 0x10ad4
movl 0xd4f9(%rip), %edx      # 0x10ad8
leaq 0xd44a(%rip), %rsi      # 0x10a30
addl (%rsi,%rcx,4), %edx
movb $0x1, 0xd4d8(%rip)      # 0x10ac8
movl %edx, %ecx
andl $0x3, %ecx
leaq 0x3b34(%rip), %rsi      # 0x7130
movslq (%rsi,%rcx,4), %rcx
addq %rsi, %rcx
jmpq *%rcx
cmpl $-0x1, 0x18(%rax)
jne 0x3659
movl $0xffffffff, %ecx       # imm = 0xFFFFFFFF
jmp 0x3624
xorl %eax, %eax
jmp 0x3731
movl 0x18(%rax), %ecx
cmpl $0xff, %ecx
je 0x3659
leaq 0x4300(%rip), %rsi      # 0x792b
leaq 0x10(%rsp), %r15
movq %r15, %rdi
xorl %eax, %eax
callq 0x2210
movq %r15, %rdi
callq 0x4d36
movzbl 0xd48b(%rip), %eax      # 0x10ad4
movl 0xd489(%rip), %edx      # 0x10ad8
leaq 0xd3da(%rip), %rcx      # 0x10a30
addl (%rcx,%rax,4), %edx
movl %edx, %edi
callq 0x5fe3
testl %eax, %eax
je 0x366b
movb $0x1, 0xd481(%rip)      # 0x10aec
movl $0x1, %eax
cmpb $0x0, 0xd451(%rip)      # 0x10ac8
jne 0x3731
movq 0xd434(%rip), %rcx      # 0x10ab8
cmpb $0x0, 0x12(%rcx)
setne %sil
movb 0xd42e(%rip), %dl       # 0x10ac0
testb %dl, %dl
setne %dil
andb %sil, %dil
cmpb $0x1, %dil
jne 0x36af
movzbl %dl, %edx
leaq 0xd385(%rip), %rsi      # 0x10a30
movl %r14d, (%rsi,%rdx,4)
movzbl 0x14(%rcx), %edx
decl %edx
cmpl $0x5, %edx
ja 0x36e3
leaq 0x3a7f(%rip), %rsi      # 0x7140
movslq (%rsi,%rdx,4), %rdx
addq %rsi, %rdx
jmpq *%rdx
cmpb $0x0, 0xd403(%rip)      # 0x10ad4
je 0x36e3
movl 0xd407(%rip), %edx      # 0x10ae0
leaq 0x9340(%rip), %rsi      # 0xca20
movl %ebx, (%rsi,%rdx,4)
movzbl 0x13(%rcx), %ecx
cmpq $0x4, %rcx
ja 0x3731
leaq 0x3a64(%rip), %rdx      # 0x7158
movslq (%rdx,%rcx,4), %rcx
addq %rdx, %rcx
jmpq *%rcx
movl 0x4(%rsp), %r13d
jmp 0x372a
addl 0x8(%rsp), %ebp
andl $-0x2, %ebp
movl %ebp, %r13d
jmp 0x372a
testl %r14d, %r14d
cmovel 0x4(%rsp), %r12d
movl %r12d, %r13d
jmp 0x372a
testl %r14d, %r14d
movl 0x4(%rsp), %r13d
cmovel %r12d, %r13d
movl %r13d, 0x92df(%rip)     # 0xca10
addq $0x78, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq