// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE*)
void DRC_MEMORY_CONTROLLER::reset_remain_requests(PACKET_QUEUE *queue)
{
    for (uint32_t i=0; i<queue->SIZE; i++) {
        if (queue->entry[i].scheduled) {

            uint64_t op_addr = queue->entry[i].address;
            uint32_t op_cpu = queue->entry[i].cpu,
                     op_channel = drc_get_channel(op_addr), 
                     op_rank = drc_get_rank(op_addr), 
                     op_bank = drc_get_bank(op_addr), 
                     op_row = drc_get_row(op_addr);

#ifdef DEBUG_PRINT
            //uint32_t op_column = drc_get_column(op_addr);
#endif

            // update open row
            if ((bank_request[op_channel][op_rank][op_bank].cycle_available - tCAS) <= current_core_cycle[op_cpu])
                bank_request[op_channel][op_rank][op_bank].open_row = op_row;
            else
                bank_request[op_channel][op_rank][op_bank].open_row = UINT32_MAX;

            // this bank is ready for another DRC request
            bank_request[op_channel][op_rank][op_bank].request_index = -1;
            bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0;
            bank_request[op_channel][op_rank][op_bank].working = 0;
            bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu];
            if (bank_request[op_channel][op_rank][op_bank].is_write) {
                scheduled_writes--;
                bank_request[op_channel][op_rank][op_bank].is_write = 0;
            }
            else if (bank_request[op_channel][op_rank][op_bank].is_read) {
                scheduled_reads--;
                bank_request[op_channel][op_rank][op_bank].is_read = 0;
            }

            queue->entry[i].scheduled = 0;
            queue->entry[i].event_cycle = current_core_cycle[op_cpu];

            DP ( if (warmup_complete[op_cpu]) {
            cout << queue->NAME << " instr_id: " << queue->entry[i].instr_id << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads << endl; });

        }
    }
    
    update_schedule_cycle(&RQ);
    update_schedule_cycle(&WQ);
    update_process_cycle(&RQ);
    update_process_cycle(&WQ);

#ifdef SANITY_CHECK
    if (queue->is_WQ) {
        if (scheduled_writes != 0)
            assert(0);
    }
    else {
        if (scheduled_reads != 0)
            assert(0);
    }
#endif
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movl 0x20(%rsi), %eax
leaq 0x409470(%rdi), %rcx
movq %rcx, 0x10(%rsp)
movl 0x409464(%rdi), %ecx
movl %ecx, 0xc(%rsp)
movl 0x409468(%rdi), %esi
pushq $0x2
popq %rdi
xorl %r8d, %r8d
xorl %r15d, %r15d
cmpq %rax, %r15
jae 0xe3e0
movq 0x98(%r14), %r12
cmpb $0x0, (%r12,%rdi)
je 0xe3d1
movq %rbx, %r10
movl 0x32e(%r12,%rdi), %r13d
movl 0x33e(%r12,%rdi), %ebp
movl %ebp, %r9d
shrl $0x5, %r9d
andl $0x3, %r9d
movl %ebp, %r11d
shrl $0xb, %r11d
andl $0x1, %r11d
movl %ebp, %edx
shrl $0x7, %edx
andl $0xf, %edx
imulq $0x500, %r9, %r9        # imm = 0x500
addq 0x10(%rsp), %r9
imulq $0x280, %r11, %r11      # imm = 0x280
addq %r9, %r11
imulq $0x28, %rdx, %rdx
leaq (%r11,%rdx), %r9
movq (%rdx,%r11), %rbx
leaq 0x9ec7(%rip), %rcx      # 0x1820c
movl (%rcx), %ecx
subq %rcx, %rbx
leaq 0x6eb5f(%rip), %rcx     # 0x7ceb0
movq (%rcx,%r13,8), %rcx
shrl $0xc, %ebp
andl $0xfff, %ebp            # imm = 0xFFF
cmpq %rcx, %rbx
pushq $-0x1
popq %rbx
cmoval %ebx, %ebp
movl %ebp, 0x18(%rdx,%r11)
orl $-0x1, 0x24(%rdx,%r11)
movb %r8b, 0x1e(%rdx,%r11)
movb %r8b, 0x1c(%rdx,%r11)
movq %rcx, (%rdx,%r11)
cmpb %r8b, 0x20(%rdx,%r11)
je 0xe39a
decl %esi
movq %r10, %rbx
movl %esi, 0x409468(%r10)
movb $0x0, 0x20(%r9)
jmp 0xe3b9
cmpb $0x0, 0x21(%r9)
movq %r10, %rbx
je 0xe3b9
movl 0xc(%rsp), %ecx
decl %ecx
movl %ecx, 0xc(%rsp)
movl %ecx, 0x409464(%rbx)
movb $0x0, 0x21(%r9)
movb $0x0, (%r12,%rdi)
leaq 0x6eaeb(%rip), %rcx     # 0x7ceb0
movq (%rcx,%r13,8), %rcx
movq %rcx, 0x376(%r12,%rdi)
incq %r15
addq $0x380, %rdi            # imm = 0x380
jmp 0xe2d0
leaq 0x40c510(%rbx), %r15
movq %r15, %rsi
callq 0xe496
leaq 0x40a870(%rbx), %r12
movq %r12, %rsi
callq 0xe496
movq %r15, %rsi
callq 0xe4ea
movq %r12, %rsi
callq 0xe4ea
cmpb $0x0, 0x25(%r14)
je 0xe437
cmpl $0x0, 0x409468(%rbx)
je 0xe440
leaq 0x1c42(%rip), %rdi      # 0x10067
leaq 0x2b7c(%rip), %rsi      # 0x10fa8
leaq 0x2b8b(%rip), %rcx      # 0x10fbe
pushq $0x3d
jmp 0xe466
cmpl $0x0, 0x409464(%rbx)
jne 0xe44f
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x1c11(%rip), %rdi      # 0x10067
leaq 0x2b4b(%rip), %rsi      # 0x10fa8
leaq 0x2b5a(%rip), %rcx      # 0x10fbe
pushq $0x41
popq %rdx
callq 0x2160