// File: /workspace/github_c_makefile_star2_O3/ughman[P]c2c/src/emu.c
// Function: EMU_Write32
void EMU_Write32(uint32_t address,uint32_t value)
{
	if (address & 3)
		SDL_LogError(LOG_EMU,"Unaligned word store");
	if (address >= 0x80000000 && address <= 0x801FFFFF)
	{
normal:
		{
			uint32_t (*codehandler)(uint32_t) = EMU_codemap[(address & 0x1FFFFF) >> 2];
			if (codehandler != EMU_ExecuteUnrecognizedCode)
			{
				SDL_LogError(LOG_EMU,"Writing over code");
			}
		}
		EMU_ram[(address & 0x1FFFFF) >> 2] = value;
	}
	else if (address >= 0x0 && address <= 0x1FFFFF)
	{
		goto normal;
	}
	else if (address >= 0xA0000000 && address <= 0xA01FFFFF)
	{
		goto normal;
	}
	else if (address >= 0x1F800000 && address <= 0x1F8003FF)
	{
		EMU_scratch[(address & 0x3FF) >> 2] = value;
	}
	else switch (address)
	{
	case 0x1F801014:
	case 0x1F801018:
	case 0x1F801020:
		// Unused waitstate configuration
		PCSX_Write32(address,value);
		break;
	case 0x1F801074:
		IRQ_SetMask(value);
		break;
	case 0x1F8010A0:
		DMA_SetAddress(DMA_GPU,value);
		break;
	case 0x1F8010A4:
		DMA_SetBlockData(DMA_GPU,value);
		break;
	case 0x1F8010A8:
		DMA_SetMode(DMA_GPU,value);
		break;
	case 0x1F8010B0:
		DMA_SetAddress(DMA_CDR,value);
		break;
	case 0x1F8010B4:
		DMA_SetBlockData(DMA_CDR,value);
		break;
	case 0x1F8010B8:
		DMA_SetMode(DMA_CDR,value);
		break;
	case 0x1F8010C0:
		DMA_SetAddress(DMA_SPU,value);
		break;
	case 0x1F8010C4:
		DMA_SetBlockData(DMA_SPU,value);
		break;
	case 0x1F8010C8:
		DMA_SetMode(DMA_SPU,value);
		break;
	case 0x1F8010F0:
		DMA_SetControlRegister(value);
		break;
	case 0x1F8010F4:
		DMA_SetInterruptRegister(value);
		break;
	case 0x1F801114:
		RCNT_SetMode(RCNT_HBLANK,value);
		break;
	case 0x1F801810:
		GPU_Write(value);
		break;
	case 0x1F801814:
		GPU_WriteAlt(value);
		break;
	default:
		SDL_LogError(LOG_EMU,"Unrecognized 32-bit write address %.8X",address);
		PCSX_Write32(address,value);
		break;
	}
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movl %esi, %ebx
movl %edi, %r14d
testb $0x3, %r14b
je 0x172ac3
leaq 0x4a11(%rip), %rsi      # 0x1774c8
movl $0x13, %edi
xorl %eax, %eax
callq 0x10d0
testl $0x7fe00000, %r14d      # imm = 0x7FE00000
setne %al
movl %r14d, %ecx
andl $0xffe00000, %ecx       # imm = 0xFFE00000
cmpl $0xa0000000, %ecx       # imm = 0xA0000000
setne %cl
testb %cl, %al
jne 0x172b22
shrl $0x2, %r14d
andl $0x7ffff, %r14d         # imm = 0x7FFFF
leaq 0x886b(%rip), %rax      # 0x17b360
leaq -0xb24(%rip), %rcx      # 0x171fd8
cmpq %rcx, (%rax,%r14,8)
je 0x172b15
leaq 0x4947(%rip), %rsi      # 0x177450
movl $0x13, %edi
xorl %eax, %eax
callq 0x10d0
movq 0x408844(%rip), %rax    # 0x57b360
movl %ebx, (%rax,%r14,4)
jmp 0x172b43
movl %r14d, %eax
andl $0xfffffc00, %eax       # imm = 0xFFFFFC00
cmpl $0x1f800000, %eax       # imm = 0x1F800000
jne 0x172b4b
movq 0x408830(%rip), %rax    # 0x57b368
andl $0x3fc, %r14d           # imm = 0x3FC
movl %ebx, (%rax,%r14)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
cmpl $0x1f8010b7, %r14d      # imm = 0x1F8010B7
jg 0x172b9f
cmpl $0x1f80109f, %r14d      # imm = 0x1F80109F
jle 0x172bea
cmpl $0x1f8010a7, %r14d      # imm = 0x1F8010A7
jle 0x172c66
cmpl $0x1f8010a8, %r14d      # imm = 0x1F8010A8
je 0x172cde
cmpl $0x1f8010b0, %r14d      # imm = 0x1F8010B0
je 0x172cc9
cmpl $0x1f8010b4, %r14d      # imm = 0x1F8010B4
jne 0x172d26
movl $0x3, %edi
jmp 0x172cbb
cmpl $0x1f8010ef, %r14d      # imm = 0x1F8010EF
jle 0x172c20
cmpl $0x1f801113, %r14d      # imm = 0x1F801113
jle 0x172c87
cmpl $0x1f801114, %r14d      # imm = 0x1F801114
je 0x172cf1
cmpl $0x1f801810, %r14d      # imm = 0x1F801810
je 0x172cd0
cmpl $0x1f801814, %r14d      # imm = 0x1F801814
jne 0x172d26
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x171269
leal -0x1f801014(%r14), %eax
cmpl $0xc, %eax
ja 0x172c04
movl $0x1011, %ecx           # imm = 0x1011
btl %eax, %ecx
jb 0x172d3c
cmpl $0x1f801074, %r14d      # imm = 0x1F801074
jne 0x172d26
movzwl %bx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x171233
cmpl $0x1f8010c3, %r14d      # imm = 0x1F8010C3
jg 0x172c49
cmpl $0x1f8010b8, %r14d      # imm = 0x1F8010B8
je 0x172caf
cmpl $0x1f8010c0, %r14d      # imm = 0x1F8010C0
jne 0x172d26
movl $0x4, %edi
jmp 0x172d0a
cmpl $0x1f8010c4, %r14d      # imm = 0x1F8010C4
je 0x172cb6
cmpl $0x1f8010c8, %r14d      # imm = 0x1F8010C8
jne 0x172d26
movl $0x4, %edi
jmp 0x172ce3
cmpl $0x1f8010a0, %r14d      # imm = 0x1F8010A0
je 0x172d05
cmpl $0x1f8010a4, %r14d      # imm = 0x1F8010A4
jne 0x172d26
movl $0x2, %edi
jmp 0x172cbb
cmpl $0x1f8010f0, %r14d      # imm = 0x1F8010F0
je 0x172d18
cmpl $0x1f8010f4, %r14d      # imm = 0x1F8010F4
jne 0x172d26
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x171348
movl $0x3, %edi
jmp 0x172ce3
movl $0x4, %edi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1712dd
movl $0x3, %edi
jmp 0x172d0a
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x171256
movl $0x2, %edi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x171304
movzwl %bx, %esi
movl $0x1, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x17129e
movl $0x2, %edi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1712c8
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x171327
leaq 0x47b0(%rip), %rsi      # 0x1774dd
movl $0x13, %edi
movl %r14d, %edx
xorl %eax, %eax
callq 0x10d0
leaq 0x8565(%rip), %rax      # 0x17b2a8
movq (%rax), %rax
movl %r14d, %edi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmpq *%rax