// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/ssd/Host_Interface_NVMe.cpp
// Function: SSD_Components::Request_Fetch_Unit_NVMe::Process_pcie_write_message(unsigned long, void*, unsigned int)
void Request_Fetch_Unit_NVMe::Process_pcie_write_message(uint64_t address, void *payload, unsigned int payload_size)
{
	Host_Interface_NVMe *hi = (Host_Interface_NVMe *)host_interface;
	uint64_t val = (uint64_t)payload;
	switch (address)
	{
	case SUBMISSION_QUEUE_REGISTER_1:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(0, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_1:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(0, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_2:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(1, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_2:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(1, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_3:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(2, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_3:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(2, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_4:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(3, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_4:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(3, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_5:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(4, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_5:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(4, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_6:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(5, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_6:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(5, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_7:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(6, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_7:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(6, (uint16_t)val);
		break;
	case SUBMISSION_QUEUE_REGISTER_8:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Submission_queue_tail_pointer_update(7, (uint16_t)val);
		break;
	case COMPLETION_QUEUE_REGISTER_8:
		((Input_Stream_Manager_NVMe *)(hi->input_stream_manager))->Completion_queue_head_pointer_update(7, (uint16_t)val);
		break;
	default:
		throw std::invalid_argument("Unknown register is written!");
	}
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movq 0x8(%rdi), %rax
cmpq $0x1083, %rsi           # imm = 0x1083
je 0x34d41
cmpq $0x1013, %rsi           # imm = 0x1013
je 0x34d99
cmpq $0x1020, %rsi           # imm = 0x1020
je 0x34ce6
cmpq $0x1023, %rsi           # imm = 0x1023
je 0x34cf4
cmpq $0x1030, %rsi           # imm = 0x1030
je 0x34d83
cmpq $0x1033, %rsi           # imm = 0x1033
je 0x34d57
cmpq $0x1040, %rsi           # imm = 0x1040
je 0x34d78
cmpq $0x1043, %rsi           # imm = 0x1043
je 0x34d20
cmpq $0x1050, %rsi           # imm = 0x1050
je 0x34d36
cmpq $0x1053, %rsi           # imm = 0x1053
je 0x34d62
cmpq $0x1060, %rsi           # imm = 0x1060
je 0x34d4c
cmpq $0x1063, %rsi           # imm = 0x1063
je 0x34cff
cmpq $0x1070, %rsi           # imm = 0x1070
je 0x34d15
cmpq $0x1073, %rsi           # imm = 0x1073
je 0x34d2b
cmpq $0x1080, %rsi           # imm = 0x1080
je 0x34d0a
cmpq $0x1010, %rsi           # imm = 0x1010
jne 0x34da4
movq 0x50(%rax), %rdi
movzwl %dx, %edx
xorl %esi, %esi
jmp 0x34d8d
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x1
jmp 0x34d8c
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x1
jmp 0x34d6b
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x5
jmp 0x34d6b
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x7
jmp 0x34d8c
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x6
jmp 0x34d8c
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x3
jmp 0x34d6b
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x6
jmp 0x34d6b
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x4
jmp 0x34d8c
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x7
jmp 0x34d6b
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x5
jmp 0x34d8c
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x2
jmp 0x34d6b
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x4
popq %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x35c46
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x3
jmp 0x34d8c
movq 0x50(%rax), %rdi
movzwl %dx, %edx
pushq $0x2
popq %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x35be8
movq 0x50(%rax), %rdi
movzwl %dx, %edx
xorl %esi, %esi
jmp 0x34d6c
pushq $0x10
popq %rdi
callq 0x71b0
movq %rax, %rbx
leaq 0x13077(%rip), %rsi     # 0x47e2d
movq %rax, %rdi
callq 0x7620
movq 0x2d203(%rip), %rsi     # 0x61fc8
movq 0x2d1dc(%rip), %rdx     # 0x61fa8
movq %rbx, %rdi
callq 0x7590
movq %rax, %r14
movq %rbx, %rdi
callq 0x72a0
movq %r14, %rdi
callq 0x75d0
nop