// File: /workspace/github_cpp_makefile_star2_O1/jkingan[P]ladyheather/heathgps.cpp
// Function: show_x72_status(int, int, int)
int show_x72_status(int row,int col, int max_row)
{
int color;

   if(have_x72_creg) {
      if(x72_creg & 0x0008) vidstr(row,col, YELLOW, "PPS OUT: OFF  ");
      else                  vidstr(row,col, GREEN,  "PPS OUT: ON   ");
      if(++row > max_row) return row;

      if(x72_fw_discipline()) {
         if((last_x72_dmode != 1) && (last_x72_dmode != 2)) {
            vidstr(row,col, GREEN, "PPS IN:  UNKN ");
         }
         else if(x72_creg & 0x1000) {  // PPS input detected - fw discipline units only
            vidstr(row,col, GREEN,  "PPS IN:  SEEN ");
         }
         else {
            vidstr(row,col, YELLOW, "PPS IN:  NONE ");
         }
         if(++row > max_row) return row;

         if(user_set_x72_dmode && last_x72_dmode && (last_x72_dmode != 3)) {
            if(x72_creg & 0x0800) {  // PPS out locked to PPS in - fw discipline units only
               vidstr(row,col, GREEN,  "PPS OUT: LOCKED");
            }
            else if(x72_creg & 0x1000) {  // PPS input detected - fw discipline units only
               vidstr(row,col, YELLOW, "PPS OUT: UNLOCK");
            }
            else {
               vidstr(row,col, GREEN,  "PPS OUT: UNLOCK");
            }
            if(++row > max_row) return row;
         }
         else {
            vidstr(row,col, GREEN,  "PPS OUT: UNKN  ");
            if(++row > max_row) return row;
         }
      }

      if(x72_creg & 0x0004) vidstr(row,col, YELLOW, "FXO OUT: OFF  ");
      else                  vidstr(row,col, GREEN,  "FXO OUT: ON   ");
      if(++row > max_row) return row;

      if(x72_creg & 0x0010) vidstr(row,col, YELLOW, "ACMOS:   OFF  ");
      else                  vidstr(row,col, GREEN,  "ACMOS:   ON   ");
      if(++row > max_row) return row;

      if(x72_sine_level == 0) {
         vidstr(row,col, YELLOW, "Sine:    OFF  ");
      }
      else {
         sprintf(out,            "Sine ON: %d%%  ", x72_sine_level);
         vidstr(row,col, GREEN,  out);
      }
      if(++row > max_row) return row;


      if(x72_creg & 0x0002) vidstr(row,col, RED,    "Rb lock: OFF  ");
      else                  vidstr(row,col, GREEN,  "Rb lock: OK   ");
      if(++row > max_row) return row;

      if(x72_creg & 0x0400) vidstr(row,col, RED,    "Service: FAULT");
      else                  vidstr(row,col, GREEN,  "Service: OK   ");
      if(++row > max_row) return row;

      if(have_x72_srvc) {
         if(x72_srvc) vidstr(row,col, GREEN,  "SVC pol: HIGH ");
         else         vidstr(row,col, GREEN,  "SVC pol: LOW  ");
         if(++row > max_row) return row;
      }
      else {
         vidstr(row,col, GREEN,  "SVC pol: UNKN ");
         if(++row > max_row) return row;
      }

      if(x72_creg & 0x2000) {
         vidstr(row,col, GREEN,  "EFC INP: ON   ");
         if(++row > max_row) return row;
      }
      else if(have_x72_efc) {
         if(x72_efc) vidstr(row,col, GREEN,  "EFC inp: ON   ");
         else        vidstr(row,col, GREEN,  "EFC inp: OFF  ");
         if(++row > max_row) return row;
      }
      else {
         vidstr(row,col, GREEN,  "EFC inp: UNKN ");
         if(++row > max_row) return row;
      }

      if(have_x72_state) {
         color = YELLOW;
         if(x72_state == X72_STATE_DISCIPLINE) color = GREEN;
         else if(x72_state == X72_STATE_PIDCALC) color = GREEN;
         else if(x72_state == X72_STATE_PIDUPDATE) color = GREEN;
         else if(x72_state == X72_STATE_START0) color = GREEN;

         sprintf(out, "D State: %-3d  ", x72_state);
         if(color != GREEN)    vidstr(row,col, color, out);
         else if(x72_user_dis) vidstr(row,col, OSC_PID_COLOR, out);
         else                  vidstr(row,col, color,  out);
         if(++row > max_row) return row;
      }
      else {
         sprintf(out, "D State: UNKN ");
         vidstr(row,col, GREEN,  out);
         if(++row > max_row) return row;
      }


      if(x72_creg & 0x0001) vidstr(row,col, YELLOW, "L boost: ON   ");
      else                  vidstr(row,col, GREEN,  "L boost: OFF  ");
      if(++row > max_row) return row;

      if(x72_creg & 0x0020) vidstr(row,col, YELLOW, "C boost: ON   ");
      else                  vidstr(row,col, GREEN,  "C boost: OFF  ");
      if(++row > max_row) return row;
   }

   return row;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %edi, %r15d
leaq 0x1640d9(%rip), %rax    # 0x21ac70
cmpl $0x0, (%rax)
je 0xb7027
movl %edx, %r14d
movl %esi, %ebx
leaq 0x16422c(%rip), %r13    # 0x21add8
testb $0x8, (%r13)
jne 0xb6bc6
leaq 0x720f6(%rip), %rcx     # 0x128cb0
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb6bd7
leaq 0x720d4(%rip), %rcx     # 0x128ca1
movl %r15d, %edi
movl %ebx, %esi
movl $0xe, %edx
callq 0xe7d0
leal 0x1(%r15), %r12d
cmpl %r14d, %r15d
jge 0xb7024
callq 0x6cc14
testl %eax, %eax
je 0xb6ce7
leaq 0x164323(%rip), %r13    # 0x21af20
movl (%r13), %eax
addl $-0x3, %eax
cmpl $-0x3, %eax
ja 0xb6c12
leaq 0x720af(%rip), %rcx     # 0x128cbf
jmp 0xb6c39
leaq 0x1641bf(%rip), %rax    # 0x21add8
testb $0x10, 0x1(%rax)
jne 0xb6c32
leaq 0x720b7(%rip), %rcx     # 0x128cdd
movl %r12d, %edi
movl %ebx, %esi
movl $0xe, %edx
jmp 0xb6c43
leaq 0x72095(%rip), %rcx     # 0x128cce
movl %r12d, %edi
movl %ebx, %esi
movl $0xa, %edx
callq 0xe7d0
leal 0x2(%r15), %edi
cmpl %r14d, %edi
jle 0xb6c59
movl %edi, %r15d
jmp 0xb7027
leaq 0x1642a4(%rip), %rax    # 0x21af04
cmpl $0x0, (%rax)
je 0xb6c99
movl (%r13), %eax
testl %eax, %eax
je 0xb6c99
cmpl $0x3, %eax
je 0xb6c99
leaq 0x16415f(%rip), %r13    # 0x21add8
movl (%r13), %eax
btl $0xb, %eax
jb 0xb6cc4
leaq 0x72072(%rip), %rcx     # 0x128cfc
btl $0xc, %eax
jae 0xb6ccb
movl %ebx, %esi
movl $0xe, %edx
jmp 0xb6cd2
leaq 0x7206c(%rip), %rcx     # 0x128d0c
movl %ebx, %esi
movl $0xa, %edx
callq 0xe7d0
addl $0x3, %r15d
movl %r15d, %r12d
cmpl %r14d, %r15d
leaq 0x16411b(%rip), %r13    # 0x21add8
jle 0xb6ce7
jmp 0xb7027
leaq 0x72021(%rip), %rcx     # 0x128cec
movl %ebx, %esi
movl $0xa, %edx
callq 0xe7d0
addl $0x3, %r15d
movl %r15d, %r12d
cmpl %r14d, %r15d
jg 0xb7027
testb $0x4, (%r13)
jne 0xb6d01
leaq 0x72036(%rip), %rcx     # 0x128d2b
movl %r12d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb6d12
leaq 0x72014(%rip), %rcx     # 0x128d1c
movl %r12d, %edi
movl %ebx, %esi
movl $0xe, %edx
callq 0xe7d0
leal 0x1(%r12), %r15d
cmpl %r14d, %r12d
jge 0xb7027
testb $0x10, (%r13)
jne 0xb6d3f
leaq 0x72016(%rip), %rcx     # 0x128d49
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb6d50
leaq 0x71ff4(%rip), %rcx     # 0x128d3a
movl %r15d, %edi
movl %ebx, %esi
movl $0xe, %edx
callq 0xe7d0
leal 0x2(%r12), %r15d
cmpl %r14d, %r15d
jg 0xb7027
leaq 0x16408e(%rip), %rax    # 0x21adf8
movl (%rax), %edx
testl %edx, %edx
je 0xb6d98
leaq 0x2854a9(%rip), %rdi    # 0x33c220
leaq 0x71fe9(%rip), %rsi     # 0x128d67
xorl %eax, %eax
callq 0x9060
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
leaq 0x28548a(%rip), %rcx    # 0x33c220
jmp 0xb6da9
leaq 0x71fb9(%rip), %rcx     # 0x128d58
movl %r15d, %edi
movl %ebx, %esi
movl $0xe, %edx
callq 0xe7d0
leal 0x3(%r12), %r15d
cmpl %r14d, %r15d
jg 0xb7027
testb $0x2, (%r13)
jne 0xb6dd6
leaq 0x71fbc(%rip), %rcx     # 0x128d86
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb6de7
leaq 0x71f9a(%rip), %rcx     # 0x128d77
movl %r15d, %edi
movl %ebx, %esi
movl $0xc, %edx
callq 0xe7d0
leal 0x4(%r12), %r15d
cmpl %r14d, %r15d
jg 0xb7027
testb $0x4, 0x1(%r13)
jne 0xb6e14
leaq 0x71f9c(%rip), %rcx     # 0x128da4
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb6e25
leaq 0x71f7a(%rip), %rcx     # 0x128d95
movl %r15d, %edi
movl %ebx, %esi
movl $0xc, %edx
callq 0xe7d0
leal 0x5(%r12), %r15d
cmpl %r14d, %r15d
jg 0xb7027
leaq 0x163ec9(%rip), %rax    # 0x21ad08
cmpl $0x0, (%rax)
je 0xb6e62
leaq 0x163ef1(%rip), %rax    # 0x21ad3c
cmpl $0x0, (%rax)
leaq 0x71f6d(%rip), %rax     # 0x128dc2
leaq 0x71f57(%rip), %rcx     # 0x128db3
cmoveq %rax, %rcx
jmp 0xb6e69
leaq 0x71f68(%rip), %rcx     # 0x128dd1
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
callq 0xe7d0
addl $0x6, %r12d
movl %r12d, %r15d
cmpl %r14d, %r12d
jg 0xb7027
testb $0x20, 0x1(%r13)
jne 0xb6eb9
leaq 0x163e6e(%rip), %rax    # 0x21ad04
cmpl $0x0, (%rax)
je 0xb6ec2
leaq 0x163e96(%rip), %rax    # 0x21ad38
cmpl $0x0, (%rax)
leaq 0x71f52(%rip), %rax     # 0x128dfe
leaq 0x71f3c(%rip), %rcx     # 0x128def
cmoveq %rax, %rcx
jmp 0xb6ec9
leaq 0x71f20(%rip), %rcx     # 0x128de0
jmp 0xb6ec9
leaq 0x71f44(%rip), %rcx     # 0x128e0d
movl %r12d, %edi
movl %ebx, %esi
movl $0xa, %edx
callq 0xe7d0
leal 0x1(%r12), %r15d
cmpl %r14d, %r12d
jge 0xb7027
leaq 0x163de7(%rip), %rax    # 0x21acd4
cmpl $0x0, (%rax)
je 0xb6f79
leaq 0x163f03(%rip), %rax    # 0x21ae00
movl (%rax), %edx
cmpl $0x8, %edx
ja 0xb7039
movl $0x1c1, %eax            # imm = 0x1C1
btl %edx, %eax
jae 0xb7039
movb $0xa, %r12b
movb $0x1, %r13b
leaq 0x2852fd(%rip), %rdi    # 0x33c220
leaq 0x71ef2(%rip), %rsi     # 0x128e1c
xorl %eax, %eax
callq 0x9060
leaq 0x163fb8(%rip), %rax    # 0x21aef0
cmpl $0x0, (%rax)
sete %al
xorb $0xb, %al
movzbl %r12b, %ecx
movzbl %al, %eax
testb %r13b, %r13b
cmovel %ecx, %eax
movzbl %al, %edx
movl %r15d, %edi
movl %ebx, %esi
leaq 0x2852c4(%rip), %rcx    # 0x33c220
callq 0xe7d0
leal 0x1(%r15), %r12d
cmpl %r14d, %r15d
movl %r12d, %r15d
leaq 0x163e66(%rip), %r13    # 0x21add8
jl 0xb6fb6
jmp 0xb7027
leaq 0x2852a0(%rip), %rcx    # 0x33c220
movabsq $0x204e4b4e55203a, %rax # imm = 0x204E4B4E55203A
movq %rax, 0x7(%rcx)
movabsq $0x3a65746174532044, %rax # imm = 0x3A65746174532044
movq %rax, (%rcx)
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
callq 0xe7d0
leal 0x1(%r15), %r12d
cmpl %r14d, %r15d
movl %r12d, %r15d
jge 0xb7027
testb $0x1, (%r13)
jne 0xb6fd0
leaq 0x71e86(%rip), %rcx     # 0x128e4a
movl %r12d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb6fe1
leaq 0x71e64(%rip), %rcx     # 0x128e3b
movl %r12d, %edi
movl %ebx, %esi
movl $0xe, %edx
callq 0xe7d0
leal 0x1(%r12), %r15d
cmpl %r14d, %r12d
jge 0xb7027
testb $0x20, (%r13)
jne 0xb700a
leaq 0x71e6a(%rip), %rcx     # 0x128e68
movl %r15d, %edi
movl %ebx, %esi
movl $0xa, %edx
jmp 0xb701b
leaq 0x71e48(%rip), %rcx     # 0x128e59
movl %r15d, %edi
movl %ebx, %esi
movl $0xe, %edx
callq 0xe7d0
addl $0x2, %r12d
movl %r12d, %r15d
movl %r15d, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movb $0xe, %r12b
xorl %r13d, %r13d
jmp 0xb6f1c