// File: CMU-SAFARI[P]MQSim/src/ssd/TSU_Base.cpp
// Function: SSD_Components::TSU_Base::issue_command_to_chip(SSD_Components::Flash_Transaction_Queue*, SSD_Components::Flash_Transaction_Queue*, SSD_Components::Transaction_Type, bool)
bool TSU_Base::issue_command_to_chip(Flash_Transaction_Queue *sourceQueue1, Flash_Transaction_Queue *sourceQueue2, Transaction_Type transactionType, bool suspensionRequired)
	{
		flash_die_ID_type dieID = sourceQueue1->front()->Address.DieID;
		flash_page_ID_type pageID = sourceQueue1->front()->Address.PageID;
		unsigned int planeVector = 0;
		static int issueCntr = 0;
		
		for (unsigned int i = 0; i < die_no_per_chip; i++)
		{
			transaction_dispatch_slots.clear();
			planeVector = 0;

			for (Flash_Transaction_Queue::iterator it = sourceQueue1->begin(); it != sourceQueue1->end();)
			{
				if (transaction_is_ready(*it) && (*it)->Address.DieID == dieID && !(planeVector & 1 << (*it)->Address.PlaneID))
				{
					//Check for identical pages when running multiplane command
					if (planeVector == 0 || (*it)->Address.PageID == pageID)
					{
						(*it)->SuspendRequired = suspensionRequired;
						planeVector |= 1 << (*it)->Address.PlaneID;
						transaction_dispatch_slots.push_back(*it);
						DEBUG(issueCntr++ << ": " << Simulator->Time() <<" Issueing Transaction - Type:" << TRTOSTR((*it)) << ", PPA:" << (*it)->PPA << ", LPA:" << (*it)->LPA << ", Channel: " << (*it)->Address.ChannelID << ", Chip: " << (*it)->Address.ChipID);
						sourceQueue1->remove(it++);
						continue;
					}
				}
				it++;
			}

			if (sourceQueue2 != NULL && transaction_dispatch_slots.size() < plane_no_per_die)
			{
				for (Flash_Transaction_Queue::iterator it = sourceQueue2->begin(); it != sourceQueue2->end();)
				{
					if (transaction_is_ready(*it) && (*it)->Address.DieID == dieID && !(planeVector & 1 << (*it)->Address.PlaneID))
					{
						//Check for identical pages when running multiplane command
						if (planeVector == 0 || (*it)->Address.PageID == pageID)
						{
							(*it)->SuspendRequired = suspensionRequired;
							planeVector |= 1 << (*it)->Address.PlaneID;
							transaction_dispatch_slots.push_back(*it);
							DEBUG(issueCntr++ << ": " << Simulator->Time() << " Issueing Transaction - Type:" << TRTOSTR((*it)) << ", PPA:" << (*it)->PPA << ", LPA:" << (*it)->LPA << ", Channel: " << (*it)->Address.ChannelID << ", Chip: " << (*it)->Address.ChipID);
							sourceQueue2->remove(it++);
							continue;
						}
					}
					it++;
				}
			}

			if (transaction_dispatch_slots.size() > 0)
			{
				_NVMController->Send_command_to_chip(transaction_dispatch_slots);
				transaction_dispatch_slots.clear();
				dieID = (dieID + 1) % die_no_per_chip;
				return true;
			}
			else
			{
				transaction_dispatch_slots.clear();
				dieID = (dieID + 1) % die_no_per_chip;
				return false;
			}			
		}

		return false;
	}

// Assembly:
subq $0xb8, %rsp
movb %r8b, %al
movq %rdi, 0xa8(%rsp)
movq %rsi, 0xa0(%rsp)
movq %rdx, 0x98(%rsp)
movl %ecx, 0x94(%rsp)
andb $0x1, %al
movb %al, 0x93(%rsp)
movq 0xa8(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0xa0(%rsp), %rdi
addq $0x8, %rdi
callq 0x7fe10
movq (%rax), %rax
movl 0x40(%rax), %eax
movl %eax, 0x8c(%rsp)
movq 0xa0(%rsp), %rdi
addq $0x8, %rdi
callq 0x7fe10
movq (%rax), %rax
movl 0x4c(%rax), %eax
movl %eax, 0x88(%rsp)
movl $0x0, 0x84(%rsp)
movl $0x0, 0x80(%rsp)
movq 0x38(%rsp), %rcx
movl 0x80(%rsp), %eax
cmpl 0x4c(%rcx), %eax
jae 0x9b764
movq 0x38(%rsp), %rdi
addq $0x90, %rdi
callq 0x5d190
movl $0x0, 0x84(%rsp)
movq 0xa0(%rsp), %rdi
addq $0x8, %rdi
callq 0x7ff20
movq %rax, 0x78(%rsp)
movq 0xa0(%rsp), %rdi
addq $0x8, %rdi
callq 0x5d430
movq %rax, 0x70(%rsp)
leaq 0x78(%rsp), %rdi
leaq 0x70(%rsp), %rsi
callq 0x80030
testb $0x1, %al
jne 0x9b3a6
jmp 0x9b4fd
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movq 0x38(%rsp), %rdi
movq (%rax), %rsi
callq 0x9b7e0
testb $0x1, %al
jne 0x9b3c6
jmp 0x9b4e7
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movq (%rax), %rax
movl 0x40(%rax), %eax
cmpl 0x8c(%rsp), %eax
jne 0x9b4e7
movl 0x84(%rsp), %eax
movl %eax, 0x34(%rsp)
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movq %rax, %rcx
movl 0x34(%rsp), %eax
movq (%rcx), %rcx
movl 0x44(%rcx), %ecx
movl $0x1, %edx
shll %cl, %edx
movl %edx, %ecx
andl %ecx, %eax
cmpl $0x0, %eax
jne 0x9b4e7
cmpl $0x0, 0x84(%rsp)
je 0x9b440
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movq (%rax), %rax
movl 0x4c(%rax), %eax
cmpl 0x88(%rsp), %eax
jne 0x9b4e5
movb 0x93(%rsp), %al
movb %al, 0x1f(%rsp)
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movb 0x1f(%rsp), %cl
movq (%rax), %rax
andb $0x1, %cl
movb %cl, 0x68(%rax)
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movq %rax, %rcx
movq 0x38(%rsp), %rax
movq (%rcx), %rcx
movl 0x44(%rcx), %ecx
movl $0x1, %edx
shll %cl, %edx
movl %edx, %ecx
orl 0x84(%rsp), %ecx
movl %ecx, 0x84(%rsp)
addq $0x90, %rax
movq %rax, 0x20(%rsp)
leaq 0x78(%rsp), %rdi
callq 0x7fda0
movq 0x20(%rsp), %rdi
movq %rax, %rsi
callq 0x5d3a0
movq 0xa0(%rsp), %rax
movq %rax, 0x28(%rsp)
leaq 0x78(%rsp), %rdi
xorl %esi, %esi
callq 0x91c50
movq 0x28(%rsp), %rdi
movq %rax, 0x68(%rsp)
leaq 0x68(%rsp), %rsi
callq 0x7f030
jmp 0x9b378
jmp 0x9b4e7
leaq 0x78(%rsp), %rdi
xorl %esi, %esi
callq 0x91c50
movq %rax, 0x60(%rsp)
jmp 0x9b378
cmpq $0x0, 0x98(%rsp)
je 0x9b6cb
movq 0x38(%rsp), %rdi
addq $0x90, %rdi
callq 0x91c80
movq 0x38(%rsp), %rcx
movl 0x50(%rcx), %ecx
cmpq %rcx, %rax
jae 0x9b6cb
movq 0x98(%rsp), %rdi
addq $0x8, %rdi
callq 0x7ff20
movq %rax, 0x58(%rsp)
movq 0x98(%rsp), %rdi
addq $0x8, %rdi
callq 0x5d430
movq %rax, 0x50(%rsp)
leaq 0x58(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x80030
testb $0x1, %al
jne 0x9b572
jmp 0x9b6c9
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movq 0x38(%rsp), %rdi
movq (%rax), %rsi
callq 0x9b7e0
testb $0x1, %al
jne 0x9b592
jmp 0x9b6b3
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movq (%rax), %rax
movl 0x40(%rax), %eax
cmpl 0x8c(%rsp), %eax
jne 0x9b6b3
movl 0x84(%rsp), %eax
movl %eax, 0x18(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movq %rax, %rcx
movl 0x18(%rsp), %eax
movq (%rcx), %rcx
movl 0x44(%rcx), %ecx
movl $0x1, %edx
shll %cl, %edx
movl %edx, %ecx
andl %ecx, %eax
cmpl $0x0, %eax
jne 0x9b6b3
cmpl $0x0, 0x84(%rsp)
je 0x9b60c
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movq (%rax), %rax
movl 0x4c(%rax), %eax
cmpl 0x88(%rsp), %eax
jne 0x9b6b1
movb 0x93(%rsp), %al
movb %al, 0x7(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movb 0x7(%rsp), %cl
movq (%rax), %rax
andb $0x1, %cl
movb %cl, 0x68(%rax)
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movq %rax, %rcx
movq 0x38(%rsp), %rax
movq (%rcx), %rcx
movl 0x44(%rcx), %ecx
movl $0x1, %edx
shll %cl, %edx
movl %edx, %ecx
orl 0x84(%rsp), %ecx
movl %ecx, 0x84(%rsp)
addq $0x90, %rax
movq %rax, 0x8(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x7fda0
movq 0x8(%rsp), %rdi
movq %rax, %rsi
callq 0x5d3a0
movq 0x98(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x58(%rsp), %rdi
xorl %esi, %esi
callq 0x91c50
movq 0x10(%rsp), %rdi
movq %rax, 0x48(%rsp)
leaq 0x48(%rsp), %rsi
callq 0x7f030
jmp 0x9b544
jmp 0x9b6b3
leaq 0x58(%rsp), %rdi
xorl %esi, %esi
callq 0x91c50
movq %rax, 0x40(%rsp)
jmp 0x9b544
jmp 0x9b6cb
movq 0x38(%rsp), %rdi
addq $0x90, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9b72e
movq 0x38(%rsp), %rsi
movq 0x38(%rsi), %rdi
addq $0x90, %rsi
movq (%rdi), %rax
callq *0x58(%rax)
movq 0x38(%rsp), %rdi
addq $0x90, %rdi
callq 0x5d190
movq 0x38(%rsp), %rcx
movl 0x8c(%rsp), %eax
addl $0x1, %eax
xorl %edx, %edx
divl 0x4c(%rcx)
movl %edx, 0x8c(%rsp)
movb $0x1, 0xb7(%rsp)
jmp 0x9b76c
movq 0x38(%rsp), %rdi
addq $0x90, %rdi
callq 0x5d190
movq 0x38(%rsp), %rcx
movl 0x8c(%rsp), %eax
addl $0x1, %eax
xorl %edx, %edx
divl 0x4c(%rcx)
movl %edx, 0x8c(%rsp)
movb $0x0, 0xb7(%rsp)
jmp 0x9b76c
movb $0x0, 0xb7(%rsp)
movb 0xb7(%rsp), %al
andb $0x1, %al
addq $0xb8, %rsp
retq
nopl (%rax)