// File: rfotino[P]consolite-emulator/src/processor.cpp
// Function: EmuProcessor::execute()
void EmuProcessor::execute() {
  // The value of the clock at the last time we encountered
  // a TIMERST instruction.
  clock_t timeSinceRst = clock();

  // Seeds the random number generator (crude, but you probably
  // aren't going to be running this emulator more than once
  // per second).
  srand(time(nullptr));

  while (_running) {
    // Execute next instruction
    uint8_t *inst = &_mainMem[_instructionPointer];
    uint8_t opcode = inst[0];
    uint8_t arg1 = inst[1];
    uint8_t arg2 = inst[2];
    uint8_t reg1 = arg1 & 0xf;
    uint8_t reg2 = arg2 & 0xf;
    uint16_t argA = (inst[1] << 8) | inst[2];
    uint16_t argB = (inst[2] << 8) | inst[3];

    uint32_t dest = _registers[reg1];
    uint32_t src = _registers[reg2];
    uint32_t result;

    uint16_t nextInstPtr = _instructionPointer + INST_SIZE;
    bool clearFlags = true;

    switch (opcode) {
    case OPCODE_NOP:
    default:
      // Do nothing
      break;
    case OPCODE_INPUT:
      // INPUT DEST SRC
      // Where DEST is the register where the input data will be
      // stored and SRC holds the input ID that we want to check
      _registers[reg1] = _window->getInput(src);
      break;
    case OPCODE_CALL:
      // CALL ADDR
      // Push the instruction pointer onto the stack and jump to
      // address within the current instruction.
      _push(_instructionPointer);
      nextInstPtr = argA;
      break;
    case OPCODE_RET:
      // RET NUM
      // Pop the instruction pointer off the stack, add the provided
      // argument, and jump to it.
      nextInstPtr = _pop() + INST_SIZE;
      _registers[REG_SP] -= arg1;
      break;
    case OPCODE_LOAD:
      // LOAD DEST SRC
      // Load the memory pointed to by SRC and put it in DEST.
      _registers[reg1] = (_mainMem[src] << 8) | _mainMem[src+1];
      break;
    case OPCODE_LOADI:
      // LOADI DEST ADDR
      // Load the memory at ADDR and put it in DEST.
      _registers[reg1] = (_mainMem[argB] << 8) | _mainMem[argB+1];
      break;
    case OPCODE_MOV:
      // MOV DEST SRC
      _registers[reg1] = src;
      break;
    case OPCODE_MOVI:
      // MOV DEST VALUE
      _registers[reg1] = argB;
      break;
    case OPCODE_PUSH:
      // PUSH REG
      _push(dest);
      break;
    case OPCODE_POP:
      // POP REG
      _registers[reg1] = _pop();
      break;
    case OPCODE_ADD:
      // ADD DEST SRC
      _registers[reg1] += src;
      // Set flags
      result = dest + src;
      clearFlags = false;
      break;
    case OPCODE_SUB:
      // SUB DEST SRC
      _registers[reg1] -= src;
      // Set flags
      result = dest - src;
      clearFlags = false;
      break;
    case OPCODE_MUL:
      // MUL DEST SRC
      _registers[reg1] *= src;
      // Set flags
      result = dest * src;
      clearFlags = false;
      break;
    case OPCODE_DIV:
      // DIV DEST SRC
      // Check for divide by zero error, in which case we set the
      // destination to all ones.
      if (0 == src) {
        _registers[reg1] = 0xffff;
      } else {
        _registers[reg1] /= src;
        // Set flags
        result = dest / src;
        clearFlags = false;
      }
      break;
    case OPCODE_AND:
      // AND DEST SRC
      _registers[reg1] &= src;
      // Set flags
      result = dest & src;
      clearFlags = false;
      break;
    case OPCODE_OR:
      // OR DEST SRC
      _registers[reg1] |= src;
      // Set flags
      result = dest | src;
      clearFlags = false;
      break;
    case OPCODE_XOR:
      // XOR DEST SRC
      _registers[reg1] ^= src;
      // Set flags
      result = dest ^ src;
      clearFlags = false;
      break;
    case OPCODE_SHL:
      // SHL DEST SRC
      _registers[reg1] <<= src;
      // Set flags
      result = dest << src;
      clearFlags = false;
      break;
    case OPCODE_SHRA:
      // SHRA DEST SRC
      // Arithmetic right shift, we have to make sure to sign extend
      _registers[reg1] = (uint16_t)((int16_t)dest >> src);
      // Set flags
      result = (uint32_t)((int32_t)dest >> src);
      clearFlags = false;
      break;
    case OPCODE_SHRL:
      // SHRL DEST SRC
      // Logical right shift, no sign extend
      _registers[reg1] >>= src;
      // Set flags
      result = dest >> src;
      clearFlags = false;
      break;
    case OPCODE_CMP:
      // CMP DEST SRC
      // Does DEST - SRC and sets flags.
      result = dest - src;
      clearFlags = false;
      break;
    case OPCODE_TST:
      // TST DEST SRC
      // Do DEST & SRC and set the flags, but discard the result.
      result = dest & src;
      clearFlags = false;
      break;
    case OPCODE_COLOR:
      // COLOR REG
      // Sets the value of the color register equal to the value
      // of the argument register.
      _colorRegister = (uint8_t)_registers[reg1];
      break;
    case OPCODE_PIXEL:
      // PIXEL X Y
      // Sets the point (X, Y) equal to the value of the color register
      _window->setPixel(_registers[reg1], _registers[reg2], _colorRegister);
      break;
    case OPCODE_STOR:
      // STOR DEST SRC
      // DEST is the value you are storing, SRC is the address you
      // are storing it to.
      _mainMem[src] = dest >> 8;
      _mainMem[src+1] = dest & 0xff;
      break;
    case OPCODE_STORI:
      // STORI DEST ADDR
      // Store the value in DEST to the literal address in main memory.
      _mainMem[argB] = dest >> 8;
      _mainMem[argB+1] = dest & 0xff;
      break;
    case OPCODE_TIME:
      // TIME DEST
      // Store the time since last TIMERST (in milliseconds) into DEST
      _registers[reg1] = ((clock() - timeSinceRst) * 1000) / CLOCKS_PER_SEC;
      break;
    case OPCODE_TIMERST:
      // Resets the timer to 0
      timeSinceRst = clock();
      break;
    case OPCODE_RND:
      // RND DEST
      // Gets a random 16-bit value and stores it in DEST
      _registers[reg1] = rand() & 0xffff;
      break;
    case OPCODE_JMP:
      // JMP REG
      // Jumps to the address value in REG.
      nextInstPtr = _registers[reg1];
      break;
    case OPCODE_JMPI:
      // JMPI ADDR
      // Unconditional jump to ADDR.
      nextInstPtr = argA;
      break;
    case OPCODE_JEQ:
      // JEQ ADDR
      if (_zeroFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JNE:
      // JNE ADDR
      if (!_zeroFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JG:
      // JG ADDR
      if (!_zeroFlag && _signFlag == _overflowFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JGE:
      // JGE ADDR
      if (_signFlag == _overflowFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JA:
      // JA ADDR
      if (!_carryFlag && !_zeroFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JAE:
      // JAE ADDR
      if (!_carryFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JL:
      // JL ADDR
      if (_signFlag != _overflowFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JLE:
      // JLE ADDR
      if (_signFlag != _overflowFlag || _zeroFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JB:
      // JB ADDR
      if (_carryFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JBE:
      // JBE ADDR
      if (_carryFlag || _zeroFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JO:
      // JO ADDR
      if (_overflowFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JNO:
      // JNO ADDR
      if (!_overflowFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JS:
      // JS ADDR
      if (_signFlag) {
        nextInstPtr = argA;
      }
      break;
    case OPCODE_JNS:
      // JNS
      if (!_signFlag) {
        nextInstPtr = argA;
      }
      break;
    }

    // Set the instruction pointer to its new position
    _setInstructionPointer(nextInstPtr);
    // Clear the flags if they were not set somewhere else
    if (clearFlags) {
      _overflowFlag = false;
      _carryFlag = false;
      _zeroFlag = false;
      _signFlag = false;
    } else {
      _setFlags(dest, src, result, opcode);
    }
  }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0x60, %rsp
movq %rdi, -0x8(%rbp)
movq -0x8(%rbp), %rax
movq %rax, -0x48(%rbp)
callq 0x31c0
movq %rax, -0x10(%rbp)
xorl %eax, %eax
movl %eax, %edi
callq 0x3290
movl %eax, %edi
callq 0x32b0
movq -0x48(%rbp), %rax
testb $0x1, 0x10030(%rax)
je 0x9488
movq -0x48(%rbp), %rax
movzwl 0x10028(%rax), %ecx
leaq 0x8(%rax,%rcx), %rcx
movq %rcx, -0x18(%rbp)
movq -0x18(%rbp), %rcx
movb (%rcx), %cl
movb %cl, -0x19(%rbp)
movq -0x18(%rbp), %rcx
movb 0x1(%rcx), %cl
movb %cl, -0x1a(%rbp)
movq -0x18(%rbp), %rcx
movb 0x2(%rcx), %cl
movb %cl, -0x1b(%rbp)
movb -0x1a(%rbp), %cl
andb $0xf, %cl
movb %cl, -0x1c(%rbp)
movb -0x1b(%rbp), %cl
andb $0xf, %cl
movb %cl, -0x1d(%rbp)
movq -0x18(%rbp), %rdx
movzbl 0x1(%rdx), %ecx
shll $0x8, %ecx
movzbl 0x2(%rdx), %edx
orl %edx, %ecx
movw %cx, -0x20(%rbp)
movq -0x18(%rbp), %rdx
movzbl 0x2(%rdx), %ecx
shll $0x8, %ecx
movzbl 0x3(%rdx), %edx
orl %edx, %ecx
movw %cx, -0x22(%rbp)
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %ecx
movl %ecx, -0x28(%rbp)
movzbl -0x1d(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %ecx
movl %ecx, -0x2c(%rbp)
movl 0x10028(%rax), %eax
addl $0x4, %eax
movw %ax, -0x32(%rbp)
movb $0x1, -0x33(%rbp)
movzbl -0x19(%rbp), %eax
movq %rax, -0x50(%rbp)
subq $0x3f, %rax
ja 0x8d7e
movq -0x50(%rbp), %rax
leaq 0x14bd(%rip), %rcx      # 0xa230
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
jmp 0x8d7e
jmp 0x9435
movq -0x48(%rbp), %rax
movq (%rax), %rdi
movl -0x2c(%rbp), %eax
movw %ax, -0x36(%rbp)
leaq -0x36(%rbp), %rsi
callq 0x5660
movw %ax, %dx
movq -0x48(%rbp), %rax
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rdi
movq %rdi, %rsi
addq $0x10028, %rsi          # imm = 0x10028
callq 0x89c0
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rdi
callq 0x8a20
movw %ax, %cx
movq -0x48(%rbp), %rax
movzwl %cx, %ecx
addl $0x4, %ecx
movw %cx, -0x32(%rbp)
movzbl -0x1a(%rbp), %edx
movzwl 0x10008(%rax), %ecx
subl %edx, %ecx
movw %cx, 0x10008(%rax)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %ecx
movzbl 0x8(%rax,%rcx), %ecx
shll $0x8, %ecx
movl -0x2c(%rbp), %edx
addl $0x1, %edx
movl %edx, %edx
movzbl 0x8(%rax,%rdx), %edx
orl %edx, %ecx
movw %cx, %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rax
movzwl -0x22(%rbp), %ecx
movzbl 0x8(%rax,%rcx), %ecx
shll $0x8, %ecx
movzwl -0x22(%rbp), %edx
addl $0x1, %edx
movslq %edx, %rdx
movzbl 0x8(%rax,%rdx), %edx
orl %edx, %ecx
movw %cx, %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %ecx
movw %cx, %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rax
movw -0x22(%rbp), %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rdi
movl -0x28(%rbp), %eax
movw %ax, -0x38(%rbp)
leaq -0x38(%rbp), %rsi
callq 0x89c0
jmp 0x9435
movq -0x48(%rbp), %rdi
callq 0x8a20
movw %ax, %dx
movq -0x48(%rbp), %rax
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %edx
addl %esi, %edx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
addl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %edx
subl %esi, %edx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
subl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %edx
imull %esi, %edx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
imull -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
xorl %eax, %eax
cmpl -0x2c(%rbp), %eax
jne 0x8f84
movq -0x48(%rbp), %rax
movzbl -0x1c(%rbp), %ecx
movw $0xffff, 0x10008(%rax,%rcx,2) # imm = 0xFFFF
jmp 0x8fb8
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %eax
xorl %edx, %edx
divl %esi
movl %eax, %edx
movq -0x48(%rbp), %rax
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
xorl %edx, %edx
divl -0x2c(%rbp)
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %edx
andl %esi, %edx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
andl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %edx
orl %esi, %edx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
orl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %esi
movzbl -0x1c(%rbp), %ecx
movzwl 0x10008(%rax,%rcx,2), %edx
xorl %esi, %edx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
xorl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %ecx
movzbl -0x1c(%rbp), %edx
movq %rdx, -0x58(%rbp)
movzwl 0x10008(%rax,%rdx,2), %edx
shll %cl, %edx
movq -0x58(%rbp), %rcx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
movl -0x2c(%rbp), %ecx
shll %cl, %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x28(%rbp), %ecx
movswl %cx, %edx
movl -0x2c(%rbp), %ecx
sarl %cl, %edx
movl %edx, %ecx
movw %cx, %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
movl -0x2c(%rbp), %ecx
sarl %cl, %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x2c(%rbp), %ecx
movzbl -0x1c(%rbp), %edx
movq %rdx, -0x60(%rbp)
movzwl 0x10008(%rax,%rdx,2), %edx
sarl %cl, %edx
movq -0x60(%rbp), %rcx
movw %dx, 0x10008(%rax,%rcx,2)
movl -0x28(%rbp), %eax
movl -0x2c(%rbp), %ecx
shrl %cl, %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movl -0x28(%rbp), %eax
subl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movl -0x28(%rbp), %eax
andl -0x2c(%rbp), %eax
movl %eax, -0x30(%rbp)
movb $0x0, -0x33(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
movzbl -0x1c(%rbp), %ecx
movw 0x10008(%rax,%rcx,2), %cx
movb %cl, 0x1002a(%rax)
jmp 0x9435
movq -0x48(%rbp), %rcx
movq (%rcx), %rdi
movzbl -0x1c(%rbp), %eax
movw 0x10008(%rcx,%rax,2), %ax
movb %al, -0x39(%rbp)
movzbl -0x1d(%rbp), %eax
movw 0x10008(%rcx,%rax,2), %ax
movb %al, -0x3a(%rbp)
addq $0x1002a, %rcx          # imm = 0x1002A
leaq -0x39(%rbp), %rsi
leaq -0x3a(%rbp), %rdx
callq 0x5620
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x28(%rbp), %ecx
shrl $0x8, %ecx
movb %cl, %dl
movl -0x2c(%rbp), %ecx
movb %dl, 0x8(%rax,%rcx)
movl -0x28(%rbp), %ecx
andl $0xff, %ecx
movb %cl, %dl
movl -0x2c(%rbp), %ecx
addl $0x1, %ecx
movl %ecx, %ecx
movb %dl, 0x8(%rax,%rcx)
jmp 0x9435
movq -0x48(%rbp), %rax
movl -0x28(%rbp), %ecx
shrl $0x8, %ecx
movb %cl, %dl
movzwl -0x22(%rbp), %ecx
movb %dl, 0x8(%rax,%rcx)
movl -0x28(%rbp), %ecx
andl $0xff, %ecx
movb %cl, %dl
movzwl -0x22(%rbp), %ecx
addl $0x1, %ecx
movslq %ecx, %rcx
movb %dl, 0x8(%rax,%rcx)
jmp 0x9435
callq 0x31c0
subq -0x10(%rbp), %rax
imulq $0x3e8, %rax, %rax      # imm = 0x3E8
movl $0xf4240, %ecx          # imm = 0xF4240
cqto
idivq %rcx
movq %rax, %rcx
movq -0x48(%rbp), %rax
movw %cx, %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
callq 0x31c0
movq %rax, -0x10(%rbp)
jmp 0x9435
callq 0x3080
movl %eax, %ecx
movq -0x48(%rbp), %rax
andl $0xffff, %ecx           # imm = 0xFFFF
movw %cx, %dx
movzbl -0x1c(%rbp), %ecx
movw %dx, 0x10008(%rax,%rcx,2)
jmp 0x9435
movq -0x48(%rbp), %rax
movzbl -0x1c(%rbp), %ecx
movw 0x10008(%rax,%rcx,2), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002d(%rax)
je 0x9271
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002d(%rax)
jne 0x928b
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002d(%rax)
jne 0x92c4
movq -0x48(%rbp), %rcx
movb 0x1002e(%rcx), %al
andb $0x1, %al
movzbl %al, %eax
movb 0x1002b(%rcx), %cl
andb $0x1, %cl
movzbl %cl, %ecx
cmpl %ecx, %eax
jne 0x92c4
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rcx
movb 0x1002e(%rcx), %al
andb $0x1, %al
movzbl %al, %eax
movb 0x1002b(%rcx), %cl
andb $0x1, %cl
movzbl %cl, %ecx
cmpl %ecx, %eax
jne 0x92f0
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002c(%rax)
jne 0x9317
movq -0x48(%rbp), %rax
testb $0x1, 0x1002d(%rax)
jne 0x9317
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002c(%rax)
jne 0x9331
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rcx
movb 0x1002e(%rcx), %al
andb $0x1, %al
movzbl %al, %eax
movb 0x1002b(%rcx), %cl
andb $0x1, %cl
movzbl %cl, %ecx
cmpl %ecx, %eax
je 0x935d
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rcx
movb 0x1002e(%rcx), %al
andb $0x1, %al
movzbl %al, %eax
movb 0x1002b(%rcx), %cl
andb $0x1, %cl
movzbl %cl, %ecx
cmpl %ecx, %eax
jne 0x938e
movq -0x48(%rbp), %rax
testb $0x1, 0x1002d(%rax)
je 0x9396
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002c(%rax)
je 0x93b0
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002c(%rax)
jne 0x93cf
movq -0x48(%rbp), %rax
testb $0x1, 0x1002d(%rax)
je 0x93d7
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002b(%rax)
je 0x93ee
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002b(%rax)
jne 0x9405
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002e(%rax)
je 0x941c
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rax
testb $0x1, 0x1002e(%rax)
jne 0x9433
movw -0x20(%rbp), %ax
movw %ax, -0x32(%rbp)
jmp 0x9435
movq -0x48(%rbp), %rdi
leaq -0x32(%rbp), %rsi
callq 0x8a70
testb $0x1, -0x33(%rbp)
je 0x946a
movq -0x48(%rbp), %rax
movb $0x0, 0x1002b(%rax)
movb $0x0, 0x1002c(%rax)
movb $0x0, 0x1002d(%rax)
movb $0x0, 0x1002e(%rax)
jmp 0x9483
movq -0x48(%rbp), %rdi
leaq -0x28(%rbp), %rsi
leaq -0x2c(%rbp), %rdx
leaq -0x30(%rbp), %rcx
leaq -0x19(%rbp), %r8
callq 0x8aa0
jmp 0x8cad
addq $0x60, %rsp
popq %rbp
retq
nop