// File: /workspace/github_cpp_makefile_star2_O3/pollow[P]MIPSClide/instruction.cpp
// Function: Instruction::compile()
unsigned int Instruction::compile() {
    unsigned long result = 0;
    if ( !opcode.count(command) ) {
        throw invalid_argument("No such command"); 
    }
    switch ( type ) {
        case 'R':
            result += opcode[command] << 26;
            if (reg_num == 1) {
                if ( !regs.count(reg1) ) {
                    throw invalid_argument("No such register"); 
                }
                if ( command == "mfhi" || command == "mflo" ) {
                    result += regs[reg1] << 11;
                } else {
                    result += regs[reg1] << 21;
                }
            } else if ( reg_num == 2 ) {
                if ( !(regs.count(reg1) && regs.count(reg2)) ) {
                    throw invalid_argument("No such register"); 
                }
                if(has_shamt) {
                    result += (regs[reg1] << 11) + (regs[reg2] << 16);
                    result += shamt << 6;
                } else if ( command == "jarl" ) {
                    result += (regs[reg1] << 21) + (regs[reg2] << 11);
                } else if ( command == "clo" || command == "clz" ) {
                    result += (regs[reg1] << 11) + (regs[reg2] << 21);
                } else {
                    result += (regs[reg1] << 21) + (regs[reg2] << 16);
                }
            } else {
                if ( !(regs.count(reg1) && regs.count(reg2) && regs.count(reg3)) ) {
                    throw invalid_argument("No such register"); 
                }
                result += (regs[reg1] << 11) + (regs[reg2] << 21) + (regs[reg3] << 16);
            }
            result += func[command];
            break;
        case 'I':
            result += opcode[command] << 26;
            if (reg_num == 1) {
                if (command == "lui") result += regs[reg1] << 16;
                else result += regs[reg1] << 21;
            }
            if (reg_num == 2) {
                if (command == "beq" || command == "bne") {
                    result += regs[reg2] << 16;
                    result += regs[reg1] << 21;
                } else {
                    result += regs[reg1] << 16;
                    result += regs[reg2] << 21;
                }
            }
            result += imm;
            break;
        case 'J':
            result += opcode[command] << 26;
            result += imm;
            break;
    }

    return result;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0xec4c(%rip), %rdi      # 0x2b970
movq %rbx, %rsi
callq 0x2033e
leaq 0xec45(%rip), %rcx      # 0x2b978
cmpq %rcx, %rax
je 0x1d136
movzbl 0x90(%rbx), %eax
cmpl $0x49, %eax
je 0x1ce22
cmpl $0x4a, %eax
je 0x1cdfe
xorl %r14d, %r14d
cmpl $0x52, %eax
jne 0x1d124
leaq 0xec08(%rip), %rdi      # 0x2b970
movq %rbx, %rsi
callq 0x1f9bc
movl (%rax), %r13d
shll $0x1a, %r13d
movl 0x80(%rbx), %r15d
leaq 0x20(%rbx), %r14
leaq 0xed97(%rip), %rdi      # 0x2bb20
movq %r14, %rsi
callq 0x2033e
cmpl $0x2, %r15d
je 0x1ced2
cmpl $0x1, %r15d
jne 0x1cf54
leaq 0xed7c(%rip), %rcx      # 0x2bb28
cmpq %rcx, %rax
je 0x1d1a4
leaq 0x553e(%rip), %rsi      # 0x222fa
movq %rbx, %rdi
callq 0x50b0
testl %eax, %eax
je 0x1cfe7
leaq 0x552c(%rip), %rsi      # 0x222ff
movq %rbx, %rdi
callq 0x50b0
testl %eax, %eax
je 0x1cfe7
leaq 0xed36(%rip), %rdi      # 0x2bb20
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r14d
shll $0x15, %r14d
jmp 0x1cffd
leaq 0xeb6b(%rip), %rdi      # 0x2b970
movq %rbx, %rsi
callq 0x1f9bc
movl (%rax), %eax
shll $0x1a, %eax
movzwl 0x88(%rbx), %r14d
orl %eax, %r14d
jmp 0x1d124
leaq 0xeb47(%rip), %rdi      # 0x2b970
movq %rbx, %rsi
callq 0x1f9bc
movl (%rax), %r12d
shll $0x1a, %r12d
movl 0x80(%rbx), %eax
cmpl $0x1, %eax
jne 0x1ce80
leaq 0x54d2(%rip), %rsi      # 0x2231c
movq %rbx, %rdi
callq 0x50b0
movl %eax, %r14d
leaq 0x20(%rbx), %rsi
leaq 0xecc0(%rip), %rdi      # 0x2bb20
callq 0x1f9bc
xorl %ecx, %ecx
testl %r14d, %r14d
movl (%rax), %eax
setne %cl
leal (%rcx,%rcx,4), %ecx
addl $0x10, %ecx
shll %cl, %eax
addl %eax, %r12d
movl 0x80(%rbx), %eax
cmpl $0x2, %eax
jne 0x1d044
leaq 0x5442(%rip), %rsi      # 0x222d2
movq %rbx, %rdi
callq 0x50b0
testl %eax, %eax
je 0x1d005
leaq 0x542f(%rip), %rsi      # 0x222d6
movq %rbx, %rdi
callq 0x50b0
xorl %r14d, %r14d
xorl %esi, %esi
testl %eax, %eax
setne %r14b
sete %sil
shll $0x5, %esi
addq $0x20, %rsi
shll $0x5, %r14d
addq $0x20, %r14
jmp 0x1d010
leaq 0xec4f(%rip), %r12      # 0x2bb28
cmpq %r12, %rax
je 0x1d186
leaq 0x40(%rbx), %r15
leaq 0xec33(%rip), %rdi      # 0x2bb20
movq %r15, %rsi
callq 0x2033e
cmpq %r12, %rax
je 0x1d186
cmpb $0x1, 0x91(%rbx)
jne 0x1d054
leaq 0xec0e(%rip), %r12      # 0x2bb20
movq %r12, %rdi
movq %r14, %rsi
callq 0x1f9bc
movl %r13d, %r14d
movl (%rax), %r13d
shll $0xb, %r13d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1f9bc
movl (%rax), %eax
shll $0x10, %eax
addl %r14d, %r13d
addl %eax, %r13d
movl 0x86(%rbx), %r14d
andl $0x1f, %r14d
shll $0x6, %r14d
orl %r13d, %r14d
jmp 0x1d112
movl %r13d, -0x2c(%rbp)
leaq 0xebc9(%rip), %r13      # 0x2bb28
cmpq %r13, %rax
je 0x1d168
leaq 0x40(%rbx), %r15
leaq 0xebad(%rip), %rdi      # 0x2bb20
movq %r15, %rsi
callq 0x2033e
cmpq %r13, %rax
je 0x1d168
leaq 0x60(%rbx), %r12
leaq 0xeb91(%rip), %rdi      # 0x2bb20
movq %r12, %rsi
callq 0x2033e
cmpq %r13, %rax
je 0x1d168
leaq 0xeb79(%rip), %r13      # 0x2bb20
movq %r13, %rdi
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r14d
shll $0xb, %r14d
movq %r13, %rdi
movq %r15, %rsi
callq 0x1f9bc
movl (%rax), %r15d
shll $0x15, %r15d
movq %r13, %rdi
movq %r12, %rsi
callq 0x1f9bc
movl (%rax), %eax
shll $0x10, %eax
addl %r15d, %eax
addl -0x2c(%rbp), %r14d
jmp 0x1d10f
leaq 0xeb32(%rip), %rdi      # 0x2bb20
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r14d
shll $0xb, %r14d
addl %r13d, %r14d
jmp 0x1d112
movl $0x20, %r14d
movl $0x40, %esi
addq %rbx, %rsi
leaq 0xeb06(%rip), %r15      # 0x2bb20
movq %r15, %rdi
callq 0x1f9bc
movl (%rax), %r13d
shll $0x10, %r13d
addl %r12d, %r13d
addq %rbx, %r14
movq %r15, %rdi
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r12d
shll $0x15, %r12d
addl %r13d, %r12d
movzwl 0x88(%rbx), %r14d
addl %r12d, %r14d
jmp 0x1d124
leaq 0x5344(%rip), %rsi      # 0x2239f
movq %rbx, %rdi
callq 0x50b0
testl %eax, %eax
je 0x1d0e3
leaq 0x529a(%rip), %rsi      # 0x22308
movq %rbx, %rdi
callq 0x50b0
testl %eax, %eax
je 0x1d0b8
leaq 0x528b(%rip), %rsi      # 0x2230c
movq %rbx, %rdi
callq 0x50b0
testl %eax, %eax
je 0x1d0b8
leaq 0xea8c(%rip), %r12      # 0x2bb20
movq %r12, %rdi
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r14d
shll $0x15, %r14d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1f9bc
movl (%rax), %eax
shll $0x10, %eax
jmp 0x1d10c
leaq 0xea61(%rip), %r12      # 0x2bb20
movq %r12, %rdi
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r14d
shll $0xb, %r14d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1f9bc
movl (%rax), %eax
shll $0x15, %eax
jmp 0x1d10c
leaq 0xea36(%rip), %r12      # 0x2bb20
movq %r12, %rdi
movq %r14, %rsi
callq 0x1f9bc
movl (%rax), %r14d
shll $0x15, %r14d
movq %r12, %rdi
movq %r15, %rsi
callq 0x1f9bc
movl (%rax), %eax
shll $0xb, %eax
addl %r13d, %r14d
addl %eax, %r14d
leaq 0xe9d7(%rip), %rdi      # 0x2baf0
movq %rbx, %rsi
callq 0x1f9bc
addl (%rax), %r14d
movl %r14d, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl $0x10, %edi
callq 0x5180
movq %rax, %rbx
leaq 0x5234(%rip), %rsi      # 0x2237e
movq %rax, %rdi
callq 0x55d0
movq 0xde77(%rip), %rsi      # 0x2afd0
movq 0xde58(%rip), %rdx      # 0x2afb8
movq %rbx, %rdi
callq 0x5510
movl $0x10, %edi
callq 0x5180
movq %rax, %rbx
leaq 0x5212(%rip), %rsi      # 0x2238e
movq %rax, %rdi
callq 0x55d0
jmp 0x1d152
movl $0x10, %edi
callq 0x5180
movq %rax, %rbx
leaq 0x51f4(%rip), %rsi      # 0x2238e
movq %rax, %rdi
callq 0x55d0
jmp 0x1d152
movl $0x10, %edi
callq 0x5180
movq %rax, %rbx
leaq 0x51d6(%rip), %rsi      # 0x2238e
movq %rax, %rdi
callq 0x55d0
jmp 0x1d152
jmp 0x1d1c8
jmp 0x1d1c8
jmp 0x1d1c8
movq %rax, %r14
movq %rbx, %rdi
callq 0x5260
movq %r14, %rdi
callq 0x5560
nop