// File: CMU-SAFARI[P]Register-Interval/main.cpp
// Function: main
int main(int argc, char **argv)
{
	int REGNUM=atoi(argv[1]); //REGNUM is the allowed number of registers in register-intervals

        //At first the graphviz dot code (the output of nvidisasm tool) will be parsed and the CFG will be generated.
	vector<basicBlock*> basic_blocks = create_control_flow_graph(argv[2]);
        
        basic_blocks_log(basic_blocks, argv[2]);//generates a log file

        //Register-interval creation algorithm (pass one) will construct the initial register-intervals from basic blocks and CFG
	auto intervals = RegisterIntervalCreationPass::registerIntervalCreationPassOne(basic_blocks, REGNUM);

        //In the following loop, pass two of register-interval creation algorithm will be repeated until no changes occur
	int Size, i = 0;
	do
	{
		registerInterval_log(intervals, i++, argv[2]);

		Size = intervals.size();
		intervals = RegisterIntervalCreationPass::registerIntervalCreationPassTwo(intervals, REGNUM);
	} while (intervals.size() < Size); //Pass 2 of register-interval creation algorithm will be done until the CFG can not be reduced anymore

	return 0;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0xf0, %rsp
movl $0x0, -0x4(%rbp)
movl %edi, -0x8(%rbp)
movq %rsi, -0x10(%rbp)
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rdi
callq 0x33b0
movl %eax, -0x14(%rbp)
movq -0x10(%rbp), %rax
movq 0x10(%rax), %rsi
leaq -0x30(%rbp), %rdi
movq %rdi, -0xe0(%rbp)
callq 0x7ff0
movq -0xe0(%rbp), %rsi
leaq -0x48(%rbp), %rdi
callq 0xc370
jmp 0x7e03
movq -0x10(%rbp), %rax
movq 0x10(%rax), %rsi
leaq -0x48(%rbp), %rdi
callq 0x9540
jmp 0x7e16
leaq -0x48(%rbp), %rdi
callq 0xbdd0
leaq -0x88(%rbp), %rdi
leaq -0x30(%rbp), %rsi
callq 0xc370
jmp 0x7e31
movl -0x14(%rbp), %edx
leaq -0x70(%rbp), %rdi
leaq -0x88(%rbp), %rsi
callq 0x46a0
jmp 0x7e46
leaq -0x88(%rbp), %rdi
callq 0xbdd0
movl $0x0, -0x90(%rbp)
leaq -0xa8(%rbp), %rdi
leaq -0x70(%rbp), %rsi
callq 0xbcc0
jmp 0x7e6e
movl -0x90(%rbp), %esi
movl %esi, %eax
incl %eax
movl %eax, -0x90(%rbp)
movq -0x10(%rbp), %rax
movq 0x10(%rax), %rdx
leaq -0xa8(%rbp), %rdi
callq 0x9cb0
jmp 0x7e94
leaq -0xa8(%rbp), %rdi
callq 0xb670
leaq -0x70(%rbp), %rdi
movq %rdi, -0xe8(%rbp)
callq 0xbc10
movq -0xe8(%rbp), %rsi
movl %eax, -0x8c(%rbp)
leaq -0xd8(%rbp), %rdi
callq 0xbcc0
jmp 0x7ecb
movl -0x14(%rbp), %edx
leaq -0xc0(%rbp), %rdi
leaq -0xd8(%rbp), %rsi
callq 0x6710
jmp 0x7ee3
leaq -0x70(%rbp), %rdi
leaq -0xc0(%rbp), %rsi
callq 0xcd70
leaq -0xc0(%rbp), %rdi
callq 0xb670
leaq -0xd8(%rbp), %rdi
callq 0xb670
leaq -0x70(%rbp), %rdi
callq 0xbc10
movslq -0x8c(%rbp), %rcx
cmpq %rcx, %rax
jb 0x7e5c
movl $0x0, -0x4(%rbp)
leaq -0x70(%rbp), %rdi
callq 0xb670
leaq -0x30(%rbp), %rdi
callq 0xbdd0
movl -0x4(%rbp), %eax
addq $0xf0, %rsp
popq %rbp
retq
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x50(%rbp)
movl %eax, -0x54(%rbp)
jmp 0x7fd1
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x50(%rbp)
movl %eax, -0x54(%rbp)
leaq -0x48(%rbp), %rdi
callq 0xbdd0
jmp 0x7fd1
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x50(%rbp)
movl %eax, -0x54(%rbp)
leaq -0x88(%rbp), %rdi
callq 0xbdd0
jmp 0x7fd1
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x50(%rbp)
movl %eax, -0x54(%rbp)
jmp 0x7fc8
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x50(%rbp)
movl %eax, -0x54(%rbp)
leaq -0xa8(%rbp), %rdi
callq 0xb670
jmp 0x7fc8
movq %rax, %rcx
movl %edx, %eax
movq %rcx, -0x50(%rbp)
movl %eax, -0x54(%rbp)
leaq -0xd8(%rbp), %rdi
callq 0xb670
leaq -0x70(%rbp), %rdi
callq 0xb670
leaq -0x30(%rbp), %rdi
callq 0xbdd0
movq -0x50(%rbp), %rdi
callq 0x3440
nopw %cs:(%rax,%rax)