// File: /workspace/github_c_makefile_star2_O2/michaelforney[P]wld/./intel/blt.h
// Function: xy_setup_blt
static inline void
xy_setup_blt(struct intel_batch *batch,
             bool monochrome_source_transparency,
             uint8_t raster_operation,
             uint32_t background_color,
             uint32_t foreground_color,
             drm_intel_bo *dst, uint16_t dst_pitch)
{
	uint32_t tiling_mode, swizzle_mode;

	intel_batch_ensure_space(batch, GEN(batch, 8) ? 10 : 8);

	drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
	drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
	                              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);

	intel_batch_add_dwords(batch, 4,
	                       BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
	                           | BLT_BR00_OP(BLT_OP_XY_SETUP_BLT)
	                           | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
	                           | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
	                           | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 8 : 6),

	                       BLT_BR01_CLIPPING_ENABLE(false)
	                           | BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency)
	                           | BLT_BR01_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
	                           | BLT_BR01_RASTER_OPERATION(raster_operation)
	                           | BLT_BR01_DST_PITCH(tiling_mode == I915_TILING_NONE
	                                                    ? dst_pitch
	                                                    : dst_pitch >> 2),

	                       /* XXX: No clipping yet */
	                       BLT_BR24_CLP_Y1(0)
	                           | BLT_BR24_CLP_X1(0),

	                       BLT_BR25_CLP_Y2(0)
	                           | BLT_BR25_CLP_X2(0));

	intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
	                       BLT_BR09_DST_ADDRESS(dst->offset64),
	                       /* if gen8 */
	                       BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32));

	intel_batch_add_dwords(batch, 2,
	                       BLT_BR05_BACKGROUND_COLOR(background_color),
	                       BLT_BR06_FOREGROUND_COLOR(foreground_color));

	intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
	                       BLT_BR07_PAT_ADDRESS(0),
	                       /* if gen8 */
	                       BLT_BR30_PAT_ADDRESS_HI(0));
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %r12d
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movq (%rdi), %rax
xorl %ecx, %ecx
cmpl $0x8, (%rax)
setge %cl
leal 0x8(,%rcx,2), %esi
callq 0xb34a
leaq 0x4(%rsp), %r13
movq %rsp, %rdx
movq %r14, %rdi
movq %r13, %rsi
callq 0x9350
movq 0x8(%rbx), %rdi
movl 0x8010(%rbx), %eax
leal 0x10(,%rax,4), %esi
pushq $0x2
popq %r15
movq %r14, %rdx
xorl %ecx, %ecx
movl %r15d, %r8d
movl %r15d, %r9d
callq 0x9740
movl %r12d, %ecx
shrl $0x2, %ecx
xorl %eax, %eax
cmpl $0x0, (%r13)
setne %al
movq (%rbx), %rdx
cmovel %r12d, %ecx
shll $0xb, %eax
xorl %esi, %esi
cmpl $0x8, (%rdx)
setge %sil
leal (%rax,%rsi,2), %edx
addl $0x40700006, %edx       # imm = 0x40700006
orl $0x23cc0000, %ecx       # imm = 0x23CC0000
pushq $0x4
popq %rsi
movq %rbx, %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
xorl %eax, %eax
callq 0xb35e
movq (%rbx), %rax
xorl %esi, %esi
cmpl $0x8, (%rax)
setge %sil
incl %esi
movq 0x30(%r14), %rdx
movq %rdx, %rcx
shrq $0x20, %rcx
movq %rbx, %rdi
xorl %eax, %eax
callq 0xb35e
movq %rbx, %rdi
movl %r15d, %esi
xorl %edx, %edx
movl %ebp, %ecx
xorl %eax, %eax
callq 0xb35e
movq (%rbx), %rax
xorl %esi, %esi
cmpl $0x8, (%rax)
setge %sil
incl %esi
movq %rbx, %rdi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %eax, %eax
callq 0xb35e
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq