// File: /workspace/github_cpp_makefile_star2_O2/gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::handleAccess(Access)
allocDecision
HybridCache::handleAccess(Access element)
{
	uint64_t address = element.m_address;
	bool isWrite = element.isWrite();
 	int size = element.m_size;
	RD_TYPE rd_type = RD_NOT_ACCURATE;
	
	if(!m_isWarmup)
		stats_operations[element.m_type]++;
	
	assert(size > 0);
	
	uint64_t block_addr = bitRemove(address , 0 , m_start_index+1);
	element.block_addr = block_addr;
	
	int id_set = addressToCacheSet(address);

	int stats_index = isWrite ? 1 : 0;

	CacheEntry* current = getEntry(block_addr);
	allocDecision des = ALLOCATE_IN_SRAM;
	
	if(current == NULL){ // The cache line is not in the hybrid cache, Miss !
				
		CacheEntry* destination_entry = NULL;
		
		des = m_predictor->allocateInNVM(id_set, element);
		element.isSRAMerror = m_predictor->reportMiss(block_addr , id_set);

//		m_predictor->recordAllocationDecision(id_set, element, des);
		
		if(des == BYPASS_CACHE )
		{
			entete_debug();
			DPRINTF(DebugCache , "Bypassing the cache for this \n");
			if(!m_isWarmup)
				stats_bypass++;
			if( element.isDemandAccess())
				stats_demand_BP++;
			else
				stats_WB_BP++;
		}
		else
		{
		
			//Verify if the cache line is in missing tags 
			bool inNVM = (des == ALLOCATE_IN_NVM) ? true : false; 
			int id_assoc = -1;
			
			if( element.isDemandAccess())
				stats_allocateDemand++;
			else
				stats_allocateWB++;
					
			id_assoc = m_predictor->evictPolicy(id_set, inNVM);	
			
			if(inNVM){//New line allocated in NVM
				destination_entry = m_tableNVM[id_set][id_assoc];
			}
			else{//Allocated in SRAM 
				destination_entry = m_tableSRAM[id_set][id_assoc];
			}
				
			//Deallocate the cache line in the lower levels (inclusive system)
			if(destination_entry->isValid){


				if(simu_parameters.traceLLC && m_ID == -1)
				{
					string line =  "EVICT " + convert_hex(destination_entry->address);
					//cout << "Writing to LLC_trace.out: " <<  line << endl;
					gzwrite(LLC_trace, line.c_str() , LLC_TRACE_BUFFER_SIZE);	
				}


				entete_debug();
				DPRINTF(DebugCache , "Invalidation of the cache line : %#lx , id_assoc %d\n" , destination_entry->address,id_assoc);
				//Prevent the cache line from being migrated du to WBs 
				//Inform the higher level of the deallocation
				if(simu_parameters.strongInclusivity)	
					m_system->signalDeallocate(destination_entry->address); 
				
				//WB this cache line to the lower cache 			
				Access wb_request;
				wb_request.m_address = destination_entry->address;
				wb_request.m_size = 4;
				wb_request.m_pc = destination_entry->m_pc;
				if(destination_entry->isDirty)
					wb_request.m_type = MemCmd::DIRTY_WRITEBACK;
				else
					wb_request.m_type = MemCmd::CLEAN_WRITEBACK;

				signalWB(wb_request, false);	
				
				if(!m_isWarmup)
					stats_evict++;
		
			}


			
			deallocate(destination_entry);
			allocate(address , id_set , id_assoc, inNVM, element.m_pc, element.isPrefetch());			
			m_predictor->insertionPolicy(id_set , id_assoc , inNVM, element);
			


			if(inNVM){
				entete_debug();
				DPRINTF(DebugCache , "It is a Miss ! Block[%#lx] is allocated \
						 in the NVM cache : Set=%d, Way=%d\n", block_addr , id_set, id_assoc);
				if(!m_isWarmup)
				{
					stats_missNVM[stats_index]++;
					stats_hitsNVM[1]++; // The insertion write 
				}

				if(element.isWrite())
					m_tableNVM[id_set][id_assoc]->isDirty = true;			
							
				m_tableNVM[id_set][id_assoc]->coherence_state = COHERENCE_EXCLUSIVE;					
				m_tableNVM[id_set][id_assoc]->m_compilerHints = element.m_compilerHints;
			
				if(simu_parameters.enablePCHistoryTracking && m_printStats)
					m_tableNVM[id_set][id_assoc]->pc_history.push_back(element.m_pc);
			}
			else{
				entete_debug();
				DPRINTF(DebugCache , "It is a Miss ! Block[%#lx] is allocated \
						in the SRAM cache : Set=%d, Way=%d\n",block_addr, id_set, id_assoc);
				if(!m_isWarmup){				
					stats_missSRAM[stats_index]++;			
					stats_hitsSRAM[1]++; // The insertion write 
				}
			
				if(element.isWrite())
					m_tableSRAM[id_set][id_assoc]->isDirty = true;

				m_tableSRAM[id_set][id_assoc]->coherence_state = COHERENCE_EXCLUSIVE;
				m_tableSRAM[id_set][id_assoc]->m_compilerHints = element.m_compilerHints;

				if(simu_parameters.enablePCHistoryTracking&& m_printStats)
					m_tableSRAM[id_set][id_assoc]->pc_history.push_back(element.m_pc);
			}
		}
	}
	else{
		// It is a hit in the cache 		
		int id_assoc = -1;
		map<uint64_t,HybridLocation>::iterator p = m_tag_index.find(current->address);
		id_assoc = p->second.m_way;
		string a = current->isNVM ? "in NVM" : "in SRAM";

		entete_debug();
		DPRINTF(DebugCache , "It is a hit ! Block[%#lx] Found %s Set=%d, Way=%d, Req=%s\n" \
				 , block_addr, a.c_str(), id_set, id_assoc , memCmd_str[element.m_type]);
		
		m_predictor->updatePolicy(id_set , id_assoc, current->isNVM, element , false);
		
		current->justMigrate = false;
		if(element.isWrite()){
			current->isDirty = true;
			current->nbWrite++;
			current->coherence_state = COHERENCE_MODIFIED;
		}
		else{
			//current->coherence_state stays in the same state in any case 
			if(element.m_type != CLEAN_WRITEBACK)
				current->nbRead++;		
		}

		if(simu_parameters.enablePCHistoryTracking && m_printStats)
			current->pc_history.push_back(element.m_pc);
	
		if(!m_isWarmup)
		{
			if(current->isNVM)	
				stats_hitsNVM[stats_index]++;
			else
				stats_hitsSRAM[stats_index]++;
		
		}
		
		
		current->m_compilerHints = element.m_compilerHints;
	
		if(simu_parameters.traceLLC && m_ID == -1)
			rd_type = classifyRD(id_set , id_assoc);	
	}
	
	if(simu_parameters.traceLLC && m_ID == -1 && des != BYPASS_CACHE)
	{
		string access = element.isWrite() ? "WRITE" : "READ";
		string data_type = element.isInstFetch() ? "INST" : "DATA";
		string line = data_type + " " + access + " " + str_RD_status[rd_type];
		line += " 0x" + convert_hex(block_addr) + " 0x" + convert_hex(element.m_pc);  
		//cout << "Writing to LLC_trace.out: " <<  line << endl;
		gzwrite(LLC_trace, line.c_str() , LLC_TRACE_BUFFER_SIZE);	
	}
	return des;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp            # imm = 0x1A8
movq %rdi, %r14
movq 0x1e0(%rsp), %r13
movl 0x1fc(%rsp), %ecx
cmpq $0x6, %rcx
sete %al
cmpq $0x3, %rcx
sete %bl
movl 0x1e8(%rsp), %edx
cmpb $0x0, 0x91(%rdi)
jne 0x1545e
movq 0x188(%r14), %rsi
incq (%rsi,%rcx,8)
testl %edx, %edx
jle 0x15e2d
leaq 0x1e0(%rsp), %r12
orb %al, %bl
movl 0x94(%r14), %edx
incl %edx
movq %r13, %rdi
xorl %esi, %esi
callq 0x24f70
movq %rax, %r15
movq %rax, 0x30(%r12)
movq %r14, %rdi
movq %r13, %rsi
callq 0x15f56
movq %r13, %r12
movl %eax, %r13d
movq %r14, %rdi
movq %r15, %rsi
callq 0x153ae
movq %rax, %rbp
movslq %r13d, %rsi
movzbl %bl, %eax
movq %rax, 0x90(%rsp)
testq %rbp, %rbp
movq %r15, 0x68(%rsp)
movl %r13d, 0x38(%rsp)
je 0x155fc
movq %rsi, %r12
leaq 0x38(%r14), %rdi
leaq 0x8(%rbp), %rsi
callq 0x1817e
movslq 0x28(%rax), %r13
leaq 0x154a0(%rip), %rax     # 0x2a986
leaq 0x154a0(%rip), %rsi     # 0x2a98d
cmpb $0x0, 0x40(%rbp)
cmovneq %rax, %rsi
leaq 0x40(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x5140
movq %r14, %rdi
callq 0x1529c
leaq 0x1533a(%rip), %rsi     # 0x2a84d
leaq 0x70(%rsp), %rdi
leaq 0x110(%rsp), %rdx
callq 0x5140
leaq 0x28a24(%rip), %r15     # 0x3df50
leaq 0x8(%r15), %rdi
leaq 0x70(%rsp), %rsi
callq 0x138f8
movq %rax, %rbx
leaq 0x70(%rsp), %rdi
callq 0x5618
testq %rbx, %rbx
leaq 0x1e0(%rsp), %rbx
je 0x15581
movq 0x40(%rsp), %rdx
movl 0x1c(%rbx), %eax
leaq 0x27dcd(%rip), %rcx     # 0x3d330
movq (%rcx,%rax,8), %r9
leaq 0x15427(%rip), %rdi     # 0x2a995
movq 0x68(%rsp), %rsi
movl 0x38(%rsp), %ecx
movl %r13d, %r8d
xorl %eax, %eax
callq 0x5040
movq 0x68(%r14), %rdi
movzbl 0x40(%rbp), %ecx
movq (%rdi), %rax
movq 0x18(%rax), %rax
movq 0x30(%rbx), %rdx
movq %rdx, 0x30(%rsp)
movups (%rbx), %xmm0
movups 0x10(%rbx), %xmm1
movups 0x20(%rbx), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq %r12, %rsi
movq %r13, %rdx
xorl %r8d, %r8d
callq *%rax
movb $0x0, 0x14c(%rbp)
leaq 0x1e0(%rsp), %rax
movl 0x1c(%rax), %eax
cmpl $0x6, %eax
je 0x155e6
cmpl $0x5, %eax
je 0x15a22
cmpl $0x3, %eax
jne 0x15a1c
movb $0x1, 0x1(%rbp)
incl 0x11c(%rbp)
andl $0x0, 0x168(%rbp)
jmp 0x15a22
movq %r12, 0xa8(%rsp)
movq 0x68(%r14), %rdi
movq (%rdi), %rax
leaq 0x1e0(%rsp), %rbp
movq 0x30(%rbp), %rcx
movq %rcx, 0x30(%rsp)
movups (%rbp), %xmm0
movups 0x10(%rbp), %xmm1
movups 0x20(%rbp), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq %rsi, 0xa0(%rsp)
callq *0x10(%rax)
movq 0x68(%r14), %rdi
movq %r15, %rsi
movl %eax, %r15d
movl %r13d, %edx
callq 0x1fbb8
movb %al, 0x28(%rbp)
cmpl $0x2, %r15d
jne 0x156e7
movq %r14, %rdi
callq 0x1529c
leaq 0x151de(%rip), %rsi     # 0x2a84d
leaq 0x40(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x5140
leaq 0x288cb(%rip), %rdi     # 0x3df50
addq $0x8, %rdi
leaq 0x40(%rsp), %rsi
callq 0x138f8
movq %rax, %rbx
leaq 0x40(%rsp), %rdi
callq 0x5618
testq %rbx, %rbx
je 0x156b1
leaq 0x156cd(%rip), %rdi     # 0x2ad79
callq 0x5480
cmpb $0x0, 0x91(%r14)
jne 0x156c2
incq 0x108(%r14)
movl 0x1c(%rbp), %eax
pushq $0x2
popq %r15
cmpl $0x3, %eax
ja 0x15b79
cmpl $0x1, %eax
je 0x15b79
incq 0x160(%r14)
jmp 0x15b80
movl 0x1c(%rbp), %eax
movl $0x150, %ecx            # imm = 0x150
cmpq $0x3, %rax
ja 0x15700
leaq 0x1569c(%rip), %rcx     # 0x2ad98
movq (%rcx,%rax,8), %rcx
incq (%r14,%rcx)
movq 0x68(%r14), %rdi
movq (%rdi), %rax
leaq 0x20(%r14), %rbx
leaq 0x8(%r14), %rcx
xorl %edx, %edx
cmpl $0x1, %r15d
cmoveq %rcx, %rbx
sete %dl
movl 0x38(%rsp), %esi
callq *0x28(%rax)
movq (%rbx), %rdx
imulq $0x18, 0xa0(%rsp), %rcx
movl %eax, 0x3c(%rsp)
movslq %eax, %r13
movq %rcx, 0x60(%rsp)
movq (%rdx,%rcx), %rax
movq (%rax,%r13,8), %rbx
cmpb $0x1, (%rbx)
jne 0x158ba
leaq 0x287f9(%rip), %rbp     # 0x3df50
cmpb $0x1, 0x89(%rbp)
jne 0x157b9
cmpl $-0x1, (%r14)
jne 0x157b9
movl 0x8(%rbx), %esi
leaq 0x70(%rsp), %rbp
movq %rbp, %rdi
callq 0x25593
leaq 0x15129(%rip), %rsi     # 0x2a8a6
leaq 0x40(%rsp), %rdi
movq %rbp, %rdx
callq 0x176ad
leaq 0x70(%rsp), %rdi
callq 0x5618
movq 0x282ed(%rip), %rdi     # 0x3da88
movq 0x40(%rsp), %rsi
pushq $0x32
popq %rdx
callq 0x5430
leaq 0x40(%rsp), %rdi
callq 0x5618
leaq 0x28797(%rip), %rbp     # 0x3df50
movq %r14, %rdi
callq 0x1529c
leaq 0x15085(%rip), %rsi     # 0x2a84d
leaq 0x40(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x5140
movq %rbp, %r12
leaq 0x8(%rbp), %rdi
leaq 0x40(%rsp), %rsi
callq 0x138f8
movq %rax, %rbp
leaq 0x40(%rsp), %rdi
callq 0x5618
testq %rbp, %rbp
je 0x15810
movq 0x8(%rbx), %rsi
leaq 0x150a8(%rip), %rdi     # 0x2a8ad
movl 0x3c(%rsp), %edx
xorl %eax, %eax
callq 0x5040
cmpb $0x1, 0x8a(%r12)
jne 0x1582b
movq 0xb8(%r14), %rdi
movq 0x8(%rbx), %rsi
callq 0x194ee
movq 0x8(%rbx), %rax
movq 0x10(%rbx), %rcx
movzbl 0x1(%rbx), %edx
addl $0x5, %edx
movq %rax, 0x130(%rsp)
movl $0x4, 0x138(%rsp)
movq %rcx, 0x140(%rsp)
movl %edx, 0x14c(%rsp)
andl $0x0, 0x150(%rsp)
movb $0x0, 0x158(%rsp)
movq 0x160(%rsp), %rax
movq %rax, 0x30(%rsp)
movups 0x130(%rsp), %xmm0
movups 0x140(%rsp), %xmm1
movups 0x150(%rsp), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq %r14, %rdi
xorl %esi, %esi
callq 0x15fb2
cmpb $0x0, 0x91(%r14)
jne 0x158ba
incq 0x100(%r14)
xorl %ebp, %ebp
cmpl $0x1, %r15d
sete %bpl
movq %r14, %rdi
movq %rbx, %rsi
callq 0x16096
leaq 0x1e0(%rsp), %rbx
leaq 0x10(%rbx), %rax
movq %rax, 0x98(%rsp)
movq 0x10(%rbx), %r9
movl 0x1c(%rbx), %eax
cmpl $0x4, %eax
sete %cl
cmpl $0x1, %eax
sete %al
orb %cl, %al
movzbl %al, %eax
movl %eax, (%rsp)
movq %r14, %rdi
movq 0xa8(%rsp), %rsi
movl 0x38(%rsp), %edx
movl 0x3c(%rsp), %ecx
movl %ebp, %r8d
callq 0x160ec
movq 0x68(%r14), %rdi
movq (%rdi), %rax
movq 0x30(%rbx), %rcx
movq %rcx, 0x30(%rsp)
movups (%rbx), %xmm0
movups 0x10(%rbx), %xmm1
movups 0x20(%rbx), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq 0xa0(%rsp), %rsi
movq %r13, %rdx
movl %ebp, %ecx
callq *0x20(%rax)
movq %r14, %rdi
callq 0x1529c
cmpl $0x1, %r15d
jne 0x15acc
leaq 0x14ee2(%rip), %rsi     # 0x2a84d
leaq 0x40(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x5140
leaq 0x285cf(%rip), %r12     # 0x3df50
leaq 0x8(%r12), %rdi
leaq 0x40(%rsp), %rsi
callq 0x138f8
leaq 0x1e0(%rsp), %rbp
movl 0x38(%rsp), %r15d
movq %rax, %rbx
leaq 0x40(%rsp), %rdi
callq 0x5618
testq %rbx, %rbx
je 0x159c9
leaq 0x14f2c(%rip), %rdi     # 0x2a8e2
movq 0x68(%rsp), %rsi
movl %r15d, %edx
movl 0x3c(%rsp), %ecx
xorl %eax, %eax
callq 0x5040
cmpb $0x0, 0x91(%r14)
jne 0x159f1
movq 0x110(%r14), %rax
movq 0x90(%rsp), %rcx
incq (%rax,%rcx,8)
movq 0x128(%r14), %rax
incq 0x8(%rax)
movl 0x1c(%rbp), %eax
cmpl $0x3, %eax
je 0x15a02
cmpl $0x6, %eax
jne 0x15b85
movq 0x8(%r14), %rax
movq 0x60(%rsp), %rcx
movq (%rax,%rcx), %rax
movq (%rax,%r13,8), %rdi
movb $0x1, 0x1(%rdi)
jmp 0x15b96
incl 0x120(%rbp)
cmpb $0x1, 0x95(%r15)
jne 0x15a51
cmpb $0x1, 0x90(%r14)
jne 0x15a51
movq %rbp, %rdi
addq $0x150, %rdi            # imm = 0x150
leaq 0x1e0(%rsp), %rax
leaq 0x10(%rax), %rsi
callq 0x176d2
cmpb $0x0, 0x91(%r14)
jne 0x15a80
leaq 0xd8(%r14), %rax
leaq 0x128(%r14), %rcx
cmpb $0x0, 0x40(%rbp)
cmovneq %rcx, %rax
movq (%rax), %rax
movq 0x90(%rsp), %rcx
incq (%rax,%rcx,8)
pushq $0x2
popq %rbx
leaq 0x1e0(%rsp), %rax
movl 0x24(%rax), %eax
movl %eax, 0x3c(%rbp)
cmpb $0x1, 0x89(%r15)
jne 0x15ab2
cmpl $-0x1, (%r14)
jne 0x15ab2
movq %r14, %rdi
movl 0x38(%rsp), %esi
movl %r13d, %edx
callq 0x161e4
movl %eax, %ebx
leaq 0x40(%rsp), %rdi
callq 0x5618
xorl %r15d, %r15d
leaq 0x1e0(%rsp), %rbp
jmp 0x15bfc
leaq 0x14d7a(%rip), %rsi     # 0x2a84d
leaq 0x40(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x5140
leaq 0x28467(%rip), %r12     # 0x3df50
leaq 0x8(%r12), %rdi
leaq 0x40(%rsp), %rsi
callq 0x138f8
leaq 0x1e0(%rsp), %rbp
movq %rax, %rbx
leaq 0x40(%rsp), %rdi
callq 0x5618
testq %rbx, %rbx
je 0x15b2d
leaq 0x14e1b(%rip), %rdi     # 0x2a934
movq 0x68(%rsp), %rsi
movl 0x38(%rsp), %edx
movl 0x3c(%rsp), %ecx
xorl %eax, %eax
callq 0x5040
cmpb $0x0, 0x91(%r14)
jne 0x15b55
movq 0xc0(%r14), %rax
movq 0x90(%rsp), %rcx
incq (%rax,%rcx,8)
movq 0xd8(%r14), %rax
incq 0x8(%rax)
movl 0x1c(%rbp), %eax
cmpl $0x3, %eax
je 0x15b62
cmpl $0x6, %eax
jne 0x15baf
movq 0x20(%r14), %rax
movq 0x60(%rsp), %rcx
movq (%rax,%rcx), %rax
movq (%rax,%r13,8), %rdi
movb $0x1, 0x1(%rdi)
jmp 0x15bc0
incq 0x168(%r14)
pushq $0x2
popq %rbx
jmp 0x15bfc
movq 0x8(%r14), %rax
movq 0x60(%rsp), %rcx
movq (%rax,%rcx), %rax
movq (%rax,%r13,8), %rdi
movl $0x1, 0x168(%rdi)
movl 0x24(%rbp), %eax
movl %eax, 0x3c(%rdi)
pushq $0x2
popq %rbx
pushq $0x1
popq %r15
jmp 0x15bd3
movq 0x20(%r14), %rax
movq 0x60(%rsp), %rcx
movq (%rax,%rcx), %rax
movq (%rax,%r13,8), %rdi
movl $0x1, 0x168(%rdi)
movl 0x24(%rbp), %eax
movl %eax, 0x3c(%rdi)
pushq $0x2
popq %rbx
cmpb $0x1, 0x95(%r12)
jne 0x15bfc
cmpb $0x1, 0x90(%r14)
jne 0x15bfc
addq $0x150, %rdi            # imm = 0x150
movq 0x98(%rsp), %rsi
callq 0x176d2
leaq 0x2834d(%rip), %rax     # 0x3df50
cmpb $0x1, 0x89(%rax)
jne 0x15e18
cmpl $0x2, %r15d
je 0x15e18
cmpl $-0x1, (%r14)
jne 0x15e18
movl 0x1c(%rbp), %eax
cmpl $0x6, %eax
leaq 0x16396(%rip), %rcx     # 0x2bfc7
leaq 0x16385(%rip), %rsi     # 0x2bfbd
cmoveq %rcx, %rsi
cmpl $0x3, %eax
cmoveq %rcx, %rsi
leaq 0x40(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x5140
cmpl $0x2, 0x1c(%rbp)
leaq 0x14d73(%rip), %rax     # 0x2a9d0
leaq 0x14d71(%rip), %rsi     # 0x2a9d5
cmovbq %rax, %rsi
leaq 0x70(%rsp), %rdi
leaq 0x110(%rsp), %rdx
callq 0x5140
movq 0x68(%rsp), %r14
leaq 0x13b28(%rip), %rdx     # 0x297ae
leaq 0xb0(%rsp), %rdi
leaq 0x70(%rsp), %rsi
callq 0x9fc4
leaq 0xd0(%rsp), %rdi
leaq 0xb0(%rsp), %rsi
leaq 0x40(%rsp), %rdx
callq 0x176f2
leaq 0x13af5(%rip), %rdx     # 0x297ae
leaq 0xf0(%rsp), %rdi
leaq 0xd0(%rsp), %rsi
callq 0xa0bd
leaq 0x2775b(%rip), %rax     # 0x3d430
movq (%rax,%rbx,8), %rdx
leaq 0x110(%rsp), %rdi
leaq 0xf0(%rsp), %rsi
callq 0xa0bd
leaq 0xf0(%rsp), %rdi
callq 0x5618
leaq 0xd0(%rsp), %rdi
callq 0x5618
leaq 0xb0(%rsp), %rdi
callq 0x5618
leaq 0x188(%rsp), %rdi
movl %r14d, %esi
callq 0x25593
leaq 0x133fb(%rip), %rsi     # 0x29127
leaq 0xb0(%rsp), %rdi
leaq 0x188(%rsp), %rdx
callq 0x176ad
leaq 0x133df(%rip), %rdx     # 0x29127
leaq 0xd0(%rsp), %rdi
leaq 0xb0(%rsp), %rsi
callq 0xa0bd
movl 0x10(%rbp), %esi
leaq 0x168(%rsp), %rdi
callq 0x25593
leaq 0xf0(%rsp), %rdi
leaq 0xd0(%rsp), %rsi
leaq 0x168(%rsp), %rdx
callq 0x17711
leaq 0x110(%rsp), %rdi
leaq 0xf0(%rsp), %rsi
callq 0x55f0
leaq 0xf0(%rsp), %rdi
callq 0x5618
leaq 0x168(%rsp), %rdi
callq 0x5618
leaq 0xd0(%rsp), %rdi
callq 0x5618
leaq 0xb0(%rsp), %rdi
callq 0x5618
leaq 0x188(%rsp), %rdi
callq 0x5618
movq 0x27ca1(%rip), %rdi     # 0x3da88
movq 0x110(%rsp), %rsi
pushq $0x32
popq %rdx
callq 0x5430
leaq 0x110(%rsp), %rdi
callq 0x5618
leaq 0x70(%rsp), %rdi
callq 0x5618
leaq 0x40(%rsp), %rdi
callq 0x5618
movl %r15d, %eax
addq $0x1a8, %rsp            # imm = 0x1A8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x14a39(%rip), %rdi     # 0x2a86d
leaq 0x148f6(%rip), %rsi     # 0x2a731
leaq 0x14a34(%rip), %rcx     # 0x2a876
movl $0x11b, %edx            # imm = 0x11B
callq 0x51e0
jmp 0x15f41
movq %rax, %rbx
leaq 0x70(%rsp), %rdi
jmp 0x15f49
jmp 0x15f41
jmp 0x15f41
jmp 0x15f41
jmp 0x15f3c
jmp 0x15f3c
jmp 0x15f3c
jmp 0x15f41
jmp 0x15f3c
jmp 0x15ee2
movq %rax, %rbx
leaq 0xf0(%rsp), %rdi
callq 0x5618
jmp 0x15e9d
movq %rax, %rbx
leaq 0x168(%rsp), %rdi
callq 0x5618
jmp 0x15eaf
movq %rax, %rbx
leaq 0xd0(%rsp), %rdi
callq 0x5618
jmp 0x15ec1
movq %rax, %rbx
leaq 0xb0(%rsp), %rdi
callq 0x5618
jmp 0x15ed3
movq %rax, %rbx
leaq 0x188(%rsp), %rdi
callq 0x5618
jmp 0x15ee5
movq %rax, %rbx
leaq 0x110(%rsp), %rdi
jmp 0x15f1e
movq %rax, %rbx
leaq 0xf0(%rsp), %rdi
callq 0x5618
jmp 0x15f04
movq %rax, %rbx
leaq 0xd0(%rsp), %rdi
callq 0x5618
jmp 0x15f16
movq %rax, %rbx
leaq 0xb0(%rsp), %rdi
callq 0x5618
jmp 0x15f2e
jmp 0x15f2b
jmp 0x15f41
jmp 0x15f3c
movq %rax, %rbx
leaq 0x70(%rsp), %rdi
callq 0x5618
jmp 0x15f44
jmp 0x15f41
movq %rax, %rbx
jmp 0x15f4e
movq %rax, %rbx
leaq 0x40(%rsp), %rdi
callq 0x5618
movq %rbx, %rdi
callq 0x5570