// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/exec/SSD_Device.cpp
// Function: SSD_Device::SSD_Device(Device_Parameter_Set*, std::vector<IO_Flow_Parameter_Set*, std::allocator<IO_Flow_Parameter_Set*>>*)
SSD_Device::SSD_Device(Device_Parameter_Set *parameters, std::vector<IO_Flow_Parameter_Set *> *io_flows) : MQSimEngine::Sim_Object("SSDDevice")
{
	SSD_Device *device = this;
	my_instance = device; //used for static functions
	Simulator->AddObject(device);

	device->Preconditioning_required = parameters->Enabled_Preconditioning;
	device->Memory_Type = parameters->Memory_Type;

	switch (Memory_Type)
	{
	case NVM::NVM_Type::FLASH:
	{
		sim_time_type *read_latencies, *write_latencies;
		sim_time_type average_flash_read_latency = 0, average_flash_write_latency = 0; //Required for FTL initialization

		//Step 1: create memory chips (flash chips in our case)
		switch (parameters->Flash_Parameters.Flash_Technology)
		{
		case Flash_Technology_Type::SLC:
			read_latencies = new sim_time_type[1];
			read_latencies[0] = parameters->Flash_Parameters.Page_Read_Latency_LSB;
			write_latencies = new sim_time_type[1];
			write_latencies[0] = parameters->Flash_Parameters.Page_Program_Latency_LSB;
			average_flash_read_latency = read_latencies[0];
			average_flash_write_latency = write_latencies[0];
			break;
		case Flash_Technology_Type::MLC:
			read_latencies = new sim_time_type[2];
			read_latencies[0] = parameters->Flash_Parameters.Page_Read_Latency_LSB;
			read_latencies[1] = parameters->Flash_Parameters.Page_Read_Latency_MSB;
			write_latencies = new sim_time_type[2];
			write_latencies[0] = parameters->Flash_Parameters.Page_Program_Latency_LSB;
			write_latencies[1] = parameters->Flash_Parameters.Page_Program_Latency_MSB;
			average_flash_read_latency = (read_latencies[0] + read_latencies[1]) / 2;
			average_flash_write_latency = (write_latencies[0] + write_latencies[1]) / 2;
			break;
		case Flash_Technology_Type::TLC:
			read_latencies = new sim_time_type[3];
			read_latencies[0] = parameters->Flash_Parameters.Page_Read_Latency_LSB;
			read_latencies[1] = parameters->Flash_Parameters.Page_Read_Latency_CSB;
			read_latencies[2] = parameters->Flash_Parameters.Page_Read_Latency_MSB;
			write_latencies = new sim_time_type[3];
			write_latencies[0] = parameters->Flash_Parameters.Page_Program_Latency_LSB;
			write_latencies[1] = parameters->Flash_Parameters.Page_Program_Latency_CSB;
			write_latencies[2] = parameters->Flash_Parameters.Page_Program_Latency_MSB;
			average_flash_read_latency = (read_latencies[0] + read_latencies[1] + read_latencies[2]) / 3;
			average_flash_write_latency = (write_latencies[0] + write_latencies[1] + write_latencies[2]) / 3;
			break;
		default:
			throw std::invalid_argument("The specified flash technologies is not supported");
		}

		//Step 2: create memory channels to connect chips to the controller
		this->Channel_count = parameters->Flash_Channel_Count;
		this->Chip_no_per_channel = parameters->Chip_No_Per_Channel;
		switch (parameters->Flash_Comm_Protocol)
		{
		case SSD_Components::ONFI_Protocol::NVDDR2:
		{
			SSD_Components::ONFI_Channel_NVDDR2 **channels = new SSD_Components::ONFI_Channel_NVDDR2 *[parameters->Flash_Channel_Count];
			for (unsigned int channel_cntr = 0; channel_cntr < parameters->Flash_Channel_Count; channel_cntr++)
			{
				NVM::FlashMemory::Flash_Chip **chips = new NVM::FlashMemory::Flash_Chip *[parameters->Chip_No_Per_Channel];
				for (unsigned int chip_cntr = 0; chip_cntr < parameters->Chip_No_Per_Channel; chip_cntr++)
				{
					chips[chip_cntr] = new NVM::FlashMemory::Flash_Chip(device->ID() + ".Channel." + std::to_string(channel_cntr) + ".Chip." + std::to_string(chip_cntr),
																		channel_cntr, chip_cntr, parameters->Flash_Parameters.Flash_Technology, parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
																		parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block,
																		read_latencies, write_latencies, parameters->Flash_Parameters.Block_Erase_Latency,
																		parameters->Flash_Parameters.Suspend_Program_Time, parameters->Flash_Parameters.Suspend_Erase_Time);
					Simulator->AddObject(chips[chip_cntr]); //Each simulation object (a child of MQSimEngine::Sim_Object) should be added to the engine
				}
				channels[channel_cntr] = new SSD_Components::ONFI_Channel_NVDDR2(channel_cntr, parameters->Chip_No_Per_Channel,
																				 chips, parameters->Flash_Channel_Width,
																				 (sim_time_type)((double)1000 / parameters->Channel_Transfer_Rate) * 2, (sim_time_type)((double)1000 / parameters->Channel_Transfer_Rate) * 2);
				device->Channels.push_back(channels[channel_cntr]); //Channels should not be added to the simulator core, they are passive object that do not handle any simulation event
			}

			//Step 3: create channel controller and connect channels to it
			device->PHY = new SSD_Components::NVM_PHY_ONFI_NVDDR2(device->ID() + ".PHY", channels, parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel,
																  parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die);
			Simulator->AddObject(device->PHY);
			break;
		}
		default:
			throw std::invalid_argument("No implementation is available for the specified flash communication protocol");
		}
		delete[] read_latencies;
		delete[] write_latencies;

		//Steps 4 - 8: create FTL components and connect them together
		SSD_Components::FTL *ftl = new SSD_Components::FTL(device->ID() + ".FTL", NULL, parameters->Flash_Channel_Count,
														   parameters->Chip_No_Per_Channel, parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
														   parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block,
														   parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, average_flash_read_latency, average_flash_write_latency, parameters->Overprovisioning_Ratio,
														   parameters->Flash_Parameters.Block_PE_Cycles_Limit, parameters->Seed++);
		ftl->PHY = (SSD_Components::NVM_PHY_ONFI *)PHY;
		Simulator->AddObject(ftl);
		device->Firmware = ftl;

		//Step 5: create TSU
		SSD_Components::TSU_Base *tsu;
		bool erase_suspension = false, program_suspension = false;
		if (parameters->Flash_Parameters.CMD_Suspension_Support == NVM::FlashMemory::Command_Suspension_Mode::PROGRAM)
		{
			program_suspension = true;
		}
		if (parameters->Flash_Parameters.CMD_Suspension_Support == NVM::FlashMemory::Command_Suspension_Mode::ERASE)
		{
			erase_suspension = true;
		}
		if (parameters->Flash_Parameters.CMD_Suspension_Support == NVM::FlashMemory::Command_Suspension_Mode::PROGRAM_ERASE)
		{
			program_suspension = true;
			erase_suspension = true;
		}
		switch (parameters->Transaction_Scheduling_Policy)
		{
		case SSD_Components::Flash_Scheduling_Type::OUT_OF_ORDER:
			tsu = new SSD_Components::TSU_OutOfOrder(ftl->ID() + ".TSU", ftl, static_cast<SSD_Components::NVM_PHY_ONFI_NVDDR2 *>(device->PHY),
													 parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel,
													 parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
													 parameters->Preferred_suspend_write_time_for_read, parameters->Preferred_suspend_erase_time_for_read,
													 parameters->Preferred_suspend_erase_time_for_write,
													 erase_suspension, program_suspension);
			break;
		case SSD_Components::Flash_Scheduling_Type::PRIORITY_OUT_OF_ORDER:
			tsu = new SSD_Components::TSU_Priority_OutOfOrder(ftl->ID() + ".TSU", ftl, static_cast<SSD_Components::NVM_PHY_ONFI_NVDDR2 *>(device->PHY),
										  parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel,
										  parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
										  parameters->Preferred_suspend_write_time_for_read, parameters->Preferred_suspend_erase_time_for_read,
										  parameters->Preferred_suspend_erase_time_for_write,
										  erase_suspension, program_suspension);
			break;
		/*case SSD_Components::Flash_Scheduling_Type::FLIN:
				{
					unsigned int * stream_count_per_priority_class = new unsigned int[4];
					for (int i = 0; i < 4; i++)
						stream_count_per_priority_class[i] = 0;
					for (auto &flow : (*io_flows))
						stream_count_per_priority_class[(int)flow->Priority_Class]++;
					stream_id_type** stream_ids_per_priority_class = new stream_id_type*[4];
					for (int i = 0; i < 4; i++)
						stream_ids_per_priority_class[i] = new stream_id_type[stream_count_per_priority_class[i]];

					tsu = new SSD_Components::TSU_FLIN(ftl->ID() + ".TSU", ftl, static_cast<SSD_Components::NVM_PHY_ONFI_NVDDR2*>(device->PHY),
						parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel,
						parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die, parameters->Flash_Parameters.Page_Capacity,
						10000000, 33554432, 262144, 4, (unsigned int)io_flows->size(), stream_count_per_priority_class, stream_ids_per_priority_class,
						0.6,
						parameters->Preferred_suspend_write_time_for_read, parameters->Preferred_suspend_erase_time_for_read, parameters->Preferred_suspend_erase_time_for_write,
						erase_suspension, program_suspension);
					break;
				}*/
		default:
			throw std::invalid_argument("No implementation is available for the specified transaction scheduling algorithm");
		}
		Simulator->AddObject(tsu);
		ftl->TSU = tsu;

		//Step 6: create Flash_Block_Manager
		SSD_Components::Flash_Block_Manager_Base *fbm;
		fbm = new SSD_Components::Flash_Block_Manager(NULL, parameters->Flash_Parameters.Block_PE_Cycles_Limit,
													  (unsigned int)io_flows->size(), parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel,
													  parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
													  parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block);
		ftl->BlockManager = fbm;

		//Step 7: create Address_Mapping_Unit
		SSD_Components::Address_Mapping_Unit_Base *amu;
		std::vector<std::vector<flash_channel_ID_type>> flow_channel_id_assignments;
		std::vector<std::vector<flash_chip_ID_type>> flow_chip_id_assignments;
		std::vector<std::vector<flash_die_ID_type>> flow_die_id_assignments;
		std::vector<std::vector<flash_plane_ID_type>> flow_plane_id_assignments;
		unsigned int stream_count = 0;
		for (unsigned int i = 0; i < io_flows->size(); i++)
		{
			switch (parameters->HostInterface_Type)
			{
			case HostInterface_Types::SATA:
			{
				stream_count = 1;
				std::vector<flash_channel_ID_type> channel_ids;
				flow_channel_id_assignments.push_back(channel_ids);
				for (unsigned int j = 0; j < parameters->Flash_Channel_Count; j++)
				{
					flow_channel_id_assignments[i].push_back(j);
				}
				std::vector<flash_chip_ID_type> chip_ids;
				flow_chip_id_assignments.push_back(chip_ids);
				for (unsigned int j = 0; j < parameters->Chip_No_Per_Channel; j++)
				{
					flow_chip_id_assignments[i].push_back(j);
				}
				std::vector<flash_die_ID_type> die_ids;
				flow_die_id_assignments.push_back(die_ids);
				for (unsigned int j = 0; j < parameters->Flash_Parameters.Die_No_Per_Chip; j++)
				{
					flow_die_id_assignments[i].push_back(j);
				}
				std::vector<flash_plane_ID_type> plane_ids;
				flow_plane_id_assignments.push_back(plane_ids);
				for (unsigned int j = 0; j < parameters->Flash_Parameters.Plane_No_Per_Die; j++)
				{
					flow_plane_id_assignments[i].push_back(j);
				}
				break;
			}
			case HostInterface_Types::NVME:
			{
				stream_count = (unsigned int)io_flows->size();
				std::vector<flash_channel_ID_type> channel_ids;
				flow_channel_id_assignments.push_back(channel_ids);
				for (int j = 0; j < (*io_flows)[i]->Channel_No; j++)
				{
					flow_channel_id_assignments[i].push_back((*io_flows)[i]->Channel_IDs[j]);
				}
				std::vector<flash_chip_ID_type> chip_ids;
				flow_chip_id_assignments.push_back(chip_ids);
				for (int j = 0; j < (*io_flows)[i]->Chip_No; j++)
				{
					flow_chip_id_assignments[i].push_back((*io_flows)[i]->Chip_IDs[j]);
				}
				std::vector<flash_die_ID_type> die_ids;
				flow_die_id_assignments.push_back(die_ids);
				for (int j = 0; j < (*io_flows)[i]->Die_No; j++)
				{
					flow_die_id_assignments[i].push_back((*io_flows)[i]->Die_IDs[j]);
				}
				std::vector<flash_plane_ID_type> plane_ids;
				flow_plane_id_assignments.push_back(plane_ids);
				for (int j = 0; j < (*io_flows)[i]->Plane_No; j++)
				{
					flow_plane_id_assignments[i].push_back((*io_flows)[i]->Plane_IDs[j]);
				}
				break;
			}
			default:
				break;
			}
		}

		Utils::Logical_Address_Partitioning_Unit::Allocate_logical_address_for_flows(parameters->HostInterface_Type, (unsigned int)io_flows->size(),
																					 parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel, parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
																					 flow_channel_id_assignments, flow_chip_id_assignments, flow_die_id_assignments, flow_plane_id_assignments,
																					 parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block,
																					 parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, parameters->Overprovisioning_Ratio);
		switch (parameters->Address_Mapping)
		{
		case SSD_Components::Flash_Address_Mapping_Type::PAGE_LEVEL:
			amu = new SSD_Components::Address_Mapping_Unit_Page_Level(ftl->ID() + ".AddressMappingUnit", ftl, (SSD_Components::NVM_PHY_ONFI *)device->PHY,
																	  fbm, parameters->Ideal_Mapping_Table, parameters->CMT_Capacity, parameters->Plane_Allocation_Scheme, stream_count,
																	  parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel, parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
																	  flow_channel_id_assignments, flow_chip_id_assignments, flow_die_id_assignments, flow_plane_id_assignments,
																	  parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block,
																	  parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, parameters->Flash_Parameters.Page_Capacity, parameters->Overprovisioning_Ratio,
																	  parameters->CMT_Sharing_Mode);
			break;
		case SSD_Components::Flash_Address_Mapping_Type::HYBRID:
			amu = new SSD_Components::Address_Mapping_Unit_Hybrid(ftl->ID() + ".AddressMappingUnit", ftl, (SSD_Components::NVM_PHY_ONFI *)device->PHY,
																  fbm, parameters->Ideal_Mapping_Table, stream_count,
																  parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel, parameters->Flash_Parameters.Die_No_Per_Chip,
																  parameters->Flash_Parameters.Plane_No_Per_Die, parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block,
																  parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, parameters->Flash_Parameters.Page_Capacity, parameters->Overprovisioning_Ratio);
			break;
		default:
			throw std::invalid_argument("No implementation is available fo the secified address mapping strategy");
		}
		Simulator->AddObject(amu);
		ftl->Address_Mapping_Unit = amu;

		//Step 8: create GC_and_WL_unit
		double max_rho = 0;
		for (unsigned int i = 0; i < io_flows->size(); i++)
		{
			if ((*io_flows)[i]->Initial_Occupancy_Percentage > max_rho)
			{
				max_rho = (*io_flows)[i]->Initial_Occupancy_Percentage;
			}
		}
		max_rho /= 100; //Convert from percentage to a value between zero and 1
		SSD_Components::GC_and_WL_Unit_Base *gcwl;
		gcwl = new SSD_Components::GC_and_WL_Unit_Page_Level(ftl->ID() + ".GCandWLUnit", amu, fbm, tsu, (SSD_Components::NVM_PHY_ONFI *)device->PHY,
															 parameters->GC_Block_Selection_Policy, parameters->GC_Exec_Threshold, parameters->Preemptible_GC_Enabled, parameters->GC_Hard_Threshold,
															 parameters->Flash_Channel_Count, parameters->Chip_No_Per_Channel,
															 parameters->Flash_Parameters.Die_No_Per_Chip, parameters->Flash_Parameters.Plane_No_Per_Die,
															 parameters->Flash_Parameters.Block_No_Per_Plane, parameters->Flash_Parameters.Page_No_Per_Block,
															 parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, parameters->Use_Copyback_for_GC, max_rho, 10,
															 parameters->Seed++);
		Simulator->AddObject(gcwl);
		fbm->Set_GC_and_WL_Unit(gcwl);
		ftl->GC_and_WL_Unit = gcwl;

		//Step 9: create Data_Cache_Manager
		SSD_Components::Data_Cache_Manager_Base *dcm;
		SSD_Components::Caching_Mode *caching_modes = new SSD_Components::Caching_Mode[io_flows->size()];
		for (unsigned int i = 0; i < io_flows->size(); i++)
		{
			caching_modes[i] = (*io_flows)[i]->Device_Level_Data_Caching_Mode;
		}

		switch (parameters->Caching_Mechanism)
		{
		case SSD_Components::Caching_Mechanism::SIMPLE:
			dcm = new SSD_Components::Data_Cache_Manager_Flash_Simple(device->ID() + ".DataCache", NULL, ftl, (SSD_Components::NVM_PHY_ONFI *)device->PHY,
																	  parameters->Data_Cache_Capacity, parameters->Data_Cache_DRAM_Row_Size, parameters->Data_Cache_DRAM_Data_Rate,
																	  parameters->Data_Cache_DRAM_Data_Busrt_Size, parameters->Data_Cache_DRAM_tRCD, parameters->Data_Cache_DRAM_tCL, parameters->Data_Cache_DRAM_tRP,
																	  caching_modes, (unsigned int)io_flows->size(),
																	  parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, parameters->Flash_Channel_Count * parameters->Chip_No_Per_Channel * parameters->Flash_Parameters.Die_No_Per_Chip * parameters->Flash_Parameters.Plane_No_Per_Die * parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE);

			break;
		case SSD_Components::Caching_Mechanism::ADVANCED:
			dcm = new SSD_Components::Data_Cache_Manager_Flash_Advanced(device->ID() + ".DataCache", NULL, ftl, (SSD_Components::NVM_PHY_ONFI *)device->PHY,
																		parameters->Data_Cache_Capacity, parameters->Data_Cache_DRAM_Row_Size, parameters->Data_Cache_DRAM_Data_Rate,
																		parameters->Data_Cache_DRAM_Data_Busrt_Size, parameters->Data_Cache_DRAM_tRCD, parameters->Data_Cache_DRAM_tCL, parameters->Data_Cache_DRAM_tRP,
																		caching_modes, parameters->Data_Cache_Sharing_Mode, (unsigned int)io_flows->size(),
																		parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, parameters->Flash_Channel_Count * parameters->Chip_No_Per_Channel * parameters->Flash_Parameters.Die_No_Per_Chip * parameters->Flash_Parameters.Plane_No_Per_Die * parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE);

			break;
		default:
			PRINT_ERROR("Unknown data caching mechanism!")
		}

		Simulator->AddObject(dcm);
		ftl->Data_cache_manager = dcm;
		device->Cache_manager = dcm;

		//Step 10: create Host_Interface
		switch (parameters->HostInterface_Type)
		{
		case HostInterface_Types::NVME:
			device->Host_interface = new SSD_Components::Host_Interface_NVMe(device->ID() + ".HostInterface",
																			 Utils::Logical_Address_Partitioning_Unit::Get_total_device_lha_count(), parameters->IO_Queue_Depth, parameters->IO_Queue_Depth,
																			 (unsigned int)io_flows->size(), parameters->Queue_Fetch_Size, parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, dcm);
			break;
		case HostInterface_Types::SATA:
			device->Host_interface = new SSD_Components::Host_Interface_SATA(device->ID() + ".HostInterface",
																			 parameters->IO_Queue_Depth, Utils::Logical_Address_Partitioning_Unit::Get_total_device_lha_count(), parameters->Flash_Parameters.Page_Capacity / SECTOR_SIZE_IN_BYTE, dcm);

			break;
		default:
			break;
		}
		Simulator->AddObject(device->Host_interface);
		dcm->Set_host_interface(device->Host_interface);
		break;
	}
	default:
		throw std::invalid_argument("Undefined NVM type specified ");
	} // switch (Memory_Type)
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x268, %rsp            # imm = 0x268
movq %rdx, 0x78(%rsp)
movq %rdi, %rbx
leaq 0x308d0(%rip), %rsi     # 0x454a0
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rdx
callq 0x7150
leaq 0x20(%rsp), %rsi
movq %rbx, %rdi
callq 0x11bca
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x4beeb(%rip), %rax     # 0x60ae8
movq %rax, (%rbx)
leaq 0x4bf19(%rip), %rax     # 0x60b20
movq %rax, 0x30(%rbx)
leaq 0x60(%rbx), %rax
movq %rax, 0x170(%rsp)
xorpd %xmm0, %xmm0
movupd %xmm0, 0x60(%rbx)
andq $0x0, 0x70(%rbx)
movq %rbx, 0x8(%rsp)
movq %rbx, 0x4d95f(%rip)     # 0x62590
callq 0x1f784
movq %rax, %rdi
movq 0x8(%rsp), %rsi
callq 0x1f7f2
leaq 0x4d702(%rip), %rax     # 0x6234c
movb (%rax), %al
movq 0x8(%rsp), %rcx
movb %al, 0x38(%rcx)
leaq 0x4d8ad(%rip), %rax     # 0x62508
movl (%rax), %eax
movl %eax, 0x3c(%rcx)
testl %eax, %eax
jne 0x16352
leaq 0x4d789(%rip), %rax     # 0x623f8
movl (%rax), %eax
cmpl $0x3, %eax
je 0x14d2d
cmpl $0x2, %eax
je 0x14cc6
cmpl $0x1, %eax
jne 0x1644a
pushq $0x8
popq %rdi
callq 0x7030
movq %rax, %r12
leaq 0x4d766(%rip), %rax     # 0x62400
movq (%rax), %r14
movq %r14, (%r12)
pushq $0x8
popq %rdi
callq 0x7030
movq %rax, %r9
leaq 0x4d765(%rip), %rax     # 0x62418
movq (%rax), %rax
movq %rax, 0x80(%rsp)
movq %rax, (%r9)
jmp 0x14dc3
pushq $0x10
popq %rdi
callq 0x7030
movq %rax, %r12
leaq 0x4d728(%rip), %rax     # 0x62400
movq (%rax), %rbx
movq %rbx, (%r12)
leaq 0x4d72a(%rip), %rax     # 0x62410
movq (%rax), %r14
movq %r14, 0x8(%r12)
pushq $0x10
popq %rdi
callq 0x7030
movq %rax, %r9
leaq 0x4d718(%rip), %rax     # 0x62418
movq (%rax), %rax
movq %rax, (%r9)
leaq 0x4d71b(%rip), %rcx     # 0x62428
movq (%rcx), %rcx
movq %rcx, 0x8(%r9)
addq %rbx, %r14
shrq %r14
addq %rax, %rcx
shrq %rcx
movq %rcx, 0x80(%rsp)
jmp 0x14dc3
pushq $0x18
popq %rdi
callq 0x7030
movq %rax, %r12
leaq 0x4d6c1(%rip), %rax     # 0x62400
movq (%rax), %r14
movq %r14, (%r12)
leaq 0x4d6bb(%rip), %rax     # 0x62408
movq (%rax), %rbx
movq %rbx, 0x8(%r12)
leaq 0x4d6b4(%rip), %rax     # 0x62410
movq (%rax), %r15
movq %r15, 0x10(%r12)
pushq $0x18
popq %rdi
callq 0x7030
movq %rax, %r9
leaq 0x4d6a2(%rip), %rax     # 0x62418
movq (%rax), %rsi
movq %rsi, (%r9)
leaq 0x4d69d(%rip), %rax     # 0x62420
movq (%rax), %rcx
movq %rcx, 0x8(%r9)
leaq 0x4d697(%rip), %rax     # 0x62428
movq (%rax), %rdi
movq %rdi, 0x10(%r9)
addq %r14, %rbx
addq %r15, %rbx
pushq $0x3
popq %r8
movq %rbx, %rax
xorl %edx, %edx
divq %r8
movq %rax, %r14
addq %rsi, %rcx
addq %rdi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r8
movq %rax, 0x80(%rsp)
movq %r9, 0x10(%rsp)
movq %r12, 0x48(%rsp)
leaq 0x4d5fc(%rip), %rax     # 0x623d0
movl (%rax), %ebx
movq 0x8(%rsp), %rcx
movl %ebx, 0x78(%rcx)
leaq 0x4d5f7(%rip), %rax     # 0x623dc
movl (%rax), %eax
movl %eax, 0x7c(%rcx)
leaq 0x4d737(%rip), %rax     # 0x62528
cmpl $0x0, (%rax)
jne 0x16387
leaq (,%rbx,8), %rdi
callq 0x7030
movq %rax, 0x70(%rsp)
movq %r14, 0x90(%rsp)
movq 0x8(%rsp), %rax
addq $0x8, %rax
movq %rax, 0x88(%rsp)
xorl %ebp, %ebp
movl %ebx, %eax
cmpq %rax, %rbp
jae 0x150de
leaq 0x4d5a3(%rip), %rax     # 0x623dc
movl (%rax), %r13d
leaq (,%r13,8), %rdi
callq 0x7030
movq %rax, %r12
xorl %ebx, %ebx
movl %r13d, %eax
cmpq %rax, %rbx
jae 0x15020
movl $0x108, %edi            # imm = 0x108
callq 0x7370
movq %rax, %r13
leaq 0x130(%rsp), %r14
movq %r14, %rdi
movq 0x88(%rsp), %rsi
callq 0x7480
leaq 0xd0(%rsp), %rdi
movq %r14, %rsi
leaq 0x3064b(%rip), %rdx     # 0x454dc
callq 0x9b29
leaq 0x110(%rsp), %r14
movq %r14, %rdi
movl %ebp, %esi
callq 0xe74b
leaq 0x150(%rsp), %r15
movq %r15, %rdi
leaq 0xd0(%rsp), %rsi
movq %r14, %rdx
callq 0x9b48
leaq 0x50(%rsp), %rdi
movq %r15, %rsi
leaq 0x30614(%rip), %rdx     # 0x454e6
callq 0x9b29
leaq 0xb0(%rsp), %r14
movq %r14, %rdi
movl %ebx, %esi
callq 0xe74b
leaq 0x20(%rsp), %r15
movq %r15, %rdi
leaq 0x50(%rsp), %rsi
movq %r14, %rdx
callq 0x9b48
leaq 0x4d4f3(%rip), %rax     # 0x623f8
movl (%rax), %r8d
leaq 0x4d541(%rip), %rax     # 0x62450
movl (%rax), %r9d
leaq 0x4d53b(%rip), %rax     # 0x62454
movl (%rax), %eax
leaq 0x4d536(%rip), %rcx     # 0x62458
movl (%rcx), %ecx
leaq 0x4d531(%rip), %rdx     # 0x6245c
movl (%rdx), %edx
leaq 0x4d4fc(%rip), %rsi     # 0x62430
movq (%rsi), %rsi
leaq 0x4d50a(%rip), %rdi     # 0x62448
movq (%rdi), %rdi
leaq 0x4d4f8(%rip), %r10     # 0x62440
movq (%r10), %r10
subq $0x60, %rsp
xorpd %xmm0, %xmm0
movupd %xmm0, 0x48(%rsp)
movq %r10, 0x38(%rsp)
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x70(%rsp), %rsi
movq %rsi, 0x20(%rsp)
movq 0xa8(%rsp), %rsi
movq %rsi, 0x18(%rsp)
movl %edx, 0x10(%rsp)
movl %ecx, 0x8(%rsp)
movl %eax, (%rsp)
movq $0x14, 0x40(%rsp)
movq %r13, %rdi
movq %r15, %rsi
movl %ebp, %edx
movl %ebx, %ecx
callq 0x1e1f0
addq $0x60, %rsp
movq %r13, (%r12,%rbx,8)
movq %r15, %rdi
callq 0x7678
leaq 0xb0(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
leaq 0x150(%rsp), %rdi
callq 0x7678
leaq 0x110(%rsp), %rdi
callq 0x7678
leaq 0xd0(%rsp), %rdi
callq 0x7678
leaq 0x130(%rsp), %rdi
callq 0x7678
callq 0x1f784
movq (%r12,%rbx,8), %rsi
movq %rax, %rdi
callq 0x1f7f2
incq %rbx
leaq 0x4d3c4(%rip), %rax     # 0x623dc
movl (%rax), %r13d
jmp 0x14e4e
movl $0x158, %edi            # imm = 0x158
callq 0x7370
movq %rax, %rbx
leaq 0x4d3a0(%rip), %rax     # 0x623d4
movl (%rax), %r8d
leaq 0x4d39a(%rip), %rax     # 0x623d8
movl (%rax), %eax
cvtsi2sd %rax, %xmm0
movsd 0x3044b(%rip), %xmm1    # 0x45498
divsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
subsd 0x2dfef(%rip), %xmm1    # 0x43050
cvttsd2si %xmm1, %r9
sarq $0x3f, %rcx
andq %rcx, %r9
orq %rax, %r9
addq %r9, %r9
movq %rbx, %rdi
movl %ebp, %esi
movl %r13d, %edx
movq %r12, %rcx
pushq $0xf
popq %rax
pushq %rax
pushq $0x6
pushq $0x12c                  # imm = 0x12C
pushq $0x64
popq %r10
pushq %r10
pushq %rax
pushq %rax
pushq %rax
pushq $0x46
pushq $0x19
pushq %r10
pushq $0x14
popq %rax
pushq %rax
pushq %rax
pushq $0x1f4                  # imm = 0x1F4
pushq %r9
callq 0x3a3dc
addq $0x70, %rsp
movq 0x70(%rsp), %rax
movq %rbx, (%rax,%rbp,8)
movq %rbx, 0x20(%rsp)
movq 0x170(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x16ed4
incq %rbp
leaq 0x4d2f9(%rip), %rax     # 0x623d0
movl (%rax), %ebx
jmp 0x14e27
movl $0xb8, %edi
callq 0x7370
leaq 0x4d2e1(%rip), %r14     # 0x623d0
movq 0x90(%rsp), %rbp
movq %rax, %rbx
leaq 0x50(%rsp), %rdi
movq 0x88(%rsp), %rsi
callq 0x7480
leaq 0x303da(%rip), %rdx     # 0x454ed
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
movl (%r14), %ecx
leaq 0x4d2b0(%rip), %rax     # 0x623dc
movl (%rax), %r8d
leaq 0x4d31a(%rip), %rax     # 0x62450
movl (%rax), %r9d
leaq 0x4d314(%rip), %rax     # 0x62454
movl (%rax), %eax
subq $0x8, %rsp
leaq 0x28(%rsp), %rsi
movq %rbx, %rdi
movq 0x78(%rsp), %rdx
pushq %rax
callq 0x378f4
popq %rax
popq %rcx
movq 0x8(%rsp), %rax
movq %rbx, 0x58(%rax)
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
callq 0x1f784
movq 0x8(%rsp), %rcx
movq 0x58(%rcx), %rsi
movq %rax, %rdi
callq 0x1f7f2
movq 0x48(%rsp), %rdi
callq 0x7430
movq 0x10(%rsp), %rdi
callq 0x7430
movl $0xb8, %edi
callq 0x7370
leaq 0x50(%rsp), %rdi
movq 0x88(%rsp), %rsi
movq %rax, 0x10(%rsp)
callq 0x7480
leaq 0x4d206(%rip), %rbx     # 0x623d0
leaq 0x3036f(%rip), %rdx     # 0x45540
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
movl (%rbx), %ecx
leaq 0x4d1f3(%rip), %rax     # 0x623dc
movl (%rax), %r8d
leaq 0x4d25d(%rip), %rax     # 0x62450
movl (%rax), %r9d
leaq 0x4d257(%rip), %rax     # 0x62454
movl (%rax), %eax
leaq 0x4d252(%rip), %rdx     # 0x62458
movl (%rdx), %r10d
leaq 0x4d24c(%rip), %rdx     # 0x6245c
movl (%rdx), %r11d
leaq 0x4d246(%rip), %rdx     # 0x62460
movl (%rdx), %r14d
shrl $0x9, %r14d
leaq 0x4d168(%rip), %rdx     # 0x62390
movsd (%rdx), %xmm0
leaq 0x4d205(%rip), %rbx     # 0x62438
leaq 0x4d10e(%rip), %rsi     # 0x62348
movl (%rsi), %r15d
leal 0x1(%r15), %edx
movl %edx, (%rsi)
movl (%rbx), %r12d
leaq 0x20(%rsp), %rsi
movq 0x10(%rsp), %r13
movq %r13, %rdi
xorl %edx, %edx
pushq %r15
pushq %r12
pushq 0x90(%rsp)
pushq %rbp
pushq %r14
pushq %r11
pushq %r10
pushq %rax
callq 0x2c22c
addq $0x40, %rsp
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
movq 0x8(%rsp), %rax
movq 0x58(%rax), %rax
movq %rax, 0x58(%r13)
callq 0x1f784
movq %rax, %rdi
movq %r13, %rsi
callq 0x1f7f2
movq 0x8(%rsp), %rax
movq %r13, 0x50(%rax)
leaq 0x4d14a(%rip), %rax     # 0x623fc
movl (%rax), %r14d
movl %r14d, %ebp
andl $-0x2, %ebp
decl %r14d
leaq 0x4d25b(%rip), %rax     # 0x62520
movl (%rax), %eax
testl %eax, %eax
je 0x1539d
cmpl $0x1, %eax
jne 0x163a6
movl $0x108, %edi            # imm = 0x108
callq 0x7370
movq %rax, 0x70(%rsp)
movq 0x10(%rsp), %rax
leaq 0x8(%rax), %rsi
leaq 0x50(%rsp), %rdi
callq 0x7480
leaq 0x30244(%rip), %rdx     # 0x45545
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
xorl %r10d, %r10d
cmpl $0x2, %r14d
setb %r10b
xorl %r11d, %r11d
cmpl $0x2, %ebp
sete %r11b
movq 0x8(%rsp), %rax
movq 0x58(%rax), %rcx
leaq 0x4d09b(%rip), %rax     # 0x623d0
movl (%rax), %r8d
leaq 0x4d09d(%rip), %rax     # 0x623dc
movl (%rax), %r9d
leaq 0x4d107(%rip), %rax     # 0x62450
movl (%rax), %eax
leaq 0x4d102(%rip), %rdx     # 0x62454
movl (%rdx), %r14d
leaq 0x4d06c(%rip), %r15     # 0x623c8
leaq 0x4d055(%rip), %r12     # 0x623b8
leaq 0x4d056(%rip), %r13     # 0x623c0
subq $0x8, %rsp
leaq 0x28(%rsp), %rsi
movq 0x78(%rsp), %rdi
movq 0x18(%rsp), %rdx
pushq %r10
pushq %r11
pushq (%r13)
pushq (%r12)
pushq (%r15)
pushq %r14
pushq %rax
callq 0x3db44
addq $0x40, %rsp
jmp 0x1545d
movl $0xe8, %edi
callq 0x7370
movq %rax, 0x70(%rsp)
movq 0x10(%rsp), %rax
leaq 0x8(%rax), %rsi
leaq 0x50(%rsp), %rdi
callq 0x7480
leaq 0x3017f(%rip), %rdx     # 0x45545
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
xorl %r10d, %r10d
cmpl $0x2, %r14d
setb %r10b
xorl %r11d, %r11d
cmpl $0x2, %ebp
sete %r11b
movq 0x8(%rsp), %rax
movq 0x58(%rax), %rcx
leaq 0x4cfd6(%rip), %rax     # 0x623d0
movl (%rax), %r8d
leaq 0x4cfd8(%rip), %rax     # 0x623dc
movl (%rax), %r9d
leaq 0x4d042(%rip), %rax     # 0x62450
movl (%rax), %eax
leaq 0x4d03d(%rip), %rdx     # 0x62454
movl (%rdx), %r14d
leaq 0x4cfa7(%rip), %r15     # 0x623c8
leaq 0x4cf90(%rip), %r12     # 0x623b8
leaq 0x4cf91(%rip), %r13     # 0x623c0
subq $0x8, %rsp
leaq 0x28(%rsp), %rsi
movq 0x78(%rsp), %rdi
movq 0x18(%rsp), %rdx
pushq %r10
pushq %r11
pushq (%r13)
pushq (%r12)
pushq (%r15)
pushq %r14
pushq %rax
callq 0x3c288
addq $0x40, %rsp
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
callq 0x1f784
movq %rax, %rdi
movq 0x70(%rsp), %rsi
callq 0x1f7f2
movq 0x10(%rsp), %rax
movq 0x70(%rsp), %rcx
movq %rcx, 0x50(%rax)
pushq $0x38
popq %rdi
callq 0x7370
movq %rax, %r12
movq 0x78(%rsp), %rax
movq 0x8(%rax), %rcx
subq (%rax), %rcx
movl (%rbx), %edx
shrq $0x3, %rcx
leaq 0x4cf1b(%rip), %r14     # 0x623d0
movl (%r14), %r8d
leaq 0x4cf1d(%rip), %rax     # 0x623dc
movl (%rax), %r9d
leaq 0x4cf87(%rip), %rax     # 0x62450
movl (%rax), %eax
leaq 0x4cf82(%rip), %rsi     # 0x62454
movl (%rsi), %r10d
leaq 0x4cf7c(%rip), %rsi     # 0x62458
movl (%rsi), %r11d
leaq 0x4cf76(%rip), %rsi     # 0x6245c
movl (%rsi), %ebx
movq %r12, %rdi
xorl %esi, %esi
pushq %rbx
pushq %r11
pushq %r10
pushq %rax
callq 0x30938
addq $0x20, %rsp
movq 0x10(%rsp), %rax
movq %r12, 0x90(%rsp)
movq %r12, 0x40(%rax)
xorpd %xmm0, %xmm0
leaq 0x150(%rsp), %rax
andq $0x0, 0x10(%rax)
leaq 0xd0(%rsp), %rcx
andq $0x0, 0x10(%rcx)
movapd %xmm0, (%rax)
movapd %xmm0, (%rcx)
leaq 0x130(%rsp), %rax
movapd %xmm0, (%rax)
andq $0x0, 0x10(%rax)
leaq 0x110(%rsp), %rax
movapd %xmm0, (%rax)
andq $0x0, 0x10(%rax)
leaq 0x4cdf4(%rip), %rbp     # 0x62350
leaq 0xf0(%rsp), %r13
xorl %ebx, %ebx
xorl %ecx, %ecx
movq 0x78(%rsp), %rax
movq 0x8(%rax), %r15
subq (%rax), %r15
movl %ebx, %ebx
sarq $0x3, %r15
movl (%rbp), %r12d
cmpq %rbx, %r15
jbe 0x158ed
cmpl $0x1, %r12d
je 0x155ec
testl %r12d, %r12d
leaq 0xb0(%rsp), %r12
jne 0x158e6
xorpd %xmm0, %xmm0
movapd %xmm0, 0x20(%rsp)
andq $0x0, 0x30(%rsp)
leaq 0x150(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x16d8c
xorl %eax, %eax
leaq 0x50(%rsp), %r15
movl %eax, 0x50(%rsp)
cmpl (%r14), %eax
jae 0x1564c
imulq $0x18, %rbx, %rdi
addq 0x150(%rsp), %rdi
movq %r15, %rsi
callq 0x16db8
movl 0x50(%rsp), %eax
incl %eax
jmp 0x155c7
xorpd %xmm0, %xmm0
movapd %xmm0, 0x20(%rsp)
andq $0x0, 0x30(%rsp)
leaq 0x150(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x16d8c
imulq $0x18, %rbx, %r12
xorl %ebp, %ebp
xorl %r14d, %r14d
movq 0x78(%rsp), %rax
movq (%rax), %rax
movq (%rax,%rbx,8), %rax
movslq 0x3c(%rax), %rcx
cmpq %rcx, %r14
jge 0x1569f
movq 0x150(%rsp), %rdi
addq %r12, %rdi
movq 0x18(%rax), %rsi
addq %rbp, %rsi
callq 0x16db8
incq %r14
addq $0x4, %rbp
jmp 0x15617
xorpd %xmm0, %xmm0
movapd %xmm0, 0x50(%rsp)
andq $0x0, 0x60(%rsp)
leaq 0xd0(%rsp), %rdi
movq %r15, %rsi
callq 0x16d8c
xorl %eax, %eax
movl %eax, 0xb0(%rsp)
leaq 0x4cd60(%rip), %rcx     # 0x623dc
cmpl (%rcx), %eax
jae 0x156fb
imulq $0x18, %rbx, %rdi
addq 0xd0(%rsp), %rdi
movq %r12, %rsi
callq 0x16db8
movl 0xb0(%rsp), %eax
incl %eax
jmp 0x1566e
xorpd %xmm0, %xmm0
movapd %xmm0, 0x50(%rsp)
andq $0x0, 0x60(%rsp)
leaq 0xd0(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x16d8c
xorl %ebp, %ebp
xorl %r14d, %r14d
movq 0x78(%rsp), %rax
movq (%rax), %rax
movq (%rax,%rbx,8), %rax
movslq 0x40(%rax), %rcx
cmpq %rcx, %r14
jge 0x15758
movq 0xd0(%rsp), %rdi
addq %r12, %rdi
movq 0x20(%rax), %rsi
addq %rbp, %rsi
callq 0x16db8
incq %r14
addq $0x4, %rbp
jmp 0x156c6
xorpd %xmm0, %xmm0
movapd %xmm0, 0xb0(%rsp)
andq $0x0, 0xc0(%rsp)
leaq 0x130(%rsp), %rdi
movq %r12, %rsi
callq 0x16d8c
xorl %eax, %eax
movl %eax, 0xf0(%rsp)
leaq 0x4cd1f(%rip), %rcx     # 0x62450
cmpl (%rcx), %eax
jae 0x157c1
imulq $0x18, %rbx, %rdi
addq 0x130(%rsp), %rdi
movq %r13, %rsi
callq 0x16db8
movl 0xf0(%rsp), %eax
incl %eax
jmp 0x15723
xorpd %xmm0, %xmm0
movapd %xmm0, 0xb0(%rsp)
andq $0x0, 0xc0(%rsp)
leaq 0x130(%rsp), %rdi
leaq 0xb0(%rsp), %rsi
callq 0x16d8c
xorl %ebp, %ebp
xorl %r14d, %r14d
movq 0x78(%rsp), %rax
movq (%rax), %rax
movq (%rax,%rbx,8), %rax
movslq 0x44(%rax), %rcx
cmpq %rcx, %r14
jge 0x15823
movq 0x130(%rsp), %rdi
addq %r12, %rdi
movq 0x28(%rax), %rsi
addq %rbp, %rsi
callq 0x16db8
incq %r14
addq $0x4, %rbp
jmp 0x15788
xorpd %xmm0, %xmm0
movapd %xmm0, 0xf0(%rsp)
andq $0x0, 0x100(%rsp)
leaq 0x110(%rsp), %rdi
movq %r13, %rsi
callq 0x16d8c
xorl %eax, %eax
movl %eax, 0x9c(%rsp)
leaq 0x4cc5d(%rip), %rcx     # 0x62454
cmpl (%rcx), %eax
jae 0x15883
imulq $0x18, %rbx, %rdi
addq 0x110(%rsp), %rdi
leaq 0x9c(%rsp), %rsi
callq 0x16db8
movl 0x9c(%rsp), %eax
incl %eax
jmp 0x157e9
xorpd %xmm0, %xmm0
movapd %xmm0, 0xf0(%rsp)
andq $0x0, 0x100(%rsp)
leaq 0x110(%rsp), %rdi
movq %r13, %rsi
callq 0x16d8c
xorl %ebp, %ebp
xorl %r14d, %r14d
movq 0x78(%rsp), %rax
movq (%rax), %rax
movq (%rax,%rbx,8), %rax
movslq 0x48(%rax), %rcx
cmpq %rcx, %r14
jge 0x158ac
movq 0x110(%rsp), %rdi
addq %r12, %rdi
movq 0x30(%rax), %rsi
addq %rbp, %rsi
callq 0x16db8
incq %r14
addq $0x4, %rbp
jmp 0x1584e
movq %r13, %rdi
callq 0x11edc
movq %r12, %rdi
callq 0x11edc
movq %r15, %rdi
callq 0x11edc
leaq 0x20(%rsp), %rdi
callq 0x11edc
pushq $0x1
popq %rax
movl %eax, %ecx
jmp 0x158e6
movq %r13, %rdi
callq 0x11edc
leaq 0xb0(%rsp), %rdi
callq 0x11edc
leaq 0x50(%rsp), %rdi
callq 0x11edc
leaq 0x20(%rsp), %rdi
callq 0x11edc
movl %r15d, %ecx
leaq 0x4caf1(%rip), %r14     # 0x623d0
leaq 0x4ca6a(%rip), %rbp     # 0x62350
incl %ebx
jmp 0x15568
movq %rcx, 0x80(%rsp)
movl (%r14), %ebp
leaq 0x4cadd(%rip), %rax     # 0x623dc
movl (%rax), %r13d
leaq 0x4cb47(%rip), %rax     # 0x62450
movl (%rax), %eax
movl %eax, 0x48(%rsp)
leaq 0x4cb3e(%rip), %rax     # 0x62454
movl (%rax), %r14d
leaq 0x200(%rsp), %rdi
leaq 0x150(%rsp), %rsi
callq 0x16dd6
leaq 0x1e8(%rsp), %rdi
leaq 0xd0(%rsp), %rsi
callq 0x16dd6
leaq 0x1d0(%rsp), %rdi
leaq 0x130(%rsp), %rsi
callq 0x16dd6
leaq 0x250(%rsp), %rbx
leaq 0x110(%rsp), %rsi
movq %rbx, %rdi
callq 0x16dd6
leaq 0x4cae1(%rip), %rax     # 0x62458
movl (%rax), %eax
leaq 0x4cadc(%rip), %rcx     # 0x6245c
movl (%rcx), %r10d
leaq 0x4cad6(%rip), %rcx     # 0x62460
movl (%rcx), %r11d
shrl $0x9, %r11d
leaq 0x4c9f8(%rip), %rcx     # 0x62390
movsd (%rcx), %xmm0
subq $0x8, %rsp
movl %r12d, %edi
movl %r15d, %esi
movl %ebp, %edx
movl %r13d, %ecx
movl 0x50(%rsp), %r8d
movl %r14d, %r9d
pushq %r11
pushq %r10
pushq %rax
pushq %rbx
leaq 0x1f8(%rsp), %rax
pushq %rax
leaq 0x218(%rsp), %rax
pushq %rax
leaq 0x238(%rsp), %rax
pushq %rax
callq 0x4062c
addq $0x40, %rsp
leaq 0x250(%rsp), %rdi
callq 0x16e30
leaq 0x1d0(%rsp), %rdi
callq 0x16e30
leaq 0x1e8(%rsp), %rdi
callq 0x16e30
leaq 0x200(%rsp), %rdi
callq 0x16e30
leaq 0x4caf8(%rip), %rax     # 0x62510
movl (%rax), %eax
testl %eax, %eax
je 0x15b28
cmpl $0x1, %eax
jne 0x163d8
movl $0xa8, %edi
callq 0x7370
movq %rax, %rbp
movq 0x10(%rsp), %rax
leaq 0x8(%rax), %rsi
leaq 0x20(%rsp), %rdi
callq 0x7480
leaq 0x2fb4a(%rip), %rdx     # 0x4559c
leaq 0x218(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x9b29
leaq 0x4c965(%rip), %rdx     # 0x623d0
movq 0x8(%rsp), %rax
movq 0x58(%rax), %rcx
leaq 0x4ca99(%rip), %rax     # 0x62514
movzbl (%rax), %r9d
movl (%rdx), %eax
leaq 0x4c954(%rip), %rdx     # 0x623dc
movl (%rdx), %r10d
leaq 0x4c9be(%rip), %rdx     # 0x62450
movl (%rdx), %r11d
leaq 0x4c9b8(%rip), %rdx     # 0x62454
movl (%rdx), %ebx
leaq 0x4c9b3(%rip), %rdx     # 0x62458
movl (%rdx), %r14d
leaq 0x4c9ad(%rip), %rdx     # 0x6245c
movl (%rdx), %r15d
leaq 0x4c9a7(%rip), %rdx     # 0x62460
movl (%rdx), %r12d
leaq 0x4c8cd(%rip), %rdx     # 0x62390
movsd (%rdx), %xmm0
movl %r12d, %r13d
shrl $0x9, %r13d
subq $0x8, %rsp
leaq 0x220(%rsp), %rsi
movq %rbp, %rdi
movq 0x18(%rsp), %rdx
movq 0x98(%rsp), %r8
pushq $0x1
pushq $0x0
pushq %r12
pushq %r13
pushq %r15
pushq %r14
pushq %rbx
pushq %r11
pushq %r10
pushq %rax
pushq 0xd8(%rsp)
callq 0x208b8
addq $0x60, %rsp
leaq 0x218(%rsp), %rdi
callq 0x7678
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x15d2b
movl $0xc8, %edi
callq 0x7370
movq %rax, %rbx
movq 0x10(%rsp), %rax
leaq 0x8(%rax), %rsi
leaq 0x50(%rsp), %rdi
movq %rbx, 0x48(%rsp)
callq 0x7480
leaq 0x2fa48(%rip), %rdx     # 0x4559c
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
movq 0x8(%rsp), %rax
movq 0x58(%rax), %rax
movq %rax, 0xa0(%rsp)
leaq 0x4c999(%rip), %rax     # 0x62514
movb (%rax), %al
movb %al, 0x1f(%rsp)
leaq 0x4c800(%rip), %rax     # 0x62388
movl (%rax), %r12d
leaq 0x4c98a(%rip), %rax     # 0x6251c
movl (%rax), %r13d
leaq 0x4c834(%rip), %rax     # 0x623d0
movl (%rax), %r15d
leaq 0x4c836(%rip), %rax     # 0x623dc
movl (%rax), %r14d
leaq 0x4c8a0(%rip), %rax     # 0x62450
movl (%rax), %ebp
leaq 0x4c89b(%rip), %rax     # 0x62454
movl (%rax), %eax
movq %rax, 0xa8(%rsp)
leaq 0x1b8(%rsp), %rdi
leaq 0x150(%rsp), %rsi
callq 0x16dd6
leaq 0x1a0(%rsp), %rdi
leaq 0xd0(%rsp), %rsi
callq 0x16dd6
leaq 0x188(%rsp), %rdi
leaq 0x130(%rsp), %rsi
callq 0x16dd6
movq %rbp, 0x178(%rsp)
movq %r13, 0x180(%rsp)
leaq 0x238(%rsp), %r13
leaq 0x110(%rsp), %rsi
movq %r13, %rdi
callq 0x16dd6
leaq 0x4c827(%rip), %rax     # 0x62458
movl (%rax), %eax
leaq 0x4c822(%rip), %rcx     # 0x6245c
movl (%rcx), %r10d
leaq 0x4c81c(%rip), %rcx     # 0x62460
movl (%rcx), %r11d
movl %r11d, %ebp
shrl $0x9, %ebp
leaq 0x4c73c(%rip), %rcx     # 0x62390
movsd (%rcx), %xmm0
leaq 0x4c8b9(%rip), %rcx     # 0x62518
movl (%rcx), %ebx
subq $0x8, %rsp
movzbl 0x27(%rsp), %r9d
leaq 0x28(%rsp), %rsi
movq 0x50(%rsp), %rdi
movq 0x18(%rsp), %rdx
movq 0xa8(%rsp), %rcx
movq 0x98(%rsp), %r8
pushq $0x1
pushq %rbx
pushq %r11
pushq %rbp
pushq %r10
pushq %rax
pushq %r13
leaq 0x1c8(%rsp), %rax
pushq %rax
leaq 0x1e8(%rsp), %rax
pushq %rax
leaq 0x208(%rsp), %rax
pushq %rax
pushq 0x100(%rsp)
pushq 0x1d8(%rsp)
pushq %r14
pushq %r15
pushq 0xf8(%rsp)
pushq 0x200(%rsp)
pushq %r12
callq 0x214e2
addq $0x90, %rsp
leaq 0x238(%rsp), %rdi
callq 0x16e30
leaq 0x188(%rsp), %rdi
callq 0x16e30
leaq 0x1a0(%rsp), %rdi
callq 0x16e30
leaq 0x1b8(%rsp), %rdi
callq 0x16e30
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
movq 0x48(%rsp), %rbp
callq 0x1f784
movq %rax, %rdi
movq %rbp, %rsi
callq 0x1f7f2
movq 0x10(%rsp), %r14
movq %rbp, 0x38(%r14)
movq 0x78(%rsp), %rcx
movq (%rcx), %rax
movq 0x8(%rcx), %rcx
subq %rax, %rcx
sarq $0x3, %rcx
xorl %edx, %edx
xorpd %xmm0, %xmm0
movsd %xmm0, 0x48(%rsp)
movl %edx, %edx
cmpq %rdx, %rcx
jbe 0x15d80
movq (%rax,%rdx,8), %rsi
movl 0x38(%rsi), %esi
cvtsi2sd %rsi, %xmm0
maxsd 0x48(%rsp), %xmm0
incl %edx
jmp 0x15d5d
movl $0x118, %edi            # imm = 0x118
callq 0x7370
movq %rax, %rbx
movq %r14, %rsi
addq $0x8, %rsi
leaq 0x50(%rsp), %rdi
callq 0x7480
leaq 0x4c62b(%rip), %r15     # 0x623d0
movq %rbp, %r14
leaq 0x2f849(%rip), %rdx     # 0x455f8
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
movsd 0x48(%rsp), %xmm2
divsd 0x2f064(%rip), %xmm2    # 0x44e30
movq 0x8(%rsp), %rax
movq 0x58(%rax), %r9
leaq 0x4c5c4(%rip), %rax     # 0x623a0
movl (%rax), %eax
movq %rax, 0x48(%rsp)
leaq 0x4c5ae(%rip), %rax     # 0x62398
movsd (%rax), %xmm0
leaq 0x4c5af(%rip), %rax     # 0x623a4
movzbl (%rax), %eax
movq %rax, 0x80(%rsp)
leaq 0x4c5a1(%rip), %rax     # 0x623a8
movsd (%rax), %xmm1
movl (%r15), %eax
movq %rax, 0xa8(%rsp)
leaq 0x4c5bf(%rip), %rax     # 0x623dc
movl (%rax), %eax
movq %rax, 0xa0(%rsp)
leaq 0x4c622(%rip), %rax     # 0x62450
movl (%rax), %r15d
leaq 0x4c61c(%rip), %rax     # 0x62454
movl (%rax), %r12d
leaq 0x4c616(%rip), %rax     # 0x62458
movl (%rax), %r13d
leaq 0x4c610(%rip), %rax     # 0x6245c
movl (%rax), %ebp
leaq 0x4c4f3(%rip), %rdx     # 0x62348
movl (%rdx), %ecx
leal 0x1(%rcx), %eax
movl %eax, (%rdx)
leaq 0x4c5fd(%rip), %rax     # 0x62460
movl (%rax), %eax
shrl $0x9, %eax
xorl %r10d, %r10d
testl %ecx, %ecx
leaq 0x4c6b0(%rip), %rcx     # 0x62524
movzbl (%rcx), %r11d
setne %r10b
subq $0x8, %rsp
leaq 0x28(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movq 0x98(%rsp), %rcx
movq 0x78(%rsp), %r8
pushq $0x1b0                  # imm = 0x1B0
pushq $0x64
pushq $0x1
pushq %r10
pushq $0xa
pushq %r11
pushq %rax
pushq %rbp
pushq %r13
pushq %r12
pushq %r15
pushq 0x100(%rsp)
pushq 0x110(%rsp)
pushq 0xf0(%rsp)
pushq 0xc0(%rsp)
callq 0x33b90
addq $0x80, %rsp
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
callq 0x1f784
movq 0x10(%rsp), %r14
movq %rax, %rdi
movq %rbx, %rsi
callq 0x1f7f2
movq 0x90(%rsp), %rdi
movq %rbx, %rsi
callq 0x31846
movq %rbx, 0x48(%r14)
movq 0x78(%rsp), %rax
movq (%rax), %r14
movq 0x8(%rax), %rax
subq %r14, %rax
movq %rax, %r15
sarq $0x3, %r15
movq %r15, %rcx
shrq $0x3e, %rcx
sarq %rax
xorl %r12d, %r12d
negq %rcx
movl $0x0, %edi
sbbq %rdi, %rdi
orq %rax, %rdi
callq 0x7030
movq %rax, %rbx
movl %r12d, %eax
cmpq %rax, %r15
jbe 0x15f65
movq (%r14,%rax,8), %rcx
movl 0x8(%rcx), %ecx
movl %ecx, (%rbx,%rax,4)
leal 0x1(%rax), %r12d
jmp 0x15f4d
leaq 0x4c3ec(%rip), %rax     # 0x62358
movl (%rax), %eax
testl %eax, %eax
je 0x16089
cmpl $0x1, %eax
jne 0x16408
movl $0x110, %edi            # imm = 0x110
callq 0x7370
movq %rax, %rbp
leaq 0x50(%rsp), %rdi
movq 0x88(%rsp), %rsi
callq 0x7480
leaq 0x2f660(%rip), %rdx     # 0x45605
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
movq 0x8(%rsp), %rax
movq 0x58(%rax), %r8
leaq 0x4c398(%rip), %rax     # 0x6235c
movl (%rax), %r9d
leaq 0x4c392(%rip), %rax     # 0x62360
movl (%rax), %eax
leaq 0x4c38d(%rip), %rcx     # 0x62364
movl (%rcx), %r10d
leaq 0x4c387(%rip), %rcx     # 0x62368
movl (%rcx), %r11d
leaq 0x4c475(%rip), %rcx     # 0x62460
movl (%rcx), %r13d
movl %r13d, %r14d
leaq 0x4c3d8(%rip), %rcx     # 0x623d0
imull (%rcx), %r13d
leaq 0x4c3d9(%rip), %rcx     # 0x623dc
imull (%rcx), %r13d
leaq 0x4c442(%rip), %rcx     # 0x62450
imull (%rcx), %r13d
leaq 0x4c43b(%rip), %rcx     # 0x62454
imull (%rcx), %r13d
leaq 0x4c4e8(%rip), %rcx     # 0x6250c
movq 0x78(%rsp), %rdx
movq 0x8(%rdx), %r15
subq (%rdx), %r15
movl (%rcx), %r12d
shrq $0x3, %r15
shrl $0x9, %r14d
shrl $0x9, %r13d
subq $0x8, %rsp
leaq 0x28(%rsp), %rsi
movq %rbp, %rdi
xorl %edx, %edx
movq 0x18(%rsp), %rcx
pushq %r13
pushq %r14
pushq %r15
pushq %r12
pushq %rbx
leaq 0x4c31e(%rip), %rbx     # 0x62380
pushq (%rbx)
leaq 0x4c30d(%rip), %rbx     # 0x62378
pushq (%rbx)
leaq 0x4c2fc(%rip), %rbx     # 0x62370
pushq (%rbx)
pushq %r11
pushq %r10
pushq %rax
callq 0x298d8
addq $0x60, %rsp
jmp 0x1617f
movl $0x100, %edi            # imm = 0x100
callq 0x7370
movq %rax, %rbp
leaq 0x50(%rsp), %rdi
movq 0x88(%rsp), %rsi
callq 0x7480
leaq 0x2f556(%rip), %rdx     # 0x45605
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
leaq 0x4c30b(%rip), %rdx     # 0x623d0
movq 0x8(%rsp), %rax
movq 0x58(%rax), %r8
leaq 0x4c287(%rip), %rax     # 0x6235c
movl (%rax), %r9d
leaq 0x4c281(%rip), %rax     # 0x62360
movl (%rax), %eax
leaq 0x4c27c(%rip), %rcx     # 0x62364
movl (%rcx), %r10d
leaq 0x4c276(%rip), %rcx     # 0x62368
leaq 0x4c367(%rip), %rsi     # 0x62460
movl (%rsi), %r13d
movl %r13d, %r12d
imull (%rdx), %r13d
movl (%rcx), %r11d
leaq 0x4c2cf(%rip), %rcx     # 0x623dc
imull (%rcx), %r13d
leaq 0x4c338(%rip), %rcx     # 0x62450
imull (%rcx), %r13d
movq 0x78(%rsp), %rcx
movq 0x8(%rcx), %r14
subq (%rcx), %r14
leaq 0x4c325(%rip), %rcx     # 0x62454
imull (%rcx), %r13d
leaq 0x4c246(%rip), %r15     # 0x62380
shrq $0x3, %r14
shrl $0x9, %r12d
shrl $0x9, %r13d
leaq 0x20(%rsp), %rsi
movq %rbp, %rdi
xorl %edx, %edx
movq 0x10(%rsp), %rcx
pushq %r13
pushq %r12
pushq %r14
pushq %rbx
pushq (%r15)
leaq 0x4c212(%rip), %rbx     # 0x62378
pushq (%rbx)
leaq 0x4c201(%rip), %rbx     # 0x62370
pushq (%rbx)
pushq %r11
pushq %r10
pushq %rax
callq 0x2b444
addq $0x50, %rsp
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
callq 0x1f784
movq %rax, %rdi
movq %rbp, %rsi
callq 0x1f7f2
movq 0x10(%rsp), %rax
movq %rbp, 0x30(%rax)
movq 0x8(%rsp), %rax
movq %rbp, 0x48(%rax)
leaq 0x4c194(%rip), %rax     # 0x62350
movl (%rax), %eax
testl %eax, %eax
je 0x1625e
cmpl $0x1, %eax
jne 0x162e5
movl $0x90, %edi
callq 0x7370
movq %rax, %rbx
leaq 0x50(%rsp), %rdi
movq 0x88(%rsp), %rsi
callq 0x7480
leaq 0x2f43b(%rip), %rdx     # 0x45630
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
callq 0x41128
leaq 0x4c144(%rip), %rcx     # 0x62354
movzwl (%rcx), %ecx
movq 0x78(%rsp), %rdx
movq 0x8(%rdx), %r9
subq (%rdx), %r9
shrq $0x3, %r9
leaq 0x4c12c(%rip), %rdx     # 0x62356
movzwl (%rdx), %r10d
leaq 0x4c22b(%rip), %rdx     # 0x62460
movl (%rdx), %r11d
shrl $0x9, %r11d
subq $0x8, %rsp
leaq 0x28(%rsp), %rsi
movq %rbx, %rdi
movq %rax, %rdx
movl %ecx, %r8d
pushq %rbp
pushq %r11
pushq %r10
callq 0x350be
addq $0x20, %rsp
jmp 0x162c8
movl $0x90, %edi
callq 0x7370
movq %rax, %rbx
leaq 0x50(%rsp), %rdi
movq 0x88(%rsp), %rsi
callq 0x7480
leaq 0x2f3ac(%rip), %rdx     # 0x45630
leaq 0x20(%rsp), %rdi
leaq 0x50(%rsp), %rsi
callq 0x9b29
leaq 0x4c0ba(%rip), %rax     # 0x62354
movzwl (%rax), %r14d
callq 0x41128
leaq 0x4c1b6(%rip), %rcx     # 0x62460
movl (%rcx), %r8d
shrl $0x9, %r8d
movzwl %r14w, %edx
leaq 0x20(%rsp), %rsi
movq %rbx, %rdi
movq %rax, %rcx
movq %rbp, %r9
callq 0x367c0
movq 0x8(%rsp), %rax
movq %rbx, 0x40(%rax)
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
callq 0x1f784
movq 0x8(%rsp), %rcx
movq 0x40(%rcx), %rsi
movq %rax, %rdi
callq 0x1f7f2
movq 0x8(%rsp), %rax
movq 0x40(%rax), %rsi
movq %rbp, %rdi
callq 0x295de
leaq 0x110(%rsp), %rdi
callq 0x16e30
leaq 0x130(%rsp), %rdi
callq 0x16e30
leaq 0xd0(%rsp), %rdi
callq 0x16e30
leaq 0x150(%rsp), %rdi
callq 0x16e30
addq $0x268, %rsp            # imm = 0x268
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
pushq $0x10
popq %rdi
callq 0x71b0
movq %rax, %rbx
leaq 0x2f2db(%rip), %rsi     # 0x4563f
movq %rax, %rdi
callq 0x7620
movq 0x4bc55(%rip), %rsi     # 0x61fc8
movq 0x4bc2e(%rip), %rdx     # 0x61fa8
movq %rbx, %rdi
callq 0x7590
jmp 0x16408
pushq $0x10
popq %rdi
callq 0x71b0
movq %rax, %rbx
leaq 0x2f159(%rip), %rsi     # 0x454f2
movq %rax, %rdi
callq 0x7620
jmp 0x16464
pushq $0x10
popq %rdi
callq 0x71b0
movq %rax, %rbx
leaq 0x2f192(%rip), %rsi     # 0x4554a
movq %rax, %rdi
callq 0x7620
movq 0x4bc01(%rip), %rsi     # 0x61fc8
movq 0x4bbda(%rip), %rdx     # 0x61fa8
movq %rbx, %rdi
callq 0x7590
jmp 0x16408
pushq $0x10
popq %rdi
callq 0x71b0
movq %rax, %rbx
leaq 0x2f1c6(%rip), %rsi     # 0x455b0
movq %rax, %rdi
callq 0x7620
movq 0x4bbcf(%rip), %rsi     # 0x61fc8
movq 0x4bba8(%rip), %rdx     # 0x61fa8
movq %rbx, %rdi
callq 0x7590
movq 0x4bbe1(%rip), %rdi     # 0x61ff0
leaq 0x2e172(%rip), %rsi     # 0x44588
callq 0x7360
movq 0x4bbce(%rip), %rdi     # 0x61ff0
leaq 0x2f1e7(%rip), %rsi     # 0x45610
callq 0x7360
movq %rax, %rdi
callq 0x71a0
movq 0x4bb93(%rip), %rdi     # 0x61fd0
callq 0x73d0
pushq $0x1
popq %rdi
callq 0x73e0
pushq $0x10
popq %rdi
callq 0x71b0
movq %rax, %rbx
leaq 0x2f04e(%rip), %rsi     # 0x454aa
movq %rax, %rdi
callq 0x7620
movq 0x4bb5d(%rip), %rsi     # 0x61fc8
movq 0x4bb36(%rip), %rdx     # 0x61fa8
movq %rbx, %rdi
callq 0x7590
jmp 0x165dc
movq %rax, %r15
movq %rbx, %rdi
callq 0x72a0
jmp 0x167cd
jmp 0x165dc
movq %rax, %r15
jmp 0x165f9
movq %rax, %r15
jmp 0x16608
jmp 0x164a6
movq %rax, %r15
jmp 0x16635
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x164cf
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x164d4
movq %rax, %r15
jmp 0x164d4
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x16584
jmp 0x164e5
movq %rax, %r15
jmp 0x16584
movq %rax, %r15
leaq 0x238(%rsp), %rdi
callq 0x16e30
jmp 0x16502
movq %rax, %r15
leaq 0x188(%rsp), %rdi
callq 0x16e30
jmp 0x16514
movq %rax, %r15
leaq 0x1a0(%rsp), %rdi
callq 0x16e30
jmp 0x16526
movq %rax, %r15
leaq 0x1b8(%rsp), %rdi
callq 0x16e30
jmp 0x16538
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
movq 0x48(%rsp), %rdi
jmp 0x16638
movq %rax, %r15
leaq 0x218(%rsp), %rdi
callq 0x7678
jmp 0x16570
movq %rax, %r15
jmp 0x16542
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x16584
movq %rax, %r15
jmp 0x1654c
movq %rax, %r15
movq %rbp, %rdi
jmp 0x16638
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x165ad
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x165bc
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x165cb
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x165d0
movq %rax, %r15
jmp 0x165d0
movq %rax, %r15
movq 0x70(%rsp), %rdi
jmp 0x1687a
jmp 0x165dc
movq %rax, %r15
movq %rbx, %rdi
callq 0x72a0
jmp 0x1688e
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x16608
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x16635
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x16626
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x16635
movq %rax, %r15
movq %rbx, %rdi
callq 0x7340
jmp 0x167cd
movq %rax, %r15
leaq 0x250(%rsp), %rdi
callq 0x16e30
jmp 0x16657
movq %rax, %r15
leaq 0x1d0(%rsp), %rdi
callq 0x16e30
jmp 0x16669
movq %rax, %r15
leaq 0x1e8(%rsp), %rdi
callq 0x16e30
jmp 0x1667b
movq %rax, %r15
leaq 0x200(%rsp), %rdi
callq 0x16e30
jmp 0x167cd
movq %rax, %r15
movq %r12, %rdi
jmp 0x1687a
jmp 0x1688b
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x166af
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x166be
movq %rax, %r15
movq 0x10(%rsp), %rdi
jmp 0x1687a
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x166da
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x166e9
movq %rax, %r15
jmp 0x16748
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
jmp 0x168a5
movq %rax, %r15
jmp 0x168a5
jmp 0x1688b
jmp 0x1688b
jmp 0x1688b
jmp 0x1688b
jmp 0x16722
jmp 0x1688b
jmp 0x16722
movq %rax, %r15
jmp 0x167cd
jmp 0x16767
jmp 0x16755
jmp 0x167ac
jmp 0x1678b
jmp 0x16779
jmp 0x1679d
jmp 0x167bb
jmp 0x167c0
jmp 0x1688b
movq %rax, %r15
movq %rbx, %rdi
jmp 0x1687a
jmp 0x1688b
movq %rax, %r15
leaq 0xf0(%rsp), %rdi
callq 0x11edc
jmp 0x1678e
movq %rax, %r15
leaq 0xf0(%rsp), %rdi
callq 0x11edc
jmp 0x1677c
movq %rax, %r15
leaq 0xb0(%rsp), %rdi
callq 0x11edc
jmp 0x167af
movq %rax, %r15
leaq 0xb0(%rsp), %rdi
callq 0x11edc
jmp 0x167a0
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x11edc
jmp 0x167c3
movq %rax, %r15
leaq 0x50(%rsp), %rdi
callq 0x11edc
jmp 0x167c3
movq %rax, %r15
jmp 0x167c3
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x11edc
leaq 0x110(%rsp), %rdi
callq 0x16e30
leaq 0x130(%rsp), %rdi
callq 0x16e30
leaq 0xd0(%rsp), %rdi
callq 0x16e30
leaq 0x150(%rsp), %rdi
callq 0x16e30
jmp 0x1688e
movq %rax, %r15
jmp 0x16877
movq %rax, %r15
jmp 0x16834
movq %rax, %r15
jmp 0x16850
movq %rax, %r15
jmp 0x16827
movq %rax, %r15
leaq 0x20(%rsp), %rdi
callq 0x7678
leaq 0xb0(%rsp), %rdi
callq 0x7678
leaq 0x50(%rsp), %rdi
callq 0x7678
jmp 0x16843
movq %rax, %r15
leaq 0x150(%rsp), %rdi
callq 0x7678
leaq 0x110(%rsp), %rdi
callq 0x7678
leaq 0xd0(%rsp), %rdi
callq 0x7678
leaq 0x130(%rsp), %rdi
callq 0x7678
movq %r13, %rdi
callq 0x7340
jmp 0x1688e
movq %rax, %r15
jmp 0x1685d
movq %rax, %r15
jmp 0x1686a
movq %rax, %r15
movq 0x170(%rsp), %rdi
callq 0x16ec6
movq 0x8(%rsp), %rdi
callq 0x11c8c
movq %r15, %rdi
callq 0x75d0
nop