// File: /workspace/github_cpp_makefile_star2_O2/0x6D70[P]chip8_emu/src/cpu.cpp
// Function: Cpu::run(SDL_Renderer*)
void Cpu::run(SDL_Renderer *renderer) {

    bool isFinished = false;
    bool update_video = false;
    uint64_t instruction_count = 0;

    SDL_Event event;

    // variable for keyboard
    bool keys[0x10] = {false};
    

    while (!isFinished) {
        instruction_count++;

        uint16_t opcode = this->mem_read_u16(this->state.pc);
        this->state.pc += 2;

        //  uncomment for single stepping
        // std::cout << "0x" << std::hex << opcode;
        // getchar();

        uint8_t opcode_n3 = opcode & 0xf;
        uint8_t opcode_n2 = (opcode >> 4) & 0xf;
        uint8_t opcode_n1 = (opcode >> 8) & 0xf;
        uint8_t opcode_n0 = (opcode >> 12) & 0xf;

        switch (opcode_n0) {
            case 0x0: {
                if (opcode == 0x00e0) {
                    // cls
                    update_video = true;
                    for (int y = 0; y < VIDEO_HEIGHT; y++) {
                        for (int x = 0; x < VIDEO_WIDTH; x++) {
                            this->state.video[x][y] = false;
                        }
                    }
                } else if (opcode == 0x00ee) {
                    // ret
                    this->state.pc = this->state.call_stack.top();
                    this->state.call_stack.pop();
                } else {
                    // sys addr
                    // this instruction is ignored
                    // http://devernay.free.fr/hacks/chip8/C8TECH10.HTM#0nnn
                }
                break;
            }
            case 0x1: {
                // JP addr
                this->state.pc = opcode & 0xfff;
                break;
            }
            case 0x2: {
                // CALL addr
                this->state.call_stack.push(this->state.pc);
                this->state.pc = opcode & 0xfff;
                break;
            }
            case 0x3: {
                // SE Vx, byte
                if (this->state.regs[opcode_n1] == (uint8_t)(opcode & 0xff)) {
                    // skip instruction
                    this->state.pc += 2;
                }
                break;
            }
            case 0x4: {
                // SNE Vx, byte
                if (this->state.regs[opcode_n1] != (uint8_t)(opcode & 0xff)) {
                    // skip instruction
                    this->state.pc += 2;
                }
                break;
            }
            case 0x5: {
                // SE Vx, Vy
                if (this->state.regs[opcode_n1] == this->state.regs[opcode_n2]) {
                    // skip instruction
                    this->state.pc += 2;
                }
                break;
            }
            case 0x6: {
                // ld vx,byte
                this->state.regs[opcode_n1] = (uint8_t)(opcode & 0xff);
                break;
            }
            case 0x7: {
                // ADD Vx, byte
                this->state.regs[opcode_n1] += (opcode & 0xff);
                break;
            }
            case 0x8: {
                // logical and arithmetic instruction
                switch (opcode_n3) {
                    case 0x0: {
                        this->state.regs[opcode_n1] = this->state.regs[opcode_n2];
                        break;
                    }
                    case 0x1: {
                        this->state.regs[opcode_n1] |= this->state.regs[opcode_n2];
                        break;
                    }
                    case 0x2: {
                        this->state.regs[opcode_n1] &= this->state.regs[opcode_n2];
                        break;
                    }
                    case 0x3: {
                        this->state.regs[opcode_n1] ^= this->state.regs[opcode_n2];
                        break;
                    }
                    case 0x4: {
                        // check overflow
                        if ((uint16_t)this->state.regs[opcode_n1] + (uint16_t)this->state.regs[opcode_n2] > 0xff) {
                            this->state.regs[0xf] = 1;
                        } else {
                            this->state.regs[0xf] = 0;
                        }

                        this->state.regs[opcode_n1] += this->state.regs[opcode_n2];
                        break;
                    }
                    case 0x5: {
                        if (this->state.regs[opcode_n1] > this->state.regs[opcode_n2]) {
                            this->state.regs[0xf] = 1;
                        } else {
                            this->state.regs[0xf] = 0;
                        }

                        this->state.regs[opcode_n1] -= this->state.regs[opcode_n2];
                        break;
                    }
                    case 0x6: {
                        this->state.regs[opcode_n1] = this->state.regs[opcode_n2];
                        // shift right

                        this->state.regs[0xf] = this->state.regs[opcode_n1] & 1;
                        this->state.regs[opcode_n1] >>= 1;

                        break;
                    }
                    case 0x7: {
                        if (this->state.regs[opcode_n2] > this->state.regs[opcode_n1]) {
                            this->state.regs[0xf] = 1;
                        } else {
                            this->state.regs[0xf] = 0;
                        }
                        
                        this->state.regs[opcode_n1] = this->state.regs[opcode_n2] - this->state.regs[opcode_n1];
                        break;
                    }
                    case 0xe: {
                        this->state.regs[opcode_n1] = this->state.regs[opcode_n2];
                        // shift left

                        this->state.regs[0xf] = (this->state.regs[opcode_n1] >> 7) & 1;
                        this->state.regs[opcode_n1] <<= 1;

                        break;
                    }
                }
                break;
            }
            case 0x9: {
                // SNE Vx, Vy
                if (this->state.regs[opcode_n1] != this->state.regs[opcode_n2]) {
                    // skip instruction
                    this->state.pc += 2;
                }
                break;
            }
            case 0xa: {
                // ld l, addr
                this->state.l = opcode & 0xfff;
                break;
            }
            case 0xb: {
                // Bnnn - JP V0, addr
                this->state.pc = (opcode & 0xfff) + this->state.regs[0x0];
                break;
            }
            case 0xc: {
                // Cxkk - RND Vx, byte
                this->state.regs[opcode_n1] = (uint8_t)(rand() & (opcode & 0xff));
                break;
            }
            case 0xd: {
                // DXYN
                uint8_t x_base = this->state.regs[opcode_n1] % 64;
                uint8_t y_base = this->state.regs[opcode_n2] % 32;
                this->state.regs[0xf] = 0;
                update_video = true;

                for (int n = 0; n < opcode_n3; n++) {
                    uint8_t pixels = this->state.ram[this->state.l + n];

                    for (int x = 0; x < 8; x++) {
                        if (pixels & (0x80 >> x)) {
                            // current bit is one

                            if (this->state.video[x_base + x][y_base + n]) {
                                this->state.regs[0xf] = 1;
                                // flip bit
                                this->state.video[x_base + x][y_base + n] = false;
                            } else {
                                this->state.video[x_base + x][y_base + n] = true;
                            }
                        }
                    }

                }

                break;
            }
            case 0xe: {
                switch (opcode & 0xff) {
                    case 0x9e: {
                        // Ex9E - SKP Vx
                        uint8_t index = this->state.regs[opcode_n1] & 0xf;
                        if (keys[index])
                            this->state.pc += 2;
                        break;
                    }
                    case 0xa1: {
                        // ExA1 - SKNP Vx
                        uint8_t index = this->state.regs[opcode_n1] & 0xf;
                        if (!keys[index])
                            this->state.pc += 2;
                        break;
                    }
                }
                break;
            }
            case 0xf: {

                switch (opcode & 0xff) { 
                    case 0x7: {
                        // LD Vx, DT
                        this->state.regs[opcode_n1] = this->state.delay_timer;
                        break;
                    }
                    case 0xa: {
                        // LD Vx, K
                        // wait until key is pressed
                        // when the key is pressed, put it into Vx

                        if (isKeyPressed(keys)) {
                            for (int i = 0; i < 0x10; i++) {
                                if (keys[i]) {
                                    this->state.regs[opcode_n1] = i;
                                }
                            }
                        } else {
                            // decrement pc to hit this instruction again
                            this->state.pc -= 2;
                        }
                        break;
                    }
                    case 0x15: {
                        // LD DT, Vx
                        this->state.delay_timer = this->state.regs[opcode_n1];
                        break;
                    }
                    case 0x18: {
                        // LD ST, Vx
                        this->state.sound_timer = this->state.regs[opcode_n1];
                        break;
                    }
                    case 0x1e: {
                        // ADD I, Vx
                        this->state.l += this->state.regs[opcode_n1];

                        if (this->state.l > 0xfff) {
                            this->state.regs[0xf] = 1;
                        } else {
                            this->state.regs[0xf] = 0;
                        }

                        this->state.l &= 0xfff;
                        break;
                    }
                    case 0x29: {
                        // LD F, Vx
                        this->state.l = 0x50 + (opcode & 0xff) * 5;
                        break;
                    }
                    case 0x33: {
                        // Fx33 - LD B, Vx
                        // Binary-coded decimal conversion

                        this->state.ram[this->state.l + 0] = this->state.regs[opcode_n1] / 100;
                        this->state.ram[this->state.l + 1] = (this->state.regs[opcode_n1] / 10) % 10;
                        this->state.ram[this->state.l + 2] = this->state.regs[opcode_n1] % 10;

                        break;
                    }
                    case 0x55: {
                        // LD [I], Vx

                        for (int i = 0; i <= opcode_n1; i++) {
                            this->state.ram[this->state.l + i] = this->state.regs[i];
                        }

                        break;
                    }
                    case 0x65: {
                        // LD Vx, [I]

                        for (int i = 0; i <= opcode_n1; i++) {
                            this->state.regs[i] = this->state.ram[this->state.l + i];
                        }

                        break;
                    }
                }
                break;
            }
            default:
                std::cout << "missing instruction 0x" << std::hex << (int)opcode_n0 << std::endl;
                isFinished = true;
        }

        // update timers

        if (instruction_count % 10  == 0) {
            // ownly decrease every 10 instructions which should be a rate of about ~60 times a second

            if (this->state.delay_timer > 0)
                this->state.delay_timer--;
            if (this->state.sound_timer > 0)
                this->state.sound_timer--;
        }

        if (update_video || instruction_count % 0x100 == 0) {
            // video array has changed => update window

            SDL_RenderClear(renderer);

            for (int y = 0; y < VIDEO_HEIGHT; y++) {
                for (int x = 0; x < VIDEO_WIDTH; x++) {
                    if (this->state.video[x][y]) {
                        // white
                        SDL_SetRenderDrawColor(renderer, 255, 255, 255, 255);
                    } else {
                        // black
                        SDL_SetRenderDrawColor(renderer, 0, 0, 0, 255);
                    }

                    SDL_Rect rect;
                    rect.h = VIDEO_MULTI;
                    rect.w = VIDEO_MULTI;
                    rect.x = x * VIDEO_MULTI;
                    rect.y = y * VIDEO_MULTI;

                    SDL_RenderFillRect(renderer, &rect);
                }
            }

            SDL_RenderPresent(renderer);

            update_video = false;
        }

        while(SDL_PollEvent(&event)) {
            switch (event.type) {
                case SDL_QUIT:
                    isFinished = true;
                    break;
                case SDL_KEYDOWN: {
                    uint8_t index = keysym_to_index(event.key.keysym);

                    if (index < 0x10) {
                        keys[index] = true;
                    }
                    
                    break;
                }
                case SDL_KEYUP: {
                    uint8_t index = keysym_to_index(event.key.keysym);

                    if (index < 0x10) {
                        keys[index] = false;
                    }

                    break;
                }
            }
        }

        SDL_Delay(1);
    }

    std::cout << "Exited after 0x" << std::hex << (long)instruction_count << " instructions\n";
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rsi, %r14
xorps %xmm0, %xmm0
leaq -0xa0(%rbp), %rax
movaps %xmm0, (%rax)
leaq 0x1860(%rdi), %rax
movq %rax, -0x38(%rbp)
leaq 0x1000(%rdi), %rax
movq %rax, -0x30(%rbp)
leaq 0x1010(%rdi), %rax
movq %rax, -0x80(%rbp)
leaq 0x1810(%rdi), %rax
movq %rax, -0xa8(%rbp)
movq $0x0, -0x88(%rbp)
xorl %r15d, %r15d
movq %rdi, -0x40(%rbp)
testb $0x1, %r15b
jne 0x2dcd
movzwl 0x1860(%rdi), %r8d
movzbl (%rdi,%r8), %ecx
movl %ecx, %r13d
shll $0x8, %r13d
leal 0x1(%r8), %eax
movzwl %ax, %eax
movzbl (%rdi,%rax), %r15d
orl %r15d, %r13d
leal 0x2(%r8), %eax
movw %ax, 0x1860(%rdi)
movl %r15d, %eax
andl $0xf, %eax
movl %r15d, %esi
shrl $0x4, %esi
movl %ecx, %r12d
andl $0xf, %r12d
shrl $0x4, %ecx
leaq 0x19b0(%rip), %rdx      # 0x4088
movslq (%rdx,%rcx,4), %rcx
addq %rdx, %rcx
jmpq *%rcx
cmpl $0xee, %r13d
je 0x29c8
cmpl $0xe0, %r13d
jne 0x2962
movq -0x80(%rbp), %rax
xorl %ecx, %ecx
leaq -0x78(%rbp), %rbx
cmpq $0x20, %rcx
je 0x2942
xorl %edx, %edx
cmpq $0x800, %rdx            # imm = 0x800
je 0x2724
movb $0x0, (%rax,%rdx)
addq $0x20, %rdx
jmp 0x2711
incq %rcx
incq %rax
jmp 0x2705
cmpl $0xa1, %r15d
je 0x299a
cmpl $0x9e, %r15d
leaq -0x78(%rbp), %rbx
jne 0x2c3d
movq -0x30(%rbp), %rax
movzbl (%rax,%r12), %eax
andl $0xf, %eax
cmpb $0x1, -0xa0(%rbp,%rax)
je 0x29b8
jmp 0x2c3d
andl $0xfff, %r13d           # imm = 0xFFF
movq -0x30(%rbp), %rax
movzbl (%rax), %eax
addl %r13d, %eax
jmp 0x28b5
movq -0x30(%rbp), %rax
cmpb %r15b, (%rax,%r12)
jne 0x28b1
jmp 0x2962
callq 0x20a0
movq -0x40(%rbp), %rdi
andb %r15b, %al
movq -0x30(%rbp), %rcx
movb %al, (%rcx,%r12)
jmp 0x2962
movq -0x30(%rbp), %rcx
movb (%rcx,%r12), %al
cmpb (%rcx,%rsi), %al
jne 0x28b1
jmp 0x2962
movq -0xa8(%rbp), %rdi
movq -0x38(%rbp), %rbx
movq %rbx, %rsi
callq 0x326c
movq -0x40(%rbp), %rdi
andl $0xfff, %r13d           # imm = 0xFFF
movw %r13w, (%rbx)
jmp 0x2962
cmpl $0x7, %r15d
je 0x2a78
cmpl $0xa, %r15d
je 0x2ba1
cmpl $0x15, %r15d
leaq -0x78(%rbp), %rbx
je 0x2b28
cmpl $0x18, %r15d
je 0x2a0f
cmpl $0x1e, %r15d
je 0x2a4c
cmpl $0x29, %r15d
je 0x2b1a
cmpl $0x33, %r15d
je 0x2a8b
cmpl $0x55, %r15d
je 0x2a22
cmpl $0x65, %r15d
jne 0x2c3d
incb %r12b
movzbl %r12b, %eax
movq -0x30(%rbp), %rcx
subq $0x1, %rax
jb 0x2c3d
movzwl 0x1862(%rdi), %edx
movb -0x1000(%rcx,%rdx), %dl
movb %dl, (%rcx)
incq %rcx
jmp 0x2851
movq -0x30(%rbp), %rax
cmpb %r15b, (%rax,%r12)
je 0x28b1
jmp 0x2962
movq -0x30(%rbp), %rax
addb %r15b, (%rax,%r12)
jmp 0x2962
andl $0xfff, %r13d           # imm = 0xFFF
movq -0x38(%rbp), %rax
movw %r13w, (%rax)
jmp 0x2962
movq -0x30(%rbp), %rcx
movb (%rcx,%r12), %al
cmpb (%rcx,%rsi), %al
jne 0x2962
leal 0x4(%r8), %eax
movq -0x38(%rbp), %rcx
movw %ax, (%rcx)
jmp 0x2962
movzbl 0x1000(%rdi,%r12), %edx
andl $0x3f, %edx
movzbl 0x1000(%rdi,%rsi), %ecx
andl $0x1f, %ecx
movb $0x0, 0x100f(%rdi)
movzwl 0x1862(%rdi), %esi
shll $0x5, %edx
orq %rcx, %rdx
addq -0x80(%rbp), %rdx
xorl %r11d, %r11d
leaq -0x78(%rbp), %rbx
cmpq %rax, %r11
je 0x2942
leaq (%r11,%rsi), %rcx
movzbl (%rdi,%rcx), %r8d
movq %rdx, %r9
xorl %ecx, %ecx
cmpq $0x8, %rcx
je 0x293a
movl %r8d, %r10d
shll %cl, %r10d
testb %r10b, %r10b
jns 0x2931
movb $0x1, %r10b
cmpb $0x1, (%r9)
jne 0x292e
movb $0x1, 0x100f(%rdi)
xorl %r10d, %r10d
movb %r10b, (%r9)
incq %rcx
addq $0x20, %r9
jmp 0x290a
incq %r11
incq %rdx
jmp 0x28f7
movb $0x1, %cl
jmp 0x2c3f
movq -0x30(%rbp), %rax
movb %r15b, (%rax,%r12)
jmp 0x2962
andl $0xfff, %r13d           # imm = 0xFFF
movw %r13w, 0x1862(%rdi)
xorl %ecx, %ecx
leaq -0x78(%rbp), %rbx
jmp 0x2c3f
xorl %ecx, %ecx
cmpb $0xe, %al
ja 0x2964
movzbl %al, %eax
leaq 0x174b(%rip), %rdx      # 0x40c8
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
leaq -0x78(%rbp), %rbx
jmpq *%rax
movq -0x30(%rbp), %rcx
movb (%rcx,%rsi), %al
movb %al, (%rcx,%r12)
jmp 0x2c3d
movq -0x30(%rbp), %rax
movzbl (%rax,%r12), %eax
andl $0xf, %eax
cmpb $0x0, -0xa0(%rbp,%rax)
leaq -0x78(%rbp), %rbx
jne 0x2c3d
leal 0x4(%r8), %eax
movq -0x38(%rbp), %rcx
movw %ax, (%rcx)
jmp 0x2c3d
movq 0x1840(%rdi), %rax
cmpq 0x1848(%rdi), %rax
leaq -0x78(%rbp), %rbx
jne 0x29ef
movq 0x1858(%rdi), %rax
movq -0x8(%rax), %rax
movl $0x200, %ecx            # imm = 0x200
addq %rcx, %rax
movzwl -0x2(%rax), %eax
movq -0x38(%rbp), %rcx
movw %ax, (%rcx)
movq -0xa8(%rbp), %rdi
callq 0x3206
movq -0x40(%rbp), %rdi
jmp 0x2c3d
movb 0x1000(%rdi,%r12), %al
movb %al, 0x1865(%rdi)
jmp 0x2c3d
incb %r12b
movzbl %r12b, %eax
movq -0x30(%rbp), %rcx
subq $0x1, %rax
jb 0x2c3d
movb (%rcx), %dl
movzwl 0x1862(%rdi), %esi
movb %dl, -0x1000(%rcx,%rsi)
incq %rcx
jmp 0x2a2d
movzbl 0x1000(%rdi,%r12), %eax
addw 0x1862(%rdi), %ax
cmpw $0x1000, %ax            # imm = 0x1000
setae 0x100f(%rdi)
andl $0xfff, %eax            # imm = 0xFFF
movw %ax, 0x1862(%rdi)
jmp 0x2c3d
movb 0x1864(%rdi), %al
movb %al, 0x1000(%rdi,%r12)
jmp 0x2962
movzbl 0x1000(%rdi,%r12), %eax
movb $0x64, %cl
divb %cl
movzwl 0x1862(%rdi), %ecx
movb %al, (%rdi,%rcx)
movzbl 0x1000(%rdi,%r12), %eax
movb $0xa, %dl
divb %dl
movzbl %al, %eax
divb %dl
movzbl %ah, %eax
movzwl 0x1862(%rdi), %ecx
movb %al, 0x1(%rcx,%rdi)
movzbl 0x1000(%rdi,%r12), %eax
divb %dl
movzbl %ah, %eax
movzwl 0x1862(%rdi), %ecx
movb %al, 0x2(%rcx,%rdi)
jmp 0x2c3d
movq -0x30(%rbp), %rcx
movb (%rcx,%rsi), %al
andb %al, (%rcx,%r12)
jmp 0x2c3d
movb 0x1000(%rdi,%r12), %al
cmpb 0x1000(%rdi,%rsi), %al
seta 0x100f(%rdi)
movb 0x1000(%rdi,%rsi), %al
subb %al, 0x1000(%rdi,%r12)
jmp 0x2c3d
movw $0x11d, 0x1862(%rdi)    # imm = 0x11D
jmp 0x2c3d
movb 0x1000(%rdi,%r12), %al
movb %al, 0x1864(%rdi)
jmp 0x2c3d
movq -0x30(%rbp), %rcx
movb (%rcx,%rsi), %al
orb %al, (%rcx,%r12)
jmp 0x2c3d
movb 0x1000(%rdi,%rsi), %al
movb %al, 0x1000(%rdi,%r12)
andb $0x1, %al
movb %al, 0x100f(%rdi)
shrb 0x1000(%rdi,%r12)
jmp 0x2c3d
movb 0x1000(%rdi,%rsi), %al
cmpb 0x1000(%rdi,%r12), %al
seta 0x100f(%rdi)
movb 0x1000(%rdi,%rsi), %al
subb 0x1000(%rdi,%r12), %al
movb %al, 0x1000(%rdi,%r12)
jmp 0x2c3d
movq %r8, %r15
leaq -0xa0(%rbp), %rdi
callq 0x25fc
testb %al, %al
leaq -0x78(%rbp), %rbx
je 0x2dba
xorl %eax, %eax
movq -0x40(%rbp), %rdi
cmpq $0x10, %rax
je 0x2c3d
cmpb $0x1, -0xa0(%rbp,%rax)
jne 0x2bda
movq -0x30(%rbp), %rcx
movb %al, (%rcx,%r12)
incq %rax
jmp 0x2bc2
movq -0x30(%rbp), %rcx
movb (%rcx,%rsi), %al
xorb %al, (%rcx,%r12)
jmp 0x2c3d
movzbl 0x1000(%rdi,%r12), %eax
movzbl 0x1000(%rdi,%rsi), %ecx
addl %eax, %ecx
cmpl $0x100, %ecx            # imm = 0x100
setae 0x100f(%rdi)
movb 0x1000(%rdi,%rsi), %al
addb %al, 0x1000(%rdi,%r12)
jmp 0x2c3d
movb 0x1000(%rdi,%rsi), %al
movb %al, 0x1000(%rdi,%r12)
shrb $0x7, %al
movb %al, 0x100f(%rdi)
shlb 0x1000(%rdi,%r12)
xorl %ecx, %ecx
movq -0x88(%rbp), %rsi
incq %rsi
movq %rsi, %rax
xorl %edx, %edx
pushq $0xa
popq %r8
divq %r8
testq %rdx, %rdx
jne 0x2c7e
movb 0x1864(%rdi), %al
testb %al, %al
je 0x2c6c
decb %al
movb %al, 0x1864(%rdi)
movb 0x1865(%rdi), %al
testb %al, %al
je 0x2c7e
decb %al
movb %al, 0x1865(%rdi)
movq %rsi, -0x88(%rbp)
testb %sil, %sil
sete %al
orb %al, %cl
cmpb $0x1, %cl
jne 0x2d49
movq %r14, %rdi
callq 0x21c0
movq -0x80(%rbp), %r15
xorl %r13d, %r13d
cmpq $0x20, %r13
je 0x2d3d
imull $0x14, %r13d, %ebx
movq %r15, -0xb0(%rbp)
xorl %r12d, %r12d
cmpq $0x500, %r12            # imm = 0x500
je 0x2d2b
cmpb $0x1, (%r15)
jne 0x2ce0
movq %r14, %rdi
movl $0xff, %esi
movl $0xff, %edx
movl $0xff, %ecx
jmp 0x2ce9
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
movl $0xff, %r8d
callq 0x2240
movabsq $0x1400000014, %rax     # imm = 0x1400000014
movq %rax, -0xb8(%rbp)
movl %r12d, -0xc0(%rbp)
movl %ebx, -0xbc(%rbp)
movq %r14, %rdi
leaq -0xc0(%rbp), %rsi
callq 0x2110
addq $0x14, %r12
addq $0x20, %r15
jmp 0x2cbd
incq %r13
movq -0xb0(%rbp), %r15
incq %r15
jmp 0x2ca5
movq %r14, %rdi
callq 0x2070
leaq -0x78(%rbp), %rbx
xorl %r15d, %r15d
movq %rbx, %rdi
callq 0x2130
testl %eax, %eax
je 0x2da9
movl -0x78(%rbp), %eax
cmpl $0x300, %eax            # imm = 0x300
je 0x2d8f
cmpl $0x301, %eax            # imm = 0x301
je 0x2d75
cmpl $0x100, %eax            # imm = 0x100
jne 0x2d4c
movb $0x1, %r15b
jmp 0x2d4c
movq -0x68(%rbp), %rdi
callq 0x2580
cmpb $0xf, %al
ja 0x2d4c
movzbl %al, %eax
movb $0x0, -0xa0(%rbp,%rax)
jmp 0x2d4c
movq -0x68(%rbp), %rdi
callq 0x2580
cmpb $0xf, %al
ja 0x2d4c
movzbl %al, %eax
movb $0x1, -0xa0(%rbp,%rax)
jmp 0x2d4c
pushq $0x1
popq %rdi
callq 0x2150
movq -0x40(%rbp), %rdi
jmp 0x2683
movq -0x38(%rbp), %rax
movw %r15w, (%rax)
xorl %ecx, %ecx
movq -0x40(%rbp), %rdi
jmp 0x2c3f
movq 0x3204(%rip), %rdi      # 0x5fd8
leaq 0x1388(%rip), %rsi      # 0x4163
callq 0x21e0
movq (%rax), %rcx
movq -0x18(%rcx), %rcx
movl 0x18(%rax,%rcx), %edx
andl $-0x4b, %edx
orl $0x8, %edx
movl %edx, 0x18(%rax,%rcx)
movq %rax, %rdi
movq -0x88(%rbp), %rsi
callq 0x21d0
leaq 0x1368(%rip), %rsi      # 0x4173
movq %rax, %rdi
callq 0x21e0
addq $0x98, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop