// File: /workspace/github_cpp_makefile_star2_O2/gvaumour[P]cache-simulator/src/SimplePerceptron.cc
// Function: SimplePerceptronPredictor::checkLazyMigration(CacheEntry*, unsigned long, bool, unsigned long, bool)
CacheEntry*
SimplePerceptronPredictor::checkLazyMigration(CacheEntry* current ,uint64_t set,bool inNVM, uint64_t index, bool isWrite)
{

	int yout = 0;
	for(unsigned i = 0 ; i < m_features.size() ; i++)
	{
		int hash = hashing_function1( m_features_hash[i] , current->address , current->missPC );
		int pred = m_features[i]->getCounter(hash);
		yout += pred;
	}
	
	if ( abs(yout) < simu_parameters.simple_perceptron_learningTreshold)
		return current;

	allocDecision des = yout > 0 ? ALLOCATE_IN_NVM : ALLOCATE_IN_SRAM;

	if( inNVM == false && des == ALLOCATE_IN_NVM)
	{
		//cl is SRAM , check whether we should migrate to NVM 
		if(simu_parameters.enableDatasetSpilling && m_isNVMbusy[set])
		{
			//reportSpilling(rap_current, current->address, false ,  inNVM);
			//stats_busyness_migrate_change++; //If NVM tab is busy , don't migrate
		}
		else
		{
			//Trigger Migration
			int id_assocNVM = evictPolicy(set, true);//Select LRU candidate from NVM cache
			//DPRINTF("DBAMBPredictor:: Migration Triggered from SRAM, index %ld, id_assoc %d \n" , index, id_assoc);

			CacheEntry* replaced_entry_NVM = m_tableNVM[set][id_assocNVM];
					
			/** Migration incurs one read and one extra write */ 
			replaced_entry_NVM->nbWrite++;
			current->nbRead++;
		
			/* Record the write error migration */ 
			Predictor::migrationRecording();
		
			reportMigration(current, false , isWrite);
		
			m_cache->triggerMigration(set, index , id_assocNVM , false);
			if(!m_isWarmup)
				stats_nbMigrations[true]++;


			current = replaced_entry_NVM;
		}

	}
	else if( des == ALLOCATE_IN_SRAM && inNVM == true)
	{
		//cl is in NVM , check whether we should migrate to SRAM 
			
		//If SRAM tab is busy , don't migrate
		if(simu_parameters.enableDatasetSpilling && m_isSRAMbusy[set])
		{
			//reportSpilling(rap_current, current->address, false ,  inNVM);
			//stats_busyness_migrate_change++; //If NVM tab is busy , don't migrate
		}
		else 
		{		
			int id_assocSRAM = evictPolicy(set, false);
		
			CacheEntry* replaced_entry_SRAM = m_tableSRAM[set][id_assocSRAM];

			/** Migration incurs one read and one extra write */ 
			replaced_entry_SRAM->nbWrite++;
			current->nbRead++;
			reportMigration( current, true , isWrite);
	
			m_cache->triggerMigration(set, id_assocSRAM , index , true);
		
			if(!m_isWarmup)
				stats_nbMigrations[false]++;

			current = replaced_entry_SRAM;		
		}

	}
	return current;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r8, 0x18(%rsp)
movl %ecx, 0x14(%rsp)
movq %rdx, 0x8(%rsp)
movq %rsi, %r12
movq %rdi, %rbx
xorl %eax, %eax
leaq 0x20(%rsp), %r13
xorl %r15d, %r15d
movl %eax, %ebp
movq 0x278(%rbx), %rax
subq 0x270(%rbx), %rax
sarq $0x3, %rax
cmpq %rbp, %rax
jbe 0x23d78
imulq $0x28, %rbp, %rsi
addq 0x288(%rbx), %rsi
movq %r13, %rdi
callq 0x9f3a
movq 0x8(%r12), %rsi
movq 0x20(%r12), %rdx
movq %r13, %rdi
callq 0x11de8
movl %eax, %r14d
movq %r13, %rdi
callq 0x5618
movq 0x270(%rbx), %rax
movq (%rax,%rbp,8), %rdi
movl %r14d, %esi
callq 0x22264
addl %eax, %r15d
leal 0x1(%rbp), %eax
jmp 0x23d14
movl %r15d, %ecx
negl %ecx
cmovsl %r15d, %ecx
leaq 0x1a1c8(%rip), %rax     # 0x3df50
cmpl 0x248(%rax), %ecx
jl 0x23ef6
movl 0x14(%rsp), %edx
testb %dl, %dl
jne 0x23e50
testl %r15d, %r15d
jle 0x23e50
cmpb $0x1, 0x158(%rax)
jne 0x23dcc
leaq 0x110(%rbx), %rdi
movq 0x8(%rsp), %rsi
callq 0x9f66
testq %rdx, (%rax)
jne 0x23ef6
movq (%rbx), %rax
pushq $0x1
popq %rdx
movq %rbx, %rdi
movq 0x8(%rsp), %r13
movl %r13d, %esi
callq *0x28(%rax)
movq 0x10(%rbx), %rcx
movq (%rcx), %rcx
imulq $0x18, %r13, %rdx
movslq %eax, %r14
movq (%rcx,%rdx), %rax
movq (%rax,%r14,8), %r15
incl 0x11c(%r15)
incl 0x120(%r12)
movq %rbx, %rdi
callq 0x1fe30
movq %rbx, %rdi
movq %r12, %rsi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x24480
movq 0x70(%rbx), %rdi
movl %r13d, %esi
movq 0x18(%rsp), %rdx
movl %r14d, %ecx
xorl %r8d, %r8d
callq 0x163be
cmpb $0x0, 0x81(%rbx)
jne 0x23ef3
movq 0x350(%rbx), %rax
addq $0x4, %rax
jmp 0x23ef1
xorb $0x1, %dl
testl %r15d, %r15d
setg %cl
orb %dl, %cl
jne 0x23ef6
cmpb $0x1, 0x158(%rax)
jne 0x23e80
leaq 0xe8(%rbx), %rdi
movq 0x8(%rsp), %rsi
callq 0x9f66
testq %rdx, (%rax)
jne 0x23ef6
movq (%rbx), %rax
movq %rbx, %rdi
movq 0x8(%rsp), %r13
movl %r13d, %esi
xorl %edx, %edx
callq *0x28(%rax)
movq 0x8(%rbx), %rcx
movq (%rcx), %rcx
imulq $0x18, %r13, %rdx
movslq %eax, %r14
movq (%rcx,%rdx), %rax
movq (%rax,%r14,8), %r15
incl 0x11c(%r15)
incl 0x120(%r12)
pushq $0x1
popq %rbp
movq %rbx, %rdi
movq %r12, %rsi
movl %ebp, %edx
xorl %ecx, %ecx
callq 0x24480
movq 0x70(%rbx), %rdi
movl %r13d, %esi
movl %r14d, %edx
movq 0x18(%rsp), %rcx
movl %ebp, %r8d
callq 0x163be
cmpb $0x0, 0x81(%rbx)
jne 0x23ef3
movq 0x350(%rbx), %rax
incl (%rax)
movq %r15, %r12
movq %r12, %rax
addq $0x48, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq %rax, %rbx
leaq 0x20(%rsp), %rdi
callq 0x5618
movq %rbx, %rdi
callq 0x5570
nop