// File: /workspace/github_c_makefile_star2_O3/samtools[P]htslib/htscodecs/htscodecs/rANS_static32x16pr_avx512.c
// Function: rans_compress_O0_32x16_avx512
unsigned char *rans_compress_O0_32x16_avx512(unsigned char *in,
                                             unsigned int in_size,
                                             unsigned char *out,
                                             unsigned int *out_size) {
    unsigned char *cp, *out_end;
    RansEncSymbol syms[256];
    RansState ransN[32] __attribute__((aligned(64)));
    uint8_t* ptr;
    uint32_t F[256+MAGIC] = {0};
    int i, j, tab_size = 0, x, z;
    // -20 for order/size/meta
    uint32_t bound = rans_compress_bound_4x16(in_size,0)-20;

    if (!out) {
        *out_size = bound;
        out = malloc(*out_size);
    }
    if (!out || bound > *out_size)
        return NULL;

    // If "out" isn't word aligned, tweak out_end/ptr to ensure it is.
    // We already added more round in bound to allow for this.
    if (((size_t)out)&1)
        bound--;
    ptr = out_end = out + bound;

    if (in_size == 0)
        goto empty;

    // Compute statistics
    if (hist8(in, in_size, F) < 0)
        return NULL;

    // Normalise so frequences sum to power of 2
    uint32_t fsum = in_size;
    uint32_t max_val = round2(fsum);
    if (max_val > TOTFREQ)
        max_val = TOTFREQ;

    if (normalise_freq(F, fsum, max_val) < 0)
        return NULL;
    fsum=max_val;

    cp = out;
    cp += encode_freq(cp, F);
    tab_size = cp-out;
    //write(2, out+4, cp-(out+4));

    if (normalise_freq(F, fsum, TOTFREQ) < 0)
        return NULL;

    // Encode statistics and build lookup tables for SIMD encoding.
    uint32_t SB[256], SA[256], SD[256], SC[256];
    for (x = j = 0; j < 256; j++) {
        if (F[j]) {
            RansEncSymbolInit(&syms[j], x, F[j], TF_SHIFT);
            SB[j] = syms[j].x_max;
            SA[j] = syms[j].rcp_freq;
            SD[j] = (syms[j].cmpl_freq<<0) | ((syms[j].rcp_shift-32)<<16);
            SC[j] = syms[j].bias;
            x += F[j];
        }
    }

    for (z = 0; z < 32; z++)
      RansEncInit(&ransN[z]);

    z = i = in_size&(32-1);
    while (z-- > 0)
      RansEncPutSymbol(&ransN[z], &ptr, &syms[in[in_size-(i-z)]]);

#define LOAD512(a,b)                                     \
    __m512i a##1 = _mm512_load_si512((__m512i *)&b[0]); \
    __m512i a##2 = _mm512_load_si512((__m512i *)&b[16]);

#define STORE512(a,b)                           \
    _mm512_store_si512((__m256i *)&b[0], a##1); \
    _mm512_store_si512((__m256i *)&b[16], a##2);

    LOAD512(Rv, ransN);

    uint16_t *ptr16 = (uint16_t *)ptr;
    for (i=(in_size &~(32-1)); i>0; i-=32) {
        uint8_t *c = &in[i-32];

        // GATHER versions
        // Much faster now we have an efficient loadu mechanism in place,
        // BUT...
        // Try this for avx2 variant too?  Better way to populate the mm256
        // regs for mix of avx2 and avx512 opcodes.
        __m256i c12 = _mm256_loadu_si256((__m256i const *)c);
        __m512i c1 = _mm512_cvtepu8_epi32(_mm256_extracti128_si256(c12,0));
        __m512i c2 = _mm512_cvtepu8_epi32(_mm256_extracti128_si256(c12,1));
#define SET512(a,b) \
        __m512i a##1 = _mm512_i32gather_epi32x(c1, b, 4); \
        __m512i a##2 = _mm512_i32gather_epi32x(c2, b, 4)

        SET512(xmax, SB);

        uint16_t gt_mask1 = _mm512_cmpgt_epi32_mask(Rv1, xmax1);
        int pc1 = _mm_popcnt_u32(gt_mask1);
        __m512i Rp1 = _mm512_and_si512(Rv1, _mm512_set1_epi32(0xffff));
        __m512i Rp2 = _mm512_and_si512(Rv2, _mm512_set1_epi32(0xffff));
        uint16_t gt_mask2 = _mm512_cmpgt_epi32_mask(Rv2, xmax2);
        SET512(SDv,  SD);
        int pc2 = _mm_popcnt_u32(gt_mask2);

        Rp1 = _mm512_maskz_compress_epi32(gt_mask1, Rp1);
        Rp2 = _mm512_maskz_compress_epi32(gt_mask2, Rp2);

        _mm512_mask_cvtepi32_storeu_epi16(ptr16-pc2, (1<<pc2)-1, Rp2);
        ptr16 -= pc2;
        _mm512_mask_cvtepi32_storeu_epi16(ptr16-pc1, (1<<pc1)-1, Rp1);
        ptr16 -= pc1;

        SET512(rfv,  SA);
        Rv1 = _mm512_mask_srli_epi32(Rv1, gt_mask1, Rv1, 16);
        Rv2 = _mm512_mask_srli_epi32(Rv2, gt_mask2, Rv2, 16);

        // interleaved form of this, helps on icc a bit
        //rfv1 = _mm512_mulhi_epu32(Rv1, rfv1);
        //rfv2 = _mm512_mulhi_epu32(Rv2, rfv2);

        // Alternatives here:
        // SHIFT right/left instead of AND: (very marginally slower)
        //   rf1_hm = _mm512_and_epi32(
        //           rf1_hm, _mm512_set1_epi64((uint64_t)0xffffffff00000000));
        // vs
        //   rf1_hm = _mm512_srli_epi64(rf1_hm, 32);
        //   rf1_hm = _mm512_slli_epi64(rf1_hm, 32);
        __m512i rf1_hm = _mm512_mul_epu32(_mm512_srli_epi64(Rv1,  32),
                                          _mm512_srli_epi64(rfv1, 32));
        __m512i rf2_hm = _mm512_mul_epu32(_mm512_srli_epi64(Rv2,  32),
                                          _mm512_srli_epi64(rfv2, 32));
        __m512i rf1_lm = _mm512_srli_epi64(_mm512_mul_epu32(Rv1, rfv1), 32);
        __m512i rf2_lm = _mm512_srli_epi64(_mm512_mul_epu32(Rv2, rfv2), 32);
        rf1_hm = _mm512_and_epi32(rf1_hm,
                                  _mm512_set1_epi64((uint64_t)0xffffffff<<32));
        rf2_hm = _mm512_and_epi32(rf2_hm,
                                  _mm512_set1_epi64((uint64_t)0xffffffff<<32));
        rfv1 = _mm512_or_epi32(rf1_lm, rf1_hm);
        rfv2 = _mm512_or_epi32(rf2_lm, rf2_hm);

        // Or a pure masked blend approach, sadly slower.
        // rfv1 = _mm512_mask_blend_epi32(0x5555,
        //            _mm512_mul_epu32(
        //                _mm512_srli_epi64(Rv1, 32),
        //                _mm512_srli_epi64(rfv1, 32)),
        //            _mm512_srli_epi64(
        //                _mm512_mul_epu32(Rv1, rfv1),
        //                32));
        // rfv2 = _mm512_mask_blend_epi32(0xaaaa,
        //            _mm512_srli_epi64(
        //                _mm512_mul_epu32(Rv2, rfv2),
        //                32),
        //            _mm512_mul_epu32(
        //                _mm512_srli_epi64(Rv2, 32),
        //                _mm512_srli_epi64(rfv2, 32)));

        SET512(biasv, SC);
        __m512i shiftv1 = _mm512_srli_epi32(SDv1, 16);
        __m512i shiftv2 = _mm512_srli_epi32(SDv2, 16);

        __m512i qv1 = _mm512_srlv_epi32(rfv1, shiftv1);
        __m512i qv2 = _mm512_srlv_epi32(rfv2, shiftv2);

        qv1 = _mm512_mullo_epi32(qv1,
                  _mm512_and_si512(SDv1,_mm512_set1_epi32(0xffff)));
        qv1 = _mm512_add_epi32(qv1, biasv1);
        Rv1 = _mm512_add_epi32(Rv1, qv1);

        qv2 = _mm512_mullo_epi32(qv2,
                  _mm512_and_si512(SDv2, _mm512_set1_epi32(0xffff)));
        qv2 = _mm512_add_epi32(qv2, biasv2);
        Rv2 = _mm512_add_epi32(Rv2, qv2);
    }
    ptr = (uint8_t *)ptr16;
    STORE512(Rv, ransN);

    for (z = 32-1; z >= 0; z--)
        RansEncFlush(&ransN[z], &ptr);

 empty:
    // Finalise block size and return it
    *out_size = (out_end - ptr) + tab_size;

    memmove(out + tab_size, ptr, out_end-ptr);

    return out;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
andq $-0x40, %rsp
subq $0x2e40, %rsp           # imm = 0x2E40
movq %rcx, %r12
movq %rdx, %r15
movl %esi, %r13d
movq %rdi, %r14
leaq 0x11a0(%rsp), %rdi
movl $0x420, %edx            # imm = 0x420
xorl %esi, %esi
callq 0x4260
movl %r13d, %edi
xorl %esi, %esi
callq 0x61e28
movl %eax, %edx
leal -0x14(%rdx), %ebx
testq %r15, %r15
je 0x6bd77
cmpl (%r12), %ebx
jbe 0x6bd9a
jmp 0x6c5e9
movl %ebx, (%r12)
movl %ebx, %edi
movq %r14, %r15
movq %rdx, %r14
callq 0x4680
movq %r14, %rdx
movq %r15, %r14
movq %rax, %r15
testq %rax, %rax
je 0x6c5e9
addl $-0x15, %edx
testb $0x1, %r15b
cmovel %ebx, %edx
addq %r15, %rdx
testl %r13d, %r13d
je 0x6beb5
movq %rdx, 0x38(%rsp)
cmpl $0x7a121, %r13d         # imm = 0x7A121
movq %r14, 0x40(%rsp)
jb 0x6bec2
movl $0x3006f, %edi          # imm = 0x3006F
movl $0x4, %esi
callq 0x7e245
xorl %ecx, %ecx
testq %rax, %rax
je 0x6c5e9
movl %r13d, %edx
andl $-0x10, %edx
je 0x6be55
movl %edx, %edx
xorl %ecx, %ecx
movzwl (%r14,%rcx), %esi
movzwl 0x2(%r14,%rcx), %edi
movzwl 0x4(%r14,%rcx), %r8d
movzwl 0x6(%r14,%rcx), %r9d
incl (%rax,%rsi,4)
incl 0x40094(%rax,%rdi,4)
incl 0x80128(%rax,%r8,4)
incl (%rax,%r9,4)
movzwl 0x8(%r14,%rcx), %esi
movzwl 0xa(%r14,%rcx), %edi
movzwl 0xc(%r14,%rcx), %r8d
movzwl 0xe(%r14,%rcx), %r9d
incl 0x40094(%rax,%rsi,4)
incl (%rax,%rdi,4)
incl 0x40094(%rax,%r8,4)
incl 0x80128(%rax,%r9,4)
addq $0x10, %rcx
cmpq %rdx, %rcx
jb 0x6bded
cmpl %r13d, %ecx
jae 0x6be73
movl %ecx, %ecx
movl %r13d, %edx
movzbl (%r14,%rcx), %esi
incq %rcx
incl 0x11a0(%rsp,%rsi,4)
cmpq %rcx, %rdx
jne 0x6be5f
xorl %ecx, %ecx
movl 0x40094(%rax,%rcx,4), %edx
addl (%rax,%rcx,4), %edx
addl 0x80128(%rax,%rcx,4), %edx
movzbl %cl, %esi
addl %edx, 0x11a0(%rsp,%rsi,4)
movl %ecx, %esi
shrl $0x8, %esi
addl %edx, 0x11a0(%rsp,%rsi,4)
incq %rcx
cmpq $0x10000, %rcx          # imm = 0x10000
jne 0x6be75
movq %rax, %rdi
callq 0x7e26a
jmp 0x6bfdb
xorl %eax, %eax
movq %r12, %rcx
movq %rdx, %r12
jmp 0x6d154
leaq 0x1e00(%rsp), %rdi
xorl %ebx, %ebx
movl $0x420, %edx            # imm = 0x420
xorl %esi, %esi
callq 0x4260
leaq 0x15c0(%rsp), %rdi
movl $0x420, %edx            # imm = 0x420
xorl %esi, %esi
callq 0x4260
leaq 0x19e0(%rsp), %rdi
movl $0x420, %edx            # imm = 0x420
xorl %esi, %esi
callq 0x4260
movl %r13d, %eax
andl $0x7fff8, %eax          # imm = 0x7FFF8
je 0x6bf7e
movl %eax, %eax
xorl %ebx, %ebx
movzbl (%r14,%rbx), %ecx
incl 0x11a0(%rsp,%rcx,4)
movzbl 0x1(%r14,%rbx), %ecx
incl 0x1e00(%rsp,%rcx,4)
movzbl 0x2(%r14,%rbx), %ecx
incl 0x15c0(%rsp,%rcx,4)
movzbl 0x3(%r14,%rbx), %ecx
incl 0x19e0(%rsp,%rcx,4)
movzbl 0x4(%r14,%rbx), %ecx
incl 0x11a0(%rsp,%rcx,4)
movzbl 0x5(%r14,%rbx), %ecx
incl 0x1e00(%rsp,%rcx,4)
movzbl 0x6(%r14,%rbx), %ecx
incl 0x15c0(%rsp,%rcx,4)
movzbl 0x7(%r14,%rbx), %ecx
incl 0x19e0(%rsp,%rcx,4)
addq $0x8, %rbx
cmpq %rax, %rbx
jb 0x6bf0e
cmpl %r13d, %ebx
jae 0x6bf9c
movl %ebx, %eax
movl %r13d, %ecx
movzbl (%r14,%rax), %edx
incq %rax
incl 0x11a0(%rsp,%rdx,4)
cmpq %rax, %rcx
jne 0x6bf88
xorl %eax, %eax
vmovdqu64 0x15c0(%rsp,%rax,4), %zmm0
vpaddd 0x1e00(%rsp,%rax,4), %zmm0, %zmm0
vpaddd 0x19e0(%rsp,%rax,4), %zmm0, %zmm0
vpaddd 0x11a0(%rsp,%rax,4), %zmm0, %zmm0
vmovdqu64 %zmm0, 0x11a0(%rsp,%rax,4)
addq $0x10, %rax
cmpq $0x100, %rax            # imm = 0x100
jne 0x6bf9e
leal -0x1(%r13), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %r9d
shrl $0x10, %r9d
orl %eax, %r9d
incl %r9d
movl $0x1000, %r8d           # imm = 0x1000
cmpl %r8d, %r9d
cmovbl %r9d, %r8d
movq %r8, %rcx
shlq $0x1f, %rcx
movb $0x1, %dil
movl $0x1, %r10d
movl %r13d, %esi
movslq %esi, %rbx
xorl %r11d, %r11d
movq %rcx, %rax
xorl %edx, %edx
divq %rbx
movq %rax, %rsi
movl $0x40000000, %eax       # imm = 0x40000000
xorl %edx, %edx
idivl %ebx
movslq %eax, %rdx
addq %rsi, %rdx
xorl %esi, %esi
xorl %ebx, %ebx
xorl %eax, %eax
movl 0x11a0(%rsp,%r11,4), %r14d
testq %r14, %r14
je 0x6c083
cmpl %r14d, %ebx
cmovbl %r11d, %eax
cmovbel %r14d, %ebx
imulq %rdx, %r14
shrq $0x1f, %r14
cmpl $0x2, %r14d
cmovbl %r10d, %r14d
movl %r14d, 0x11a0(%rsp,%r11,4)
addl %esi, %r14d
movl %r14d, %esi
incq %r11
cmpq $0x100, %r11            # imm = 0x100
jne 0x6c04d
movl %r8d, %edx
subl %esi, %edx
cltq
testl %edx, %edx
jg 0x6c127
jns 0x6c13a
movl 0x11a0(%rsp,%rax,4), %r11d
movl %edx, %ebx
negl %ebx
cmpl %ebx, %r11d
jbe 0x6c0c6
movl %r11d, %r14d
shrl %r14d
cmpl %ebx, %r14d
setb %bl
testb %bl, %dil
je 0x6c12f
testb $0x1, %dil
movl $0x0, %edi
jne 0x6c027
addl %r11d, %edx
movl $0x1, 0x11a0(%rsp,%rax,4)
decl %edx
je 0x6c13a
xorl %ecx, %ecx
movl 0x11a0(%rsp,%rcx,4), %esi
cmpl $0x2, %esi
jb 0x6c115
movl %edx, %edi
negl %edi
movl $0x1, %r10d
subl %esi, %r10d
cmpl %edi, %esi
cmoval %edx, %r10d
addl %r10d, %esi
movl %esi, 0x11a0(%rsp,%rcx,4)
subl %r10d, %edx
cmpq $0xfe, %rcx
ja 0x6c13a
incq %rcx
testl %edx, %edx
jne 0x6c0e9
jmp 0x6c13a
movl 0x11a0(%rsp,%rax,4), %r11d
addl %edx, %r11d
movl %r11d, 0x11a0(%rsp,%rax,4)
xorl %edx, %edx
cmpl $0x0, 0x11a0(%rsp,%rax,4)
je 0x6c5e9
movl $0x1, %eax
xorl %ecx, %ecx
movq %r15, %rdi
movq 0x40(%rsp), %r14
movq %rdi, %rsi
cmpl $0x0, 0x11a0(%rsp,%rcx,4)
je 0x6c16c
testl %edx, %edx
je 0x6c180
decl %edx
movq %rsi, %rdi
incq %rcx
incq %rax
cmpq $0x100, %rcx            # imm = 0x100
jne 0x6c159
jmp 0x6c1ce
leaq 0x1(%rsi), %rdi
movb %cl, (%rsi)
xorl %edx, %edx
testq %rcx, %rcx
je 0x6c16f
cmpl $0x0, 0x119c(%rsp,%rcx,4)
je 0x6c16f
leal 0x1(%rcx), %edi
movl %edi, %edx
cmpq $0xfe, %rcx
ja 0x6c1c3
movq %rax, %rdx
cmpl $0x0, 0x11a0(%rsp,%rdx,4)
je 0x6c1c3
incq %rdx
cmpq $0x100, %rdx            # imm = 0x100
jne 0x6c1a8
movl $0x100, %edx            # imm = 0x100
subl %edi, %edx
movb %dl, 0x1(%rsi)
addq $0x2, %rsi
jmp 0x6c16c
movb $0x0, (%rdi)
subl %r15d, %edi
incl %edi
movslq %edi, %rdi
addq %r15, %rdi
xorl %eax, %eax
vpmovsxbd 0x33da1(%rip), %xmm0 # 0x9ff88
vmovd 0x2fd61(%rip), %xmm1    # 0x9bf50
vpbroadcastb 0x33ec8(%rip), %xmm2 # 0xa00c0
movl 0x11a0(%rsp,%rax,4), %ecx
testl %ecx, %ecx
je 0x6c2c2
cmpl $0x7f, %ecx
ja 0x6c218
movb %cl, (%rdi)
movl $0x1, %ecx
jmp 0x6c2bf
cmpl $0x3fff, %ecx           # imm = 0x3FFF
ja 0x6c23a
movl %ecx, %edx
shrl $0x7, %edx
orb $-0x80, %dl
movb %dl, (%rdi)
andb $0x7f, %cl
movb %cl, 0x1(%rdi)
movl $0x2, %ecx
jmp 0x6c2bf
cmpl $0x1fffff, %ecx         # imm = 0x1FFFFF
ja 0x6c264
movl %ecx, %edx
shrl $0xe, %edx
orb $-0x80, %dl
movb %dl, (%rdi)
movl %ecx, %edx
shrl $0x7, %edx
orb $-0x80, %dl
movb %dl, 0x1(%rdi)
andb $0x7f, %cl
movb %cl, 0x2(%rdi)
movl $0x3, %ecx
jmp 0x6c2bf
cmpl $0xfffffff, %ecx        # imm = 0xFFFFFFF
ja 0x6c299
movl %ecx, %edx
shrl $0x15, %edx
orb $-0x80, %dl
movb %dl, (%rdi)
movl %ecx, %edx
shrl $0xe, %edx
orb $-0x80, %dl
movb %dl, 0x1(%rdi)
movl %ecx, %edx
shrl $0x7, %edx
orb $-0x80, %dl
movb %dl, 0x2(%rdi)
andb $0x7f, %cl
movb %cl, 0x3(%rdi)
movl $0x4, %ecx
jmp 0x6c2bf
vmovd %ecx, %xmm3
vpbroadcastd %xmm3, %xmm3
vpsrlvd %xmm0, %xmm3, %xmm3
vpshufb %xmm1, %xmm3, %xmm3
vpor %xmm2, %xmm3, %xmm3
vmovd %xmm3, (%rdi)
andb $0x7f, %cl
movb %cl, 0x4(%rdi)
movl $0x5, %ecx
addq %rcx, %rdi
incq %rax
cmpq $0x100, %rax            # imm = 0x100
jne 0x6c1f8
testl %r9d, %r9d
je 0x6c428
movq %rdi, %rbx
movb $0x1, %dil
movabsq $0x80000000000, %rcx    # imm = 0x80000000000
movl $0x1, %r9d
movslq %r8d, %r8
xorl %r10d, %r10d
movq %rcx, %rax
xorl %edx, %edx
divq %r8
movq %rax, %rsi
movl $0x40000000, %eax       # imm = 0x40000000
xorl %edx, %edx
idivl %r8d
movslq %eax, %rdx
addq %rsi, %rdx
xorl %r8d, %r8d
xorl %esi, %esi
xorl %eax, %eax
movl 0x11a0(%rsp,%r10,4), %r11d
testq %r11, %r11
je 0x6c34e
cmpl %r11d, %esi
cmovbl %r10d, %eax
cmovbel %r11d, %esi
imulq %rdx, %r11
shrq $0x1f, %r11
cmpl $0x2, %r11d
cmovbl %r9d, %r11d
movl %r11d, 0x11a0(%rsp,%r10,4)
addl %r8d, %r11d
movl %r11d, %r8d
incq %r10
cmpq $0x100, %r10            # imm = 0x100
jne 0x6c318
leal -0x1000(%r8), %r10d
movl $0x1000, %esi           # imm = 0x1000
subl %r8d, %esi
cltq
testl %esi, %esi
jg 0x6c407
jns 0x6c402
movl 0x11a0(%rsp,%rax,4), %edx
cmpl %r10d, %edx
jbe 0x6c397
movl %edx, %r11d
shrl %r11d
cmpl %r10d, %r11d
setb %r10b
testb %r10b, %dil
je 0x6c40e
testb $0x1, %dil
movl $0x0, %edi
jne 0x6c2f0
subl %r8d, %edx
movl $0x1, 0x11a0(%rsp,%rax,4)
addl $0xfff, %edx            # imm = 0xFFF
je 0x6c402
xorl %ecx, %ecx
movq %rbx, %rdi
movl 0x11a0(%rsp,%rcx,4), %esi
cmpl $0x2, %esi
jb 0x6c3f0
movl %edx, %edi
negl %edi
movl $0x1, %r8d
subl %esi, %r8d
cmpl %edi, %esi
movq %rbx, %rdi
cmoval %edx, %r8d
addl %r8d, %esi
movl %esi, 0x11a0(%rsp,%rcx,4)
subl %r8d, %edx
cmpq $0xfe, %rcx
ja 0x6c41a
incq %rcx
testl %edx, %edx
jne 0x6c3c1
jmp 0x6c41a
movq %rbx, %rdi
jmp 0x6c41a
movl 0x11a0(%rsp,%rax,4), %edx
movq %rbx, %rdi
addl %esi, %edx
movl %edx, 0x11a0(%rsp,%rax,4)
cmpl $0x0, 0x11a0(%rsp,%rax,4)
je 0x6c5e9
subl %r15d, %edi
movq %rdi, 0xd8(%rsp)
xorl %edi, %edi
xorl %r8d, %r8d
movl 0x11a0(%rsp,%rdi,4), %r9d
testq %r9, %r9
je 0x6c521
cmpl $0x1001, %r8d           # imm = 0x1001
jae 0x6d182
movl $0x1000, %eax           # imm = 0x1000
subl %r8d, %eax
cmpl %r9d, %eax
jb 0x6d1a4
movq %rdi, %rax
shlq $0x4, %rax
leaq (%rsp,%rax), %r11
addq $0x1e00, %r11           # imm = 0x1E00
movl $0x1000, %r10d          # imm = 0x1000
subl %r9d, %r10d
movl %r9d, %ebx
shll $0x13, %ebx
decl %ebx
movl %ebx, (%r11)
movw %r10w, 0xc(%r11)
cmpq $0x1, %r9
jne 0x6c4b6
movl $0xffffffff, 0x4(%r11)  # imm = 0xFFFFFFFF
leal 0xfff(%r8), %ecx
movl %ecx, 0x8(%r11)
movw $0x20, %si
movl $0xffffffff, %eax       # imm = 0xFFFFFFFF
jmp 0x6c4ec
movl $0x1e, %esi
leal -0x1e(%rsi), %ecx
movl $0x1, %eax
shll %cl, %eax
incl %esi
cmpl %r9d, %eax
jb 0x6c4bb
movl $0x1, %eax
movl %esi, %ecx
shlq %cl, %rax
addq %r9, %rax
decq %rax
xorl %edx, %edx
divq %r9
movl %eax, 0x4(%r11)
movl %r8d, 0x8(%r11)
movl %r8d, %ecx
movw %si, 0xe(%r11)
movl %ebx, 0xda0(%rsp,%rdi,4)
movl %eax, 0x9a0(%rsp,%rdi,4)
movzwl %r10w, %eax
shll $0x10, %esi
addl %esi, %eax
addl $0xffe00000, %eax       # imm = 0xFFE00000
movl %eax, 0x5a0(%rsp,%rdi,4)
movl %ecx, 0x1a0(%rsp,%rdi,4)
addl %r8d, %r9d
movl %r9d, %r8d
incq %rdi
cmpq $0x100, %rdi            # imm = 0x100
jne 0x6c438
vpbroadcastd 0x33a45(%rip), %zmm0 # 0x9ff80
vmovdqa64 %zmm0, 0x15c0(%rsp)
vmovdqa64 %zmm0, 0x1600(%rsp)
testb $0x1f, %r13b
movq %r12, 0xc8(%rsp)
je 0x6c5f1
movl %r13d, %eax
andl $-0x20, %eax
andl $0x1f, %r13d
decq %r13
movq 0x38(%rsp), %r12
leal (%rax,%r13), %ecx
movzbl (%r14,%rcx), %edx
shll $0x4, %edx
movl 0x15c0(%rsp,%r13,4), %edi
xorl %ecx, %ecx
cmpl 0x1e00(%rsp,%rdx), %edi
seta %cl
leal (%rcx,%rcx), %r8d
movw %di, -0x2(%r12)
shll $0x4, %ecx
shrl %cl, %edi
movl 0x1e04(%rsp,%rdx), %r9d
imulq %rdi, %r9
movb 0x1e0e(%rsp,%rdx), %cl
shrq %cl, %r9
subq %r8, %r12
addl 0x1e08(%rsp,%rdx), %edi
movzwl 0x1e0c(%rsp,%rdx), %ecx
imull %r9d, %ecx
addl %edi, %ecx
movl %ecx, 0x15c0(%rsp,%r13,4)
leaq -0x1(%r13), %rcx
incq %r13
cmpq $0x1, %r13
movq %rcx, %r13
ja 0x6c56f
movl %eax, %r13d
jmp 0x6c5f6
xorl %r15d, %r15d
jmp 0x6d16d
movq 0x38(%rsp), %r12
movq %r15, 0xd0(%rsp)
vmovdqa64 0x15c0(%rsp), %zmm18
vmovdqa64 0x1600(%rsp), %zmm17
testl %r13d, %r13d
jle 0x6d10c
movl %r13d, %ecx
addq $0x20, %rcx
vpbroadcastd 0x33dd8(%rip), %zmm16 # 0xa0400
movw $0xaaaa, %ax            # imm = 0xAAAA
kmovw %eax, %k1
movq %rcx, 0x148(%rsp)
vpmovzxbd -0x40(%r14,%rcx), %zmm4
vpmovzxbd -0x30(%r14,%rcx), %zmm3
vpextrd $0x1, %xmm4, %edx
vpextrd $0x2, %xmm4, %ecx
vmovd %xmm4, %edi
vpextrd $0x3, %xmm4, %eax
shll $0x2, %edi
movq %rdi, %r10
movq %rdi, 0xc0(%rsp)
vextracti128 $0x1, %ymm4, %xmm0
vpextrd $0x1, %xmm0, %ebx
shll $0x2, %edx
movq %rdx, %rsi
movq %rdx, 0xa0(%rsp)
shll $0x2, %ecx
movq %rcx, %r13
vpextrd $0x2, %xmm0, %edx
shll $0x2, %eax
movq %rax, 0x78(%rsp)
vmovd %xmm0, %eax
vpextrd $0x3, %xmm0, %ecx
shll $0x2, %eax
movq %rax, %r14
movq %rax, 0xa8(%rsp)
shll $0x2, %ebx
vextracti32x4 $0x2, %zmm4, %xmm0
vmovd %xmm0, %eax
shll $0x2, %edx
movq %rdx, 0x70(%rsp)
shll $0x2, %eax
movq %rax, %rdi
movq %rax, 0xb8(%rsp)
vpextrd $0x1, %xmm0, %eax
shll $0x2, %ecx
movq %rcx, 0x58(%rsp)
shll $0x2, %eax
movq %rax, %r15
movq %rax, 0xb0(%rsp)
vpextrd $0x2, %xmm0, %eax
shll $0x2, %eax
movq %rax, %r9
vpextrd $0x3, %xmm0, %eax
vextracti32x4 $0x3, %zmm4, %xmm0
shll $0x2, %eax
movq %rax, 0x50(%rsp)
vmovd %xmm0, %eax
shll $0x2, %eax
movq %rax, %r8
movq %rax, 0x98(%rsp)
vpextrd $0x1, %xmm0, %edx
shll $0x2, %edx
movq %rdx, 0x68(%rsp)
vpextrd $0x2, %xmm0, %eax
shll $0x2, %eax
movq %rax, %r11
vpextrd $0x3, %xmm0, %eax
shll $0x2, %eax
movq %rax, 0x48(%rsp)
vmovd 0xda0(%rsp,%r8), %xmm1
vmovd 0xda0(%rsp,%rdi), %xmm0
vmovd 0xda0(%rsp,%r10), %xmm2
vpinsrd $0x1, 0xda0(%rsp,%rsi), %xmm2, %xmm6
vmovd 0xda0(%rsp,%r14), %xmm9
vmovd %xmm3, %eax
vpextrd $0x1, %xmm3, %esi
shll $0x2, %eax
movq %rax, 0x100(%rsp)
shll $0x2, %esi
movq %rsi, 0x60(%rsp)
vpinsrd $0x1, 0xda0(%rsp,%rdx), %xmm1, %xmm7
vpextrd $0x2, %xmm3, %esi
vpextrd $0x3, %xmm3, %ecx
shll $0x2, %esi
movq %rsi, %r10
movq %rsi, 0x88(%rsp)
shll $0x2, %ecx
movq %rcx, %rsi
vpinsrd $0x1, 0xda0(%rsp,%r15), %xmm0, %xmm8
vextracti128 $0x1, %ymm3, %xmm4
vmovd %xmm4, %ecx
vpextrd $0x1, %xmm4, %edx
shll $0x2, %ecx
movq %rcx, 0xf8(%rsp)
shll $0x2, %edx
movq %rdx, 0xf0(%rsp)
vextracti32x4 $0x2, %zmm3, %xmm5
vmovd %xmm5, %edi
shll $0x2, %edi
movq %rdi, 0x80(%rsp)
vextracti32x4 $0x3, %zmm3, %xmm3
movq %rbx, 0x120(%rsp)
vpinsrd $0x1, 0xda0(%rsp,%rbx), %xmm9, %xmm1
vmovd %xmm3, %r15d
shll $0x2, %r15d
vpextrd $0x1, %xmm3, %r14d
shll $0x2, %r14d
vmovd 0xda0(%rsp,%r15), %xmm0
movq %r15, 0x110(%rsp)
movq %r13, 0x130(%rsp)
vpinsrd $0x2, 0xda0(%rsp,%r13), %xmm6, %xmm2
vpinsrd $0x1, 0xda0(%rsp,%r14), %xmm0, %xmm9
movq %r14, 0x108(%rsp)
vpextrd $0x1, %xmm5, %r8d
shll $0x2, %r8d
movq %r8, 0xe8(%rsp)
vmovd 0xda0(%rsp,%rdi), %xmm0
movq %r11, 0x140(%rsp)
vpinsrd $0x2, 0xda0(%rsp,%r11), %xmm7, %xmm6
vpinsrd $0x1, 0xda0(%rsp,%r8), %xmm0, %xmm7
vpextrd $0x2, %xmm4, %edi
shll $0x2, %edi
movq %rdi, 0x90(%rsp)
vmovd 0xda0(%rsp,%rcx), %xmm10
movq %r9, 0x138(%rsp)
vpinsrd $0x2, 0xda0(%rsp,%r9), %xmm8, %xmm0
vpinsrd $0x1, 0xda0(%rsp,%rdx), %xmm10, %xmm8
vpextrd $0x2, %xmm3, %r8d
shll $0x2, %r8d
vmovd 0xda0(%rsp,%rax), %xmm10
movq 0x70(%rsp), %rdx
vpinsrd $0x2, 0xda0(%rsp,%rdx), %xmm1, %xmm1
movq 0x60(%rsp), %rax
vpinsrd $0x1, 0xda0(%rsp,%rax), %xmm10, %xmm10
vpinsrd $0x2, 0xda0(%rsp,%r8), %xmm9, %xmm13
movq %r8, 0x128(%rsp)
vpinsrd $0x2, 0xda0(%rsp,%r10), %xmm10, %xmm9
vpextrd $0x2, %xmm5, %ecx
shll $0x2, %ecx
movq %rcx, %rax
movq %rcx, 0xe0(%rsp)
movq 0x98(%rsp), %rcx
vmovd 0x5a0(%rsp,%rcx), %xmm10
vpinsrd $0x2, 0xda0(%rsp,%rax), %xmm7, %xmm14
movq 0x68(%rsp), %rax
vpinsrd $0x1, 0x5a0(%rsp,%rax), %xmm10, %xmm7
vpinsrd $0x2, 0xda0(%rsp,%rdi), %xmm8, %xmm15
vpinsrd $0x2, 0x5a0(%rsp,%r11), %xmm7, %xmm7
vpextrd $0x3, %xmm4, %edi
shll $0x2, %edi
movq 0xb8(%rsp), %rax
vmovd 0x5a0(%rsp,%rax), %xmm4
movq 0x78(%rsp), %rcx
vpinsrd $0x3, 0xda0(%rsp,%rcx), %xmm2, %xmm10
movq 0xb0(%rsp), %rax
vpinsrd $0x1, 0x5a0(%rsp,%rax), %xmm4, %xmm2
vpinsrd $0x3, 0xda0(%rsp,%rsi), %xmm9, %xmm4
movq %rsi, %r10
vpinsrd $0x2, 0x5a0(%rsp,%r9), %xmm2, %xmm9
vpextrd $0x3, %xmm5, %r9d
shll $0x2, %r9d
movq 0xa8(%rsp), %rax
vmovd 0x5a0(%rsp,%rax), %xmm2
movq 0x48(%rsp), %rsi
vpinsrd $0x3, 0xda0(%rsp,%rsi), %xmm6, %xmm6
vpinsrd $0x1, 0x5a0(%rsp,%rbx), %xmm2, %xmm2
movq 0x50(%rsp), %rax
vpinsrd $0x3, 0xda0(%rsp,%rax), %xmm0, %xmm11
vpinsrd $0x2, 0x5a0(%rsp,%rdx), %xmm2, %xmm8
vpextrd $0x3, %xmm3, %ebx
shll $0x2, %ebx
movq 0xc0(%rsp), %rdx
vmovd 0x5a0(%rsp,%rdx), %xmm0
movq 0x58(%rsp), %rdx
vpinsrd $0x3, 0xda0(%rsp,%rdx), %xmm1, %xmm12
movq 0xa0(%rsp), %r11
vpinsrd $0x1, 0x5a0(%rsp,%r11), %xmm0, %xmm0
vpinsrd $0x3, 0xda0(%rsp,%rbx), %xmm13, %xmm1
vpinsrd $0x2, 0x5a0(%rsp,%r13), %xmm0, %xmm0
vpinsrd $0x3, 0xda0(%rsp,%r9), %xmm14, %xmm2
vpinsrd $0x3, 0x5a0(%rsp,%rcx), %xmm0, %xmm0
vmovdqa %ymm0, 0x180(%rsp)
movq %rdi, 0x118(%rsp)
vpinsrd $0x3, 0xda0(%rsp,%rdi), %xmm15, %xmm0
vmovd 0x5a0(%rsp,%r15), %xmm3
vpinsrd $0x1, 0x5a0(%rsp,%r14), %xmm3, %xmm3
vinserti128 $0x1, %xmm1, %ymm2, %ymm1
vinserti128 $0x1, %xmm0, %ymm4, %ymm0
vpinsrd $0x2, 0x5a0(%rsp,%r8), %xmm3, %xmm13
vinserti64x4 $0x1, %ymm1, %zmm0, %zmm0
vpcmpgtd %zmm0, %zmm17, %k2
kmovw %k2, %ecx
popcntl %ecx, %ecx
leal (%rcx,%rcx), %r13d
subq %r13, %r12
movq 0x80(%rsp), %r8
vmovd 0x5a0(%rsp,%r8), %xmm0
vpinsrd $0x3, 0x5a0(%rsp,%rsi), %xmm7, %xmm1
vmovdqa %xmm1, 0x170(%rsp)
movq 0xe8(%rsp), %r15
vpinsrd $0x1, 0x5a0(%rsp,%r15), %xmm0, %xmm0
vpinsrd $0x3, 0x5a0(%rsp,%rax), %xmm9, %xmm4
movq 0xe0(%rsp), %r14
vpinsrd $0x2, 0x5a0(%rsp,%r14), %xmm0, %xmm0
movl $0xffffffff, %r13d      # imm = 0xFFFFFFFF
shll %cl, %r13d
notl %r13d
kmovw %r13d, %k4
movq 0xf8(%rsp), %rsi
vmovd 0x5a0(%rsp,%rsi), %xmm1
vpinsrd $0x3, 0x5a0(%rsp,%rdx), %xmm8, %xmm9
movq 0xf0(%rsp), %rdx
vpinsrd $0x1, 0x5a0(%rsp,%rdx), %xmm1, %xmm1
vpinsrd $0x3, 0x5a0(%rsp,%rbx), %xmm13, %xmm2
vmovdqa %xmm2, 0x150(%rsp)
movq 0x90(%rsp), %rax
vpinsrd $0x2, 0x5a0(%rsp,%rax), %xmm1, %xmm1
vpinsrd $0x3, 0x5a0(%rsp,%r9), %xmm0, %xmm8
vinserti128 $0x1, %xmm6, %ymm11, %ymm0
vpinsrd $0x3, 0x5a0(%rsp,%rdi), %xmm1, %xmm1
vmovdqa %xmm1, 0x160(%rsp)
vinserti128 $0x1, %xmm12, %ymm10, %ymm1
movq 0x100(%rsp), %r8
vmovd 0x5a0(%rsp,%r8), %xmm2
movq 0x60(%rsp), %r11
vpinsrd $0x1, 0x5a0(%rsp,%r11), %xmm2, %xmm2
vinserti64x4 $0x1, %ymm0, %zmm1, %zmm0
vpcmpgtd %zmm0, %zmm18, %k3
movq 0x88(%rsp), %rax
vpinsrd $0x2, 0x5a0(%rsp,%rax), %xmm2, %xmm0
kmovw %k3, %ecx
popcntl %ecx, %ecx
vpinsrd $0x3, 0x5a0(%rsp,%r10), %xmm0, %xmm10
movl $0xffffffff, %r13d      # imm = 0xFFFFFFFF
shll %cl, %r13d
vpandq %zmm16, %zmm17, %zmm0
vpcompressd %zmm0, %zmm0 {%k2} {z}
vpmovdw %zmm0, (%r12) {%k4}
addl %ecx, %ecx
subq %rcx, %r12
movq 0x148(%rsp), %rcx
notl %r13d
kmovw %r13d, %k4
vpandq %zmm16, %zmm18, %zmm0
vpcompressd %zmm0, %zmm0 {%k3} {z}
vpmovdw %zmm0, (%r12) {%k4}
movq 0x98(%rsp), %rax
vmovd 0x9a0(%rsp,%rax), %xmm11
vmovd 0x1a0(%rsp,%rax), %xmm0
movq 0x68(%rsp), %rax
vpinsrd $0x1, 0x9a0(%rsp,%rax), %xmm11, %xmm11
vpinsrd $0x1, 0x1a0(%rsp,%rax), %xmm0, %xmm12
movq 0xb8(%rsp), %rax
vmovd 0x9a0(%rsp,%rax), %xmm0
vmovd 0x1a0(%rsp,%rax), %xmm1
movq 0xb0(%rsp), %rax
vpinsrd $0x1, 0x9a0(%rsp,%rax), %xmm0, %xmm13
vpinsrd $0x1, 0x1a0(%rsp,%rax), %xmm1, %xmm14
movq 0xa8(%rsp), %rax
vmovd 0x9a0(%rsp,%rax), %xmm0
vmovd 0x1a0(%rsp,%rax), %xmm1
movq 0x120(%rsp), %rax
vpinsrd $0x1, 0x9a0(%rsp,%rax), %xmm0, %xmm15
vpinsrd $0x1, 0x1a0(%rsp,%rax), %xmm1, %xmm7
movq 0xc0(%rsp), %rax
vmovd 0x9a0(%rsp,%rax), %xmm0
vmovd 0x1a0(%rsp,%rax), %xmm1
movq 0xa0(%rsp), %rax
vpinsrd $0x1, 0x9a0(%rsp,%rax), %xmm0, %xmm5
vpinsrd $0x1, 0x1a0(%rsp,%rax), %xmm1, %xmm3
movq 0x110(%rsp), %rax
vmovd 0x9a0(%rsp,%rax), %xmm0
movq 0x108(%rsp), %rdi
vpinsrd $0x1, 0x9a0(%rsp,%rdi), %xmm0, %xmm2
vmovd 0x1a0(%rsp,%rax), %xmm0
vpinsrd $0x1, 0x1a0(%rsp,%rdi), %xmm0, %xmm1
vinserti128 $0x1, 0x170(%rsp), %ymm4, %ymm0
movq 0x80(%rsp), %rax
vmovd 0x9a0(%rsp,%rax), %xmm4
vpinsrd $0x1, 0x9a0(%rsp,%r15), %xmm4, %xmm4
vmovdqa 0x180(%rsp), %ymm6
vinserti128 $0x1, %xmm9, %ymm6, %ymm9
vmovd 0x1a0(%rsp,%rax), %xmm6
vpinsrd $0x1, 0x1a0(%rsp,%r15), %xmm6, %xmm6
vinserti64x4 $0x1, %ymm0, %zmm9, %zmm19
vmovd 0x9a0(%rsp,%rsi), %xmm0
vpinsrd $0x1, 0x9a0(%rsp,%rdx), %xmm0, %xmm9
vinserti128 $0x1, 0x150(%rsp), %ymm8, %ymm0
vmovd 0x1a0(%rsp,%rsi), %xmm8
vpinsrd $0x1, 0x1a0(%rsp,%rdx), %xmm8, %xmm8
vinserti128 $0x1, 0x160(%rsp), %ymm10, %ymm10
vinserti64x4 $0x1, %ymm0, %zmm10, %zmm20
vmovd 0x9a0(%rsp,%r8), %xmm10
vmovd 0x1a0(%rsp,%r8), %xmm0
vpinsrd $0x1, 0x9a0(%rsp,%r11), %xmm10, %xmm10
vpinsrd $0x1, 0x1a0(%rsp,%r11), %xmm0, %xmm0
movq 0x140(%rsp), %rax
vpinsrd $0x2, 0x9a0(%rsp,%rax), %xmm11, %xmm11
vpinsrd $0x2, 0x1a0(%rsp,%rax), %xmm12, %xmm12
movq 0x138(%rsp), %rax
vpinsrd $0x2, 0x9a0(%rsp,%rax), %xmm13, %xmm13
vpinsrd $0x2, 0x1a0(%rsp,%rax), %xmm14, %xmm14
movq 0x70(%rsp), %rdi
vpinsrd $0x2, 0x9a0(%rsp,%rdi), %xmm15, %xmm15
vpinsrd $0x2, 0x1a0(%rsp,%rdi), %xmm7, %xmm7
movq 0x130(%rsp), %rdi
vpinsrd $0x2, 0x9a0(%rsp,%rdi), %xmm5, %xmm5
vpinsrd $0x2, 0x1a0(%rsp,%rdi), %xmm3, %xmm3
movq 0x128(%rsp), %rax
vpinsrd $0x2, 0x9a0(%rsp,%rax), %xmm2, %xmm2
vpinsrd $0x2, 0x1a0(%rsp,%rax), %xmm1, %xmm1
vpinsrd $0x2, 0x9a0(%rsp,%r14), %xmm4, %xmm4
vpinsrd $0x2, 0x1a0(%rsp,%r14), %xmm6, %xmm6
movq 0x90(%rsp), %rax
vpinsrd $0x2, 0x9a0(%rsp,%rax), %xmm9, %xmm9
vpinsrd $0x2, 0x1a0(%rsp,%rax), %xmm8, %xmm8
movq 0x40(%rsp), %r14
movq 0x88(%rsp), %rax
vpinsrd $0x2, 0x9a0(%rsp,%rax), %xmm10, %xmm10
vpinsrd $0x2, 0x1a0(%rsp,%rax), %xmm0, %xmm0
movq 0x48(%rsp), %rax
vpinsrd $0x3, 0x9a0(%rsp,%rax), %xmm11, %xmm11
vpinsrd $0x3, 0x1a0(%rsp,%rax), %xmm12, %xmm12
movq 0x50(%rsp), %rax
vpinsrd $0x3, 0x9a0(%rsp,%rax), %xmm13, %xmm13
vpinsrd $0x3, 0x1a0(%rsp,%rax), %xmm14, %xmm14
movq 0x58(%rsp), %rdi
vpinsrd $0x3, 0x9a0(%rsp,%rdi), %xmm15, %xmm15
vpinsrd $0x3, 0x1a0(%rsp,%rdi), %xmm7, %xmm7
movq 0x78(%rsp), %rdi
vpinsrd $0x3, 0x9a0(%rsp,%rdi), %xmm5, %xmm5
vpinsrd $0x3, 0x1a0(%rsp,%rdi), %xmm3, %xmm3
vpinsrd $0x3, 0x9a0(%rsp,%rbx), %xmm2, %xmm2
vpinsrd $0x3, 0x1a0(%rsp,%rbx), %xmm1, %xmm1
vpinsrd $0x3, 0x9a0(%rsp,%r9), %xmm4, %xmm4
vpinsrd $0x3, 0x1a0(%rsp,%r9), %xmm6, %xmm6
movq 0x118(%rsp), %rax
vpinsrd $0x3, 0x9a0(%rsp,%rax), %xmm9, %xmm9
vpinsrd $0x3, 0x1a0(%rsp,%rax), %xmm8, %xmm8
vpinsrd $0x3, 0x9a0(%rsp,%r10), %xmm10, %xmm10
vpinsrd $0x3, 0x1a0(%rsp,%r10), %xmm0, %xmm0
vinserti128 $0x1, %xmm11, %ymm13, %ymm11
vinserti128 $0x1, %xmm15, %ymm5, %ymm5
vinserti128 $0x1, %xmm2, %ymm4, %ymm2
vinserti64x4 $0x1, %ymm11, %zmm5, %zmm4
vinserti128 $0x1, %xmm9, %ymm10, %ymm5
vinserti128 $0x1, %xmm12, %ymm14, %ymm9
vinserti128 $0x1, %xmm7, %ymm3, %ymm3
vinserti64x4 $0x1, %ymm2, %zmm5, %zmm2
vpsrld $0x10, %zmm18, %zmm18 {%k3}
vpsrld $0x10, %zmm17, %zmm17 {%k2}
vpsrlq $0x20, %zmm18, %zmm5
vinserti64x4 $0x1, %ymm9, %zmm3, %zmm3
vpsrlq $0x20, %zmm4, %zmm7
vpsrlq $0x20, %zmm17, %zmm9
vpsrlq $0x20, %zmm2, %zmm10
vpmuludq %zmm5, %zmm7, %zmm5
vpmuludq %zmm9, %zmm10, %zmm7
vpmuludq %zmm18, %zmm4, %zmm4
vpsrlq $0x20, %zmm4, %zmm4
vpord %zmm5, %zmm4, %zmm4 {%k1}
vinserti128 $0x1, %xmm1, %ymm6, %ymm1
vpmuludq %zmm17, %zmm2, %zmm2
vpsrlq $0x20, %zmm2, %zmm2
vpord %zmm7, %zmm2, %zmm2 {%k1}
vinserti128 $0x1, %xmm8, %ymm0, %ymm0
vinserti64x4 $0x1, %ymm1, %zmm0, %zmm0
vpsrld $0x10, %zmm19, %zmm1
vpsrlvd %zmm1, %zmm4, %zmm1
vpsrld $0x10, %zmm20, %zmm4
vpsrlvd %zmm4, %zmm2, %zmm2
vpandq %zmm16, %zmm19, %zmm4
vpmulld %zmm4, %zmm1, %zmm1
vpaddd %zmm3, %zmm18, %zmm3
vpandq %zmm16, %zmm20, %zmm4
vpmulld %zmm4, %zmm2, %zmm2
vpaddd %zmm1, %zmm3, %zmm18
vpaddd %zmm0, %zmm17, %zmm0
vpaddd %zmm0, %zmm2, %zmm17
addq $-0x20, %rcx
cmpq $0x20, %rcx
ja 0x6c630
vmovdqa64 %zmm18, 0x15c0(%rsp)
vmovdqa64 %zmm17, 0x1600(%rsp)
xorl %eax, %eax
movl 0x163c(%rsp,%rax), %ecx
movl %ecx, -0x4(%r12,%rax)
addq $-0x4, %rax
cmpq $-0x80, %rax
jne 0x6d11e
addq %rax, %r12
movq 0xd0(%rsp), %r15
movq 0xc8(%rsp), %rcx
movq 0x38(%rsp), %rdx
movq 0xd8(%rsp), %rax
subq %r12, %rdx
movslq %eax, %rdi
leal (%rdi,%rdx), %eax
movl %eax, (%rcx)
addq %r15, %rdi
movq %r12, %rsi
vzeroupper
callq 0x4830
movq %r15, %rax
leaq -0x28(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
vzeroupper
retq
leaq 0x2ed2d(%rip), %rdi     # 0x9beb6
leaq 0x2ecc0(%rip), %rsi     # 0x9be50
leaq 0x2ecd9(%rip), %rcx     # 0x9be70
movl $0xcc, %edx
vzeroupper
callq 0x42f0
leaq 0x2ed27(%rip), %rdi     # 0x9bed2
leaq 0x2ec9e(%rip), %rsi     # 0x9be50
leaq 0x2ecb7(%rip), %rcx     # 0x9be70
movl $0xcd, %edx
vzeroupper
callq 0x42f0