// File: /workspace/github_c_makefile_star2_O2/Nico01[P]obj2asm/odisasm.c
// Function: mod_reg
int mod_reg( byte, text, class )
    uchar   byte;
    char            *text;
    int             class;
{
    char            *opcode;
    int             dir;
    int             size;
    int             reg_size;
    int             size_needed;
    int             type;
    int             method;
    int             group;
    dword   mod_reg;
    uchar   mod;
    uchar   r_m;
    uchar   reg;
    int             additional;
    char            mem_text[50];
    char            reg_text[50];
    char            third_text[50];
    char            operands[80];
    int             ref_mode;

    if ( get_checkc( &mod_reg ) ) {
        return( 0 );
    }

    mod = (uchar)(((int)mod_reg & 0xC0) >> 6);
    reg = (uchar)(((int)mod_reg & 0x38) >> 3);
    r_m = (uchar)(((int)mod_reg & 0x07) >> 0);

    dir         = modrm_class[class].dir;
    size        = modrm_class[class].size;
    method      = modrm_class[class].method;
    group       = modrm_class[class].group;
    size_needed = modrm_class[class].size_needed;
    type        = modrm_class[class].type;

    ref_mode = 0;

    if ( group == 6 ) {
        if ( mod == 3 ) {
            if ( reg == 0 || reg == 1 || reg == 2 || reg == 3 ) {
                addr_large = FALSE;         /* 286 only instructions */
                size_large = FALSE;
            }
        }
        type = WORD_PTR;
        size_needed = TRUE;
    }

    reg_size = size;                /* 386 Segments effect register names */
    if ( reg_size == 1 && size_large ) {
        reg_size = 2;
    }
    if ( type == UNKNOWN ) {
        type = reg_size_to_type( reg_size );
    }

    if ( group == 0 ) {
        opcode = text;
    } else {
        opcode = op_grp[group-1][reg];
    }
    if ( strlen(opcode) == 0 ) {
        return( 0 );
    }

    if ( class == 26 ) {
        reg_size = 1;
    }

    if ( byte == 0x62 || byte == 0x63 ) {
        if ( byte == 0x63 ) {
            type = WORD_PTR;
        }
        size_needed = TRUE;     /* LAR, LSL, BOUND, ARPL need size */
    }
    if ( byte == 0xC4 || byte == 0xC5
           || byte == 0xB2 || byte == 0xB4 || byte == 0xB5 ) {
        size_needed = TRUE;
    }

    if ( group == 3 ) {         /* Group 3 has a test instruction which    */
        if ( reg == 0 ) {       /* needs an immediate value (byte or word) */
            method = 5 + size;  /* the rest of group 3 needs nothing       */
            dir = 0;
            size_needed = TRUE;
        } else {
            method = 0;
            if ( reg == 2 || reg == 3 ) {
                size_needed = FALSE;
            } else {
                size_needed = TRUE;
            }
        }
    }

    if ( group == 5 ) {                 /* Group 5 has call far and jump far */
        if ( reg == 3 || reg == 5 ) {   /* instructions which are dwords     */
                                        /* the rest of group 5 is words      */
            if ( size_large ) {
                type = FWORD_PTR;
            } else {
                type = DWORD_PTR;
            }
            size_needed = TRUE;
        } else {
            if ( reg == 0 || reg == 1 ) {
                size_needed = TRUE;
            }
        }
    }

    if ( group == 7 ) {                 /* Group 7 has mostly FWORD sized    */
        if ( reg == 4 || reg == 6 ) {   /* EAs, but these two are WORD sized */
            type = WORD_PTR;
        }
    }

    if ( dir == 0 && mod == 3 && (class == 0 || class == 1) ) {
        /*
        ** Ambiguous!   eg. OBJ 20F8 = and al,bh => MASM 22C7
        ** This is because MASM prefers the first operand to be
        ** a register and the other operand to be a mem/reg.
        */
        return(0);
    }

    mem_text[0] = '\0';
    additional = do_mod_rm( mem_text, mod, r_m, type, size_needed, ref_mode );
    if ( additional == -1 ) {
        return( 0 );
    }

    switch( method ) {
        case 0:         /* No additional information (one operand only) */
            break;
        case 1:         /* Other operand is a register */
                        /* LES,LDS,BOUND,LSS,LFS,LGS, ARPL instructions */
                        /* revert to Word */
            if ( byte == 0xC4 || byte == 0xC5 || byte == 0x62 || byte == 0x63
                   || byte == 0xB2 || byte == 0xB4 || byte == 0xB5 ) {
                reg_size = 1;
            }

            strcpy( reg_text, regs[reg_size][reg] );
            break;
        case 2:         /* Other operand is a segment register */
            if ( reg > 5 ) {    /* 0=ES,1=CS,2=SS,3=DS,4=FS,5=GS */
                return( 0 );
            }
            strcpy( reg_text, sregs[reg] );
            break;
        case 3:         /* Other operand is 1 */
            strcpy( reg_text, "1" );
            break;
        case 4:         /* Other operand is register CL */
            strcpy( reg_text, "cl" );
            break;
        case 5:         /* Immediate byte value */
            if ( byte_immed(reg_text, additional,FALSE) ) {
                return( 0 );
            }
            additional++;
            break;
        case 6:         /* Immediate word value (could be fixupp) */
            if ( word_immed(reg_text, additional) ) {
                return( 0 );
            }
            if ( size_large ) {
                additional += 4;
            } else {
                additional += 2;
            }
            break;
        case 7:         /* Immediate signed byte value */
            if ( byte_immed(reg_text,additional,TRUE) ) {
                return( 0 );
            }
            additional++;
            break;
        case 8:         /* IMUL (3 operands [reg,mem,immed word]) */
            strcpy( reg_text, regs[reg_size][reg] );
            if ( word_immed(third_text, additional) ) {
                return(0);
            }
            additional += 2;
            break;
        case 9:         /* IMUL (3 operands [reg,mem,immed signed byte]) */
            strcpy( reg_text, regs[reg_size][reg] );
            if ( byte_immed(third_text, additional,TRUE) ) {
                return(0);
            }
            additional += 1;
            break;
        case 10:        /* Control Register (CR0...) */
            strcpy( reg_text, cr_regs[reg] );
            break;
        case 11:        /* Debug Register (DR0...) */
            strcpy( reg_text, dr_regs[reg] );
            break;
        case 12:
            strcpy( reg_text, tr_regs[reg] );
            break;
        case 13:
            strcpy( reg_text, regs[reg_size][reg] );
            strcpy( third_text, "cl" );
            break;
    }

    if ( dir & 0x01 ) {
        sprintf( operands, dir_fmt[dir], reg_text, mem_text, third_text );
    } else {
        sprintf( operands, dir_fmt[dir], mem_text, reg_text, third_text );
    }

    adjust_assumes();
    instr_opcode( opcode );
    instr_operand( operands );

    return( 2+additional );
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x148, %rsp            # imm = 0x148
movl %edx, %r15d
movq %rsi, %rbx
movl %edi, %ebp
leaq 0x68(%rsp), %rdi
callq 0x946e
movl $0x0, 0x18(%rsp)
testl %eax, %eax
je 0xae29
movl 0x18(%rsp), %eax
addq $0x148, %rsp            # imm = 0x148
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl %ebp, 0x1c(%rsp)
movq %rbx, 0x8(%rsp)
movb 0x68(%rsp), %r11b
movl %r11d, %r9d
shrb $0x6, %r9b
movl %r11d, %ebx
shrb $0x3, %bl
andb $0x7, %bl
movslq %r15d, %rax
imulq $0x18, %rax, %rcx
leaq 0xd85b(%rip), %rdx      # 0x186b0
movl 0x4(%rcx,%rdx), %r14d
movslq 0xc(%rcx,%rdx), %r13
pushq $0x4
popq %r10
cmpq $0x6, %r13
jne 0xae96
cmpb $0x3, %r9b
sete %al
cmpb $0x4, %bl
setb %sil
andb %al, %sil
pushq $0x1
popq %rbp
cmpb $0x1, %sil
jne 0xae91
andl $0x0, 0x10ffe(%rip)     # 0x1be88
andl $0x0, 0x10ff3(%rip)     # 0x1be84
movl %r10d, %eax
jmp 0xae9e
movl 0x10(%rcx,%rdx), %ebp
movl 0x14(%rcx,%rdx), %eax
movl (%rcx,%rdx), %esi
cmpl $0x0, 0x10fdc(%rip)     # 0x1be84
movl 0x8(%rcx,%rdx), %ecx
movq %rcx, 0x20(%rsp)
pushq $0x2
popq %r12
cmovel %r14d, %r12d
cmpl $0x1, %r14d
cmovnel %r14d, %r12d
testl %eax, %eax
jne 0xaeff
movl %esi, 0x4(%rsp)
movl %r12d, %edi
movl %r15d, 0x2c(%rsp)
movl %r9d, %r15d
movb %bl, 0x17(%rsp)
movl %r11d, %ebx
callq 0xeece
movl %ebx, %r11d
movb 0x17(%rsp), %bl
pushq $0x4
popq %r10
movl %r15d, %r9d
movl 0x2c(%rsp), %r15d
movl 0x4(%rsp), %esi
movl $0x0, 0x18(%rsp)
movzbl %bl, %edi
testl %r13d, %r13d
je 0xaf22
movq %r13, %rcx
shlq $0x6, %rcx
leaq 0xd4bb(%rip), %rdx      # 0x183d0
addq %rcx, %rdx
movq -0x40(%rdx,%rdi,8), %rcx
movq %rcx, 0x8(%rsp)
movq 0x8(%rsp), %rcx
cmpb $0x0, (%rcx)
je 0xae13
movq %r13, %r8
pushq $0x1
popq %r13
cmpl $0x1a, %r15d
cmovel %r13d, %r12d
movl 0x1c(%rsp), %edx
movl %edx, %ecx
andb $-0x2, %cl
cmpb $0x63, %dl
cmovel %r10d, %eax
cmpb $-0x4c, %cl
cmovel %r13d, %ebp
cmpb $-0x4e, %dl
cmovel %r13d, %ebp
cmpb $-0x3c, %cl
cmovel %r13d, %ebp
cmpb $0x62, %cl
cmovel %r13d, %ebp
cmpl $0x5, %r8d
je 0xaf99
movq %r8, %rdx
cmpl $0x3, %r8d
jne 0xafce
testb %bl, %bl
je 0xafb5
movl %r11d, %ecx
andb $0x30, %cl
xorl %r13d, %r13d
cmpb $0x10, %cl
setne %r13b
movq $0x0, 0x20(%rsp)
jmp 0xafd1
movq %r8, %rdx
cmpb $0x5, %bl
je 0xafa6
cmpl $0x3, %edi
jne 0xafc5
cmpl $0x1, 0x10ed7(%rip)     # 0x1be84
pushq $0x6
popq %rax
sbbl $0x0, %eax
jmp 0xafd1
addl $0x5, %r14d
xorl %esi, %esi
movl %r14d, %ecx
movq %rcx, 0x20(%rsp)
jmp 0xafd1
cmpb $0x2, %bl
pushq $0x1
popq %rcx
cmovbl %ecx, %ebp
movl %ebp, %r13d
cmpl $0x1, %r15d
ja 0xafe5
testl %esi, %esi
jne 0xafe5
cmpb $0x3, %r9b
je 0xae13
movq %rdi, %rbp
movl %esi, 0x4(%rsp)
movl %r11d, %ecx
andb $0x7, %cl
andb $0x28, %r11b
cmpb $0x20, %r11b
cmovnel %eax, %r10d
cmpl $0x7, %edx
cmovnel %eax, %r10d
leaq 0xb0(%rsp), %rdi
movb $0x0, (%rdi)
movzbl %r9b, %esi
movzbl %cl, %edx
movl %r10d, %ecx
movl %r13d, %r8d
callq 0xaae5
cmpl $-0x1, %eax
je 0xae13
movl %eax, %r14d
movq 0x20(%rsp), %rcx
decl %ecx
cmpl $0xc, %ecx
ja 0xb19c
leaq 0x700f(%rip), %rax      # 0x12054
movslq (%rax,%rcx,4), %rcx
addq %rax, %rcx
jmpq *%rcx
movzbl 0x1c(%rsp), %eax
leal -0xb2(%rax), %ecx
cmpl $0x13, %ecx
ja 0xb068
movl $0xc000d, %edx          # imm = 0xC000D
btl %ecx, %edx
jb 0xb070
addl $-0x62, %eax
cmpl $0x2, %eax
jae 0xb074
pushq $0x1
popq %r12
movslq %r12d, %rax
shlq $0x6, %rax
leaq 0xd08e(%rip), %rcx      # 0x18110
addq %rax, %rcx
movq (%rcx,%rbp,8), %rsi
jmp 0xb192
leaq 0xd25b(%rip), %rax      # 0x182f0
jmp 0xb18e
leaq 0x30(%rsp), %rdi
movl $0x0, 0x18(%rsp)
movl %r14d, %esi
xorl %edx, %edx
jmp 0xb23b
movslq %r12d, %rax
shlq $0x6, %rax
leaq 0xd051(%rip), %rcx      # 0x18110
addq %rax, %rcx
movq (%rcx,%rbp,8), %rsi
leaq 0x30(%rsp), %rdi
callq 0x9070
movw $0x6c63, 0x70(%rsp)     # imm = 0x6C63
movb $0x0, 0x72(%rsp)
jmp 0xb19c
leaq 0xd188(%rip), %rax      # 0x18270
jmp 0xb18e
movw $0x31, 0x30(%rsp)
jmp 0xb19c
movb $0x0, 0x32(%rsp)
movw $0x6c63, 0x30(%rsp)     # imm = 0x6C63
jmp 0xb19c
movslq %r12d, %rax
shlq $0x6, %rax
leaq 0xcff8(%rip), %rcx      # 0x18110
addq %rax, %rcx
movq (%rcx,%rbp,8), %rsi
leaq 0x30(%rsp), %rdi
callq 0x9070
leaq 0x70(%rsp), %rdi
movl %r14d, %esi
callq 0xad38
testl %eax, %eax
jne 0xae13
jmp 0xb250
cmpb $0x5, %bl
ja 0xae13
leaq 0xd0bd(%rip), %rax      # 0x18210
jmp 0xb18e
leaq 0x30(%rsp), %rdi
movl %r14d, %esi
callq 0xad38
testl %eax, %eax
jne 0xae13
cmpl $0x0, 0x10d13(%rip)     # 0x1be84
je 0xb250
addl $0x4, %r14d
jmp 0xb19c
leaq 0x30(%rsp), %rdi
jmp 0xb235
leaq 0xd122(%rip), %rax      # 0x182b0
movq (%rax,%rbp,8), %rsi
leaq 0x30(%rsp), %rdi
callq 0x9070
movq 0x8(%rsp), %rbx
movl 0x4(%rsp), %ebp
movslq %ebp, %rax
leaq 0xd4d1(%rip), %rcx      # 0x18680
movq (%rcx,%rax,8), %rsi
leaq 0xf0(%rsp), %rdi
testb $0x1, %bpl
jne 0xb1d0
leaq 0xb0(%rsp), %rdx
leaq 0x30(%rsp), %rcx
jmp 0xb1dd
leaq 0x30(%rsp), %rdx
leaq 0xb0(%rsp), %rcx
leaq 0x70(%rsp), %r8
xorl %eax, %eax
callq 0x91b0
callq 0xf1c1
movq %rbx, %rdi
callq 0x9491
leaq 0xf0(%rsp), %rdi
callq 0x94b3
addl $0x2, %r14d
movl %r14d, 0x18(%rsp)
jmp 0xae13
movslq %r12d, %rax
shlq $0x6, %rax
leaq 0xcef1(%rip), %rcx      # 0x18110
addq %rax, %rcx
movq (%rcx,%rbp,8), %rsi
leaq 0x30(%rsp), %rdi
callq 0x9070
leaq 0x70(%rsp), %rdi
pushq $0x1
popq %rdx
movl %r14d, %esi
callq 0xacaa
testl %eax, %eax
jne 0xae13
incl %r14d
jmp 0xb19c
addl $0x2, %r14d
jmp 0xb19c