// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::return_data(PACKET*)
void DRC_MEMORY_CONTROLLER::return_data(PACKET *packet)
{
    // check MSHR information
    int mshr_index = check_mshr(packet);

    // sanity check
    if (mshr_index == -1) {
        cerr << "[" << NAME << "_MSHR] " << __func__ << " instr_id: " << packet->instr_id << " cannot find a matching entry!";
        cerr << " full_addr: " << hex << packet->full_addr;
        cerr << " address: " << packet->address << dec;
        cerr << " event: " << packet->event_cycle << " current: " << current_core_cycle[packet->cpu] << endl;
        assert(0);
    }

    // MSHR holds the most updated information about this request
    // no need to do memcpy
    MSHR.num_returned++;
    MSHR.entry[mshr_index].returned = COMPLETED;
    MSHR.entry[mshr_index].data = packet->data;

    // ADD LATENCY
    MSHR.entry[mshr_index].event_cycle = current_core_cycle[packet->cpu];
    packet->event_cycle = current_core_cycle[packet->cpu];
    /*
    if (MSHR.entry[mshr_index].event_cycle < current_core_cycle[packet->cpu])
        MSHR.entry[mshr_index].event_cycle = current_core_cycle[packet->cpu] + LATENCY;
    else
        MSHR.entry[mshr_index].event_cycle += LATENCY;
    */

    // we need to immediately return these data to upper level memory
    // if we don't, it takes a very long time to 
    // 1) change the DRC mode from read to write
    // 2) fill in missing cache blocks in DRC
    // 3) finally return data to upper level cache
    // which eventually stalls the main core pipeline

    // FIXME: need to consider DRC dbus congestion
    // first add it to the wq and make one more function that can return data to on-chip caches

    // check fill level
    if (packet->fill_level < fill_level) {

        if (packet->instruction) 
            upper_level_icache[packet->cpu]->return_data(packet);
        else // data
            upper_level_dcache[packet->cpu]->return_data(packet);

        // since it is now returned to the upper level memory we must reset the fill_level
        // if we don't, when the DRC mode changes to the write mode and this block gets filled in the DRC
        // it will try to retun data again to the upper level memory
        packet->fill_level = FILL_DRC;
    }

    // before we add returned packet to DRC WQ, we must reset scheduled bit in this packet
    // since this packet once scheduled while it was sitting in DRC RQ to be processed
    packet->scheduled = 0;

    // add it to the WQ
    add_wq(packet); 
    update_schedule_cycle(&WQ);

    // even though it is not filled in the DRC yet, we can safely release MSHR resource
    MSHR.remove_queue(&MSHR.entry[mshr_index]);

    DP (if (warmup_complete[packet->cpu]) {
    cout << "[" << NAME << "_MSHR] " <<  __func__ << " instr_id: " << MSHR.entry[mshr_index].instr_id;
    cout << " address: " << hex << MSHR.entry[mshr_index].address << " full_addr: " << MSHR.entry[mshr_index].full_addr;
    cout << " data: " << MSHR.entry[mshr_index].data << dec << " num_returned: " << MSHR.num_returned;
    cout << " index: " << mshr_index << " occupancy: " << MSHR.occupancy;
    cout << " event: " << MSHR.entry[mshr_index].event_cycle << " current: " << current_core_cycle[packet->cpu] << " next: " << MSHR.next_fill_cycle << endl; });
}

// Assembly:
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r15
callq 0xf5cc
cmpl $-0x1, %eax
je 0xf8f0
incl 0x4073a8(%r15)
movq 0x407408(%r15), %rcx
cltq
imulq $0x380, %rax, %r14      # imm = 0x380
movb $0x2, 0x32c(%rcx,%r14)
movq 0x360(%rbx), %rax
movq %rax, 0x360(%rcx,%r14)
movl 0x330(%rbx), %eax
leaq 0x6d640(%rip), %rdx     # 0x7ceb0
movq (%rdx,%rax,8), %rdx
movq %rdx, 0x378(%rcx,%r14)
movq %rdx, 0x378(%rbx)
movl 0x8(%rbx), %ecx
cmpl 0x40946c(%r15), %ecx
jge 0xf8b0
xorl %ecx, %ecx
cmpb $0x0, (%rbx)
sete %cl
leaq (%r15,%rcx,8), %rcx
movq 0x8(%rcx,%rax,8), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x18(%rax)
movl $0x8, 0x8(%rbx)
leaq 0x407370(%r15), %r12
movb $0x0, 0x2(%rbx)
movq (%r15), %rax
movq %r15, %rdi
movq %rbx, %rsi
callq *0x8(%rax)
leaq 0x40a870(%r15), %rsi
callq 0xe496
addq 0x407408(%r15), %r14
movq %r12, %rdi
movq %r14, %rsi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
jmp 0x9cc0
movq 0x66f9(%rip), %r14      # 0x15ff0
leaq 0x792(%rip), %rsi       # 0x10090
movq %r14, %rdi
callq 0x2230
addq $0x7348, %r15           # imm = 0x7348
movq %rax, %rdi
movq %r15, %rsi
callq 0x21d0
leaq 0x980(%rip), %rsi       # 0x1029f
movq %rax, %rdi
callq 0x2230
leaq 0x979(%rip), %rsi       # 0x102a7
movq %rax, %rdi
callq 0x2230
leaq 0x151b(%rip), %rsi      # 0x10e58
movq %rax, %rdi
callq 0x2230
movq 0x368(%rbx), %rsi
movq %rax, %rdi
callq 0x2080
leaq 0x958(%rip), %rsi       # 0x102b3
movq %rax, %rdi
callq 0x2230
leaq 0x824(%rip), %rsi       # 0x1018e
movq %r14, %rdi
callq 0x2230
movq (%rax), %rcx
movq -0x18(%rcx), %rcx
movl 0x18(%rax,%rcx), %edx
andl $-0x4b, %edx
orl $0x8, %edx
movl %edx, 0x18(%rax,%rcx)
movq 0x348(%rbx), %rsi
movq %rax, %rdi
callq 0x2080
leaq 0x7e6(%rip), %rsi       # 0x10183
movq %r14, %rdi
callq 0x2230
movq 0x340(%rbx), %rsi
movq %rax, %rdi
callq 0x2080
movq (%rax), %rcx
movq -0x18(%rcx), %rcx
movl 0x18(%rax,%rcx), %edx
andl $-0x4b, %edx
orl $0x2, %edx
movl %edx, 0x18(%rax,%rcx)
leaq 0x7cb(%rip), %rsi       # 0x1019b
movq %r14, %rdi
callq 0x2230
movq 0x378(%rbx), %rsi
movq %rax, %rdi
callq 0x2080
leaq 0x8e4(%rip), %rsi       # 0x102d2
movq %rax, %rdi
callq 0x2230
movl 0x330(%rbx), %ecx
leaq 0x6d4ad(%rip), %rdx     # 0x7ceb0
movq (%rdx,%rcx,8), %rsi
movq %rax, %rdi
callq 0x2080
movq %rax, %rdi
callq 0x2110
leaq 0x649(%rip), %rdi       # 0x10067
leaq 0x1583(%rip), %rsi      # 0x10fa8
leaq 0x164a(%rip), %rcx      # 0x11076
movl $0x381, %edx            # imm = 0x381
callq 0x2160