// File: /workspace/github_c_makefile_star2_O0/nh13[P]ksw/src/parasail/src/nw_diag_avx2_256_32.c
// Function: arr_store_si256
static inline void arr_store_si256(
        int *array,
        __m256i vWH,
        int32_t i,
        int32_t s1Len,
        int32_t j,
        int32_t s2Len)
{
    if (0 <= i+0 && i+0 < s1Len && 0 <= j-0 && j-0 < s2Len) {
        array[1LL*(i+0)*s2Len + (j-0)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 7);
    }
    if (0 <= i+1 && i+1 < s1Len && 0 <= j-1 && j-1 < s2Len) {
        array[1LL*(i+1)*s2Len + (j-1)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 6);
    }
    if (0 <= i+2 && i+2 < s1Len && 0 <= j-2 && j-2 < s2Len) {
        array[1LL*(i+2)*s2Len + (j-2)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 5);
    }
    if (0 <= i+3 && i+3 < s1Len && 0 <= j-3 && j-3 < s2Len) {
        array[1LL*(i+3)*s2Len + (j-3)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 4);
    }
    if (0 <= i+4 && i+4 < s1Len && 0 <= j-4 && j-4 < s2Len) {
        array[1LL*(i+4)*s2Len + (j-4)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 3);
    }
    if (0 <= i+5 && i+5 < s1Len && 0 <= j-5 && j-5 < s2Len) {
        array[1LL*(i+5)*s2Len + (j-5)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 2);
    }
    if (0 <= i+6 && i+6 < s1Len && 0 <= j-6 && j-6 < s2Len) {
        array[1LL*(i+6)*s2Len + (j-6)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 1);
    }
    if (0 <= i+7 && i+7 < s1Len && 0 <= j-7 && j-7 < s2Len) {
        array[1LL*(i+7)*s2Len + (j-7)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 0);
    }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
andq $-0x20, %rsp
subq $0x60, %rsp
movq %rdi, 0x48(%rsp)
vmovdqa %ymm0, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movl %edx, 0x18(%rsp)
movl %ecx, 0x14(%rsp)
movl %r8d, 0x10(%rsp)
movl 0x1c(%rsp), %ecx
addl $0x0, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c049c
movl 0x1c(%rsp), %eax
addl $0x0, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c049c
movl 0x14(%rsp), %ecx
subl $0x0, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c049c
movl 0x14(%rsp), %eax
subl $0x0, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c049c
movl 0x3c(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x0, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x0, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x1, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0500
movl 0x1c(%rsp), %eax
addl $0x1, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c0500
movl 0x14(%rsp), %ecx
subl $0x1, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0500
movl 0x14(%rsp), %eax
subl $0x1, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c0500
movl 0x38(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x1, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x1, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x2, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0564
movl 0x1c(%rsp), %eax
addl $0x2, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c0564
movl 0x14(%rsp), %ecx
subl $0x2, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0564
movl 0x14(%rsp), %eax
subl $0x2, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c0564
movl 0x34(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x2, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x2, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x3, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c05c8
movl 0x1c(%rsp), %eax
addl $0x3, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c05c8
movl 0x14(%rsp), %ecx
subl $0x3, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c05c8
movl 0x14(%rsp), %eax
subl $0x3, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c05c8
movl 0x30(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x3, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x3, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x4, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c062c
movl 0x1c(%rsp), %eax
addl $0x4, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c062c
movl 0x14(%rsp), %ecx
subl $0x4, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c062c
movl 0x14(%rsp), %eax
subl $0x4, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c062c
movl 0x2c(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x4, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x4, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x5, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0690
movl 0x1c(%rsp), %eax
addl $0x5, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c0690
movl 0x14(%rsp), %ecx
subl $0x5, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0690
movl 0x14(%rsp), %eax
subl $0x5, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c0690
movl 0x28(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x5, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x5, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x6, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c06f4
movl 0x1c(%rsp), %eax
addl $0x6, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c06f4
movl 0x14(%rsp), %ecx
subl $0x6, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c06f4
movl 0x14(%rsp), %eax
subl $0x6, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c06f4
movl 0x24(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x6, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x6, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %ecx
addl $0x7, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0758
movl 0x1c(%rsp), %eax
addl $0x7, %eax
cmpl 0x18(%rsp), %eax
jge 0x9c0758
movl 0x14(%rsp), %ecx
subl $0x7, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0x9c0758
movl 0x14(%rsp), %eax
subl $0x7, %eax
cmpl 0x10(%rsp), %eax
jge 0x9c0758
movl 0x20(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x7, %ecx
movslq %ecx, %rcx
shlq $0x0, %rcx
movslq 0x10(%rsp), %rsi
imulq %rsi, %rcx
movl 0x14(%rsp), %esi
subl $0x7, %esi
movslq %esi, %rsi
addq %rsi, %rcx
movl %edx, (%rax,%rcx,4)
movq %rbp, %rsp
popq %rbp
vzeroupper
retq