// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]ramulator/src/Scheduler.h
// Function: ramulator::Scheduler<ramulator::DDR3>::get_head(std::__cxx11::list<ramulator::Request, std::allocator<ramulator::Request>>&)
list<Request>::iterator get_head(list<Request>& q)
    {
        // TODO make the decision at compile time
        if (type != Type::FRFCFS_PriorHit) {
            //If queue is empty, return end of queue
            if (!q.size())
                return q.end();

            //Else return based on the policy
            auto head = q.begin();
            for (auto itr = next(q.begin(), 1); itr != q.end(); itr++)
                head = compare[int(type)](head, itr);

            return head;
        } 
        else { //Code to get around edge cases for FRFCFS_PriorHit
            
       //If queue is empty, return end of queue
            if (!q.size())
                return q.end();

       //Else return based on FRFCFS_PriorHit Scheduling Policy
            auto head = q.begin();
            for (auto itr = next(q.begin(), 1); itr != q.end(); itr++) {
                head = compare[int(Type::FRFCFS_PriorHit)](head, itr);
            }

            if (this->ctrl->is_ready(head) && this->ctrl->is_row_hit(head)) {
                return head;
            }

            // prepare a list of hit request
            vector<vector<int>> hit_reqs;
            for (auto itr = q.begin() ; itr != q.end() ; ++itr) {
                if (this->ctrl->is_row_hit(itr)) {
                    auto begin = itr->addr_vec.begin();
                    // TODO Here it assumes all DRAM standards use PRE to close a row
                    // It's better to make it more general.
                    auto end = begin + int(ctrl->channel->spec->scope[int(T::Command::PRE)]) + 1;
                    vector<int> rowgroup(begin, end); // bank or subarray
                    hit_reqs.push_back(rowgroup);
                }
            }
            // if we can't find proper request, we need to return q.end(),
            // so that no command will be scheduled
            head = q.end();
            for (auto itr = q.begin(); itr != q.end(); itr++) {
                bool violate_hit = false;
                if ((!this->ctrl->is_row_hit(itr)) && this->ctrl->is_row_open(itr)) {
                    // so the next instruction to be scheduled is PRE, might violate hit
                    auto begin = itr->addr_vec.begin();
                    // TODO Here it assumes all DRAM standards use PRE to close a row
                    // It's better to make it more general.
                    auto end = begin + int(ctrl->channel->spec->scope[int(T::Command::PRE)]) + 1;
                    vector<int> rowgroup(begin, end); // bank or subarray
                    for (const auto& hit_req_rowgroup : hit_reqs) {
                        if (rowgroup == hit_req_rowgroup) {
                            violate_hit = true;
                            break;
                        }  
                    }
                }
                if (violate_hit) {
                    continue;
                }
                // If it comes here, that means it won't violate any hit request
                if (head == q.end()) {
                    head = itr;
                } else {
                    head = compare[int(Type::FRFCFS)](head, itr);
                }
            }

            return head;
        }
    }

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, %r14
cmpl $0x3, 0x8(%rdi)
movq %rsi, 0x10(%rsp)
movq 0x10(%rsi), %rax
jne 0x1f6a6
testq %rax, %rax
je 0x1f6ee
movq 0x10(%rsp), %rax
movq (%rax), %r15
pushq $0x1
popq %rsi
movq %r15, %rdi
callq 0x201ab
movq %rax, %rbx
leaq 0x78(%r14), %r13
cmpq 0x10(%rsp), %rbx
je 0x1f6f8
movq %r13, %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq 0x201ca
movq %rax, %r15
movq (%rbx), %rbx
jmp 0x1f689
testq %rax, %rax
je 0x1f6ee
movq 0x10(%rsp), %rax
movq (%rax), %r15
pushq $0x1
popq %rsi
movq %r15, %rdi
callq 0x201ab
movq %rax, %rbx
leaq 0x18(%r14), %r13
cmpq 0x10(%rsp), %rbx
je 0x1f86b
movslq 0x8(%r14), %rdi
shlq $0x5, %rdi
addq %r13, %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq 0x201ca
movq %rax, %r15
movq (%rbx), %rbx
jmp 0x1f6c5
movq 0x10(%rsp), %r15
jmp 0x1f86b
movq (%r14), %rdi
movq %r15, %rsi
callq 0x1b440
testb %al, %al
je 0x1f71a
movq (%r14), %rdi
movq %r15, %rsi
callq 0x1ba2a
testb %al, %al
jne 0x1f86b
xorps %xmm0, %xmm0
leaq 0x20(%rsp), %rbx
andq $0x0, 0x10(%rbx)
movaps %xmm0, (%rbx)
leaq 0x40(%rsp), %r15
leaq 0xf(%rsp), %r13
movq 0x10(%rsp), %rbp
movq (%rbp), %rbp
cmpq 0x10(%rsp), %rbp
je 0x1f794
movq (%r14), %rdi
movq %rbp, %rsi
callq 0x1ba2a
testb %al, %al
je 0x1f739
movq 0x20(%rbp), %rsi
movq (%r14), %rax
movq 0x1098(%rax), %rax
movq 0x390(%rax), %rax
movslq 0x184(%rax), %rax
leaq 0x4(%rsi,%rax,4), %rdx
movq %r15, %rdi
movq %r13, %rcx
callq 0x201f6
movq %rbx, %rdi
movq %r15, %rsi
callq 0x20228
movq %r15, %rdi
callq 0x1b7dc
jmp 0x1f739
leaq 0x38(%r14), %rax
movq %rax, 0x18(%rsp)
leaq 0x40(%rsp), %r13
movq 0x10(%rsp), %rax
movq %rax, %rbx
movq %rax, %r15
movq (%rbx), %rbx
cmpq 0x10(%rsp), %rbx
je 0x1f861
movq (%r14), %rdi
movq %rbx, %rsi
callq 0x1ba2a
testb %al, %al
jne 0x1f83e
movq (%r14), %rdi
movq %rbx, %rsi
callq 0x1faf4
testb %al, %al
je 0x1f83e
movq 0x20(%rbx), %rsi
movq (%r14), %rax
movq 0x1098(%rax), %rax
movq 0x390(%rax), %rax
movslq 0x184(%rax), %rax
leaq 0x4(%rsi,%rax,4), %rdx
movq %r13, %rdi
leaq 0xf(%rsp), %rcx
callq 0x201f6
movq 0x20(%rsp), %rbp
movq 0x28(%rsp), %r12
cmpq %r12, %rbp
je 0x1f836
movq %r13, %rdi
movq %rbp, %rsi
callq 0x20254
addq $0x18, %rbp
testb %al, %al
je 0x1f811
movq %r13, %rdi
callq 0x1b7dc
jmp 0x1f7ad
movq %r13, %rdi
callq 0x1b7dc
movq %rbx, %rax
cmpq 0x10(%rsp), %r15
je 0x1f7aa
movq 0x18(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq 0x201ca
jmp 0x1f7aa
leaq 0x20(%rsp), %rdi
callq 0x1bef6
movq %r15, %rax
addq $0x58, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
jmp 0x1f887
jmp 0x1f887
jmp 0x1f88c
jmp 0x1f887
jmp 0x1f887
movq %rax, %rbx
jmp 0x1f899
movq %rax, %rbx
leaq 0x40(%rsp), %rdi
callq 0x1b7dc
leaq 0x20(%rsp), %rdi
callq 0x1bef6
movq %rbx, %rdi
callq 0xb4d0
nop