// File: /workspace/github_c_makefile_star2_O0/samtools[P]htslib/htscodecs/htscodecs/rANS_static32x16pr_avx512.c
// Function: rans_compress_O0_32x16_avx512
unsigned char *rans_compress_O0_32x16_avx512(unsigned char *in,
                                             unsigned int in_size,
                                             unsigned char *out,
                                             unsigned int *out_size) {
    unsigned char *cp, *out_end;
    RansEncSymbol syms[256];
    RansState ransN[32] __attribute__((aligned(64)));
    uint8_t* ptr;
    uint32_t F[256+MAGIC] = {0};
    int i, j, tab_size = 0, x, z;
    // -20 for order/size/meta
    uint32_t bound = rans_compress_bound_4x16(in_size,0)-20;

    if (!out) {
        *out_size = bound;
        out = malloc(*out_size);
    }
    if (!out || bound > *out_size)
        return NULL;

    // If "out" isn't word aligned, tweak out_end/ptr to ensure it is.
    // We already added more round in bound to allow for this.
    if (((size_t)out)&1)
        bound--;
    ptr = out_end = out + bound;

    if (in_size == 0)
        goto empty;

    // Compute statistics
    if (hist8(in, in_size, F) < 0)
        return NULL;

    // Normalise so frequences sum to power of 2
    uint32_t fsum = in_size;
    uint32_t max_val = round2(fsum);
    if (max_val > TOTFREQ)
        max_val = TOTFREQ;

    if (normalise_freq(F, fsum, max_val) < 0)
        return NULL;
    fsum=max_val;

    cp = out;
    cp += encode_freq(cp, F);
    tab_size = cp-out;
    //write(2, out+4, cp-(out+4));

    if (normalise_freq(F, fsum, TOTFREQ) < 0)
        return NULL;

    // Encode statistics and build lookup tables for SIMD encoding.
    uint32_t SB[256], SA[256], SD[256], SC[256];
    for (x = j = 0; j < 256; j++) {
        if (F[j]) {
            RansEncSymbolInit(&syms[j], x, F[j], TF_SHIFT);
            SB[j] = syms[j].x_max;
            SA[j] = syms[j].rcp_freq;
            SD[j] = (syms[j].cmpl_freq<<0) | ((syms[j].rcp_shift-32)<<16);
            SC[j] = syms[j].bias;
            x += F[j];
        }
    }

    for (z = 0; z < 32; z++)
      RansEncInit(&ransN[z]);

    z = i = in_size&(32-1);
    while (z-- > 0)
      RansEncPutSymbol(&ransN[z], &ptr, &syms[in[in_size-(i-z)]]);

#define LOAD512(a,b)                                     \
    __m512i a##1 = _mm512_load_si512((__m512i *)&b[0]); \
    __m512i a##2 = _mm512_load_si512((__m512i *)&b[16]);

#define STORE512(a,b)                           \
    _mm512_store_si512((__m256i *)&b[0], a##1); \
    _mm512_store_si512((__m256i *)&b[16], a##2);

    LOAD512(Rv, ransN);

    uint16_t *ptr16 = (uint16_t *)ptr;
    for (i=(in_size &~(32-1)); i>0; i-=32) {
        uint8_t *c = &in[i-32];

        // GATHER versions
        // Much faster now we have an efficient loadu mechanism in place,
        // BUT...
        // Try this for avx2 variant too?  Better way to populate the mm256
        // regs for mix of avx2 and avx512 opcodes.
        __m256i c12 = _mm256_loadu_si256((__m256i const *)c);
        __m512i c1 = _mm512_cvtepu8_epi32(_mm256_extracti128_si256(c12,0));
        __m512i c2 = _mm512_cvtepu8_epi32(_mm256_extracti128_si256(c12,1));
#define SET512(a,b) \
        __m512i a##1 = _mm512_i32gather_epi32x(c1, b, 4); \
        __m512i a##2 = _mm512_i32gather_epi32x(c2, b, 4)

        SET512(xmax, SB);

        uint16_t gt_mask1 = _mm512_cmpgt_epi32_mask(Rv1, xmax1);
        int pc1 = _mm_popcnt_u32(gt_mask1);
        __m512i Rp1 = _mm512_and_si512(Rv1, _mm512_set1_epi32(0xffff));
        __m512i Rp2 = _mm512_and_si512(Rv2, _mm512_set1_epi32(0xffff));
        uint16_t gt_mask2 = _mm512_cmpgt_epi32_mask(Rv2, xmax2);
        SET512(SDv,  SD);
        int pc2 = _mm_popcnt_u32(gt_mask2);

        Rp1 = _mm512_maskz_compress_epi32(gt_mask1, Rp1);
        Rp2 = _mm512_maskz_compress_epi32(gt_mask2, Rp2);

        _mm512_mask_cvtepi32_storeu_epi16(ptr16-pc2, (1<<pc2)-1, Rp2);
        ptr16 -= pc2;
        _mm512_mask_cvtepi32_storeu_epi16(ptr16-pc1, (1<<pc1)-1, Rp1);
        ptr16 -= pc1;

        SET512(rfv,  SA);
        Rv1 = _mm512_mask_srli_epi32(Rv1, gt_mask1, Rv1, 16);
        Rv2 = _mm512_mask_srli_epi32(Rv2, gt_mask2, Rv2, 16);

        // interleaved form of this, helps on icc a bit
        //rfv1 = _mm512_mulhi_epu32(Rv1, rfv1);
        //rfv2 = _mm512_mulhi_epu32(Rv2, rfv2);

        // Alternatives here:
        // SHIFT right/left instead of AND: (very marginally slower)
        //   rf1_hm = _mm512_and_epi32(
        //           rf1_hm, _mm512_set1_epi64((uint64_t)0xffffffff00000000));
        // vs
        //   rf1_hm = _mm512_srli_epi64(rf1_hm, 32);
        //   rf1_hm = _mm512_slli_epi64(rf1_hm, 32);
        __m512i rf1_hm = _mm512_mul_epu32(_mm512_srli_epi64(Rv1,  32),
                                          _mm512_srli_epi64(rfv1, 32));
        __m512i rf2_hm = _mm512_mul_epu32(_mm512_srli_epi64(Rv2,  32),
                                          _mm512_srli_epi64(rfv2, 32));
        __m512i rf1_lm = _mm512_srli_epi64(_mm512_mul_epu32(Rv1, rfv1), 32);
        __m512i rf2_lm = _mm512_srli_epi64(_mm512_mul_epu32(Rv2, rfv2), 32);
        rf1_hm = _mm512_and_epi32(rf1_hm,
                                  _mm512_set1_epi64((uint64_t)0xffffffff<<32));
        rf2_hm = _mm512_and_epi32(rf2_hm,
                                  _mm512_set1_epi64((uint64_t)0xffffffff<<32));
        rfv1 = _mm512_or_epi32(rf1_lm, rf1_hm);
        rfv2 = _mm512_or_epi32(rf2_lm, rf2_hm);

        // Or a pure masked blend approach, sadly slower.
        // rfv1 = _mm512_mask_blend_epi32(0x5555,
        //            _mm512_mul_epu32(
        //                _mm512_srli_epi64(Rv1, 32),
        //                _mm512_srli_epi64(rfv1, 32)),
        //            _mm512_srli_epi64(
        //                _mm512_mul_epu32(Rv1, rfv1),
        //                32));
        // rfv2 = _mm512_mask_blend_epi32(0xaaaa,
        //            _mm512_srli_epi64(
        //                _mm512_mul_epu32(Rv2, rfv2),
        //                32),
        //            _mm512_mul_epu32(
        //                _mm512_srli_epi64(Rv2, 32),
        //                _mm512_srli_epi64(rfv2, 32)));

        SET512(biasv, SC);
        __m512i shiftv1 = _mm512_srli_epi32(SDv1, 16);
        __m512i shiftv2 = _mm512_srli_epi32(SDv2, 16);

        __m512i qv1 = _mm512_srlv_epi32(rfv1, shiftv1);
        __m512i qv2 = _mm512_srlv_epi32(rfv2, shiftv2);

        qv1 = _mm512_mullo_epi32(qv1,
                  _mm512_and_si512(SDv1,_mm512_set1_epi32(0xffff)));
        qv1 = _mm512_add_epi32(qv1, biasv1);
        Rv1 = _mm512_add_epi32(Rv1, qv1);

        qv2 = _mm512_mullo_epi32(qv2,
                  _mm512_and_si512(SDv2, _mm512_set1_epi32(0xffff)));
        qv2 = _mm512_add_epi32(qv2, biasv2);
        Rv2 = _mm512_add_epi32(Rv2, qv2);
    }
    ptr = (uint8_t *)ptr16;
    STORE512(Rv, ransN);

    for (z = 32-1; z >= 0; z--)
        RansEncFlush(&ransN[z], &ptr);

 empty:
    // Finalise block size and return it
    *out_size = (out_end - ptr) + tab_size;

    memmove(out + tab_size, ptr, out_end-ptr);

    return out;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
andq $-0x40, %rsp
subq $0x43c0, %rsp           # imm = 0x43C0
movq %rdi, 0x2be8(%rsp)
movl %esi, 0x2be4(%rsp)
movq %rdx, 0x2bd8(%rsp)
movq %rcx, 0x2bd0(%rsp)
leaq 0x1710(%rsp), %rdi
xorl %esi, %esi
movl $0x420, %edx            # imm = 0x420
callq 0x4250
movl $0x0, 0x1704(%rsp)
movl 0x2be4(%rsp), %edi
xorl %esi, %esi
callq 0x8e2d0
subl $0x14, %eax
movl %eax, 0x16f8(%rsp)
cmpq $0x0, 0x2bd8(%rsp)
jne 0xa74da
movl 0x16f8(%rsp), %ecx
movq 0x2bd0(%rsp), %rax
movl %ecx, (%rax)
movq 0x2bd0(%rsp), %rax
movl (%rax), %eax
movl %eax, %edi
callq 0x4650
movq %rax, 0x2bd8(%rsp)
cmpq $0x0, 0x2bd8(%rsp)
je 0xa74f8
movl 0x16f8(%rsp), %eax
movq 0x2bd0(%rsp), %rcx
cmpl (%rcx), %eax
jbe 0xa7509
movq $0x0, 0x2bf0(%rsp)
jmp 0xa87e5
movq 0x2bd8(%rsp), %rax
andq $0x1, %rax
cmpq $0x0, %rax
je 0xa752c
movl 0x16f8(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x16f8(%rsp)
movq 0x2bd8(%rsp), %rax
movl 0x16f8(%rsp), %ecx
addq %rcx, %rax
movq %rax, 0x2bc0(%rsp)
movq %rax, 0x1b38(%rsp)
cmpl $0x0, 0x2be4(%rsp)
jne 0xa755d
jmp 0xa8775
movq 0x2be8(%rsp), %rdi
movl 0x2be4(%rsp), %esi
leaq 0x1710(%rsp), %rdx
callq 0xa8800
cmpl $0x0, %eax
jge 0xa758f
movq $0x0, 0x2bf0(%rsp)
jmp 0xa87e5
movl 0x2be4(%rsp), %eax
movl %eax, 0x16f4(%rsp)
movl 0x16f4(%rsp), %edi
callq 0xa8c40
movl %eax, 0x16f0(%rsp)
cmpl $0x1000, 0x16f0(%rsp) # imm = 0x1000
jbe 0xa75c8
movl $0x1000, 0x16f0(%rsp) # imm = 0x1000
leaq 0x1710(%rsp), %rdi
movl 0x16f4(%rsp), %esi
movl 0x16f0(%rsp), %edx
callq 0xa8ca0
cmpl $0x0, %eax
jge 0xa75f9
movq $0x0, 0x2bf0(%rsp)
jmp 0xa87e5
movl 0x16f0(%rsp), %eax
movl %eax, 0x16f4(%rsp)
movq 0x2bd8(%rsp), %rax
movq %rax, 0x2bc8(%rsp)
movq 0x2bc8(%rsp), %rdi
leaq 0x1710(%rsp), %rsi
callq 0xa8f20
movl %eax, %ecx
movq 0x2bc8(%rsp), %rax
movslq %ecx, %rcx
addq %rcx, %rax
movq %rax, 0x2bc8(%rsp)
movq 0x2bc8(%rsp), %rax
movq 0x2bd8(%rsp), %rcx
subq %rcx, %rax
movl %eax, 0x1704(%rsp)
leaq 0x1710(%rsp), %rdi
movl 0x16f4(%rsp), %esi
movl $0x1000, %edx           # imm = 0x1000
callq 0xa8ca0
cmpl $0x0, %eax
jge 0xa768d
movq $0x0, 0x2bf0(%rsp)
jmp 0xa87e5
movl $0x0, 0x1708(%rsp)
movl $0x0, 0x1700(%rsp)
cmpl $0x100, 0x1708(%rsp) # imm = 0x100
jge 0xa7800
movslq 0x1708(%rsp), %rax
cmpl $0x0, 0x1710(%rsp,%rax,4)
je 0xa77e8
movslq 0x1708(%rsp), %rax
leaq 0x1bc0(%rsp), %rdi
shlq $0x4, %rax
addq %rax, %rdi
movl 0x1700(%rsp), %esi
movslq 0x1708(%rsp), %rax
movl 0x1710(%rsp,%rax,4), %edx
movl $0xc, %ecx
callq 0xa8fc0
movslq 0x1708(%rsp), %rcx
leaq 0x1bc0(%rsp), %rax
shlq $0x4, %rcx
addq %rcx, %rax
movl (%rax), %ecx
movslq 0x1708(%rsp), %rax
movl %ecx, 0x12f0(%rsp,%rax,4)
movslq 0x1708(%rsp), %rcx
leaq 0x1bc0(%rsp), %rax
shlq $0x4, %rcx
addq %rcx, %rax
movl 0x4(%rax), %ecx
movslq 0x1708(%rsp), %rax
movl %ecx, 0xef0(%rsp,%rax,4)
movslq 0x1708(%rsp), %rcx
leaq 0x1bc0(%rsp), %rax
shlq $0x4, %rcx
addq %rcx, %rax
movzwl 0xc(%rax), %ecx
shll $0x0, %ecx
movslq 0x1708(%rsp), %rdx
leaq 0x1bc0(%rsp), %rax
shlq $0x4, %rdx
addq %rdx, %rax
movzwl 0xe(%rax), %eax
subl $0x20, %eax
shll $0x10, %eax
orl %eax, %ecx
movslq 0x1708(%rsp), %rax
movl %ecx, 0xaf0(%rsp,%rax,4)
movslq 0x1708(%rsp), %rcx
leaq 0x1bc0(%rsp), %rax
shlq $0x4, %rcx
addq %rcx, %rax
movl 0x8(%rax), %ecx
movslq 0x1708(%rsp), %rax
movl %ecx, 0x6f0(%rsp,%rax,4)
movslq 0x1708(%rsp), %rax
movl 0x1710(%rsp,%rax,4), %eax
addl 0x1700(%rsp), %eax
movl %eax, 0x1700(%rsp)
jmp 0xa77ea
movl 0x1708(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x1708(%rsp)
jmp 0xa76a3
movl $0x0, 0x16fc(%rsp)
cmpl $0x20, 0x16fc(%rsp)
jge 0xa7844
movslq 0x16fc(%rsp), %rax
leaq 0x1b40(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
callq 0xa9160
movl 0x16fc(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x16fc(%rsp)
jmp 0xa780b
movl 0x2be4(%rsp), %eax
andl $0x1f, %eax
movl %eax, 0x170c(%rsp)
movl %eax, 0x16fc(%rsp)
movl 0x16fc(%rsp), %eax
movl %eax, %ecx
addl $-0x1, %ecx
movl %ecx, 0x16fc(%rsp)
cmpl $0x0, %eax
jle 0xa78ce
movslq 0x16fc(%rsp), %rax
leaq 0x1b40(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
movq 0x2be8(%rsp), %rax
movl 0x2be4(%rsp), %ecx
movl 0x170c(%rsp), %edx
subl 0x16fc(%rsp), %edx
subl %edx, %ecx
movl %ecx, %ecx
movzbl (%rax,%rcx), %eax
leaq 0x1bc0(%rsp), %rdx
shlq $0x4, %rax
addq %rax, %rdx
leaq 0x1b38(%rsp), %rsi
callq 0xa9180
jmp 0xa785c
leaq 0x1b40(%rsp), %rax
movq %rax, 0x2c00(%rsp)
movq 0x2c00(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x680(%rsp)
leaq 0x1b40(%rsp), %rax
addq $0x40, %rax
movq %rax, 0x2bf8(%rsp)
movq 0x2bf8(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x640(%rsp)
movq 0x1b38(%rsp), %rax
movq %rax, 0x638(%rsp)
movl 0x2be4(%rsp), %eax
andl $-0x20, %eax
movl %eax, 0x170c(%rsp)
cmpl $0x0, 0x170c(%rsp)
jle 0xa8698
movq 0x2be8(%rsp), %rax
movl 0x170c(%rsp), %ecx
addl $-0x20, %ecx
movslq %ecx, %rcx
addq %rcx, %rax
movq %rax, 0x630(%rsp)
movq 0x630(%rsp), %rax
movq %rax, 0x2c08(%rsp)
movq 0x2c08(%rsp), %rax
vmovups (%rax), %ymm0
vmovaps %ymm0, 0x600(%rsp)
vmovaps 0x600(%rsp), %ymm0
vmovdqa %xmm0, 0x2c20(%rsp)
vpmovzxbd 0x2c20(%rsp), %zmm0
vmovdqa64 %zmm0, 0x5c0(%rsp)
vmovaps 0x600(%rsp), %ymm0
vextracti128 $0x1, %ymm0, 0x2c10(%rsp)
vpmovzxbd 0x2c10(%rsp), %zmm0
vmovdqa64 %zmm0, 0x580(%rsp)
vmovdqa64 0x5c0(%rsp), %zmm0
leaq 0x12f0(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movl $0x4, %esi
movl %esi, 0x3c(%rsp)
callq 0xa9240
movq 0x10(%rsp), %rdi
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x540(%rsp)
vmovdqa64 0x580(%rsp), %zmm0
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x500(%rsp)
vmovdqa64 0x680(%rsp), %zmm0
vmovdqa64 0x540(%rsp), %zmm1
vpcmpgtd %zmm1, %zmm0, %k0
kmovw %k0, 0x4fe(%rsp)
movzwl 0x4fe(%rsp), %eax
movl %eax, 0x2c3c(%rsp)
popcntl 0x2c3c(%rsp), %eax
movl %eax, 0x4f8(%rsp)
vmovdqa64 0x680(%rsp), %zmm1
movl $0xffff, 0x303c(%rsp) # imm = 0xFFFF
vpbroadcastd 0x303c(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2fc0(%rsp)
vmovdqa64 0x2fc0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2e00(%rsp)
vmovdqa64 %zmm0, 0x2dc0(%rsp)
vmovdqa64 0x2e00(%rsp), %zmm0
vmovdqa64 0x2dc0(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x480(%rsp)
vmovdqa64 0x640(%rsp), %zmm1
movl $0xffff, 0x2fbc(%rsp) # imm = 0xFFFF
vpbroadcastd 0x2fbc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2f40(%rsp)
vmovdqa64 0x2f40(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2d80(%rsp)
vmovdqa64 %zmm0, 0x2d40(%rsp)
vmovdqa64 0x2d80(%rsp), %zmm0
vmovdqa64 0x2d40(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x440(%rsp)
vmovdqa64 0x640(%rsp), %zmm0
vmovdqa64 0x500(%rsp), %zmm1
vpcmpgtd %zmm1, %zmm0, %k0
kmovw %k0, 0x43e(%rsp)
vmovdqa64 0x5c0(%rsp), %zmm0
leaq 0xaf0(%rsp), %rdi
movq %rdi, 0x18(%rsp)
callq 0xa9240
movq 0x18(%rsp), %rdi
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x3c0(%rsp)
vmovdqa64 0x580(%rsp), %zmm0
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x380(%rsp)
movzwl 0x43e(%rsp), %eax
movl %eax, 0x2c38(%rsp)
popcntl 0x2c38(%rsp), %eax
movl %eax, 0x37c(%rsp)
movw 0x4fe(%rsp), %ax
vmovdqa64 0x480(%rsp), %zmm0
movw %ax, 0x313e(%rsp)
vmovdqa64 %zmm0, 0x30c0(%rsp)
vmovdqa64 0x30c0(%rsp), %zmm2
vxorps %xmm0, %xmm0, %xmm0
vmovdqa64 %zmm0, 0x4300(%rsp)
vmovdqa64 0x4300(%rsp), %zmm1
kmovw 0x313e(%rsp), %k1
vpcompressd %zmm2, %zmm1 {%k1}
vmovdqa64 %zmm1, 0x480(%rsp)
movw 0x43e(%rsp), %ax
vmovdqa64 0x440(%rsp), %zmm1
movw %ax, 0x30be(%rsp)
vmovdqa64 %zmm1, 0x3040(%rsp)
vmovdqa64 0x3040(%rsp), %zmm1
vmovdqa64 %zmm0, 0x4340(%rsp)
vmovdqa64 0x4340(%rsp), %zmm0
kmovw 0x30be(%rsp), %k1
vpcompressd %zmm1, %zmm0 {%k1}
vmovdqa64 %zmm0, 0x440(%rsp)
movq 0x638(%rsp), %rdx
movslq 0x37c(%rsp), %rax
movq %rax, %rcx
addq %rcx, %rcx
subq %rcx, %rdx
movb %al, %cl
movl $0x1, %eax
movl %eax, %edi
shll %cl, %edi
movl %edi, %ecx
decl %ecx
vmovdqa64 0x440(%rsp), %zmm0
movq %rdx, 0x3230(%rsp)
movw %cx, 0x322e(%rsp)
vmovdqa64 %zmm0, 0x31c0(%rsp)
movq 0x3230(%rsp), %rcx
vmovdqa64 0x31c0(%rsp), %zmm0
kmovw 0x322e(%rsp), %k1
vpmovdw %zmm0, (%rcx) {%k1}
movslq 0x37c(%rsp), %rdx
movq 0x638(%rsp), %rcx
addq %rdx, %rdx
subq %rdx, %rcx
movq %rcx, 0x638(%rsp)
movq 0x638(%rsp), %rdx
movslq 0x4f8(%rsp), %rcx
movq %rcx, %rdi
addq %rdi, %rdi
subq %rdi, %rdx
movq %rdx, 0x20(%rsp)
shll %cl, %eax
movq 0x20(%rsp), %rcx
decl %eax
vmovdqa64 0x480(%rsp), %zmm0
movq %rcx, 0x31b8(%rsp)
movw %ax, 0x31b6(%rsp)
vmovdqa64 %zmm0, 0x3140(%rsp)
movq 0x31b8(%rsp), %rax
vmovdqa64 0x3140(%rsp), %zmm0
kmovw 0x31b6(%rsp), %k1
vpmovdw %zmm0, (%rax) {%k1}
movslq 0x4f8(%rsp), %rcx
movq 0x638(%rsp), %rax
addq %rcx, %rcx
subq %rcx, %rax
movq %rax, 0x638(%rsp)
vmovdqa64 0x5c0(%rsp), %zmm0
leaq 0xef0(%rsp), %rdi
movq %rdi, 0x28(%rsp)
callq 0xa9240
movq 0x28(%rsp), %rdi
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x300(%rsp)
vmovdqa64 0x580(%rsp), %zmm0
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x2c0(%rsp)
vmovdqa64 0x680(%rsp), %zmm0
movw 0x4fe(%rsp), %ax
vmovdqa64 %zmm0, 0x33c0(%rsp)
movw %ax, 0x33be(%rsp)
vmovdqa64 %zmm0, 0x3340(%rsp)
movl $0x10, 0x333c(%rsp)
vmovdqa64 0x3340(%rsp), %zmm0
movl 0x333c(%rsp), %eax
kmovw 0x33be(%rsp), %k1
vmovdqa64 %zmm0, 0x3c40(%rsp)
movl %eax, 0x3c3c(%rsp)
vmovdqa64 0x3c40(%rsp), %zmm1
vmovd 0x3c3c(%rsp), %xmm2
vmovdqa64 0x33c0(%rsp), %zmm0
vpsrld %xmm2, %zmm1, %zmm0 {%k1}
vmovdqa64 %zmm0, 0x680(%rsp)
vmovdqa64 0x640(%rsp), %zmm0
movw 0x43e(%rsp), %ax
vmovdqa64 %zmm0, 0x32c0(%rsp)
movw %ax, 0x32be(%rsp)
vmovdqa64 %zmm0, 0x3240(%rsp)
movl $0x10, 0x323c(%rsp)
vmovdqa64 0x3240(%rsp), %zmm0
movl 0x323c(%rsp), %eax
kmovw 0x32be(%rsp), %k1
vmovdqa64 %zmm0, 0x3cc0(%rsp)
movl %eax, 0x3cbc(%rsp)
vmovdqa64 0x3cc0(%rsp), %zmm1
vmovd 0x3cbc(%rsp), %xmm2
vmovdqa64 0x32c0(%rsp), %zmm0
vpsrld %xmm2, %zmm1, %zmm0 {%k1}
vmovdqa64 %zmm0, 0x640(%rsp)
vmovdqa64 0x680(%rsp), %zmm0
vmovdqa64 %zmm0, 0x38c0(%rsp)
movl $0x20, 0x38bc(%rsp)
vmovdqa64 0x38c0(%rsp), %zmm0
vmovd 0x38bc(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm1
vmovdqa64 0x300(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3840(%rsp)
movl $0x20, 0x383c(%rsp)
vmovdqa64 0x3840(%rsp), %zmm0
vmovd 0x383c(%rsp), %xmm2
vpsrlq %xmm2, %zmm0, %zmm0
vmovdqa64 %zmm1, 0x35c0(%rsp)
vmovdqa64 %zmm0, 0x3580(%rsp)
vmovdqa64 0x35c0(%rsp), %zmm0
vmovdqa64 0x3580(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x280(%rsp)
vmovdqa64 0x640(%rsp), %zmm0
vmovdqa64 %zmm0, 0x37c0(%rsp)
movl $0x20, 0x37bc(%rsp)
vmovdqa64 0x37c0(%rsp), %zmm0
vmovd 0x37bc(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm1
vmovdqa64 0x2c0(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3740(%rsp)
movl $0x20, 0x373c(%rsp)
vmovdqa64 0x3740(%rsp), %zmm0
vmovd 0x373c(%rsp), %xmm2
vpsrlq %xmm2, %zmm0, %zmm0
vmovdqa64 %zmm1, 0x3540(%rsp)
vmovdqa64 %zmm0, 0x3500(%rsp)
vmovdqa64 0x3540(%rsp), %zmm0
vmovdqa64 0x3500(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x240(%rsp)
vmovdqa64 0x680(%rsp), %zmm1
vmovdqa64 0x300(%rsp), %zmm0
vmovdqa64 %zmm1, 0x34c0(%rsp)
vmovdqa64 %zmm0, 0x3480(%rsp)
vmovdqa64 0x34c0(%rsp), %zmm0
vmovdqa64 0x3480(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x36c0(%rsp)
movl $0x20, 0x36bc(%rsp)
vmovdqa64 0x36c0(%rsp), %zmm0
vmovd 0x36bc(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x200(%rsp)
vmovdqa64 0x640(%rsp), %zmm1
vmovdqa64 0x2c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3440(%rsp)
vmovdqa64 %zmm0, 0x3400(%rsp)
vmovdqa64 0x3440(%rsp), %zmm0
vmovdqa64 0x3400(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x3640(%rsp)
movl $0x20, 0x363c(%rsp)
vmovdqa64 0x3640(%rsp), %zmm0
vmovd 0x363c(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x1c0(%rsp)
vmovdqa64 0x280(%rsp), %zmm1
movabsq $-0x100000000, %rax     # imm = 0xFFFFFFFF00000000
movq %rax, 0x3af8(%rsp)
vpbroadcastq 0x3af8(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3a80(%rsp)
vmovdqa64 0x3a80(%rsp), %zmm0
vmovdqa64 %zmm1, 0x39c0(%rsp)
vmovdqa64 %zmm0, 0x3980(%rsp)
vmovdqa64 0x39c0(%rsp), %zmm0
vmovdqa64 0x3980(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x280(%rsp)
vmovdqa64 0x240(%rsp), %zmm1
movq %rax, 0x3a78(%rsp)
vpbroadcastq 0x3a78(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3a00(%rsp)
vmovdqa64 0x3a00(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3940(%rsp)
vmovdqa64 %zmm0, 0x3900(%rsp)
vmovdqa64 0x3940(%rsp), %zmm0
vmovdqa64 0x3900(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x240(%rsp)
vmovdqa64 0x200(%rsp), %zmm1
vmovdqa64 0x280(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3bc0(%rsp)
vmovdqa64 %zmm0, 0x3b80(%rsp)
vmovdqa64 0x3bc0(%rsp), %zmm0
vmovdqa64 0x3b80(%rsp), %zmm1
vporq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x300(%rsp)
vmovdqa64 0x1c0(%rsp), %zmm1
vmovdqa64 0x240(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3b40(%rsp)
vmovdqa64 %zmm0, 0x3b00(%rsp)
vmovdqa64 0x3b40(%rsp), %zmm0
vmovdqa64 0x3b00(%rsp), %zmm1
vporq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x2c0(%rsp)
vmovdqa64 0x5c0(%rsp), %zmm0
leaq 0x6f0(%rsp), %rdi
movq %rdi, 0x30(%rsp)
callq 0xa9240
movq 0x30(%rsp), %rdi
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x180(%rsp)
vmovdqa64 0x580(%rsp), %zmm0
callq 0xa9240
vmovdqa64 %zmm0, 0x140(%rsp)
vmovdqa64 0x3c0(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3dc0(%rsp)
movl $0x10, 0x3dbc(%rsp)
vmovdqa64 0x3dc0(%rsp), %zmm0
vmovd 0x3dbc(%rsp), %xmm1
vpsrld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x100(%rsp)
vmovdqa64 0x380(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3d40(%rsp)
movl $0x10, 0x3d3c(%rsp)
vmovdqa64 0x3d40(%rsp), %zmm0
vmovd 0x3d3c(%rsp), %xmm1
vpsrld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xc0(%rsp)
vmovdqa64 0x300(%rsp), %zmm1
vmovdqa64 0x100(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3ec0(%rsp)
vmovdqa64 %zmm0, 0x3e80(%rsp)
vmovdqa64 0x3ec0(%rsp), %zmm0
vmovdqa64 0x3e80(%rsp), %zmm1
vpsrlvd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x80(%rsp)
vmovdqa64 0x2c0(%rsp), %zmm1
vmovdqa64 0xc0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3e40(%rsp)
vmovdqa64 %zmm0, 0x3e00(%rsp)
vmovdqa64 0x3e40(%rsp), %zmm0
vmovdqa64 0x3e00(%rsp), %zmm1
vpsrlvd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x40(%rsp)
vmovdqa64 0x80(%rsp), %zmm1
vmovdqa64 0x3c0(%rsp), %zmm2
movl $0xffff, 0x2f3c(%rsp) # imm = 0xFFFF
vpbroadcastd 0x2f3c(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2ec0(%rsp)
vmovdqa64 0x2ec0(%rsp), %zmm0
vmovdqa64 %zmm2, 0x2d00(%rsp)
vmovdqa64 %zmm0, 0x2cc0(%rsp)
vmovdqa64 0x2d00(%rsp), %zmm0
vmovdqa64 0x2cc0(%rsp), %zmm2
vpandq %zmm2, %zmm0, %zmm0
vmovdqa64 %zmm1, 0x3fc0(%rsp)
vmovdqa64 %zmm0, 0x3f80(%rsp)
vmovdqa64 0x3fc0(%rsp), %zmm0
vmovdqa64 0x3f80(%rsp), %zmm1
vpmulld %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x80(%rsp)
vmovdqa64 0x80(%rsp), %zmm1
vmovdqa64 0x180(%rsp), %zmm0
vmovdqa64 %zmm1, 0x41c0(%rsp)
vmovdqa64 %zmm0, 0x4180(%rsp)
vmovdqa64 0x41c0(%rsp), %zmm0
vmovdqa64 0x4180(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x80(%rsp)
vmovdqa64 0x680(%rsp), %zmm1
vmovdqa64 0x80(%rsp), %zmm0
vmovdqa64 %zmm1, 0x4140(%rsp)
vmovdqa64 %zmm0, 0x4100(%rsp)
vmovdqa64 0x4140(%rsp), %zmm0
vmovdqa64 0x4100(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x680(%rsp)
vmovdqa64 0x40(%rsp), %zmm1
vmovdqa64 0x380(%rsp), %zmm2
movl $0xffff, 0x2ebc(%rsp) # imm = 0xFFFF
vpbroadcastd 0x2ebc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2e40(%rsp)
vmovdqa64 0x2e40(%rsp), %zmm0
vmovdqa64 %zmm2, 0x2c80(%rsp)
vmovdqa64 %zmm0, 0x2c40(%rsp)
vmovdqa64 0x2c80(%rsp), %zmm0
vpandq 0x2c40(%rsp), %zmm0, %zmm0
vmovdqa64 %zmm1, 0x3f40(%rsp)
vmovdqa64 %zmm0, 0x3f00(%rsp)
vmovdqa64 0x3f40(%rsp), %zmm0
vmovdqa64 0x3f00(%rsp), %zmm1
vpmulld %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x40(%rsp)
vmovdqa64 0x40(%rsp), %zmm1
vmovdqa64 0x140(%rsp), %zmm0
vmovdqa64 %zmm1, 0x40c0(%rsp)
vmovdqa64 %zmm0, 0x4080(%rsp)
vmovdqa64 0x40c0(%rsp), %zmm0
vmovdqa64 0x4080(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x40(%rsp)
vmovdqa64 0x640(%rsp), %zmm1
vmovdqa64 0x40(%rsp), %zmm0
vmovdqa64 %zmm1, 0x4040(%rsp)
vmovdqa64 %zmm0, 0x4000(%rsp)
vmovdqa64 0x4040(%rsp), %zmm0
vmovdqa64 0x4000(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x640(%rsp)
movl 0x170c(%rsp), %eax
subl $0x20, %eax
movl %eax, 0x170c(%rsp)
jmp 0xa793f
movq 0x638(%rsp), %rax
movq %rax, 0x1b38(%rsp)
leaq 0x1b40(%rsp), %rax
vmovdqa64 0x680(%rsp), %zmm0
movq %rax, 0x42f8(%rsp)
vmovdqa64 %zmm0, 0x4280(%rsp)
vmovdqa64 0x4280(%rsp), %zmm0
movq 0x42f8(%rsp), %rax
vmovdqa64 %zmm0, (%rax)
leaq 0x1b40(%rsp), %rax
addq $0x40, %rax
vmovdqa64 0x640(%rsp), %zmm0
movq %rax, 0x4278(%rsp)
vmovdqa64 %zmm0, 0x4200(%rsp)
vmovdqa64 0x4200(%rsp), %zmm0
movq 0x4278(%rsp), %rax
vmovdqa64 %zmm0, (%rax)
movl $0x1f, 0x16fc(%rsp)
cmpl $0x0, 0x16fc(%rsp)
jl 0xa8773
movslq 0x16fc(%rsp), %rax
leaq 0x1b40(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
leaq 0x1b38(%rsp), %rsi
vzeroupper
callq 0xa9760
movl 0x16fc(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x16fc(%rsp)
jmp 0xa872f
jmp 0xa8775
movq 0x2bc0(%rsp), %rax
movq 0x1b38(%rsp), %rcx
subq %rcx, %rax
movslq 0x1704(%rsp), %rcx
addq %rcx, %rax
movl %eax, %ecx
movq 0x2bd0(%rsp), %rax
movl %ecx, (%rax)
movq 0x2bd8(%rsp), %rdi
movslq 0x1704(%rsp), %rax
addq %rax, %rdi
movq 0x1b38(%rsp), %rsi
movq 0x2bc0(%rsp), %rdx
movq 0x1b38(%rsp), %rax
subq %rax, %rdx
vzeroupper
callq 0x4810
movq 0x2bd8(%rsp), %rax
movq %rax, 0x2bf0(%rsp)
movq 0x2bf0(%rsp), %rax
movq %rbp, %rsp
popq %rbp
retq
nopw %cs:(%rax,%rax)