// File: /workspace/github_c_makefile_star2_O3/ughman[P]c2c/src/emu.c
// Function: EMU_Write16
void EMU_Write16(uint32_t address,uint16_t value)
{
	if (address & 1)
		SDL_LogError(LOG_EMU,"Unaligned halfword store");
	if (address >= 0x80000000 && address <= 0x801FFFFF)
	{
normal:
		{
			uint32_t (*codehandler)(uint32_t) = EMU_codemap[(address & 0x1FFFFF) >> 2];
			if (codehandler != EMU_ExecuteUnrecognizedCode)
			{
				SDL_LogError(LOG_EMU,"Writing over code");
			}
		}
		uint32_t *word = &EMU_ram[(address & 0x1FFFFF) >> 2];
		*word &= ~(0xFFFF << (address & 2) * 8);
		*word |= value << (address & 2) * 8;
	}
	else if (address >= 0x0 && address <= 0x1FFFFF)
	{
		goto normal;
	}
	else if (address >= 0xA0000000 && address <= 0xA01FFFFF)
	{
		goto normal;
	}
	else if (address >= 0x1F800000 && address <= 0x1F8003FF)
	{
		uint32_t *word = &EMU_scratch[(address & 0x3FF) >> 2];
		*word &= ~(0xFFFF << (address & 2) * 8);
		*word |= value << (address & 2) * 8;
	}
	else switch (address)
	{
	case 0x1F80104A:
		PAD_SetControl(value);
		break;
	case 0x1F801070:
		IRQ_AcknowledgeBits(value);
		break;
	case 0x1F801074:
		IRQ_SetMask(value);
		break;
	case 0x1F801124:
		RCNT_SetMode(RCNT_SYSDIV8,value);
		break;
	case 0x1F801128:
		RCNT_SetTarget(RCNT_SYSDIV8,value);
		break;
	CASE_SPU_IO_PORT(0x0):
		SPU_Voice_SetVolumeLeft((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0x2):
		SPU_Voice_SetVolumeRight((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0x4):
		SPU_Voice_SetSampleRate((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0x6):
		SPU_Voice_SetStartAddress((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0x8):
		SPU_Voice_SetADSRLow((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0xA):
		SPU_Voice_SetADSRHigh((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0xC):
		SPU_Voice_SetADSRVolume((address & 0x1F0) >> 4,value);
		break;
	CASE_SPU_IO_PORT(0xE):
		SPU_Voice_SetLoopAddress((address & 0x1F0) >> 4,value);
		break;
	case 0x1F801D80:
		SPU_SetVolumeLeft(value);
		break;
	case 0x1F801D82:
		SPU_SetVolumeRight(value);
		break;
	case 0x1F801D84:
		SPU_SetReverbVolumeLeft(value);
		break;
	case 0x1F801D86:
		SPU_SetReverbVolumeRight(value);
		break;
	case 0x1F801D88:
		SPU_NoteOnLow(value);
		break;
	case 0x1F801D8A:
		SPU_NoteOnHigh(value);
		break;
	case 0x1F801D8C:
		SPU_NoteOffLow(value);
		break;
	case 0x1F801D8E:
		SPU_NoteOffHigh(value);
		break;
	case 0x1F801D90:
		SPU_SetFMLow(value);
		break;
	case 0x1F801D92:
		SPU_SetFMHigh(value);
		break;
	case 0x1F801D94:
		SPU_SetNoiseLow(value);
		break;
	case 0x1F801D96:
		SPU_SetNoiseHigh(value);
		break;
	case 0x1F801D98:
		SPU_SetReverbLow(value);
		break;
	case 0x1F801D9A:
		SPU_SetReverbHigh(value);
		break;
	case 0x1F801D9C:
	case 0x1F801D9E:
		// nonsense write to read-only registers
		PCSX_Write16(address,value);
		break;
	case 0x1F801DA2:
		SPU_SetReverbStartAddress(value);
		break;
	case 0x1F801DA6:
		SPU_SetTransferAddress(value);
		break;
	case 0x1F801DA8:
		SPU_Write(value);
		break;
	case 0x1F801DAA:
		SPU_WriteControlRegister(value);
		break;
	case 0x1F801DAC:
		SPU_SetTransferMode(value);
		break;
	case 0x1F801DB0:
		SPU_SetCDVolumeLeft(value);
		break;
	case 0x1F801DB2:
		SPU_SetCDVolumeRight(value);
		break;
	case 0x1F801DB4:
		SPU_SetExternVolumeLeft(value);
		break;
	case 0x1F801DB6:
		SPU_SetExternVolumeRight(value);
		break;
	case 0x1F801DC0:
	case 0x1F801DC2:
	case 0x1F801DC4:
	case 0x1F801DC6:
	case 0x1F801DC8:
	case 0x1F801DCA:
	case 0x1F801DCC:
	case 0x1F801DCE:
	case 0x1F801DD0:
	case 0x1F801DD2:
	case 0x1F801DD4:
	case 0x1F801DD6:
	case 0x1F801DD8:
	case 0x1F801DDA:
	case 0x1F801DDC:
	case 0x1F801DDE:
	case 0x1F801DE0:
	case 0x1F801DE2:
	case 0x1F801DE4:
	case 0x1F801DE6:
	case 0x1F801DE8:
	case 0x1F801DEA:
	case 0x1F801DEC:
	case 0x1F801DEE:
	case 0x1F801DF0:
	case 0x1F801DF2:
	case 0x1F801DF4:
	case 0x1F801DF6:
	case 0x1F801DF8:
	case 0x1F801DFA:
	case 0x1F801DFC:
	case 0x1F801DFE:
		SPU_ConfigureReverb((address - 0x1F801DC0) / 2,value);
		break;
	default:
		SDL_LogError(LOG_EMU,"Unrecognized 16-bit write address %.8X",address);
		PCSX_Write16(address,value);
		break;
	}
}

// Assembly:
pushq %r15
pushq %r14
pushq %rbx
movl %esi, %ebx
movl %edi, %r14d
testb $0x1, %r14b
je 0x1726fe
leaq 0x4d96(%rip), %rsi      # 0x177488
movl $0x13, %edi
xorl %eax, %eax
callq 0x10d0
testl $0x7fe00000, %r14d      # imm = 0x7FE00000
setne %al
movl %r14d, %ecx
andl $0xffe00000, %ecx       # imm = 0xFFE00000
cmpl $0xa0000000, %ecx       # imm = 0xA0000000
setne %cl
testb %cl, %al
jne 0x17277f
movl %r14d, %r15d
shrl $0x2, %r15d
andl $0x7ffff, %r15d         # imm = 0x7FFFF
leaq 0x8c2d(%rip), %rax      # 0x17b360
leaq -0x762(%rip), %rcx      # 0x171fd8
cmpq %rcx, (%rax,%r15,8)
je 0x172753
leaq 0x4d09(%rip), %rsi      # 0x177450
movl $0x13, %edi
xorl %eax, %eax
callq 0x10d0
shll $0x3, %r14d
andb $0x10, %r14b
movl $0xffff, %eax           # imm = 0xFFFF
movl %r14d, %ecx
shll %cl, %eax
movq 0x408bf4(%rip), %rdx    # 0x57b360
notl %eax
movzwl %bx, %esi
shll %cl, %esi
andl (%rdx,%r15,4), %eax
orl %eax, %esi
movl %esi, (%rdx,%r15,4)
jmp 0x1727be
movl %r14d, %eax
andl $0xfffffc00, %eax       # imm = 0xFFFFFC00
cmpl $0x1f800000, %eax       # imm = 0x1F800000
jne 0x1727c4
movl %r14d, %eax
shll $0x3, %r14d
andb $0x10, %r14b
movl $0xffff, %edx           # imm = 0xFFFF
movl %r14d, %ecx
shll %cl, %edx
movq 0x408bbe(%rip), %rsi    # 0x57b368
andl $0x3fc, %eax            # imm = 0x3FC
notl %edx
movzwl %bx, %edi
shll %cl, %edi
andl (%rsi,%rax), %edx
orl %edx, %edi
movl %edi, (%rsi,%rax)
popq %rbx
popq %r14
popq %r15
retq
cmpl $0x1f801123, %r14d      # imm = 0x1F801123
jle 0x1728cd
leal -0x1f801c00(%r14), %eax
cmpl $0x1fe, %eax            # imm = 0x1FE
ja 0x1728f5
leaq 0x435e(%rip), %rcx      # 0x176b48
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
addl $0xe07fe240, %r14d      # imm = 0xE07FE240
shrl %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1735e3
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173403
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173367
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173340
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1733dc
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1732f2
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1733b5
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17338e
shrl $0x4, %r14d
andl $0x1f, %r14d
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173319
cmpl $0x1f80104a, %r14d      # imm = 0x1F80104A
je 0x17292a
cmpl $0x1f801070, %r14d      # imm = 0x1F801070
je 0x17291d
cmpl $0x1f801074, %r14d      # imm = 0x1F801074
jne 0x172937
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x171233
cmpl $0x1f801124, %r14d      # imm = 0x1F801124
je 0x172a8f
cmpl $0x1f801128, %r14d      # imm = 0x1F801128
jne 0x172937
movzwl %bx, %esi
movl $0x2, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1712b3
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x171212
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x127b
leaq 0x4b63(%rip), %rsi      # 0x1774a1
movl $0x13, %edi
movl %r14d, %edx
xorl %eax, %eax
callq 0x10d0
leaq 0x894c(%rip), %rax      # 0x17b2a0
movq (%rax), %rax
movzwl %bx, %esi
movl %r14d, %edi
popq %rbx
popq %r14
popq %r15
jmpq *%rax
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1734f2
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17342b
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1735b4
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1732cd
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173526
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1734be
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1734df
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173464
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173294
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17343e
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17357b
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173477
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173547
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1732a7
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173513
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1735a1
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173418
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17358e
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17349d
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17348a
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x173451
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x1732ba
movzwl %bx, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17355a
movzwl %bx, %esi
movl $0x2, %edi
popq %rbx
popq %r14
popq %r15
jmp 0x17129e