// File: /workspace/github_c_makefile_star2_O0/Ihsoh[P]ilang/compiler/assembler/ins_enc.c
// Function: ins_enc_opcode_rXX
void ins_enc_opcode_rXX(
	Instruction *ins,
	InstructionEncoderData *data
) {
	_CHECK_PARAMS(1);

	ParserASTNode *ins_node = data->ins_node;

	ParserASTNode *target = data->ins_node->childs[0];

	EncoderInstruction enc_ins;

	ins_init(data->ctx, ins, ins_node, &enc_ins);

	int arch = ASM_PARSER_CONTEXT_DATA_GET_ARCH(data->ctx);

	InsRegister *target_reg = ASM_REG_AST_NODE_GET_REG(target);

	switch (arch) {
		case ASM_ARCH_BIT16: {
			switch (target_reg->type) {
				case INS_REGISTER_GENERAL_2BYTE: {
					// 无需操作数大小前缀。
					break;
				}
				case INS_REGISTER_GENERAL_4BYTE: {
					enc_ins.legacy_prefix.operand_size_override = true;
					break;
				}
				case INS_REGISTER_GENERAL_8BYTE: {
					data->ctx->syntax_error_node_msg(
						data->ctx,
						ins_node,
						"instruction not supported in 16-bit mode."
					);
					break;
				}
				default: {
					assert(0);
					break;
				}
			}
			break;
		}
		case ASM_ARCH_BIT32: {
			switch (target_reg->type) {
				case INS_REGISTER_GENERAL_2BYTE: {
					enc_ins.legacy_prefix.operand_size_override = true;
					break;
				}
				case INS_REGISTER_GENERAL_4BYTE: {
					// 无需操作数大小前缀。
					break;
				}
				case INS_REGISTER_GENERAL_8BYTE: {
					data->ctx->syntax_error_node_msg(
						data->ctx,
						ins_node,
						"instruction not supported in 32-bit mode."
					);
					break;
				}
				default: {
					assert(0);
					break;
				}
			}
			break;
		}
		case ASM_ARCH_BIT64: {
			switch (target_reg->type) {
				case INS_REGISTER_GENERAL_2BYTE: {
					enc_ins.legacy_prefix.operand_size_override = true;
					break;
				}
				case INS_REGISTER_GENERAL_4BYTE: {
					data->ctx->syntax_error_node_msg(
						data->ctx,
						ins_node,
						"instruction not supported in 64-bit mode."
					);
					break;
				}
				case INS_REGISTER_GENERAL_8BYTE: {
					// 无需操作数大小前缀。
					break;
				}
				default: {
					assert(0);
					break;
				}
			}
			break;
		}
		default: {
			assert(0);
			break;
		}
	}

	_output(data, &enc_ins);
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0xa0, %rsp
movq %rdi, -0x8(%rbp)
movq %rsi, -0x10(%rbp)
cmpq $0x0, -0x8(%rbp)
je 0x1f4dc
jmp 0x1f4fb
leaq 0x2a623(%rip), %rdi     # 0x49b06
leaq 0x2bb36(%rip), %rsi     # 0x4b020
movl $0x16e, %edx            # imm = 0x16E
leaq 0x2be27(%rip), %rcx     # 0x4b31d
callq 0xa0b0
cmpq $0x0, -0x10(%rbp)
je 0x1f504
jmp 0x1f523
leaq 0x30ae4(%rip), %rdi     # 0x4ffef
leaq 0x2bb0e(%rip), %rsi     # 0x4b020
movl $0x16e, %edx            # imm = 0x16E
leaq 0x2bdff(%rip), %rcx     # 0x4b31d
callq 0xa0b0
movq -0x10(%rbp), %rax
cmpq $0x0, (%rax)
je 0x1f52f
jmp 0x1f54e
leaq 0x2bb47(%rip), %rdi     # 0x4b07d
leaq 0x2bae3(%rip), %rsi     # 0x4b020
movl $0x16e, %edx            # imm = 0x16E
leaq 0x2bdd4(%rip), %rcx     # 0x4b31d
callq 0xa0b0
movq -0x10(%rbp), %rax
movq (%rax), %rax
cmpl $0x1, 0x44(%rax)
jne 0x1f55d
jmp 0x1f57c
leaq 0x2bd9a(%rip), %rdi     # 0x4b2fe
leaq 0x2bab5(%rip), %rsi     # 0x4b020
movl $0x16e, %edx            # imm = 0x16E
leaq 0x2bda6(%rip), %rcx     # 0x4b31d
callq 0xa0b0
movq -0x10(%rbp), %rax
movq (%rax), %rax
movq %rax, -0x18(%rbp)
movq -0x10(%rbp), %rax
movq (%rax), %rax
movq 0x48(%rax), %rax
movq (%rax), %rax
movq %rax, -0x20(%rbp)
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rdi
movq -0x8(%rbp), %rsi
movq -0x18(%rbp), %rdx
leaq -0x80(%rbp), %rcx
callq 0x1a9e0
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movl 0xb0(%rax), %eax
movl %eax, -0x84(%rbp)
movq -0x20(%rbp), %rax
movq 0x60(%rax), %rax
movq %rax, -0x90(%rbp)
movl -0x84(%rbp), %eax
movl %eax, -0x94(%rbp)
subl $0x1, %eax
je 0x1f60d
jmp 0x1f5e8
movl -0x94(%rbp), %eax
subl $0x2, %eax
je 0x1f68d
jmp 0x1f5f9
movl -0x94(%rbp), %eax
subl $0x4, %eax
je 0x1f70d
jmp 0x1f78a
movq -0x90(%rbp), %rax
movl 0xc(%rax), %eax
movl %eax, -0x98(%rbp)
subl $0x3, %eax
je 0x1f63e
jmp 0x1f624
movl -0x98(%rbp), %eax
subl $0x4, %eax
je 0x1f640
jmp 0x1f631
movl -0x98(%rbp), %eax
subl $0x5, %eax
je 0x1f646
jmp 0x1f669
jmp 0x1f688
movb $0x1, -0x75(%rbp)
jmp 0x1f688
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2bbc7(%rip), %rdx     # 0x4b22c
callq *%rax
jmp 0x1f688
leaq 0x27df5(%rip), %rdi     # 0x47465
leaq 0x2b9a9(%rip), %rsi     # 0x4b020
movl $0x190, %edx            # imm = 0x190
leaq 0x2bc9a(%rip), %rcx     # 0x4b31d
callq 0xa0b0
jmp 0x1f7a9
movq -0x90(%rbp), %rax
movl 0xc(%rax), %eax
movl %eax, -0x9c(%rbp)
subl $0x3, %eax
je 0x1f6be
jmp 0x1f6a4
movl -0x9c(%rbp), %eax
subl $0x4, %eax
je 0x1f6c4
jmp 0x1f6b1
movl -0x9c(%rbp), %eax
subl $0x5, %eax
je 0x1f6c6
jmp 0x1f6e9
movb $0x1, -0x75(%rbp)
jmp 0x1f708
jmp 0x1f708
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2bb71(%rip), %rdx     # 0x4b256
callq *%rax
jmp 0x1f708
leaq 0x27d75(%rip), %rdi     # 0x47465
leaq 0x2b929(%rip), %rsi     # 0x4b020
movl $0x1a9, %edx            # imm = 0x1A9
leaq 0x2bc1a(%rip), %rcx     # 0x4b31d
callq 0xa0b0
jmp 0x1f7a9
movq -0x90(%rbp), %rax
movl 0xc(%rax), %eax
movl %eax, -0xa0(%rbp)
subl $0x3, %eax
je 0x1f73e
jmp 0x1f724
movl -0xa0(%rbp), %eax
subl $0x4, %eax
je 0x1f744
jmp 0x1f731
movl -0xa0(%rbp), %eax
subl $0x5, %eax
je 0x1f767
jmp 0x1f769
movb $0x1, -0x75(%rbp)
jmp 0x1f788
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2bbfb(%rip), %rdx     # 0x4b35e
callq *%rax
jmp 0x1f788
jmp 0x1f788
leaq 0x27cf5(%rip), %rdi     # 0x47465
leaq 0x2b8a9(%rip), %rsi     # 0x4b020
movl $0x1c2, %edx            # imm = 0x1C2
leaq 0x2bb9a(%rip), %rcx     # 0x4b31d
callq 0xa0b0
jmp 0x1f7a9
leaq 0x27cd4(%rip), %rdi     # 0x47465
leaq 0x2b888(%rip), %rsi     # 0x4b020
movl $0x1c9, %edx            # imm = 0x1C9
leaq 0x2bb79(%rip), %rcx     # 0x4b31d
callq 0xa0b0
movq -0x10(%rbp), %rdi
leaq -0x80(%rbp), %rsi
callq 0x1e570
addq $0xa0, %rsp
popq %rbp
retq
nop