// File: /workspace/github_cpp_makefile_star2_O2/SYZYGYfpga[P]syzygy-tools/smartvio/syzygy.c
// Function: szgParsePortDNA
int
szgParsePortDNA(int n, szgSmartVIOConfig *svio, unsigned char *dnaBuf, int length)
{
	int i;
	int vmin, vmax;
	unsigned int offset;


	// Bounds check for input buffer.
	if (length < SZG_DNA_HEADER_LENGTH_V1) {
		return(-1);
	}

	// Validate the DNA CRC.
	if (0 != szgComputeCRC(dnaBuf, SZG_DNA_HEADER_LENGTH_V1)) {
		return(-1);
	}

	svio->ports[n].present = 1;
	svio->ports[n].req_ver_major = dnaBuf[SZG_DNA_PTR_DNA_REQUIRED_MAJOR];
	svio->ports[n].req_ver_minor = dnaBuf[SZG_DNA_PTR_DNA_REQUIRED_MINOR];
	svio->ports[n].attr = (dnaBuf[SZG_DNA_PTR_ATTRIBUTES + 1] << 8) | (dnaBuf[SZG_DNA_PTR_ATTRIBUTES]);
	for (i=0; i<SZG_MAX_DNA_RANGES; i++) {
		vmin = (dnaBuf[SZG_DNA_MIN_VIO_RANGE0 + i*4 + 1] << 8) | (dnaBuf[SZG_DNA_MIN_VIO_RANGE0 + i*4]);
		vmax = (dnaBuf[SZG_DNA_MAX_VIO_RANGE0 + i*4 + 1] << 8) | (dnaBuf[SZG_DNA_MAX_VIO_RANGE0 + i*4]);
		if ((vmin == 0) && (vmin == 0)) {
			break;
		} else {
			svio->ports[n].ranges[i].min = vmin;
			svio->ports[n].ranges[i].max = vmax;
			svio->ports[n].range_count++;
		}
	}

	// If the DOUBLEWIDE attribute is set, we need to add the mating group to the dependents.
	// We also need to create the reciprocal relationship so that the mating group includes
	// the present port.
	if (svio->ports[n].attr & SZG_ATTR_DOUBLEWIDE) {
		svio->group_masks[svio->ports[n].group] |= (1 << svio->ports[n].doublewide_mate);
		svio->group_masks[svio->ports[n].doublewide_mate] |= (1 << svio->ports[n].group);
	}

	offset = SZG_DNA_HEADER_LENGTH_V1;
	svio->ports[n].mfr_offset = offset;
	svio->ports[n].mfr_length = dnaBuf[SZG_DNA_MANUFACTURER_NAME_LENGTH];

	offset += svio->ports[n].mfr_length;
	svio->ports[n].product_name_offset = offset;
	svio->ports[n].product_name_length = dnaBuf[SZG_DNA_PRODUCT_NAME_LENGTH];

	offset += svio->ports[n].product_name_length;
	svio->ports[n].product_model_offset = offset;
	svio->ports[n].product_model_length = dnaBuf[SZG_DNA_PRODUCT_MODEL_LENGTH];

	offset += svio->ports[n].product_model_length;
	svio->ports[n].product_version_offset = offset;
	svio->ports[n].product_version_length = dnaBuf[SZG_DNA_PRODUCT_VERSION_LENGTH];

	offset += svio->ports[n].product_version_length;
	svio->ports[n].serial_number_offset = offset;
	svio->ports[n].serial_number_length = dnaBuf[SZG_DNA_SERIAL_NUMBER_LENGTH];

	return(0);
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
pushq $-0x1
popq %rbp
cmpl $0x28, %ecx
jl 0x7c87
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %r15d
pushq $0x28
popq %rsi
movq %rdx, %rdi
callq 0x7b58
testw %ax, %ax
jne 0x7c87
movslq %r15d, %rax
imulq $0x6c, %rax, %rax
addq %r14, %rax
addq $0x20, %rax
movl $0x1, 0x4(%rax)
movzbl 0x6(%rbx), %ecx
movl %ecx, 0xc(%rax)
movzbl 0x7(%rbx), %ecx
movl %ecx, 0x10(%rax)
movzbl 0xf(%rbx), %edx
shll $0x8, %edx
movzbl 0xe(%rbx), %ecx
orl %ecx, %edx
movl %edx, 0x14(%rax)
xorl %edx, %edx
cmpq $0x4, %rdx
je 0x7c1e
movzwl 0x10(%rbx,%rdx,4), %esi
testl %esi, %esi
je 0x7c1e
movzwl 0x12(%rbx,%rdx,4), %edi
movl %esi, 0x24(%rax,%rdx,8)
movl %edi, 0x28(%rax,%rdx,8)
incl 0x20(%rax)
incq %rdx
jmp 0x7bfa
testb $0x2, %cl
je 0x7c44
movb 0x1c(%rax), %cl
pushq $0x1
popq %rdx
movl %edx, %esi
shll %cl, %esi
movslq 0x8(%rax), %rcx
orl %esi, 0x14(%r14,%rcx,4)
movb 0x8(%rax), %cl
shll %cl, %edx
movslq 0x1c(%rax), %rcx
orl %edx, 0x14(%r14,%rcx,4)
movl $0x28, 0x44(%rax)
movzbl 0x20(%rbx), %ecx
movl %ecx, 0x48(%rax)
leal 0x28(%rcx), %edx
movl %edx, 0x4c(%rax)
movzbl 0x21(%rbx), %edx
movl %edx, 0x50(%rax)
leal 0x28(%rcx,%rdx), %ecx
movl %ecx, 0x54(%rax)
movzbl 0x22(%rbx), %edx
movl %edx, 0x58(%rax)
addl %edx, %ecx
movl %ecx, 0x5c(%rax)
movzbl 0x23(%rbx), %edx
movl %edx, 0x60(%rax)
addl %edx, %ecx
movl %ecx, 0x64(%rax)
movzbl 0x24(%rbx), %ecx
movl %ecx, 0x68(%rax)
xorl %ebp, %ebp
movl %ebp, %eax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq