// File: /workspace/github_c_makefile_star2_O1/hobo0xcc[P]rve/src/cpu.c
// Function: ExecOpInstr
void ExecOpInstr(State *state, uint32_t instr) {
    uint8_t funct3 = (instr >> 12) & SetNBits(3);
    uint8_t funct7 = (instr >> 25) & SetNBits(7);

    switch (funct3) {
    case 0x0:
        if (funct7 == 0x00) {
            ExecAdd(state, instr);
        } else if (funct7 == 0x01) {
            ExecMul(state, instr);
        } else if (funct7 == 0x20) {
            ExecSub(state, instr);
        }
        break;
    case 0x1:
        if (funct7 == 0x00) {
            ExecSll(state, instr);
        } else if (funct7 == 0x01) {
            ExecMulh(state, instr);
        }
        break;
    case 0x2:
        if (funct7 == 0x00) {
            ExecSlt(state, instr);
        } else if (funct7 == 0x01) {
            ExecMulhsu(state, instr);
        }
        break;
    case 0x3:
        if (funct7 == 0x00) {
            ExecSltu(state, instr);
        } else if (funct7 == 0x01) {
            ExecMulhu(state, instr);
        }
        break;
    case 0x4:
        if (funct7 == 0x00) {
            ExecXor(state, instr);
        } else if (funct7 == 0x01) {
            ExecDiv(state, instr);
        }
        break;
    case 0x5:
        if (funct7 == 0x00) {
            ExecSrl(state, instr);
        } else if (funct7 == 0x01) {
            ExecDivu(state, instr);
        } else if (funct7 == 0x20) {
            ExecSra(state, instr);
        }
        break;
    case 0x6:
        if (funct7 == 0x00) {
            ExecOr(state, instr);
        } else if (funct7 == 0x01) {
            ExecRem(state, instr);
        }
        break;
    case 0x7:
        if (funct7 == 0x00) {
            ExecAnd(state, instr);
        } else if (funct7 == 0x01) {
            ExecRemu(state, instr);
        }
        break;
    }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
movl %esi, %ecx
shrl $0xc, %ecx
movl %esi, %eax
shrl $0x19, %eax
movl %ecx, %edx
andl $0x7, %edx
leaq 0x49cb(%rip), %r8       # 0x80b0
movslq (%r8,%rdx,4), %rdx
addq %r8, %rdx
jmpq *%rdx
cmpl $0x20, %eax
je 0x39c5
cmpl $0x1, %eax
je 0x39a1
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
movq 0x8008(%rdi,%rdx), %rdx
addq 0x8008(%rdi,%rcx), %rdx
jmp 0x3a53
cmpl $0x1, %eax
je 0x38bf
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
movq 0x8008(%rdi,%rdx), %rdx
xorq 0x8008(%rdi,%rcx), %rdx
jmp 0x3a53
cmpl $0x1, %eax
je 0x38c5
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rcx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
xorl %r8d, %r8d
cmpq 0x8008(%rdi,%rdx), %rcx
setl %r8b
jmp 0x37cd
cmpl $0x1, %eax
je 0x390a
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rcx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
xorl %r8d, %r8d
cmpq 0x8008(%rdi,%rdx), %rcx
setb %r8b
shrl $0x4, %esi
andl %eax, %esi
movq %r8, 0x8008(%rdi,%rsi)
jmp 0x3a60
cmpl $0x1, %eax
je 0x392d
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
movq 0x8008(%rdi,%rdx), %rdx
andq 0x8008(%rdi,%rcx), %rdx
jmp 0x3a53
cmpl $0x1, %eax
je 0x396f
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rdx
movl %esi, %ecx
shrl $0x11, %ecx
andl %eax, %ecx
movb 0x8008(%rdi,%rcx), %cl
shlq %cl, %rdx
jmp 0x3a53
cmpl $0x20, %eax
je 0x3a30
cmpl $0x1, %eax
je 0x39f2
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rdx
movl %esi, %ecx
shrl $0x11, %ecx
andl %eax, %ecx
movb 0x8008(%rdi,%rcx), %cl
andb $0x1f, %cl
shrq %cl, %rdx
jmp 0x3a53
cmpl $0x1, %eax
je 0x399b
testl %eax, %eax
jne 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
movq 0x8008(%rdi,%rdx), %rdx
orq 0x8008(%rdi,%rcx), %rdx
jmp 0x3a53
popq %rbp
jmp 0x3495
movl $0xf8, %r8d
andl %r8d, %ecx
movq 0x8008(%rdi,%rcx), %r9
movl %esi, %eax
shrl $0x11, %eax
andl %r8d, %eax
movq 0x8008(%rdi,%rax), %rcx
movq %rcx, %rax
mulq %r9
sarq $0x3f, %r9
imulq %rcx, %r9
addq %rdx, %r9
shrl $0x4, %esi
andl %r8d, %esi
movq %r9, 0x8008(%rdi,%rsi)
jmp 0x3a60
movl $0xf8, %r8d
andl %r8d, %ecx
movl %esi, %eax
shrl $0x11, %eax
andl %r8d, %eax
movq 0x8008(%rdi,%rax), %rax
mulq 0x8008(%rdi,%rcx)
jmp 0x3990
movl %esi, %r8d
shrl $0x7, %r8d
andl $0x1f, %r8d
shrl $0x11, %esi
movl $0xf8, %eax
andl %eax, %esi
movq 0x8008(%rdi,%rsi), %rsi
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rax
testq %rsi, %rsi
je 0x3a26
xorl %edx, %edx
divq %rsi
movq %rdx, 0x8008(%rdi,%r8,8)
jmp 0x3a60
movl $0xf8, %r8d
andl %r8d, %ecx
movl %esi, %eax
shrl $0x11, %eax
andl %r8d, %eax
movq 0x8008(%rdi,%rax), %rax
imulq 0x8008(%rdi,%rcx)
shrl $0x4, %esi
andl %r8d, %esi
jmp 0x3a58
popq %rbp
jmp 0x35f5
movl $0xf8, %eax
andl %eax, %ecx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
movq 0x8008(%rdi,%rdx), %rdx
imulq 0x8008(%rdi,%rcx), %rdx
jmp 0x3a53
movl $0xf8, %eax
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rcx
movl %esi, %edx
shrl $0x11, %edx
andl %eax, %edx
subq 0x8008(%rdi,%rdx), %rcx
shrl $0x4, %esi
andl %eax, %esi
movq %rcx, 0x8008(%rdi,%rsi)
jmp 0x3a60
movl %esi, %r8d
shrl $0x7, %r8d
andl $0x1f, %r8d
shrl $0x11, %esi
andl $0xf8, %esi
movq 0x8008(%rdi,%rsi), %rsi
testq %rsi, %rsi
je 0x3a62
andl $0xf8, %ecx
movq 0x8008(%rdi,%rcx), %rax
xorl %edx, %edx
divq %rsi
movq %rax, 0x8008(%rdi,%r8,8)
jmp 0x3a60
movl $0xf8, %eax
andl %eax, %ecx
movq 0x8008(%rdi,%rcx), %rdx
movl %esi, %ecx
shrl $0x11, %ecx
andl %eax, %ecx
movb 0x8008(%rdi,%rcx), %cl
andb $0x1f, %cl
sarq %cl, %rdx
shrl $0x4, %esi
andl %eax, %esi
movq %rdx, 0x8008(%rdi,%rsi)
popq %rbp
retq
movq $-0x1, 0x8008(%rdi,%r8,8)
jmp 0x3a60