// File: /workspace/github_c_makefile_star2_O0/Nico01[P]obj2asm/odisasm.c
// Function: mod_reg
int mod_reg( byte, text, class )
    uchar   byte;
    char            *text;
    int             class;
{
    char            *opcode;
    int             dir;
    int             size;
    int             reg_size;
    int             size_needed;
    int             type;
    int             method;
    int             group;
    dword   mod_reg;
    uchar   mod;
    uchar   r_m;
    uchar   reg;
    int             additional;
    char            mem_text[50];
    char            reg_text[50];
    char            third_text[50];
    char            operands[80];
    int             ref_mode;

    if ( get_checkc( &mod_reg ) ) {
        return( 0 );
    }

    mod = (uchar)(((int)mod_reg & 0xC0) >> 6);
    reg = (uchar)(((int)mod_reg & 0x38) >> 3);
    r_m = (uchar)(((int)mod_reg & 0x07) >> 0);

    dir         = modrm_class[class].dir;
    size        = modrm_class[class].size;
    method      = modrm_class[class].method;
    group       = modrm_class[class].group;
    size_needed = modrm_class[class].size_needed;
    type        = modrm_class[class].type;

    ref_mode = 0;

    if ( group == 6 ) {
        if ( mod == 3 ) {
            if ( reg == 0 || reg == 1 || reg == 2 || reg == 3 ) {
                addr_large = FALSE;         /* 286 only instructions */
                size_large = FALSE;
            }
        }
        type = WORD_PTR;
        size_needed = TRUE;
    }

    reg_size = size;                /* 386 Segments effect register names */
    if ( reg_size == 1 && size_large ) {
        reg_size = 2;
    }
    if ( type == UNKNOWN ) {
        type = reg_size_to_type( reg_size );
    }

    if ( group == 0 ) {
        opcode = text;
    } else {
        opcode = op_grp[group-1][reg];
    }
    if ( strlen(opcode) == 0 ) {
        return( 0 );
    }

    if ( class == 26 ) {
        reg_size = 1;
    }

    if ( byte == 0x62 || byte == 0x63 ) {
        if ( byte == 0x63 ) {
            type = WORD_PTR;
        }
        size_needed = TRUE;     /* LAR, LSL, BOUND, ARPL need size */
    }
    if ( byte == 0xC4 || byte == 0xC5
           || byte == 0xB2 || byte == 0xB4 || byte == 0xB5 ) {
        size_needed = TRUE;
    }

    if ( group == 3 ) {         /* Group 3 has a test instruction which    */
        if ( reg == 0 ) {       /* needs an immediate value (byte or word) */
            method = 5 + size;  /* the rest of group 3 needs nothing       */
            dir = 0;
            size_needed = TRUE;
        } else {
            method = 0;
            if ( reg == 2 || reg == 3 ) {
                size_needed = FALSE;
            } else {
                size_needed = TRUE;
            }
        }
    }

    if ( group == 5 ) {                 /* Group 5 has call far and jump far */
        if ( reg == 3 || reg == 5 ) {   /* instructions which are dwords     */
                                        /* the rest of group 5 is words      */
            if ( size_large ) {
                type = FWORD_PTR;
            } else {
                type = DWORD_PTR;
            }
            size_needed = TRUE;
        } else {
            if ( reg == 0 || reg == 1 ) {
                size_needed = TRUE;
            }
        }
    }

    if ( group == 7 ) {                 /* Group 7 has mostly FWORD sized    */
        if ( reg == 4 || reg == 6 ) {   /* EAs, but these two are WORD sized */
            type = WORD_PTR;
        }
    }

    if ( dir == 0 && mod == 3 && (class == 0 || class == 1) ) {
        /*
        ** Ambiguous!   eg. OBJ 20F8 = and al,bh => MASM 22C7
        ** This is because MASM prefers the first operand to be
        ** a register and the other operand to be a mem/reg.
        */
        return(0);
    }

    mem_text[0] = '\0';
    additional = do_mod_rm( mem_text, mod, r_m, type, size_needed, ref_mode );
    if ( additional == -1 ) {
        return( 0 );
    }

    switch( method ) {
        case 0:         /* No additional information (one operand only) */
            break;
        case 1:         /* Other operand is a register */
                        /* LES,LDS,BOUND,LSS,LFS,LGS, ARPL instructions */
                        /* revert to Word */
            if ( byte == 0xC4 || byte == 0xC5 || byte == 0x62 || byte == 0x63
                   || byte == 0xB2 || byte == 0xB4 || byte == 0xB5 ) {
                reg_size = 1;
            }

            strcpy( reg_text, regs[reg_size][reg] );
            break;
        case 2:         /* Other operand is a segment register */
            if ( reg > 5 ) {    /* 0=ES,1=CS,2=SS,3=DS,4=FS,5=GS */
                return( 0 );
            }
            strcpy( reg_text, sregs[reg] );
            break;
        case 3:         /* Other operand is 1 */
            strcpy( reg_text, "1" );
            break;
        case 4:         /* Other operand is register CL */
            strcpy( reg_text, "cl" );
            break;
        case 5:         /* Immediate byte value */
            if ( byte_immed(reg_text, additional,FALSE) ) {
                return( 0 );
            }
            additional++;
            break;
        case 6:         /* Immediate word value (could be fixupp) */
            if ( word_immed(reg_text, additional) ) {
                return( 0 );
            }
            if ( size_large ) {
                additional += 4;
            } else {
                additional += 2;
            }
            break;
        case 7:         /* Immediate signed byte value */
            if ( byte_immed(reg_text,additional,TRUE) ) {
                return( 0 );
            }
            additional++;
            break;
        case 8:         /* IMUL (3 operands [reg,mem,immed word]) */
            strcpy( reg_text, regs[reg_size][reg] );
            if ( word_immed(third_text, additional) ) {
                return(0);
            }
            additional += 2;
            break;
        case 9:         /* IMUL (3 operands [reg,mem,immed signed byte]) */
            strcpy( reg_text, regs[reg_size][reg] );
            if ( byte_immed(third_text, additional,TRUE) ) {
                return(0);
            }
            additional += 1;
            break;
        case 10:        /* Control Register (CR0...) */
            strcpy( reg_text, cr_regs[reg] );
            break;
        case 11:        /* Debug Register (DR0...) */
            strcpy( reg_text, dr_regs[reg] );
            break;
        case 12:
            strcpy( reg_text, tr_regs[reg] );
            break;
        case 13:
            strcpy( reg_text, regs[reg_size][reg] );
            strcpy( third_text, "cl" );
            break;
    }

    if ( dir & 0x01 ) {
        sprintf( operands, dir_fmt[dir], reg_text, mem_text, third_text );
    } else {
        sprintf( operands, dir_fmt[dir], mem_text, reg_text, third_text );
    }

    adjust_assumes();
    instr_opcode( opcode );
    instr_operand( operands );

    return( 2+additional );
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0x170, %rsp            # imm = 0x170
movb %dil, %al
movb %al, -0x5(%rbp)
movq %rsi, -0x10(%rbp)
movl %edx, -0x14(%rbp)
leaq -0x48(%rbp), %rdi
callq 0x9620
cmpl $0x0, %eax
je 0xbe12
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movq -0x48(%rbp), %rax
andl $0xc0, %eax
sarl $0x6, %eax
movb %al, -0x49(%rbp)
movq -0x48(%rbp), %rax
andl $0x38, %eax
sarl $0x3, %eax
movb %al, -0x4b(%rbp)
movq -0x48(%rbp), %rax
andl $0x7, %eax
sarl $0x0, %eax
movb %al, -0x4a(%rbp)
movslq -0x14(%rbp), %rcx
leaq 0x1085a(%rip), %rax     # 0x1c6a0
imulq $0x18, %rcx, %rcx
addq %rcx, %rax
movl (%rax), %eax
movl %eax, -0x24(%rbp)
movslq -0x14(%rbp), %rcx
leaq 0x10843(%rip), %rax     # 0x1c6a0
imulq $0x18, %rcx, %rcx
addq %rcx, %rax
movl 0x4(%rax), %eax
movl %eax, -0x28(%rbp)
movslq -0x14(%rbp), %rcx
leaq 0x1082b(%rip), %rax     # 0x1c6a0
imulq $0x18, %rcx, %rcx
addq %rcx, %rax
movl 0x8(%rax), %eax
movl %eax, -0x38(%rbp)
movslq -0x14(%rbp), %rcx
leaq 0x10813(%rip), %rax     # 0x1c6a0
imulq $0x18, %rcx, %rcx
addq %rcx, %rax
movl 0xc(%rax), %eax
movl %eax, -0x3c(%rbp)
movslq -0x14(%rbp), %rcx
leaq 0x107fb(%rip), %rax     # 0x1c6a0
imulq $0x18, %rcx, %rcx
addq %rcx, %rax
movl 0x10(%rax), %eax
movl %eax, -0x30(%rbp)
movslq -0x14(%rbp), %rcx
leaq 0x107e3(%rip), %rax     # 0x1c6a0
imulq $0x18, %rcx, %rcx
addq %rcx, %rax
movl 0x14(%rax), %eax
movl %eax, -0x34(%rbp)
movl $0x0, -0x164(%rbp)
cmpl $0x6, -0x3c(%rbp)
jne 0xbf2b
movzbl -0x49(%rbp), %eax
cmpl $0x3, %eax
jne 0xbf1d
movzbl -0x4b(%rbp), %eax
cmpl $0x0, %eax
je 0xbf07
movzbl -0x4b(%rbp), %eax
cmpl $0x1, %eax
je 0xbf07
movzbl -0x4b(%rbp), %eax
cmpl $0x2, %eax
je 0xbf07
movzbl -0x4b(%rbp), %eax
cmpl $0x3, %eax
jne 0xbf1b
movl $0x0, 0x1414f(%rip)     # 0x20060
movl $0x0, 0x14141(%rip)     # 0x2005c
jmp 0xbf1d
movl $0x4, -0x34(%rbp)
movl $0x1, -0x30(%rbp)
movl -0x28(%rbp), %eax
movl %eax, -0x2c(%rbp)
cmpl $0x1, -0x2c(%rbp)
jne 0xbf47
cmpl $0x0, 0x1411e(%rip)     # 0x2005c
je 0xbf47
movl $0x2, -0x2c(%rbp)
cmpl $0x0, -0x34(%rbp)
jne 0xbf58
movl -0x2c(%rbp), %edi
callq 0x11e50
movl %eax, -0x34(%rbp)
cmpl $0x0, -0x3c(%rbp)
jne 0xbf68
movq -0x10(%rbp), %rax
movq %rax, -0x20(%rbp)
jmp 0xbf8b
movl -0x3c(%rbp), %eax
subl $0x1, %eax
movslq %eax, %rcx
leaq 0x10448(%rip), %rax     # 0x1c3c0
shlq $0x6, %rcx
addq %rcx, %rax
movzbl -0x4b(%rbp), %ecx
movq (%rax,%rcx,8), %rax
movq %rax, -0x20(%rbp)
movq -0x20(%rbp), %rdi
callq 0x90a0
cmpq $0x0, %rax
jne 0xbfa6
movl $0x0, -0x4(%rbp)
jmp 0xc4de
cmpl $0x1a, -0x14(%rbp)
jne 0xbfb3
movl $0x1, -0x2c(%rbp)
movzbl -0x5(%rbp), %eax
cmpl $0x62, %eax
je 0xbfc5
movzbl -0x5(%rbp), %eax
cmpl $0x63, %eax
jne 0xbfdc
movzbl -0x5(%rbp), %eax
cmpl $0x63, %eax
jne 0xbfd5
movl $0x4, -0x34(%rbp)
movl $0x1, -0x30(%rbp)
movzbl -0x5(%rbp), %eax
cmpl $0xc4, %eax
je 0xc013
movzbl -0x5(%rbp), %eax
cmpl $0xc5, %eax
je 0xc013
movzbl -0x5(%rbp), %eax
cmpl $0xb2, %eax
je 0xc013
movzbl -0x5(%rbp), %eax
cmpl $0xb4, %eax
je 0xc013
movzbl -0x5(%rbp), %eax
cmpl $0xb5, %eax
jne 0xc01a
movl $0x1, -0x30(%rbp)
cmpl $0x3, -0x3c(%rbp)
jne 0xc06f
movzbl -0x4b(%rbp), %eax
cmpl $0x0, %eax
jne 0xc042
movl -0x28(%rbp), %eax
addl $0x5, %eax
movl %eax, -0x38(%rbp)
movl $0x0, -0x24(%rbp)
movl $0x1, -0x30(%rbp)
jmp 0xc06d
movl $0x0, -0x38(%rbp)
movzbl -0x4b(%rbp), %eax
cmpl $0x2, %eax
je 0xc05b
movzbl -0x4b(%rbp), %eax
cmpl $0x3, %eax
jne 0xc064
movl $0x0, -0x30(%rbp)
jmp 0xc06b
movl $0x1, -0x30(%rbp)
jmp 0xc06d
jmp 0xc06f
cmpl $0x5, -0x3c(%rbp)
jne 0xc0c6
movzbl -0x4b(%rbp), %eax
cmpl $0x3, %eax
je 0xc087
movzbl -0x4b(%rbp), %eax
cmpl $0x5, %eax
jne 0xc0a9
cmpl $0x0, 0x13fce(%rip)     # 0x2005c
je 0xc099
movl $0x6, -0x34(%rbp)
jmp 0xc0a0
movl $0x5, -0x34(%rbp)
movl $0x1, -0x30(%rbp)
jmp 0xc0c4
movzbl -0x4b(%rbp), %eax
cmpl $0x0, %eax
je 0xc0bb
movzbl -0x4b(%rbp), %eax
cmpl $0x1, %eax
jne 0xc0c2
movl $0x1, -0x30(%rbp)
jmp 0xc0c4
jmp 0xc0c6
cmpl $0x7, -0x3c(%rbp)
jne 0xc0e7
movzbl -0x4b(%rbp), %eax
cmpl $0x4, %eax
je 0xc0de
movzbl -0x4b(%rbp), %eax
cmpl $0x6, %eax
jne 0xc0e5
movl $0x4, -0x34(%rbp)
jmp 0xc0e7
cmpl $0x0, -0x24(%rbp)
jne 0xc10e
movzbl -0x49(%rbp), %eax
cmpl $0x3, %eax
jne 0xc10e
cmpl $0x0, -0x14(%rbp)
je 0xc102
cmpl $0x1, -0x14(%rbp)
jne 0xc10e
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movb $0x0, -0x90(%rbp)
leaq -0x90(%rbp), %rdi
movb -0x49(%rbp), %dl
movb -0x4a(%rbp), %al
movl -0x34(%rbp), %ecx
movl -0x30(%rbp), %r8d
movl -0x164(%rbp), %r9d
movzbl %dl, %esi
movzbl %al, %edx
callq 0xb980
movl %eax, -0x50(%rbp)
cmpl $-0x1, -0x50(%rbp)
jne 0xc150
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movl -0x38(%rbp), %eax
movq %rax, -0x170(%rbp)
subq $0xd, %rax
ja 0xc44a
movq -0x170(%rbp), %rax
leaq 0xaf62(%rip), %rcx      # 0x170d4
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
jmp 0xc44a
movzbl -0x5(%rbp), %eax
cmpl $0xc4, %eax
je 0xc1c9
movzbl -0x5(%rbp), %eax
cmpl $0xc5, %eax
je 0xc1c9
movzbl -0x5(%rbp), %eax
cmpl $0x62, %eax
je 0xc1c9
movzbl -0x5(%rbp), %eax
cmpl $0x63, %eax
je 0xc1c9
movzbl -0x5(%rbp), %eax
cmpl $0xb2, %eax
je 0xc1c9
movzbl -0x5(%rbp), %eax
cmpl $0xb4, %eax
je 0xc1c9
movzbl -0x5(%rbp), %eax
cmpl $0xb5, %eax
jne 0xc1d0
movl $0x1, -0x2c(%rbp)
leaq -0xd0(%rbp), %rdi
movslq -0x2c(%rbp), %rcx
leaq 0xff1e(%rip), %rax      # 0x1c100
shlq $0x6, %rcx
addq %rcx, %rax
movzbl -0x4b(%rbp), %ecx
movq (%rax,%rcx,8), %rsi
callq 0x9060
jmp 0xc44a
movzbl -0x4b(%rbp), %eax
cmpl $0x5, %eax
jle 0xc210
movl $0x0, -0x4(%rbp)
jmp 0xc4de
leaq -0xd0(%rbp), %rdi
movzbl -0x4b(%rbp), %eax
movl %eax, %ecx
leaq 0xffdc(%rip), %rax      # 0x1c200
movq (%rax,%rcx,8), %rsi
callq 0x9060
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
leaq 0xb1e9(%rip), %rsi      # 0x17429
callq 0x9060
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
leaq 0xaf93(%rip), %rsi      # 0x171eb
callq 0x9060
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movl -0x50(%rbp), %esi
xorl %edx, %edx
callq 0xbbe0
cmpl $0x0, %eax
je 0xc284
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movl -0x50(%rbp), %eax
addl $0x1, %eax
movl %eax, -0x50(%rbp)
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movl -0x50(%rbp), %esi
callq 0xbcc0
cmpl $0x0, %eax
je 0xc2b2
movl $0x0, -0x4(%rbp)
jmp 0xc4de
cmpl $0x0, 0x13da3(%rip)     # 0x2005c
je 0xc2c6
movl -0x50(%rbp), %eax
addl $0x4, %eax
movl %eax, -0x50(%rbp)
jmp 0xc2cf
movl -0x50(%rbp), %eax
addl $0x2, %eax
movl %eax, -0x50(%rbp)
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movl -0x50(%rbp), %esi
movl $0x1, %edx
callq 0xbbe0
cmpl $0x0, %eax
je 0xc2f9
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movl -0x50(%rbp), %eax
addl $0x1, %eax
movl %eax, -0x50(%rbp)
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movslq -0x2c(%rbp), %rcx
leaq 0xfde7(%rip), %rax      # 0x1c100
shlq $0x6, %rcx
addq %rcx, %rax
movzbl -0x4b(%rbp), %ecx
movq (%rax,%rcx,8), %rsi
callq 0x9060
leaq -0x110(%rbp), %rdi
movl -0x50(%rbp), %esi
callq 0xbcc0
cmpl $0x0, %eax
je 0xc34d
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movl -0x50(%rbp), %eax
addl $0x2, %eax
movl %eax, -0x50(%rbp)
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movslq -0x2c(%rbp), %rcx
leaq 0xfd93(%rip), %rax      # 0x1c100
shlq $0x6, %rcx
addq %rcx, %rax
movzbl -0x4b(%rbp), %ecx
movq (%rax,%rcx,8), %rsi
callq 0x9060
leaq -0x110(%rbp), %rdi
movl -0x50(%rbp), %esi
movl $0x1, %edx
callq 0xbbe0
cmpl $0x0, %eax
je 0xc3a6
movl $0x0, -0x4(%rbp)
jmp 0xc4de
movl -0x50(%rbp), %eax
addl $0x1, %eax
movl %eax, -0x50(%rbp)
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movzbl -0x4b(%rbp), %eax
movl %eax, %ecx
leaq 0xfe98(%rip), %rax      # 0x1c260
movq (%rax,%rcx,8), %rsi
callq 0x9060
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movzbl -0x4b(%rbp), %eax
movl %eax, %ecx
leaq 0xfeb9(%rip), %rax      # 0x1c2a0
movq (%rax,%rcx,8), %rsi
callq 0x9060
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movzbl -0x4b(%rbp), %eax
movl %eax, %ecx
leaq 0xfeda(%rip), %rax      # 0x1c2e0
movq (%rax,%rcx,8), %rsi
callq 0x9060
jmp 0xc44a
leaq -0xd0(%rbp), %rdi
movslq -0x2c(%rbp), %rcx
leaq 0xfcdd(%rip), %rax      # 0x1c100
shlq $0x6, %rcx
addq %rcx, %rax
movzbl -0x4b(%rbp), %ecx
movq (%rax,%rcx,8), %rsi
callq 0x9060
leaq -0x110(%rbp), %rdi
leaq 0xada6(%rip), %rsi      # 0x171eb
callq 0x9060
movl -0x24(%rbp), %eax
andl $0x1, %eax
cmpl $0x0, %eax
je 0xc489
leaq -0x160(%rbp), %rdi
movslq -0x24(%rbp), %rcx
leaq 0x10209(%rip), %rax     # 0x1c670
movq (%rax,%rcx,8), %rsi
leaq -0xd0(%rbp), %rdx
leaq -0x90(%rbp), %rcx
leaq -0x110(%rbp), %r8
movb $0x0, %al
callq 0x9190
jmp 0xc4bb
leaq -0x160(%rbp), %rdi
movslq -0x24(%rbp), %rcx
leaq 0x101d5(%rip), %rax     # 0x1c670
movq (%rax,%rcx,8), %rsi
leaq -0x90(%rbp), %rdx
leaq -0xd0(%rbp), %rcx
leaq -0x110(%rbp), %r8
movb $0x0, %al
callq 0x9190
callq 0x123f0
movq -0x20(%rbp), %rdi
callq 0x9670
leaq -0x160(%rbp), %rdi
callq 0x96b0
movl -0x50(%rbp), %eax
addl $0x2, %eax
movl %eax, -0x4(%rbp)
movl -0x4(%rbp), %eax
addq $0x170, %rsp            # imm = 0x170
popq %rbp
retq
nopw (%rax,%rax)