// File: /workspace/github_c_makefile_star2_O2/nh13[P]ksw/src/parasail/src/nw_stats_diag_avx2_256_32.c
// Function: arr_store_si256
static inline void arr_store_si256(
        int *array,
        __m256i vWH,
        int32_t i,
        int32_t s1Len,
        int32_t j,
        int32_t s2Len)
{
    if (0 <= i+0 && i+0 < s1Len && 0 <= j-0 && j-0 < s2Len) {
        array[1LL*(i+0)*s2Len + (j-0)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 7);
    }
    if (0 <= i+1 && i+1 < s1Len && 0 <= j-1 && j-1 < s2Len) {
        array[1LL*(i+1)*s2Len + (j-1)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 6);
    }
    if (0 <= i+2 && i+2 < s1Len && 0 <= j-2 && j-2 < s2Len) {
        array[1LL*(i+2)*s2Len + (j-2)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 5);
    }
    if (0 <= i+3 && i+3 < s1Len && 0 <= j-3 && j-3 < s2Len) {
        array[1LL*(i+3)*s2Len + (j-3)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 4);
    }
    if (0 <= i+4 && i+4 < s1Len && 0 <= j-4 && j-4 < s2Len) {
        array[1LL*(i+4)*s2Len + (j-4)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 3);
    }
    if (0 <= i+5 && i+5 < s1Len && 0 <= j-5 && j-5 < s2Len) {
        array[1LL*(i+5)*s2Len + (j-5)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 2);
    }
    if (0 <= i+6 && i+6 < s1Len && 0 <= j-6 && j-6 < s2Len) {
        array[1LL*(i+6)*s2Len + (j-6)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 1);
    }
    if (0 <= i+7 && i+7 < s1Len && 0 <= j-7 && j-7 < s2Len) {
        array[1LL*(i+7)*s2Len + (j-7)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 0);
    }
}

// Assembly:
vextractf128 $0x1, %ymm0, %xmm1
movl %r8d, %eax
movl %ecx, %r9d
cmpl %r8d, %ecx
jge 0x4ced53
cmpl %edx, %esi
jge 0x4ced53
movl %ecx, %r10d
orl %esi, %r10d
js 0x4ced53
movl %esi, %r10d
imulq %rax, %r10
leaq (%rdi,%r10,4), %r10
vextractps $0x3, %xmm1, (%r10,%r9,4)
pushq %rbp
pushq %rbx
leal 0x1(%rsi), %r10d
cmpl $-0x1, %esi
setl %r11b
cmpl %edx, %r10d
setge %bl
testl %ecx, %ecx
setle %bpl
orb %r11b, %bpl
orb %bl, %bpl
cmpl %r8d, %ecx
setg %r11b
orb %bpl, %r11b
jne 0x4ced91
movl %r10d, %r10d
imulq %rax, %r10
leaq (%rdi,%r10,4), %r10
vextractps $0x2, %xmm1, -0x4(%r10,%r9,4)
leal 0x2(%rsi), %r9d
cmpl $-0x2, %esi
setge %r10b
cmpl %edx, %r9d
setl %r11b
andb %r10b, %r11b
cmpb $0x1, %r11b
jne 0x4cedda
leal -0x2(%rcx), %r10d
cmpl $0x2, %ecx
setge %r11b
cmpl %r8d, %r10d
setl %bl
andb %r11b, %bl
cmpb $0x1, %bl
jne 0x4cedda
movl %r9d, %r9d
imulq %rax, %r9
movl %r10d, %r10d
leaq (%rdi,%r9,4), %r9
vextractps $0x1, %xmm1, (%r9,%r10,4)
leal 0x3(%rsi), %r9d
cmpl $-0x3, %esi
setge %r10b
cmpl %edx, %r9d
setl %r11b
andb %r10b, %r11b
cmpb $0x1, %r11b
jne 0x4cee22
leal -0x3(%rcx), %r10d
cmpl $0x3, %ecx
setge %r11b
cmpl %r8d, %r10d
setl %bl
andb %r11b, %bl
cmpb $0x1, %bl
jne 0x4cee22
movl %r9d, %r9d
imulq %rax, %r9
movl %r10d, %r10d
leaq (%rdi,%r9,4), %r9
vmovss %xmm1, (%r9,%r10,4)
leal 0x4(%rsi), %r9d
cmpl $-0x4, %esi
setge %r10b
cmpl %edx, %r9d
setl %r11b
andb %r10b, %r11b
cmpb $0x1, %r11b
jne 0x4cee6b
leal -0x4(%rcx), %r10d
cmpl $0x4, %ecx
setge %r11b
cmpl %r8d, %r10d
setl %bl
andb %r11b, %bl
cmpb $0x1, %bl
jne 0x4cee6b
movl %r9d, %r9d
imulq %rax, %r9
movl %r10d, %r10d
leaq (%rdi,%r9,4), %r9
vextractps $0x3, %xmm0, (%r9,%r10,4)
leal 0x5(%rsi), %r9d
cmpl $-0x5, %esi
setge %r10b
cmpl %edx, %r9d
setl %r11b
andb %r10b, %r11b
cmpb $0x1, %r11b
jne 0x4ceeb4
leal -0x5(%rcx), %r10d
cmpl $0x5, %ecx
setge %r11b
cmpl %r8d, %r10d
setl %bl
andb %r11b, %bl
cmpb $0x1, %bl
jne 0x4ceeb4
movl %r9d, %r9d
imulq %rax, %r9
movl %r10d, %r10d
leaq (%rdi,%r9,4), %r9
vextractps $0x2, %xmm0, (%r9,%r10,4)
leal 0x6(%rsi), %r9d
cmpl $-0x6, %esi
setge %r10b
cmpl %edx, %r9d
setl %r11b
andb %r10b, %r11b
cmpb $0x1, %r11b
jne 0x4ceefd
leal -0x6(%rcx), %r10d
cmpl $0x6, %ecx
setge %r11b
cmpl %r8d, %r10d
setl %bl
andb %r11b, %bl
cmpb $0x1, %bl
jne 0x4ceefd
movl %r9d, %r9d
imulq %rax, %r9
movl %r10d, %r10d
leaq (%rdi,%r9,4), %r9
vextractps $0x1, %xmm0, (%r9,%r10,4)
leal 0x7(%rsi), %r9d
cmpl $-0x7, %esi
setge %sil
cmpl %edx, %r9d
setl %dl
andb %sil, %dl
cmpb $0x1, %dl
popq %rbx
popq %rbp
jne 0x4cef43
leal -0x7(%rcx), %edx
cmpl $0x7, %ecx
setge %cl
cmpl %r8d, %edx
setl %sil
andb %cl, %sil
cmpb $0x1, %sil
jne 0x4cef43
movl %r9d, %ecx
imulq %rcx, %rax
movl %edx, %ecx
leaq (%rdi,%rax,4), %rax
vmovss %xmm0, (%rax,%rcx,4)
vzeroupper
retq
nop