// File: /workspace/github_cpp_makefile_star2_O1/NishadSaraf[P]Championship-Simulator/src/cache.cc
// Function: CACHE::handle_prefetch()
void CACHE::handle_prefetch()
{
    // handle prefetch
    uint32_t prefetch_cpu = PQ.entry[PQ.head].cpu;
    if (prefetch_cpu == NUM_CPUS)
        return;

    for (uint32_t i=0; i<MAX_READ; i++) {

        // handle the oldest entry
        if ((PQ.entry[PQ.head].event_cycle <= current_core_cycle[prefetch_cpu]) && (PQ.occupancy > 0)) {
            int index = PQ.head;

            // access cache
            uint32_t set = get_set(PQ.entry[index].address);
            int way = check_hit(&PQ.entry[index]);
            
            if (way >= 0) { // prefetch hit

                // update replacement policy
                if (cache_type == IS_LLC) {
                    llc_update_replacement_state(prefetch_cpu, set, way, block[set][way].full_addr, PQ.entry[index].ip, 0, PQ.entry[index].type, 1);

                }
                else
                    update_replacement_state(prefetch_cpu, set, way, block[set][way].full_addr, PQ.entry[index].ip, 0, PQ.entry[index].type, 1);

                // COLLECT STATS
                sim_hit[prefetch_cpu][PQ.entry[index].type]++;
                sim_access[prefetch_cpu][PQ.entry[index].type]++;

                // check fill level
                if (PQ.entry[index].fill_level < fill_level) {

                    if (PQ.entry[index].instruction) 
                        upper_level_icache[prefetch_cpu]->return_data(&PQ.entry[index]);
                    else // data
                        upper_level_dcache[prefetch_cpu]->return_data(&PQ.entry[index]);
                }

                HIT[PQ.entry[index].type]++;
                ACCESS[PQ.entry[index].type]++;
                
                // remove this entry from PQ
                PQ.remove_queue(&PQ.entry[index]);
            }
            else { // prefetch miss

                DP ( if (warmup_complete[prefetch_cpu]) {
                cout << "[" << NAME << "] " << __func__ << " prefetch miss";
                cout << " instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
                cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << PQ.entry[index].fill_level;
                cout << " cycle: " << PQ.entry[index].event_cycle << endl; });

                // check mshr
                uint8_t miss_handled = 1;
                int mshr_index = check_mshr(&PQ.entry[index]);

                if ((mshr_index == -1) && (MSHR.occupancy < MSHR_SIZE)) { // this is a new miss

                    DP ( if (warmup_complete[PQ.entry[index].cpu]) {
                    cout << "[" << NAME << "_PQ] " <<  __func__ << " want to add instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
                    cout << " full_addr: " << PQ.entry[index].full_addr << dec;
                    cout << " occupancy: " << lower_level->get_occupancy(3) << " SIZE: " << lower_level->get_size(3) << endl; });

                    // first check if the lower level PQ is full or not
                    // this is possible since multiple prefetchers can exist at each level of caches
                    if (lower_level) {
                        if (cache_type == IS_LLC) {
                            if (lower_level->get_occupancy(1) == lower_level->get_size(1))
                                miss_handled = 0;
                            else {
                                // add it to MSHRs if this prefetch miss will be filled to this cache level
                                if (PQ.entry[index].fill_level <= fill_level)
                                    add_mshr(&PQ.entry[index]);
                                
                                lower_level->add_rq(&PQ.entry[index]); // add it to the DRAM RQ
                            }
                        }
                        else {
                            if (lower_level->get_occupancy(3) == lower_level->get_size(3))
                                miss_handled = 0;
                            else {
                                // add it to MSHRs if this prefetch miss will be filled to this cache level
                                if (PQ.entry[index].fill_level <= fill_level)
                                    add_mshr(&PQ.entry[index]);

                                lower_level->add_pq(&PQ.entry[index]); // add it to the DRAM RQ
                            }
                        }
                    }
                }
                else {
                    if ((mshr_index == -1) && (MSHR.occupancy == MSHR_SIZE)) { // not enough MSHR resource

                        // TODO: should we allow prefetching with lower fill level at this case?
                        
                        // cannot handle miss request until one of MSHRs is available
                        miss_handled = 0;
                        STALL[PQ.entry[index].type]++;
                    }
                    else if (mshr_index != -1) { // already in-flight miss

                        // no need to update request except fill_level
                        // update fill_level
                        if (PQ.entry[index].fill_level < MSHR.entry[mshr_index].fill_level)
                            MSHR.entry[mshr_index].fill_level = PQ.entry[index].fill_level;

                        MSHR_MERGED[PQ.entry[index].type]++;

                        DP ( if (warmup_complete[prefetch_cpu]) {
                        cout << "[" << NAME << "] " << __func__ << " mshr merged";
                        cout << " instr_id: " << PQ.entry[index].instr_id << " prior_id: " << MSHR.entry[mshr_index].instr_id; 
                        cout << " address: " << hex << PQ.entry[index].address;
                        cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << MSHR.entry[mshr_index].fill_level;
                        cout << " cycle: " << MSHR.entry[mshr_index].event_cycle << endl; });
                    }
                    else { // WE SHOULD NOT REACH HERE
                        cerr << "[" << NAME << "] MSHR errors" << endl;
                        assert(0);
                    }
                }

                if (miss_handled) {

                    DP ( if (warmup_complete[prefetch_cpu]) {
                    cout << "[" << NAME << "] " << __func__ << " prefetch miss handled";
                    cout << " instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
                    cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << PQ.entry[index].fill_level;
                    cout << " cycle: " << PQ.entry[index].event_cycle << endl; });

                    MISS[PQ.entry[index].type]++;
                    ACCESS[PQ.entry[index].type]++;

                    // remove this entry from PQ
                    PQ.remove_queue(&PQ.entry[index]);
                }
            }
        }
    }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq 0xad80(%rdi), %rax
movl 0xad14(%rdi), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
movl 0x330(%rax,%rcx), %ecx
movq %rcx, 0x8(%rsp)
cmpq $0x1, %rcx
je 0x5844
movq %rdi, %rbx
cmpl $0x0, 0x739c(%rdi)
je 0x5844
leaq 0xace8(%rbx), %rax
movq %rax, 0x10(%rsp)
leaq 0x10308(%rbx), %rcx
leaq 0x102e8(%rbx), %rax
movq 0x8(%rsp), %rsi
leaq 0x8(%rbx,%rsi,8), %rdx
movq %rdx, 0x20(%rsp)
leaq (%rbx,%rsi,8), %rdx
addq $0x10, %rdx
movq %rdx, 0x18(%rsp)
xorl %r13d, %r13d
leaq 0x7b9ca(%rip), %r14     # 0x80ec0
shlq $0x5, %rsi
addq %rsi, %rcx
movq %rcx, 0x30(%rsp)
addq %rax, %rsi
movq %rsi, 0x28(%rsp)
movq 0xad80(%rbx), %rax
movl 0xad14(%rbx), %ecx
imulq $0x380, %rcx, %rdx      # imm = 0x380
movq 0x378(%rax,%rdx), %rdx
movq 0x8(%rsp), %rsi
cmpq (%r14,%rsi,8), %rdx
ja 0x573c
cmpl $0x0, 0xad1c(%rbx)
je 0x573c
movslq %ecx, %rcx
imulq $0x380, %rcx, %r15      # imm = 0x380
movl 0x340(%rax,%r15), %r12d
movl 0x7370(%rbx), %edi
callq 0x9196
movl $0xffffffff, %ebp       # imm = 0xFFFFFFFF
movl %eax, %ecx
shll %cl, %ebp
movq 0xad80(%rbx), %rsi
addq %r15, %rsi
movq %rbx, %rdi
callq 0x495c
testl %eax, %eax
js 0x55e4
notl %ebp
andl %r12d, %ebp
cmpb $0x6, 0x73a4(%rbx)
movl %ebp, %ecx
movl %eax, %edx
movq 0xad80(%rbx), %rsi
movq 0x370(%rsi,%r15), %r9
movzbl 0x32f(%rsi,%r15), %r10d
leaq (%rdx,%rdx,4), %rdx
jne 0x5637
movq 0x7390(%rbx), %rsi
movq (%rsi,%rcx,8), %rcx
shlq $0x4, %rdx
movq 0x20(%rcx,%rdx), %r8
subq $0x8, %rsp
movq %rbx, %rdi
movq 0x10(%rsp), %rsi
movl %ebp, %edx
movl %eax, %ecx
pushq $0x1
pushq %r10
pushq $0x0
callq 0x1385c
jmp 0x5666
movq 0xad80(%rbx), %rax
movl 0x7388(%rbx), %edx
movl $0xffffffff, %ecx       # imm = 0xFFFFFFFF
testq %rdx, %rdx
je 0x56d3
movq 0x340(%rax,%r15), %rsi
movq 0xca20(%rbx), %rdi
movl $0x340, %r8d            # imm = 0x340
addq %r8, %rdi
xorl %r8d, %r8d
cmpq %rsi, (%rdi)
je 0x56d0
incq %r8
addq $0x380, %rdi            # imm = 0x380
cmpq %r8, %rdx
jne 0x561a
jmp 0x56d3
movq 0x7390(%rbx), %rsi
movq (%rsi,%rcx,8), %rcx
shlq $0x4, %rdx
movq 0x20(%rcx,%rdx), %r8
subq $0x8, %rsp
movq %rbx, %rdi
movq 0x10(%rsp), %rsi
movl %ebp, %edx
movl %eax, %ecx
pushq $0x1
pushq %r10
pushq $0x0
callq 0x137be
addq $0x20, %rsp
movq 0xad80(%rbx), %rsi
movzbl 0x32f(%rsi,%r15), %eax
shll $0x3, %eax
movq 0x30(%rsp), %rcx
incq (%rax,%rcx)
movq 0x28(%rsp), %rcx
incq (%rax,%rcx)
movl 0x8(%rsi,%r15), %eax
cmpl 0x7398(%rbx), %eax
jge 0x56b6
addq %r15, %rsi
cmpb $0x0, (%rsi)
movq 0x20(%rsp), %rax
cmoveq 0x18(%rsp), %rax
movq (%rax), %rdi
movq (%rdi), %rax
callq *0x18(%rax)
movq 0xad80(%rbx), %rax
movzbl 0x32f(%rax,%r15), %ecx
incq 0x72c8(%rbx,%rcx,8)
jmp 0x5726
movl %r8d, %ecx
cmpl $-0x1, %ecx
je 0x5751
movl 0x8(%rax,%r15), %edx
movq 0xca20(%rbx), %rsi
movslq %ecx, %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
cmpl 0x8(%rsi,%rcx), %edx
jge 0x56fd
addq %rsi, %rcx
addq $0x8, %rcx
movl %edx, (%rcx)
movzbl 0x32f(%rax,%r15), %eax
incq 0x7308(%rbx,%rax,8)
movq 0xad80(%rbx), %rax
movzbl 0x32f(%rax,%r15), %ecx
incq 0x72e8(%rbx,%rcx,8)
leaq (%rax,%r15), %rsi
incq 0x72a8(%rbx,%rcx,8)
movq 0x10(%rsp), %rdi
callq 0xc3e6
incl %r13d
cmpl 0x739c(%rbx), %r13d
jb 0x550a
jmp 0x5844
movl 0xc9bc(%rbx), %esi
cmpl %edx, %esi
jae 0x57c7
movq 0x18(%rbx), %rdi
testq %rdi, %rdi
je 0x570e
cmpb $0x6, 0x73a4(%rbx)
movq (%rdi), %rax
movq 0x30(%rax), %rax
jne 0x57ec
movl $0x1, %esi
callq *%rax
movl %eax, %ebp
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
movl $0x1, %esi
callq *0x38(%rax)
cmpl %eax, %ebp
je 0x573c
movq 0xad80(%rbx), %rsi
movl 0x8(%rsi,%r15), %eax
cmpl 0x7398(%rbx), %eax
jg 0x57af
addq %r15, %rsi
movq %rbx, %rdi
callq 0x4b3e
movq 0x18(%rbx), %rdi
movq 0xad80(%rbx), %rsi
addq %r15, %rsi
movq (%rdi), %rax
callq *(%rax)
jmp 0x570e
cmpl %edx, %esi
jne 0x57e1
movzbl 0x32f(%rax,%r15), %eax
incq 0x7328(%rbx,%rax,8)
jmp 0x573c
cmpl $-0x1, %ecx
jne 0x56d8
jmp 0x5853
movl $0x3, %esi
callq *%rax
movl %eax, %ebp
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
movl $0x3, %esi
callq *0x38(%rax)
cmpl %eax, %ebp
je 0x573c
movq 0xad80(%rbx), %rsi
movl 0x8(%rsi,%r15), %eax
cmpl 0x7398(%rbx), %eax
jg 0x582b
addq %r15, %rsi
movq %rbx, %rdi
callq 0x4b3e
movq 0x18(%rbx), %rdi
movq 0xad80(%rbx), %rsi
addq %r15, %rsi
movq (%rdi), %rax
callq *0x10(%rax)
jmp 0x570e
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0x14796(%rip), %rdi     # 0x19ff0
leaq 0xe82f(%rip), %rsi      # 0x14090
callq 0x3250
addq $0x7350, %rbx           # imm = 0x7350
movq %rax, %rdi
movq %rbx, %rsi
callq 0x31e0
leaq 0xe813(%rip), %rsi      # 0x14092
movq %rax, %rdi
callq 0x3250
movq %rax, %rdi
callq 0x3110
leaq 0xe7d1(%rip), %rdi      # 0x14067
leaq 0xe7cc(%rip), %rsi      # 0x14069
leaq 0xe862(%rip), %rcx      # 0x14106
movl $0x302, %edx            # imm = 0x302
callq 0x3160