// File: /workspace/github_c_makefile_star2_O2/xiane[P]libvphevcodec/AML_HEVCEncoder.cpp
// Function: Wave4VpuEncEncPic(AMVHEVCEncHandle_s*, unsigned int, int, unsigned char*, unsigned int*, int*)
AMVEnc_Status Wave4VpuEncEncPic(AMVHEVCEncHandle *Handle, Uint32 idx, int end, unsigned char *buffer, unsigned int *buf_nal_size, int *nal_type) {
    int coreIdx = 0;
    Uint32 addr_report_buf = 0;    // [31:0]
    Uint32 report_buf_size = 0;    // [31:0]
    unsigned char report_endian = 0;    // [ 3:0]
    //Uint32 use_sec_axi = 0;    // [31:0]
    //Uint32 sec_axi_buf_size = 0x00012800;   // 74KB
    Uint32 rd_ptr, wr_ptr;
    //Uint32 src_num, fb_num, i, j;   // [31:0]
    Uint32 src_stride;
    Uint32 luma_stride, chroma_stride;
    Uint32 size_src_luma, size_src_chroma;
   // char *y = NULL;
    src_stride = wave420l_align32(Handle->enc_width);
    luma_stride = src_stride;
    chroma_stride = src_stride;

    // set frame buffers

    // calculate required buffer size
    size_src_luma = luma_stride * wave420l_align32(Handle->enc_height);

    size_src_chroma = luma_stride * (wave420l_align16(Handle->enc_height) / 2);

    // Bitstream Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_BS_START_ADDR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_SIZE, Handle->bs_vb.size - 0x8000);
    VpuWriteReg(Handle->instance_id, W4_BS_PARAM, 0xf);
    VpuWriteReg(Handle->instance_id, W4_BS_OPTION, 0);

    uint32_t current_idx = 0;
    current_idx |= (0 << 24); // [27:24] codec_std_aux
    current_idx |= (1 << 16); // [23:16] codec_std
    current_idx |= (Handle->instance_id << 0);  // [15: 0] Handle->instance_id
    VpuWriteReg(Handle->instance_id, W4_INST_INDEX, current_idx);

    // Work Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_WORK_BASE, Handle->work_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_WORK_SIZE, Handle->work_vb.size);
    VpuWriteReg(Handle->instance_id, W4_WORK_PARAM, 0);

    // Temp Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_TEMP_BASE, Handle->temp_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_TEMP_SIZE, Handle->temp_vb.size);
    VpuWriteReg(Handle->instance_id, W4_TEMP_PARAM, gol_endian);

    VpuWriteReg(Handle->instance_id, W4_BS_RD_PTR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_WR_PTR, Handle->bs_vb.phys_addr);

    /* Secondary AXI */
    VpuWriteReg(Handle->instance_id, W4_ADDR_SEC_AXI, 0);
    VpuWriteReg(Handle->instance_id, W4_SEC_AXI_SIZE, 0);
    VpuWriteReg(Handle->instance_id, W4_USE_SEC_AXI, 0);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_ADDR_REPORT_BASE, addr_report_buf);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_SIZE, report_buf_size);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_PARAM, report_endian);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_CODE_OPTION, 3);
    if (Handle->idrPeriod == -1 || (Handle->src_pics[idx].op_flag & AMVEncFrameIO_FORCE_IDR_FLAG))
        VpuWriteReg(Handle->instance_id, W4_CMD_ENC_PIC_PARAM, (3 << 21) | (1 << 20));
    else
        VpuWriteReg(Handle->instance_id, W4_CMD_ENC_PIC_PARAM, 0);
    if (end)
        VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_PIC_IDX, 0xffffffff);
    else
        VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_PIC_IDX, idx);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_ADDR_Y, Handle->src_pics[idx].vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_ADDR_U, Handle->src_pics[idx].vb.phys_addr + size_src_luma);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_ADDR_V, Handle->src_pics[idx].vb.phys_addr + size_src_luma);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_STRIDE, (src_stride << 16) | src_stride);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_FORMAT, ((2 + Handle->mUvSwap) << 0) | (0 << 3) | (gol_endian << 6));

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SEI_USER_ADDR, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SEI_USER_INFO, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_TIMESTAMP_LOW, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_TIMESTAMP_HIGH, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_LONGTERM_PIC, 0);
    // set ROI param
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_ROI_PARAM, 0);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_ROI_ADDR_CTU_MAP, 0);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SUB_FRAME_SYNC_CONFIG, 0);

    VpuWriteReg(Handle->instance_id, W4_VPU_BUSY_STATUS, 1);
    VpuWriteReg(Handle->instance_id, W4_RET_SUCCESS, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_CORE_INDEX, 0);
    VpuWriteReg(Handle->instance_id, W4_RET_FAIL_REASON, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_COMMAND, ENC_PIC);
    VpuWriteReg(Handle->instance_id, W4_VPU_HOST_INT_REQ, 1);
    uint32_t status = VpuReadReg(Handle->instance_id, W4_VPU_BUSY_STATUS);
    VLOG(NONE, "W4_VPU_BUSY_STATUS :0x%x\n", status);
    if (vdi_wait_interrupt(Handle->instance_id, VPU_BUSY_CHECK_TIMEOUT) == -1) {
        VLOG(ERR, "Wave4VpuEncEncPic error time out\n");
        Wave4VpuReset(Handle, coreIdx, reset_mode);
        return AMVENC_TIMEOUT;
    }

    if (VpuReadReg(Handle->instance_id, W4_RET_SUCCESS) == 0) {
        uint32_t reasonCode = VpuReadReg(Handle->instance_id, W4_RET_FAIL_REASON);
        VLOG(ERR, "Wave4VpuEncEncPic failedREASON CODE(%08x)\n", reasonCode);
        Wave4VpuReset(Handle, coreIdx, reset_mode);
        return AMVENC_HARDWARE;
    }

    uint32_t result = VpuReadReg(Handle->instance_id, W4_RET_SUCCESS);
    VLOG(NONE, "W4_RET_SUCCESS %x\n", result );

    uint32_t nal_length;
    {
        rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
        wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);

        nal_length = VpuReadReg(Handle->instance_id, W4_RET_ENC_PIC_BYTE);
        VLOG(NONE, "Wave4VpuEncEncPic, rd:0x%x, wr:0x%x, ret bytes: %d, buffer size:%d\n", rd_ptr, wr_ptr, nal_length, wr_ptr - rd_ptr);

        if (nal_length > Handle->mOutputBufferLen) {
            VLOG(ERR, "nal size %d bigger than output buffer %d!\n", nal_length, Handle->mOutputBufferLen);
            return AMVENC_OVERFLOW;
        }
        if (buf_nal_size != NULL)
            *buf_nal_size = nal_length;
        if (nal_length && (buffer!= NULL))
            vdi_read_memory(Handle->instance_id, rd_ptr, (unsigned char *)buffer, nal_length);
        else if (buffer == NULL)
            VLOG(DEBUG, "HEVC flushing input");
        VLOG(DEBUG, "Wave4VpuEncEncPic %d, ret bytes: %d, buffer size:%d", Handle->enc_counter, nal_length, wr_ptr - rd_ptr);
    }

    uint32_t type = Handle->src_pics[idx].type = VpuReadReg(Handle->instance_id, W4_RET_ENC_PIC_TYPE);
    if (nal_type != NULL) {
        if ((type& 0xff) == I_SLICE) {
            if (Handle->mNumInputFrames == 1)
                *nal_type = HEVC_IDR;
            else
                *nal_type = Handle->mEncParams->refresh_type;
        } else if ((type& 0xff) == P_SLICE || (type & 0xff) == B_SLICE)
           *nal_type = NON_IRAP;
    }

    VLOG(DEBUG, "Wave4VpuEncEncPic PIC type: 0x%x", type);

    //dumpCodedPicture(Handle, idx, buffer, nal_length);
    VpuWriteReg(Handle->instance_id, W4_BS_RD_PTR, wr_ptr);
    VpuWriteReg(Handle->instance_id, W4_RET_ENC_PIC_BYTE, 0);
    return AMVENC_SUCCESS;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r9, 0x20(%rsp)
movq %r8, 0x10(%rsp)
movq %rcx, 0x18(%rsp)
movl %edx, 0xc(%rsp)
movl %esi, %r14d
movq %rdi, %rbx
movl (%rdi), %edi
movl 0xc(%rbx), %r13d
addl $0x1f, %r13d
andl $-0x20, %r13d
movl 0x10(%rbx), %ebp
addl $0x1f, %ebp
andl $0x7ffffe0, %ebp        # imm = 0x7FFFFE0
imull %r13d, %ebp
movl 0x88(%rbx), %edx
movl $0x120, %esi            # imm = 0x120
callq 0x2160
movl (%rbx), %edi
movl $0xffff8000, %edx       # imm = 0xFFFF8000
addl 0x80(%rbx), %edx
movl $0x124, %esi            # imm = 0x124
callq 0x2160
movl (%rbx), %edi
pushq $0xf
popq %r12
movl $0x128, %esi            # imm = 0x128
movl %r12d, %edx
callq 0x2160
movl (%rbx), %edi
xorl %r15d, %r15d
movl $0x12c, %esi            # imm = 0x12C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl %edi, %edx
orl $0x10000, %edx          # imm = 0x10000
movl $0x108, %esi            # imm = 0x108
callq 0x2160
movl (%rbx), %edi
movl 0x48(%rbx), %edx
movl $0x138, %esi            # imm = 0x138
callq 0x2160
movl (%rbx), %edi
movl 0x40(%rbx), %edx
movl $0x13c, %esi            # imm = 0x13C
callq 0x2160
movl (%rbx), %edi
movl $0x140, %esi            # imm = 0x140
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl 0x68(%rbx), %edx
movl $0x144, %esi            # imm = 0x144
callq 0x2160
movl (%rbx), %edi
movl 0x60(%rbx), %edx
movl $0x148, %esi            # imm = 0x148
callq 0x2160
movl (%rbx), %edi
movl $0x14c, %esi            # imm = 0x14C
movl %r12d, %edx
callq 0x2160
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x130, %esi            # imm = 0x130
callq 0x2160
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x134, %esi            # imm = 0x134
callq 0x2160
movl (%rbx), %edi
movl $0x150, %esi            # imm = 0x150
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x154, %esi            # imm = 0x154
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x158, %esi            # imm = 0x158
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x15c, %esi            # imm = 0x15C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x160, %esi            # imm = 0x160
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x164, %esi            # imm = 0x164
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x3
popq %rdx
movl $0x168, %esi            # imm = 0x168
callq 0x2160
cmpl $-0x1, 0x1c(%rbx)
movl %r14d, %r12d
je 0x5ef5
imulq $0x50, %r12, %rax
movl 0xb0(%rbx,%rax), %edx
andl $0x1, %edx
negl %edx
andl $0x700000, %edx         # imm = 0x700000
jmp 0x5efa
movl $0x700000, %edx         # imm = 0x700000
movl (%rbx), %edi
movl $0x16c, %esi            # imm = 0x16C
callq 0x2160
negl 0xc(%rsp)
sbbl %r15d, %r15d
orl %r14d, %r15d
movl (%rbx), %edi
movl $0x170, %esi            # imm = 0x170
movl %r15d, %edx
callq 0x2160
movl (%rbx), %edi
imulq $0x50, %r12, %r12
movl 0xc8(%rbx,%r12), %edx
movl $0x174, %esi            # imm = 0x174
callq 0x2160
movl (%rbx), %edi
movl 0xc8(%rbx,%r12), %edx
addl %ebp, %edx
movl $0x178, %esi            # imm = 0x178
callq 0x2160
movl (%rbx), %edi
addl 0xc8(%rbx,%r12), %ebp
movl $0x17c, %esi            # imm = 0x17C
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl %r13d, %edx
shll $0x10, %edx
orl %r13d, %edx
movl $0x180, %esi            # imm = 0x180
callq 0x2160
movl (%rbx), %edi
movl 0x308(%rbx), %edx
addl $0x2, %edx
orl $0x3c0, %edx            # imm = 0x3C0
movl $0x184, %esi            # imm = 0x184
callq 0x2160
movl (%rbx), %edi
movl $0x188, %esi            # imm = 0x188
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x18c, %esi            # imm = 0x18C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x190, %esi            # imm = 0x190
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x194, %esi            # imm = 0x194
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x198, %esi            # imm = 0x198
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x1a0, %esi            # imm = 0x1A0
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x1a4, %esi            # imm = 0x1A4
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x19c, %esi            # imm = 0x19C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x70
popq %r14
pushq $0x1
popq %rbp
movl %r14d, %esi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x104, %esi            # imm = 0x104
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x114, %esi            # imm = 0x114
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x8
popq %rdx
movl $0x100, %esi            # imm = 0x100
callq 0x2160
movl (%rbx), %edi
pushq $0x38
popq %rsi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl %r14d, %esi
callq 0x2210
movl (%rbx), %edi
movl $0x1388, %esi           # imm = 0x1388
callq 0x2360
cmpl $-0x1, %eax
je 0x60ea
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
testl %eax, %eax
je 0x610f
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2210
movl %eax, %r15d
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl %eax, %r14d
movl (%rbx), %edi
movl $0x1c8, %esi            # imm = 0x1C8
callq 0x2210
movl 0x300(%rbx), %edx
cmpl %edx, %eax
jbe 0x6152
leaq 0x25e54(%rip), %rdi     # 0x2bf29
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x27
jmp 0x6140
leaq 0x261d1(%rip), %rdi     # 0x2c2c2
callq 0x2290
pushq $0xa
popq %rdi
callq 0x2230
pushq $0x2
popq %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq 0x2180
pushq $-0x24
jmp 0x6140
movl $0x114, %esi            # imm = 0x114
callq 0x2210
leaq 0x25e34(%rip), %rdi     # 0x2bf54
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
pushq $0xa
popq %rdi
callq 0x2230
pushq $0x2
popq %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq 0x2180
pushq $-0x25
popq %rbp
movl %ebp, %eax
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0x10(%rsp), %rcx
testq %rcx, %rcx
je 0x615e
movl %eax, (%rcx)
addq %rbx, %r12
addq $0xa0, %r12
testl %eax, %eax
sete %cl
movq 0x18(%rsp), %rdx
testq %rdx, %rdx
sete %sil
orb %cl, %sil
jne 0x618a
movl (%rbx), %edi
movl %r15d, %esi
movl %eax, %ecx
callq 0x2110
movl (%rbx), %edi
movl $0x1e0, %esi            # imm = 0x1E0
callq 0x2210
movl %eax, 0x18(%r12)
movq 0x20(%rsp), %rsi
testq %rsi, %rsi
je 0x61c8
movzbl %al, %ecx
xorl %eax, %eax
leal -0x1(%rcx), %edx
cmpl $0x2, %edx
jae 0x61b6
movl %eax, (%rsi)
jmp 0x61c8
testl %ecx, %ecx
jne 0x61c8
cmpl $0x1, 0x2f8(%rbx)
jne 0x61ea
pushq $0x2
popq %rax
jmp 0x61b2
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
movl %r14d, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x1c8, %esi            # imm = 0x1C8
xorl %edx, %edx
callq 0x2160
jmp 0x6141
movq 0x2e0(%rbx), %rax
movl 0x5c(%rax), %eax
jmp 0x61b2