// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::operate()
void DRC_MEMORY_CONTROLLER::operate()
{
    if (do_write == 0) {
        if (WQ.occupancy >= DRC_WRITE_HIGH_WM) {
            do_write = 1;
            processed_writes = 0;
            last_drc_read_mode = current_core_cycle[0];
            //cout << "DRC is now WRITE mode cycle: " << current_core_cycle[0] << endl;

            // reset scheduled RQ requests
            reset_remain_requests(&RQ);

            for (uint32_t i=0; i<DRC_CHANNELS; i++) {
                // add data bus turnaround time
                dbus_cycle_available[i] += DRC_DBUS_TURN_AROUND_TIME;
            }
        }
    } else {
        if (WQ.occupancy == 0)
            do_write = 0;
        else if (RQ.occupancy && (WQ.occupancy < DRC_WRITE_LOW_WM))
            do_write = 0;
        else if (RQ.occupancy && (MIN_DRC_WRITES_PER_SWITCH <= processed_writes))
            do_write = 0;

        if (do_write == 0) {
            processed_writes = 0;
            last_drc_write_mode = current_core_cycle[0];
            //cout << "DRC is now READ  mode cycle: " << current_core_cycle[0] << endl;

            // reset scheduled WQ requests
            reset_remain_requests(&WQ);

            for (uint32_t i=0; i<DRC_CHANNELS; i++) {
                // add data bus turnaround time
                dbus_cycle_available[i] += DRC_DBUS_TURN_AROUND_TIME;
            }
        }
    }

    // do FR-FCFS scheduling

    // handle write
    // schedule new entry
    //for (uint32_t channel=0; channel<DRC_CHANNELS; channel++) {
        //if (write_mode[channel] && (WQ.next_schedule_index < WQ.SIZE)) {
        if (do_write && (WQ.next_schedule_index < WQ.SIZE)) {
            if (WQ.next_schedule_cycle <= current_core_cycle[WQ.entry[WQ.next_schedule_index].cpu])
                schedule(&WQ);
                //schedule(channel, &WQ);
        }
    //}

    // process DRC requests
    //for (uint32_t channel=0; channel<DRC_CHANNELS; channel++) {
        //if (write_mode[channel] && (WQ.next_process_index < WQ.SIZE)) {
        if (do_write && (WQ.next_process_index < WQ.SIZE)) {
            if (WQ.next_process_cycle <= current_core_cycle[WQ.entry[WQ.next_process_index].cpu])
                //process(channel, &WQ);
                process(&WQ);
        }
    //}

    // handle read
    // schedule new entry
    //for (uint32_t channel=0; channel<DRC_CHANNELS; channel++) {
        //if ((write_mode[channel] == 0) && (RQ.next_schedule_index < RQ.SIZE)) {
        if ((do_write == 0) && (RQ.next_schedule_index < RQ.SIZE)) {
            if (RQ.next_schedule_cycle <= current_core_cycle[RQ.entry[RQ.next_schedule_index].cpu])
                schedule(&RQ);
                //schedule(channel, &RQ);
        }
    //}

    // process DRC requests
    //for (uint32_t channel=0; channel<DRC_CHANNELS; channel++) {
        //if ((write_mode[channel] == 0) && (RQ.next_process_index < RQ.SIZE)) {
        if ((do_write == 0) && (RQ.next_process_index < RQ.SIZE)) {
            if (RQ.next_process_cycle <= current_core_cycle[RQ.entry[RQ.next_process_index].cpu])
                process(&RQ);
                //process(channel, &RQ);
        }
    //}
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
cmpb $0x0, 0x40944c(%rdi)
je 0xe5be
movl 0x40a8a4(%rbx), %ecx
testl %ecx, %ecx
je 0xe57a
movl 0x40c544(%rbx), %eax
testl %eax, %eax
setne %dl
cmpl $0xc, %ecx
setb %cl
testb %dl, %cl
jne 0xe57a
testl %eax, %eax
je 0xe618
cmpl $0xc, 0x409450(%rbx)
jb 0xe618
movb $0x0, 0x40944c(%rbx)
andl $0x0, 0x409450(%rbx)
leaq 0x40a870(%rbx), %rsi
leaq 0x6e91a(%rip), %rax     # 0x7ceb0
movq (%rax), %rax
movq %rax, 0x8a880(%rip)     # 0x98e20
movq %rbx, %rdi
callq 0xe294
xorl %eax, %eax
cmpq $0x4, %rax
je 0xe60b
addq $0x18, 0x409010(%rbx,%rax,8)
incq %rax
jmp 0xe5aa
cmpl $0x24, 0x40a8a4(%rbx)
jb 0xe60b
movb $0x1, 0x40944c(%rbx)
andl $0x0, 0x409450(%rbx)
leaq 0x6e8d4(%rip), %rax     # 0x7ceb0
movq (%rax), %rax
movq %rax, 0x8a832(%rip)     # 0x98e18
leaq 0x40c510(%rbx), %rsi
movq %rbx, %rdi
callq 0xe294
xorl %eax, %eax
cmpq $0x4, %rax
je 0xe60b
addq $0x18, 0x409010(%rbx,%rax,8)
incq %rax
jmp 0xe5f7
cmpb $0x0, 0x40944c(%rbx)
je 0xe6c1
leaq 0x40a870(%rbx), %r14
movl 0x40a8b0(%rbx), %eax
cmpl 0x40a890(%rbx), %eax
jae 0xe66a
movq 0x40a8c0(%rbx), %rcx
movq 0x40a908(%rbx), %rdx
imulq $0x380, %rax, %rax      # imm = 0x380
movl 0x330(%rdx,%rax), %eax
leaq 0x6e860(%rip), %rdx     # 0x7ceb0
cmpq (%rdx,%rax,8), %rcx
ja 0xe66a
movq %rbx, %rdi
movq %r14, %rsi
callq 0xe764
cmpb $0x0, 0x40944c(%rbx)
je 0xe6c1
movl 0x40a8b4(%rbx), %eax
cmpl 0x40a890(%rbx), %eax
jae 0xe74a
movq 0x40a8c8(%rbx), %rcx
movq 0x40a908(%rbx), %rdx
imulq $0x380, %rax, %rax      # imm = 0x380
movl 0x330(%rdx,%rax), %eax
leaq 0x6e811(%rip), %rdx     # 0x7ceb0
cmpq (%rdx,%rax,8), %rcx
ja 0xe74a
movq %rbx, %rdi
movq %r14, %rsi
callq 0xe9e6
cmpb $0x0, 0x40944c(%rbx)
jne 0xe74a
leaq 0x40c510(%rbx), %r14
movl 0x40c550(%rbx), %eax
cmpl 0x40c530(%rbx), %eax
jae 0xe713
movq 0x40c560(%rbx), %rcx
movq 0x40c5a8(%rbx), %rdx
imulq $0x380, %rax, %rax      # imm = 0x380
movl 0x330(%rdx,%rax), %eax
leaq 0x6e7b7(%rip), %rdx     # 0x7ceb0
cmpq (%rdx,%rax,8), %rcx
ja 0xe713
movq %rbx, %rdi
movq %r14, %rsi
callq 0xe764
cmpb $0x0, 0x40944c(%rbx)
jne 0xe74a
movl 0x40c554(%rbx), %eax
cmpl 0x40c530(%rbx), %eax
jae 0xe74a
movq 0x40c568(%rbx), %rcx
movq 0x40c5a8(%rbx), %rdx
imulq $0x380, %rax, %rax      # imm = 0x380
movl 0x330(%rdx,%rax), %eax
leaq 0x6e76c(%rip), %rdx     # 0x7ceb0
cmpq (%rdx,%rax,8), %rcx
jbe 0xe752
addq $0x8, %rsp
popq %rbx
popq %r14
retq
movq %rbx, %rdi
movq %r14, %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0xe9e6