// File: /workspace/github_cpp_makefile_star2_O3/CMU-SAFARI[P]MQSim/src/host/IO_Flow_Base.cpp
// Function: Host_Components::IO_Flow_Base::IO_Flow_Base(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>> const&, unsigned short, unsigned long, unsigned long, unsigned short, unsigned short, unsigned short, IO_Flow_Priority_Class::Priority, unsigned long, double, unsigned int, HostInterface_Types, Host_Components::PCIe_Root_Complex*, Host_Components::SATA_HBA*, bool, unsigned long, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
IO_Flow_Base::IO_Flow_Base(const sim_object_id_type &name, uint16_t flow_id, LHA_type start_lsa_on_device, LHA_type end_lsa_on_device, uint16_t io_queue_id,
						   uint16_t nvme_submission_queue_size, uint16_t nvme_completion_queue_size,
						   IO_Flow_Priority_Class::Priority priority_class, sim_time_type stop_time, double initial_occupancy_ratio, unsigned int total_requets_to_be_generated,
						   HostInterface_Types SSD_device_type, PCIe_Root_Complex *pcie_root_complex, SATA_HBA *sata_hba,
						   bool enabled_logging, sim_time_type logging_period, std::string logging_file_path) : MQSimEngine::Sim_Object(name), flow_id(flow_id), start_lsa_on_device(start_lsa_on_device), end_lsa_on_device(end_lsa_on_device), io_queue_id(io_queue_id),
																												priority_class(priority_class), stop_time(stop_time), initial_occupancy_ratio(initial_occupancy_ratio), total_requests_to_be_generated(total_requets_to_be_generated), SSD_device_type(SSD_device_type), pcie_root_complex(pcie_root_complex), sata_hba(sata_hba),
																												STAT_generated_request_count(0), STAT_generated_read_request_count(0), STAT_generated_write_request_count(0),
																												STAT_ignored_request_count(0),
																												STAT_serviced_request_count(0), STAT_serviced_read_request_count(0), STAT_serviced_write_request_count(0),
																												STAT_sum_device_response_time(0), STAT_sum_device_response_time_read(0), STAT_sum_device_response_time_write(0),
																												STAT_min_device_response_time(MAXIMUM_TIME), STAT_min_device_response_time_read(MAXIMUM_TIME), STAT_min_device_response_time_write(MAXIMUM_TIME),
																												STAT_max_device_response_time(0), STAT_max_device_response_time_read(0), STAT_max_device_response_time_write(0),
																												STAT_sum_request_delay(0), STAT_sum_request_delay_read(0), STAT_sum_request_delay_write(0),
																												STAT_min_request_delay(MAXIMUM_TIME), STAT_min_request_delay_read(MAXIMUM_TIME), STAT_min_request_delay_write(MAXIMUM_TIME),
																												STAT_max_request_delay(0), STAT_max_request_delay_read(0), STAT_max_request_delay_write(0),
																												STAT_transferred_bytes_total(0), STAT_transferred_bytes_read(0), STAT_transferred_bytes_write(0), progress(0), next_progress_step(0),
																												enabled_logging(enabled_logging), logging_period(logging_period), logging_file_path(logging_file_path)
{
	Host_IO_Request *t = NULL;

	switch (SSD_device_type)
	{
	case HostInterface_Types::NVME:
		for (uint16_t cmdid = 0; cmdid < (uint16_t)(0xffffffff); cmdid++)
		{
			available_command_ids.insert(cmdid);
		}
		for (uint16_t cmdid = 0; cmdid < nvme_submission_queue_size; cmdid++)
		{
			request_queue_in_memory.push_back(t);
		}
		nvme_queue_pair.Submission_queue_size = nvme_submission_queue_size;
		nvme_queue_pair.Submission_queue_head = 0;
		nvme_queue_pair.Submission_queue_tail = 0;
		nvme_queue_pair.Completion_queue_size = nvme_completion_queue_size;
		nvme_queue_pair.Completion_queue_head = 0;
		nvme_queue_pair.Completion_queue_tail = 0;

		//id = 0: admin queues, id = 1 to 8, normal I/O queues
		switch (io_queue_id)
		{
		case 0:
			throw std::logic_error("I/O queue id 0 is reserved for NVMe admin queues and should not be used for I/O flows");
			/*
						nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_0;
						nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_0;
						nvme_queue_pair.Completion_queue_tail = COMPLETION_QUEUE_REGISTER_0;*/
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_REGISTER_0;
			break;
		case 1:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_1;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_1;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_1;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_1;
			break;
		case 2:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_2;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_2;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_2;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_2;
			break;
		case 3:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_3;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_3;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_3;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_3;
			break;
		case 4:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_4;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_4;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_4;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_4;
			break;
		case 5:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_5;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_5;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_5;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_5;
			break;
		case 6:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_6;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_6;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_6;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_6;
			break;
		case 7:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_7;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_7;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_7;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_7;
			break;
		case 8:
			nvme_queue_pair.Submission_queue_memory_base_address = SUBMISSION_QUEUE_MEMORY_8;
			nvme_queue_pair.Submission_tail_register_address_on_device = SUBMISSION_QUEUE_REGISTER_8;
			nvme_queue_pair.Completion_queue_memory_base_address = COMPLETION_QUEUE_MEMORY_8;
			nvme_queue_pair.Completion_head_register_address_on_device = COMPLETION_QUEUE_REGISTER_8;
			break;
		default:
			break;
		}
		break;
	default:
		break;
	}
	}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movsd %xmm0, 0x10(%rsp)
movl %r9d, %ebp
movq %r8, %r14
movq %rcx, %r15
movl %edx, %r12d
movq %rdi, %rbx
movl 0x98(%rsp), %r13d
callq 0x164ce
leaq 0x4f8f9(%rip), %rax     # 0x6dbc8
movq %rax, (%rbx)
leaq 0x4f947(%rip), %rax     # 0x6dc20
movq %rax, 0x30(%rbx)
movw %r12w, 0x38(%rbx)
movsd 0x10(%rsp), %xmm0
movsd %xmm0, 0x40(%rbx)
movq 0x88(%rsp), %rax
movq %rax, 0x48(%rbx)
movl 0x90(%rsp), %eax
movl %eax, 0x50(%rbx)
movl %r13d, 0x54(%rbx)
movaps 0xa0(%rsp), %xmm0
movups %xmm0, 0x58(%rbx)
movq %r15, 0x68(%rbx)
movq %r14, 0x70(%rbx)
movl 0x80(%rsp), %eax
movl %eax, 0x78(%rbx)
movl %ebp, 0x10(%rsp)
movw %bp, 0xb0(%rbx)
leaq 0xb8(%rbx), %r14
leaq 0xc0(%rbx), %rcx
movl $0x0, 0xc0(%rbx)
xorl %eax, %eax
movq %rax, 0xc8(%rbx)
movq %rcx, 0xd0(%rbx)
movq %rcx, 0xd8(%rbx)
leaq 0xe8(%rbx), %r15
leaq 0x100(%rbx), %r13
xorps %xmm0, %xmm0
movups %xmm0, 0xe0(%rbx)
movups %xmm0, 0xf0(%rbx)
movq %r13, 0x108(%rbx)
movq %r13, 0x100(%rbx)
movq %rax, 0x110(%rbx)
leaq 0x148(%rbx), %rcx
movq %rcx, 0x118(%rbx)
movq $0x1, 0x120(%rbx)
movups %xmm0, 0x128(%rbx)
movl $0x3f800000, 0x138(%rbx) # imm = 0x3F800000
movups %xmm0, 0x140(%rbx)
movups %xmm0, 0x150(%rbx)
movups %xmm0, 0x15c(%rbx)
movq %rax, 0x180(%rbx)
movups %xmm0, 0x170(%rbx)
movq $-0x1, %rcx
movq %rcx, 0x198(%rbx)
pcmpeqd %xmm1, %xmm1
movdqu %xmm1, 0x188(%rbx)
movups %xmm0, 0x1c0(%rbx)
movups %xmm0, 0x1b0(%rbx)
movups %xmm0, 0x1a0(%rbx)
movq %rcx, 0x1e0(%rbx)
movdqu %xmm1, 0x1d0(%rbx)
movq %rax, 0x218(%rbx)
movups %xmm0, 0x208(%rbx)
movups %xmm0, 0x1f8(%rbx)
movups %xmm0, 0x1e8(%rbx)
movb 0xb0(%rsp), %al
movb %al, 0x220(%rbx)
movq 0xb8(%rsp), %rax
movq %rax, 0x228(%rbx)
leaq 0x238(%rbx), %r12
leaq 0x248(%rbx), %rax
movq %rax, 0x30(%rsp)
movq %rax, 0x238(%rbx)
movq 0xc0(%rsp), %rax
movq (%rax), %rsi
movq 0x8(%rax), %rdx
addq %rsi, %rdx
movq %r12, %rdi
callq 0xaf32
leaq 0x258(%rbx), %rdi
movq %rdi, 0x28(%rsp)
callq 0x75d0
movq $0x0, 0x20(%rsp)
cmpl $0x1, 0x98(%rsp)
jne 0x1e600
movq %r12, 0x18(%rsp)
leaq 0xe(%rsp), %r12
movw $0x0, (%r12)
movq %r14, %rdi
movq %r12, %rsi
callq 0x216d2
movzwl 0xe(%rsp), %eax
incl %eax
movw %ax, 0xe(%rsp)
cmpw $-0x1, %ax
jne 0x1e4c3
cmpw $0x0, 0x70(%rsp)
je 0x1e524
leaq 0x20(%rsp), %r12
movzwl 0x70(%rsp), %ebp
movq 0xf0(%rbx), %rsi
cmpq 0xf8(%rbx), %rsi
je 0x1e514
movq 0x20(%rsp), %rax
movq %rax, (%rsi)
addq $0x8, 0xf0(%rbx)
jmp 0x1e51f
movq %r15, %rdi
movq %r12, %rdx
callq 0x217ea
decw %bp
jne 0x1e4f2
movzwl 0x70(%rsp), %eax
movw %ax, 0x84(%rbx)
xorl %eax, %eax
movl %eax, 0x80(%rbx)
movzwl 0x78(%rsp), %ecx
movw %cx, 0x9c(%rbx)
movl %eax, 0x98(%rbx)
cmpw $0x8, 0x10(%rsp)
ja 0x1e600
movzwl 0x10(%rsp), %eax
leaq 0x3937e(%rip), %rcx     # 0x578e0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movaps 0x3924e(%rip), %xmm0    # 0x577c0
movdqa 0x39256(%rip), %xmm1    # 0x577d0
jmp 0x1e5f1
movaps 0x392bd(%rip), %xmm0    # 0x57840
movdqa 0x392c5(%rip), %xmm1    # 0x57850
jmp 0x1e5f1
movaps 0x3930c(%rip), %xmm0    # 0x578a0
movdqa 0x39314(%rip), %xmm1    # 0x578b0
jmp 0x1e5f1
movaps 0x392bb(%rip), %xmm0    # 0x57860
movdqa 0x392c3(%rip), %xmm1    # 0x57870
jmp 0x1e5f1
movaps 0x392ca(%rip), %xmm0    # 0x57880
movdqa 0x392d2(%rip), %xmm1    # 0x57890
jmp 0x1e5f1
movaps 0x39219(%rip), %xmm0    # 0x577e0
movdqa 0x39221(%rip), %xmm1    # 0x577f0
jmp 0x1e5f1
movaps 0x39248(%rip), %xmm0    # 0x57820
movdqa 0x39250(%rip), %xmm1    # 0x57830
jmp 0x1e5f1
movaps 0x39217(%rip), %xmm0    # 0x57800
movdqa 0x3921f(%rip), %xmm1    # 0x57810
movdqu %xmm1, 0x88(%rbx)
movups %xmm0, 0xa0(%rbx)
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl $0x10, %edi
callq 0x71d0
movq %rax, %r12
leaq 0x3930d(%rip), %rsi     # 0x57930
movq %rax, %rdi
callq 0x7500
movq 0x5098e(%rip), %rsi     # 0x6efc0
movq 0x50947(%rip), %rdx     # 0x6ef80
movq %r12, %rdi
callq 0x75e0
jmp 0x1e661
movq %rax, %rbp
movq %r12, %rdi
callq 0x72c0
jmp 0x1e664
movq %r12, 0x18(%rsp)
movq %rax, %rbp
jmp 0x1e66e
movq %rax, %rbp
jmp 0x1e682
jmp 0x1e661
movq %rax, %rbp
movq 0x28(%rsp), %rdi
callq 0x7530
movq 0x18(%rsp), %rax
movq (%rax), %rdi
cmpq 0x30(%rsp), %rdi
je 0x1e682
callq 0x7370
leaq 0x118(%rbx), %rdi
callq 0x21626
movq (%r13), %rdi
cmpq %r13, %rdi
je 0x1e6a7
movq (%rdi), %r12
callq 0x7370
movq %r12, %rdi
cmpq %r13, %r12
jne 0x1e697
movq (%r15), %rdi
testq %rdi, %rdi
je 0x1e6b4
callq 0x7370
movq %r14, %rdi
callq 0x21688
leaq 0x4f3a5(%rip), %rax     # 0x6da68
movq %rax, (%rbx)
movq 0x8(%rbx), %rdi
addq $0x18, %rbx
cmpq %rbx, %rdi
je 0x1e6d8
callq 0x7370
movq %rbp, %rdi
callq 0x7620