// File: /workspace/github_c_makefile_star2_O2/mmcco[P]sljit/sljit_src/sljitNativeX86_64.c
// Function: emit_x86_instruction
static u_char* emit_x86_instruction(struct sljit_compiler *compiler, int size,
	/* The reg or immediate operand. */
	int a, long imma,
	/* The general operand (not immediate). */
	int b, long immb)
{
	u_char *inst;
	u_char *buf_ptr;
	u_char rex = 0;
	int flags = size & ~0xf;
	int inst_size;

	/* The immediate operand must be 32 bit. */
	SLJIT_ASSERT(!(a & SLJIT_IMM) || compiler->mode32 || IS_HALFWORD(imma));
	/* Both cannot be switched on. */
	SLJIT_ASSERT((flags & (EX86_BIN_INS | EX86_SHIFT_INS)) != (EX86_BIN_INS | EX86_SHIFT_INS));
	/* Size flags not allowed for typed instructions. */
	SLJIT_ASSERT(!(flags & (EX86_BIN_INS | EX86_SHIFT_INS)) || (flags & (EX86_BYTE_ARG | EX86_HALF_ARG)) == 0);
	/* Both size flags cannot be switched on. */
	SLJIT_ASSERT((flags & (EX86_BYTE_ARG | EX86_HALF_ARG)) != (EX86_BYTE_ARG | EX86_HALF_ARG));
	/* SSE2 and immediate is not possible. */
	SLJIT_ASSERT(!(a & SLJIT_IMM) || !(flags & EX86_SSE2));
	SLJIT_ASSERT((flags & (EX86_PREF_F2 | EX86_PREF_F3)) != (EX86_PREF_F2 | EX86_PREF_F3)
		&& (flags & (EX86_PREF_F2 | EX86_PREF_66)) != (EX86_PREF_F2 | EX86_PREF_66)
		&& (flags & (EX86_PREF_F3 | EX86_PREF_66)) != (EX86_PREF_F3 | EX86_PREF_66));

	size &= 0xf;
	inst_size = size;

	if (!compiler->mode32 && !(flags & EX86_NO_REXW))
		rex |= REX_W;
	else if (flags & EX86_REX)
		rex |= REX;

	if (flags & (EX86_PREF_F2 | EX86_PREF_F3))
		inst_size++;
	if (flags & EX86_PREF_66)
		inst_size++;

	/* Calculate size of b. */
	inst_size += 1; /* mod r/m byte. */
	if (b & SLJIT_MEM) {
		if (!(b & OFFS_REG_MASK)) {
			if (NOT_HALFWORD(immb)) {
				if (emit_load_imm64(compiler, TMP_REG3, immb))
					return NULL;
				immb = 0;
				if (b & REG_MASK)
					b |= TO_OFFS_REG(TMP_REG3);
				else
					b |= TMP_REG3;
			}
			else if (reg_lmap[b & REG_MASK] == 4)
				b |= TO_OFFS_REG(SLJIT_SP);
		}

		if ((b & REG_MASK) == SLJIT_UNUSED)
			inst_size += 1 + sizeof(int); /* SIB byte required to avoid RIP based addressing. */
		else {
			if (reg_map[b & REG_MASK] >= 8)
				rex |= REX_B;

			if (immb != 0 && (!(b & OFFS_REG_MASK) || (b & OFFS_REG_MASK) == TO_OFFS_REG(SLJIT_SP))) {
				/* Immediate operand. */
				if (immb <= 127 && immb >= -128)
					inst_size += sizeof(s_char);
				else
					inst_size += sizeof(int);
			}
			else if (reg_lmap[b & REG_MASK] == 5)
				inst_size += sizeof(s_char);

			if ((b & OFFS_REG_MASK) != SLJIT_UNUSED) {
				inst_size += 1; /* SIB byte. */
				if (reg_map[OFFS_REG(b)] >= 8)
					rex |= REX_X;
			}
		}
	}
	else if (!(flags & EX86_SSE2_OP2) && reg_map[b] >= 8)
		rex |= REX_B;

	if (a & SLJIT_IMM) {
		if (flags & EX86_BIN_INS) {
			if (imma <= 127 && imma >= -128) {
				inst_size += 1;
				flags |= EX86_BYTE_ARG;
			} else
				inst_size += 4;
		}
		else if (flags & EX86_SHIFT_INS) {
			imma &= compiler->mode32 ? 0x1f : 0x3f;
			if (imma != 1) {
				inst_size ++;
				flags |= EX86_BYTE_ARG;
			}
		} else if (flags & EX86_BYTE_ARG)
			inst_size++;
		else if (flags & EX86_HALF_ARG)
			inst_size += sizeof(short);
		else
			inst_size += sizeof(int);
	}
	else {
		SLJIT_ASSERT(!(flags & EX86_SHIFT_INS) || a == SLJIT_PREF_SHIFT_REG);
		/* reg_map[SLJIT_PREF_SHIFT_REG] is less than 8. */
		if (!(flags & EX86_SSE2_OP1) && reg_map[a] >= 8)
			rex |= REX_R;
	}

	if (rex)
		inst_size++;

	inst = ensure_buf(compiler, 1 + inst_size);
	if (!inst)
		return NULL;

	/* Encoding the byte. */
	INC_SIZE(inst_size);
	if (flags & EX86_PREF_F2)
		*inst++ = 0xf2;
	if (flags & EX86_PREF_F3)
		*inst++ = 0xf3;
	if (flags & EX86_PREF_66)
		*inst++ = 0x66;
	if (rex)
		*inst++ = rex;
	buf_ptr = inst + size;

	/* Encode mod/rm byte. */
	if (!(flags & EX86_SHIFT_INS)) {
		if ((flags & EX86_BIN_INS) && (a & SLJIT_IMM))
			*inst = (flags & EX86_BYTE_ARG) ? GROUP_BINARY_83 : GROUP_BINARY_81;

		if ((a & SLJIT_IMM) || (a == 0))
			*buf_ptr = 0;
		else if (!(flags & EX86_SSE2_OP1))
			*buf_ptr = reg_lmap[a] << 3;
		else
			*buf_ptr = a << 3;
	}
	else {
		if (a & SLJIT_IMM) {
			if (imma == 1)
				*inst = GROUP_SHIFT_1;
			else
				*inst = GROUP_SHIFT_N;
		} else
			*inst = GROUP_SHIFT_CL;
		*buf_ptr = 0;
	}

	if (!(b & SLJIT_MEM))
		*buf_ptr++ |= MOD_REG + ((!(flags & EX86_SSE2_OP2)) ? reg_lmap[b] : b);
	else if ((b & REG_MASK) != SLJIT_UNUSED) {
		if ((b & OFFS_REG_MASK) == SLJIT_UNUSED || (b & OFFS_REG_MASK) == TO_OFFS_REG(SLJIT_SP)) {
			if (immb != 0 || reg_lmap[b & REG_MASK] == 5) {
				if (immb <= 127 && immb >= -128)
					*buf_ptr |= 0x40;
				else
					*buf_ptr |= 0x80;
			}

			if ((b & OFFS_REG_MASK) == SLJIT_UNUSED)
				*buf_ptr++ |= reg_lmap[b & REG_MASK];
			else {
				*buf_ptr++ |= 0x04;
				*buf_ptr++ = reg_lmap[b & REG_MASK] | (reg_lmap[OFFS_REG(b)] << 3);
			}

			if (immb != 0 || reg_lmap[b & REG_MASK] == 5) {
				if (immb <= 127 && immb >= -128)
					*buf_ptr++ = immb; /* 8 bit displacement. */
				else {
					*(int*)buf_ptr = immb; /* 32 bit displacement. */
					buf_ptr += sizeof(int);
				}
			}
		}
		else {
			if (reg_lmap[b & REG_MASK] == 5)
				*buf_ptr |= 0x40;
			*buf_ptr++ |= 0x04;
			*buf_ptr++ = reg_lmap[b & REG_MASK] | (reg_lmap[OFFS_REG(b)] << 3) | (immb << 6);
			if (reg_lmap[b & REG_MASK] == 5)
				*buf_ptr++ = 0;
		}
	}
	else {
		*buf_ptr++ |= 0x04;
		*buf_ptr++ = 0x25;
		*(int*)buf_ptr = immb; /* 32 bit displacement. */
		buf_ptr += sizeof(int);
	}

	if (a & SLJIT_IMM) {
		if (flags & EX86_BYTE_ARG)
			*buf_ptr = imma;
		else if (flags & EX86_HALF_ARG)
			*(short*)buf_ptr = imma;
		else if (!(flags & EX86_SHIFT_INS))
			*(int*)buf_ptr = imma;
	}

	return !(flags & EX86_SHIFT_INS) ? inst : (inst + 1);
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movl %r8d, %r12d
movq %rcx, %r8
movl %esi, %ebp
testb $0x40, %dl
je 0x1408e
movslq %r8d, %rax
cmpq %r8, %rax
je 0x1408e
cmpl $0x0, 0x70(%rdi)
je 0x14614
movl %ebp, %ecx
movl %ebp, %eax
notl %eax
andl $0x30, %ecx
je 0x140ba
cmpl $0x30, %ecx
je 0x14622
testw $0x300, %bp             # imm = 0x300
je 0x140c4
leaq 0xd219(%rip), %rdi      # 0x212c9
movl $0x16b, %esi            # imm = 0x16B
jmp 0x1464a
testw $0x300, %ax             # imm = 0x300
je 0x14630
testb $0x40, %dl
sete %cl
testw $0x6000, %bp            # imm = 0x6000
sete %sil
orb %cl, %sil
je 0x145f8
movq %rdx, 0x8(%rsp)
testw $0x1400, %ax            # imm = 0x1400
je 0x14606
movl %ebp, %eax
andl $0x1800, %eax           # imm = 0x1800
cmpl $0x1800, %eax           # imm = 0x1800
je 0x14606
movl %ebp, %ecx
andl $0xc00, %ecx            # imm = 0xC00
cmpl $0xc00, %ecx            # imm = 0xC00
je 0x14606
movl %ebp, %esi
andl $0xf, %esi
movl %ebp, %ecx
andl $0x80, %ecx
movl %ebp, %edx
andb $0x40, %dl
orl 0x70(%rdi), %ecx
movzbl %dl, %ecx
pushq $0x48
popq %rbx
cmovnel %ecx, %ebx
xorl %r14d, %r14d
testl %eax, %eax
setne %r14b
btl $0xa, %ebp
movl %esi, 0x1c(%rsp)
adcl %esi, %r14d
leal 0x1(%r14), %r13d
movzbl %bl, %r15d
testb %r12b, %r12b
js 0x14174
btl $0xe, %ebp
jb 0x14213
movl %r15d, %eax
orb $0x41, %al
movl $0x10ef0, %ecx          # imm = 0x10EF0
btq %r12, %rcx
movzbl %al, %ebx
cmovael %r15d, %ebx
jmp 0x14213
testw $0x3f00, %r12w          # imm = 0x3F00
je 0x141cc
movl %r12d, %eax
andl $0x3f, %eax
je 0x1420c
movl %r15d, %ecx
orb $0x41, %cl
movl $0x10ef0, %edx          # imm = 0x10EF0
btq %rax, %rdx
movzbl %cl, %ebx
cmovael %r15d, %ebx
movl %r12d, %eax
andl $0x3f00, %eax           # imm = 0x3F00
testq %r9, %r9
je 0x1421a
cmpl $0xd00, %eax            # imm = 0xD00
je 0x141b6
testl %eax, %eax
jne 0x1421a
movsbq %r9b, %rcx
cmpq %r9, %rcx
jne 0x1424d
addl $0x2, %r14d
jmp 0x14251
movslq %r9d, %rax
cmpq %r9, %rax
je 0x1422d
movq %r8, 0x10(%rsp)
pushq $0x10
popq %rsi
movq %rdi, 0x20(%rsp)
movq %r9, %rdx
callq 0x14aa1
testl %eax, %eax
jne 0x1434c
movq 0x20(%rsp), %rdi
testb $0x3f, %r12b
je 0x145e7
orl $0x1000, %r12d          # imm = 0x1000
jmp 0x145eb
addl $0x6, %r14d
movl %r14d, %r13d
movq 0x8(%rsp), %rsi
jmp 0x14276
movl %r12d, %ecx
andl $0x3e, %ecx
addl $0x2, %r14d
cmpl $0x8, %ecx
cmovel %r14d, %r13d
jmp 0x14254
movl %r12d, %eax
andl $0x3f, %eax
cmpl $0xd, %eax
je 0x14241
cmpl $0x7, %eax
jne 0x1417c
orl $0xd00, %r12d           # imm = 0xD00
jmp 0x1417c
addl $0x5, %r14d
movl %r14d, %r13d
movq 0x8(%rsp), %rsi
testl %eax, %eax
je 0x14276
incl %r13d
movl %r12d, %eax
shrl $0x8, %eax
movzbl %bl, %ecx
orb $0x42, %bl
btq %rax, %rdx
movzbl %bl, %ebx
cmovael %ecx, %ebx
movq %r9, 0x10(%rsp)
testb $0x40, %sil
je 0x142a6
testb $0x10, %bpl
jne 0x142db
testb $0x20, %bpl
jne 0x142ed
btl $0x8, %ebp
jb 0x14319
btl $0x9, %ebp
jae 0x142e4
movq %r8, %r14
addl $0x2, %r13d
jmp 0x1431f
testb $0x20, %bpl
sete %al
cmpl $0x3, %esi
sete %cl
orb %al, %cl
je 0x1463e
movq %r8, %r14
btl $0xd, %ebp
jb 0x1431f
movzbl %bl, %eax
orb $0x44, %bl
movl $0x10ef0, %ecx          # imm = 0x10EF0
btq %rsi, %rcx
movzbl %bl, %ebx
cmovael %eax, %ebx
jmp 0x1431f
movsbq %r8b, %rax
cmpq %r8, %rax
je 0x1430b
movq %r8, %r14
addl $0x4, %r13d
jmp 0x1431f
xorl %eax, %eax
cmpl $0x0, 0x70(%rdi)
sete %al
shll $0x5, %eax
orl $0x1f, %eax
andl %eax, %r8d
cmpl $0x1, %r8d
jne 0x1430b
pushq $0x1
popq %r14
jmp 0x1431f
movq %r8, %r14
incl %r13d
orl $0x100, %ebp            # imm = 0x100
jmp 0x1431f
movq %r8, %r14
incl %r13d
cmpb $0x1, %bl
sbbl $-0x1, %r13d
leal 0x1(%r13), %esi
movq %rdi, %r15
callq 0x1354f
testq %rax, %rax
je 0x1434c
movb %r13b, (%rax)
movl %r13d, %ecx
addq %rcx, 0x60(%r15)
btl $0xb, %ebp
jb 0x14353
incq %rax
jmp 0x1435b
xorl %eax, %eax
jmp 0x145d8
movb $-0xe, 0x1(%rax)
addq $0x2, %rax
movq %r14, %r11
movq 0x8(%rsp), %r14
btl $0xc, %ebp
jae 0x1436f
movb $-0xd, (%rax)
incq %rax
btl $0xa, %ebp
jae 0x1437b
movb $0x66, (%rax)
incq %rax
testb %bl, %bl
je 0x14384
movb %bl, (%rax)
incq %rax
movl 0x1c(%rsp), %edx
movl %ebp, %ecx
andl $0x20, %ecx
jne 0x143bc
testb $0x40, %r14b
sete %sil
testb $0x10, %bpl
sete %dil
orb %sil, %dil
jne 0x14475
movl %ebp, %esi
shrl $0x8, %esi
andl $0x1, %esi
addb %sil, %sil
orb $-0x7f, %sil
movb %sil, (%rax)
jmp 0x143df
cmpq $0x1, %r11
sete %sil
shlb $0x4, %sil
orb $-0x3f, %sil
movzbl %sil, %esi
testb $0x40, %r14b
movl $0xd3, %edi
cmovnel %esi, %edi
movb %dil, (%rax)
xorl %esi, %esi
addq %rax, %rdx
testb %r12b, %r12b
js 0x1440f
btl $0xe, %ebp
jb 0x143fd
movslq %r12d, %rdi
leaq 0xcdb7(%rip), %r8       # 0x211b0
movb (%rdi,%r8), %r12b
addb $-0x40, %r12b
orb %sil, %r12b
movb %r12b, (%rdx)
incq %rdx
jmp 0x145ab
movl %r12d, %edi
andl $0x3f, %edi
je 0x144af
movl %r12d, %r9d
andl $0x3f00, %r9d           # imm = 0x3F00
cmpl $0xd00, %r9d            # imm = 0xD00
je 0x14437
testl %r9d, %r9d
jne 0x144cb
movq 0x10(%rsp), %rbx
testq %rbx, %rbx
setne %r10b
movl %r12d, %r8d
andl $0x3e, %r8d
cmpl $0x8, %r8d
sete %r8b
orb %r10b, %r8b
cmpb $0x1, %r8b
jne 0x14542
movsbq %bl, %r10
cmpq %rbx, %r10
jne 0x1453e
orb $0x40, %sil
jmp 0x14542
movl %r14d, %esi
andl $0x40, %esi
shrl $0x6, %esi
testl %r14d, %r14d
sete %dil
orb %sil, %dil
jne 0x143df
btl $0xd, %ebp
jb 0x14531
movslq %r14d, %rsi
leaq 0xcd0e(%rip), %rdi      # 0x211b0
movb (%rsi,%rdi), %sil
shlb $0x3, %sil
jmp 0x143e1
orb $0x4, %sil
movb %sil, (%rdx)
movb $0x25, 0x1(%rdx)
movq 0x10(%rsp), %rsi
movl %esi, 0x2(%rdx)
addq $0x6, %rdx
jmp 0x145ab
leaq 0xccde(%rip), %r9       # 0x211b0
movl %r12d, %r8d
andl $0x3e, %r8d
movzbl %sil, %r10d
orb $0x40, %sil
cmpl $0x8, %r8d
movzbl %sil, %esi
cmovnel %r10d, %esi
orb $0x4, %sil
movzbl (%rdi,%r9), %edi
shrl $0x8, %r12d
andl $0x3f, %r12d
movzbl (%r12,%r9), %r9d
shll $0x3, %r9d
movq 0x10(%rsp), %r10
shll $0x6, %r10d
orl %edi, %r10d
orl %r9d, %r10d
movb %sil, (%rdx)
movb %r10b, 0x1(%rdx)
cmpl $0x8, %r8d
jne 0x145a7
movb $0x0, 0x2(%rdx)
addq $0x3, %rdx
jmp 0x145ab
leal (,%r14,8), %esi
jmp 0x143e1
orb $-0x80, %sil
testl %r9d, %r9d
je 0x1456f
leaq 0xcc62(%rip), %r9       # 0x211b0
shrl $0x8, %r12d
andl $0x3f, %r12d
movb (%r12,%r9), %r10b
shlb $0x3, %r10b
orb (%rdi,%r9), %r10b
leaq 0x2(%rdx), %rdi
movb %r10b, 0x1(%rdx)
movb $0x4, %r9b
jmp 0x1457e
leaq 0xcc3a(%rip), %r9       # 0x211b0
movb (%rdi,%r9), %r9b
leaq 0x1(%rdx), %rdi
orb %r9b, %sil
movb %sil, (%rdx)
testb %r8b, %r8b
je 0x145ae
movq 0x10(%rsp), %rsi
movsbq %sil, %rdx
cmpq %rsi, %rdx
jne 0x1459f
movb %sil, (%rdi)
incq %rdi
jmp 0x145ae
movl %esi, (%rdi)
addq $0x4, %rdi
jmp 0x145ae
addq $0x2, %rdx
movq %rdx, %rdi
testb $0x40, %r14b
je 0x145d2
btl $0x8, %ebp
jb 0x145c9
btl $0x9, %ebp
jb 0x145ce
testl %ecx, %ecx
jne 0x145d2
movl %r11d, (%rdi)
jmp 0x145d2
movb %r11b, (%rdi)
jmp 0x145d2
movw %r11w, (%rdi)
shrl $0x5, %ecx
addq %rcx, %rax
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
orl $0x10, %r12d
xorl %r9d, %r9d
movq 0x10(%rsp), %r8
jmp 0x1417c
leaq 0xccca(%rip), %rdi      # 0x212c9
movl $0x16f, %esi            # imm = 0x16F
jmp 0x1464a
leaq 0xccbc(%rip), %rdi      # 0x212c9
movl $0x172, %esi            # imm = 0x172
jmp 0x1464a
leaq 0xccae(%rip), %rdi      # 0x212c9
movl $0x167, %esi            # imm = 0x167
jmp 0x1464a
leaq 0xcca0(%rip), %rdi      # 0x212c9
movl $0x169, %esi            # imm = 0x169
jmp 0x1464a
leaq 0xcc92(%rip), %rdi      # 0x212c9
movl $0x16d, %esi            # imm = 0x16D
jmp 0x1464a
leaq 0xcc84(%rip), %rdi      # 0x212c9
movl $0x1c2, %esi            # imm = 0x1C2
xorl %eax, %eax
callq 0x2080
callq 0x2040