// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/ssd/TSU_Priority_OutOfOrder.cpp
// Function: SSD_Components::TSU_Priority_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip*)
bool TSU_Priority_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip *chip)
{
    Flash_Transaction_Queue *sourceQueue1 = NULL, *sourceQueue2 = NULL;

    //If flash transactions related to GC are prioritzed (non-preemptive execution mode of GC), then GC queues are checked first
    if (ftl->GC_and_WL_Unit->GC_is_in_urgent_mode(chip))
    {
        if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
            sourceQueue2 = get_next_write_service_queue(chip);
        }
        else if (GCEraseTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            return false;
        }
        else
        {
            sourceQueue1 = get_next_write_service_queue(chip);
            if(sourceQueue1 == NULL)
            {
                return false;
            }
        }
    }
    else
    {
        //If GC is currently executed in the preemptive mode, then user IO transaction queues are checked first
        sourceQueue1 = get_next_write_service_queue(chip);
        if (sourceQueue1 != NULL)
        {
            if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
            {
                sourceQueue2 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
            }
        }
        else if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
        }
        else
        {
            return false;
        }
    }

    bool suspensionRequired = false;
    ChipStatus cs = _NVMController->GetChipStatus(chip);
    switch (cs)
    {
    case ChipStatus::IDLE:
        break;
    case ChipStatus::ERASING:
        if (!eraseSuspensionEnabled || _NVMController->HasSuspendedCommand(chip))
            return false;
        if (_NVMController->Expected_finish_time(chip) - Simulator->Time() < eraseReasonableSuspensionTimeForWrite)
            return false;
        suspensionRequired = true;
    default:
        return false;
    }

    issue_command_to_chip(sourceQueue1, sourceQueue2, Transaction_Type::WRITE, suspensionRequired);

    return true;
}

// Assembly:
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x30(%rdi), %rax
movq 0x48(%rax), %rdi
movq (%rdi), %rax
callq *0x20(%rax)
testb %al, %al
je 0x3fa29
movq 0xc8(%r14), %rcx
movl 0x2c(%rbx), %eax
movl 0x30(%rbx), %edx
movq (%rcx,%rax,8), %r12
imulq $0x108, %rdx, %rcx      # imm = 0x108
cmpq $0x0, 0x18(%r12,%rcx)
je 0x3fa65
addq %rcx, %r12
movq %r14, %rdi
movq %rbx, %rsi
callq 0x3f8c0
movq %rax, %r15
jmp 0x3fa9e
movq %r14, %rdi
movq %rbx, %rsi
callq 0x3f8c0
movq %rax, %r12
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
movq 0xc8(%r14), %rdx
movq (%rdx,%rcx,8), %r15
movq 0x18(%r15,%rax), %rcx
testq %r12, %r12
je 0x3fa90
addq %rax, %r15
testq %rcx, %rcx
cmoveq %rcx, %r15
jmp 0x3fa9e
movq 0xd0(%r14), %rdx
movq (%rdx,%rax,8), %rax
cmpq $0x0, 0x18(%rax,%rcx)
jne 0x3fae6
movq %r14, %rdi
movq %rbx, %rsi
callq 0x3f8c0
xorl %r15d, %r15d
testq %rax, %rax
je 0x3fb02
movq %rax, %r12
jmp 0x3fa9e
testq %rcx, %rcx
je 0x3fae6
addq %rax, %r15
movq %r15, %r12
xorl %r15d, %r15d
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x48(%rax)
testl %eax, %eax
je 0x3faeb
cmpl $0x6, %eax
jne 0x3fae6
cmpb $0x1, 0x54(%r14)
jne 0x3fae6
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x40(%rax)
testb %al, %al
jne 0x3fae6
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x50(%rax)
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
xorl %r15d, %r15d
jmp 0x3fb02
pushq $0x1
popq %rcx
movq %r14, %rdi
movq %r12, %rsi
movq %r15, %rdx
xorl %r8d, %r8d
callq 0x3c064
movb $0x1, %r15b
movl %r15d, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop