// File: CMU-SAFARI[P]MQSim/src/ssd/TSU_Priority_OutOfOrder.cpp
// Function: SSD_Components::TSU_Priority_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip*)
bool TSU_Priority_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip *chip)
{
    Flash_Transaction_Queue *sourceQueue1 = NULL, *sourceQueue2 = NULL;

    //If flash transactions related to GC are prioritzed (non-preemptive execution mode of GC), then GC queues are checked first
    if (ftl->GC_and_WL_Unit->GC_is_in_urgent_mode(chip))
    {
        if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
            sourceQueue2 = get_next_write_service_queue(chip);
        }
        else if (GCEraseTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            return false;
        }
        else
        {
            sourceQueue1 = get_next_write_service_queue(chip);
            if(sourceQueue1 == NULL)
            {
                return false;
            }
        }
    }
    else
    {
        //If GC is currently executed in the preemptive mode, then user IO transaction queues are checked first
        sourceQueue1 = get_next_write_service_queue(chip);
        if (sourceQueue1 != NULL)
        {
            if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
            {
                sourceQueue2 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
            }
        }
        else if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
        }
        else
        {
            return false;
        }
    }

    bool suspensionRequired = false;
    ChipStatus cs = _NVMController->GetChipStatus(chip);
    switch (cs)
    {
    case ChipStatus::IDLE:
        break;
    case ChipStatus::ERASING:
        if (!eraseSuspensionEnabled || _NVMController->HasSuspendedCommand(chip))
            return false;
        if (_NVMController->Expected_finish_time(chip) - Simulator->Time() < eraseReasonableSuspensionTimeForWrite)
            return false;
        suspensionRequired = true;
    default:
        return false;
    }

    issue_command_to_chip(sourceQueue1, sourceQueue2, Transaction_Type::WRITE, suspensionRequired);

    return true;
}

// Assembly:
subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp)
movq $0x0, 0x28(%rsp)
movq $0x0, 0x20(%rsp)
movq 0x30(%rax), %rax
movq 0x48(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
callq *0x20(%rax)
testb $0x1, %al
jne 0xa3ab6
jmp 0xa3ba1
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0xa3b2f
movq 0x10(%rsp), %rdi
movq 0xc8(%rdi), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x28(%rsp)
movq 0x30(%rsp), %rsi
callq 0xa3760
movq %rax, 0x20(%rsp)
jmp 0xa3b9c
movq 0x10(%rsp), %rax
movq 0xd0(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0xa3b72
movb $0x0, 0x47(%rsp)
jmp 0xa3d7b
movq 0x10(%rsp), %rdi
movq 0x30(%rsp), %rsi
callq 0xa3760
movq %rax, 0x28(%rsp)
cmpq $0x0, 0x28(%rsp)
jne 0xa3b98
movb $0x0, 0x47(%rsp)
jmp 0xa3d7b
jmp 0xa3b9a
jmp 0xa3b9c
jmp 0xa3c9f
movq 0x10(%rsp), %rdi
movq 0x30(%rsp), %rsi
callq 0xa3760
movq %rax, 0x28(%rsp)
cmpq $0x0, 0x28(%rsp)
je 0xa3c27
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0xa3c25
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x20(%rsp)
jmp 0xa3c9d
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0xa3c91
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x28(%rsp)
jmp 0xa3c9b
movb $0x0, 0x47(%rsp)
jmp 0xa3d7b
jmp 0xa3c9d
jmp 0xa3c9f
movq 0x10(%rsp), %rax
movb $0x0, 0x1f(%rsp)
movq 0x38(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
movq 0x48(%rax), %rax
callq *%rax
movl %eax, 0x18(%rsp)
movl 0x18(%rsp), %eax
movl %eax, 0xc(%rsp)
testl %eax, %eax
je 0xa3cd8
jmp 0xa3ccd
movl 0xc(%rsp), %eax
subl $0x6, %eax
je 0xa3cda
jmp 0xa3d4c
jmp 0xa3d53
movq 0x10(%rsp), %rax
testb $0x1, 0x54(%rax)
je 0xa3cff
movq 0x10(%rsp), %rax
movq 0x38(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
callq *0x40(%rax)
testb $0x1, %al
jne 0xa3cff
jmp 0xa3d06
movb $0x0, 0x47(%rsp)
jmp 0xa3d7b
movq 0x10(%rsp), %rax
movq 0x38(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
callq *0x50(%rax)
movq %rax, (%rsp)
callq 0x46500
movq %rax, %rdi
callq 0x46c50
movq 0x10(%rsp), %rcx
movq %rax, %rdx
movq (%rsp), %rax
subq %rdx, %rax
cmpq 0x68(%rcx), %rax
jae 0xa3d47
movb $0x0, 0x47(%rsp)
jmp 0xa3d7b
movb $0x1, 0x1f(%rsp)
movb $0x0, 0x47(%rsp)
jmp 0xa3d7b
movq 0x10(%rsp), %rdi
movq 0x28(%rsp), %rsi
movq 0x20(%rsp), %rdx
movb 0x1f(%rsp), %al
movl $0x1, %ecx
andb $0x1, %al
movzbl %al, %r8d
callq 0x9b2a0
movb $0x1, 0x47(%rsp)
movb 0x47(%rsp), %al
andb $0x1, %al
addq $0x48, %rsp
retq
nopw %cs:(%rax,%rax)