LLM4Binary/decompile-bench-makefile huggingface dataset:
// File: gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::deallocate(unsigned long)
void
HybridCache::deallocate(uint64_t block_addr)
{
	entete_debug();
	DPRINTF(DebugCache , "DEALLOCATE %#lx\n", block_addr);
	map<uint64_t,HybridLocation>::iterator it = m_tag_index.find(block_addr);	
	
	if(it != m_tag_index.end()){

		int id_set = blockAddressToCacheSet(block_addr);

		HybridLocation loc = it->second;
		CacheEntry* current = NULL; 

		if(loc.m_inNVM)
			current = m_tableNVM[id_set][loc.m_way]; 		
		else
			current = m_tableSRAM[id_set][loc.m_way]; 		

		updateStatsDeallocate(current);
		current->initEntry();
				
		m_tag_index.erase(it);	

	}
}

// Assembly:
subq $0x98, %rsp
movq %rdi, 0x90(%rsp)
movq %rsi, 0x88(%rsp)
movq 0x90(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0x38560
leaq 0x67(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x56a0
movq 0x10(%rsp), %rdx
leaq 0x37eca(%rip), %rsi     # 0x7286e
leaq 0x68(%rsp), %rdi
callq 0x5530
jmp 0x3a9b0
leaq 0x59639(%rip), %rdi     # 0x93ff0
addq $0x8, %rdi
leaq 0x68(%rsp), %rsi
callq 0x33a00
movq %rax, (%rsp)
jmp 0x3a9cb
leaq 0x68(%rsp), %rdi
callq 0x5768
leaq 0x67(%rsp), %rdi
callq 0x53e0
movq (%rsp), %rax
cmpq $0x0, %rax
je 0x3aa38
movq 0x88(%rsp), %rsi
leaq 0x38022(%rip), %rdi     # 0x72a1a
movb $0x0, %al
callq 0x5060
jmp 0x3aa38
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
jmp 0x3aa29
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
leaq 0x68(%rsp), %rdi
callq 0x5768
leaq 0x67(%rsp), %rdi
callq 0x53e0
jmp 0x3ab4c
movq 0x8(%rsp), %rdi
addq $0x38, %rdi
leaq 0x88(%rsp), %rsi
callq 0x3d9b0
movq 0x8(%rsp), %rdi
movq %rax, 0x48(%rsp)
addq $0x38, %rdi
callq 0x3db60
movq %rax, 0x40(%rsp)
leaq 0x48(%rsp), %rdi
leaq 0x40(%rsp), %rsi
callq 0x3db40
testb $0x1, %al
jne 0x3aa7e
jmp 0x3ab44
movq 0x8(%rsp), %rdi
movq 0x88(%rsp), %rsi
callq 0x3ab60
movl %eax, 0x3c(%rsp)
leaq 0x48(%rsp), %rdi
callq 0x3d9e0
movq 0x8(%rax), %rax
movq %rax, 0x34(%rsp)
movq $0x0, 0x28(%rsp)
testb $0x1, 0x38(%rsp)
je 0x3aae1
movq 0x8(%rsp), %rdi
addq $0x8, %rdi
movslq 0x3c(%rsp), %rsi
callq 0xf9a0
movq %rax, %rdi
movslq 0x34(%rsp), %rsi
callq 0xf9c0
movq (%rax), %rax
movq %rax, 0x28(%rsp)
jmp 0x3ab09
movq 0x8(%rsp), %rdi
addq $0x20, %rdi
movslq 0x3c(%rsp), %rsi
callq 0xf9a0
movq %rax, %rdi
movslq 0x34(%rsp), %rsi
callq 0xf9c0
movq (%rax), %rax
movq %rax, 0x28(%rsp)
movq 0x8(%rsp), %rdi
movq 0x28(%rsp), %rsi
callq 0x37fc0
movq 0x28(%rsp), %rdi
callq 0x3dbd0
movq 0x8(%rsp), %rdi
addq $0x38, %rdi
movq 0x48(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rsi
callq 0x3db90
movq %rax, 0x18(%rsp)
addq $0x98, %rsp
retq
movq 0x58(%rsp), %rdi
callq 0x5690
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::blockAddressToCacheSet(unsigned long)
int 
HybridCache::blockAddressToCacheSet(uint64_t block_addr) 
{
	uint64_t a =block_addr;
	a = bitRemove(a , m_end_index,64);
	
	a = a >> (m_start_index+1);
	assert(a < (unsigned int)m_nb_set);
	
	return (int)a;
}

// Assembly:
subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x18(%rsp), %rcx
movq %rcx, 0x10(%rsp)
movq 0x10(%rsp), %rdi
movl 0x98(%rax), %esi
movl $0x40, %edx
callq 0x655b0
movq 0x8(%rsp), %rcx
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rax
movl 0x94(%rcx), %ecx
addl $0x1, %ecx
movl %ecx, %ecx
shrq %cl, %rax
movq 0x8(%rsp), %rcx
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rax
movl 0xac(%rcx), %ecx
cmpq %rcx, %rax
jae 0x3abd0
jmp 0x3abef
leaq 0x37550(%rip), %rdi     # 0x72127
leaq 0x37b74(%rip), %rsi     # 0x72752
movl $0x2e7, %edx            # imm = 0x2E7
leaq 0x38014(%rip), %rcx     # 0x72bfe
callq 0x5260
movq 0x10(%rsp), %rax
addq $0x28, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::isPrefetchBlock(unsigned long)
bool
HybridCache::isPrefetchBlock(uint64_t addr)
{
	CacheEntry* entry = getEntry(addr);
	if(entry != NULL)
		return entry->isPrefetch;
	return false;
}

// Assembly:
subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x18(%rsp), %rdi
movq 0x10(%rsp), %rsi
callq 0x387e0
movq %rax, 0x8(%rsp)
cmpq $0x0, 0x8(%rsp)
je 0x3b6ad
movq 0x8(%rsp), %rax
movb 0x14b(%rax), %al
andb $0x1, %al
movb %al, 0x27(%rsp)
jmp 0x3b6b2
movb $0x0, 0x27(%rsp)
movb 0x27(%rsp), %al
andb $0x1, %al
addq $0x28, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Cache.hh
// Function: CacheEntry::CacheEntry()
CacheEntry() { 
			isNVM = false;
			isLearning_policy = false;
			isLearning_weight = false;
			isLearning = false;
			initEntry();
		}

// Assembly:
subq $0x68, %rsp
movq %rdi, 0x60(%rsp)
movq 0x60(%rsp), %rdi
movq %rdi, 0x48(%rsp)
addq $0x48, %rdi
movq %rdi, (%rsp)
callq 0xe8d0
movq 0x48(%rsp), %rdi
addq $0x60, %rdi
movq %rdi, 0x8(%rsp)
callq 0xe8d0
movq 0x48(%rsp), %rdi
addq $0x78, %rdi
movq %rdi, 0x10(%rsp)
callq 0xe8d0
movq 0x48(%rsp), %rdi
addq $0x90, %rdi
movq %rdi, 0x18(%rsp)
callq 0xe8d0
movq 0x48(%rsp), %rdi
addq $0xa8, %rdi
movq %rdi, 0x20(%rsp)
callq 0x21100
movq 0x48(%rsp), %rdi
addq $0xd0, %rdi
movq %rdi, 0x28(%rsp)
callq 0x3e170
movq 0x48(%rsp), %rdi
addq $0xe8, %rdi
movq %rdi, 0x30(%rsp)
callq 0x3e180
movq 0x48(%rsp), %rdi
addq $0x100, %rdi            # imm = 0x100
movq %rdi, 0x38(%rsp)
callq 0xe8d0
movq 0x48(%rsp), %rdi
addq $0x150, %rdi            # imm = 0x150
movq %rdi, 0x40(%rsp)
callq 0xe8c0
movq 0x48(%rsp), %rdi
movb $0x0, 0x40(%rdi)
movb $0x0, 0x149(%rdi)
movb $0x0, 0x14a(%rdi)
movb $0x0, 0x148(%rdi)
callq 0x3dbd0
jmp 0x3d22f
addq $0x68, %rsp
retq
movq 0x40(%rsp), %rdi
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x58(%rsp)
movl %eax, 0x54(%rsp)
callq 0xf0e0
movq 0x38(%rsp), %rdi
callq 0xef00
movq 0x30(%rsp), %rdi
callq 0x21ac0
movq 0x28(%rsp), %rdi
callq 0x3d5d0
movq 0x20(%rsp), %rdi
callq 0x211c0
movq 0x18(%rsp), %rdi
callq 0xef00
movq 0x10(%rsp), %rdi
callq 0xef00
movq 0x8(%rsp), %rdi
callq 0xef00
movq (%rsp), %rdi
callq 0xef00
movq 0x58(%rsp), %rdi
callq 0x5690
nopw %cs:(%rax,%rax)
nop
// File: gvaumour[P]cache-simulator/src/Cache.hh
// Function: CacheEntry::initEntry()
void initEntry() {
			isValid = false; 
			isDirty = false;
			lastWrite = false;
			
			isPrefetch = false;
			address = 0;

			policyInfo = 0; 
			saturation_counter = 0;
			m_pc = 0;
			nbRead = 0;
			nbWrite = 0;
			write_counter = 0;
			m_compilerHints = 0;
			justMigrate = false;
			value = 0;
			cost_value = 0;
			signature = 0;
			last_time_access = 0;
			coherence_state = COHERENCE_INVALID;
			e_nvm = 0, e_sram = 0;
			missPC = 0;
		}

// Assembly:
movq %rdi, -0x8(%rsp)
movq -0x8(%rsp), %rax
movb $0x0, (%rax)
movb $0x0, 0x1(%rax)
movb $0x0, 0x124(%rax)
movb $0x0, 0x14b(%rax)
movq $0x0, 0x8(%rax)
movl $0x0, 0x38(%rax)
movl $0x0, 0x128(%rax)
movq $0x0, 0x10(%rax)
movl $0x0, 0x120(%rax)
movl $0x0, 0x11c(%rax)
movl $0x0, 0x118(%rax)
movl $0x0, 0x3c(%rax)
movb $0x0, 0x14c(%rax)
movq $0x0, 0x28(%rax)
xorps %xmm0, %xmm0
movsd %xmm0, 0x130(%rax)
movq $0x0, 0x18(%rax)
movq $0x0, 0x30(%rax)
movl $0x3, 0x168(%rax)
movq $0x0, 0x140(%rax)
movq $0x0, 0x138(%rax)
movq $0x0, 0x20(%rax)
retq
nopl (%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Cache.hh
// Function: CacheEntry::copyCL(CacheEntry*)
void copyCL(CacheEntry* a)
		{
			address = a->address;
			isDirty = a->isDirty;
			nbWrite = a->nbWrite;
			nbRead = a->nbRead;
			lastWrite = a->lastWrite;
			m_compilerHints = a->m_compilerHints;
			isLearning = a->isLearning;
			m_pc = a->m_pc;
			coherence_state = a->coherence_state; 
			isPrefetch = a->isPrefetch;
			pc_history = a->pc_history;
			missPC = a->missPC;
			signature = a->signature;
		}

// Assembly:
subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movq 0x8(%rsp), %rax
movq 0x8(%rax), %rax
movq %rax, 0x8(%rdi)
movq 0x8(%rsp), %rax
movb 0x1(%rax), %al
andb $0x1, %al
movb %al, 0x1(%rdi)
movq 0x8(%rsp), %rax
movl 0x11c(%rax), %eax
movl %eax, 0x11c(%rdi)
movq 0x8(%rsp), %rax
movl 0x120(%rax), %eax
movl %eax, 0x120(%rdi)
movq 0x8(%rsp), %rax
movb 0x124(%rax), %al
andb $0x1, %al
movb %al, 0x124(%rdi)
movq 0x8(%rsp), %rax
movl 0x3c(%rax), %eax
movl %eax, 0x3c(%rdi)
movq 0x8(%rsp), %rax
movb 0x148(%rax), %al
andb $0x1, %al
movb %al, 0x148(%rdi)
movq 0x8(%rsp), %rax
movq 0x10(%rax), %rax
movq %rax, 0x10(%rdi)
movq 0x8(%rsp), %rax
movl 0x168(%rax), %eax
movl %eax, 0x168(%rdi)
movq 0x8(%rsp), %rax
movb 0x14b(%rax), %al
andb $0x1, %al
movb %al, 0x14b(%rdi)
movq 0x8(%rsp), %rsi
addq $0x150, %rsi            # imm = 0x150
addq $0x150, %rdi            # imm = 0x150
callq 0x3e7f0
movq (%rsp), %rax
movq 0x8(%rsp), %rcx
movq 0x20(%rcx), %rcx
movq %rcx, 0x20(%rax)
movq 0x8(%rsp), %rcx
movq 0x18(%rcx), %rcx
movq %rcx, 0x18(%rax)
addq $0x18, %rsp
retq
// File: gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::allocateInNVM(unsigned long, Access)
allocDecision
InstructionPredictor::allocateInNVM(uint64_t set, Access element)
{
	//DPRINTF("InstructionPredictor::allocateInNVM\n");
	
	if(element.isInstFetch())
		return ALLOCATE_IN_NVM;

	if(pc_counters.count(element.m_pc) == 0){
		//New PC to track		
		pc_counters.insert(pair<uint64_t,int>(element.m_pc, 1));	

		if(!m_isWarmup)
			stats_PCwrites.insert(pair<uint64_t,pair<int,int> >(element.m_pc, pair<int,int>(0,0) ));
		
		map<uint64_t, pair<int,int> > my_tab = map<uint64_t, pair<int,int> >();
	}

	if(pc_counters[element.m_pc] < 2)
		return ALLOCATE_IN_NVM; 
	else
		return ALLOCATE_IN_SRAM;

}

// Assembly:
subq $0xc8, %rsp
movq %rdi, %rax
leaq 0xd0(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq %rax, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x20(%rsp)
callq 0x20960
testb $0x1, %al
jne 0x43c1f
jmp 0x43c2f
movl $0x1, 0xc4(%rsp)
jmp 0x43d87
movq 0x18(%rsp), %rsi
movq 0x20(%rsp), %rdi
addq $0x280, %rdi            # imm = 0x280
addq $0x10, %rsi
callq 0x44860
cmpq $0x0, %rax
jne 0x43d50
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rsi
addq $0x280, %rax            # imm = 0x280
movq %rax, 0x10(%rsp)
addq $0x10, %rsi
movl $0x1, 0x9c(%rsp)
leaq 0xa0(%rsp), %rdi
leaq 0x9c(%rsp), %rdx
callq 0x448c0
movq 0x10(%rsp), %rdi
leaq 0xa0(%rsp), %rsi
callq 0xfdb0
movq %rax, %rcx
movq 0x20(%rsp), %rax
movq %rcx, 0x88(%rsp)
movb %dl, 0x90(%rsp)
testb $0x1, 0x81(%rax)
jne 0x43d2b
movq 0x18(%rsp), %rax
movq 0x20(%rsp), %rcx
addq $0x2b0, %rcx            # imm = 0x2B0
movq %rcx, 0x8(%rsp)
addq $0x10, %rax
movq %rax, (%rsp)
movl $0x0, 0x6c(%rsp)
movl $0x0, 0x68(%rsp)
leaq 0x70(%rsp), %rdi
leaq 0x6c(%rsp), %rsi
leaq 0x68(%rsp), %rdx
callq 0xf1b0
movq (%rsp), %rsi
leaq 0x78(%rsp), %rdi
leaq 0x70(%rsp), %rdx
callq 0x44940
movq 0x8(%rsp), %rdi
leaq 0x78(%rsp), %rsi
callq 0x448f0
movq %rax, 0x58(%rsp)
movb %dl, 0x60(%rsp)
leaq 0x28(%rsp), %rdi
xorl %esi, %esi
movl $0x30, %edx
callq 0x5210
leaq 0x28(%rsp), %rdi
callq 0x44820
leaq 0x28(%rsp), %rdi
callq 0x44850
movq 0x18(%rsp), %rsi
movq 0x20(%rsp), %rdi
addq $0x280, %rdi            # imm = 0x280
addq $0x10, %rsi
callq 0x44970
cmpl $0x2, (%rax)
jge 0x43d7c
movl $0x1, 0xc4(%rsp)
jmp 0x43d87
movl $0x0, 0xc4(%rsp)
movl 0xc4(%rsp), %eax
addq $0xc8, %rsp
retq
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::insertionPolicy(unsigned long, unsigned long, bool, Access)
void InstructionPredictor::insertionPolicy(uint64_t set, uint64_t index, bool inNVM, Access element)
{
	//DPRINTF("InstructionPredictor::insertionPolicy\n");
	
	CacheEntry* current;
	if(inNVM){
		current = m_tableNVM[set][index];
	}		
	else{
		current = m_tableSRAM[set][index];
	}
	
	current->policyInfo = m_cpt;

	if(element.isWrite())
		current->cost_value = WRITE_VALUE;
	else
		current->cost_value = READ_VALUE;
	
	Predictor::insertionPolicy(set , index , inNVM , element);
	m_cpt++;
}

// Assembly:
subq $0xc8, %rsp
movb %cl, %al
leaq 0xd0(%rsp), %rcx
movq %rcx, 0x58(%rsp)
movq %rdi, 0xc0(%rsp)
movq %rsi, 0xb8(%rsp)
movq %rdx, 0xb0(%rsp)
andb $0x1, %al
movb %al, 0xaf(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0x60(%rsp)
testb $0x1, 0xaf(%rsp)
je 0x44161
movq 0x60(%rsp), %rax
movq 0x10(%rax), %rdi
movq 0xb8(%rsp), %rsi
callq 0xf9a0
movq %rax, %rdi
movq 0xb0(%rsp), %rsi
callq 0xf9c0
movq (%rax), %rax
movq %rax, 0xa0(%rsp)
jmp 0x44192
movq 0x60(%rsp), %rax
movq 0x8(%rax), %rdi
movq 0xb8(%rsp), %rsi
callq 0xf9a0
movq %rax, %rdi
movq 0xb0(%rsp), %rsi
callq 0xf9c0
movq (%rax), %rax
movq %rax, 0xa0(%rsp)
movq 0x58(%rsp), %rdi
movq 0x60(%rsp), %rax
movq 0x270(%rax), %rax
movl %eax, %ecx
movq 0xa0(%rsp), %rax
movl %ecx, 0x38(%rax)
callq 0xf7c0
testb $0x1, %al
jne 0x441bb
jmp 0x441d5
movq 0xa0(%rsp), %rax
movsd 0x2ebf5(%rip), %xmm0    # 0x72dc0
movsd %xmm0, 0x130(%rax)
jmp 0x441ed
movq 0xa0(%rsp), %rax
movsd 0x2dd6b(%rip), %xmm0    # 0x71f50
movsd %xmm0, 0x130(%rax)
movq 0x58(%rsp), %rsi
movq 0xb8(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0xb0(%rsp), %rax
movq %rax, 0x50(%rsp)
movb 0xaf(%rsp), %al
movb %al, 0x47(%rsp)
leaq 0x68(%rsp), %rdi
movl $0x38, %edx
callq 0x52f0
movb 0x47(%rsp), %al
movq 0x48(%rsp), %rsi
movq 0x50(%rsp), %rdx
movq 0x60(%rsp), %rdi
movq 0x98(%rsp), %r8
movq %rsp, %rcx
movq %r8, 0x30(%rcx)
movups 0x68(%rsp), %xmm0
movups 0x78(%rsp), %xmm1
movups 0x88(%rsp), %xmm2
movups %xmm2, 0x20(%rcx)
movups %xmm1, 0x10(%rcx)
movups %xmm0, (%rcx)
movzbl %al, %ecx
andl $0x1, %ecx
callq 0x55140
movq 0x60(%rsp), %rax
movq 0x270(%rax), %rcx
addq $0x1, %rcx
movq %rcx, 0x270(%rax)
addq $0xc8, %rsp
retq
nop
// File: gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::printConfig(std::ostream&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
void
InstructionPredictor::printConfig(std::ostream& out, string entete){
	out << entete << ":InstructionPredictor" << std::endl;
	out << entete << ":READ_VALUE\t" << READ_VALUE << std::endl;		
	out << entete << ":WRITE_VALUE\t" << WRITE_VALUE << std::endl;		
	out << entete << ":CostThreshold\t" << simu_parameters.cost_threshold << std::endl;		
	out << entete << ":PCThreshold\t" << PC_THRESHOLD << endl;
	Predictor::printConfig(out, entete);
}

// Assembly:
subq $0x88, %rsp
movq %rdx, 0x8(%rsp)
movq %rsi, %rax
movq 0x8(%rsp), %rsi
movq %rsi, 0x20(%rsp)
movq %rdi, 0x80(%rsp)
movq %rax, 0x78(%rsp)
movq %rsi, 0x70(%rsp)
movq 0x80(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x78(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2eaec(%rip), %rsi     # 0x72dc8
callq 0x5380
movq %rax, %rdi
movq 0x4eccd(%rip), %rsi     # 0x92fb8
movq %rsi, 0x18(%rsp)
callq 0x53d0
movq 0x20(%rsp), %rsi
movq 0x78(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2ead0(%rip), %rsi     # 0x72dde
callq 0x5380
movq %rax, %rdi
movl $0xffffffff, %esi       # imm = 0xFFFFFFFF
callq 0x5680
movq 0x18(%rsp), %rsi
movq %rax, %rdi
callq 0x53d0
movq 0x20(%rsp), %rsi
movq 0x78(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2eaa5(%rip), %rsi     # 0x72deb
callq 0x5380
movq %rax, %rdi
movl $0x3, %esi
movl %esi, 0x14(%rsp)
callq 0x5680
movq 0x18(%rsp), %rsi
movq %rax, %rdi
callq 0x53d0
movq 0x20(%rsp), %rsi
movq 0x78(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2ea77(%rip), %rsi     # 0x72df9
callq 0x5380
movq %rax, %rdi
leaq 0x4fc5f(%rip), %rax     # 0x93ff0
movl 0xbc(%rax), %esi
callq 0x5680
movq 0x18(%rsp), %rsi
movq %rax, %rdi
callq 0x53d0
movq 0x20(%rsp), %rsi
movq 0x78(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2ea47(%rip), %rsi     # 0x72e09
callq 0x5380
movl 0x14(%rsp), %esi
movq %rax, %rdi
callq 0x5680
movq 0x18(%rsp), %rsi
movq %rax, %rdi
callq 0x53d0
movq 0x20(%rsp), %rsi
movq 0x78(%rsp), %rax
movq %rax, 0x30(%rsp)
leaq 0x50(%rsp), %rdi
movq %rdi, 0x38(%rsp)
callq 0x51b0
movq 0x28(%rsp), %rdi
movq 0x30(%rsp), %rsi
movq 0x38(%rsp), %rdx
callq 0x579f0
jmp 0x44414
leaq 0x50(%rsp), %rdi
callq 0x5768
addq $0x88, %rsp
retq
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x48(%rsp)
movl %eax, 0x44(%rsp)
leaq 0x50(%rsp), %rdi
callq 0x5768
movq 0x48(%rsp), %rdi
callq 0x5690
nopl (%rax,%rax)
// File: gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::printStats(std::ostream&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
void 
InstructionPredictor::printStats(std::ostream& out, string entete)
{	
	int totalWrite = 0;
	for(auto p : stats_PCwrites)
	{
		pair<int,int> current = p.second;
		totalWrite += current.first;
	}
	
	out << entete << ":InstructionPredictor Parameters:" << endl;
	out << entete << ":Total Write\t" << totalWrite << endl;
	
	/*
	ofstream output_file;
	output_file.open(OUTPUT_PREDICTOR_FILE , std::ofstream::app);
	if(totalWrite > 0){
		output_file << "Write Intensity Per Instruction "<< endl;
		for(auto p : stats_PCwrites)
		{
			pair<int,int> current = p.second;
			output_file << p.first << "\t" << current.first << "\t" << current.second << endl;
		}
	}
	output_file.close();
	*/
	Predictor::printStats(out,entete);
}

// Assembly:
subq $0xa8, %rsp
movq %rdx, 0x18(%rsp)
movq %rdi, 0xa0(%rsp)
movq %rsi, 0x98(%rsp)
movq %rdx, 0x90(%rsp)
movq 0xa0(%rsp), %rax
movq %rax, 0x20(%rsp)
movl $0x0, 0x8c(%rsp)
addq $0x2b0, %rax            # imm = 0x2B0
movq %rax, 0x80(%rsp)
movq 0x80(%rsp), %rdi
callq 0x44a60
movq %rax, 0x78(%rsp)
movq 0x80(%rsp), %rdi
callq 0x44a90
movq %rax, 0x70(%rsp)
leaq 0x78(%rsp), %rdi
leaq 0x70(%rsp), %rsi
callq 0x44ac0
testb $0x1, %al
jne 0x444d3
jmp 0x44516
leaq 0x78(%rsp), %rdi
callq 0x44ae0
movq (%rax), %rcx
movq %rcx, 0x60(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x68(%rsp)
movq 0x68(%rsp), %rax
movq %rax, 0x58(%rsp)
movl 0x58(%rsp), %eax
addl 0x8c(%rsp), %eax
movl %eax, 0x8c(%rsp)
leaq 0x78(%rsp), %rdi
callq 0x44b00
jmp 0x444be
movq 0x18(%rsp), %rsi
movq 0x98(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2e8e5(%rip), %rsi     # 0x72e17
callq 0x5380
movq %rax, %rdi
movq 0x4ea77(%rip), %rsi     # 0x92fb8
movq %rsi, (%rsp)
callq 0x53d0
movq 0x18(%rsp), %rsi
movq 0x98(%rsp), %rdi
callq 0x5330
movq %rax, %rdi
leaq 0x2e8d3(%rip), %rsi     # 0x72e39
callq 0x5380
movq %rax, %rdi
movl 0x8c(%rsp), %esi
callq 0x5680
movq (%rsp), %rsi
movq %rax, %rdi
callq 0x53d0
movq 0x18(%rsp), %rsi
movq 0x98(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x38(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x51b0
movq 0x20(%rsp), %rdi
movq 0x8(%rsp), %rsi
movq 0x10(%rsp), %rdx
callq 0x57bf0
jmp 0x445bd
leaq 0x38(%rsp), %rdi
callq 0x5768
addq $0xa8, %rsp
retq
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x30(%rsp)
movl %eax, 0x2c(%rsp)
leaq 0x38(%rsp), %rdi
callq 0x5768
movq 0x30(%rsp), %rdi
callq 0x5690
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::handleAccess(Access)
allocDecision
Level::handleAccess(Access element)
{
	if(element.isInstFetch() && !m_isUnified)
		return m_icache->handleAccess(element);	
	else
		return m_dcache->handleAccess(element);		
}

// Assembly:
subq $0xd8, %rsp
movq %rdi, %rax
leaq 0xe0(%rsp), %rdi
movq %rdi, 0x48(%rsp)
movq %rax, 0xc8(%rsp)
movq 0xc8(%rsp), %rax
movq %rax, 0x50(%rsp)
callq 0x20960
testb $0x1, %al
jne 0x46b67
jmp 0x46bdc
movq 0x50(%rsp), %rax
testb $0x1, 0x20(%rax)
jne 0x46bdc
movq 0x48(%rsp), %rsi
movq 0x50(%rsp), %rax
movq 0x8(%rax), %rax
movq %rax, 0x40(%rsp)
leaq 0x90(%rsp), %rdi
movl $0x38, %edx
callq 0x52f0
movq 0x40(%rsp), %rdi
movq 0xc0(%rsp), %rcx
movq %rsp, %rax
movq %rcx, 0x30(%rax)
movups 0x90(%rsp), %xmm0
movups 0xa0(%rsp), %xmm1
movups 0xb0(%rsp), %xmm2
movups %xmm2, 0x20(%rax)
movups %xmm1, 0x10(%rax)
movups %xmm0, (%rax)
callq 0x388d0
movl %eax, 0xd4(%rsp)
jmp 0x46c37
movq 0x48(%rsp), %rsi
movq 0x50(%rsp), %rax
movq (%rax), %rax
movq %rax, 0x38(%rsp)
leaq 0x58(%rsp), %rdi
movl $0x38, %edx
callq 0x52f0
movq 0x38(%rsp), %rdi
movq 0x88(%rsp), %rcx
movq %rsp, %rax
movq %rcx, 0x30(%rax)
movups 0x58(%rsp), %xmm0
movups 0x68(%rsp), %xmm1
movups 0x78(%rsp), %xmm2
movups %xmm2, 0x20(%rax)
movups %xmm1, 0x10(%rax)
movups %xmm0, (%rax)
callq 0x388d0
movl %eax, 0xd4(%rsp)
movl 0xd4(%rsp), %eax
addq $0xd8, %rsp
retq
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::lookup(Access)
bool
Level::lookup(Access element)
{
	if(element.isInstFetch() && !m_isUnified)
		return m_icache->lookup(element);
	else 
		return m_dcache->lookup(element);	
}

// Assembly:
subq $0xd8, %rsp
movq %rdi, %rax
leaq 0xe0(%rsp), %rdi
movq %rdi, 0x48(%rsp)
movq %rax, 0xc8(%rsp)
movq 0xc8(%rsp), %rax
movq %rax, 0x50(%rsp)
callq 0x20960
testb $0x1, %al
jne 0x46c87
jmp 0x46cfe
movq 0x50(%rsp), %rax
testb $0x1, 0x20(%rax)
jne 0x46cfe
movq 0x48(%rsp), %rsi
movq 0x50(%rsp), %rax
movq 0x8(%rax), %rax
movq %rax, 0x40(%rsp)
leaq 0x90(%rsp), %rdi
movl $0x38, %edx
callq 0x52f0
movq 0x40(%rsp), %rdi
movq 0xc0(%rsp), %rcx
movq %rsp, %rax
movq %rcx, 0x30(%rax)
movups 0x90(%rsp), %xmm0
movups 0xa0(%rsp), %xmm1
movups 0xb0(%rsp), %xmm2
movups %xmm2, 0x20(%rax)
movups %xmm1, 0x10(%rax)
movups %xmm0, (%rax)
callq 0x38460
andb $0x1, %al
movb %al, 0xd7(%rsp)
jmp 0x46d5b
movq 0x48(%rsp), %rsi
movq 0x50(%rsp), %rax
movq (%rax), %rax
movq %rax, 0x38(%rsp)
leaq 0x58(%rsp), %rdi
movl $0x38, %edx
callq 0x52f0
movq 0x38(%rsp), %rdi
movq 0x88(%rsp), %rcx
movq %rsp, %rax
movq %rcx, 0x30(%rax)
movups 0x58(%rsp), %xmm0
movups 0x68(%rsp), %xmm1
movups 0x78(%rsp), %xmm2
movups %xmm2, 0x20(%rax)
movups %xmm1, 0x10(%rax)
movups %xmm0, (%rax)
callq 0x38460
andb $0x1, %al
movb %al, 0xd7(%rsp)
movb 0xd7(%rsp), %al
andb $0x1, %al
addq $0xd8, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::getEntry(unsigned long)
CacheEntry* 
Level::getEntry(uint64_t addr)
{
	CacheEntry* entry = m_dcache->getEntry(addr);
	
	if(!m_isUnified && entry == NULL)
		return m_icache->getEntry(addr);
	
	return entry;
}

// Assembly:
subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
movq (%rax), %rdi
movq 0x10(%rsp), %rsi
callq 0x387e0
movq %rax, %rcx
movq (%rsp), %rax
movq %rcx, 0x8(%rsp)
testb $0x1, 0x20(%rax)
jne 0x47037
cmpq $0x0, 0x8(%rsp)
jne 0x47037
movq (%rsp), %rax
movq 0x8(%rax), %rdi
movq 0x10(%rsp), %rsi
callq 0x387e0
movq %rax, 0x20(%rsp)
jmp 0x47041
movq 0x8(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x20(%rsp), %rax
addq $0x28, %rsp
retq
nopl (%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::printResults(std::ostream&)
void
Level::printResults(std::ostream& out)
{
	out << "************************************************" << endl;
//	out << "Core n°" << m_IDcore << endl;
	if(m_isUnified)
		m_dcache->printResults(out);
	else
	{
//		out << "Data Cache " << endl;
		m_dcache->printResults(out);
		out << "******" << endl;
//		out << "Instruction Cache " << endl;
		m_icache->printResults(out);
	}
}

// Assembly:
subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rax
movq %rax, (%rsp)
movq 0x8(%rsp), %rdi
leaq 0x2be9a(%rip), %rsi     # 0x72f0d
callq 0x5380
movq %rax, %rdi
movq 0x4bf36(%rip), %rsi     # 0x92fb8
callq 0x53d0
movq (%rsp), %rax
testb $0x1, 0x20(%rax)
je 0x470a4
movq (%rsp), %rax
movq (%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x3b730
jmp 0x470e7
movq (%rsp), %rax
movq (%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x3b730
movq 0x8(%rsp), %rdi
leaq 0x2be76(%rip), %rsi     # 0x72f37
callq 0x5380
movq %rax, %rdi
movq 0x4bee8(%rip), %rsi     # 0x92fb8
callq 0x53d0
movq (%rsp), %rax
movq 0x8(%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x3b730
addq $0x18, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::printConfig(std::ostream&)
void
Level::printConfig(std::ostream& out)
{
	out << "************************************************" << endl;
//	out << "Core n°" << m_IDcore << endl;
	if(m_isUnified)
		m_dcache->printConfig(out);
	else
	{
//		out << "Data Cache " << endl;
		m_dcache->printConfig(out);
		out << "******" << endl;
//		out << "Instruction Cache " << endl;
		m_icache->printConfig(out);
	}
}

// Assembly:
subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rax
movq %rax, (%rsp)
movq 0x8(%rsp), %rdi
leaq 0x2bdfa(%rip), %rsi     # 0x72f0d
callq 0x5380
movq %rax, %rdi
movq 0x4be96(%rip), %rsi     # 0x92fb8
callq 0x53d0
movq (%rsp), %rax
testb $0x1, 0x20(%rax)
je 0x47144
movq (%rsp), %rax
movq (%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x3cb20
jmp 0x47187
movq (%rsp), %rax
movq (%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x3cb20
movq 0x8(%rsp), %rdi
leaq 0x2bdd6(%rip), %rsi     # 0x72f37
callq 0x5380
movq %rax, %rdi
movq 0x4be48(%rip), %rsi     # 0x92fb8
callq 0x53d0
movq (%rsp), %rax
movq 0x8(%rax), %rdi
movq 0x8(%rsp), %rsi
callq 0x3cb20
addq $0x18, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: CompressedTrace::open()
bool
CompressedTrace::open()
{
	m_compressedTrace = gzopen(m_trace.c_str() , "rb8");
	if(!m_compressedTrace)
		cout << "The trace " << m_trace << " cannot be opened" << endl;
	else
		m_isOpen = true;

	return m_isOpen;
}

// Assembly:
subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, 0x8(%rsp)
addq $0x8, %rdi
callq 0x51a0
movq %rax, %rdi
leaq 0x2b979(%rip), %rsi     # 0x72fdf
callq 0x5580
movq %rax, %rcx
movq 0x8(%rsp), %rax
movq %rcx, 0x30(%rax)
cmpq $0x0, 0x30(%rax)
jne 0x476c2
movq 0x4b94b(%rip), %rdi     # 0x92fd0
leaq 0x2b957(%rip), %rsi     # 0x72fe3
callq 0x5380
movq 0x8(%rsp), %rsi
movq %rax, %rdi
addq $0x8, %rsi
callq 0x5330
movq %rax, %rdi
leaq 0x2b942(%rip), %rsi     # 0x72fee
callq 0x5380
movq %rax, %rdi
movq 0x4b8fd(%rip), %rsi     # 0x92fb8
callq 0x53d0
jmp 0x476cb
movq 0x8(%rsp), %rax
movb $0x1, 0x28(%rax)
movq 0x8(%rsp), %rax
movb 0x28(%rax), %al
andb $0x1, %al
addq $0x18, %rsp
retq
nopw (%rax,%rax)
// File: gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: TextTrace::open()
bool
TextTrace::open()
{
	m_textTrace.open(m_trace);
	if(!m_textTrace)
		cout << "The trace " << m_trace << " cannot be opened" << endl;
	else
		m_isOpen = true;


	return m_isOpen;
}

// Assembly:
subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rsi
movq %rsi, 0x8(%rsp)
movq %rsi, %rdi
addq $0x30, %rdi
addq $0x8, %rsi
movl $0x8, %edx
callq 0x5300
movq 0x8(%rsp), %rax
movq %rax, %rdi
addq $0x30, %rdi
movq 0x30(%rax), %rax
addq -0x18(%rax), %rdi
callq 0x51d0
testb $0x1, %al
jne 0x47df7
jmp 0x47e3b
movq 0x4b1d2(%rip), %rdi     # 0x92fd0
leaq 0x2b1de(%rip), %rsi     # 0x72fe3
callq 0x5380
movq 0x8(%rsp), %rsi
movq %rax, %rdi
addq $0x8, %rsi
callq 0x5330
movq %rax, %rdi
leaq 0x2b1c9(%rip), %rsi     # 0x72fee
callq 0x5380
movq %rax, %rdi
movq 0x4b184(%rip), %rsi     # 0x92fb8
callq 0x53d0
jmp 0x47e44
movq 0x8(%rsp), %rax
movb $0x1, 0x28(%rax)
movq 0x8(%rsp), %rax
movb 0x28(%rax), %al
andb $0x1, %al
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: initTrace(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
MemoryTrace* initTrace(std::string trace_name)
{
	std::vector<std::string> split_line;
	std::string ext = split(trace_name , '.').back();	
	if(ext.size() == 3 && ext == "txt")
		return new TextTrace(trace_name);
	else
		return new CompressedTrace(trace_name);		

}

// Assembly:
subq $0x108, %rsp            # imm = 0x108
movq %rdi, 0x20(%rsp)
movq %rdi, 0xf8(%rsp)
leaq 0xe0(%rsp), %rdi
callq 0xe850
movq 0x20(%rsp), %rsi
leaq 0x88(%rsp), %rdi
callq 0x51b0
jmp 0x47eb5
leaq 0xa8(%rsp), %rdi
leaq 0x88(%rsp), %rsi
movl $0x2e, %edx
callq 0x653b0
jmp 0x47ed1
leaq 0xa8(%rsp), %rdi
callq 0x48270
movq %rax, %rsi
leaq 0xc0(%rsp), %rdi
callq 0x51b0
jmp 0x47ef0
leaq 0xa8(%rsp), %rdi
callq 0xf560
leaq 0x88(%rsp), %rdi
callq 0x5768
leaq 0xc0(%rsp), %rdi
callq 0x5290
cmpq $0x3, %rax
jne 0x4805e
leaq 0x297e7(%rip), %rsi     # 0x7170f
leaq 0xc0(%rsp), %rdi
callq 0xfa60
movb %al, 0x1f(%rsp)
jmp 0x47f3b
movb 0x1f(%rsp), %al
testb $0x1, %al
jne 0x47f48
jmp 0x4805e
movl $0x238, %edi            # imm = 0x238
callq 0x53a0
movq %rax, 0x10(%rsp)
jmp 0x47f59
movq 0x20(%rsp), %rsi
movb $0x1, 0x57(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x51b0
jmp 0x47f6f
movq 0x10(%rsp), %rdi
leaq 0x58(%rsp), %rsi
callq 0x482b0
jmp 0x47f80
movq 0x10(%rsp), %rax
movb $0x0, 0x57(%rsp)
movq %rax, 0x100(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x5768
movl $0x1, 0x50(%rsp)
jmp 0x480ff
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
jmp 0x48136
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
jmp 0x47ff0
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
leaq 0xa8(%rsp), %rdi
callq 0xf560
leaq 0x88(%rsp), %rdi
callq 0x5768
jmp 0x48136
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
jmp 0x48129
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
jmp 0x48046
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
leaq 0x58(%rsp), %rdi
callq 0x5768
testb $0x1, 0x57(%rsp)
jne 0x4804f
jmp 0x48059
movq 0x10(%rsp), %rdi
callq 0x5340
jmp 0x48129
movl $0x38, %edi
callq 0x53a0
movq %rax, 0x8(%rsp)
jmp 0x4806f
movq 0x20(%rsp), %rsi
movb $0x1, 0x2f(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x51b0
jmp 0x48085
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
callq 0x48380
jmp 0x48096
movq 0x8(%rsp), %rax
movb $0x0, 0x2f(%rsp)
movq %rax, 0x100(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x5768
movl $0x1, 0x50(%rsp)
jmp 0x480ff
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
jmp 0x480ea
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x80(%rsp)
movl %eax, 0x7c(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x5768
testb $0x1, 0x2f(%rsp)
jne 0x480f3
jmp 0x480fd
movq 0x8(%rsp), %rdi
callq 0x5340
jmp 0x48129
leaq 0xc0(%rsp), %rdi
callq 0x5768
leaq 0xe0(%rsp), %rdi
callq 0xf560
movq 0x100(%rsp), %rax
addq $0x108, %rsp            # imm = 0x108
retq
leaq 0xc0(%rsp), %rdi
callq 0x5768
leaq 0xe0(%rsp), %rdi
callq 0xf560
movq 0x80(%rsp), %rdi
callq 0x5690
// File: gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::allocateInNVM(unsigned long, Access)
allocDecision
PHCPredictor::allocateInNVM(uint64_t set, Access element)
{
//	if(element.isInstFetch())
//		return ALLOCATE_IN_NVM;
	
	update_globalPChistory(element.m_pc);
	stats_nbMiss++;
	miss_counter++;
	if(miss_counter > 255)
		miss_counter = 255;
	
	// All the set is a learning/sampled set independantly of its way or SRAM/NVM alloc
	//bool isLearning = m_tableSRAM[set][0]->isLearning; 

	int sum_pred = 0;
	for(unsigned i = 0 ; i < m_features.size() ; i++)
	{
		int hash = m_features_hash[i](element.block_addr , element.m_pc);
		sum_pred += m_features[i]->getAllocationPrediction(hash, true);
	}
	if( abs(sum_pred) < simu_parameters.perceptron_allocation_threshold )
	{
		stats_prediction_preemptive++;
		if( element.isWrite() )
			return ALLOCATE_IN_SRAM;
		else 
			return ALLOCATE_IN_NVM;
	}
	else
	{
		stats_prediction_confident++;
		if( sum_pred < simu_parameters.perceptron_allocation_threshold )
			return ALLOCATE_IN_SRAM;
		else
			return ALLOCATE_IN_NVM;
	}

}

// Assembly:
subq $0x48, %rsp
leaq 0x50(%rsp), %rax
movq %rax, 0x10(%rsp)
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq 0x38(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x10(%rax), %rsi
callq 0x4ab00
movq 0x18(%rsp), %rax
movq 0x368(%rax), %rcx
addq $0x1, %rcx
movq %rcx, 0x368(%rax)
leaq 0x498b7(%rip), %rax     # 0x94240
movl (%rax), %ecx
addl $0x1, %ecx
leaq 0x498ab(%rip), %rax     # 0x94240
movl %ecx, (%rax)
leaq 0x498a2(%rip), %rax     # 0x94240
cmpl $0xff, (%rax)
jle 0x4a9b3
leaq 0x49893(%rip), %rax     # 0x94240
movl $0xff, (%rax)
movl $0x0, 0x2c(%rsp)
movl $0x0, 0x28(%rsp)
movq 0x18(%rsp), %rdi
movl 0x28(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x270, %rdi            # imm = 0x270
callq 0xf840
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x4aa57
movq 0x18(%rsp), %rdi
addq $0x288, %rdi            # imm = 0x288
movl 0x28(%rsp), %eax
movl %eax, %esi
callq 0x4d780
movq 0x10(%rsp), %rcx
movq (%rax), %rax
movq 0x30(%rcx), %rdi
movq 0x10(%rcx), %rsi
callq *%rax
movq 0x18(%rsp), %rdi
movl %eax, 0x24(%rsp)
addq $0x270, %rdi            # imm = 0x270
movl 0x28(%rsp), %eax
movl %eax, %esi
callq 0xf8c0
movq (%rax), %rdi
movl 0x24(%rsp), %esi
movl $0x1, %edx
callq 0x2d4e0
addl 0x2c(%rsp), %eax
movl %eax, 0x2c(%rsp)
movl 0x28(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x28(%rsp)
jmp 0x4a9c3
movl 0x2c(%rsp), %eax
movl %eax, %ecx
negl %ecx
cmovnsl %ecx, %eax
leaq 0x49587(%rip), %rcx     # 0x93ff0
cmpl 0x1c0(%rcx), %eax
jge 0x4aaac
movq 0x10(%rsp), %rdi
movq 0x18(%rsp), %rax
movq 0x3e0(%rax), %rcx
addq $0x1, %rcx
movq %rcx, 0x3e0(%rax)
callq 0xf7c0
testb $0x1, %al
jne 0x4aa98
jmp 0x4aaa2
movl $0x0, 0x44(%rsp)
jmp 0x4aae8
movl $0x1, 0x44(%rsp)
jmp 0x4aae8
movq 0x18(%rsp), %rax
movq 0x3d8(%rax), %rcx
addq $0x1, %rcx
movq %rcx, 0x3d8(%rax)
movl 0x2c(%rsp), %eax
leaq 0x49522(%rip), %rcx     # 0x93ff0
cmpl 0x1c0(%rcx), %eax
jge 0x4aae0
movl $0x0, 0x44(%rsp)
jmp 0x4aae8
movl $0x1, 0x44(%rsp)
movl 0x44(%rsp), %eax
addq $0x48, %rsp
retq
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::update_globalPChistory(unsigned long)
void
PHCPredictor::update_globalPChistory(uint64_t pc)
{	
	m_global_PChistory.push_front(pc);
	if( m_global_PChistory.size() == 11)
		m_global_PChistory.pop_back();
	
	if(!m_need_callee_file)
		return;
	
	if(m_callee_map.count(pc) != 0)
	{
		m_callee_PChistory.push_front(pc);
		if( m_callee_PChistory.size() == 11)
			m_callee_PChistory.pop_back();
	}
}

// Assembly:
subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rax
movq %rax, (%rsp)
leaq 0x49092(%rip), %rdi     # 0x93bb0
leaq 0x8(%rsp), %rsi
callq 0x4d7a0
leaq 0x49081(%rip), %rdi     # 0x93bb0
callq 0x4d800
cmpq $0xb, %rax
jne 0x4ab46
leaq 0x4906f(%rip), %rdi     # 0x93bb0
callq 0x4d820
movq (%rsp), %rax
testb $0x1, 0x2e0(%rax)
jne 0x4ab55
jmp 0x4aba1
movq (%rsp), %rdi
addq $0x2e8, %rdi            # imm = 0x2E8
leaq 0x8(%rsp), %rsi
callq 0x44860
cmpq $0x0, %rax
je 0x4aba1
leaq 0x49089(%rip), %rdi     # 0x93c00
leaq 0x8(%rsp), %rsi
callq 0x4d7a0
leaq 0x49078(%rip), %rdi     # 0x93c00
callq 0x4d800
cmpq $0xb, %rax
jne 0x4ab9f
leaq 0x49066(%rip), %rdi     # 0x93c00
callq 0x4d820
jmp 0x4aba1
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::finishSimu()
void 
PHCPredictor::finishSimu()
{
	
	if(simu_parameters.perceptron_drawFeatureMaps)
	{
		drawFeatureMaps();
	}
	
	for(auto feature : m_features)
		feature->finishSimu();
	
	Predictor::finishSimu();
}

// Assembly:
subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x46e06(%rip), %rax     # 0x93ff0
testb $0x1, 0x1cc(%rax)
je 0x4d1fd
movq 0x8(%rsp), %rdi
callq 0x4d280
movq 0x8(%rsp), %rax
addq $0x270, %rax            # imm = 0x270
movq %rax, 0x28(%rsp)
movq 0x28(%rsp), %rdi
callq 0xf680
movq %rax, 0x20(%rsp)
movq 0x28(%rsp), %rdi
callq 0xf6b0
movq %rax, 0x18(%rsp)
leaq 0x20(%rsp), %rdi
leaq 0x18(%rsp), %rsi
callq 0xf6e0
testb $0x1, %al
jne 0x4d240
jmp 0x4d268
leaq 0x20(%rsp), %rdi
callq 0xf720
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x2da40
leaq 0x20(%rsp), %rdi
callq 0xf730
jmp 0x4d22b
movq 0x8(%rsp), %rdi
callq 0xfcb0
addq $0x38, %rsp
retq
nopw (%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Perceptron.cc
// Function: PerceptronPredictor::setBPPrediction(CacheEntry*)
void 
PerceptronPredictor::setBPPrediction(CacheEntry* current)
{
	int bp_pred=0;
	for(unsigned i = 0 ; i < m_BP_features.size() ; i++)
	{
		int hash = m_BP_features_hash[i](current->address , current->m_pc);
		bp_pred = m_BP_features[i]->getConfidence(hash,true);
		current->perceptron_BPpred[i] = bp_pred;
		current->perceptron_BPHash[i] = hash;
		if(bp_pred > simu_parameters.perceptron_bypass_threshold)
			current->predictedReused[i] = false;
		else
			current->predictedReused[i] = true;
	}
}

// Assembly:
subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x0, 0x44(%rsp)
movl $0x0, 0x40(%rsp)
movq 0x10(%rsp), %rdi
movl 0x40(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x2b8, %rdi            # imm = 0x2B8
callq 0xf840
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x51f07
movq 0x10(%rsp), %rdi
addq $0x2d0, %rdi            # imm = 0x2D0
movl 0x40(%rsp), %eax
movl %eax, %esi
callq 0x4d780
movq (%rax), %rax
movq 0x48(%rsp), %rcx
movq 0x8(%rcx), %rdi
movq 0x48(%rsp), %rcx
movq 0x10(%rcx), %rsi
callq *%rax
movq 0x10(%rsp), %rdi
movl %eax, 0x3c(%rsp)
addq $0x2b8, %rdi            # imm = 0x2B8
movl 0x40(%rsp), %eax
movl %eax, %esi
callq 0xf8c0
movq (%rax), %rdi
movl 0x3c(%rsp), %esi
movl $0x1, %edx
callq 0x2d520
movl %eax, 0x44(%rsp)
movl 0x44(%rsp), %eax
movl %eax, (%rsp)
movq 0x48(%rsp), %rdi
addq $0x48, %rdi
movl 0x40(%rsp), %eax
movl %eax, %esi
callq 0xef90
movl (%rsp), %ecx
movl %ecx, (%rax)
movl 0x3c(%rsp), %eax
movl %eax, 0x4(%rsp)
movq 0x48(%rsp), %rdi
addq $0x78, %rdi
movl 0x40(%rsp), %eax
movl %eax, %esi
callq 0xef90
movl 0x4(%rsp), %ecx
movl %ecx, (%rax)
movl 0x44(%rsp), %eax
leaq 0x42162(%rip), %rcx     # 0x93ff0
cmpl 0x1b8(%rcx), %eax
jle 0x51ec5
movq 0x48(%rsp), %rdi
addq $0xa8, %rdi
movl 0x40(%rsp), %eax
movl %eax, %esi
callq 0xfa90
movq %rax, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
leaq 0x28(%rsp), %rdi
xorl %esi, %esi
callq 0x250f0
jmp 0x51ef5
movq 0x48(%rsp), %rdi
addq $0xa8, %rdi
movl 0x40(%rsp), %eax
movl %eax, %esi
callq 0xfa90
movq %rax, 0x18(%rsp)
movq %rdx, 0x20(%rsp)
leaq 0x18(%rsp), %rdi
movl $0x1, %esi
callq 0x250f0
jmp 0x51ef7
movl 0x40(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x40(%rsp)
jmp 0x51db8
addq $0x58, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Perceptron.cc
// Function: PerceptronPredictor::setAllocPrediction(CacheEntry*)
void
PerceptronPredictor::setAllocPrediction(CacheEntry *current)
{
	int alloc_pred=0;
	for(unsigned i = 0 ; i < m_Allocation_features.size() ; i++)
	{
		int hash = m_Allocation_features_hash[i](current->address , current->m_pc);
		alloc_pred = m_Allocation_features[i]->getConfidence(hash, true);
		current->perceptron_Allocpred[i] = alloc_pred;
		current->perceptron_AllocHash[i] = hash;
//		if(alloc_pred > simu_parameters.perceptron_allocation_threshold)
//			current->predictedReused[i] = false;
//		else
//			current->predictedReused[i] = true;
	}
}

// Assembly:
subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x0, 0x24(%rsp)
movl $0x0, 0x20(%rsp)
movq 0x10(%rsp), %rdi
movl 0x20(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x270, %rdi            # imm = 0x270
callq 0xf840
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x52236
movq 0x10(%rsp), %rdi
addq $0x288, %rdi            # imm = 0x288
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0x4d780
movq (%rax), %rax
movq 0x28(%rsp), %rcx
movq 0x8(%rcx), %rdi
movq 0x28(%rsp), %rcx
movq 0x10(%rcx), %rsi
callq *%rax
movq 0x10(%rsp), %rdi
movl %eax, 0x1c(%rsp)
addq $0x270, %rdi            # imm = 0x270
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0xf8c0
movq (%rax), %rdi
movl 0x1c(%rsp), %esi
movl $0x1, %edx
callq 0x2d520
movl %eax, 0x24(%rsp)
movl 0x24(%rsp), %eax
movl %eax, (%rsp)
movq 0x28(%rsp), %rdi
addq $0x60, %rdi
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0xef90
movl (%rsp), %ecx
movl %ecx, (%rax)
movl 0x1c(%rsp), %eax
movl %eax, 0x4(%rsp)
movq 0x28(%rsp), %rdi
addq $0x90, %rdi
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0xef90
movl 0x4(%rsp), %ecx
movl %ecx, (%rax)
movl 0x20(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x20(%rsp)
jmp 0x52158
addq $0x38, %rsp
retq
nopl (%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::updateCachePressure()
void
Predictor::updateCachePressure()
{
	if(!m_trackError || !simu_parameters.enableDatasetSpilling)
		return;
		
	if( (cpt_time - stats_beginTimeFrame) > simu_parameters.MT_timeframe)
	{
		for(int i = 0 ; i < m_nb_set ; i++)
		{
			m_isNVMbusy[i] = (m_NVM_MT_counters[i] > simu_parameters.MT_counter_th) ? true : false;		
			m_isSRAMbusy[i] = (m_SRAM_MT_counters[i] > simu_parameters.MT_counter_th) ? true : false;
		
			m_NVM_MT_counters[i] = 0;
			m_SRAM_MT_counters[i] = 0;
		}

		if(simu_parameters.printDebug)
		{
			//stats_SRAMpressure.push_back(m_isSRAMbusy);
		}

		stats_beginTimeFrame = cpt_time;	
	}
}

// Assembly:
subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0x20(%rsp)
testb $0x1, 0x80(%rax)
je 0x55f2c
leaq 0x3e0cd(%rip), %rax     # 0x93ff0
testb $0x1, 0x158(%rax)
jne 0x55f31
jmp 0x560b7
movq 0x20(%rsp), %rcx
leaq 0x3e07b(%rip), %rax     # 0x93fb8
movq (%rax), %rax
subq 0x268(%rcx), %rax
leaq 0x3e0a2(%rip), %rcx     # 0x93ff0
cmpq 0xd0(%rcx), %rax
jbe 0x560b7
movl $0x0, 0x4c(%rsp)
movq 0x20(%rsp), %rcx
movl 0x4c(%rsp), %eax
cmpl 0x18(%rcx), %eax
jge 0x56093
movq 0x20(%rsp), %rdi
addq $0xd0, %rdi
movslq 0x4c(%rsp), %rsi
callq 0xfa20
movq 0x20(%rsp), %rdi
movq (%rax), %rax
leaq 0x3e056(%rip), %rcx     # 0x93ff0
movq %rcx, 0x10(%rsp)
movl 0xc8(%rcx), %ecx
subq %rcx, %rax
seta %al
movb %al, 0xf(%rsp)
addq $0x110, %rdi            # imm = 0x110
movslq 0x4c(%rsp), %rsi
callq 0xfa90
movq %rax, %rcx
movb 0xf(%rsp), %al
movq %rcx, 0x38(%rsp)
movq %rdx, 0x40(%rsp)
movzbl %al, %esi
leaq 0x38(%rsp), %rdi
callq 0x250f0
movq 0x20(%rsp), %rdi
addq $0xb8, %rdi
movslq 0x4c(%rsp), %rsi
callq 0xfa20
movq 0x20(%rsp), %rdi
movq %rax, %rcx
movq 0x10(%rsp), %rax
movq (%rcx), %rdx
movl 0xc8(%rax), %eax
movl %eax, %ecx
xorl %eax, %eax
subq %rdx, %rcx
sbbl %eax, %eax
movb %al, 0x1f(%rsp)
addq $0xe8, %rdi
movslq 0x4c(%rsp), %rsi
callq 0xfa90
movq %rax, %rcx
movb 0x1f(%rsp), %al
movq %rcx, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
movzbl %al, %esi
andl $0x1, %esi
leaq 0x28(%rsp), %rdi
callq 0x250f0
movq 0x20(%rsp), %rdi
addq $0xd0, %rdi
movslq 0x4c(%rsp), %rsi
callq 0xfa20
movq 0x20(%rsp), %rdi
movq $0x0, (%rax)
addq $0xb8, %rdi
movslq 0x4c(%rsp), %rsi
callq 0xfa20
movq $0x0, (%rax)
movl 0x4c(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x4c(%rsp)
jmp 0x55f63
leaq 0x3df56(%rip), %rax     # 0x93ff0
testb $0x1, (%rax)
je 0x560a1
jmp 0x560a1
movq 0x20(%rsp), %rax
leaq 0x3df0b(%rip), %rcx     # 0x93fb8
movq (%rcx), %rcx
movq %rcx, 0x268(%rax)
addq $0x58, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::missingTagCostValue(unsigned long, int)
int 
Predictor::missingTagCostValue(uint64_t block_addr, int set)
{
	for(unsigned i = 0 ; i < m_SRAM_missing_tags[set].size() ; i++)
	{
		if(m_SRAM_missing_tags[set][i]->addr == block_addr && m_SRAM_missing_tags[set][i]->isValid)
		{
			return m_SRAM_missing_tags[set][i]->cost_value;
		}
	}	
	return 0;
}

// Assembly:
subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movl %edx, 0x1c(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x0, 0x18(%rsp)
movq 0x10(%rsp), %rdi
movl 0x18(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x88, %rdi
movslq 0x1c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
callq 0x58940
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x564fc
movq 0x10(%rsp), %rdi
addq $0x88, %rdi
movslq 0x1c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x18(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
movq (%rax), %rax
cmpq 0x20(%rsp), %rax
jne 0x564ea
movq 0x10(%rsp), %rdi
addq $0x88, %rdi
movslq 0x1c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x18(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
testb $0x1, 0x14(%rax)
je 0x564ea
movq 0x10(%rsp), %rdi
addq $0x88, %rdi
movslq 0x1c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x18(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
movl 0x10(%rax), %eax
movl %eax, 0x34(%rsp)
jmp 0x56504
jmp 0x564ec
movl 0x18(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x18(%rsp)
jmp 0x56424
movl $0x0, 0x34(%rsp)
movl 0x34(%rsp), %eax
addq $0x38, %rsp
retq
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::missingTagMissPC(unsigned long, int)
uint64_t 
Predictor::missingTagMissPC(uint64_t block_addr, int set)
{
	assert( m_policy == "Cerebron" || m_policy == "SimplePerceptron");
	
	for(unsigned i = 0 ; i < m_SRAM_missing_tags[set].size() ; i++)
	{
		if(m_SRAM_missing_tags[set][i]->addr == block_addr && m_SRAM_missing_tags[set][i]->isValid)
		{
			return m_SRAM_missing_tags[set][i]->missPC;
		}
	}
	
	//Sanity check , shouldn't go there 
	assert(false);

	return 0;
}

// Assembly:
subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movl %edx, 0x24(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x10(%rsp)
addq $0x40, %rdi
leaq 0x1c2b1(%rip), %rsi     # 0x727e8
callq 0xfa60
movb %al, %cl
movb $0x1, %al
testb $0x1, %cl
movb %al, 0x1f(%rsp)
jne 0x56562
movq 0x10(%rsp), %rdi
addq $0x40, %rdi
leaq 0x1c298(%rip), %rsi     # 0x727f1
callq 0xfa60
movb %al, 0x1f(%rsp)
movb 0x1f(%rsp), %al
testb $0x1, %al
jne 0x5656c
jmp 0x5656e
jmp 0x5658d
leaq 0x1d185(%rip), %rdi     # 0x736fa
leaq 0x1d1b7(%rip), %rsi     # 0x73733
movl $0x15d, %edx            # imm = 0x15D
leaq 0x1d1bc(%rip), %rcx     # 0x73744
callq 0x5260
movl $0x0, 0x20(%rsp)
movq 0x10(%rsp), %rdi
movl 0x20(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x88, %rdi
movslq 0x24(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
callq 0x58940
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x5666d
movq 0x10(%rsp), %rdi
addq $0x88, %rdi
movslq 0x24(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
movq (%rax), %rax
cmpq 0x28(%rsp), %rax
jne 0x5665b
movq 0x10(%rsp), %rdi
addq $0x88, %rdi
movslq 0x24(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
testb $0x1, 0x14(%rax)
je 0x5665b
movq 0x10(%rsp), %rdi
addq $0x88, %rdi
movslq 0x24(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x20(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
movq 0x18(%rax), %rax
addq $0x38, %rsp
retq
jmp 0x5665d
movl 0x20(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x20(%rsp)
jmp 0x56595
leaq 0x1beaa(%rip), %rdi     # 0x7251e
leaq 0x1d0b8(%rip), %rsi     # 0x73733
movl $0x168, %edx            # imm = 0x168
leaq 0x1d0bd(%rip), %rcx     # 0x73744
callq 0x5260
nopl (%rax)
// File: gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::missingTagFeaturesHash(unsigned long, int)
vector<int>
Predictor::missingTagFeaturesHash(uint64_t block_addr, int set)
{
	if( m_policy == "Cerebron")
	{
		for(unsigned i = 0 ; i < m_SRAM_missing_tags[set].size() ; i++)
		{
			if(m_SRAM_missing_tags[set][i]->addr == block_addr && m_SRAM_missing_tags[set][i]->isValid)
			{
				return m_SRAM_missing_tags[set][i]->features_hash;
			}
		}	
	}
	return vector<int>();
}

// Assembly:
subq $0x48, %rsp
movq %rdi, 0x10(%rsp)
movq %rdi, %rax
movq %rax, 0x18(%rsp)
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movl %ecx, 0x2c(%rsp)
movq 0x38(%rsp), %rdi
movq %rdi, 0x20(%rsp)
addq $0x40, %rdi
leaq 0x1c11f(%rip), %rsi     # 0x727e8
callq 0xfa60
testb $0x1, %al
jne 0x566d7
jmp 0x567c0
movl $0x0, 0x28(%rsp)
movq 0x20(%rsp), %rdi
movl 0x28(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x88, %rdi
movslq 0x2c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
callq 0x58940
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x567be
movq 0x20(%rsp), %rdi
addq $0x88, %rdi
movslq 0x2c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x28(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
movq (%rax), %rax
cmpq 0x30(%rsp), %rax
jne 0x567ac
movq 0x20(%rsp), %rdi
addq $0x88, %rdi
movslq 0x2c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x28(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
testb $0x1, 0x14(%rax)
je 0x567ac
movq 0x20(%rsp), %rdi
addq $0x88, %rdi
movslq 0x2c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x28(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq 0x10(%rsp), %rdi
movq (%rax), %rsi
addq $0x20, %rsi
callq 0x12f20
jmp 0x567db
jmp 0x567ae
movl 0x28(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x28(%rsp)
jmp 0x566df
jmp 0x567c0
movq 0x10(%rsp), %rdi
xorl %esi, %esi
movl $0x18, %edx
callq 0x5210
movq 0x10(%rsp), %rdi
callq 0xe8d0
movq 0x18(%rsp), %rax
addq $0x48, %rsp
retq
nopw %cs:(%rax,%rax)
// File: gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::checkBypassTag(unsigned long, int)
bool
Predictor::checkBypassTag(uint64_t block_addr , int set)
{	
	for(unsigned i = 0 ; i < BP_missing_tags[set].size() ; i++)
	{	
		if(BP_missing_tags[set][i]->addr == block_addr)
			return true;
	}
	return false;
}

// Assembly:
subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movl %edx, 0x1c(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x10(%rsp)
movl $0x0, 0x18(%rsp)
movq 0x10(%rsp), %rdi
movl 0x18(%rsp), %eax
movq %rax, 0x8(%rsp)
addq $0x140, %rdi            # imm = 0x140
movslq 0x1c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
callq 0x58940
movq %rax, %rcx
movq 0x8(%rsp), %rax
cmpq %rcx, %rax
jae 0x5688f
movq 0x10(%rsp), %rdi
addq $0x140, %rdi            # imm = 0x140
movslq 0x1c(%rsp), %rsi
callq 0x58920
movq %rax, %rdi
movl 0x18(%rsp), %eax
movl %eax, %esi
callq 0x58860
movq (%rax), %rax
movq (%rax), %rax
cmpq 0x20(%rsp), %rax
jne 0x56880
movb $0x1, 0x37(%rsp)
jmp 0x56894
jmp 0x56882
movl 0x18(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x18(%rsp)
jmp 0x56814
movb $0x0, 0x37(%rsp)
movb 0x37(%rsp), %al
andb $0x1, %al
addq $0x38, %rsp
retq
nop