// File: /workspace/github_cpp_makefile_star2_O1/martinferianc[P]CPUSimulator-EIE2/src/mips_cpu_execute.cpp
// Function: mips_execute_I_X(mips_cpu_impl*, mips_mem_provider*, unsigned int const*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>> const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>&, unsigned int&, unsigned int&)
mips_error mips_execute_I_X(mips_cpu_h state, mips_mem_h mem, const uint32_t* instruction_data, const string& op, string& instruction, uint32_t& pcN, uint32_t& pc){
	stringstream ss;
	mips_error err = mips_ExceptionInvalidInstruction;

	uint32_t* source2 = new uint32_t;
	uint32_t* source1 = new uint32_t;
	uint32_t destination = instruction_data[2];
	int32_t imm_signed =  int32_t(int16_t(instruction_data[3]));
	uint32_t imm_unsigned = uint32_t(instruction_data[3]);


	err = mips_cpu_get_register(state, (unsigned)instruction_data[1], source1);
	if (err==mips_Success)
	err = mips_cpu_get_register(state, (unsigned)instruction_data[2], source2);
	if (err!=mips_Success)
	return mips_ExceptionAccessViolation;

	if (op.compare("ADDIU")==0)
		err = mips_cpu_set_register(state, destination, *source1 + imm_signed);

	if (op.compare("ADDI")==0){
		if (!addition_overflow(imm_signed,*source1))
			err = mips_cpu_set_register(state, destination, *source1 + imm_signed);
		else
			err = mips_ExceptionArithmeticOverflow;
	}
	if (op.compare("ORI")==0)
	err = mips_cpu_set_register(state, destination, imm_unsigned | *source1);

	if (op.compare("XORI")==0)
	err = mips_cpu_set_register(state, destination, uint32_t(*source1 ^ imm_unsigned));

	if (op.compare("ANDI")==0)
		err = mips_cpu_set_register(state, destination, imm_unsigned & *source1);

	if (op.compare("SLTIU")==0)
	err = mips_cpu_set_register(state, destination, int(uint32_t(*source1) < uint32_t(imm_signed)));

	if (op.compare("SLTI")==0)
	err = mips_cpu_set_register(state, destination, int((int32_t(*source1) < imm_signed)));

	if (op.compare("BEQ")==0){
		if (*source1 == *source2){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}
	if (op.compare("BNE")==0){
		if (*source1 != *source2){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}
	if (op.compare("BGEZ")==0){
		if (int32_t(*source1) >= 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BLEZ")==0){
		if (int32_t(*source1) <= 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BGTZ")==0){
		if (int32_t(*source1) > 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BLTZ")==0){
		if (int32_t(*source1) < 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BLTZAL")==0){
		if (instruction_data[1]==31) {
			err = mips_ErrorInvalidArgument;
		} else {
			if (int32_t(*source1) < 0){
				mips_cpu_set_register(state, 31, pc + 8);
				pc = pcN;
				pcN = int32_t(pcN) + (imm_signed << 2);
				err = mips_ExceptionBreak;
			} else {
				err = mips_Success;
			}
		}
	}
	if (op.compare("BGEZAL")==0){
		if (instruction_data[1]==31) {
			err = mips_ErrorInvalidArgument;
		} else {
			if (int32_t(*source1) >= 0){
				mips_cpu_set_register(state, 31, pc + 8);
				pc = pcN;
				pcN = int32_t(pcN) + (imm_signed << 2);
				err = mips_ExceptionBreak;
			} else {
				err = mips_Success;
			}
		}
	}

	if (op.compare("LW")==0){
		if ((imm_signed + *source1)%4!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint8_t dataOut[4];
			err = mips_mem_read(mem, imm_signed + *source1, 4, dataOut);
			uint32_t mem_value =  dataOut[3] | (uint32_t(dataOut[2]) << 8) | (uint32_t(dataOut[1]) << 16) | (uint32_t(dataOut[0]) << 24);
			err = mips_cpu_set_register(state, destination, mem_value);
		}
	}

	if (op.compare("LBU")==0){
		uint8_t dataOut;
		err = mips_mem_read(mem, imm_signed + *source1, 1, (uint8_t*)&dataOut);
		uint32_t mem_value = uint32_t(dataOut);
		err = mips_cpu_set_register(state, destination, mem_value);
	}

	if (op.compare("LB")==0){
		uint8_t dataOut;
		err= mips_mem_read(mem, imm_signed + *source1, 1, (uint8_t*)&dataOut);
		int32_t mem_value = int8_t(dataOut);
		err = mips_cpu_set_register(state, destination, mem_value);
	}

	if (op.compare("LHU")==0){
		if ((imm_signed + *source1)%2!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint16_t dataOut;
			err = mips_mem_read(mem, imm_signed + *source1, 2, (uint8_t*)&dataOut);
			uint32_t mem_value = uint32_t(endian16(dataOut));
			err = mips_cpu_set_register(state, destination, mem_value);
		}
	}

	if (op.compare("LH")==0){
		if ((imm_signed + *source1)%2!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint16_t dataOut;
			err = mips_mem_read(mem, imm_signed + *source1, 2, (uint8_t*)&dataOut);
			int32_t mem_value = int32_t(int16_t(endian16(dataOut)));
			err = mips_cpu_set_register(state, destination, mem_value);
		}
	}

	if (op.compare("SW")==0){
		if ((imm_signed + *source1)%4!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint32_t value = uint32_t(endian32(*source2));
			err = mips_mem_write(mem, imm_signed + *source1 ,4, (uint8_t*)&value);
		}
	}


	if (op.compare("SB")==0){
		uint8_t mem_value = *source2 & 0xFF;
		err = mips_mem_write(mem, imm_signed + *source1 ,1, (uint8_t*)&mem_value);
	}

	if (op.compare("SH")==0){
		if ((imm_signed + *source1)%2!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint16_t mem_value = endian16(uint16_t(*source2 & 0x0000FFFF));
			uint16_t value = uint16_t(mem_value);
			err = mips_mem_write(mem, imm_signed + *source1 ,2, (uint8_t*)&value);
		}
	}

	if (op.compare("LUI")==0)
		err = mips_cpu_set_register(state, destination, imm_signed << 16);

	if (op.compare("LWL")==0){
		uint32_t address = imm_signed + *source1;
		uint8_t length = 4 - int(address % 4);
		uint8_t dataOut[4];
		mips_error err= mips_mem_read(mem, address - int(address % 4), 4, dataOut);
		uint32_t mem_value = uint32_t(dataOut[3]) | (uint32_t(dataOut[2]) << 8) | (uint32_t(dataOut[1]) << 16) | (uint32_t(dataOut[0]) << 24);
		mem_value = uint32_t(mem_value) << (4-length)*8;
		*source2 = *source2 & (uint32_t(0xFFFFFFFF) >> length*8);
		*source2 = (uint32_t(mem_value)) | uint32_t(*source2);
		err = mips_cpu_set_register(state, destination, *source2);
	}

	if (op.compare("LWR")==0){
		uint32_t address = imm_signed + *source1;
		uint8_t length = int(address % 4) + 1;
		uint8_t dataOut[4];
		mips_error err= mips_mem_read(mem, address - int(address % 4), 4, dataOut);
		uint32_t mem_value = uint32_t(dataOut[3]) | (uint32_t(dataOut[2]) << 8) | (uint32_t(dataOut[1]) << 16) | (uint32_t(dataOut[0]) << 24);
		mem_value = uint32_t(mem_value) >> (4-length)*8;
		*source2 = *source2 & (uint32_t(0xFFFFFFFF) << length*8);
		*source2 = (uint32_t(mem_value)) | uint32_t(*source2);
		err = mips_cpu_set_register(state, destination, *source2);
	}

	//COUT OUTPUT
	if ((err==mips_Success) || (err==mips_ExceptionBreak)) {
		if ((op.compare("SB")==0) || (op.compare("SW")==0) || (op.compare("LBU")==0) || (op.compare("LW")==0)
		|| (op.compare("SH")==0) || (op.compare("LH")==0) || (op.compare("LHU")==0) || (op.compare("LB")==0))
		ss <<op<<" R["<<instruction_data[2]<<"],"<<" #"<<instruction_data[3]<<", R["<<instruction_data[1]<<"] ";

		if ((op.compare("BGEZ")==0) || (op.compare("BGEZAL")==0) || (op.compare("BGTZ")==0) || (op.compare("BLEZ")==0) ||
		(op.compare("BLTZAL")==0))
		ss <<op<<" R["<<instruction_data[1]<<"],"<<" #"<<instruction_data[3];

		if((op.compare("LUI")==0))
		ss <<op<<" R["<<instruction_data[2]<<"],"<<" #"<<instruction_data[3];

		if ((op.compare("BEQ")==0) || (op.compare("BNE")==0))
		ss <<op<<" R["<<instruction_data[1]<<"] , R["<<instruction_data[2]<<"], "<<"#"<<instruction_data[3];

		if (ss.str().empty())
		ss <<op<<" R["<<instruction_data[2]<<"] , R["<<instruction_data[1]<<"], "<<"#"<<instruction_data[3];
		instruction = ss.str();
	} else {
		instruction = "Invalid instruction format";
	}

	delete source1;
	return err;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1d8, %rsp            # imm = 0x1D8
movq %r9, %r14
movq %r8, 0x48(%rsp)
movq %rcx, %r12
movq %rdx, %r15
movq %rsi, 0x18(%rsp)
movq %rdi, %r13
leaq 0x50(%rsp), %rdi
callq 0x3150
movl $0x4, %edi
callq 0x31d0
movq %rax, 0x20(%rsp)
movl $0x4, %edi
callq 0x31d0
movl 0x4(%r15), %esi
movl 0x8(%r15), %ecx
movl %ecx, 0x4(%rsp)
movl 0xc(%r15), %ebx
movq %r13, %rdi
movq %rax, 0x8(%rsp)
movq %rax, %rdx
callq 0x4c44
movl $0x2004, %ebp           # imm = 0x2004
testl %eax, %eax
jne 0x7dec
movl 0x8(%r15), %esi
movq %r13, %rdi
movq 0x20(%rsp), %rdx
callq 0x4c44
testl %eax, %eax
jne 0x7dec
movswl %bx, %eax
movl %eax, 0x14(%rsp)
leaq 0x32ec(%rip), %rsi      # 0xa569
movq %r12, %rdi
callq 0x30a0
xorl %ebp, %ebp
testl %eax, %eax
jne 0x72a4
movq 0x8(%rsp), %rax
movl (%rax), %edx
addl 0x14(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x329b(%rip), %rsi      # 0xa546
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x72e9
movq 0x8(%rsp), %rax
movl (%rax), %esi
movl 0x14(%rsp), %edi
callq 0x805c
movl $0x2006, %ebp           # imm = 0x2006
testb %al, %al
jne 0x72e9
movq 0x8(%rsp), %rax
movl (%rax), %edx
addl 0x14(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x3750(%rip), %rsi      # 0xaa40
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7313
movq 0x8(%rsp), %rax
movl (%rax), %edx
orl %ebx, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x3725(%rip), %rsi      # 0xaa3f
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x733d
movq 0x8(%rsp), %rax
movl (%rax), %edx
xorl %ebx, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x3280(%rip), %rsi      # 0xa5c4
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7367
movq 0x8(%rsp), %rax
movl (%rax), %edx
andl %ebx, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x35c3(%rip), %rsi      # 0xa931
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7398
xorl %edx, %edx
movq 0x8(%rsp), %rax
movl 0x14(%rsp), %ecx
cmpl %ecx, (%rax)
setb %dl
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x3569(%rip), %rsi      # 0xa908
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x73c9
xorl %edx, %edx
movq 0x8(%rsp), %rax
movl 0x14(%rsp), %ecx
cmpl %ecx, (%rax)
setl %dl
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
movl %ebx, %eax
shll $0x10, %eax
movl %eax, 0x10(%rsp)
leaq 0x3206(%rip), %rsi      # 0xa5df
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7413
movq 0x8(%rsp), %rax
movl (%rax), %eax
xorl %ebp, %ebp
movq 0x20(%rsp), %rcx
cmpl (%rcx), %eax
jne 0x7413
movl (%r14), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x32d0(%rip), %rsi      # 0xa6ea
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7454
movq 0x8(%rsp), %rax
movl (%rax), %eax
xorl %ebp, %ebp
movq 0x20(%rsp), %rcx
cmpl (%rcx), %eax
je 0x7454
movl (%r14), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x3198(%rip), %rsi      # 0xa5f3
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7491
movq 0x8(%rsp), %rax
cmpl $0x0, (%rax)
js 0x748f
movl (%r14), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
jmp 0x7491
xorl %ebp, %ebp
leaq 0x31e1(%rip), %rsi      # 0xa679
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x74cc
xorl %ebp, %ebp
movq 0x8(%rsp), %rax
cmpl $0x0, (%rax)
jg 0x74cc
movl (%r14), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x3185(%rip), %rsi      # 0xa658
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7509
movq 0x8(%rsp), %rax
cmpl $0x0, (%rax)
jle 0x7507
movl (%r14), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
jmp 0x7509
xorl %ebp, %ebp
leaq 0x3193(%rip), %rsi      # 0xa6a3
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7544
xorl %ebp, %ebp
movq 0x8(%rsp), %rax
cmpl $0x0, (%rax)
jns 0x7544
movl (%r14), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x3176(%rip), %rsi      # 0xa6c1
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x759f
movl $0x1001, %ebp           # imm = 0x1001
cmpl $0x1f, 0x4(%r15)
je 0x759f
xorl %ebp, %ebp
movq 0x8(%rsp), %rax
cmpl $0x0, (%rax)
jns 0x759f
movq 0x210(%rsp), %rbp
movl (%rbp), %edx
addl $0x8, %edx
movq %r13, %rdi
movl $0x1f, %esi
callq 0x4c64
movl (%r14), %eax
movl %eax, (%rbp)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x307a(%rip), %rsi      # 0xa620
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x75fc
movl $0x1001, %ebp           # imm = 0x1001
cmpl $0x1f, 0x4(%r15)
je 0x75fc
movq 0x8(%rsp), %rax
cmpl $0x0, (%rax)
js 0x75fa
movq 0x210(%rsp), %rbp
movl (%rbp), %edx
addl $0x8, %edx
movq %r13, %rdi
movl $0x1f, %esi
callq 0x4c64
movl (%r14), %eax
movl %eax, (%rbp)
movl 0x10(%rsp), %eax
sarl $0xe, %eax
addl %eax, (%r14)
movl $0x2000, %ebp           # imm = 0x2000
jmp 0x75fc
xorl %ebp, %ebp
leaq 0x31d0(%rip), %rsi      # 0xa7d3
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
movl 0x14(%rsp), %r14d
jne 0x7652
movq 0x8(%rsp), %rax
movl (%rax), %esi
leal (%rsi,%rbx), %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x3, %al
jne 0x7652
addl %r14d, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x4, %edx
callq 0x4ad9
movl 0x28(%rsp), %edx
bswapl %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x311c(%rip), %rsi      # 0xa775
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7696
movq 0x8(%rsp), %rax
movl (%rax), %esi
addl %r14d, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x1, %edx
callq 0x4ad9
movzbl 0x28(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x30cb(%rip), %rsi      # 0xa768
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x76da
movq 0x8(%rsp), %rax
movl (%rax), %esi
addl %r14d, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x1, %edx
callq 0x4ad9
movsbl 0x28(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x30bd(%rip), %rsi      # 0xa79e
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7732
movq 0x8(%rsp), %rax
movl (%rax), %esi
leal (%rsi,%rbx), %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x1, %al
jne 0x7732
addl %r14d, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x2, %edx
callq 0x4ad9
leaq 0x28(%rsp), %rdi
callq 0x80aa
movzwl %ax, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x3053(%rip), %rsi      # 0xa78c
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x778a
movq 0x8(%rsp), %rax
movl (%rax), %esi
leal (%rsi,%rbx), %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x1, %al
jne 0x778a
addl %r14d, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x2, %edx
callq 0x4ad9
leaq 0x28(%rsp), %rdi
callq 0x80aa
movswl %ax, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
movl %eax, %ebp
leaq 0x3287(%rip), %rsi      # 0xaa18
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x77db
movq 0x8(%rsp), %rax
movl (%rax), %eax
addl %ebx, %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x3, %al
jne 0x77db
movq 0x20(%rsp), %rdi
callq 0x80a5
leaq 0x28(%rsp), %rcx
movl %eax, (%rcx)
movq 0x8(%rsp), %rax
movl (%rax), %esi
addl %r14d, %esi
movq 0x18(%rsp), %rdi
movl $0x4, %edx
callq 0x4b72
movl %eax, %ebp
leaq 0x30af(%rip), %rsi      # 0xa891
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7817
movq 0x20(%rsp), %rax
movb (%rax), %al
leaq 0x28(%rsp), %rcx
movb %al, (%rcx)
movq 0x8(%rsp), %rax
movl (%rax), %esi
addl %r14d, %esi
movq 0x18(%rsp), %rdi
movl $0x1, %edx
callq 0x4b72
movl %eax, %ebp
leaq 0x3081(%rip), %rsi      # 0xa89f
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7873
movq 0x8(%rsp), %rax
addl (%rax), %ebx
movl $0x2003, %ebp           # imm = 0x2003
testb $0x1, %bl
jne 0x7873
movq 0x20(%rsp), %rax
movzwl (%rax), %eax
leaq 0x28(%rsp), %rdi
movw %ax, (%rdi)
callq 0x80aa
leaq 0x28(%rsp), %rcx
movw %ax, (%rcx)
movq 0x8(%rsp), %rax
movl (%rax), %esi
addl %r14d, %esi
movq 0x18(%rsp), %rdi
movl $0x2, %edx
callq 0x4b72
movl %eax, %ebp
leaq 0x2f40(%rip), %rsi      # 0xa7ba
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7898
movq %r13, %rdi
movl 0x4(%rsp), %esi
movl 0x10(%rsp), %edx
callq 0x4c64
movl %eax, %ebp
leaq 0x2f41(%rip), %rsi      # 0xa7e0
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7901
movq 0x8(%rsp), %rax
movl (%rax), %r14d
addl 0x14(%rsp), %r14d
movl %r14d, %esi
andl $-0x4, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x4, %edx
callq 0x4ad9
movl 0x28(%rsp), %edx
bswapl %edx
shll $0x3, %r14d
movq 0x20(%rsp), %rsi
movl (%rsi), %eax
movl %r14d, %ecx
andb $0x18, %cl
negb %cl
shll %cl, %eax
movl %r14d, %ecx
shldl %cl, %eax, %edx
movl %edx, (%rsi)
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
leaq 0x2eeb(%rip), %rsi      # 0xa7f3
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x796b
movq 0x8(%rsp), %rax
movl 0x14(%rsp), %ebx
addl (%rax), %ebx
movl %ebx, %esi
andl $-0x4, %esi
leaq 0x28(%rsp), %rcx
movq 0x18(%rsp), %rdi
movl $0x4, %edx
callq 0x4ad9
movl 0x28(%rsp), %eax
bswapl %eax
shll $0x3, %ebx
andl $0x18, %ebx
movl %ebx, %ecx
xorb $0x18, %cl
shrl %cl, %eax
movl $0xffffff00, %edx       # imm = 0xFFFFFF00
movl %ebx, %ecx
shll %cl, %edx
movq 0x20(%rsp), %rcx
andl (%rcx), %edx
orl %eax, %edx
movl %edx, (%rcx)
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4c64
testl $0xffffdfff, %ebp       # imm = 0xFFFFDFFF
je 0x7995
movq 0x48(%rsp), %rdi
movq 0x8(%rdi), %rdx
leaq 0x3329(%rip), %rcx      # 0xacac
movl $0x1a, %r8d
xorl %esi, %esi
callq 0x32d0
jmp 0x7ddd
leaq 0x2ef5(%rip), %rsi      # 0xa891
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x3065(%rip), %rsi      # 0xaa18
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x2daf(%rip), %rsi      # 0xa775
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x2dfa(%rip), %rsi      # 0xa7d3
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x2eb3(%rip), %rsi      # 0xa89f
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x2d8d(%rip), %rsi      # 0xa78c
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x2d8c(%rip), %rsi      # 0xa79e
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7a35
leaq 0x2d43(%rip), %rsi      # 0xa768
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7ad9
leaq 0x60(%rsp), %rdi
movq (%r12), %rsi
movq 0x8(%r12), %rdx
callq 0x3210
movq %rax, %r14
leaq 0x327d(%rip), %rsi      # 0xaccf
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
movl 0x8(%r15), %esi
movq %r14, %rdi
callq 0x3120
movq %rax, %r14
leaq 0x3277(%rip), %rsi      # 0xacec
movl $0x2, %edx
movq %rax, %rdi
callq 0x3210
leaq 0x324c(%rip), %rsi      # 0xacd5
movl $0x2, %edx
movq %r14, %rdi
callq 0x3210
movl 0xc(%r15), %esi
movq %r14, %rdi
callq 0x3120
movq %rax, %r14
leaq 0x3222(%rip), %rsi      # 0xacce
movl $0x4, %edx
movq %rax, %rdi
callq 0x3210
movl 0x4(%r15), %esi
movq %r14, %rdi
callq 0x3120
leaq 0x3223(%rip), %rsi      # 0xacef
movl $0x2, %edx
movq %rax, %rdi
callq 0x3210
leaq 0x2b13(%rip), %rsi      # 0xa5f3
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7b38
leaq 0x2b2d(%rip), %rsi      # 0xa620
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7b38
leaq 0x2b52(%rip), %rsi      # 0xa658
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7b38
leaq 0x2b60(%rip), %rsi      # 0xa679
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7b38
leaq 0x2b95(%rip), %rsi      # 0xa6c1
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7ba5
leaq 0x60(%rsp), %rdi
movq (%r12), %rsi
movq 0x8(%r12), %rdx
callq 0x3210
movq %rax, %r14
leaq 0x317a(%rip), %rsi      # 0xaccf
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
movl 0x4(%r15), %esi
movq %r14, %rdi
callq 0x3120
movq %rax, %r14
leaq 0x3174(%rip), %rsi      # 0xacec
movl $0x2, %edx
movq %rax, %rdi
callq 0x3210
leaq 0x3149(%rip), %rsi      # 0xacd5
movl $0x2, %edx
movq %r14, %rdi
callq 0x3210
movl 0xc(%r15), %esi
movq %r14, %rdi
callq 0x3120
leaq 0x2c0e(%rip), %rsi      # 0xa7ba
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7c25
leaq 0x60(%rsp), %rdi
movq (%r12), %rsi
movq 0x8(%r12), %rdx
callq 0x3210
movq %rax, %r14
leaq 0x30fa(%rip), %rsi      # 0xaccf
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
movl 0x8(%r15), %esi
movq %r14, %rdi
callq 0x3120
movq %rax, %r14
leaq 0x30f4(%rip), %rsi      # 0xacec
movl $0x2, %edx
movq %rax, %rdi
callq 0x3210
leaq 0x30c9(%rip), %rsi      # 0xacd5
movl $0x2, %edx
movq %r14, %rdi
callq 0x3210
movl 0xc(%r15), %esi
movq %r14, %rdi
callq 0x3120
leaq 0x29b3(%rip), %rsi      # 0xa5df
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
je 0x7c4f
leaq 0x2aab(%rip), %rsi      # 0xa6ea
movq %r12, %rdi
callq 0x30a0
testl %eax, %eax
jne 0x7cdf
leaq 0x60(%rsp), %rdi
movq (%r12), %rsi
movq 0x8(%r12), %rdx
callq 0x3210
movq %rax, %r14
leaq 0x3063(%rip), %rsi      # 0xaccf
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
movl 0x4(%r15), %esi
movq %r14, %rdi
callq 0x3120
movq %rax, %r14
leaq 0x303d(%rip), %rsi      # 0xaccc
movl $0x6, %edx
movq %rax, %rdi
callq 0x3210
movl 0x8(%r15), %esi
movq %r14, %rdi
callq 0x3120
movq %rax, %r14
leaq 0x3040(%rip), %rsi      # 0xacf2
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
leaq 0x3010(%rip), %rsi      # 0xacd6
movl $0x1, %edx
movq %r14, %rdi
callq 0x3210
movl 0xc(%r15), %esi
movq %r14, %rdi
callq 0x3120
leaq 0x68(%rsp), %r14
leaq 0x28(%rsp), %rdi
movq %r14, %rsi
callq 0x32f0
leaq 0x38(%rsp), %rbx
movq -0x10(%rbx), %rdi
movq -0x8(%rbx), %r13
cmpq %rbx, %rdi
je 0x7d10
movq 0x38(%rsp), %rsi
incq %rsi
callq 0x31e0
testq %r13, %r13
jne 0x7da9
leaq 0x60(%rsp), %rdi
movq (%r12), %rsi
movq 0x8(%r12), %rdx
callq 0x3210
movq %rax, %r12
leaq 0x2f99(%rip), %rsi      # 0xaccf
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
movl 0x8(%r15), %esi
movq %r12, %rdi
callq 0x3120
movq %rax, %r12
leaq 0x2f73(%rip), %rsi      # 0xaccc
movl $0x6, %edx
movq %rax, %rdi
callq 0x3210
movl 0x4(%r15), %esi
movq %r12, %rdi
callq 0x3120
movq %rax, %r12
leaq 0x2f76(%rip), %rsi      # 0xacf2
movl $0x3, %edx
movq %rax, %rdi
callq 0x3210
leaq 0x2f46(%rip), %rsi      # 0xacd6
movl $0x1, %edx
movq %r12, %rdi
callq 0x3210
movl 0xc(%r15), %esi
movq %r12, %rdi
callq 0x3120
leaq 0x28(%rsp), %rdi
movq %r14, %rsi
callq 0x32f0
leaq 0x28(%rsp), %r14
movq 0x48(%rsp), %rdi
movq %r14, %rsi
callq 0x3250
movq (%r14), %rdi
cmpq %rbx, %rdi
je 0x7ddd
movq 0x38(%rsp), %rsi
incq %rsi
callq 0x31e0
movl $0x4, %esi
movq 0x8(%rsp), %rdi
callq 0x31e0
movq 0x71bd(%rip), %rsi      # 0xefb0
leaq 0x50(%rsp), %rdi
callq 0x3170
leaq 0xd0(%rsp), %rdi
callq 0x30b0
movl %ebp, %eax
addq $0x1d8, %rsp            # imm = 0x1D8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
jmp 0x7e4a
movq %rax, %rbx
movq 0x715c(%rip), %rsi      # 0xefb0
leaq 0x50(%rsp), %rdi
callq 0x3170
leaq 0xd0(%rsp), %rdi
callq 0x30b0
movq %rbx, %rdi
callq 0x3330