// File: /workspace/github_c_makefile_star2_O3/mbitsnbites[P]SoftFP/./softfp_template_icvt.h
// Function: internal_cvt_sf32_i128
static ICVT_INT glue(glue(glue(internal_cvt_sf, F_SIZE), _i), ICVT_SIZE)(F_UINT a, RoundingModeEnum rm,
                                                                         uint32_t *pfflags, BOOL is_unsigned)
{
    uint32_t a_sign, addend, rnd_bits;
    int32_t a_exp;
    F_UINT a_mant;
    ICVT_UINT r, r_max;

    a_sign = a >> (F_SIZE - 1);
    a_exp = (a >> MANT_SIZE) & EXP_MASK;
    a_mant = a & MANT_MASK;
    if (a_exp == EXP_MASK && a_mant != 0)
        a_sign = 0; /* NaN is like +infinity */
    if (a_exp == 0) {
        a_exp = 1;
    } else {
        a_mant |= (F_UINT)1 << MANT_SIZE;
    }
    a_mant <<= RND_SIZE;
    a_exp = a_exp - (EXP_MASK / 2) - MANT_SIZE;

    if (is_unsigned)
        r_max = (ICVT_UINT)a_sign - 1;
    else
        r_max = ((ICVT_UINT)1 << (ICVT_SIZE - 1)) - (ICVT_UINT)(a_sign ^ 1);
    if (a_exp >= 0) {
        if (a_exp <= (ICVT_SIZE - 1 - MANT_SIZE)) {
            r = (ICVT_UINT)(a_mant >> RND_SIZE) << a_exp;
            if (r > r_max)
                goto overflow;
        } else {
        overflow:
            *pfflags |= FFLAG_INVALID_OP;
            return r_max;
        }
    } else {
        a_mant = rshift_rnd(a_mant, -a_exp);

        switch(rm) {
        case RM_RNE:
        case RM_RMM:
            addend = (1 << (RND_SIZE - 1));
            break;
        case RM_RTZ:
            addend = 0;
            break;
        default:
        case RM_RDN:
        case RM_RUP:
            if (a_sign ^ (rm & 1))
                addend = (1 << RND_SIZE) - 1;
            else
                addend = 0;
            break;
        }
        
        rnd_bits = a_mant & ((1 << RND_SIZE ) - 1);
        a_mant = (a_mant + addend) >> RND_SIZE;
        /* half way: select even result */
        if (rm == RM_RNE && rnd_bits == (1 << (RND_SIZE - 1)))
            a_mant &= ~1;
        if (a_mant > r_max)
            goto overflow;
        r = a_mant;
        if (rnd_bits != 0)
            *pfflags |= FFLAG_INEXACT;
    }
    if (a_sign)
        r = -r;
    return r;
}

// Assembly:
pushq %rbx
movl %ecx, %r8d
movl %edi, %eax
shrl $0x1f, %eax
movl %edi, %ecx
shrl $0x17, %ecx
movl $0xff, %r9d
andl %r9d, %ecx
andl $0x7fffff, %edi         # imm = 0x7FFFFF
xorl %r11d, %r11d
cmpl %r9d, %ecx
movl %eax, %r9d
cmovel %r11d, %r9d
testl %edi, %edi
cmovel %eax, %r9d
leal 0x800000(%rdi), %r10d
leal -0x96(%rcx), %eax
testl %ecx, %ecx
movl $0xffffff6b, %ecx       # imm = 0xFFFFFF6B
cmovnel %eax, %ecx
cmovel %edi, %r10d
movq %r9, %rbx
addq $-0x1, %rbx
adcq $-0x1, %r11
movl %r9d, %eax
xorl $0x1, %eax
negq %rax
movabsq $-0x8000000000000000, %rdi # imm = 0x8000000000000000
sbbq $0x0, %rdi
testl %r8d, %r8d
cmovneq %rbx, %rax
cmovneq %r11, %rdi
testl %ecx, %ecx
js 0x6009
movl %r10d, %esi
xorl %r8d, %r8d
shldq %cl, %rsi, %r8
shlq %cl, %rsi
xorl %r10d, %r10d
testb $0x40, %cl
cmovneq %rsi, %r8
cmovneq %r10, %rsi
cmpl $0x68, %ecx
ja 0x6099
cmpq %rsi, %rax
movq %rdi, %rcx
sbbq %r8, %rcx
jae 0x60ab
jmp 0x6099
negl %ecx
cmpl $0x20, %ecx
jb 0x601a
xorl %ecx, %ecx
testl %r10d, %r10d
setne %cl
jmp 0x603b
movl $0xffffffff, %r8d       # imm = 0xFFFFFFFF
shll %cl, %r8d
shll $0x7, %r10d
notl %r8d
movl %r10d, %r11d
shrl %cl, %r11d
xorl %ecx, %ecx
testl %r8d, %r10d
setne %cl
orl %r11d, %ecx
movl $0x40, %r8d
testl %esi, %esi
je 0x606b
cmpl $0x4, %esi
je 0x606b
cmpl $0x1, %esi
jne 0x6054
xorl %r8d, %r8d
jmp 0x606b
movl %esi, %r8d
andl $0x1, %r8d
xorl %r10d, %r10d
cmpl %r8d, %r9d
movl $0x7f, %r8d
cmovel %r10d, %r8d
addl %ecx, %r8d
andl $0x7f, %ecx
shrl $0x7, %r8d
movl %ecx, %r11d
xorl $0x40, %r11d
movl %r8d, %r10d
andl $0xfffffe, %r10d        # imm = 0xFFFFFE
orl %r11d, %esi
cmovnel %r8d, %r10d
cmpq %r10, %rax
movq %rdi, %rsi
sbbq $0x0, %rsi
jae 0x609e
orb $0x10, (%rdx)
jmp 0x60c1
movl %r10d, %esi
xorl %r8d, %r8d
testl %ecx, %ecx
je 0x60ab
orb $0x1, (%rdx)
xorl %edi, %edi
movq %rsi, %rax
negq %rax
sbbq %r8, %rdi
testl %r9d, %r9d
cmoveq %rsi, %rax
cmoveq %r8, %rdi
movq %rdi, %rdx
popq %rbx
retq