// File: /workspace/github_c_makefile_star2_O2/lucvoo[P]sparse-dev/target-riscv.c
// Function: predefine_riscv
static void predefine_riscv(const struct target *self)
{
	static const char *cmodels[CMODEL_LAST] = {
		[CMODEL_MEDANY] = "medany",
		[CMODEL_MEDLOW] = "medlow",
		[CMODEL_PIC]    = "pic",
	};
	const char *cmodel = cmodels[arch_cmodel];

	predefine("__riscv", 1, "1");
	predefine("__riscv_xlen", 1, "%d", ptr_ctype.bit_size);

	if (riscv_flags & RISCV_ATOMIC)
		predefine("__riscv_atomic", 1, "1");
	if (riscv_flags & RISCV_COMP)
		predefine("__riscv_compressed", 1, "1");
	if (riscv_flags & RISCV_DIV)
		predefine("__riscv_div", 1, "1");
	if (riscv_flags & RISCV_EMBD)
		predefine("__riscv_32e", 1, "1");
	if (riscv_flags & RISCV_FPU)
		predefine("__riscv_flen", 1, "%d", (riscv_flags & RISCV_DOUBLE) ? 64 : 32);
	if (riscv_flags & RISCV_FDIV)
		predefine("__riscv_fdiv", 1, "1");
	if (riscv_flags & RISCV_FDIV)
		predefine("__riscv_fsqrt", 1, "1");
	if (riscv_flags & RISCV_MUL)
		predefine("__riscv_mul", 1, "1");
	if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV))
		predefine("__riscv_muldiv", 1, "1");
	if (riscv_flags & RISCV_ZICSR)
		predefine("__riscv_zicsr", 1, "1");
	if (riscv_flags & RISCV_ZIFENCEI)
		predefine("__riscv_zifencei", 1, "1");
	if (riscv_flags & RISCV_ZICBOM)
		predefine("__riscv_zicbom", 1, "1");
	if (riscv_flags & RISCV_ZIHINTPAUSE)
		predefine("__riscv_zihintpause", 1, "1");

	if (cmodel)
		predefine_strong("__riscv_cmodel_%s", cmodel);
}

// Assembly:
pushq %rbp
pushq %r14
pushq %rbx
leaq 0x38416(%rip), %rax     # 0x60d9c
movslq (%rax), %r14
leaq 0x2cc30(%rip), %rax     # 0x555c0
movq (%rax,%r14,8), %rbx
leaq 0x186b9(%rip), %rdi     # 0x41054
leaq 0x1bad1(%rip), %rdx     # 0x44473
pushq $0x1
popq %rbp
movl %ebp, %esi
xorl %eax, %eax
callq 0x1c59c
leaq 0x3db83(%rip), %rax     # 0x66538
movl 0x50(%rax), %ecx
leaq 0x1869d(%rip), %rdi     # 0x4105c
leaq 0x11d8b(%rip), %rdx     # 0x3a751
movl %ebp, %esi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f5c3(%rip), %ecx     # 0x67f98
testb $0x10, %cl
je 0x289f8
leaq 0x18688(%rip), %rdi     # 0x41069
leaq 0x1ba8b(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f5a0(%rip), %ecx     # 0x67f98
btl $0x8, %ecx
jae 0x28a1c
leaq 0x18673(%rip), %rdi     # 0x41078
leaq 0x1ba67(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f57c(%rip), %ecx     # 0x67f98
testb $0x8, %cl
je 0x28a3f
leaq 0x18663(%rip), %rdi     # 0x4108b
leaq 0x1ba44(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f559(%rip), %ecx     # 0x67f98
btl $0x9, %ecx
jae 0x28a63
leaq 0x1864b(%rip), %rdi     # 0x41097
leaq 0x1ba20(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f535(%rip), %ecx     # 0x67f98
testb $-0x20, %cl
je 0x28a8e
andl $0x40, %ecx
shrl %ecx
addl $0x20, %ecx
leaq 0x1862c(%rip), %rdi     # 0x410a3
leaq 0x11cd3(%rip), %rdx     # 0x3a751
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f50a(%rip), %ecx     # 0x67f98
testb %cl, %cl
jns 0x28ad2
leaq 0x18617(%rip), %rdi     # 0x410b0
leaq 0x1b9d3(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f4e8(%rip), %ecx     # 0x67f98
testb %cl, %cl
jns 0x28ad2
leaq 0x18602(%rip), %rdi     # 0x410bd
leaq 0x1b9b1(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f4c6(%rip), %ecx     # 0x67f98
testb $0x4, %cl
je 0x28af5
leaq 0x185ed(%rip), %rdi     # 0x410cb
leaq 0x1b98e(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f4a3(%rip), %ecx     # 0x67f98
movl %ecx, %eax
notl %eax
testb $0xc, %al
jne 0x28b1b
leaq 0x185d3(%rip), %rdi     # 0x410d7
leaq 0x1b968(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f47d(%rip), %ecx     # 0x67f98
btl $0xa, %ecx
jae 0x28b3f
leaq 0x185be(%rip), %rdi     # 0x410e6
leaq 0x1b944(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f459(%rip), %ecx     # 0x67f98
btl $0xb, %ecx
jae 0x28b63
leaq 0x185a8(%rip), %rdi     # 0x410f4
leaq 0x1b920(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f435(%rip), %ecx     # 0x67f98
btl $0xc, %ecx
jae 0x28b87
leaq 0x18595(%rip), %rdi     # 0x41105
leaq 0x1b8fc(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl 0x3f411(%rip), %ecx     # 0x67f98
btl $0xd, %ecx
jae 0x28ba5
leaq 0x18580(%rip), %rdi     # 0x41114
leaq 0x1b8d8(%rip), %rdx     # 0x44473
pushq $0x1
popq %rsi
xorl %eax, %eax
callq 0x1c59c
movl $0x197, %eax            # imm = 0x197
btq %r14, %rax
jb 0x28bc5
leaq 0x18571(%rip), %rdi     # 0x41128
movq %rbx, %rsi
xorl %eax, %eax
popq %rbx
popq %r14
popq %rbp
jmp 0x1cabc
popq %rbx
popq %r14
popq %rbp
retq