// File: /workspace/github_c_makefile_star2_O1/xiane[P]libvphevcodec/AML_HEVCEncoder.cpp
// Function: Wave4VpuEncGetHeader(AMVHEVCEncHandle_s*, unsigned char*, unsigned int*)
AMVEnc_Status Wave4VpuEncGetHeader(AMVHEVCEncHandle *Handle, unsigned char *buffer, unsigned int *buf_nal_size) {
    Uint32 addr_report_buf = 0;    // [31:0]
    Uint32 report_buf_size = 0;    // [31:0]
    unsigned char report_endian = 0;    // [ 3:0]
    //Uint32 use_sec_axi = 0;    // [31:0]
    //Uint32 sec_axi_buf_size = 0x00012800;   // 74KB

    // Bitstream Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_BS_START_ADDR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_SIZE, Handle->bs_vb.size - 0x8000);
    VpuWriteReg(Handle->instance_id, W4_BS_PARAM, 0xf);
    VpuWriteReg(Handle->instance_id, W4_BS_OPTION, 0);

    uint32_t current_idx = 0;
    current_idx |= (0 << 24); // [27:24] codec_std_aux
    current_idx |= (1 << 16); // [23:16] codec_std
    current_idx |= (Handle->instance_id << 0);  // [15: 0] Handle->instance_id
    VpuWriteReg(Handle->instance_id, W4_INST_INDEX, current_idx);

    // Work Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_WORK_BASE, Handle->work_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_WORK_SIZE, Handle->work_vb.size);
    VpuWriteReg(Handle->instance_id, W4_WORK_PARAM, 0);

    // Temp Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_TEMP_BASE, Handle->temp_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_TEMP_SIZE, Handle->temp_vb.size);
    VpuWriteReg(Handle->instance_id, W4_TEMP_PARAM, gol_endian);

    VpuWriteReg(Handle->instance_id, W4_BS_RD_PTR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_WR_PTR, Handle->bs_vb.phys_addr);

    /* Secondary AXI */
    VpuWriteReg(Handle->instance_id, W4_ADDR_SEC_AXI, 0);
    VpuWriteReg(Handle->instance_id, W4_SEC_AXI_SIZE, 0);
    VpuWriteReg(Handle->instance_id, W4_USE_SEC_AXI, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_ADDR_REPORT_BASE, addr_report_buf);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_SIZE, report_buf_size);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_PARAM, report_endian);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SRC_PIC_IDX, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_CODE_OPTION, 0x1c);

    VpuWriteReg(Handle->instance_id, W4_VPU_BUSY_STATUS, 1);
    VpuWriteReg(Handle->instance_id, W4_RET_SUCCESS, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_CORE_INDEX, 0);
    VpuWriteReg(Handle->instance_id, W4_COMMAND, ENC_PIC);
    VpuWriteReg(Handle->instance_id, W4_VPU_HOST_INT_REQ, 1);

    uint32_t status = VpuReadReg(Handle->instance_id, W4_VPU_BUSY_STATUS);
    VLOG(DEBUG, "W4_VPU_BUSY_STATUS :0x%x\n", status);

    if (vdi_wait_interrupt(Handle->instance_id, VPU_BUSY_CHECK_TIMEOUT) == -1) {
        VLOG(ERR, "Wave4VpuEncGetHeader error time out\n");
        return AMVENC_TIMEOUT;
    }

    if (VpuReadReg(Handle->instance_id, W4_RET_SUCCESS) == 0) {
        uint32_t reasonCode = VpuReadReg(Handle->instance_id, W4_RET_FAIL_REASON);
        VLOG(ERR, "Wave4VpuEncGetHeader failedREASON CODE(%08x)\n", reasonCode);
        return AMVENC_HARDWARE;
    }
    uint32_t result = VpuReadReg(Handle->instance_id, W4_RET_SUCCESS);
    VLOG(DEBUG, "W4_RET_SUCCESS %x\n", result);

    {
        Uint32 rd_ptr, wr_ptr;

        rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
        wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
        uint32_t header_length = VpuReadReg(Handle->instance_id, W4_RET_ENC_PIC_BYTE);

        if (header_length > Handle->mOutputBufferLen) {
            VLOG(ERR, "nal size %d bigger than output buffer %d!\n", header_length, Handle->mOutputBufferLen);
            return AMVENC_OVERFLOW;
        }
        *buf_nal_size = header_length;
        vdi_read_memory(Handle->instance_id, rd_ptr, (unsigned char *) buffer, header_length);
        VpuWriteReg(Handle->instance_id, W4_BS_RD_PTR, wr_ptr);
        VLOG(DEBUG, "Wave4VpuEncGetHeader, rd:0x%x, wr:0x%x, ret bytes: %d, buffer size:%d\n", rd_ptr, wr_ptr, header_length, wr_ptr - rd_ptr);
    }
    return AMVENC_SUCCESS;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movl (%rdi), %edi
movl 0x88(%rbx), %edx
movl $0x120, %esi            # imm = 0x120
callq 0x2150
movl (%rbx), %edi
movl $0xffff8000, %edx       # imm = 0xFFFF8000
addl 0x80(%rbx), %edx
movl $0x124, %esi            # imm = 0x124
callq 0x2150
movl (%rbx), %edi
movl $0x128, %esi            # imm = 0x128
movl $0xf, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x12c, %esi            # imm = 0x12C
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl %edi, %edx
orl $0x10000, %edx          # imm = 0x10000
movl $0x108, %esi            # imm = 0x108
callq 0x2150
movl (%rbx), %edi
movl 0x48(%rbx), %edx
movl $0x138, %esi            # imm = 0x138
callq 0x2150
movl (%rbx), %edi
movl 0x40(%rbx), %edx
movl $0x13c, %esi            # imm = 0x13C
callq 0x2150
movl (%rbx), %edi
movl $0x140, %esi            # imm = 0x140
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl 0x68(%rbx), %edx
movl $0x144, %esi            # imm = 0x144
callq 0x2150
movl (%rbx), %edi
movl 0x60(%rbx), %edx
movl $0x148, %esi            # imm = 0x148
callq 0x2150
movl (%rbx), %edi
movl $0x14c, %esi            # imm = 0x14C
movl $0xf, %edx
callq 0x2150
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x130, %esi            # imm = 0x130
callq 0x2150
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x134, %esi            # imm = 0x134
callq 0x2150
movl (%rbx), %edi
movl $0x150, %esi            # imm = 0x150
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x154, %esi            # imm = 0x154
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x158, %esi            # imm = 0x158
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x15c, %esi            # imm = 0x15C
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x160, %esi            # imm = 0x160
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x164, %esi            # imm = 0x164
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x170, %esi            # imm = 0x170
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x168, %esi            # imm = 0x168
movl $0x1c, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x70, %esi
movl $0x1, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x104, %esi            # imm = 0x104
xorl %edx, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x100, %esi            # imm = 0x100
movl $0x8, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x38, %esi
movl $0x1, %edx
callq 0x2150
movl (%rbx), %edi
movl $0x70, %esi
callq 0x2200
movl (%rbx), %edi
movl $0x1388, %esi           # imm = 0x1388
callq 0x2340
cmpl $-0x1, %eax
je 0x5fb7
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2200
movl (%rbx), %edi
testl %eax, %eax
je 0x5fd4
movl $0x110, %esi            # imm = 0x110
callq 0x2200
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2200
movl %eax, %r12d
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2200
movl %eax, %ebp
movl (%rbx), %edi
movl $0x1c8, %esi            # imm = 0x1C8
callq 0x2200
movl 0x300(%rbx), %edx
cmpl %edx, %eax
jbe 0x5fff
leaq 0x26f74(%rip), %rdi     # 0x2cf11
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
movl $0xa, %edi
callq 0x2220
movl $0xffffffd9, %eax       # imm = 0xFFFFFFD9
jmp 0x6024
leaq 0x272c8(%rip), %rdi     # 0x2d286
callq 0x2280
movl $0xa, %edi
callq 0x2220
movl $0xffffffdc, %eax       # imm = 0xFFFFFFDC
jmp 0x6024
movl $0x114, %esi            # imm = 0x114
callq 0x2200
leaq 0x26efe(%rip), %rdi     # 0x2cee3
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
movl $0xa, %edi
callq 0x2220
movl $0xffffffdb, %eax       # imm = 0xFFFFFFDB
jmp 0x6024
movl %eax, (%r15)
movl (%rbx), %edi
movl %r12d, %esi
movq %r14, %rdx
movl %eax, %ecx
callq 0x2100
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
movl %ebp, %edx
callq 0x2150
movl $0x1, %eax
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq