// File: NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::schedule(PACKET_QUEUE*)
void DRC_MEMORY_CONTROLLER::schedule(PACKET_QUEUE *queue)
{
    uint64_t drc_addr;
    uint32_t drc_channel, drc_rank, drc_bank, drc_row;
    uint8_t  row_buffer_hit = 0;

    int oldest_index = -1;
    uint64_t oldest_cycle = UINT64_MAX;

    // first, search for the oldest open row hit
    for (uint32_t i=0; i<queue->SIZE; i++) {

        // empty entry
        drc_addr = queue->entry[i].address;
        if (drc_addr == 0)
            continue;

        // already scheduled
        if (queue->entry[i].scheduled) { 
            //cout << queue->NAME << " index: " << i << " is already scheduled" << endl;
            continue;
        }

        drc_channel = drc_get_channel(drc_addr);
        drc_rank = drc_get_rank(drc_addr);
        drc_bank = drc_get_bank(drc_addr);

        // bank is busy
        if (bank_request[drc_channel][drc_rank][drc_bank].working) {

            //DP ( if (warmup_complete[0]) {
            //cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " bank is busy";
            //cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            //cout << " write: " << +bank_request[drc_channel][drc_rank][drc_bank].is_write << " read: " << +bank_request[drc_channel][drc_rank][drc_bank].is_read << hex;
            //cout << " address: " << queue->entry[i].address << dec << " channel: " << drc_channel << " rank: " << drc_rank << " bank: " << drc_bank << endl; });
            //cout << queue->NAME << " index: " << i << " rank: " << drc_rank << " bank: " << drc_bank << " is busy" << endl;

            continue;
        }

        // check open row
        drc_row = drc_get_row(drc_addr);
        if (bank_request[drc_channel][drc_rank][drc_bank].open_row != drc_row) {

            /*
            DP ( if (warmup_complete[0]) {
            cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " row is inactive";
            cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            cout << " write: " << +bank_request[drc_channel][drc_rank][drc_bank].is_write << " read: " << +bank_request[drc_channel][drc_rank][drc_bank].is_read << hex;
            cout << " address: " << queue->entry[i].address << dec << " channel: " << drc_channel << " rank: " << drc_rank << " bank: " << drc_bank << endl; });
            */
            //cout << queue->NAME << " index: " << i << " event_cycle: " << queue->entry[i].event_cycle << " is selected" << endl;

            continue;
        }

        // select the oldest entry
        if (queue->entry[i].event_cycle < oldest_cycle) {
            oldest_cycle = queue->entry[i].event_cycle;
            oldest_index = i;
            row_buffer_hit = 1;
        }	  
    }

    if (oldest_index == -1) { // no matching open_row (row buffer miss)

        oldest_cycle = UINT64_MAX;
        for (uint32_t i=0; i<queue->SIZE; i++) {

            // empty entry
            drc_addr = queue->entry[i].address;
            if (drc_addr == 0)
                continue;
            
            // already scheduled
            if (queue->entry[i].scheduled) {
                //cout << queue->NAME << " index: " << i << " is already scheduled" << endl;
                continue;
            }

            drc_channel = drc_get_channel(drc_addr);
            drc_rank = drc_get_rank(drc_addr);
            drc_bank = drc_get_bank(drc_addr);

            // bank is busy
            if (bank_request[drc_channel][drc_rank][drc_bank].working) { 
                //cout << queue->NAME << " index: " << i << " rank: " << drc_rank << " bank: " << drc_bank << " is busy" << endl;
                continue;
            }

            // select the oldest entry
            if (queue->entry[i].event_cycle < oldest_cycle) {
                oldest_cycle = queue->entry[i].event_cycle;
                oldest_index = i;
                //cout << queue->NAME << " index: " << i << " event_cycle: " << queue->entry[i].event_cycle << " is selected" << endl;
            }
        }
    }

    // at this point, the scheduler knows which channel, rank, bank, row to access and if the request is a row buffer hit or miss
    if (oldest_index != -1) { // scheduler might not find anything if all requests are already scheduled or all banks are busy

        uint64_t LATENCY = 0;
        if (row_buffer_hit)
            LATENCY = tCAS;
            //LATENCY = tCAS + DRC_TAG_CHECK_TIME;
        else 
            LATENCY = tRP + tRCD + tCAS;
            //LATENCY = tRP + tRCD + tCAS + DRC_TAG_CHECK_TIME;

        uint64_t op_addr = queue->entry[oldest_index].address;
        uint32_t op_cpu = queue->entry[oldest_index].cpu,
                 op_channel = drc_get_channel(op_addr), 
                 op_rank = drc_get_rank(op_addr), 
                 op_bank = drc_get_bank(op_addr), 
                 op_row = drc_get_row(op_addr);
#ifdef DEBUG_PRINT
        uint32_t op_column = drc_get_column(op_addr);
#endif
        // this bank is now busy
        bank_request[op_channel][op_rank][op_bank].working = 1;
        bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu] + LATENCY;

        bank_request[op_channel][op_rank][op_bank].request_index = oldest_index;
        bank_request[op_channel][op_rank][op_bank].row_buffer_hit = row_buffer_hit;
        if (queue->is_WQ) {
            bank_request[op_channel][op_rank][op_bank].is_write = 1;
            bank_request[op_channel][op_rank][op_bank].is_read = 0;
            scheduled_writes++;
        } else {
            bank_request[op_channel][op_rank][op_bank].is_write = 0;
            bank_request[op_channel][op_rank][op_bank].is_read = 1;
            scheduled_reads++;
        }

        // update open row
        bank_request[op_channel][op_rank][op_bank].open_row = op_row;
        queue->entry[oldest_index].scheduled = 1;
        queue->entry[oldest_index].event_cycle = current_core_cycle[op_cpu] + LATENCY;

        DP (if (warmup_complete[op_cpu]) {
        cout << "[" << queue->NAME << "] " <<  __func__ << " instr_id: " << queue->entry[oldest_index].instr_id;
        cout << " row buffer: " << (row_buffer_hit ? (int)bank_request[op_channel][op_rank][op_bank].open_row : -1) << hex;
        cout << " address: " << queue->entry[oldest_index].address << " full_addr: " << queue->entry[oldest_index].full_addr << dec;
        cout << " index: " << oldest_index << " occupancy: " << queue->occupancy;
        cout << " ch: " << op_channel << " rank: " << op_rank << " bank: " << op_bank; // wrong from here
        cout << " row: " << op_row << " current: " << current_core_cycle[op_cpu] << " event: " << queue->entry[oldest_index].event_cycle << endl; });

        update_schedule_cycle(queue);
        update_process_cycle(queue);
    }
}

// Assembly:
subq $0x78, %rsp
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0x4f(%rsp)
movl $0xffffffff, 0x48(%rsp) # imm = 0xFFFFFFFF
movq $-0x1, 0x40(%rsp)
movl $0x0, 0x3c(%rsp)
movl 0x3c(%rsp), %eax
movq 0x68(%rsp), %rcx
cmpl 0x20(%rcx), %eax
jae 0x1ee27
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x60(%rsp)
cmpq $0x0, 0x60(%rsp)
jne 0x1eccb
jmp 0x1ee17
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
cmpb $0x0, 0x2(%rax)
je 0x1ecf0
jmp 0x1ee17
movq 0x8(%rsp), %rdi
movq 0x60(%rsp), %rsi
callq 0x1e630
movq 0x8(%rsp), %rdi
movl %eax, 0x5c(%rsp)
movq 0x60(%rsp), %rsi
callq 0x1e660
movq 0x8(%rsp), %rdi
movl %eax, 0x58(%rsp)
movq 0x60(%rsp), %rsi
callq 0x1e690
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x54(%rsp)
addq $0x409470, %rax         # imm = 0x409470
movl 0x5c(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x58(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x54(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
cmpb $0x0, 0x1c(%rax)
je 0x1ed68
jmp 0x1ee17
movq 0x8(%rsp), %rdi
movq 0x60(%rsp), %rsi
callq 0x1e6c0
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x50(%rsp)
addq $0x409470, %rax         # imm = 0x409470
movl 0x5c(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x58(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x54(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
movl 0x18(%rax), %eax
cmpl 0x50(%rsp), %eax
je 0x1edba
jmp 0x1ee17
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
cmpq 0x40(%rsp), %rax
jae 0x1ee15
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
movq %rax, 0x40(%rsp)
movl 0x3c(%rsp), %eax
movl %eax, 0x48(%rsp)
movb $0x1, 0x4f(%rsp)
jmp 0x1ee17
movl 0x3c(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x3c(%rsp)
jmp 0x1ec86
cmpl $-0x1, 0x48(%rsp)
jne 0x1ef8c
movq $-0x1, 0x40(%rsp)
movl $0x0, 0x38(%rsp)
movl 0x38(%rsp), %eax
movq 0x68(%rsp), %rcx
cmpl 0x20(%rcx), %eax
jae 0x1ef8a
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x60(%rsp)
cmpq $0x0, 0x60(%rsp)
jne 0x1ee88
jmp 0x1ef7a
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
cmpb $0x0, 0x2(%rax)
je 0x1eead
jmp 0x1ef7a
movq 0x8(%rsp), %rdi
movq 0x60(%rsp), %rsi
callq 0x1e630
movq 0x8(%rsp), %rdi
movl %eax, 0x5c(%rsp)
movq 0x60(%rsp), %rsi
callq 0x1e660
movq 0x8(%rsp), %rdi
movl %eax, 0x58(%rsp)
movq 0x60(%rsp), %rsi
callq 0x1e690
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x54(%rsp)
addq $0x409470, %rax         # imm = 0x409470
movl 0x5c(%rsp), %ecx
imulq $0x500, %rcx, %rcx      # imm = 0x500
addq %rcx, %rax
movl 0x58(%rsp), %ecx
imulq $0x280, %rcx, %rcx      # imm = 0x280
addq %rcx, %rax
movl 0x54(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
cmpb $0x0, 0x1c(%rax)
je 0x1ef22
jmp 0x1ef7a
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
cmpq 0x40(%rsp), %rax
jae 0x1ef78
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
movq %rax, 0x40(%rsp)
movl 0x38(%rsp), %eax
movl %eax, 0x48(%rsp)
jmp 0x1ef7a
movl 0x38(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x38(%rsp)
jmp 0x1ee43
jmp 0x1ef8c
cmpl $-0x1, 0x48(%rsp)
je 0x1f31c
movq $0x0, 0x30(%rsp)
cmpb $0x0, 0x4f(%rsp)
je 0x1efb7
leaq 0xc26e(%rip), %rax      # 0x2b21c
movl (%rax), %eax
movq %rax, 0x30(%rsp)
jmp 0x1efd9
leaq 0xc256(%rip), %rax      # 0x2b214
movl (%rax), %eax
leaq 0xc251(%rip), %rcx      # 0x2b218
addl (%rcx), %eax
leaq 0xc24c(%rip), %rcx      # 0x2b21c
addl (%rcx), %eax
movl %eax, %eax
movq %rax, 0x30(%rsp)
movq 0x8(%rsp), %rdi
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x28(%rsp)
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movl 0x330(%rax), %eax
movl %eax, 0x24(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e630
movq 0x8(%rsp), %rdi
movl %eax, 0x20(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e660
movq 0x8(%rsp), %rdi
movl %eax, 0x1c(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e690
movq 0x8(%rsp), %rdi
movl %eax, 0x18(%rsp)
movq 0x28(%rsp), %rsi
callq 0x1e6c0
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x14(%rsp)
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x1, 0x1c(%rcx)
movl 0x24(%rsp), %ecx
movl %ecx, %edx
leaq 0x70e06(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
addq 0x30(%rsp), %rdx
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %esi
imulq $0x500, %rsi, %rsi      # imm = 0x500
addq %rsi, %rcx
movl 0x1c(%rsp), %esi
imulq $0x280, %rsi, %rsi      # imm = 0x280
addq %rsi, %rcx
movl 0x18(%rsp), %esi
imulq $0x28, %rsi, %rsi
addq %rsi, %rcx
movq %rdx, (%rcx)
movl 0x48(%rsp), %edx
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %esi
imulq $0x500, %rsi, %rsi      # imm = 0x500
addq %rsi, %rcx
movl 0x1c(%rsp), %esi
imulq $0x280, %rsi, %rsi      # imm = 0x280
addq %rsi, %rcx
movl 0x18(%rsp), %esi
imulq $0x28, %rsi, %rsi
addq %rsi, %rcx
movl %edx, 0x24(%rcx)
movb 0x4f(%rsp), %cl
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rax
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rax
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rax
movb %cl, 0x1e(%rax)
movq 0x68(%rsp), %rax
cmpb $0x0, 0x25(%rax)
je 0x1f1f2
movq 0x8(%rsp), %rax
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x1, 0x20(%rcx)
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x0, 0x21(%rcx)
movl 0x409468(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x409468(%rax)
jmp 0x1f270
movq 0x8(%rsp), %rax
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x0, 0x20(%rcx)
movq %rax, %rcx
addq $0x409470, %rcx         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x1, 0x21(%rcx)
movl 0x409464(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x409464(%rax)
movq 0x8(%rsp), %rdi
movl 0x14(%rsp), %ecx
movq %rdi, %rax
addq $0x409470, %rax         # imm = 0x409470
movl 0x20(%rsp), %edx
imulq $0x500, %rdx, %rdx      # imm = 0x500
addq %rdx, %rax
movl 0x1c(%rsp), %edx
imulq $0x280, %rdx, %rdx      # imm = 0x280
addq %rdx, %rax
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rax
movl %ecx, 0x18(%rax)
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movb $0x1, 0x2(%rax)
movl 0x24(%rsp), %eax
movl %eax, %ecx
leaq 0x70be8(%rip), %rax     # 0x8fec0
movq (%rax,%rcx,8), %rcx
addq 0x30(%rsp), %rcx
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movq %rcx, 0x378(%rax)
movq 0x68(%rsp), %rsi
callq 0x1e6f0
movq 0x8(%rsp), %rdi
movq 0x68(%rsp), %rsi
callq 0x1e810
addq $0x78, %rsp
retq
nopw %cs:(%rax,%rax)