// File: CMU-SAFARI[P]MQSim/src/ssd/TSU_OutofOrder.cpp
// Function: SSD_Components::TSU_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip*)
bool TSU_OutOfOrder::service_write_transaction(NVM::FlashMemory::Flash_Chip *chip)
{
	Flash_Transaction_Queue *sourceQueue1 = NULL, *sourceQueue2 = NULL;

	//If flash transactions related to GC are prioritzed (non-preemptive execution mode of GC), then GC queues are checked first
	if (ftl->GC_and_WL_Unit->GC_is_in_urgent_mode(chip))
	{
		if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
			if (UserWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
			{
				sourceQueue2 = &UserWriteTRQueue[chip->ChannelID][chip->ChipID];
			}
		}
		else if (GCEraseTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			return false;
		}
		else if (UserWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &UserWriteTRQueue[chip->ChannelID][chip->ChipID];
		}
		else
		{
			return false;
		}
	}
	else
	{
		//If GC is currently executed in the preemptive mode, then user IO transaction queues are checked first
		if (UserWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &UserWriteTRQueue[chip->ChannelID][chip->ChipID];
			if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
			{
				sourceQueue2 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
			}
		}
		else if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
		{
			sourceQueue1 = &GCWriteTRQueue[chip->ChannelID][chip->ChipID];
		}
		else
		{
			return false;
		}
	}

	bool suspensionRequired = false;
	ChipStatus cs = _NVMController->GetChipStatus(chip);
	switch (cs)
	{
	case ChipStatus::IDLE:
		break;
	case ChipStatus::ERASING:
		if (!eraseSuspensionEnabled || _NVMController->HasSuspendedCommand(chip))
			return false;
		if (_NVMController->Expected_finish_time(chip) - Simulator->Time() < eraseReasonableSuspensionTimeForWrite)
			return false;
		suspensionRequired = true;
	default:
		return false;
	}

	issue_command_to_chip(sourceQueue1, sourceQueue2, Transaction_Type::WRITE, suspensionRequired);

	return true;
}

// Assembly:
subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x10(%rsp)
movq $0x0, 0x28(%rsp)
movq $0x0, 0x20(%rsp)
movq 0x30(%rax), %rax
movq 0x48(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
callq *0x20(%rax)
testb $0x1, %al
jne 0x9f056
jmp 0x9f1ea
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f12a
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rcx
movq 0x30(%rsp), %rdx
movl 0x2c(%rdx), %edx
movq (%rcx,%rdx,8), %rcx
movq 0x30(%rsp), %rdx
movl 0x30(%rdx), %edx
imulq $0x108, %rdx, %rdx      # imm = 0x108
addq %rdx, %rcx
movq %rcx, 0x28(%rsp)
movq 0xb8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f125
movq 0x10(%rsp), %rax
movq 0xb8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x20(%rsp)
jmp 0x9f1e5
movq 0x10(%rsp), %rax
movq 0xd0(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f16d
movb $0x0, 0x47(%rsp)
jmp 0x9f40f
movq 0x10(%rsp), %rax
movq 0xb8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f1d7
movq 0x10(%rsp), %rax
movq 0xb8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x28(%rsp)
jmp 0x9f1e1
movb $0x0, 0x47(%rsp)
jmp 0x9f40f
jmp 0x9f1e3
jmp 0x9f1e5
jmp 0x9f333
movq 0x10(%rsp), %rax
movq 0xb8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f2bb
movq 0x10(%rsp), %rax
movq 0xb8(%rax), %rcx
movq 0x30(%rsp), %rdx
movl 0x2c(%rdx), %edx
movq (%rcx,%rdx,8), %rcx
movq 0x30(%rsp), %rdx
movl 0x30(%rdx), %edx
imulq $0x108, %rdx, %rdx      # imm = 0x108
addq %rdx, %rcx
movq %rcx, 0x28(%rsp)
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f2b9
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x20(%rsp)
jmp 0x9f331
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rdi
movq 0x30(%rsp), %rax
movl 0x30(%rax), %eax
imulq $0x108, %rax, %rax      # imm = 0x108
addq %rax, %rdi
addq $0x8, %rdi
callq 0x91c80
cmpq $0x0, %rax
jbe 0x9f325
movq 0x10(%rsp), %rax
movq 0xc8(%rax), %rax
movq 0x30(%rsp), %rcx
movl 0x2c(%rcx), %ecx
movq (%rax,%rcx,8), %rax
movq 0x30(%rsp), %rcx
movl 0x30(%rcx), %ecx
imulq $0x108, %rcx, %rcx      # imm = 0x108
addq %rcx, %rax
movq %rax, 0x28(%rsp)
jmp 0x9f32f
movb $0x0, 0x47(%rsp)
jmp 0x9f40f
jmp 0x9f331
jmp 0x9f333
movq 0x10(%rsp), %rax
movb $0x0, 0x1f(%rsp)
movq 0x38(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
movq 0x48(%rax), %rax
callq *%rax
movl %eax, 0x18(%rsp)
movl 0x18(%rsp), %eax
movl %eax, 0xc(%rsp)
testl %eax, %eax
je 0x9f36c
jmp 0x9f361
movl 0xc(%rsp), %eax
subl $0x6, %eax
je 0x9f36e
jmp 0x9f3e0
jmp 0x9f3e7
movq 0x10(%rsp), %rax
testb $0x1, 0x54(%rax)
je 0x9f393
movq 0x10(%rsp), %rax
movq 0x38(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
callq *0x40(%rax)
testb $0x1, %al
jne 0x9f393
jmp 0x9f39a
movb $0x0, 0x47(%rsp)
jmp 0x9f40f
movq 0x10(%rsp), %rax
movq 0x38(%rax), %rdi
movq 0x30(%rsp), %rsi
movq (%rdi), %rax
callq *0x50(%rax)
movq %rax, (%rsp)
callq 0x46500
movq %rax, %rdi
callq 0x46c50
movq 0x10(%rsp), %rcx
movq %rax, %rdx
movq (%rsp), %rax
subq %rdx, %rax
cmpq 0x68(%rcx), %rax
jae 0x9f3db
movb $0x0, 0x47(%rsp)
jmp 0x9f40f
movb $0x1, 0x1f(%rsp)
movb $0x0, 0x47(%rsp)
jmp 0x9f40f
movq 0x10(%rsp), %rdi
movq 0x28(%rsp), %rsi
movq 0x20(%rsp), %rdx
movb 0x1f(%rsp), %al
movl $0x1, %ecx
andb $0x1, %al
movzbl %al, %r8d
callq 0x9b2a0
movb $0x1, 0x47(%rsp)
movb 0x47(%rsp), %al
andb $0x1, %al
addq $0x48, %rsp
retq
nopw (%rax,%rax)