LLM4Binary/decompile-bench-makefile huggingface dataset:
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::deallocate(CacheEntry*)
void 
HybridCache::deallocate(CacheEntry* destination_entry)
{
	uint64_t addr = destination_entry->address;
	updateStatsDeallocate(destination_entry);

	map<uint64_t,HybridLocation>::iterator it = m_tag_index.find(addr);	
	if(it != m_tag_index.end()){
		m_tag_index.erase(it);	
	}	

	destination_entry->initEntry();
	
	
}

// Assembly:
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsi), %r15
movq 0x8(%rsi), %r12
callq 0x19ab2
movq 0x48(%r14), %rax
testq %rax, %rax
je 0x1b240
leaq 0x38(%r14), %rdi
addq $0x40, %r14
movq %r14, %rsi
xorl %ecx, %ecx
cmpq %r12, 0x20(%rax)
setb %cl
cmovaeq %rax, %rsi
movq 0x10(%rax,%rcx,8), %rax
testq %rax, %rax
jne 0x1b219
cmpq %r14, %rsi
je 0x1b240
cmpq 0x20(%rsi), %r12
jb 0x1b240
callq 0x1d86c
xorl %eax, %eax
movw %ax, (%rbx)
movw %ax, 0x14b(%rbx)
movl $0x0, 0x128(%rbx)
movq %rax, 0x130(%rbx)
movq %rax, 0x10(%r15)
xorps %xmm0, %xmm0
movups %xmm0, (%r15)
movq %rax, 0x38(%rbx)
movups %xmm0, 0x28(%rbx)
movq %rax, 0x118(%rbx)
movq %rax, 0x11d(%rbx)
movl $0x3, 0x168(%rbx)
movq %rax, 0x20(%rbx)
movups %xmm0, 0x138(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::allocate(unsigned long, int, int, bool, unsigned long, bool)
void 
HybridCache::allocate(uint64_t address , int id_set , int id_assoc, bool inNVM, uint64_t pc, bool isPrefetch)
{

	uint64_t block_addr = bitRemove(address , 0 , m_start_index+1);
	
	if(inNVM){
	 	assert(!m_tableNVM[id_set][id_assoc]->isValid);

		m_tableNVM[id_set][id_assoc]->isValid = true;	
		m_tableNVM[id_set][id_assoc]->address = block_addr;
		m_tableNVM[id_set][id_assoc]->policyInfo = 0;
		m_tableNVM[id_set][id_assoc]->m_pc = pc;
		m_tableNVM[id_set][id_assoc]->isPrefetch = isPrefetch;
	}
	else
	{
	 	assert(!m_tableSRAM[id_set][id_assoc]->isValid);

		m_tableSRAM[id_set][id_assoc]->isValid = true;	
		m_tableSRAM[id_set][id_assoc]->address = block_addr;
		m_tableSRAM[id_set][id_assoc]->policyInfo = 0;		
		m_tableSRAM[id_set][id_assoc]->m_pc = pc;		
		m_tableSRAM[id_set][id_assoc]->isPrefetch = isPrefetch;
	}
	
	if(!m_isWarmup)
		stats_nbFetchedLines++;	
		
	HybridLocation loc(id_assoc, inNVM);
	m_tag_index.insert(pair<uint64_t , HybridLocation>(block_addr , loc));
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %r9, %r15
movl %r8d, %r14d
movl %ecx, %ebp
movl %edx, %r12d
movq %rdi, %rbx
movl 0x94(%rdi), %edx
incl %edx
movq %rsi, %rdi
xorl %esi, %esi
callq 0x2e38e
movslq %r12d, %rdx
movslq %ebp, %rcx
testl %r14d, %r14d
je 0x1b30b
movq 0x8(%rbx), %rsi
leaq (%rdx,%rdx,2), %rdx
movq (%rsi,%rdx,8), %rdx
movq (%rdx,%rcx,8), %rcx
cmpb $0x1, (%rcx)
jne 0x1b320
leaq 0x1a748(%rip), %rdi     # 0x35a3b
leaq 0x1a487(%rip), %rsi     # 0x35781
leaq 0x1a761(%rip), %rcx     # 0x35a62
movl $0x23d, %edx            # imm = 0x23D
callq 0x51d0
movq 0x20(%rbx), %rsi
leaq (%rdx,%rdx,2), %rdx
movq (%rsi,%rdx,8), %rdx
movq (%rdx,%rcx,8), %rcx
cmpb $0x1, (%rcx)
je 0x1b37c
movb 0x40(%rsp), %dl
movb $0x1, (%rcx)
movq %rax, 0x8(%rcx)
movl $0x0, 0x38(%rcx)
movq %r15, 0x10(%rcx)
movb %dl, 0x14b(%rcx)
cmpb $0x0, 0x91(%rbx)
jne 0x1b34c
incq 0x1a0(%rbx)
addq $0x38, %rbx
movq %rsp, %rsi
movq %rax, (%rsi)
movzbl %r14b, %eax
shlq $0x20, %rax
movl %ebp, %ecx
orq %rax, %rcx
movq %rcx, 0x8(%rsi)
movq %rbx, %rdi
callq 0x1db40
addq $0x10, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
leaq 0x1a724(%rip), %rdi     # 0x35aa7
leaq 0x1a3f7(%rip), %rsi     # 0x35781
leaq 0x1a6d1(%rip), %rcx     # 0x35a62
movl $0x247, %edx            # imm = 0x247
callq 0x51d0
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::deallocate(unsigned long)
void
HybridCache::deallocate(uint64_t block_addr)
{
	entete_debug();
	DPRINTF(DebugCache , "DEALLOCATE %#lx\n", block_addr);
	map<uint64_t,HybridLocation>::iterator it = m_tag_index.find(block_addr);	
	
	if(it != m_tag_index.end()){

		int id_set = blockAddressToCacheSet(block_addr);

		HybridLocation loc = it->second;
		CacheEntry* current = NULL; 

		if(loc.m_inNVM)
			current = m_tableNVM[id_set][loc.m_way]; 		
		else
			current = m_tableSRAM[id_set][loc.m_way]; 		

		updateStatsDeallocate(current);
		current->initEntry();
				
		m_tag_index.erase(it);	

	}
}

// Assembly:
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rsi, %r14
movq %rdi, %rbx
callq 0x19e2a
leaq 0x10(%rsp), %r12
movq %r12, -0x10(%r12)
leaq 0x1a438(%rip), %rsi     # 0x3589d
leaq 0x1a43b(%rip), %rdx     # 0x358a7
movq %rsp, %r15
movq %r15, %rdi
callq 0xcc6c
leaq 0x2aad2(%rip), %r13     # 0x45f50
leaq 0x8(%r13), %rdi
movq %r15, %rsi
callq 0x1800c
movq %rax, %r15
movq (%rsp), %rdi
cmpq %r12, %rdi
je 0x1b49b
callq 0x52b0
addq $0x10, %r13
cmpq %r13, %r15
je 0x1b4b5
leaq 0x1a57f(%rip), %rdi     # 0x35a2a
movq %r14, %rsi
xorl %eax, %eax
callq 0x5050
movq 0x48(%rbx), %rax
testq %rax, %rax
je 0x1b598
leaq 0x38(%rbx), %r15
leaq 0x40(%rbx), %rcx
movq %rcx, %r12
xorl %edx, %edx
cmpq %r14, 0x20(%rax)
setb %dl
cmovaeq %rax, %r12
movq 0x10(%rax,%rdx,8), %rax
testq %rax, %rax
jne 0x1b4cd
cmpq %rcx, %r12
je 0x1b598
cmpq %r14, 0x20(%r12)
ja 0x1b598
movq %rbx, %rdi
movq %r14, %rsi
callq 0x1b5c0
movslq 0x28(%r12), %rcx
cltq
leaq 0x20(%rbx), %rdx
leaq 0x8(%rbx), %rsi
testb $0x1, 0x2c(%r12)
cmovneq %rsi, %rdx
movq (%rdx), %rdx
leaq (%rax,%rax,2), %rax
movq (%rdx,%rax,8), %rax
movq (%rax,%rcx,8), %r14
movq %rbx, %rdi
movq %r14, %rsi
callq 0x19ab2
xorl %eax, %eax
movw %ax, (%r14)
movw %ax, 0x14b(%r14)
movl $0x0, 0x128(%r14)
movq %rax, 0x130(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x8(%r14)
movups %xmm0, 0x18(%r14)
movups %xmm0, 0x28(%r14)
movq %rax, 0x38(%r14)
movq %rax, 0x118(%r14)
movq %rax, 0x11d(%r14)
movl $0x3, 0x168(%r14)
movups %xmm0, 0x138(%r14)
movq %r15, %rdi
movq %r12, %rsi
callq 0x1d86c
addq $0x20, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r12, %rdi
je 0x1b5b7
callq 0x52b0
movq %rbx, %rdi
callq 0x55a0
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/HybridCache.cc
// Function: HybridCache::blockAddressToCacheSet(unsigned long)
int 
HybridCache::blockAddressToCacheSet(uint64_t block_addr) 
{
	uint64_t a =block_addr;
	a = bitRemove(a , m_end_index,64);
	
	a = a >> (m_start_index+1);
	assert(a < (unsigned int)m_nb_set);
	
	return (int)a;
}

// Assembly:
pushq %rbx
movq %rsi, %rax
movq %rdi, %rbx
movl 0x98(%rdi), %esi
movq %rax, %rdi
movl $0x40, %edx
callq 0x2e38e
movb 0x94(%rbx), %cl
incb %cl
shrq %cl, %rax
movl 0xac(%rbx), %ecx
cmpq %rcx, %rax
jae 0x1b5f2
popq %rbx
retq
leaq 0x19b26(%rip), %rdi     # 0x3511f
leaq 0x1a181(%rip), %rsi     # 0x35781
leaq 0x1a607(%rip), %rcx     # 0x35c0e
movl $0x2e7, %edx            # imm = 0x2E7
callq 0x51d0
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Cache.hh
// Function: CacheEntry::~CacheEntry()
CacheEntry() { 
			isNVM = false;
			isLearning_policy = false;
			isLearning_weight = false;
			isLearning = false;
			initEntry();
		}

// Assembly:
pushq %rbx
movq %rdi, %rbx
movq 0x150(%rdi), %rdi
testq %rdi, %rdi
je 0x1d0d7
callq 0x52b0
movq 0x100(%rbx), %rdi
testq %rdi, %rdi
je 0x1d0e8
callq 0x52b0
movq 0xe8(%rbx), %rdi
testq %rdi, %rdi
je 0x1d0f9
callq 0x52b0
movq 0xd0(%rbx), %rdi
testq %rdi, %rdi
je 0x1d10a
callq 0x52b0
leaq 0xa8(%rbx), %rdi
callq 0x12132
movq 0x90(%rbx), %rdi
testq %rdi, %rdi
je 0x1d127
callq 0x52b0
movq 0x78(%rbx), %rdi
testq %rdi, %rdi
je 0x1d135
callq 0x52b0
movq 0x60(%rbx), %rdi
testq %rdi, %rdi
je 0x1d143
callq 0x52b0
movq 0x48(%rbx), %rdi
testq %rdi, %rdi
je 0x1d152
popq %rbx
jmp 0x52b0
popq %rbx
retq
movq %rax, %rdi
callq 0xc99c
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::allocateInNVM(unsigned long, Access)
allocDecision
InstructionPredictor::allocateInNVM(uint64_t set, Access element)
{
	//DPRINTF("InstructionPredictor::allocateInNVM\n");
	
	if(element.isInstFetch())
		return ALLOCATE_IN_NVM;

	if(pc_counters.count(element.m_pc) == 0){
		//New PC to track		
		pc_counters.insert(pair<uint64_t,int>(element.m_pc, 1));	

		if(!m_isWarmup)
			stats_PCwrites.insert(pair<uint64_t,pair<int,int> >(element.m_pc, pair<int,int>(0,0) ));
		
		map<uint64_t, pair<int,int> > my_tab = map<uint64_t, pair<int,int> >();
	}

	if(pc_counters[element.m_pc] < 2)
		return ALLOCATE_IN_NVM; 
	else
		return ALLOCATE_IN_SRAM;

}

// Assembly:
pushq %r15
pushq %r14
pushq %rbx
subq $0x30, %rsp
movl $0x1, %eax
cmpl $0x2, 0x6c(%rsp)
jb 0x1de32
movq %rdi, %r15
leaq 0x50(%rsp), %rbx
leaq 0x280(%rdi), %r14
addq $0x10, %rbx
movq %r14, %rdi
movq %rbx, %rsi
callq 0x1e4ca
testq %rax, %rax
jne 0x1de1c
movq (%rbx), %rax
movq %rsp, %rsi
movq %rax, (%rsi)
movl $0x1, 0x8(%rsi)
movq %r14, %rdi
callq 0xd8a2
cmpb $0x0, 0x81(%r15)
jne 0x1ddf6
addq $0x2b0, %r15            # imm = 0x2B0
movq (%rbx), %rax
movq %rsp, %rsi
movq %rax, (%rsi)
movq $0x0, 0x8(%rsi)
movq %r15, %rdi
callq 0x1e620
leaq 0x8(%rsp), %rax
xorps %xmm0, %xmm0
movaps %xmm0, -0x8(%rax)
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
movq %rax, 0x10(%rax)
movq %rax, 0x18(%rax)
movq %rcx, 0x20(%rax)
movq %rsp, %rdi
callq 0x1e5d6
movq %r14, %rdi
movq %rbx, %rsi
callq 0x1e514
movq %rax, %rcx
xorl %eax, %eax
cmpl $0x2, (%rcx)
setl %al
addq $0x30, %rsp
popq %rbx
popq %r14
popq %r15
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::updatePolicy(unsigned long, unsigned long, bool, Access, bool)
void
InstructionPredictor::updatePolicy(uint64_t set, uint64_t index, bool inNVM, Access element, bool isWBrequest = false)
{
	//DPRINTF("InstructionPredictor::updatePolicy\n");
	
	CacheEntry* current;

	if(inNVM){
		current = m_tableNVM[set][index];
		m_replacementPolicyNVM_ptr->updatePolicy(set, index , element);
	}		
	else{
		current = m_tableSRAM[set][index];
		m_replacementPolicySRAM_ptr->updatePolicy(set, index , element);
	}
		
	current->policyInfo = m_cpt;
	if(element.isWrite()){
		current->cost_value+= WRITE_VALUE;
	}
	else{ 
		current->cost_value += READ_VALUE;	
	} 	
	Predictor::updatePolicy(set, index, inNVM, element , isWBrequest);

	m_cpt++;
	//DPRINTF("InstructionPredictor:: End updatePolicy\n");
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r14
movl %ecx, %eax
xorb $0x1, %cl
movzbl %cl, %ecx
movq 0x8(%rdi,%rax,8), %rax
movq (%rax), %rax
leaq (%rsi,%rsi,2), %rdx
movq (%rax,%rdx,8), %rax
movq (%rax,%r15,8), %r13
movq 0x60(%rdi,%rcx,8), %rdi
movq (%rdi), %rax
movq 0xa0(%rsp), %rcx
movq %rcx, 0x30(%rsp)
movaps 0x70(%rsp), %xmm0
movaps 0x80(%rsp), %xmm1
movaps 0x90(%rsp), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq %r15, %rdx
callq *0x10(%rax)
movl 0x270(%r14), %eax
movl %eax, 0x38(%r13)
movl 0x8c(%rsp), %edx
xorl %eax, %eax
cmpl $0x3, %edx
sete %cl
cmpl $0x6, %edx
je 0x1dee1
movb %cl, %al
leaq 0x17f2e(%rip), %rcx     # 0x35e08
movsd (%rcx,%rax,8), %xmm0
jmp 0x1dee9
movsd 0x17f2f(%rip), %xmm0    # 0x35e18
addsd 0x130(%r13), %xmm0
movsd %xmm0, 0x130(%r13)
movq 0xa0(%rsp), %rax
movq %rax, 0x30(%rsp)
movaps 0x70(%rsp), %xmm0
movaps 0x80(%rsp), %xmm1
movaps 0x90(%rsp), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq %r14, %rdi
movq %r12, %rsi
movq %r15, %rdx
movl %ebp, %ecx
movl %ebx, %r8d
callq 0x272da
incq 0x270(%r14)
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::insertionPolicy(unsigned long, unsigned long, bool, Access)
void InstructionPredictor::insertionPolicy(uint64_t set, uint64_t index, bool inNVM, Access element)
{
	//DPRINTF("InstructionPredictor::insertionPolicy\n");
	
	CacheEntry* current;
	if(inNVM){
		current = m_tableNVM[set][index];
	}		
	else{
		current = m_tableSRAM[set][index];
	}
	
	current->policyInfo = m_cpt;

	if(element.isWrite())
		current->cost_value = WRITE_VALUE;
	else
		current->cost_value = READ_VALUE;
	
	Predictor::insertionPolicy(set , index , inNVM , element);
	m_cpt++;
}

// Assembly:
pushq %rbx
subq $0x40, %rsp
movq %rdi, %rbx
movl %ecx, %eax
movq 0x8(%rdi,%rax,8), %rax
movq (%rax), %rax
leaq (%rsi,%rsi,2), %rdi
movq (%rax,%rdi,8), %rax
movq (%rax,%rdx,8), %rax
movl 0x270(%rbx), %edi
movl %edi, 0x38(%rax)
movl 0x6c(%rsp), %r9d
xorl %edi, %edi
cmpl $0x3, %r9d
sete %r8b
cmpl $0x6, %r9d
je 0x1dfa2
movb %r8b, %dil
leaq 0x17e6e(%rip), %r8      # 0x35e08
movsd (%r8,%rdi,8), %xmm0
jmp 0x1dfaa
movsd 0x17e6e(%rip), %xmm0    # 0x35e18
movsd %xmm0, 0x130(%rax)
movq 0x80(%rsp), %rax
movq %rax, 0x30(%rsp)
movaps 0x50(%rsp), %xmm0
movaps 0x60(%rsp), %xmm1
movaps 0x70(%rsp), %xmm2
movups %xmm2, 0x20(%rsp)
movups %xmm1, 0x10(%rsp)
movups %xmm0, (%rsp)
movq %rbx, %rdi
callq 0x26664
incq 0x270(%rbx)
addq $0x40, %rsp
popq %rbx
retq
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::printStats(std::ostream&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
void 
InstructionPredictor::printStats(std::ostream& out, string entete)
{	
	int totalWrite = 0;
	for(auto p : stats_PCwrites)
	{
		pair<int,int> current = p.second;
		totalWrite += current.first;
	}
	
	out << entete << ":InstructionPredictor Parameters:" << endl;
	out << entete << ":Total Write\t" << totalWrite << endl;
	
	/*
	ofstream output_file;
	output_file.open(OUTPUT_PREDICTOR_FILE , std::ofstream::app);
	if(totalWrite > 0){
		output_file << "Write Intensity Per Instruction "<< endl;
		for(auto p : stats_PCwrites)
		{
			pair<int,int> current = p.second;
			output_file << p.first << "\t" << current.first << "\t" << current.second << endl;
		}
	}
	output_file.close();
	*/
	Predictor::printStats(out,entete);
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq 0x2c8(%rdi), %rax
leaq 0x2b8(%rdi), %r12
xorl %ebp, %ebp
cmpq %r12, %rax
je 0x1e26b
addl 0x28(%rax), %ebp
movq %rax, %rdi
callq 0x5210
jmp 0x1e259
movq (%r15), %rsi
movq 0x8(%r15), %rdx
movq %rbx, %rdi
callq 0x5360
movq %rax, %r12
leaq 0x17beb(%rip), %rsi     # 0x35e6f
movl $0x21, %edx
movq %rax, %rdi
callq 0x5360
movq (%r12), %rax
movq -0x18(%rax), %rdi
addq %r12, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %r12, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movq (%r15), %rsi
movq 0x8(%r15), %rdx
movq %rbx, %rdi
callq 0x5360
movq %rax, %r12
leaq 0x17bbf(%rip), %rsi     # 0x35e91
movl $0xd, %edx
movq %rax, %rdi
callq 0x5360
movq %r12, %rdi
movl %ebp, %esi
callq 0x5580
movq %rax, %r12
movq (%rax), %rax
movq -0x18(%rax), %rdi
addq %r12, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %r12, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
leaq 0x10(%rsp), %r12
movq %r12, -0x10(%r12)
movq (%r15), %rsi
movq 0x8(%r15), %rdx
addq %rsi, %rdx
movq %rsp, %r15
movq %r15, %rdi
callq 0xcbd6
movq %r14, %rdi
movq %rbx, %rsi
movq %r15, %rdx
callq 0x27a64
movq (%rsp), %rdi
cmpq %r12, %rdi
je 0x1e34e
callq 0x52b0
addq $0x20, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r12, %rdi
je 0x1e36c
callq 0x52b0
movq %rbx, %rdi
callq 0x55a0
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/InstructionPredictor.cc
// Function: InstructionPredictor::evictPolicy(int, bool)
int
InstructionPredictor::evictPolicy(int set, bool inNVM)
{	
	//DPRINTF("InstructionPredictor::evictPolicy set %d\n" , set);
	int assoc_victim = -1;
	assert(m_replacementPolicyNVM_ptr != NULL);
	assert(m_replacementPolicySRAM_ptr != NULL);
	

	if(inNVM)
		assoc_victim = m_replacementPolicyNVM_ptr->evictPolicy(set);
	else
		assoc_victim = m_replacementPolicySRAM_ptr->evictPolicy(set);


	/* Update the status of the instruction */ 
	CacheEntry* current;
	if(inNVM)
		current = m_tableNVM[set][assoc_victim];
	else
		current = m_tableSRAM[set][assoc_victim];

	if(current->isValid){
		//DPRINTF("InstructionPredictor::evictPolicy is Valid\n");
		if( current->cost_value >= simu_parameters.cost_threshold)
		{
			pc_counters[current->m_pc]++;
			if(pc_counters[current->m_pc] == 3)
				pc_counters[current->m_pc] = 3;
		
		}
		else
		{
			pc_counters[current->m_pc]--;
			if(pc_counters[current->m_pc] < 0)
				pc_counters[current->m_pc] = 0;
		}	
	}
	
	evictRecording(set , assoc_victim , inNVM);
	
	return assoc_victim;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq 0x60(%rdi), %rax
testq %rax, %rax
je 0x1e48b
movq %rdi, %r14
movq 0x68(%rdi), %rdi
testq %rdi, %rdi
je 0x1e4aa
movl %esi, %ebx
movslq %esi, %r12
testb %dl, %dl
cmovneq %rax, %rdi
movzbl %dl, %r15d
movq (%rdi), %rax
movl %r12d, %esi
callq *0x20(%rax)
movl %eax, %ebp
movq 0x8(%r14,%r15,8), %rax
movq (%rax), %rax
leaq (%r12,%r12,2), %rcx
movslq %ebp, %rdx
movq (%rax,%rcx,8), %rax
movq (%rax,%rdx,8), %r12
cmpb $0x1, (%r12)
jne 0x1e46b
movsd 0x130(%r12), %xmm0
movsd %xmm0, 0x10(%rsp)
leaq 0x27b5e(%rip), %rax     # 0x45f50
xorps %xmm0, %xmm0
cvtsi2sdl 0xbc(%rax), %xmm0
movsd %xmm0, 0x8(%rsp)
leaq 0x280(%r14), %r13
addq $0x10, %r12
movq %r13, %rdi
movq %r12, %rsi
callq 0x1e514
movsd 0x10(%rsp), %xmm0
ucomisd 0x8(%rsp), %xmm0
movl (%rax), %ecx
jae 0x1e441
decl %ecx
movl %ecx, (%rax)
movq %r13, %rdi
movq %r12, %rsi
callq 0x1e514
cmpl $0x0, (%rax)
jns 0x1e46b
xorl %ecx, %ecx
jmp 0x1e45a
incl %ecx
movl %ecx, (%rax)
movq %r13, %rdi
movq %r12, %rsi
callq 0x1e514
movl $0x3, %ecx
cmpl $0x3, (%rax)
jne 0x1e46b
movq %r13, %rdi
movq %r12, %rsi
movl %ecx, %r12d
callq 0x1e514
movl %r12d, (%rax)
movq %r14, %rdi
movl %ebx, %esi
movl %ebp, %edx
movl %r15d, %ecx
callq 0x264ec
movl %ebp, %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x15ce3(%rip), %rdi     # 0x34175
leaq 0x17a06(%rip), %rsi     # 0x35e9f
leaq 0x17a1b(%rip), %rcx     # 0x35ebb
movl $0x90, %edx
callq 0x51d0
leaq 0x15d1d(%rip), %rdi     # 0x341ce
leaq 0x179e7(%rip), %rsi     # 0x35e9f
leaq 0x179fc(%rip), %rcx     # 0x35ebb
movl $0x91, %edx
callq 0x51d0
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::printResults(std::ostream&)
void
Level::printResults(std::ostream& out)
{
	out << "************************************************" << endl;
//	out << "Core n°" << m_IDcore << endl;
	if(m_isUnified)
		m_dcache->printResults(out);
	else
	{
//		out << "Data Cache " << endl;
		m_dcache->printResults(out);
		out << "******" << endl;
//		out << "Instruction Cache " << endl;
		m_icache->printResults(out);
	}
}

// Assembly:
pushq %rbp
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x172f2(%rip), %rsi     # 0x35f65
movl $0x30, %edx
movq %rbx, %rdi
callq 0x5360
movq (%rbx), %rax
movq -0x18(%rax), %rdi
addq %rbx, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %rbx, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movq (%r14), %rdi
movb 0x20(%r14), %bpl
movq %rbx, %rsi
callq 0x1bb2e
testb %bpl, %bpl
je 0x1ecc0
popq %rbx
popq %r14
popq %rbp
retq
leaq 0x172c8(%rip), %rsi     # 0x35f8f
movl $0x6, %edx
movq %rbx, %rdi
callq 0x5360
movq (%rbx), %rax
movq -0x18(%rax), %rdi
addq %rbx, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %rbx, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movq 0x8(%r14), %rdi
movq %rbx, %rsi
popq %rbx
popq %r14
popq %rbp
jmp 0x1bb2e
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Level.cc
// Function: Level::printConfig(std::ostream&)
void
Level::printConfig(std::ostream& out)
{
	out << "************************************************" << endl;
//	out << "Core n°" << m_IDcore << endl;
	if(m_isUnified)
		m_dcache->printConfig(out);
	else
	{
//		out << "Data Cache " << endl;
		m_dcache->printConfig(out);
		out << "******" << endl;
//		out << "Instruction Cache " << endl;
		m_icache->printConfig(out);
	}
}

// Assembly:
pushq %rbp
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x17248(%rip), %rsi     # 0x35f65
movl $0x30, %edx
movq %rbx, %rdi
callq 0x5360
movq (%rbx), %rax
movq -0x18(%rax), %rdi
addq %rbx, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %rbx, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movq (%r14), %rdi
movb 0x20(%r14), %bpl
movq %rbx, %rsi
callq 0x1c9cc
testb %bpl, %bpl
je 0x1ed6a
popq %rbx
popq %r14
popq %rbp
retq
leaq 0x1721e(%rip), %rsi     # 0x35f8f
movl $0x6, %edx
movq %rbx, %rdi
callq 0x5360
movq (%rbx), %rax
movq -0x18(%rax), %rdi
addq %rbx, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %rbx, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movq 0x8(%r14), %rdi
movq %rbx, %rsi
popq %rbx
popq %r14
popq %rbp
jmp 0x1c9cc
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: MemoryTrace::MemoryTrace(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
MemoryTrace::MemoryTrace(string trace) : m_trace(trace), m_isOpen(false)
{
	/*m_isOpen = false;

	if(!m_isOpen){
		cout << "Error -- Trace " << trace << " cannot be opened" << endl;
		exit(0);
	}*/
}

// Assembly:
pushq %rbx
movq %rdi, %rbx
leaq 0x259d1(%rip), %rax     # 0x447d0
movq %rax, (%rdi)
addq $0x8, %rdi
leaq 0x18(%rbx), %rax
movq %rax, 0x8(%rbx)
movq (%rsi), %rax
movq 0x8(%rsi), %rdx
addq %rax, %rdx
movq %rax, %rsi
callq 0xcbd6
movb $0x0, 0x28(%rbx)
popq %rbx
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: CompressedTrace::open()
bool
CompressedTrace::open()
{
	m_compressedTrace = gzopen(m_trace.c_str() , "rb8");
	if(!m_compressedTrace)
		cout << "The trace " << m_trace << " cannot be opened" << endl;
	else
		m_isOpen = true;

	return m_isOpen;
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq 0x8(%rdi), %rdi
leaq 0x16ff5(%rip), %rsi     # 0x36025
callq 0x5470
movq %rax, 0x30(%rbx)
testq %rax, %rax
je 0x1f046
movb $0x1, 0x28(%rbx)
movb $0x1, %al
jmp 0x1f0b2
movq 0x25f83(%rip), %r14     # 0x44fd0
leaq 0x16fd5(%rip), %rsi     # 0x36029
movl $0xa, %edx
movq %r14, %rdi
callq 0x5360
movq 0x8(%rbx), %rsi
movq 0x10(%rbx), %rdx
movq %r14, %rdi
callq 0x5360
movq %rax, %r14
leaq 0x16fb9(%rip), %rsi     # 0x36034
movl $0x11, %edx
movq %rax, %rdi
callq 0x5360
movq (%r14), %rax
movq -0x18(%rax), %rdi
addq %r14, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %r14, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movb 0x28(%rbx), %al
andb $0x1, %al
addq $0x8, %rsp
popq %rbx
popq %r14
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: TextTrace::open()
bool
TextTrace::open()
{
	m_textTrace.open(m_trace);
	if(!m_textTrace)
		cout << "The trace " << m_trace << " cannot be opened" << endl;
	else
		m_isOpen = true;


	return m_isOpen;
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
addq $0x30, %rdi
leaq 0x8(%rbx), %rsi
movl $0x8, %edx
callq 0x5290
movq 0x30(%rbx), %rax
movq -0x18(%rax), %rax
testb $0x5, 0x50(%rbx,%rax)
je 0x1f50e
movq 0x25b29(%rip), %r14     # 0x44fd0
leaq 0x16b7b(%rip), %rsi     # 0x36029
movl $0xa, %edx
movq %r14, %rdi
callq 0x5360
movq 0x8(%rbx), %rsi
movq 0x10(%rbx), %rdx
movq %r14, %rdi
callq 0x5360
movq %rax, %r14
leaq 0x16b5f(%rip), %rsi     # 0x36034
movl $0x11, %edx
movq %rax, %rdi
callq 0x5360
movq (%r14), %rax
movq -0x18(%rax), %rdi
addq %r14, %rdi
movl $0xa, %esi
callq 0x52c0
movsbl %al, %esi
movq %r14, %rdi
callq 0x5030
movq %rax, %rdi
callq 0x5200
movb 0x28(%rbx), %al
jmp 0x1f514
movb $0x1, 0x28(%rbx)
movb $0x1, %al
andb $0x1, %al
addq $0x8, %rsp
popq %rbx
popq %r14
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/MemoryTrace.cc
// Function: initTrace(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>)
MemoryTrace* initTrace(std::string trace_name)
{
	std::vector<std::string> split_line;
	std::string ext = split(trace_name , '.').back();	
	if(ext.size() == 3 && ext == "txt")
		return new TextTrace(trace_name);
	else
		return new CompressedTrace(trace_name);		

}

// Assembly:
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rdi, %r14
xorps %xmm0, %xmm0
movaps %xmm0, 0x20(%rsp)
movq $0x0, 0x30(%rsp)
leaq 0xa8(%rsp), %rbx
movq %rbx, -0x10(%rbx)
movq (%rdi), %rsi
movq 0x8(%rdi), %rdx
addq %rsi, %rdx
leaq 0x98(%rsp), %rdi
callq 0xcbd6
leaq 0x40(%rsp), %rdi
leaq 0x98(%rsp), %rsi
movl $0x2e, %edx
callq 0x2e230
movq 0x48(%rsp), %rax
leaq 0x10(%rsp), %r15
movq %r15, -0x10(%r15)
movq -0x20(%rax), %rsi
movq -0x18(%rax), %rdx
addq %rsi, %rdx
movq %rsp, %rdi
callq 0xcbd6
leaq 0x40(%rsp), %rdi
callq 0xc7c2
movq 0x98(%rsp), %rdi
cmpq %rbx, %rdi
je 0x1f5c0
callq 0x52b0
cmpq $0x3, 0x8(%rsp)
jne 0x1f5db
leaq 0x15114(%rip), %rsi     # 0x346e3
movq %rsp, %rdi
callq 0x50f0
testl %eax, %eax
je 0x1f64c
movl $0x38, %edi
callq 0x52f0
movq %rax, %rbx
leaq 0x68(%rsp), %r12
movq %r12, -0x10(%r12)
movq (%r14), %rsi
movq 0x8(%r14), %rdx
addq %rsi, %rdx
leaq 0x58(%rsp), %rdi
callq 0xcbd6
leaq 0x58(%rsp), %rsi
movq %rbx, %rdi
callq 0x1f7d0
movq 0x58(%rsp), %rdi
cmpq %r12, %rdi
je 0x1f622
callq 0x52b0
movq (%rsp), %rdi
cmpq %r15, %rdi
je 0x1f630
callq 0x52b0
leaq 0x20(%rsp), %rdi
callq 0xc7c2
movq %rbx, %rax
addq $0xb8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
movl $0x238, %edi            # imm = 0x238
callq 0x52f0
movq %rax, %rbx
leaq 0x88(%rsp), %r12
movq %r12, -0x10(%r12)
movq (%r14), %rsi
movq 0x8(%r14), %rdx
addq %rsi, %rdx
leaq 0x78(%rsp), %rdi
callq 0xcbd6
leaq 0x78(%rsp), %rsi
movq %rbx, %rdi
callq 0x1f704
movq 0x78(%rsp), %rdi
jmp 0x1f618
movq %rax, %r14
movq 0x78(%rsp), %rdi
jmp 0x1f6a2
jmp 0x1f6ae
movq %rax, %r14
movq 0x58(%rsp), %rdi
cmpq %r12, %rdi
je 0x1f6b1
callq 0x52b0
jmp 0x1f6b1
movq %rax, %r14
movq %rbx, %rdi
callq 0x52b0
jmp 0x1f6be
movq %rax, %r14
movq (%rsp), %rdi
cmpq %r15, %rdi
jne 0x1f6e8
jmp 0x1f6f2
movq %rax, %r14
leaq 0x40(%rsp), %rdi
callq 0xc7c2
jmp 0x1f6db
movq %rax, %r14
movq 0x98(%rsp), %rdi
cmpq %rbx, %rdi
je 0x1f6f2
callq 0x52b0
jmp 0x1f6f2
movq %rax, %r14
leaq 0x20(%rsp), %rdi
callq 0xc7c2
movq %r14, %rdi
callq 0x55a0
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::allocateInNVM(unsigned long, Access)
allocDecision
PHCPredictor::allocateInNVM(uint64_t set, Access element)
{
//	if(element.isInstFetch())
//		return ALLOCATE_IN_NVM;
	
	update_globalPChistory(element.m_pc);
	stats_nbMiss++;
	miss_counter++;
	if(miss_counter > 255)
		miss_counter = 255;
	
	// All the set is a learning/sampled set independantly of its way or SRAM/NVM alloc
	//bool isLearning = m_tableSRAM[set][0]->isLearning; 

	int sum_pred = 0;
	for(unsigned i = 0 ; i < m_features.size() ; i++)
	{
		int hash = m_features_hash[i](element.block_addr , element.m_pc);
		sum_pred += m_features[i]->getAllocationPrediction(hash, true);
	}
	if( abs(sum_pred) < simu_parameters.perceptron_allocation_threshold )
	{
		stats_prediction_preemptive++;
		if( element.isWrite() )
			return ALLOCATE_IN_SRAM;
		else 
			return ALLOCATE_IN_NVM;
	}
	else
	{
		stats_prediction_confident++;
		if( sum_pred < simu_parameters.perceptron_allocation_threshold )
			return ALLOCATE_IN_SRAM;
		else
			return ALLOCATE_IN_NVM;
	}

}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0x40(%rsp), %r15
movq 0x10(%r15), %r14
movq %r14, %rsi
callq 0x20e46
incq 0x368(%rbx)
leaq 0x25429(%rip), %rax     # 0x461a0
movl (%rax), %ecx
movl $0xfe, %edx
cmpl %edx, %ecx
cmovll %ecx, %edx
incl %edx
movl %edx, (%rax)
movq 0x278(%rbx), %rax
cmpq 0x270(%rbx), %rax
je 0x20def
movq 0x30(%r15), %r15
xorl %r12d, %r12d
movl $0x1, %r13d
xorl %ebp, %ebp
movq 0x288(%rbx), %rax
movq %r15, %rdi
movq %r14, %rsi
callq *(%rax,%r12,8)
movq 0x270(%rbx), %rcx
movq (%rcx,%r12,8), %rdi
movl %eax, %esi
movl $0x1, %edx
callq 0x148ea
addl %eax, %ebp
movq 0x278(%rbx), %rax
subq 0x270(%rbx), %rax
movl %r13d, %r12d
sarq $0x3, %rax
incl %r13d
cmpq %r12, %rax
ja 0x20da6
jmp 0x20df1
xorl %ebp, %ebp
movl %ebp, %ecx
negl %ecx
cmovsl %ebp, %ecx
leaq 0x25151(%rip), %rax     # 0x45f50
movl 0x1c0(%rax), %eax
cmpl %eax, %ecx
jge 0x20e28
incq 0x3e0(%rbx)
leaq 0x40(%rsp), %rax
movl 0x1c(%rax), %eax
cmpl $0x3, %eax
setne %cl
cmpl $0x6, %eax
setne %al
andb %cl, %al
jmp 0x20e34
incq 0x3d8(%rbx)
cmpl %eax, %ebp
setge %al
movzbl %al, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::update_globalPChistory(unsigned long)
void
PHCPredictor::update_globalPChistory(uint64_t pc)
{	
	m_global_PChistory.push_front(pc);
	if( m_global_PChistory.size() == 11)
		m_global_PChistory.pop_back();
	
	if(!m_need_callee_file)
		return;
	
	if(m_callee_map.count(pc) != 0)
	{
		m_callee_PChistory.push_front(pc);
		if( m_callee_PChistory.size() == 11)
			m_callee_PChistory.pop_back();
	}
}

// Assembly:
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
movq %rsi, 0x8(%rsp)
movq 0x24cc6(%rip), %rax     # 0x45b20
cmpq 0x24cc7(%rip), %rax     # 0x45b28
je 0x20e74
movq %rsi, -0x8(%rax)
addq $-0x8, %rax
movq %rax, 0x24cae(%rip)     # 0x45b20
jmp 0x20e8c
leaq 0x24c95(%rip), %rdi     # 0x45b10
leaq 0x8(%rsp), %rsi
callq 0x22fec
movq 0x24c94(%rip), %rax     # 0x45b20
movq 0x24cc5(%rip), %rcx     # 0x45b58
movq %rcx, %rdx
subq 0x24c9b(%rip), %rdx     # 0x45b38
shrq $0x3, %rdx
cmpq $0x1, %rcx
adcq $-0x1, %rdx
movq 0x24c90(%rip), %rcx     # 0x45b40
subq 0x24c91(%rip), %rcx     # 0x45b48
shlq $0x6, %rdx
sarq $0x3, %rcx
movq 0x24c6a(%rip), %rsi     # 0x45b30
subq %rax, %rsi
sarq $0x3, %rsi
addq %rcx, %rsi
addq %rdx, %rsi
cmpq $0xb, %rsi
jne 0x20ee5
leaq 0x24c30(%rip), %rdi     # 0x45b10
callq 0x22b64
cmpb $0x1, 0x2e0(%rbx)
jne 0x20fce
movq 0x2f8(%rbx), %rcx
testq %rcx, %rcx
je 0x20fce
addq $0x2f0, %rbx            # imm = 0x2F0
movq 0x8(%rsp), %rax
movq %rbx, %rdx
xorl %esi, %esi
cmpq %rax, 0x20(%rcx)
setb %sil
cmovaeq %rcx, %rdx
movq 0x10(%rcx,%rsi,8), %rcx
testq %rcx, %rcx
jne 0x20f11
cmpq %rbx, %rdx
je 0x20fce
cmpq 0x20(%rdx), %rax
jb 0x20fce
movq 0x24c2d(%rip), %rcx     # 0x45b70
cmpq 0x24c2e(%rip), %rcx     # 0x45b78
je 0x20f5d
movq %rax, -0x8(%rcx)
addq $-0x8, %rcx
movq %rcx, 0x24c15(%rip)     # 0x45b70
jmp 0x20f75
leaq 0x24bfc(%rip), %rdi     # 0x45b60
leaq 0x8(%rsp), %rsi
callq 0x22fec
movq 0x24bfb(%rip), %rcx     # 0x45b70
movq 0x24c2c(%rip), %rax     # 0x45ba8
movq %rax, %rdx
subq 0x24c02(%rip), %rdx     # 0x45b88
shrq $0x3, %rdx
cmpq $0x1, %rax
adcq $-0x1, %rdx
movq 0x24bf7(%rip), %rax     # 0x45b90
subq 0x24bf8(%rip), %rax     # 0x45b98
shlq $0x6, %rdx
sarq $0x3, %rax
movq 0x24bd1(%rip), %rsi     # 0x45b80
subq %rcx, %rsi
sarq $0x3, %rsi
addq %rax, %rsi
addq %rdx, %rsi
cmpq $0xb, %rsi
jne 0x20fce
leaq 0x24b97(%rip), %rdi     # 0x45b60
callq 0x22b64
addq $0x10, %rsp
popq %rbx
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::updatePolicy(unsigned long, unsigned long, bool, Access, bool)
void
PHCPredictor::updatePolicy(uint64_t set, uint64_t index, bool inNVM, Access element, bool isWBrequest)
{
	update_globalPChistory(element.m_pc);
	
	stats_update++;
	
	CacheEntry *entry = get_entry(set , index , inNVM);
	entry->policyInfo = m_cpt++;


	RD_TYPE rd_type = classifyRD( set , index , inNVM );
	stats_access_class[rd_type][element.isWrite()]++;

	if(entry->isLearning)
	{
		entry->cost_value += m_costAccess[element.isWrite()][rd_type];
//		cout << "UpdatePolicy Learning Cache line 0x" << std::hex << element.block_addr
//			<< std::dec << " Cost Value " << entry->cost_value << endl;

	}

	stats_nbHits++;
	miss_counter--;
	if(miss_counter < 0)
		miss_counter = 0;

	Predictor::updatePolicy(set , index , inNVM , element , isWBrequest);
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %r8d, %ebp
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r12
movq 0x50(%rsp), %rsi
callq 0x20e46
incq 0x3a8(%r12)
movl %r15d, %eax
movq 0x8(%r12,%rax,8), %rax
movq (%rax), %rax
leaq (%r14,%r14,2), %rcx
movq (%rax,%rcx,8), %rax
movq (%rax,%rbx,8), %r13
movq 0x2d8(%r12), %rax
leaq 0x1(%rax), %rcx
movq %rcx, 0x2d8(%r12)
movl %eax, 0x38(%r13)
movq %r12, %rdi
movl %r14d, %esi
movl %ebx, %edx
movl %r15d, %ecx
callq 0x210f8
movl %eax, %eax
movq 0x430(%r12), %rdx
leaq (%rax,%rax,2), %rsi
movl 0x5c(%rsp), %ecx
cmpl $0x3, %ecx
sete %dil
cmpl $0x6, %ecx
sete %cl
orb %dil, %cl
movzbl %cl, %ecx
movq (%rdx,%rsi,8), %rdx
incl (%rdx,%rcx,4)
cmpb $0x1, 0x148(%r13)
jne 0x2109c
movq 0x2b8(%r12), %rdx
leaq (%rcx,%rcx,2), %rcx
movq (%rdx,%rcx,8), %rcx
cvtsi2sdl (%rcx,%rax,4), %xmm0
addsd 0x130(%r13), %xmm0
movsd %xmm0, 0x130(%r13)
incq 0x370(%r12)
leaq 0x250f5(%rip), %rax     # 0x461a0
movl (%rax), %ecx
cmpl $0x2, %ecx
movl $0x1, %edx
cmovgel %ecx, %edx
decl %edx
movl %edx, (%rax)
movzbl %r15b, %ecx
movzbl %bpl, %r8d
movq %r12, %rdi
movq %r14, %rsi
movq %rbx, %rdx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x272da
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::classifyRD(int, int, bool)
RD_TYPE
PHCPredictor::classifyRD(int set , int index, bool inNVM)
{
	vector<CacheEntry*> line;
	int64_t ref_rd = 0;
	if(inNVM)
	{
		ref_rd = m_tableNVM[set][index]->policyInfo;
		line = m_tableNVM[set];
	}
	else
	{
		line = m_tableSRAM[set];
		ref_rd = m_tableSRAM[set][index]->policyInfo;
	}
	
	int position = 0;
	/* Determine the position of the cache line in the LRU stack */
	for(unsigned i = 0 ; i < line.size() ; i ++)
	{
		if(line[i]->policyInfo < ref_rd && line[i]->isValid)
			position++;
	}	

	if(simu_parameters.nvm_assoc > simu_parameters.sram_assoc)
	{
		if(position < simu_parameters.mediumrd_def)
			return RD_SHORT;
		else
			return RD_MEDIUM;	
	}
	else
	{
		if(position < simu_parameters.mediumrd_def)
			return RD_SHORT;
		else
			return RD_MEDIUM;
	}
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebx
movq %rdi, %r14
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0x0, 0x10(%rsp)
movslq %esi, %rax
testl %ecx, %ecx
je 0x21144
movq 0x10(%r14), %rcx
movq (%rcx), %rcx
leaq (%rax,%rax,2), %rax
leaq (%rcx,%rax,8), %rsi
movslq %ebx, %rax
movq (%rsi), %rcx
movq (%rcx,%rax,8), %rax
movl 0x38(%rax), %ebp
movq %rsp, %rdi
callq 0xc856
jmp 0x21174
movq 0x8(%r14), %rcx
leaq (%rax,%rax,2), %r15
leaq (,%r15,8), %rsi
addq (%rcx), %rsi
movq %rsp, %rdi
callq 0xc856
movq 0x8(%r14), %rax
movq (%rax), %rax
movslq %ebx, %rcx
movq (%rax,%r15,8), %rax
movq (%rax,%rcx,8), %rax
movl 0x38(%rax), %ebp
movq (%rsp), %rdi
movq 0x8(%rsp), %rax
subq %rdi, %rax
je 0x211b1
sarq $0x3, %rax
xorl %ecx, %ecx
xorl %ebx, %ebx
movq (%rdi,%rcx,8), %rdx
cmpl %ebp, 0x38(%rdx)
jge 0x21198
movzbl (%rdx), %edx
addl %edx, %ebx
incq %rcx
movl %ecx, %edx
cmpq %rdx, %rax
ja 0x2118a
leaq 0x24da7(%rip), %rax     # 0x45f50
movl 0x1fc(%rax), %ebp
jmp 0x211c5
leaq 0x24d98(%rip), %rax     # 0x45f50
movl 0x1fc(%rax), %ebp
xorl %ebx, %ebx
testq %rdi, %rdi
je 0x211ca
callq 0x52b0
xorl %eax, %eax
cmpl %ebp, %ebx
setge %al
addq $0x18, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je 0x211ed
callq 0x52b0
movq %rbx, %rdi
callq 0x55a0
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/PHC.cc
// Function: PHCPredictor::finishSimu()
void 
PHCPredictor::finishSimu()
{
	
	if(simu_parameters.perceptron_drawFeatureMaps)
	{
		drawFeatureMaps();
	}
	
	for(auto feature : m_features)
		feature->finishSimu();
	
	Predictor::finishSimu();
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0x2377c(%rip), %rax     # 0x45f50
cmpb $0x1, 0x1cc(%rax)
jne 0x227e5
movq %rbx, %rdi
callq 0x2280e
movq 0x270(%rbx), %r14
movq 0x278(%rbx), %rbx
cmpq %rbx, %r14
je 0x22806
movq (%r14), %rdi
callq 0x14c0e
addq $0x8, %r14
jmp 0x227f3
addq $0x8, %rsp
popq %rbx
popq %r14
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Perceptron.cc
// Function: PerceptronPredictor::evictPolicy(int, bool)
int PerceptronPredictor::evictPolicy(int set, bool inNVM)
{
	int assoc_victim = -1;
	assert(m_replacementPolicyNVM_ptr != NULL);
	assert(m_replacementPolicySRAM_ptr != NULL);

	CacheEntry* current = NULL;
	if(inNVM)
	{	
		assoc_victim = m_replacementPolicyNVM_ptr->evictPolicy(set);
		current = m_tableNVM[set][assoc_victim];
	}
	else
	{
		assoc_victim = m_replacementPolicySRAM_ptr->evictPolicy(set);
		current = m_tableSRAM[set][assoc_victim];		
	}

	if(current->isValid && current->isLearning)
	{
		for(unsigned i =  0 ; i < m_BP_features.size() ; i++)
		{
			if(current->predictedReused[i] || current->perceptron_BPpred[i] < simu_parameters.perceptron_bypass_learning)
			{
				int hash = m_BP_features_hash[i](current->address , current->m_pc);
 				m_BP_features[i]->increaseConfidence(hash);
			}
		}
		
		if(current->nbWrite == 0 && current->nbRead == 0)
			stats_nbDeadLine[stats_nbDeadLine.size()-1]++;
	}
	
	evictRecording(set , assoc_victim , inNVM);	
	return assoc_victim;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq 0x60(%rdi), %rax
testq %rax, %rax
je 0x24efa
movq %rdi, %r14
movq 0x68(%rdi), %rdi
testq %rdi, %rdi
je 0x24f19
movl %esi, %ebx
movslq %esi, %r12
testb %dl, %dl
cmovneq %rax, %rdi
movzbl %dl, %r15d
movq (%rdi), %rax
movl %r12d, %esi
callq *0x20(%rax)
movl %eax, %ebp
movq 0x8(%r14,%r15,8), %rax
movq (%rax), %rax
leaq (%r12,%r12,2), %rcx
movslq %ebp, %rdx
movq (%rax,%rcx,8), %rax
movq (%rax,%rdx,8), %r12
cmpb $0x1, (%r12)
jne 0x24eda
cmpb $0x1, 0x148(%r12)
jne 0x24eda
movl %ebx, 0x4(%rsp)
movq 0x2b8(%r14), %rax
movq 0x2c0(%r14), %rcx
cmpq %rax, %rcx
je 0x24eb5
movl $0x1, %r13d
xorl %ebx, %ebx
leal -0x1(%r13), %edx
movq 0xa8(%r12), %rsi
shrl $0x6, %edx
movq (%rsi,%rdx,8), %rdx
btq %rbx, %rdx
jb 0x24e6c
movq 0x48(%r12), %rdx
movl (%rdx,%rbx,4), %edx
leaq 0x210ec(%rip), %rsi     # 0x45f50
cmpl 0x1bc(%rsi), %edx
jge 0x24ea0
movq 0x2d0(%r14), %rax
movq 0x8(%r12), %rdi
movq 0x10(%r12), %rsi
callq *(%rax,%rbx,8)
movq 0x2b8(%r14), %rcx
movq (%rcx,%rbx,8), %rdi
movl %eax, %esi
callq 0x149f2
movq 0x2b8(%r14), %rax
movq 0x2c0(%r14), %rcx
movl %r13d, %ebx
movq %rcx, %rdx
subq %rax, %rdx
sarq $0x3, %rdx
incl %r13d
cmpq %rbx, %rdx
ja 0x24e3c
cmpl $0x0, 0x11c(%r12)
movl 0x4(%rsp), %ebx
jne 0x24eda
cmpl $0x0, 0x120(%r12)
jne 0x24eda
movq 0x370(%r14), %rax
incq -0x8(%rax)
movq %r14, %rdi
movl %ebx, %esi
movl %ebp, %edx
movl %r15d, %ecx
callq 0x264ec
movl %ebp, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0xf274(%rip), %rdi      # 0x34175
leaq 0x115b8(%rip), %rsi     # 0x364c0
leaq 0x115f0(%rip), %rcx     # 0x364ff
movl $0x17f, %edx            # imm = 0x17F
callq 0x51d0
leaq 0xf2ae(%rip), %rdi      # 0x341ce
leaq 0x11599(%rip), %rsi     # 0x364c0
leaq 0x115d1(%rip), %rcx     # 0x364ff
movl $0x180, %edx            # imm = 0x180
callq 0x51d0
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::insertionPolicy(unsigned long, unsigned long, bool, Access)
void
Predictor::insertionPolicy(uint64_t set, uint64_t index, bool inNVM, Access element)
{
	CacheEntry* entry = inNVM ? m_tableNVM[set][index] : m_tableSRAM[set][index];
	uint64_t block_addr = bitRemove(element.m_address , 0 , log2(BLOCK_SIZE));
	updateFUcaches(block_addr , inNVM);
	updateCachePressure();


	//Update the missing tag as a new cache line is brough into the cache 
	//Has to remove the MT entry if it exists there 
	//DPRINTF("Predictor::insertRecord Begin ");	
	if(m_trackError)
	{
		if( simu_parameters.enableFullSRAMtraffic )
		{
			//insertIntoSRAMMT(set , inNVM, element );
		}
		else
		{
			if(inNVM)
			{
				for(unsigned i = 0 ; i < m_SRAM_missing_tags[set].size(); i++)
				{
					if(m_SRAM_missing_tags[set][i]->addr == entry->address)
						m_SRAM_missing_tags[set][i]->isValid = false;
				}		
			}		
		}	
		updateBypassTag( entry , set, inNVM);
	}	
	//DPRINTF("Predictor::insertRecord Begin ");

}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movl %ecx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movl %ecx, %eax
movq 0x8(%rdi,%rax,8), %rax
movq (%rax), %rax
leaq (%rsi,%rsi,2), %r12
movq (%rax,%r12,8), %rax
movq (%rax,%rdx,8), %r15
movq 0x30(%rsp), %rdi
xorl %esi, %esi
movl $0x6, %edx
callq 0x2e38e
movq %r14, %rdi
movq %rax, %rsi
movl %ebp, %edx
callq 0x26728
movq %r14, %rdi
callq 0x26be6
cmpb $0x1, 0x80(%r14)
jne 0x2671e
testb %bpl, %bpl
je 0x26705
leaq 0x1f88a(%rip), %rax     # 0x45f50
cmpb $0x0, 0xdc(%rax)
jne 0x26705
movq 0x88(%r14), %rcx
movq (%rcx,%r12,8), %rax
movq 0x8(%rcx,%r12,8), %rcx
subq %rax, %rcx
je 0x26705
sarq $0x3, %rcx
movq 0x8(%r15), %rdx
xorl %esi, %esi
movq (%rax,%rsi,8), %rdi
cmpq %rdx, (%rdi)
jne 0x266fb
movb $0x0, 0x14(%rdi)
incq %rsi
movl %esi, %edi
cmpq %rdi, %rcx
ja 0x266ee
movzbl %bpl, %ecx
movq %r14, %rdi
movq %r15, %rsi
movl %ebx, %edx
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
jmp 0x26cca
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::updateCachePressure()
void
Predictor::updateCachePressure()
{
	if(!m_trackError || !simu_parameters.enableDatasetSpilling)
		return;
		
	if( (cpt_time - stats_beginTimeFrame) > simu_parameters.MT_timeframe)
	{
		for(int i = 0 ; i < m_nb_set ; i++)
		{
			m_isNVMbusy[i] = (m_NVM_MT_counters[i] > simu_parameters.MT_counter_th) ? true : false;		
			m_isSRAMbusy[i] = (m_SRAM_MT_counters[i] > simu_parameters.MT_counter_th) ? true : false;
		
			m_NVM_MT_counters[i] = 0;
			m_SRAM_MT_counters[i] = 0;
		}

		if(simu_parameters.printDebug)
		{
			//stats_SRAMpressure.push_back(m_isSRAMbusy);
		}

		stats_beginTimeFrame = cpt_time;	
	}
}

// Assembly:
cmpb $0x1, 0x80(%rdi)
jne 0x26cc8
leaq 0x1f356(%rip), %rcx     # 0x45f50
cmpb $0x1, 0x158(%rcx)
jne 0x26cc8
leaq 0x1f30a(%rip), %rax     # 0x45f18
movq (%rax), %rsi
movq %rsi, %rdx
subq 0x268(%rdi), %rdx
cmpq 0xd0(%rcx), %rdx
jbe 0x26cc8
movslq 0x18(%rdi), %rdx
testq %rdx, %rdx
jle 0x26cc1
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq 0xb8(%rdi), %rsi
movq 0xd0(%rdi), %r8
movl 0xc8(%rcx), %r9d
movq 0x110(%rdi), %r10
movq 0xe8(%rdi), %r11
xorl %ebx, %ebx
xorl %ecx, %ecx
movl $0x1, %r14d
shlq %cl, %r14
movl %ecx, %r15d
shrl $0x6, %r15d
cmpq %r9, (%r8,%rcx,8)
jbe 0x26c82
movq (%r10,%r15,8), %r12
orq %r14, %r12
jmp 0x26c8c
movq %r14, %r12
notq %r12
andq (%r10,%r15,8), %r12
movq %r12, (%r10,%r15,8)
cmpq %r9, (%rsi,%rcx,8)
jbe 0x26c9c
orq (%r11,%r15,8), %r14
jmp 0x26ca3
notq %r14
andq (%r11,%r15,8), %r14
movq %r14, (%r11,%r15,8)
movq %rbx, (%r8,%rcx,8)
movq %rbx, (%rsi,%rcx,8)
incq %rcx
cmpq %rcx, %rdx
jne 0x26c63
movq (%rax), %rsi
popq %rbx
popq %r12
popq %r14
popq %r15
movq %rsi, 0x268(%rdi)
retq
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::updateBypassTag(CacheEntry*, int, bool)
void
Predictor::updateBypassTag(CacheEntry* entry, int set, bool inNVM)
{
	uint64_t block_addr = entry->address;
	//DPRINTF(DebugCache, "Predictor::recordAllocationDecision Set %d, block_addr = 0x%lx\n ", set, block_addr);

	//Look if the entry already exists, if yes => BP Error, if No insert it
	for(unsigned i = 0 ; i < BP_missing_tags[set].size() ; i++)
	{	
		if(BP_missing_tags[set][i]->addr == block_addr)
		{
			BP_missing_tags[set][i]->last_time_touched = m_cpt_bypassTag++;
			return;		
		}
	}
	//DPRINTF(DebugCache, "Predictor::recordAllocationDecision Didn't find the entry in the BP Missing Tags\n");
	int index_oldest =0;
	uint64_t oldest = BP_missing_tags[set][0]->last_time_touched;
	for(unsigned i = 0 ; i < BP_missing_tags[set].size() ; i++)
	{
		if(!BP_missing_tags[set][i]->isValid)		
		{
			index_oldest= i;
			break;
		}
	
		if(BP_missing_tags[set][i]->last_time_touched < oldest)
		{
			index_oldest = i;
			oldest = BP_missing_tags[set][i]->last_time_touched;
		}
	}
	//DPRINTF(DebugCache, "Predictor::Insertion of the new entry at assoc %d\n", index_oldest);
	
	BP_missing_tags[set][index_oldest]->last_time_touched = m_cpt_bypassTag++;
	BP_missing_tags[set][index_oldest]->addr = block_addr;
	BP_missing_tags[set][index_oldest]->isValid = true;		
	BP_missing_tags[set][index_oldest]->allocSite = inNVM;
	BP_missing_tags[set][index_oldest]->missPC = entry->missPC;
	
	
	/*
	if(m_policy == "Cerebron")
	{
		for(int i = 0 ; i < simu_parameters.PHC_features.size() ; i++)
		{		
			BP_missing_tags[set][index_oldest]->features_hash[i] = entry->PHC_allocation_pred[i].first;
			
		}
	}*/
		
}

// Assembly:
pushq %rbx
movslq %edx, %rax
movq 0x140(%rdi), %r8
leaq (%rax,%rax,2), %rax
movq (%r8,%rax,8), %rdx
movq 0x8(%r8,%rax,8), %r9
movq %r9, %r8
movq 0x8(%rsi), %rax
subq %rdx, %r8
je 0x26d60
sarq $0x3, %r8
movl $0x1, %r10d
xorl %r11d, %r11d
movq (%rdx,%r11,8), %r11
cmpq %rax, (%r11)
je 0x26d44
movl %r10d, %r11d
incl %r10d
cmpq %r11, %r8
ja 0x26cfb
movq (%rdx), %r10
cmpq %rdx, %r9
je 0x26d63
movq 0x8(%r10), %r10
xorl %r9d, %r9d
xorl %r11d, %r11d
movq (%rdx,%r9,8), %rbx
cmpb $0x1, 0x14(%rbx)
jne 0x26d56
movq 0x8(%rbx), %rbx
cmpq %r10, %rbx
cmovbl %r9d, %r11d
cmovbq %rbx, %r10
incl %r9d
cmpq %r9, %r8
ja 0x26d21
jmp 0x26d59
movq 0x38(%rdi), %rax
leaq 0x1(%rax), %rcx
movq %rcx, 0x38(%rdi)
movq %rax, 0x8(%r11)
jmp 0x26d87
movl %r9d, %r11d
movslq %r11d, %r8
leaq (%rdx,%r8,8), %rdx
movq (%rdx), %r10
movq 0x38(%rdi), %rdx
leaq 0x1(%rdx), %r8
movq %r8, 0x38(%rdi)
movq %rdx, 0x8(%r10)
movq %rax, (%r10)
movb $0x1, 0x14(%r10)
movb %cl, 0x16(%r10)
movq 0x20(%rsi), %rax
movq %rax, 0x18(%r10)
popq %rbx
retq
nop
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::missingTagCostValue(unsigned long, int)
int 
Predictor::missingTagCostValue(uint64_t block_addr, int set)
{
	for(unsigned i = 0 ; i < m_SRAM_missing_tags[set].size() ; i++)
	{
		if(m_SRAM_missing_tags[set][i]->addr == block_addr && m_SRAM_missing_tags[set][i]->isValid)
		{
			return m_SRAM_missing_tags[set][i]->cost_value;
		}
	}	
	return 0;
}

// Assembly:
movslq %edx, %rax
movq 0x88(%rdi), %rcx
leaq (%rax,%rax,2), %rdx
movq (%rcx,%rdx,8), %rax
movq 0x8(%rcx,%rdx,8), %rcx
subq %rax, %rcx
je 0x26dc9
sarq $0x3, %rcx
movl $0x1, %edx
xorl %edi, %edi
movq (%rax,%rdi,8), %rdi
cmpq %rsi, (%rdi)
jne 0x26dc0
cmpb $0x1, 0x14(%rdi)
je 0x26dcc
movl %edx, %edi
incl %edx
cmpq %rdi, %rcx
ja 0x26db1
xorl %eax, %eax
retq
movl 0x10(%rdi), %eax
retq
// File: /workspace/github_cpp_makefile_star2_O3/gvaumour[P]cache-simulator/src/Predictor.cc
// Function: Predictor::missingTagMissPC(unsigned long, int)
uint64_t 
Predictor::missingTagMissPC(uint64_t block_addr, int set)
{
	assert( m_policy == "Cerebron" || m_policy == "SimplePerceptron");
	
	for(unsigned i = 0 ; i < m_SRAM_missing_tags[set].size() ; i++)
	{
		if(m_SRAM_missing_tags[set][i]->addr == block_addr && m_SRAM_missing_tags[set][i]->isValid)
		{
			return m_SRAM_missing_tags[set][i]->missPC;
		}
	}
	
	//Sanity check , shouldn't go there 
	assert(false);

	return 0;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x40(%rdi), %r15
leaq 0xea2d(%rip), %rsi      # 0x35817
movq %r15, %rdi
callq 0x50f0
testl %eax, %eax
je 0x26e09
leaq 0xea23(%rip), %rsi      # 0x35820
movq %r15, %rdi
callq 0x50f0
testl %eax, %eax
jne 0x26e76
movslq %ebp, %rax
movq 0x88(%r14), %rcx
leaq (%rax,%rax,2), %rdx
movq (%rcx,%rdx,8), %rax
movq 0x8(%rcx,%rdx,8), %rcx
subq %rax, %rcx
je 0x26e48
sarq $0x3, %rcx
movl $0x1, %edx
xorl %esi, %esi
movq (%rax,%rsi,8), %rsi
cmpq %rbx, (%rsi)
jne 0x26e3f
cmpb $0x0, 0x14(%rsi)
jne 0x26e67
movl %edx, %esi
incl %edx
cmpq %rsi, %rcx
ja 0x26e30
leaq 0xe693(%rip), %rdi      # 0x354e2
leaq 0xf935(%rip), %rsi      # 0x3678b
leaq 0xf93f(%rip), %rcx      # 0x3679c
movl $0x168, %edx            # imm = 0x168
callq 0x51d0
movq 0x18(%rsi), %rax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
leaq 0xf8d5(%rip), %rdi      # 0x36752
leaq 0xf907(%rip), %rsi      # 0x3678b
leaq 0xf911(%rip), %rcx      # 0x3679c
movl $0x15d, %edx            # imm = 0x15D
callq 0x51d0
nop