// File: /workspace/github_cpp_makefile_star2_O2/dsesami[P]superscalar-processor-model/regRead.cc
// Function: regRead()
void regRead(){
    for(u_int i=0; i<WIDTH; i++) {

        // set first cycle and duration of this instruction.
        for(deque<bundle>::iterator it = RR_register.begin(); it != RR_register.end(); it++) {
            if(RR_register.size() && it->regRead_first == -1)
                it->regRead_first = cycles;
        }

        // If the dispatch register is full, do nothing.
        if(DI_register.size() == WIDTH) {
            return;
        }
        // Otherwise check if values in the rob are ready, and if so, and move things forward.
        else if(RR_register.size()) {
            // Wake appropriate dependents! Since we do not have actual register values,
            // simply indicate that we have "ready" sources by indicating that they are not renamed.
            // Wake source 1:
            if(RR_register.front().rn_src_1 != -1) {
                if(ROB.at(RR_register.front().rn_src_1).ready) {
                    RR_register.front().rn_src_1 = -1;
                }
            }
            // Wake source 2:
            if(RR_register.front().rn_src_2 != -1) {
                if(ROB.at(RR_register.front().rn_src_2).ready) {
                    RR_register.front().rn_src_2 = -1;
                }
            }
        for(deque<bundle>::iterator it = RR_register.begin(); it != RR_register.end(); it++) {
            if(RR_register.size() && it->regRead_first == -1)
                it->regRead_first = cycles;
        }

            // Finally, move this bundle to the DI register.
            RR_register.front().regRead_time = cycles - RR_register.front().regRead_first+1;
            DI_register.push_back(RR_register.front());
            RR_register.pop_front();
        }
    }
    return;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
xorl %ebp, %ebp
leaq 0x5131(%rip), %r13      # 0x916c
leaq 0x5456(%rip), %rbx      # 0x9498
leaq 0x5133(%rip), %r14      # 0x917c
leaq 0x28(%rsp), %r15
leaq 0x8(%rsp), %r12
cmpl (%r13), %ebp
jae 0x419f
movq 0x10(%rbx), %rax
movq %rax, 0x8(%rsp)
movups 0x18(%rbx), %xmm0
movups %xmm0, 0x10(%rsp)
movq 0x28(%rbx), %rcx
movq %rcx, 0x20(%rsp)
cmpq 0x30(%rbx), %rax
je 0x40b0
movq %rbx, %rdi
callq 0x2ea4
testq %rax, %rax
je 0x409c
movq 0x8(%rsp), %rax
cmpl $-0x1, 0x3c(%rax)
jne 0x409c
movl (%r14), %ecx
movl %ecx, 0x3c(%rax)
movq %r15, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq 0x3c84
movq 0x8(%rsp), %rax
jmp 0x4078
leaq 0x5431(%rip), %rdi      # 0x94e8
callq 0x2ea4
movl (%r13), %ecx
cmpq %rcx, %rax
je 0x419f
movq %rbx, %rdi
callq 0x2ea4
testq %rax, %rax
je 0x4198
movq 0x10(%rbx), %rcx
movslq 0x18(%rcx), %rsi
cmpq $-0x1, %rsi
je 0x4102
leaq 0x52a1(%rip), %rdi      # 0x9390
callq 0x2ed6
movq 0x10(%rbx), %rcx
cmpb $0x1, 0x8(%rax)
jne 0x4102
orl $-0x1, 0x18(%rcx)
movslq 0x20(%rcx), %rsi
cmpq $-0x1, %rsi
je 0x4126
leaq 0x527d(%rip), %rdi      # 0x9390
callq 0x2ed6
movq 0x10(%rbx), %rcx
cmpb $0x1, 0x8(%rax)
jne 0x4126
orl $-0x1, 0x20(%rcx)
movq %rcx, 0x8(%rsp)
movups 0x18(%rbx), %xmm0
movups %xmm0, 0x10(%rsp)
movq 0x28(%rbx), %rax
movq %rax, 0x20(%rsp)
cmpq 0x30(%rbx), %rcx
je 0x4175
movq %rbx, %rdi
callq 0x2ea4
testq %rax, %rax
je 0x4161
movq 0x8(%rsp), %rax
cmpl $-0x1, 0x3c(%rax)
jne 0x4161
movl (%r14), %ecx
movl %ecx, 0x3c(%rax)
movq %r15, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq 0x3c84
movq 0x8(%rsp), %rcx
jmp 0x413d
movl (%r14), %eax
movq 0x10(%rbx), %rsi
subl 0x3c(%rsi), %eax
incl %eax
movl %eax, 0x40(%rsi)
leaq 0x535d(%rip), %rdi      # 0x94e8
callq 0x39b8
movq %rbx, %rdi
callq 0x3ca4
incl %ebp
jmp 0x4053
addq $0x48, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop