// File: /workspace/github_cpp_makefile_star2_O3/NishadSaraf[P]Championship-Simulator/src/dram_controller.cc
// Function: MEMORY_CONTROLLER::schedule(PACKET_QUEUE*)
void MEMORY_CONTROLLER::schedule(PACKET_QUEUE *queue)
{
    uint64_t read_addr;
    uint32_t read_channel, read_rank, read_bank, read_row;
    uint8_t  row_buffer_hit = 0;

    int oldest_index = -1;
    uint64_t oldest_cycle = UINT64_MAX;

    // first, search for the oldest open row hit
    for (uint32_t i=0; i<queue->SIZE; i++) {

        // already scheduled
        if (queue->entry[i].scheduled) 
            continue;

        // empty entry
        read_addr = queue->entry[i].address;
        if (read_addr == 0) 
            continue;

        read_channel = dram_get_channel(read_addr);
        read_rank = dram_get_rank(read_addr);
        read_bank = dram_get_bank(read_addr);

        // bank is busy
        if (bank_request[read_channel][read_rank][read_bank].working) { // should we check this or not? how do we know if bank is busy or not for all requests in the queue?

            //DP ( if (warmup_complete[0]) {
            //cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " bank is busy";
            //cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            //cout << " write: " << +bank_request[read_channel][read_rank][read_bank].is_write << " read: " << +bank_request[read_channel][read_rank][read_bank].is_read << hex;
            //cout << " address: " << queue->entry[i].address << dec << " channel: " << read_channel << " rank: " << read_rank << " bank: " << read_bank << endl; });

            continue;
        }

        read_row = dram_get_row(read_addr);
        //read_column = dram_get_column(read_addr);

        // check open row
        if (bank_request[read_channel][read_rank][read_bank].open_row != read_row) {

            /*
            DP ( if (warmup_complete[0]) {
            cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " row is inactive";
            cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            cout << " write: " << +bank_request[read_channel][read_rank][read_bank].is_write << " read: " << +bank_request[read_channel][read_rank][read_bank].is_read << hex;
            cout << " address: " << queue->entry[i].address << dec << " channel: " << read_channel << " rank: " << read_rank << " bank: " << read_bank << endl; });
            */

            continue;
        }

        // select the oldest entry
        if (queue->entry[i].event_cycle < oldest_cycle) {
            oldest_cycle = queue->entry[i].event_cycle;
            oldest_index = i;
            row_buffer_hit = 1;
        }	  
    }

    if (oldest_index == -1) { // no matching open_row (row buffer miss)

        oldest_cycle = UINT64_MAX;
        for (uint32_t i=0; i<queue->SIZE; i++) {

            // already scheduled
            if (queue->entry[i].scheduled)
                continue;

            // empty entry
            read_addr = queue->entry[i].address;
            if (read_addr == 0) 
                continue;

            // bank is busy
            read_channel = dram_get_channel(read_addr);
            read_rank = dram_get_rank(read_addr);
            read_bank = dram_get_bank(read_addr);
            if (bank_request[read_channel][read_rank][read_bank].working) 
                continue;

            //read_row = dram_get_row(read_addr);
            //read_column = dram_get_column(read_addr);

            // select the oldest entry
            if (queue->entry[i].event_cycle < oldest_cycle) {
                oldest_cycle = queue->entry[i].event_cycle;
                oldest_index = i;
            }
        }
    }

    // at this point, the scheduler knows which bank to access and if the request is a row buffer hit or miss
    if (oldest_index != -1) { // scheduler might not find anything if all requests are already scheduled or all banks are busy

        uint64_t LATENCY = 0;
        if (row_buffer_hit)  
            LATENCY = tCAS;
        else 
            LATENCY = tRP + tRCD + tCAS;

        uint64_t op_addr = queue->entry[oldest_index].address;
        uint32_t op_cpu = queue->entry[oldest_index].cpu,
                 op_channel = dram_get_channel(op_addr), 
                 op_rank = dram_get_rank(op_addr), 
                 op_bank = dram_get_bank(op_addr), 
                 op_row = dram_get_row(op_addr);
#ifdef DEBUG_PRINT
        uint32_t op_column = dram_get_column(op_addr);
#endif

        // this bank is now busy
        bank_request[op_channel][op_rank][op_bank].working = 1;
        bank_request[op_channel][op_rank][op_bank].working_type = queue->entry[oldest_index].type;
        bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu] + LATENCY;

        bank_request[op_channel][op_rank][op_bank].request_index = oldest_index;
        bank_request[op_channel][op_rank][op_bank].row_buffer_hit = row_buffer_hit;
        if (queue->is_WQ) {
            bank_request[op_channel][op_rank][op_bank].is_write = 1;
            bank_request[op_channel][op_rank][op_bank].is_read = 0;
            scheduled_writes++;
        }
        else {
            bank_request[op_channel][op_rank][op_bank].is_write = 0;
            bank_request[op_channel][op_rank][op_bank].is_read = 1;
            scheduled_reads++;
        }

        // update open row
        bank_request[op_channel][op_rank][op_bank].open_row = op_row;

        queue->entry[oldest_index].scheduled = 1;
        queue->entry[oldest_index].event_cycle = current_core_cycle[op_cpu] + LATENCY;

        update_schedule_cycle(queue);
        update_process_cycle(queue);

        DP (if (warmup_complete[op_cpu]) {
        cout << "[" << queue->NAME << "] " <<  __func__ << " instr_id: " << queue->entry[oldest_index].instr_id;
        cout << " row buffer: " << (row_buffer_hit ? (int)bank_request[op_channel][op_rank][op_bank].open_row : -1) << hex;
        cout << " address: " << queue->entry[oldest_index].address << " full_addr: " << queue->entry[oldest_index].full_addr << dec;
        cout << " index: " << oldest_index << " occupancy: " << queue->occupancy;
        cout << " ch: " << op_channel << " rank: " << op_rank << " bank: " << op_bank; // wrong from here
        cout << " row: " << op_row << " col: " << op_column;
        cout << " current: " << current_core_cycle[op_cpu] << " event: " << queue->entry[oldest_index].event_cycle << endl; });
    }
}

// Assembly:
movl 0x20(%rsi), %edx
testq %rdx, %rdx
je 0xbd60
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
leaq 0x7858(%rdi), %rsi
movl $0x378, %r8d            # imm = 0x378
addq 0x98(%rbx), %r8
movq $-0x1, %r10
movl $0xffffffff, %ecx       # imm = 0xFFFFFFFF
xorl %r9d, %r9d
xorl %eax, %eax
cmpb $0x0, -0x376(%r8)
je 0xbb36
incq %r9
addq $0x380, %r8             # imm = 0x380
cmpq %r9, %rdx
jne 0xbb1b
jmp 0xbb8f
movq -0x38(%r8), %r11
testq %r11, %r11
je 0xbb25
movl %r11d, %r14d
shrl $0x8, %r14d
andl $0x7, %r14d
movl %r11d, %r15d
andl $0x7, %r15d
leaq (%r14,%r14,4), %r14
shll $0x6, %r14d
addq %rsi, %r14
leaq (%r15,%r15,4), %r15
cmpb $0x0, 0x1c(%r14,%r15,8)
jne 0xbb25
leaq (%r14,%r15,8), %r14
shrl $0xb, %r11d
andl $0x7fff, %r11d          # imm = 0x7FFF
cmpl %r11d, 0x18(%r14)
jne 0xbb25
movq (%r8), %r11
cmpq %r10, %r11
jae 0xbb25
movb $0x1, %al
movq %r11, %r10
movl %r9d, %ecx
jmp 0xbb25
cmpl $-0x1, %ecx
je 0xbba7
testb %al, %al
je 0xbc29
movl 0x1067a(%rip), %edx     # 0x1c21c
jmp 0xbc3b
testq %rdx, %rdx
je 0xbd56
movl $0x378, %r8d            # imm = 0x378
addq 0x98(%rbx), %r8
movq $-0x1, %r9
movl $0xffffffff, %ecx       # imm = 0xFFFFFFFF
xorl %r10d, %r10d
cmpb $0x0, -0x376(%r8)
je 0xbbea
incq %r10
addq $0x380, %r8             # imm = 0x380
cmpq %r10, %rdx
jne 0xbbcc
jmp 0xbd61
movq -0x38(%r8), %r11
testq %r11, %r11
je 0xbbd6
movl %r11d, %r14d
shrl $0x8, %r14d
andl $0x7, %r14d
andl $0x7, %r11d
leaq (%r14,%r14,4), %r14
shll $0x6, %r14d
addq %rsi, %r14
leaq (%r11,%r11,4), %r11
cmpb $0x0, 0x1c(%r14,%r11,8)
jne 0xbbd6
movq (%r8), %r11
cmpq %r9, %r11
cmovbq %r11, %r9
cmovbl %r10d, %ecx
jmp 0xbbd6
movl 0x105e9(%rip), %edx     # 0x1c218
addl 0x105df(%rip), %edx     # 0x1c214
addl 0x105e1(%rip), %edx     # 0x1c21c
movl %edx, %edx
movq 0x98(%rbx), %rsi
movslq %ecx, %r10
imulq $0x380, %r10, %rcx      # imm = 0x380
movq 0x340(%rsi,%rcx), %r9
movl 0x330(%rsi,%rcx), %r8d
movl %r9d, %r11d
shrl $0x8, %r11d
andl $0x7, %r11d
movl %r9d, %r14d
andl $0x7, %r14d
shrl $0xb, %r9d
andl $0x7fff, %r9d           # imm = 0x7FFF
leaq (%r11,%r11,4), %r11
shll $0x6, %r11d
addq %rdi, %r11
leaq (%r14,%r14,4), %r14
leaq (%r11,%r14,8), %r11
addq $0x7858, %r11           # imm = 0x7858
movb $0x1, 0x1c(%r11)
movb 0x32f(%rsi,%rcx), %bpl
movb %bpl, 0x1d(%r11)
leaq 0x75213(%rip), %r14     # 0x80ec0
movq (%r14,%r8,8), %r15
addq %rdx, %r15
movq %r15, (%r11)
movl %r10d, 0x24(%r11)
movb %al, 0x1e(%r11)
cmpb $0x0, 0x25(%rbx)
je 0xbcd2
incl 0x784c(%rdi)
movb $0x1, %dil
xorl %eax, %eax
jmp 0xbcdc
incl 0x7848(%rdi)
movb $0x1, %al
xorl %edi, %edi
movb %dil, 0x20(%r11)
movb %al, 0x21(%r11)
movl %r9d, 0x18(%r11)
movb $0x1, 0x2(%rsi,%rcx)
addq (%r14,%r8,8), %rdx
movq %rdx, 0x378(%rsi,%rcx)
movq %rbx, %rsi
callq 0xb848
movl 0x20(%rbx), %eax
testq %rax, %rax
je 0xbd46
movq 0x98(%rbx), %rsi
addq $0x2, %rsi
movq $-0x1, %rcx
xorl %edi, %edi
movl %eax, %edx
cmpb $0x0, (%rsi)
je 0xbd35
movq 0x376(%rsi), %r8
cmpq %rcx, %r8
cmovbq %r8, %rcx
cmovbl %edi, %edx
incq %rdi
addq $0x380, %rsi            # imm = 0x380
cmpq %rdi, %rax
jne 0xbd1f
jmp 0xbd4f
xorl %edx, %edx
movq $-0x1, %rcx
movq %rcx, 0x58(%rbx)
movl %edx, 0x44(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
cmpl $-0x1, %ecx
jne 0xbb94
jmp 0xbd56