// File: /workspace/github_cpp_makefile_star2_O2/martinferianc[P]CPUSimulator-EIE2/src/mips_cpu_execute.cpp
// Function: mips_execute_I_X(mips_cpu_impl*, mips_mem_provider*, unsigned int const*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>> const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>&, unsigned int&, unsigned int&)
mips_error mips_execute_I_X(mips_cpu_h state, mips_mem_h mem, const uint32_t* instruction_data, const string& op, string& instruction, uint32_t& pcN, uint32_t& pc){
	stringstream ss;
	mips_error err = mips_ExceptionInvalidInstruction;

	uint32_t* source2 = new uint32_t;
	uint32_t* source1 = new uint32_t;
	uint32_t destination = instruction_data[2];
	int32_t imm_signed =  int32_t(int16_t(instruction_data[3]));
	uint32_t imm_unsigned = uint32_t(instruction_data[3]);


	err = mips_cpu_get_register(state, (unsigned)instruction_data[1], source1);
	if (err==mips_Success)
	err = mips_cpu_get_register(state, (unsigned)instruction_data[2], source2);
	if (err!=mips_Success)
	return mips_ExceptionAccessViolation;

	if (op.compare("ADDIU")==0)
		err = mips_cpu_set_register(state, destination, *source1 + imm_signed);

	if (op.compare("ADDI")==0){
		if (!addition_overflow(imm_signed,*source1))
			err = mips_cpu_set_register(state, destination, *source1 + imm_signed);
		else
			err = mips_ExceptionArithmeticOverflow;
	}
	if (op.compare("ORI")==0)
	err = mips_cpu_set_register(state, destination, imm_unsigned | *source1);

	if (op.compare("XORI")==0)
	err = mips_cpu_set_register(state, destination, uint32_t(*source1 ^ imm_unsigned));

	if (op.compare("ANDI")==0)
		err = mips_cpu_set_register(state, destination, imm_unsigned & *source1);

	if (op.compare("SLTIU")==0)
	err = mips_cpu_set_register(state, destination, int(uint32_t(*source1) < uint32_t(imm_signed)));

	if (op.compare("SLTI")==0)
	err = mips_cpu_set_register(state, destination, int((int32_t(*source1) < imm_signed)));

	if (op.compare("BEQ")==0){
		if (*source1 == *source2){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}
	if (op.compare("BNE")==0){
		if (*source1 != *source2){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}
	if (op.compare("BGEZ")==0){
		if (int32_t(*source1) >= 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BLEZ")==0){
		if (int32_t(*source1) <= 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BGTZ")==0){
		if (int32_t(*source1) > 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BLTZ")==0){
		if (int32_t(*source1) < 0){
			pc = pcN;
			pcN = int32_t(pcN) + (imm_signed << 2);
			err = mips_ExceptionBreak;
		} else {
			err = mips_Success;
		}
	}

	if (op.compare("BLTZAL")==0){
		if (instruction_data[1]==31) {
			err = mips_ErrorInvalidArgument;
		} else {
			if (int32_t(*source1) < 0){
				mips_cpu_set_register(state, 31, pc + 8);
				pc = pcN;
				pcN = int32_t(pcN) + (imm_signed << 2);
				err = mips_ExceptionBreak;
			} else {
				err = mips_Success;
			}
		}
	}
	if (op.compare("BGEZAL")==0){
		if (instruction_data[1]==31) {
			err = mips_ErrorInvalidArgument;
		} else {
			if (int32_t(*source1) >= 0){
				mips_cpu_set_register(state, 31, pc + 8);
				pc = pcN;
				pcN = int32_t(pcN) + (imm_signed << 2);
				err = mips_ExceptionBreak;
			} else {
				err = mips_Success;
			}
		}
	}

	if (op.compare("LW")==0){
		if ((imm_signed + *source1)%4!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint8_t dataOut[4];
			err = mips_mem_read(mem, imm_signed + *source1, 4, dataOut);
			uint32_t mem_value =  dataOut[3] | (uint32_t(dataOut[2]) << 8) | (uint32_t(dataOut[1]) << 16) | (uint32_t(dataOut[0]) << 24);
			err = mips_cpu_set_register(state, destination, mem_value);
		}
	}

	if (op.compare("LBU")==0){
		uint8_t dataOut;
		err = mips_mem_read(mem, imm_signed + *source1, 1, (uint8_t*)&dataOut);
		uint32_t mem_value = uint32_t(dataOut);
		err = mips_cpu_set_register(state, destination, mem_value);
	}

	if (op.compare("LB")==0){
		uint8_t dataOut;
		err= mips_mem_read(mem, imm_signed + *source1, 1, (uint8_t*)&dataOut);
		int32_t mem_value = int8_t(dataOut);
		err = mips_cpu_set_register(state, destination, mem_value);
	}

	if (op.compare("LHU")==0){
		if ((imm_signed + *source1)%2!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint16_t dataOut;
			err = mips_mem_read(mem, imm_signed + *source1, 2, (uint8_t*)&dataOut);
			uint32_t mem_value = uint32_t(endian16(dataOut));
			err = mips_cpu_set_register(state, destination, mem_value);
		}
	}

	if (op.compare("LH")==0){
		if ((imm_signed + *source1)%2!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint16_t dataOut;
			err = mips_mem_read(mem, imm_signed + *source1, 2, (uint8_t*)&dataOut);
			int32_t mem_value = int32_t(int16_t(endian16(dataOut)));
			err = mips_cpu_set_register(state, destination, mem_value);
		}
	}

	if (op.compare("SW")==0){
		if ((imm_signed + *source1)%4!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint32_t value = uint32_t(endian32(*source2));
			err = mips_mem_write(mem, imm_signed + *source1 ,4, (uint8_t*)&value);
		}
	}


	if (op.compare("SB")==0){
		uint8_t mem_value = *source2 & 0xFF;
		err = mips_mem_write(mem, imm_signed + *source1 ,1, (uint8_t*)&mem_value);
	}

	if (op.compare("SH")==0){
		if ((imm_signed + *source1)%2!=0) {
			err = mips_ExceptionInvalidAlignment;
		} else {
			uint16_t mem_value = endian16(uint16_t(*source2 & 0x0000FFFF));
			uint16_t value = uint16_t(mem_value);
			err = mips_mem_write(mem, imm_signed + *source1 ,2, (uint8_t*)&value);
		}
	}

	if (op.compare("LUI")==0)
		err = mips_cpu_set_register(state, destination, imm_signed << 16);

	if (op.compare("LWL")==0){
		uint32_t address = imm_signed + *source1;
		uint8_t length = 4 - int(address % 4);
		uint8_t dataOut[4];
		mips_error err= mips_mem_read(mem, address - int(address % 4), 4, dataOut);
		uint32_t mem_value = uint32_t(dataOut[3]) | (uint32_t(dataOut[2]) << 8) | (uint32_t(dataOut[1]) << 16) | (uint32_t(dataOut[0]) << 24);
		mem_value = uint32_t(mem_value) << (4-length)*8;
		*source2 = *source2 & (uint32_t(0xFFFFFFFF) >> length*8);
		*source2 = (uint32_t(mem_value)) | uint32_t(*source2);
		err = mips_cpu_set_register(state, destination, *source2);
	}

	if (op.compare("LWR")==0){
		uint32_t address = imm_signed + *source1;
		uint8_t length = int(address % 4) + 1;
		uint8_t dataOut[4];
		mips_error err= mips_mem_read(mem, address - int(address % 4), 4, dataOut);
		uint32_t mem_value = uint32_t(dataOut[3]) | (uint32_t(dataOut[2]) << 8) | (uint32_t(dataOut[1]) << 16) | (uint32_t(dataOut[0]) << 24);
		mem_value = uint32_t(mem_value) >> (4-length)*8;
		*source2 = *source2 & (uint32_t(0xFFFFFFFF) << length*8);
		*source2 = (uint32_t(mem_value)) | uint32_t(*source2);
		err = mips_cpu_set_register(state, destination, *source2);
	}

	//COUT OUTPUT
	if ((err==mips_Success) || (err==mips_ExceptionBreak)) {
		if ((op.compare("SB")==0) || (op.compare("SW")==0) || (op.compare("LBU")==0) || (op.compare("LW")==0)
		|| (op.compare("SH")==0) || (op.compare("LH")==0) || (op.compare("LHU")==0) || (op.compare("LB")==0))
		ss <<op<<" R["<<instruction_data[2]<<"],"<<" #"<<instruction_data[3]<<", R["<<instruction_data[1]<<"] ";

		if ((op.compare("BGEZ")==0) || (op.compare("BGEZAL")==0) || (op.compare("BGTZ")==0) || (op.compare("BLEZ")==0) ||
		(op.compare("BLTZAL")==0))
		ss <<op<<" R["<<instruction_data[1]<<"],"<<" #"<<instruction_data[3];

		if((op.compare("LUI")==0))
		ss <<op<<" R["<<instruction_data[2]<<"],"<<" #"<<instruction_data[3];

		if ((op.compare("BEQ")==0) || (op.compare("BNE")==0))
		ss <<op<<" R["<<instruction_data[1]<<"] , R["<<instruction_data[2]<<"], "<<"#"<<instruction_data[3];

		if (ss.str().empty())
		ss <<op<<" R["<<instruction_data[2]<<"] , R["<<instruction_data[1]<<"], "<<"#"<<instruction_data[3];
		instruction = ss.str();
	} else {
		instruction = "Invalid instruction format";
	}

	delete source1;
	return err;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1d8, %rsp            # imm = 0x1D8
movq %r9, %rbx
movq %r8, 0x48(%rsp)
movq %rcx, %r12
movq %rdx, %r15
movq %rsi, 0x10(%rsp)
movq %rdi, %r13
leaq 0x50(%rsp), %rdi
callq 0x3140
pushq $0x4
popq %rdi
callq 0x31d0
movq %rax, 0x20(%rsp)
pushq $0x4
popq %rdi
callq 0x31d0
movq %rax, %r14
movl 0x4(%r15), %esi
movl 0x8(%r15), %eax
movl %eax, 0x4(%rsp)
movl 0xc(%r15), %eax
movq %rax, 0x18(%rsp)
movq %r13, %rdi
movq %r14, %rdx
callq 0x4864
movl $0x2004, %ebp           # imm = 0x2004
testl %eax, %eax
jne 0x7273
movl 0x8(%r15), %esi
movq %r13, %rdi
movq 0x20(%rsp), %rdx
callq 0x4864
testl %eax, %eax
jne 0x7273
movswl 0x18(%rsp), %eax
movl %eax, 0xc(%rsp)
leaq 0x2d0b(%rip), %rsi      # 0x9569
movq %r12, %rdi
callq 0x3090
xorl %ebp, %ebp
testl %eax, %eax
jne 0x6881
movl (%r14), %edx
addl 0xc(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2cbe(%rip), %rsi      # 0x9546
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x68be
movl (%r14), %esi
movl 0xc(%rsp), %edi
callq 0x7456
movl $0x2006, %ebp           # imm = 0x2006
testb %al, %al
jne 0x68be
movl (%r14), %edx
addl 0xc(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x317b(%rip), %rsi      # 0x9a40
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x68e6
movl (%r14), %edx
orl 0x18(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x3152(%rip), %rsi      # 0x9a3f
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x690e
movl (%r14), %edx
xorl 0x18(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2caf(%rip), %rsi      # 0x95c4
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6936
movl (%r14), %edx
andl 0x18(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2ff4(%rip), %rsi      # 0x9931
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6963
xorl %edx, %edx
movl 0xc(%rsp), %eax
cmpl %eax, (%r14)
setb %dl
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2f9e(%rip), %rsi      # 0x9908
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6990
xorl %edx, %edx
movl 0xc(%rsp), %eax
cmpl %eax, (%r14)
setl %dl
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
movq 0x18(%rsp), %rax
shll $0x10, %eax
movl %eax, 0x8(%rsp)
leaq 0x2c3c(%rip), %rsi      # 0x95df
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x69d9
movl (%r14), %eax
xorl %ebp, %ebp
movq 0x20(%rsp), %rcx
cmpl (%rcx), %eax
jne 0x69d9
movl (%rbx), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x2d0a(%rip), %rsi      # 0x96ea
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6a16
movl (%r14), %eax
xorl %ebp, %ebp
movq 0x20(%rsp), %rcx
cmpl (%rcx), %eax
je 0x6a16
movl (%rbx), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x2bd6(%rip), %rsi      # 0x95f3
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6a4f
cmpl $0x0, (%r14)
js 0x6a4d
movl (%rbx), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
jmp 0x6a4f
xorl %ebp, %ebp
leaq 0x2c23(%rip), %rsi      # 0x9679
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6a86
xorl %ebp, %ebp
cmpl $0x0, (%r14)
jg 0x6a86
movl (%rbx), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x2bcb(%rip), %rsi      # 0x9658
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6abf
cmpl $0x0, (%r14)
jle 0x6abd
movl (%rbx), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
jmp 0x6abf
xorl %ebp, %ebp
leaq 0x2bdd(%rip), %rsi      # 0x96a3
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6af6
xorl %ebp, %ebp
cmpl $0x0, (%r14)
jns 0x6af6
movl (%rbx), %eax
movq 0x210(%rsp), %rcx
movl %eax, (%rcx)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x2bc4(%rip), %rsi      # 0x96c1
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6b4b
movl $0x1001, %ebp           # imm = 0x1001
cmpl $0x1f, 0x4(%r15)
je 0x6b4b
xorl %ebp, %ebp
cmpl $0x0, (%r14)
jns 0x6b4b
movq 0x210(%rsp), %rbp
movl (%rbp), %edx
addl $0x8, %edx
pushq $0x1f
popq %rsi
movq %r13, %rdi
callq 0x4884
movl (%rbx), %eax
movl %eax, (%rbp)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
leaq 0x2ace(%rip), %rsi      # 0x9620
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6ba2
movl $0x1001, %ebp           # imm = 0x1001
cmpl $0x1f, 0x4(%r15)
je 0x6ba2
cmpl $0x0, (%r14)
js 0x6ba0
movq 0x210(%rsp), %rbp
movl (%rbp), %edx
addl $0x8, %edx
pushq $0x1f
popq %rsi
movq %r13, %rdi
callq 0x4884
movl (%rbx), %eax
movl %eax, (%rbp)
movl 0x8(%rsp), %ecx
sarl $0xe, %ecx
addl %eax, %ecx
movl %ecx, (%rbx)
movl $0x2000, %ebp           # imm = 0x2000
jmp 0x6ba2
xorl %ebp, %ebp
leaq 0x2c2a(%rip), %rsi      # 0x97d3
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
movl 0xc(%rsp), %ebx
jne 0x6bf4
movl (%r14), %esi
movq 0x18(%rsp), %rax
addl %esi, %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x3, %al
jne 0x6bf4
addl %ebx, %esi
pushq $0x4
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
movl 0x28(%rsp), %edx
bswapl %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2b7a(%rip), %rsi      # 0x9775
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6c31
movl (%r14), %esi
addl %ebx, %esi
pushq $0x1
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
movzbl 0x28(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2b30(%rip), %rsi      # 0x9768
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6c6e
movl (%r14), %esi
addl %ebx, %esi
pushq $0x1
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
movsbl 0x28(%rsp), %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2b29(%rip), %rsi      # 0x979e
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6cc3
movl (%r14), %esi
movq 0x18(%rsp), %rax
addl %esi, %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x1, %al
jne 0x6cc3
addl %ebx, %esi
pushq $0x2
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
leaq 0x28(%rsp), %rdi
callq 0x748f
movzwl %ax, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2ac2(%rip), %rsi      # 0x978c
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6d18
movl (%r14), %esi
movq 0x18(%rsp), %rax
addl %esi, %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x1, %al
jne 0x6d18
addl %ebx, %esi
pushq $0x2
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
leaq 0x28(%rsp), %rdi
callq 0x748f
movswl %ax, %edx
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
movl %eax, %ebp
leaq 0x2cf9(%rip), %rsi      # 0x9a18
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6d60
movl (%r14), %eax
addl 0x18(%rsp), %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x3, %al
jne 0x6d60
movq 0x20(%rsp), %rdi
callq 0x748a
leaq 0x28(%rsp), %rcx
movl %eax, (%rcx)
movl (%r14), %esi
addl %ebx, %esi
pushq $0x4
popq %rdx
movq 0x10(%rsp), %rdi
callq 0x47d2
movl %eax, %ebp
leaq 0x2b2a(%rip), %rsi      # 0x9891
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6d95
movq 0x20(%rsp), %rax
movb (%rax), %al
leaq 0x28(%rsp), %rcx
movb %al, (%rcx)
movl (%r14), %esi
addl %ebx, %esi
pushq $0x1
popq %rdx
movq 0x10(%rsp), %rdi
callq 0x47d2
movl %eax, %ebp
leaq 0x2b03(%rip), %rsi      # 0x989f
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6dea
movq 0x18(%rsp), %rax
addl (%r14), %eax
movl $0x2003, %ebp           # imm = 0x2003
testb $0x1, %al
jne 0x6dea
movq 0x20(%rsp), %rax
movzwl (%rax), %eax
leaq 0x28(%rsp), %rdi
movw %ax, (%rdi)
callq 0x748f
leaq 0x28(%rsp), %rcx
movw %ax, (%rcx)
movl (%r14), %esi
addl %ebx, %esi
pushq $0x2
popq %rdx
movq 0x10(%rsp), %rdi
callq 0x47d2
movl %eax, %ebp
leaq 0x29c9(%rip), %rsi      # 0x97ba
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6e0f
movq %r13, %rdi
movl 0x4(%rsp), %esi
movl 0x8(%rsp), %edx
callq 0x4884
movl %eax, %ebp
leaq 0x29ca(%rip), %rsi      # 0x97e0
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6e6c
movl (%r14), %ebx
addl 0xc(%rsp), %ebx
movl %ebx, %esi
andl $-0x4, %esi
pushq $0x4
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
movl 0x28(%rsp), %edx
bswapl %edx
shll $0x3, %ebx
movq 0x20(%rsp), %rsi
movl (%rsi), %eax
movl %ebx, %ecx
andb $0x18, %cl
negb %cl
shll %cl, %eax
movl %ebx, %ecx
shldl %cl, %eax, %edx
movl %edx, (%rsi)
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
leaq 0x2980(%rip), %rsi      # 0x97f3
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x6ed0
movl 0xc(%rsp), %ebx
addl (%r14), %ebx
movl %ebx, %esi
andl $-0x4, %esi
pushq $0x4
popq %rdx
leaq 0x28(%rsp), %rcx
movq 0x10(%rsp), %rdi
callq 0x473f
movl 0x28(%rsp), %eax
bswapl %eax
shll $0x3, %ebx
andl $0x18, %ebx
movl %ebx, %ecx
xorb $0x18, %cl
shrl %cl, %eax
movl $0xffffff00, %edx       # imm = 0xFFFFFF00
movl %ebx, %ecx
shll %cl, %edx
movq 0x20(%rsp), %rcx
andl (%rcx), %edx
orl %eax, %edx
movl %edx, (%rcx)
movq %r13, %rdi
movl 0x4(%rsp), %esi
callq 0x4884
testl $0xffffdfff, %ebp       # imm = 0xFFFFDFFF
je 0x6eee
leaq 0x2dcd(%rip), %rsi      # 0x9cac
movq 0x48(%rsp), %rdi
callq 0x3360
jmp 0x7268
leaq 0x299c(%rip), %rsi      # 0x9891
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x2b0c(%rip), %rsi      # 0x9a18
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x2856(%rip), %rsi      # 0x9775
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x28a1(%rip), %rsi      # 0x97d3
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x295a(%rip), %rsi      # 0x989f
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x2834(%rip), %rsi      # 0x978c
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x2833(%rip), %rsi      # 0x979e
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x6f8a
leaq 0x27ea(%rip), %rsi      # 0x9768
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x7006
leaq 0x60(%rsp), %rdi
movq %r12, %rsi
callq 0x31b0
leaq 0x2d31(%rip), %rsi      # 0x9ccf
movq %rax, %rdi
callq 0x31c0
movl 0x8(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2d33(%rip), %rsi      # 0x9cec
movq %rax, %rdi
callq 0x31c0
leaq 0x2d0d(%rip), %rsi      # 0x9cd5
movq %rax, %rdi
callq 0x31c0
movl 0xc(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2ceb(%rip), %rsi      # 0x9cce
movq %rax, %rdi
callq 0x31c0
movl 0x4(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2cf1(%rip), %rsi      # 0x9cef
movq %rax, %rdi
callq 0x31c0
leaq 0x25e6(%rip), %rsi      # 0x95f3
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x7065
leaq 0x2600(%rip), %rsi      # 0x9620
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x7065
leaq 0x2625(%rip), %rsi      # 0x9658
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x7065
leaq 0x2633(%rip), %rsi      # 0x9679
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x7065
leaq 0x2668(%rip), %rsi      # 0x96c1
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x70b7
leaq 0x60(%rsp), %rdi
movq %r12, %rsi
callq 0x31b0
leaq 0x2c56(%rip), %rsi      # 0x9ccf
movq %rax, %rdi
callq 0x31c0
movl 0x4(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2c58(%rip), %rsi      # 0x9cec
movq %rax, %rdi
callq 0x31c0
leaq 0x2c32(%rip), %rsi      # 0x9cd5
movq %rax, %rdi
callq 0x31c0
movl 0xc(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x26fc(%rip), %rsi      # 0x97ba
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x711c
leaq 0x60(%rsp), %rdi
movq %r12, %rsi
callq 0x31b0
leaq 0x2bf1(%rip), %rsi      # 0x9ccf
movq %rax, %rdi
callq 0x31c0
movl 0x8(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2bf3(%rip), %rsi      # 0x9cec
movq %rax, %rdi
callq 0x31c0
leaq 0x2bcd(%rip), %rsi      # 0x9cd5
movq %rax, %rdi
callq 0x31c0
movl 0xc(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x24bc(%rip), %rsi      # 0x95df
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
je 0x7142
leaq 0x25b4(%rip), %rsi      # 0x96ea
movq %r12, %rdi
callq 0x3090
testl %eax, %eax
jne 0x71af
leaq 0x60(%rsp), %rdi
movq %r12, %rsi
callq 0x31b0
leaq 0x2b79(%rip), %rsi      # 0x9ccf
movq %rax, %rdi
callq 0x31c0
movl 0x4(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2b5b(%rip), %rsi      # 0x9ccc
movq %rax, %rdi
callq 0x31c0
movl 0x8(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2b66(%rip), %rsi      # 0x9cf2
movq %rax, %rdi
callq 0x31c0
leaq 0x2b3b(%rip), %rsi      # 0x9cd6
movq %rax, %rdi
callq 0x31c0
movl 0xc(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x68(%rsp), %rbx
leaq 0x28(%rsp), %rdi
movq %rbx, %rsi
callq 0x32f0
leaq 0x28(%rsp), %rdi
movq 0x8(%rdi), %r13
callq 0x30d0
testq %r13, %r13
jne 0x7241
leaq 0x60(%rsp), %rdi
movq %r12, %rsi
callq 0x31b0
leaq 0x2ae7(%rip), %rsi      # 0x9ccf
movq %rax, %rdi
callq 0x31c0
movl 0x8(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2ac9(%rip), %rsi      # 0x9ccc
movq %rax, %rdi
callq 0x31c0
movl 0x4(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x2ad4(%rip), %rsi      # 0x9cf2
movq %rax, %rdi
callq 0x31c0
leaq 0x2aa9(%rip), %rsi      # 0x9cd6
movq %rax, %rdi
callq 0x31c0
movl 0xc(%r15), %esi
movq %rax, %rdi
callq 0x3120
leaq 0x28(%rsp), %rdi
movq %rbx, %rsi
callq 0x32f0
leaq 0x28(%rsp), %rbx
movq 0x48(%rsp), %rdi
movq %rbx, %rsi
callq 0x3240
movq %rbx, %rdi
callq 0x30d0
pushq $0x4
popq %rsi
movq %r14, %rdi
callq 0x31e0
leaq 0x50(%rsp), %rdi
callq 0x3160
movl %ebp, %eax
addq $0x1d8, %rsp            # imm = 0x1D8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
jmp 0x72bd
movq %rax, %rbx
leaq 0x50(%rsp), %rdi
callq 0x3160
movq %rbx, %rdi
callq 0x3330