// File: /workspace/github_c_makefile_star2_O2/ughman[P]c2c/src/emu.c
// Function: EMU_Write32
void EMU_Write32(uint32_t address,uint32_t value)
{
	if (address & 3)
		SDL_LogError(LOG_EMU,"Unaligned word store");
	if (address >= 0x80000000 && address <= 0x801FFFFF)
	{
normal:
		{
			uint32_t (*codehandler)(uint32_t) = EMU_codemap[(address & 0x1FFFFF) >> 2];
			if (codehandler != EMU_ExecuteUnrecognizedCode)
			{
				SDL_LogError(LOG_EMU,"Writing over code");
			}
		}
		EMU_ram[(address & 0x1FFFFF) >> 2] = value;
	}
	else if (address >= 0x0 && address <= 0x1FFFFF)
	{
		goto normal;
	}
	else if (address >= 0xA0000000 && address <= 0xA01FFFFF)
	{
		goto normal;
	}
	else if (address >= 0x1F800000 && address <= 0x1F8003FF)
	{
		EMU_scratch[(address & 0x3FF) >> 2] = value;
	}
	else switch (address)
	{
	case 0x1F801014:
	case 0x1F801018:
	case 0x1F801020:
		// Unused waitstate configuration
		PCSX_Write32(address,value);
		break;
	case 0x1F801074:
		IRQ_SetMask(value);
		break;
	case 0x1F8010A0:
		DMA_SetAddress(DMA_GPU,value);
		break;
	case 0x1F8010A4:
		DMA_SetBlockData(DMA_GPU,value);
		break;
	case 0x1F8010A8:
		DMA_SetMode(DMA_GPU,value);
		break;
	case 0x1F8010B0:
		DMA_SetAddress(DMA_CDR,value);
		break;
	case 0x1F8010B4:
		DMA_SetBlockData(DMA_CDR,value);
		break;
	case 0x1F8010B8:
		DMA_SetMode(DMA_CDR,value);
		break;
	case 0x1F8010C0:
		DMA_SetAddress(DMA_SPU,value);
		break;
	case 0x1F8010C4:
		DMA_SetBlockData(DMA_SPU,value);
		break;
	case 0x1F8010C8:
		DMA_SetMode(DMA_SPU,value);
		break;
	case 0x1F8010F0:
		DMA_SetControlRegister(value);
		break;
	case 0x1F8010F4:
		DMA_SetInterruptRegister(value);
		break;
	case 0x1F801114:
		RCNT_SetMode(RCNT_HBLANK,value);
		break;
	case 0x1F801810:
		GPU_Write(value);
		break;
	case 0x1F801814:
		GPU_WriteAlt(value);
		break;
	default:
		SDL_LogError(LOG_EMU,"Unrecognized 32-bit write address %.8X",address);
		PCSX_Write32(address,value);
		break;
	}
}

// Assembly:
pushq %r14
pushq %rbx
pushq %rax
movl %esi, %ebx
movl %edi, %r14d
testb $0x3, %r14b
je 0x135d6c
leaq 0x44a6(%rip), %rsi      # 0x13a208
pushq $0x13
popq %rdi
xorl %eax, %eax
callq 0x10d0
testl $0x7fe00000, %r14d      # imm = 0x7FE00000
setne %al
movl %r14d, %ecx
andl $0xffe00000, %ecx       # imm = 0xFFE00000
cmpl $0xa0000000, %ecx       # imm = 0xA0000000
setne %cl
testb %cl, %al
jne 0x135dc9
shrl $0x2, %r14d
andl $0x7ffff, %r14d         # imm = 0x7FFFF
leaq 0x245c2(%rip), %rax     # 0x15a360
leaq -0xaad(%rip), %rcx      # 0x1352f8
cmpq %rcx, (%rax,%r14,8)
je 0x135dbc
leaq 0x43de(%rip), %rsi      # 0x13a190
pushq $0x13
popq %rdi
xorl %eax, %eax
callq 0x10d0
movq 0x42459d(%rip), %rax    # 0x55a360
movl %ebx, (%rax,%r14,4)
jmp 0x135dea
movl %r14d, %eax
andl $0xfffffc00, %eax       # imm = 0xFFFFFC00
cmpl $0x1f800000, %eax       # imm = 0x1F800000
jne 0x135df2
movq 0x424589(%rip), %rax    # 0x55a368
andl $0x3fc, %r14d           # imm = 0x3FC
movl %ebx, (%rax,%r14)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
leal -0x1f801014(%r14), %eax
cmpl $0xc, %eax
jbe 0x135ec3
cmpl $0x1f801074, %r14d      # imm = 0x1F801074
je 0x135f04
cmpl $0x1f8010a0, %r14d      # imm = 0x1F8010A0
je 0x135ed2
cmpl $0x1f8010a4, %r14d      # imm = 0x1F8010A4
je 0x135f63
cmpl $0x1f8010a8, %r14d      # imm = 0x1F8010A8
je 0x135eee
cmpl $0x1f8010b0, %r14d      # imm = 0x1F8010B0
je 0x135ed9
cmpl $0x1f8010b4, %r14d      # imm = 0x1F8010B4
je 0x135f78
cmpl $0x1f8010b8, %r14d      # imm = 0x1F8010B8
je 0x135ef2
cmpl $0x1f8010c0, %r14d      # imm = 0x1F8010C0
je 0x135f89
cmpl $0x1f8010c4, %r14d      # imm = 0x1F8010C4
je 0x135f25
cmpl $0x1f8010c8, %r14d      # imm = 0x1F8010C8
je 0x135f67
cmpl $0x1f8010f0, %r14d      # imm = 0x1F8010F0
je 0x135f55
cmpl $0x1f8010f4, %r14d      # imm = 0x1F8010F4
je 0x135ee0
cmpl $0x1f801114, %r14d      # imm = 0x1F801114
je 0x135f13
cmpl $0x1f801810, %r14d      # imm = 0x1F801810
je 0x135ef6
cmpl $0x1f801814, %r14d      # imm = 0x1F801814
jne 0x135f29
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x134641
movl $0x1011, %ecx           # imm = 0x1011
btl %eax, %ecx
jb 0x135f3d
jmp 0x135e02
pushq $0x2
jmp 0x135f8b
pushq $0x3
jmp 0x135f8b
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x134720
pushq $0x2
jmp 0x135f69
pushq $0x3
jmp 0x135f69
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x13462e
movzwl %bx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x13460b
movzwl %bx, %esi
pushq $0x1
popq %rdi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x134676
pushq $0x4
jmp 0x135f7a
leaq 0x42ed(%rip), %rsi      # 0x13a21d
pushq $0x13
popq %rdi
movl %r14d, %edx
xorl %eax, %eax
callq 0x10d0
leaq 0x24364(%rip), %rax     # 0x15a2a8
movq (%rax), %rax
movl %r14d, %edi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmpq *%rax
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1346ff
pushq $0x2
jmp 0x135f7a
pushq $0x4
popq %rdi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1346dc
pushq $0x3
popq %rdi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1346b5
pushq $0x4
popq %rdi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1346a0