// File: /workspace/github_c_makefile_star2_O0/mjosaarinen[P]brutus/crypto_aead/minalpherv11/avx2/MinalpherMode.cpp
// Function: minalpher_mode_decryption(unsigned char const*, unsigned char const*, unsigned char const*, unsigned long long, unsigned char*, unsigned long long*)
int minalpher_mode_decryption(
  const unsigned char     *_K,    /* I    Secret key                */
  const unsigned char     *_N,    /* I    Nonce                     */
  const unsigned char     *_C,    /* I    Ciphertext                */
  unsigned long long      _clen,  /* I    Length of Ciphertext      */
  unsigned char           *M_,    /* O    Message                   */
  unsigned long long      *mlen_  /* O    Length of Message         */
  ){
  /*==== Prepare ====*/
  __m256i ymmTagA[4];
  __m256i ymmTagB[4];
  for (int i = 0; i<4; i++){
    ymmTagA[i] = _mm256_setzero_si256();
    ymmTagB[i] = _mm256_setzero_si256();
  }
  __m256i DATA;
  __m256i DATA1, DATA2, DATA3, DATA4;

  /*==== Process Message ====*/
  int mblock = (int)((_clen) / 32);

  /*==== Create L ====*/
  int cnt = 0;
  __m256i ymmL, ymmL_H;
  create_l(ymmL, _K, _N);

  //Main loop
  int p = 0;
  for (p = 0; p < ((long long)(_clen)-128); p += 128)
  {
    //Encryption
    DATA1 = _mm256_load_si256((const __m256i*)(_C + p));
    DATA2 = _mm256_load_si256((const __m256i*)(_C + p + 32));
    DATA3 = _mm256_load_si256((const __m256i*)(_C + p + 64));
    DATA4 = _mm256_load_si256((const __m256i*)(_C + p + 96));

    __m256i tweak1, tweak2, tweak3, tweak4, tweak5, tweak6, tweak7, tweak8;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak1 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak5 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak2 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak6 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak3 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak7 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak4 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak8 = ymmL;

    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    DATA3 = _mm256_xor_si256(DATA3, tweak3);
    DATA4 = _mm256_xor_si256(DATA4, tweak4);
    minalpher_core_quadruple_block_inverse(DATA1, DATA2, DATA3, DATA4);
    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    DATA3 = _mm256_xor_si256(DATA3, tweak3);
    DATA4 = _mm256_xor_si256(DATA4, tweak4);
    _mm256_store_si256((__m256i *)(M_ + p), DATA1);
    _mm256_store_si256((__m256i *)(M_ + p + 32), DATA2);
    _mm256_store_si256((__m256i *)(M_ + p + 64), DATA3);
    _mm256_store_si256((__m256i *)(M_ + p + 96), DATA4);
  }

  //length update
  *mlen_ = p;

  if ((mblock % 4) == 0){
    //padding
    DATA1 = _mm256_load_si256((const __m256i*)(_C + p));
    DATA2 = _mm256_load_si256((const __m256i*)(_C + p + 32));
    DATA3 = _mm256_load_si256((const __m256i*)(_C + p + 64));
    DATA4 = _mm256_load_si256((const __m256i*)(_C + p + 96));

    //tweak update
    __m256i tweak1, tweak2, tweak3, tweak4, tweak5, tweak6, tweak7, tweak8;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak1 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak5 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak2 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak6 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak3 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak7 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak4 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak8 = ymmL;

    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    DATA3 = _mm256_xor_si256(DATA3, tweak3);
    DATA4 = _mm256_xor_si256(DATA4, tweak4);
    minalpher_core_quadruple_block_inverse(DATA1, DATA2, DATA3, DATA4);
    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    DATA3 = _mm256_xor_si256(DATA3, tweak3);
    DATA4 = _mm256_xor_si256(DATA4, tweak4);

    _mm256_store_si256((__m256i *)(M_ + p), DATA1);
    _mm256_store_si256((__m256i *)(M_ + p + 32), DATA2);
    _mm256_store_si256((__m256i *)(M_ + p + 64), DATA3);
    _mm256_store_si256((__m256i *)(M_ + p + 96), DATA4);

    //Format Verification
    for (int d = BLOCK_SIZE - 1; d >= 0; d--){
      if ( (M_ + p + 96)[d] == 0x80){
        *mlen_ += 96 + d;
        return 0;
      }
      if ((M_ + p + 96)[d] != 0x00){
        break;
      }
    }
  }
  else if ((mblock % 4) == 3){
    //padding
    DATA1 = _mm256_load_si256((const __m256i*)(_C + p));
    DATA2 = _mm256_load_si256((const __m256i*)(_C + p + 32));
    DATA3 = _mm256_load_si256((const __m256i*)(_C + p + 64));

    //tweak update
    __m256i tweak1, tweak2, tweak3, tweak4, tweak5, tweak6;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak1 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak4 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak2 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak5 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak3 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak6 = ymmL;

    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    DATA3 = _mm256_xor_si256(DATA3, tweak3);
    minalpher_core_quadruple_block_inverse(DATA1, DATA2, DATA3);
    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    DATA3 = _mm256_xor_si256(DATA3, tweak3);

    _mm256_store_si256((__m256i *)(M_ + p), DATA1);
    _mm256_store_si256((__m256i *)(M_ + p + 32), DATA2);
    _mm256_store_si256((__m256i *)(M_ + p + 64), DATA3);

    //Format Verification
    for (int d = BLOCK_SIZE - 1; d >= 0; d--){
      if ((M_ + p + 64)[d] == 0x80){
        *mlen_ += 64 + d;
        return 0;
      }
      if ((M_ + p + 64)[d] != 0x00){
        break;
      }
    }
  }
  else if ((mblock % 4) == 2){
    //padding
    DATA1 = _mm256_load_si256((const __m256i*)(_C + p));
    DATA2 = _mm256_load_si256((const __m256i*)(_C + p + 32));

    //tweak update
    __m256i tweak1, tweak2, tweak3, tweak4;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak1 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak3 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak2 = ymmL;
    tweak_update(ymmL, ymmL_H, cnt);
    tweak4 = ymmL;

    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);
    minalpher_core_double_block_inverse(DATA1, DATA2);
    DATA1 = _mm256_xor_si256(DATA1, tweak1);
    DATA2 = _mm256_xor_si256(DATA2, tweak2);

    _mm256_store_si256((__m256i *)(M_ + p), DATA1);
    _mm256_store_si256((__m256i *)(M_ + p + 32), DATA2);

    //Format Verification
    for (int d = BLOCK_SIZE - 1; d >= 0; d--){
      if ((M_ + p + 32)[d] == 0x80){
        *mlen_ += 32 + d;
        return 0;
      }
      if ((M_ + p + 32)[d] != 0x00){
        break;
      }
    }
  }
  else{
    //padding
    DATA1 = _mm256_load_si256((const __m256i*)(_C + p));

    //Encryption
    tweak_update(ymmL, ymmL_H, cnt);
    DATA1 = _mm256_xor_si256(DATA1, ymmL);
    minalpher_core_single_block_inverse(DATA1);
    DATA = _mm256_xor_si256(DATA1, ymmL);
    _mm256_store_si256((__m256i *)(M_ + p), DATA);

    //Format Verification
    for (int d = BLOCK_SIZE - 1; d >= 0; d--){
      if ((M_ + p)[d] == 0x80){
        *mlen_ += d;
        return 0;
      }
      if ((M_ + p)[d] != 0x00){
        break;
      }
    }
  }

  return -1;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
andq $-0x20, %rsp
subq $0x1160, %rsp           # imm = 0x1160
movq %rdi, 0x610(%rsp)
movq %rsi, 0x608(%rsp)
movq %rdx, 0x600(%rsp)
movq %rcx, 0x5f8(%rsp)
movq %r8, 0x5f0(%rsp)
movq %r9, 0x5e8(%rsp)
movl $0x0, 0x4dc(%rsp)
cmpl $0x4, 0x4dc(%rsp)
jge 0x3f9af
vpxor %xmm0, %xmm0, %xmm0
vmovdqa %ymm0, 0x640(%rsp)
vmovdqa 0x640(%rsp), %ymm1
movslq 0x4dc(%rsp), %rax
shlq $0x5, %rax
vmovdqa %ymm1, 0x560(%rsp,%rax)
vmovdqa %ymm0, 0x620(%rsp)
vmovdqa 0x620(%rsp), %ymm0
movslq 0x4dc(%rsp), %rcx
leaq 0x4e0(%rsp), %rax
shlq $0x5, %rcx
addq %rcx, %rax
vmovdqa %ymm0, (%rax)
movl 0x4dc(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x4dc(%rsp)
jmp 0x3f93a
movq 0x5f8(%rsp), %rax
shrq $0x5, %rax
movl %eax, 0x41c(%rsp)
movl $0x0, 0x418(%rsp)
movq 0x610(%rsp), %rsi
movq 0x608(%rsp), %rdx
leaq 0x3e0(%rsp), %rdi
vzeroupper
callq 0x3c570
movl $0x0, 0x3bc(%rsp)
movl $0x0, 0x3bc(%rsp)
movslq 0x3bc(%rsp), %rax
movq 0x5f8(%rsp), %rcx
subq $0x80, %rcx
cmpq %rcx, %rax
jge 0x3ffcb
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movq %rax, 0x6d8(%rsp)
movq 0x6d8(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x480(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
movq %rax, 0x6d0(%rsp)
movq 0x6d0(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x460(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x40, %rax
movq %rax, 0x6c8(%rsp)
movq 0x6c8(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x440(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x60, %rax
movq %rax, 0x6c0(%rsp)
movq 0x6c0(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x420(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x380(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x300(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x360(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x2e0(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x340(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x2c0(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x320(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x2a0(%rsp)
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x380(%rsp), %ymm0
vmovdqa %ymm1, 0xdc0(%rsp)
vmovdqa %ymm0, 0xda0(%rsp)
vmovdqa 0xdc0(%rsp), %ymm0
vpxor 0xda0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x360(%rsp), %ymm0
vmovdqa %ymm1, 0xd80(%rsp)
vmovdqa %ymm0, 0xd60(%rsp)
vmovdqa 0xd80(%rsp), %ymm0
vpxor 0xd60(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
vmovdqa 0x440(%rsp), %ymm1
vmovdqa 0x340(%rsp), %ymm0
vmovdqa %ymm1, 0xd40(%rsp)
vmovdqa %ymm0, 0xd20(%rsp)
vmovdqa 0xd40(%rsp), %ymm0
vpxor 0xd20(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x440(%rsp)
vmovdqa 0x420(%rsp), %ymm1
vmovdqa 0x320(%rsp), %ymm0
vmovdqa %ymm1, 0xd00(%rsp)
vmovdqa %ymm0, 0xce0(%rsp)
vmovdqa 0xd00(%rsp), %ymm0
vpxor 0xce0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x420(%rsp)
leaq 0x480(%rsp), %rdi
leaq 0x460(%rsp), %rsi
leaq 0x440(%rsp), %rdx
leaq 0x420(%rsp), %rcx
vzeroupper
callq 0x2090
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x380(%rsp), %ymm0
vmovdqa %ymm1, 0xcc0(%rsp)
vmovdqa %ymm0, 0xca0(%rsp)
vmovdqa 0xcc0(%rsp), %ymm0
vpxor 0xca0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x360(%rsp), %ymm0
vmovdqa %ymm1, 0xc80(%rsp)
vmovdqa %ymm0, 0xc60(%rsp)
vmovdqa 0xc80(%rsp), %ymm0
vpxor 0xc60(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
vmovdqa 0x440(%rsp), %ymm1
vmovdqa 0x340(%rsp), %ymm0
vmovdqa %ymm1, 0xc40(%rsp)
vmovdqa %ymm0, 0xc20(%rsp)
vmovdqa 0xc40(%rsp), %ymm0
vpxor 0xc20(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x440(%rsp)
vmovdqa 0x420(%rsp), %ymm1
vmovdqa 0x320(%rsp), %ymm0
vmovdqa %ymm1, 0xc00(%rsp)
vmovdqa %ymm0, 0xbe0(%rsp)
vmovdqa 0xc00(%rsp), %ymm0
vpxor 0xbe0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x420(%rsp)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
vmovdqa 0x480(%rsp), %ymm0
movq %rax, 0x1148(%rsp)
vmovdqa %ymm0, 0x1120(%rsp)
vmovdqa 0x1120(%rsp), %ymm0
movq 0x1148(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
vmovdqa 0x460(%rsp), %ymm0
movq %rax, 0x1118(%rsp)
vmovdqa %ymm0, 0x10e0(%rsp)
vmovdqa 0x10e0(%rsp), %ymm0
movq 0x1118(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x40, %rax
vmovdqa 0x440(%rsp), %ymm0
movq %rax, 0x10d8(%rsp)
vmovdqa %ymm0, 0x10a0(%rsp)
vmovdqa 0x10a0(%rsp), %ymm0
movq 0x10d8(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x60, %rax
vmovdqa 0x420(%rsp), %ymm0
movq %rax, 0x1098(%rsp)
vmovdqa %ymm0, 0x1060(%rsp)
vmovdqa 0x1060(%rsp), %ymm0
movq 0x1098(%rsp), %rax
vmovdqa %ymm0, (%rax)
movl 0x3bc(%rsp), %eax
addl $0x80, %eax
movl %eax, 0x3bc(%rsp)
jmp 0x3fa03
movslq 0x3bc(%rsp), %rcx
movq 0x5e8(%rsp), %rax
movq %rcx, (%rax)
movl 0x41c(%rsp), %eax
movl $0x4, %ecx
cltd
idivl %ecx
cmpl $0x0, %edx
jne 0x40635
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movq %rax, 0x6b8(%rsp)
movq 0x6b8(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x480(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
movq %rax, 0x6b0(%rsp)
movq 0x6b0(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x460(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x40, %rax
movq %rax, 0x6a8(%rsp)
movq 0x6a8(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x440(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x60, %rax
movq %rax, 0x6a0(%rsp)
movq 0x6a0(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x420(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x280(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x200(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x260(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x1e0(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x240(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x1c0(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x220(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x1a0(%rsp)
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x280(%rsp), %ymm0
vmovdqa %ymm1, 0xbc0(%rsp)
vmovdqa %ymm0, 0xba0(%rsp)
vmovdqa 0xbc0(%rsp), %ymm0
vpxor 0xba0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x260(%rsp), %ymm0
vmovdqa %ymm1, 0xb80(%rsp)
vmovdqa %ymm0, 0xb60(%rsp)
vmovdqa 0xb80(%rsp), %ymm0
vpxor 0xb60(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
vmovdqa 0x440(%rsp), %ymm1
vmovdqa 0x240(%rsp), %ymm0
vmovdqa %ymm1, 0xb40(%rsp)
vmovdqa %ymm0, 0xb20(%rsp)
vmovdqa 0xb40(%rsp), %ymm0
vpxor 0xb20(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x440(%rsp)
vmovdqa 0x420(%rsp), %ymm1
vmovdqa 0x220(%rsp), %ymm0
vmovdqa %ymm1, 0xb00(%rsp)
vmovdqa %ymm0, 0xae0(%rsp)
vmovdqa 0xb00(%rsp), %ymm0
vpxor 0xae0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x420(%rsp)
leaq 0x480(%rsp), %rdi
leaq 0x460(%rsp), %rsi
leaq 0x440(%rsp), %rdx
leaq 0x420(%rsp), %rcx
vzeroupper
callq 0x2090
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x280(%rsp), %ymm0
vmovdqa %ymm1, 0xac0(%rsp)
vmovdqa %ymm0, 0xaa0(%rsp)
vmovdqa 0xac0(%rsp), %ymm0
vpxor 0xaa0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x260(%rsp), %ymm0
vmovdqa %ymm1, 0xa80(%rsp)
vmovdqa %ymm0, 0xa60(%rsp)
vmovdqa 0xa80(%rsp), %ymm0
vpxor 0xa60(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
vmovdqa 0x440(%rsp), %ymm1
vmovdqa 0x240(%rsp), %ymm0
vmovdqa %ymm1, 0xa40(%rsp)
vmovdqa %ymm0, 0xa20(%rsp)
vmovdqa 0xa40(%rsp), %ymm0
vpxor 0xa20(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x440(%rsp)
vmovdqa 0x420(%rsp), %ymm1
vmovdqa 0x220(%rsp), %ymm0
vmovdqa %ymm1, 0xa00(%rsp)
vmovdqa %ymm0, 0x9e0(%rsp)
vmovdqa 0xa00(%rsp), %ymm0
vpxor 0x9e0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x420(%rsp)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
vmovdqa 0x480(%rsp), %ymm0
movq %rax, 0x1058(%rsp)
vmovdqa %ymm0, 0x1020(%rsp)
vmovdqa 0x1020(%rsp), %ymm0
movq 0x1058(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
vmovdqa 0x460(%rsp), %ymm0
movq %rax, 0x1018(%rsp)
vmovdqa %ymm0, 0xfe0(%rsp)
vmovdqa 0xfe0(%rsp), %ymm0
movq 0x1018(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x40, %rax
vmovdqa 0x440(%rsp), %ymm0
movq %rax, 0xfd8(%rsp)
vmovdqa %ymm0, 0xfa0(%rsp)
vmovdqa 0xfa0(%rsp), %ymm0
movq 0xfd8(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x60, %rax
vmovdqa 0x420(%rsp), %ymm0
movq %rax, 0xf98(%rsp)
vmovdqa %ymm0, 0xf60(%rsp)
vmovdqa 0xf60(%rsp), %ymm0
movq 0xf98(%rsp), %rax
vmovdqa %ymm0, (%rax)
movl $0x1f, 0x19c(%rsp)
cmpl $0x0, 0x19c(%rsp)
jl 0x40630
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0x19c(%rsp), %rcx
movzbl 0x60(%rax,%rcx), %eax
cmpl $0x80, %eax
jne 0x405f1
movl 0x19c(%rsp), %eax
addl $0x60, %eax
movslq %eax, %rcx
movq 0x5e8(%rsp), %rax
addq (%rax), %rcx
movq %rcx, (%rax)
movl $0x0, 0x61c(%rsp)
jmp 0x41048
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0x19c(%rsp), %rcx
movzbl 0x60(%rax,%rcx), %eax
cmpl $0x0, %eax
je 0x40618
jmp 0x40630
jmp 0x4061a
movl 0x19c(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x19c(%rsp)
jmp 0x40591
jmp 0x4103d
movl 0x41c(%rsp), %eax
movl $0x4, %ecx
cltd
idivl %ecx
cmpl $0x3, %edx
jne 0x40b28
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movq %rax, 0x698(%rsp)
movq 0x698(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x480(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
movq %rax, 0x690(%rsp)
movq 0x690(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x460(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x40, %rax
movq %rax, 0x688(%rsp)
movq 0x688(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x440(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x160(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x100(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x140(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0xe0(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x120(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0xc0(%rsp)
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x160(%rsp), %ymm0
vmovdqa %ymm1, 0x9c0(%rsp)
vmovdqa %ymm0, 0x9a0(%rsp)
vmovdqa 0x9c0(%rsp), %ymm0
vpxor 0x9a0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x140(%rsp), %ymm0
vmovdqa %ymm1, 0x980(%rsp)
vmovdqa %ymm0, 0x960(%rsp)
vmovdqa 0x980(%rsp), %ymm0
vpxor 0x960(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
vmovdqa 0x440(%rsp), %ymm1
vmovdqa 0x120(%rsp), %ymm0
vmovdqa %ymm1, 0x940(%rsp)
vmovdqa %ymm0, 0x920(%rsp)
vmovdqa 0x940(%rsp), %ymm0
vpxor 0x920(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x440(%rsp)
leaq 0x480(%rsp), %rdi
leaq 0x460(%rsp), %rsi
leaq 0x440(%rsp), %rdx
vzeroupper
callq 0x21b0
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x160(%rsp), %ymm0
vmovdqa %ymm1, 0x900(%rsp)
vmovdqa %ymm0, 0x8e0(%rsp)
vmovdqa 0x900(%rsp), %ymm0
vpxor 0x8e0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x140(%rsp), %ymm0
vmovdqa %ymm1, 0x8c0(%rsp)
vmovdqa %ymm0, 0x8a0(%rsp)
vmovdqa 0x8c0(%rsp), %ymm0
vpxor 0x8a0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
vmovdqa 0x440(%rsp), %ymm1
vmovdqa 0x120(%rsp), %ymm0
vmovdqa %ymm1, 0x880(%rsp)
vmovdqa %ymm0, 0x860(%rsp)
vmovdqa 0x880(%rsp), %ymm0
vpxor 0x860(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x440(%rsp)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
vmovdqa 0x480(%rsp), %ymm0
movq %rax, 0xf58(%rsp)
vmovdqa %ymm0, 0xf20(%rsp)
vmovdqa 0xf20(%rsp), %ymm0
movq 0xf58(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
vmovdqa 0x460(%rsp), %ymm0
movq %rax, 0xf18(%rsp)
vmovdqa %ymm0, 0xee0(%rsp)
vmovdqa 0xee0(%rsp), %ymm0
movq 0xf18(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x40, %rax
vmovdqa 0x440(%rsp), %ymm0
movq %rax, 0xed8(%rsp)
vmovdqa %ymm0, 0xea0(%rsp)
vmovdqa 0xea0(%rsp), %ymm0
movq 0xed8(%rsp), %rax
vmovdqa %ymm0, (%rax)
movl $0x1f, 0xbc(%rsp)
cmpl $0x0, 0xbc(%rsp)
jl 0x40b23
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0xbc(%rsp), %rcx
movzbl 0x40(%rax,%rcx), %eax
cmpl $0x80, %eax
jne 0x40ae4
movl 0xbc(%rsp), %eax
addl $0x40, %eax
movslq %eax, %rcx
movq 0x5e8(%rsp), %rax
addq (%rax), %rcx
movq %rcx, (%rax)
movl $0x0, 0x61c(%rsp)
jmp 0x41048
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0xbc(%rsp), %rcx
movzbl 0x40(%rax,%rcx), %eax
cmpl $0x0, %eax
je 0x40b0b
jmp 0x40b23
jmp 0x40b0d
movl 0xbc(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0xbc(%rsp)
jmp 0x40a84
jmp 0x4103b
movl 0x41c(%rsp), %eax
movl $0x4, %ecx
cltd
idivl %ecx
cmpl $0x2, %edx
jne 0x40e93
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movq %rax, 0x680(%rsp)
movq 0x680(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x480(%rsp)
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
movq %rax, 0x678(%rsp)
movq 0x678(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x460(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x80(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x40(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x60(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm0, 0x20(%rsp)
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x80(%rsp), %ymm0
vmovdqa %ymm1, 0x840(%rsp)
vmovdqa %ymm0, 0x820(%rsp)
vmovdqa 0x840(%rsp), %ymm0
vpxor 0x820(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x60(%rsp), %ymm0
vmovdqa %ymm1, 0x800(%rsp)
vmovdqa %ymm0, 0x7e0(%rsp)
vmovdqa 0x800(%rsp), %ymm0
vpxor 0x7e0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
leaq 0x480(%rsp), %rdi
leaq 0x460(%rsp), %rsi
vzeroupper
callq 0x2170
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x80(%rsp), %ymm0
vmovdqa %ymm1, 0x7c0(%rsp)
vmovdqa %ymm0, 0x7a0(%rsp)
vmovdqa 0x7c0(%rsp), %ymm0
vpxor 0x7a0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
vmovdqa 0x460(%rsp), %ymm1
vmovdqa 0x60(%rsp), %ymm0
vmovdqa %ymm1, 0x780(%rsp)
vmovdqa %ymm0, 0x760(%rsp)
vmovdqa 0x780(%rsp), %ymm0
vpxor 0x760(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x460(%rsp)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
vmovdqa 0x480(%rsp), %ymm0
movq %rax, 0xe98(%rsp)
vmovdqa %ymm0, 0xe60(%rsp)
vmovdqa 0xe60(%rsp), %ymm0
movq 0xe98(%rsp), %rax
vmovdqa %ymm0, (%rax)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
addq $0x20, %rax
vmovdqa 0x460(%rsp), %ymm0
movq %rax, 0xe58(%rsp)
vmovdqa %ymm0, 0xe20(%rsp)
vmovdqa 0xe20(%rsp), %ymm0
movq 0xe58(%rsp), %rax
vmovdqa %ymm0, (%rax)
movl $0x1f, 0x1c(%rsp)
cmpl $0x0, 0x1c(%rsp)
jl 0x40e8e
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0x1c(%rsp), %rcx
movzbl 0x20(%rax,%rcx), %eax
cmpl $0x80, %eax
jne 0x40e58
movl 0x1c(%rsp), %eax
addl $0x20, %eax
movslq %eax, %rcx
movq 0x5e8(%rsp), %rax
addq (%rax), %rcx
movq %rcx, (%rax)
movl $0x0, 0x61c(%rsp)
jmp 0x41048
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0x1c(%rsp), %rcx
movzbl 0x20(%rax,%rcx), %eax
cmpl $0x0, %eax
je 0x40e7c
jmp 0x40e8e
jmp 0x40e7e
movl 0x1c(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x1c(%rsp)
jmp 0x40e01
jmp 0x41039
movq 0x600(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movq %rax, 0x670(%rsp)
movq 0x670(%rsp), %rax
vmovdqa (%rax), %ymm0
vmovdqa %ymm0, 0x480(%rsp)
leaq 0x3e0(%rsp), %rdi
leaq 0x3c0(%rsp), %rsi
leaq 0x418(%rsp), %rdx
vzeroupper
callq 0x3c2d0
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm1, 0x740(%rsp)
vmovdqa %ymm0, 0x720(%rsp)
vmovdqa 0x740(%rsp), %ymm0
vpxor 0x720(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x480(%rsp)
leaq 0x480(%rsp), %rdi
vzeroupper
callq 0x21c0
vmovdqa 0x480(%rsp), %ymm1
vmovdqa 0x3e0(%rsp), %ymm0
vmovdqa %ymm1, 0x700(%rsp)
vmovdqa %ymm0, 0x6e0(%rsp)
vmovdqa 0x700(%rsp), %ymm0
vpxor 0x6e0(%rsp), %ymm0, %ymm0
vmovdqa %ymm0, 0x4a0(%rsp)
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
vmovdqa 0x4a0(%rsp), %ymm0
movq %rax, 0xe18(%rsp)
vmovdqa %ymm0, 0xde0(%rsp)
vmovdqa 0xde0(%rsp), %ymm0
movq 0xe18(%rsp), %rax
vmovdqa %ymm0, (%rax)
movl $0x1f, 0x18(%rsp)
cmpl $0x0, 0x18(%rsp)
jl 0x41037
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0x18(%rsp), %rcx
movzbl (%rax,%rcx), %eax
cmpl $0x80, %eax
jne 0x41005
movslq 0x18(%rsp), %rcx
movq 0x5e8(%rsp), %rax
addq (%rax), %rcx
movq %rcx, (%rax)
movl $0x0, 0x61c(%rsp)
jmp 0x41048
movq 0x5f0(%rsp), %rax
movslq 0x3bc(%rsp), %rcx
addq %rcx, %rax
movslq 0x18(%rsp), %rcx
movzbl (%rax,%rcx), %eax
cmpl $0x0, %eax
je 0x41028
jmp 0x41037
jmp 0x4102a
movl 0x18(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x18(%rsp)
jmp 0x40fbb
jmp 0x41039
jmp 0x4103b
jmp 0x4103d
movl $0xffffffff, 0x61c(%rsp) # imm = 0xFFFFFFFF
movl 0x61c(%rsp), %eax
movq %rbp, %rsp
popq %rbp
vzeroupper
retq
nopw (%rax,%rax)