// File: /workspace/github_cpp_makefile_star2_O1/CMU-SAFARI[P]MQSim/src/ssd/TSU_Priority_OutOfOrder.cpp
// Function: SSD_Components::TSU_Priority_OutOfOrder::service_read_transaction(NVM::FlashMemory::Flash_Chip*)
bool TSU_Priority_OutOfOrder::service_read_transaction(NVM::FlashMemory::Flash_Chip *chip)
{
    Flash_Transaction_Queue *sourceQueue1 = NULL, *sourceQueue2 = NULL;

    //Flash transactions that are related to FTL mapping data have the highest priority
    if (MappingReadTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
    {
        sourceQueue1 = &MappingReadTRQueue[chip->ChannelID][chip->ChipID];
        if (ftl->GC_and_WL_Unit->GC_is_in_urgent_mode(chip) && GCReadTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue2 = &GCReadTRQueue[chip->ChannelID][chip->ChipID];
        }
        else
        {
            sourceQueue2 = get_next_read_service_queue(chip);
        }
    }
    else if (ftl->GC_and_WL_Unit->GC_is_in_urgent_mode(chip))
    {
        //If flash transactions related to GC are prioritzed (non-preemptive execution mode of GC), then GC queues are checked first
        if (GCReadTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue1 = &GCReadTRQueue[chip->ChannelID][chip->ChipID];
            sourceQueue2 = get_next_read_service_queue(chip);
        }
        else if (GCWriteTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            return false;
        }
        else if (GCEraseTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            return false;
        }
        else
        {
            sourceQueue1 = get_next_read_service_queue(chip);
            if (sourceQueue1 == NULL)
            {
                return false;
            }
        }
    }
    else
    {
        //If GC is currently executed in the preemptive mode, then user IO transaction queues are checked first
        sourceQueue1 = get_next_read_service_queue(chip);
        if (sourceQueue1 != NULL)
        {
            if (GCReadTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
            {
                sourceQueue2 = &GCReadTRQueue[chip->ChannelID][chip->ChipID];
            }
        }
        else if (get_next_write_service_queue(chip) != NULL)
        {
            return false;
        }
        else if (GCReadTRQueue[chip->ChannelID][chip->ChipID].size() > 0)
        {
            sourceQueue1 = &GCReadTRQueue[chip->ChannelID][chip->ChipID];
        }
        else
        {
            return false;
        }
    }

    bool suspensionRequired = false;
    ChipStatus cs = _NVMController->GetChipStatus(chip);
    switch (cs)
    {
    case ChipStatus::IDLE:
        break;
    case ChipStatus::WRITING:
        if (!programSuspensionEnabled || _NVMController->HasSuspendedCommand(chip))
        {
            return false;
        }
        if (_NVMController->Expected_finish_time(chip) - Simulator->Time() < writeReasonableSuspensionTimeForRead)
        {
            return false;
        }
        suspensionRequired = true;
    case ChipStatus::ERASING:
        if (!eraseSuspensionEnabled || _NVMController->HasSuspendedCommand(chip))
        {
            return false;
        }
        if (_NVMController->Expected_finish_time(chip) - Simulator->Time() < eraseReasonableSuspensionTimeForRead)
        {
            return false;
        }
        suspensionRequired = true;
    default:
        return false;
    }

    issue_command_to_chip(sourceQueue1, sourceQueue2, Transaction_Type::READ, suspensionRequired);

    return true;
}

// Assembly:
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0xd8(%rdi), %rax
movl 0x2c(%rsi), %ecx
movl 0x30(%rsi), %edx
movq (%rax,%rcx,8), %r15
movq %rdx, %rax
shlq $0x8, %rax
leaq (%rax,%rdx,8), %rax
cmpq $0x0, 0x18(%r15,%rax)
je 0x51cc9
addq %rax, %r15
movq 0x30(%r14), %rax
movq 0x48(%rax), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x20(%rax)
testb %al, %al
je 0x51d0d
movq 0xc0(%r14), %rax
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
movq (%rax,%rcx,8), %r12
movq %rdx, %rax
shlq $0x8, %rax
leaq (%rax,%rdx,8), %rax
cmpq $0x0, 0x18(%r12,%rax)
je 0x51d0d
addq %rax, %r12
jmp 0x51d1b
movq 0x30(%r14), %rax
movq 0x48(%rax), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x20(%rax)
testb %al, %al
je 0x51de2
movq 0xc0(%r14), %rcx
movl 0x2c(%rbx), %eax
movl 0x30(%rbx), %edx
movq (%rcx,%rax,8), %r15
movq %rdx, %rcx
shlq $0x8, %rcx
leaq (%rcx,%rdx,8), %rcx
cmpq $0x0, 0x18(%r15,%rcx)
je 0x51e26
addq %rcx, %r15
movq %r14, %rdi
movq %rbx, %rsi
callq 0x51b42
movq %rax, %r12
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x48(%rax)
testl %eax, %eax
je 0x51dc7
cmpl $0x6, %eax
je 0x51d88
cmpl $0x5, %eax
jne 0x51e77
cmpb $0x1, 0x55(%r14)
jne 0x51e77
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x40(%rax)
testb %al, %al
jne 0x51e77
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x50(%rax)
movq %rax, %r15
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
subq %rax, %r15
cmpq 0x58(%r14), %r15
jb 0x51e77
cmpb $0x1, 0x54(%r14)
jne 0x51e77
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x40(%rax)
testb %al, %al
jne 0x51e77
movq 0x38(%r14), %rdi
movq (%rdi), %rax
movq %rbx, %rsi
callq *0x50(%rax)
callq 0x281b4
movq %rax, %rdi
callq 0x285a6
jmp 0x51e77
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq 0x4b192
movb $0x1, %r12b
jmp 0x51e7a
movq %r14, %rdi
movq %rbx, %rsi
callq 0x51b42
testq %rax, %rax
je 0x51e67
movq %rax, %r15
movq 0xc0(%r14), %rax
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
movq (%rax,%rcx,8), %rax
movq %rdx, %rcx
shlq $0x8, %rcx
leaq (%rcx,%rdx,8), %rcx
leaq (%rax,%rcx), %r12
movq 0x18(%rax,%rcx), %rax
testq %rax, %rax
cmoveq %rax, %r12
jmp 0x51d1b
movq 0xc8(%r14), %rdx
movq (%rdx,%rax,8), %rdx
cmpq $0x0, 0x18(%rdx,%rcx)
jne 0x51e77
movq 0xd0(%r14), %rdx
movq (%rdx,%rax,8), %rax
cmpq $0x0, 0x18(%rax,%rcx)
jne 0x51e77
movq %r14, %rdi
movq %rbx, %rsi
callq 0x51b42
xorl %r12d, %r12d
testq %rax, %rax
je 0x51e7a
movq %rax, %r15
jmp 0x51d1b
movq %r14, %rdi
movq %rbx, %rsi
callq 0x51eb8
testq %rax, %rax
je 0x51e89
xorl %r12d, %r12d
movl %r12d, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
movq 0xc0(%r14), %rax
movl 0x2c(%rbx), %ecx
movl 0x30(%rbx), %edx
movq (%rax,%rcx,8), %r15
movq %rdx, %rax
shlq $0x8, %rax
leaq (%rax,%rdx,8), %rax
cmpq $0x0, 0x18(%r15,%rax)
je 0x51e77
addq %rax, %r15
xorl %r12d, %r12d
jmp 0x51d1b