// File: /workspace/github_cpp_makefile_star2_O1/gvaumour[P]cache-simulator/src/FeatureTable.cc
// Function: FeatureEntry::updateDatasetState()
void 
FeatureEntry::updateDatasetState()
{
	
	CostFunctionParameters params = simu_parameters.optTarget;
	int E_SRAM = 0 , E_NVM = 0;
	
	if(simu_parameters.Cerebron_RDmodel)
	{
		E_SRAM = SRAM_seq[WRITE_ACCESS][false] * (params.costDRAM[WRITE_ACCESS] + params.costSRAM[WRITE_ACCESS]) +\
			 SRAM_seq[WRITE_ACCESS][true] * (params.costSRAM[WRITE_ACCESS]) +\
			 SRAM_seq[READ_ACCESS][false] * (params.costDRAM[READ_ACCESS] + params.costSRAM[READ_ACCESS]) +\
			 SRAM_seq[READ_ACCESS][true] * (params.costSRAM[READ_ACCESS]);

		E_NVM = NVM_seq[WRITE_ACCESS][false] * (params.costDRAM[WRITE_ACCESS] + params.costNVM[WRITE_ACCESS]) +\
			 NVM_seq[WRITE_ACCESS][true] * (params.costNVM[WRITE_ACCESS]) +\
			 NVM_seq[READ_ACCESS][false] * (params.costDRAM[READ_ACCESS] + params.costNVM[READ_ACCESS]) +\
			 NVM_seq[READ_ACCESS][true] * (params.costNVM[READ_ACCESS]);
	}
	else
	{
		E_SRAM =(params.costDRAM[READ_ACCESS] + params.costSRAM[READ_ACCESS])* \
				(cpts[READ_ACCESS][RD_NOT_ACCURATE]) + \
			(params.costDRAM[WRITE_ACCESS] + params.costSRAM[WRITE_ACCESS])* \
				(cpts[WRITE_ACCESS][RD_NOT_ACCURATE]) + \
			 params.costDRAM[READ_ACCESS] * cpts[READ_ACCESS][RD_MEDIUM] + \
		         params.costDRAM[WRITE_ACCESS] * cpts[WRITE_ACCESS][RD_MEDIUM] + \
			 params.costSRAM[READ_ACCESS] * cpts[READ_ACCESS][RD_SHORT] + \
			 params.costSRAM[WRITE_ACCESS] * cpts[WRITE_ACCESS][RD_SHORT];	

		E_NVM = (params.costDRAM[READ_ACCESS] + params.costNVM[READ_ACCESS])* \
				(cpts[READ_ACCESS][RD_NOT_ACCURATE]) + \
			(params.costDRAM[WRITE_ACCESS] + params.costNVM[WRITE_ACCESS])* \
				(cpts[WRITE_ACCESS][RD_NOT_ACCURATE]) + \
			       params.costNVM[READ_ACCESS] *  ( cpts[READ_ACCESS][RD_MEDIUM] + cpts[READ_ACCESS][RD_SHORT]) + \
			       params.costNVM[WRITE_ACCESS] * ( cpts[WRITE_ACCESS][RD_MEDIUM] + cpts[WRITE_ACCESS][RD_SHORT]);	
	}

	if(E_SRAM > E_NVM)
		des = ALLOCATE_IN_NVM;
	else
		des = ALLOCATE_IN_SRAM;
		
		
	cpts = vector< vector<int> >(NUM_RW_TYPE, vector<int>(NUM_RD_TYPE, 0));
	cptWindow = 0;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0xa8, %rsp
movq %rdi, %rbx
leaq 0x32029(%rip), %r14     # 0x45f50
leaq 0xe8(%r14), %rsi
leaq 0x28(%rsp), %rdi
callq 0xcde4
leaq 0x40(%rsp), %rdi
leaq 0x100(%r14), %rsi
callq 0xcde4
leaq 0x58(%rsp), %rdi
movl $0x118, %esi            # imm = 0x118
addq 0x31046(%rip), %rsi     # 0x44fa0
callq 0xcde4
cmpb $0x1, 0x226(%r14)
jne 0x13fe6
movq 0x18(%rbx), %rax
movq 0x30(%rbx), %rsi
movq (%rax), %rdi
movq 0x18(%rax), %r8
movq 0x58(%rsp), %rax
movl (%rax), %ecx
movl 0x4(%rax), %edx
movq 0x28(%rsp), %r9
movq 0x40(%rsp), %rax
movl 0x4(%rax), %r10d
leal (%r10,%rdx), %r11d
imull (%r8), %r11d
movl (%rax), %eax
imull 0x4(%r8), %r10d
leal (%rax,%rcx), %r8d
imull (%rdi), %r8d
imull 0x4(%rdi), %eax
addl %r11d, %r10d
addl %r8d, %eax
addl %r10d, %eax
movq (%rsi), %rdi
movq 0x18(%rsi), %rsi
movl (%r9), %r11d
movl 0x4(%r9), %r8d
addl %r8d, %edx
imull (%rsi), %edx
imull 0x4(%rsi), %r8d
addl %edx, %r8d
addl %r11d, %ecx
imull (%rdi), %ecx
imull 0x4(%rdi), %r11d
addl %ecx, %r11d
addl %r8d, %r11d
jmp 0x14079
movq 0x58(%rsp), %rax
movq 0x28(%rsp), %rsi
movq 0x40(%rsp), %r8
movl (%rax), %edx
movl 0x4(%rax), %ecx
movl (%r8), %edi
movl 0x4(%r8), %eax
leal (%rdi,%rdx), %r9d
movq (%rbx), %r8
movq (%r8), %r11
movq 0x18(%r8), %r14
movl 0x8(%r11), %r8d
imull %r8d, %r9d
leal (%rax,%rcx), %ebp
movl 0x8(%r14), %r10d
imull %r10d, %ebp
addl %r9d, %ebp
movl (%r11), %r9d
movl 0x4(%r11), %r11d
imull %r9d, %edi
addl %r11d, %r9d
movl %r11d, %r15d
imull %edx, %r15d
movl (%r14), %r11d
movl 0x4(%r14), %r14d
imull %r11d, %eax
addl %r14d, %r11d
imull %ecx, %r14d
addl %r15d, %r14d
addl %ebp, %r14d
addl %edi, %eax
addl %r14d, %eax
movl (%rsi), %edi
movl 0x4(%rsi), %esi
addl %edi, %edx
imull %r8d, %edx
addl %esi, %ecx
imull %r10d, %ecx
imull %edi, %r9d
addl %edx, %r9d
imull %esi, %r11d
addl %ecx, %r11d
addl %r9d, %r11d
xorl %ecx, %ecx
cmpl %r11d, %eax
setg %cl
movl %ecx, 0x58(%rbx)
xorps %xmm0, %xmm0
movaps %xmm0, 0x10(%rsp)
movq $0x0, 0x20(%rsp)
movl $0xc, %edi
callq 0x52e0
leaq 0x10(%rsp), %rdx
movq %rax, (%rdx)
movq %rax, 0x8(%rdx)
movq %rax, %rcx
addq $0xc, %rcx
movq %rcx, 0x10(%rdx)
movl $0x0, 0x8(%rax)
movq $0x0, (%rax)
movq %rcx, 0x8(%rdx)
leaq 0x70(%rsp), %rdi
leaq 0xf(%rsp), %rcx
movl $0x5, %esi
callq 0xc5b2
xorps %xmm0, %xmm0
leaq 0x90(%rsp), %rdi
movaps %xmm0, (%rdi)
movq $0x0, 0x10(%rdi)
movups (%rbx), %xmm0
movq 0x10(%rbx), %rax
leaq 0x70(%rsp), %r14
movaps (%r14), %xmm1
movups %xmm1, (%rbx)
movq 0x10(%r14), %rcx
movq %rcx, 0x10(%rbx)
movq 0x10(%rdi), %rcx
movq %rax, 0x10(%rdi)
movaps (%rdi), %xmm1
movaps %xmm0, (%rdi)
movaps %xmm1, (%r14)
movq %rcx, 0x10(%r14)
callq 0xc642
movq %r14, %rdi
callq 0xc642
movq 0x10(%rsp), %rdi
testq %rdi, %rdi
je 0x1413f
callq 0x52a0
movl $0x0, 0x48(%rbx)
movq 0x58(%rsp), %rdi
testq %rdi, %rdi
je 0x14155
callq 0x52a0
movq 0x40(%rsp), %rdi
testq %rdi, %rdi
je 0x14164
callq 0x52a0
movq 0x28(%rsp), %rdi
testq %rdi, %rdi
je 0x14173
callq 0x52a0
addq $0xa8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rax, %rbx
movq 0x10(%rsp), %rdi
testq %rdi, %rdi
je 0x14198
callq 0x52a0
jmp 0x14198
movq %rax, %rbx
leaq 0x28(%rsp), %rdi
callq 0xc800
jmp 0x141ca
movq %rax, %rbx
movq 0x40(%rsp), %rdi
testq %rdi, %rdi
je 0x141bb
callq 0x52a0
jmp 0x141bb
movq %rax, %rbx
movq 0x28(%rsp), %rdi
testq %rdi, %rdi
je 0x141ca
callq 0x52a0
movq %rbx, %rdi
callq 0x55a0