// File: /workspace/github_c_makefile_star2_O0/Ihsoh[P]ilang/compiler/assembler/ins_enc.c
// Function: ins_enc_xchg_rAX_XXX
void ins_enc_xchg_rAX_XXX(
	Instruction *ins,
	InstructionEncoderData *data
) {
	_CHECK_PARAMS(2);

	ParserASTNode *ins_node = data->ins_node;

	ParserASTNode *target = data->ins_node->childs[0];

	ParserASTNode *source = data->ins_node->childs[1];

	ins_check_operand_type(data->ctx, ins, target, source, NULL);

	EncoderInstruction enc_ins;

	ins_init(data->ctx, ins, ins_node, &enc_ins);

	InsRegister *ins_reg_target = ASM_REG_AST_NODE_GET_REG(target);
	InsRegister *ins_reg_source = ASM_REG_AST_NODE_GET_REG(source);
	InsRegister *ins_reg_another = NULL;
	if (ins_reg_target->index == INS_REGISTER_INDEX_AX) {
		ins_reg_another = ins_reg_source;
	} else {
		ins_reg_another = ins_reg_target;
	}

	int arch = ASM_PARSER_CONTEXT_DATA_GET_ARCH(data->ctx);

	switch (arch) {
		case ASM_ARCH_BIT16: {
			if (!(ins_reg_another->arch & ASM_ARCH_BIT16)) {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 16-bit mode."
				);
			}

			if (ins_reg_another->type == INS_REGISTER_GENERAL_2BYTE) {

			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_4BYTE) {
				enc_ins.legacy_prefix.operand_size_override = true;
			} else {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 16-bit mode."
				);
			}
			break;
		}
		case ASM_ARCH_BIT32: {
			if (!(ins_reg_another->arch & ASM_ARCH_BIT32)) {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 32-bit mode."
				);
			}

			if (ins_reg_another->type == INS_REGISTER_GENERAL_2BYTE) {
				enc_ins.legacy_prefix.operand_size_override = true;
			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_4BYTE) {

			} else {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 32-bit mode."
				);
			}
			break;
		}
		case ASM_ARCH_BIT64: {
			if (!(ins_reg_another->arch & ASM_ARCH_BIT64)) {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 64-bit mode."
				);
			}

			if (ins_reg_another->index & 0x08) {
				enc_ins.rex_prefix_used = true;
				enc_ins.rex_prefix.r = true;
			}

			if (ins_reg_another->type == INS_REGISTER_GENERAL_2BYTE) {
				enc_ins.legacy_prefix.operand_size_override = true;
			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_4BYTE) {

			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_8BYTE) {
				
			} else {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 64-bit mode."
				);
			}
			break;
		}
		default: {
			assert(0);
			break;
		}
	}

	_output(data, &enc_ins);
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0xb0, %rsp
movq %rdi, -0x8(%rbp)
movq %rsi, -0x10(%rbp)
cmpq $0x0, -0x8(%rbp)
je 0x2063c
jmp 0x2065b
leaq 0x294c3(%rip), %rdi     # 0x49b06
leaq 0x2a9d6(%rip), %rsi     # 0x4b020
movl $0x2ec, %edx            # imm = 0x2EC
leaq 0x2af9e(%rip), %rcx     # 0x4b5f4
callq 0xa0b0
cmpq $0x0, -0x10(%rbp)
je 0x20664
jmp 0x20683
leaq 0x2f984(%rip), %rdi     # 0x4ffef
leaq 0x2a9ae(%rip), %rsi     # 0x4b020
movl $0x2ec, %edx            # imm = 0x2EC
leaq 0x2af76(%rip), %rcx     # 0x4b5f4
callq 0xa0b0
movq -0x10(%rbp), %rax
cmpq $0x0, (%rax)
je 0x2068f
jmp 0x206ae
leaq 0x2a9e7(%rip), %rdi     # 0x4b07d
leaq 0x2a983(%rip), %rsi     # 0x4b020
movl $0x2ec, %edx            # imm = 0x2EC
leaq 0x2af4b(%rip), %rcx     # 0x4b5f4
callq 0xa0b0
movq -0x10(%rbp), %rax
movq (%rax), %rax
cmpl $0x2, 0x44(%rax)
jne 0x206bd
jmp 0x206dc
leaq 0x2a9c8(%rip), %rdi     # 0x4b08c
leaq 0x2a955(%rip), %rsi     # 0x4b020
movl $0x2ec, %edx            # imm = 0x2EC
leaq 0x2af1d(%rip), %rcx     # 0x4b5f4
callq 0xa0b0
movq -0x10(%rbp), %rax
movq (%rax), %rax
movq %rax, -0x18(%rbp)
movq -0x10(%rbp), %rax
movq (%rax), %rax
movq 0x48(%rax), %rax
movq (%rax), %rax
movq %rax, -0x20(%rbp)
movq -0x10(%rbp), %rax
movq (%rax), %rax
movq 0x48(%rax), %rax
movq 0x8(%rax), %rax
movq %rax, -0x28(%rbp)
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rdi
movq -0x8(%rbp), %rsi
movq -0x20(%rbp), %rdx
movq -0x28(%rbp), %rcx
xorl %eax, %eax
movl %eax, %r8d
callq 0x1c600
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rdi
movq -0x8(%rbp), %rsi
movq -0x18(%rbp), %rdx
leaq -0x88(%rbp), %rcx
callq 0x1a9e0
movq -0x20(%rbp), %rax
movq 0x60(%rax), %rax
movq %rax, -0x90(%rbp)
movq -0x28(%rbp), %rax
movq 0x60(%rax), %rax
movq %rax, -0x98(%rbp)
movq $0x0, -0xa0(%rbp)
movq -0x90(%rbp), %rax
cmpl $0x0, 0x10(%rax)
jne 0x2078c
movq -0x98(%rbp), %rax
movq %rax, -0xa0(%rbp)
jmp 0x2079a
movq -0x90(%rbp), %rax
movq %rax, -0xa0(%rbp)
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movl 0xb0(%rax), %eax
movl %eax, -0xa4(%rbp)
movl -0xa4(%rbp), %eax
movl %eax, -0xa8(%rbp)
subl $0x1, %eax
je 0x207e6
jmp 0x207c1
movl -0xa8(%rbp), %eax
subl $0x2, %eax
je 0x20863
jmp 0x207d2
movl -0xa8(%rbp), %eax
subl $0x4, %eax
je 0x208e0
jmp 0x20985
movq -0xa0(%rbp), %rax
movl 0x14(%rax), %eax
andl $0x1, %eax
cmpl $0x0, %eax
jne 0x20819
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2aa15(%rip), %rdx     # 0x4b22c
callq *%rax
movq -0xa0(%rbp), %rax
cmpl $0x3, 0xc(%rax)
jne 0x20828
jmp 0x2085e
movq -0xa0(%rbp), %rax
cmpl $0x4, 0xc(%rax)
jne 0x2083b
movb $0x1, -0x7d(%rbp)
jmp 0x2085c
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2a9d2(%rip), %rdx     # 0x4b22c
callq *%rax
jmp 0x2085e
jmp 0x209a4
movq -0xa0(%rbp), %rax
movl 0x14(%rax), %eax
andl $0x2, %eax
cmpl $0x0, %eax
jne 0x20896
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2a9c2(%rip), %rdx     # 0x4b256
callq *%rax
movq -0xa0(%rbp), %rax
cmpl $0x3, 0xc(%rax)
jne 0x208a9
movb $0x1, -0x7d(%rbp)
jmp 0x208db
movq -0xa0(%rbp), %rax
cmpl $0x4, 0xc(%rax)
jne 0x208b8
jmp 0x208d9
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2a97f(%rip), %rdx     # 0x4b256
callq *%rax
jmp 0x208db
jmp 0x209a4
movq -0xa0(%rbp), %rax
movl 0x14(%rax), %eax
andl $0x4, %eax
cmpl $0x0, %eax
jne 0x20913
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2aa4d(%rip), %rdx     # 0x4b35e
callq *%rax
movq -0xa0(%rbp), %rax
movl 0x10(%rax), %eax
andl $0x8, %eax
cmpl $0x0, %eax
je 0x2092d
movb $0x1, -0x7b(%rbp)
movb $0x1, -0x79(%rbp)
movq -0xa0(%rbp), %rax
cmpl $0x3, 0xc(%rax)
jne 0x20940
movb $0x1, -0x7d(%rbp)
jmp 0x20983
movq -0xa0(%rbp), %rax
cmpl $0x4, 0xc(%rax)
jne 0x2094f
jmp 0x20981
movq -0xa0(%rbp), %rax
cmpl $0x5, 0xc(%rax)
jne 0x2095e
jmp 0x2097f
movq -0x10(%rbp), %rax
movq 0x8(%rax), %rax
movq 0x58(%rax), %rax
movq -0x10(%rbp), %rcx
movq 0x8(%rcx), %rdi
movq -0x18(%rbp), %rsi
leaq 0x2a9e1(%rip), %rdx     # 0x4b35e
callq *%rax
jmp 0x20981
jmp 0x20983
jmp 0x209a4
leaq 0x26ad9(%rip), %rdi     # 0x47465
leaq 0x2a68d(%rip), %rsi     # 0x4b020
movl $0x350, %edx            # imm = 0x350
leaq 0x2ac55(%rip), %rcx     # 0x4b5f4
callq 0xa0b0
movq -0x10(%rbp), %rdi
leaq -0x88(%rbp), %rsi
callq 0x1e570
addq $0xb0, %rsp
popq %rbp
retq
nopl (%rax)