// File: /workspace/github_cpp_makefile_star2_O1/akshayrajput[P]ARMV8_Simulator/simulo.cpp
// Function: decode()
void decode()
{

    NIO = 4;
    int sf = (IR.getLowerData() & SF_MASK)>>31;
    int type_inst = (IR.getLowerData() & TYPE_MASK) >>25;//instruction group
    int sw = 0;
    
    if(type_inst == 8 || type_inst == 9)  //operand data processing immediate
    {
	    if(skip)
	{ 
	   printf("[log]- Skipping instruction\n"); 
	   return;
	}
	sw = 0;
	
        int inst = (IR.getData() & INST_IMM_TYPE) >> 23;

        if(inst == 0 || inst == 1) // PC relative addressing
        {
		//ADR , ADRP
            printf("[log] - PC relative\n");
	    if(sf == 1)
	    {
		    printf("[log]- ADRP\n");
		    ADR();
	    }
	    else
	    {
		    printf("[log] - ADR\n");
		    ADR();
	    }
        }
        else if(inst == 2 || inst == 3) // Add or subtract
        {
		int opc = (IR.getLowerData() & 0x60000000)>>29;//op + S
		int op1 = IR.getLowerData() & 0x0000001f ;//Rd
		int op2 = (IR.getLowerData() & 0x000003e0) >> 5 ;//Rn
		int op3 = (IR.getLowerData() & 0x003ffc00)>>10;//imm10
		if(opc == 0)
		{
			
			ADD(sf,sw,op1,op2,op3);
		}
		else if(opc == 1)
		{
			//TODO - adds
			ADDS();
		}
		else if(opc == 2)
		{
			
			SUB(sf,sw,op1,op2,op3);
			
		}
		else if(opc == 3)
		{
			//TODO - subs
			ADDS();
		}
        }
        
        else if(inst == 4)  //Logical 
        {
       		//only AND 
		int op1 = IR.getLowerData() & 0x0000001f ;//Rd
		int op2 = (IR.getLowerData() & 0x000003e0) >> 5 ;//Rn
		int op3 = (IR.getLowerData() & 0x04000000) >> 22;//N
		int op4 = (IR.getLowerData() & 0x0000fc00 ) >> 10 ;//imms
		int op5 = (IR.getLowerData() & 0x003f0000)>>16;//immr

		AND(sf,sw,op1,op2,0,op3,op4,op5);
        }
        
        else if(inst == 5)  //Move wide
        {
		printf("[log] - move instruction\n");
		int op1 = IR.getLowerData() & 0x0000001f ;//Rd
		int op2 = (IR.getLowerData() & 0x001fffe0 )>> 5; //imm16
		MOV(sf, sw,op1,op2);
       		 
        }
        
        else if(inst == 6)  //Bit field
        {

		printf("[log] - lsr|lsl|asr instruction\n");
		int opc = (IR.getLowerData() & 0x60000000)>>29;//op + S
		int op1 = IR.getLowerData() & 0x0000001f ;//Rd
		int op2 = (IR.getLowerData() & 0x000003e0) >> 5 ;//Rn
		int op3 = (IR.getLowerData() & 0x04000000) >> 22;//N
		int op4 = (IR.getLowerData() & 0x0000fc00 ) >> 10 ;//imms
		int op5 = (IR.getLowerData() & 0x003f0000)>>16;//immr

		if(opc == 0)
		{
			ASR(sf,sw,op1,op2,op5);
		}

		else if(opc == 2)
		{
			if(op4  == 31 || op4 == 63 )
			{
				printf("[log] - lsr instruction\n");
			 	LSR(sf,sw,op1,op2,op5);

			}

			else
			{
			 	printf("[log] - lsl instruction");
				LSL(sf,sw,op1,op2,op5);

			} 
		}
        }
        
        else if (inst == 7) //Extract
        {
        
        }
        
    }
    
    else if (type_inst == 5 || type_inst == 13)  //operand data processing register
    { 
	    if(skip)
	{ 
	   printf("[log]- Skipping instruction\n"); 
	   return;
	}
	sw  = 1;
        int inst = (IR.getLowerData() & INST_REG_TYPE)>>21;

        if(inst >= 80 && inst <=87)
        {
	   int opc = (IR.getLowerData() & 0x60000000)>>29;//opc
	   int op1 = IR.getLowerData() & 0x0000001f ;//Rd
	   int op2 = (IR.getLowerData() & 0x000003e0) >> 5 ;//Rn
	   int op3 = (IR.getLowerData() & 0x001f0000)>>16; //Rm
	   int op4 = (IR.getLowerData() & 0x0000fc00)>>10;//imm6


            printf("[log] - Logical shifted register instruction\n");

	    if(opc == 0)
	    {
		    printf("[log]- AND instruction\n");
		    AND(sf,sw,op1,op2,op3,0,0,0);
	    }
	    else if(opc == 1)
	    {
		    printf("[log]- MOV instruction\n");
		    MOV(sf, sw,op1,op3);

	    }


        }
        
        else if(inst == 88 || inst == 90 || inst == 92 || inst == 94)
        {
            printf("[log] - Add/ sub shifted register instruction\n");
		int opc = (IR.getLowerData() & 0x60000000)>>29;//op + S
		int op1 = IR.getLowerData() & 0x0000001f ;//Rd
		int op2 = (IR.getLowerData() & 0x000003e0) >> 5 ;//Rn
		int op3 = (IR.getLowerData() & 0x001f0000)>>16; //Rm
		int op4 = (IR.getLowerData() & 0x0000fc00)>>10;//imm6
		if(opc == 0)
		{
			// TODO - add
			ADD(sf,sw,op1,op2,op3);

		}
		else if(opc == 1)
		{
			//TODO - adds
			ADDS();
		}
		else if(opc == 2)
		{
			//TODO - sub
			SUB(sf,sw,op1,op2,op3);
		}
		else if(opc == 3)
		{
			//TODO - subs
			ADDS();
		}

        }
        
        else if(inst == 89 || inst == 91 || inst == 93 || inst == 95)
        {
            printf("[log] - Add/ sub extended register instruction\n");
        }
        
        else if(inst == 208)
        {
            printf("[log ] - Add/ sub with instruction\n");
        }
        
        else if(inst == 210)
        {
            printf("[log ] - condition compare register or immediate instruction\n");
        }
        
        else if(inst == 212)
        {
            printf("[log] - condition select instruction\n");
        }
        
          
    }

    else if (type_inst == 10 || type_inst == 11) // branch instructions 
  {

	 int inst = (IR.getLowerData() & INST_B_TYPE)>>25;

	 if(inst  == 10 || inst == 11)//unconditional branch
	 {
		if(skip)
		{ 
		   printf("[log]- Skipping instruction\n"); 
		   return;
		}
		 int op  = sf;//opcode for unconditional types
		 int64_t imm = IR.getLowerData()&0x03ffffff;
		 imm = signExtend(imm,25);
		 uint64_t offset = ((imm-1)*4) + PC.getData();
		 NIO = offset - PC.getData();
		 BBL(op,offset);
	 }
	 else if(inst == 42)
	 {
		 //conditional branch
		if(skip)
		{	 
	 	  printf("[log]- Skipping instruction\n"); 
	 	  return;
		}	

		if(sf ==1)
		{
			NOP();
			return;
		}

		int64_t imm = (IR.getLowerData()&0x00ffffe0)>>5;
		imm = signExtend(imm,25);
		int cond = IR.getLowerData()&0x0000000f;
			
		uint64_t offset = ((imm-1)*4)+PC.getData();//FIXME - take BR.getData() and imm*4 instead
		NIO = offset - PC.getData();
		BCOND(offset,cond);	

	 }
	 else if(inst == 43)
	 {
		 //unconditional branch register
		 int op = (IR.getLowerData() & 0x00600000)>>21;
		 int RN = (IR.getLowerData() & 0x000003e0)>>5;
		 if(op == 1 || op == 0)
		{
			//unconditional call register
		if(skip)
			{	 
	 		  printf("[log]- Skipping instruction\n"); 
	 		  return;
			}	

			BBRL(op,RN);

		}
		else if(op ==2)
		{
		
			//unconditional ret
			RN = 30;
			RET(RN);

		}
	 }
	 else if(inst == 26)
	 {
		if(skip)
			{	 
	 		  printf("[log]- Skipping instruction\n"); 
	 		  return;
			}
				
		//compare and branch immediate
		int op  = (IR.getLowerData() & 0x01000000)>>24;//opcode
		 int64_t imm = (IR.getLowerData()&0x00ffffe0)>>5;
		 imm = signExtend(imm,25);
		 int RT = IR.getLowerData()&0x0000001f ;
		 uint64_t offset = ((imm-1)*4)+PC.getData();//FIXME - use imm and BR.getData()
		 assert(RT >=0 && RT <= 31);

		 NIO = offset - PC.getData();
		 CBZNZ(sf,op,RT,offset);

	 }

  }
  else //load / store
  {
	int inst = (IR.getLowerData() & 0x10000000)>>28;

	  if(skip)
		{	 
	 		  printf("[log]- Skipping instruction\n"); 
	 		  return;
		}	
	
	if(inst == 0)
	{
		//TODO - STP,LDP 
		printf("[log] - LDP/STP instruction\n");
		LDP();
	}

	else if(inst == 1)
	{
	//TODO - LDR,LDRSW,STR
	printf("[log] - LDR/STR instruction\n");
	LDR();
	}

  }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl $0x4, 0x14f4f(%rip)     # 0x1a208
leaq 0x14f30(%rip), %r14     # 0x1a1f0
movq %r14, %rdi
callq 0x5c8a
movl %eax, %ebp
movl %eax, %ebx
shrl $0x1f, %ebx
movq %r14, %rdi
callq 0x5c8a
movl %eax, %r14d
andl $0x1c000000, %r14d      # imm = 0x1C000000
cmpl $0x10000000, %r14d      # imm = 0x10000000
jne 0x5334
cmpb $0x1, 0x14f1c(%rip)     # 0x1a20d
je 0x5544
leaq 0x14ef2(%rip), %rdi     # 0x1a1f0
callq 0x5c86
movl %eax, %ecx
shrl $0x17, %ecx
andl $0x7, %ecx
cmpl $0x1, %ecx
ja 0x54bc
leaq 0x1cb3(%rip), %rdi      # 0x6fce
callq 0x1140
testl %ebp, %ebp
js 0x577c
leaq 0x1cb3(%rip), %rdi      # 0x6fe2
jmp 0x5783
andl $0xe000000, %eax        # imm = 0xE000000
cmpl $0xa000000, %eax        # imm = 0xA000000
jne 0x540c
cmpb $0x1, 0x14ec2(%rip)     # 0x1a20d
je 0x5544
leaq 0x14e98(%rip), %rdi     # 0x1a1f0
callq 0x5c8a
movl %eax, %ecx
andl $0x1f000000, %ecx       # imm = 0x1F000000
cmpl $0xa000000, %ecx        # imm = 0xA000000
jne 0x555e
leaq 0x14e78(%rip), %r13     # 0x1a1f0
movq %r13, %rdi
callq 0x5c8a
movl %eax, %r12d
shrl $0x1d, %r12d
andl $0x3, %r12d
movq %r13, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
movq %r13, %rdi
callq 0x5c8a
movl %eax, %r15d
movq %r13, %rdi
callq 0x5c8a
movl %eax, %r14d
shrl $0x10, %r14d
andl $0x1f, %r14d
movq %r13, %rdi
callq 0x5c8a
leaq 0x1b5d(%rip), %rdi      # 0x6f22
callq 0x1140
cmpl $0x1, %r12d
je 0x57c6
testl %r12d, %r12d
jne 0x5a16
shrl $0x5, %r15d
andl $0x1f, %r15d
leaq 0x1b7a(%rip), %rdi      # 0x6f66
callq 0x1140
xorl %eax, %eax
movl %ebx, %edi
movl $0x1, %esi
movl %ebp, %edx
movl %r15d, %ecx
movl %r14d, %r8d
xorl %r9d, %r9d
pushq %rax
pushq %rax
jmp 0x5749
leaq 0x14ddd(%rip), %rdi     # 0x1a1f0
callq 0x5c8a
cmpl $0x14000000, %r14d      # imm = 0x14000000
jne 0x5537
movl %eax, %ecx
andl $0x7c000000, %ecx       # imm = 0x7C000000
cmpl $0x14000000, %ecx       # imm = 0x14000000
jne 0x560c
cmpb $0x1, 0x14dcd(%rip)     # 0x1a20d
je 0x5544
leaq 0x14da3(%rip), %rdi     # 0x1a1f0
callq 0x5c8a
movl %eax, %edx
andl $0x3ffffff, %edx        # imm = 0x3FFFFFF
xorl %ecx, %ecx
xorl %r15d, %r15d
movl $0x1, %esi
shll %cl, %esi
andl %edx, %esi
addq %rsi, %r15
incl %ecx
cmpl $0x19, %ecx
jne 0x545f
andl $0x2000000, %eax        # imm = 0x2000000
subq %rax, %r15
leaq 0x14d77(%rip), %r14     # 0x1a1f8
movq %r14, %rdi
callq 0x5c86
leaq (%rax,%r15,4), %r15
addq $-0x4, %r15
movq %r14, %rdi
callq 0x5c86
movl %r15d, %ecx
subl %eax, %ecx
movl %ecx, 0x14d64(%rip)     # 0x1a208
movl %ebx, %edi
movq %r15, %rsi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1401
andl $0x3000000, %eax        # imm = 0x3000000
cmpl $0x1000000, %eax        # imm = 0x1000000
jne 0x56c1
leaq 0x14d1d(%rip), %r12     # 0x1a1f0
movq %r12, %rdi
callq 0x5c8a
movl %eax, %r14d
shrl $0x1d, %r14d
andl $0x3, %r14d
movq %r12, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
movq %r12, %rdi
callq 0x5c8a
movl %eax, %r15d
shrl $0x5, %r15d
andl $0x1f, %r15d
movq %r12, %rdi
callq 0x5c8a
shrl $0xa, %eax
andl $0xfff, %eax            # imm = 0xFFF
leaq 0xb4f(%rip), %rcx       # 0x606c
movslq (%rcx,%r14,4), %rdx
addq %rcx, %rdx
jmpq *%rdx
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
movl %r15d, %ecx
movl %eax, %r8d
jmp 0x5a34
cmpb $0x1, 0x14ccf(%rip)     # 0x1a20d
jne 0x5757
leaq 0x1aaf(%rip), %rdi      # 0x6ffa
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1140
movl %eax, %ecx
andl $0x1fa00000, %ecx       # imm = 0x1FA00000
addl $0xf5000000, %ecx       # imm = 0xF5000000
shrl $0x15, %ecx
cmpl $0x5, %ecx
ja 0x59cd
leaq 0xac5(%rip), %rdx       # 0x6044
movslq (%rdx,%rcx,4), %rcx
addq %rdx, %rcx
jmpq *%rcx
leaq 0x1965(%rip), %rdi      # 0x6ef4
callq 0x1140
leaq 0x14c55(%rip), %r15     # 0x1a1f0
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r14d
shrl $0x1d, %r14d
andl $0x3, %r14d
movq %r15, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r12d
shrl $0x5, %r12d
andl $0x1f, %r12d
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r13d
shrl $0x10, %r13d
andl $0x1f, %r13d
movq %r15, %rdi
callq 0x5c8a
leaq 0xa6c(%rip), %rax       # 0x605c
movslq (%rax,%r14,4), %rcx
addq %rax, %rcx
jmpq *%rcx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x2382
shrl $0x19, %eax
andl $0x3f, %eax
cmpl $0x1a, %eax
je 0x588d
cmpl $0x2b, %eax
je 0x57e3
cmpl $0x2a, %eax
jne 0x5a16
cmpb $0x1, 0x14bd9(%rip)     # 0x1a20d
je 0x5544
testl %ebp, %ebp
js 0x5ab8
leaq 0x14ba7(%rip), %rdi     # 0x1a1f0
callq 0x5c8a
shrl $0x5, %eax
andl $0x7ffff, %eax          # imm = 0x7FFFF
xorl %ecx, %ecx
xorl %r15d, %r15d
movl $0x1, %edx
shll %cl, %edx
andl %eax, %edx
addq %rdx, %r15
incl %ecx
cmpl $0x19, %ecx
jne 0x565b
leaq 0x14b7b(%rip), %rdi     # 0x1a1f0
callq 0x5c8a
movl %eax, %ebx
andl $0xf, %ebx
leaq 0x14b72(%rip), %r14     # 0x1a1f8
movq %r14, %rdi
callq 0x5c86
leaq (%rax,%r15,4), %r15
addq $-0x4, %r15
movq %r14, %rdi
callq 0x5c86
movl %r15d, %ecx
subl %eax, %ecx
movl %ecx, 0x14b5f(%rip)     # 0x1a208
movq %r15, %rdi
movl %ebx, %esi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1473
cmpl $0x6, %ecx
je 0x5933
cmpl $0x5, %ecx
je 0x5835
cmpl $0x4, %ecx
jne 0x5a16
leaq 0x14b0d(%rip), %r15     # 0x1a1f0
movq %r15, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r14d
shrl $0x5, %r14d
andl $0x1f, %r14d
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r12d
shrl $0x16, %r12d
andl $0x10, %r12d
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r13d
shrl $0xa, %r13d
andl $0x3f, %r13d
movq %r15, %rdi
callq 0x5c8a
shrl $0x10, %eax
andl $0x3f, %eax
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
movl %r14d, %ecx
xorl %r8d, %r8d
movl %r12d, %r9d
pushq %rax
pushq %r13
callq 0x1d59
addq $0x18, %rsp
jmp 0x5a1a
btl $0x1c, %eax
jb 0x579b
leaq 0x16c0(%rip), %rdi      # 0x6e24
callq 0x1140
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x2be9
leaq 0x186b(%rip), %rdi      # 0x6fee
callq 0x1140
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x3e27
leaq 0x1666(%rip), %rdi      # 0x6e08
callq 0x1140
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x3ecd
leaq 0x1704(%rip), %rdi      # 0x6ec5
jmp 0x554b
leaq 0x1782(%rip), %rdi      # 0x6f4f
callq 0x1140
movl %ebx, %edi
movl $0x1, %esi
movl %ebp, %edx
movl %r14d, %ecx
jmp 0x5869
leaq 0x14a06(%rip), %r14     # 0x1a1f0
movq %r14, %rdi
callq 0x5c8a
movl %eax, %ebx
shrl $0x15, %ebx
andl $0x3, %ebx
movq %r14, %rdi
callq 0x5c8a
cmpl $0x1, %ebx
ja 0x59f9
cmpb $0x1, 0x149fb(%rip)     # 0x1a20d
je 0x5544
shrl $0x5, %eax
andl $0x1f, %eax
movl %ebx, %edi
movl %eax, %esi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1348
leaq 0x1779(%rip), %rdi      # 0x6fb5
callq 0x1140
leaq 0x149a8(%rip), %r14     # 0x1a1f0
movq %r14, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
movq %r14, %rdi
callq 0x5c8a
shrl $0x5, %eax
movzwl %ax, %ecx
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1cbd
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
movl %r15d, %ecx
movl %eax, %r8d
jmp 0x5a56
cmpb $0x1, 0x14979(%rip)     # 0x1a20d
je 0x5544
leaq 0x1494f(%rip), %r14     # 0x1a1f0
movq %r14, %rdi
callq 0x5c8a
movl %eax, %ebp
movq %r14, %rdi
callq 0x5c8a
shrl $0x5, %eax
andl $0x7ffff, %eax          # imm = 0x7FFFF
xorl %ecx, %ecx
xorl %r12d, %r12d
movl $0x1, %edx
shll %cl, %edx
andl %eax, %edx
addq %rdx, %r12
incl %ecx
cmpl $0x19, %ecx
jne 0x58c0
leaq 0x14916(%rip), %rdi     # 0x1a1f0
callq 0x5c8a
movl %eax, %r14d
leaq 0x1490f(%rip), %r15     # 0x1a1f8
movq %r15, %rdi
callq 0x5c86
leaq (%rax,%r12,4), %r12
addq $-0x4, %r12
andl $0x1f, %r14d
shrl $0x18, %ebp
andl $0x1, %ebp
movq %r15, %rdi
callq 0x5c86
movl %r12d, %ecx
subl %eax, %ecx
movl %ecx, 0x148f2(%rip)     # 0x1a208
movl %ebx, %edi
movl %ebp, %esi
movl %r14d, %edx
movq %r12, %rcx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1514
leaq 0x1643(%rip), %rdi      # 0x6f7d
callq 0x1140
leaq 0x148aa(%rip), %r15     # 0x1a1f0
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r12d
shrl $0x1d, %r12d
andl $0x3, %r12d
movq %r15, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r14d
shrl $0x5, %r14d
andl $0x1f, %r14d
movq %r15, %rdi
callq 0x5c8a
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r13d
movq %r15, %rdi
callq 0x5c8a
movl %eax, %r15d
shrl $0x10, %r15d
andl $0x3f, %r15d
cmpl $0x2, %r12d
je 0x5a69
testl %r12d, %r12d
jne 0x5a16
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
movl %r14d, %ecx
movl %r15d, %r8d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x18bf
shrl $0x15, %eax
cmpb $-0x2c, %al
je 0x5aac
movzbl %al, %eax
cmpl $0xd2, %eax
je 0x5aa0
cmpl $0xd0, %eax
jne 0x5a16
leaq 0x14ae(%rip), %rdi      # 0x6ea2
jmp 0x554b
cmpl $0x2, %ebx
jne 0x5a16
movl $0x1e, %edi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1596
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl %ebx, %edi
movl $0x1, %esi
movl %ebp, %edx
movl %r12d, %ecx
movl %r13d, %r8d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1632
movl %ebx, %edi
movl $0x1, %esi
movl %ebp, %edx
movl %r12d, %ecx
movl %r13d, %r8d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1b92
notl %r13d
testl $0x7c00, %r13d          # imm = 0x7C00
jne 0x5ac4
leaq 0x1521(%rip), %rdi      # 0x6f9d
callq 0x1140
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
movl %r14d, %ecx
movl %r15d, %r8d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1ab8
leaq 0x13be(%rip), %rdi      # 0x6e65
jmp 0x554b
leaq 0x138d(%rip), %rdi      # 0x6e40
jmp 0x554b
leaq 0x82e(%rip), %rdi       # 0x62ed
jmp 0x554b
leaq 0x7c5(%rip), %rdi       # 0x6290
xorl %eax, %eax
callq 0x1040
movl %ebx, %edi
xorl %esi, %esi
movl %ebp, %edx
movl %r14d, %ecx
movl %r15d, %r8d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x19b8