// File: /workspace/github_cpp_makefile_star2_O3/CMU-SAFARI[P]MQSim/src/ssd/TSU_Base.cpp
// Function: SSD_Components::TSU_Base::issue_command_to_chip(SSD_Components::Flash_Transaction_Queue*, SSD_Components::Flash_Transaction_Queue*, SSD_Components::Transaction_Type, bool)
bool TSU_Base::issue_command_to_chip(Flash_Transaction_Queue *sourceQueue1, Flash_Transaction_Queue *sourceQueue2, Transaction_Type transactionType, bool suspensionRequired)
	{
		flash_die_ID_type dieID = sourceQueue1->front()->Address.DieID;
		flash_page_ID_type pageID = sourceQueue1->front()->Address.PageID;
		unsigned int planeVector = 0;
		static int issueCntr = 0;
		
		for (unsigned int i = 0; i < die_no_per_chip; i++)
		{
			transaction_dispatch_slots.clear();
			planeVector = 0;

			for (Flash_Transaction_Queue::iterator it = sourceQueue1->begin(); it != sourceQueue1->end();)
			{
				if (transaction_is_ready(*it) && (*it)->Address.DieID == dieID && !(planeVector & 1 << (*it)->Address.PlaneID))
				{
					//Check for identical pages when running multiplane command
					if (planeVector == 0 || (*it)->Address.PageID == pageID)
					{
						(*it)->SuspendRequired = suspensionRequired;
						planeVector |= 1 << (*it)->Address.PlaneID;
						transaction_dispatch_slots.push_back(*it);
						DEBUG(issueCntr++ << ": " << Simulator->Time() <<" Issueing Transaction - Type:" << TRTOSTR((*it)) << ", PPA:" << (*it)->PPA << ", LPA:" << (*it)->LPA << ", Channel: " << (*it)->Address.ChannelID << ", Chip: " << (*it)->Address.ChipID);
						sourceQueue1->remove(it++);
						continue;
					}
				}
				it++;
			}

			if (sourceQueue2 != NULL && transaction_dispatch_slots.size() < plane_no_per_die)
			{
				for (Flash_Transaction_Queue::iterator it = sourceQueue2->begin(); it != sourceQueue2->end();)
				{
					if (transaction_is_ready(*it) && (*it)->Address.DieID == dieID && !(planeVector & 1 << (*it)->Address.PlaneID))
					{
						//Check for identical pages when running multiplane command
						if (planeVector == 0 || (*it)->Address.PageID == pageID)
						{
							(*it)->SuspendRequired = suspensionRequired;
							planeVector |= 1 << (*it)->Address.PlaneID;
							transaction_dispatch_slots.push_back(*it);
							DEBUG(issueCntr++ << ": " << Simulator->Time() << " Issueing Transaction - Type:" << TRTOSTR((*it)) << ", PPA:" << (*it)->PPA << ", LPA:" << (*it)->LPA << ", Channel: " << (*it)->Address.ChannelID << ", Chip: " << (*it)->Address.ChipID);
							sourceQueue2->remove(it++);
							continue;
						}
					}
					it++;
				}
			}

			if (transaction_dispatch_slots.size() > 0)
			{
				_NVMController->Send_command_to_chip(transaction_dispatch_slots);
				transaction_dispatch_slots.clear();
				dieID = (dieID + 1) % die_no_per_chip;
				return true;
			}
			else
			{
				transaction_dispatch_slots.clear();
				dieID = (dieID + 1) % die_no_per_chip;
				return false;
			}			
		}

		return false;
	}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl 0x4c(%rdi), %eax
testl %eax, %eax
je 0x4a88b
movq %rsi, %r13
movq %rdi, %r12
movq %rdx, 0x10(%rsp)
movl %r8d, 0xc(%rsp)
movl %eax, 0x2c(%rsp)
leaq 0x8(%rsi), %r15
movq 0x8(%rsi), %rax
movq 0x10(%rax), %rax
movl 0x40(%rax), %ebp
movl 0x4c(%rax), %eax
movl %eax, 0x8(%rsp)
leaq 0x90(%rdi), %r14
movq 0x90(%rdi), %rdi
cmpq %r14, %rdi
je 0x4a798
movq (%rdi), %rbx
callq 0x7370
movq %rbx, %rdi
cmpq %r14, %rbx
jne 0x4a788
movq %r14, 0x98(%r12)
movq %r14, 0x90(%r12)
movq %r12, 0x18(%rsp)
movq $0x0, 0xa0(%r12)
movq (%r15), %rbx
cmpq %r15, %rbx
je 0x4a890
movq %r13, 0x30(%rsp)
xorl %r13d, %r13d
movq 0x10(%rsp), %rsi
movl 0x8(%rsp), %edi
movq %rbx, %r12
movq 0x10(%r12), %rax
movl 0x8(%rax), %ecx
cmpl $0x1, %ecx
je 0x4a7f7
cmpl $0x2, %ecx
jne 0x4a801
cmpq $0x0, 0x90(%rax)
jne 0x4a820
jmp 0x4a801
cmpq $0x0, 0x88(%rax)
jne 0x4a820
cmpl %ebp, 0x40(%rax)
jne 0x4a820
movl 0x44(%rax), %ecx
movl $0x1, %edx
shll %cl, %edx
btl %ecx, %r13d
jb 0x4a820
testl %r13d, %r13d
je 0x4a82b
cmpl %edi, 0x4c(%rax)
je 0x4a82b
movq (%r12), %r12
cmpq %r15, %r12
jne 0x4a7d9
jmp 0x4a89c
movl 0xc(%rsp), %ecx
movb %cl, 0x68(%rax)
orl %edx, %r13d
movl $0x18, %edi
callq 0x73a0
movq 0x10(%r12), %rcx
movq %rcx, 0x10(%rax)
movq %rax, %rdi
movq %r14, %rsi
callq 0x7060
movq 0x18(%rsp), %rax
incq 0xa0(%rax)
movq (%r12), %rbx
movq %r12, 0x20(%rsp)
movq 0x30(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x3e004
movl 0x8(%rsp), %edi
movq 0x10(%rsp), %rsi
cmpq %r15, %rbx
jne 0x4a7d6
jmp 0x4a89c
jmp 0x4a9ee
xorl %r13d, %r13d
movq 0x10(%rsp), %rsi
movl 0x8(%rsp), %edi
testq %rsi, %rsi
je 0x4a979
movq 0x18(%rsp), %r15
movq 0xa0(%r15), %rax
movl 0x50(%r15), %ecx
cmpq %rcx, %rax
jae 0x4a985
leaq 0x8(%rsi), %r15
movq 0x8(%rsi), %rbx
cmpq %r15, %rbx
je 0x4a979
movq %rbx, %r12
movq 0x10(%r12), %rax
movl 0x8(%rax), %ecx
cmpl $0x1, %ecx
je 0x4a8f0
cmpl $0x2, %ecx
jne 0x4a8fa
cmpq $0x0, 0x90(%rax)
jne 0x4a919
jmp 0x4a8fa
cmpq $0x0, 0x88(%rax)
jne 0x4a919
cmpl %ebp, 0x40(%rax)
jne 0x4a919
movl 0x44(%rax), %ecx
movl $0x1, %edx
shll %cl, %edx
btl %ecx, %r13d
jb 0x4a919
testl %r13d, %r13d
je 0x4a924
cmpl %edi, 0x4c(%rax)
je 0x4a924
movq (%r12), %r12
cmpq %r15, %r12
jne 0x4a8d2
jmp 0x4a979
movl 0xc(%rsp), %ecx
movb %cl, 0x68(%rax)
orl %edx, %r13d
movl $0x18, %edi
callq 0x73a0
movq 0x10(%r12), %rcx
movq %rcx, 0x10(%rax)
movq %rax, %rdi
movq %r14, %rsi
callq 0x7060
movq 0x18(%rsp), %rax
incq 0xa0(%rax)
movq (%r12), %rbx
movq %r12, 0x20(%rsp)
movq 0x10(%rsp), %rdi
leaq 0x20(%rsp), %rsi
callq 0x3e004
movl 0x8(%rsp), %edi
jmp 0x4a8c6
movq 0x18(%rsp), %r15
movq 0xa0(%r15), %rax
testq %rax, %rax
setne %bpl
je 0x4a9b9
movq 0x38(%r15), %rdi
movq (%rdi), %rax
movq %r14, %rsi
callq *0x58(%rax)
movq 0x90(%r15), %rdi
cmpq %r14, %rdi
je 0x4a9d1
movq (%rdi), %rbx
callq 0x7370
movq %rbx, %rdi
cmpq %r14, %rbx
jne 0x4a9a7
jmp 0x4a9d1
movq (%r14), %rdi
cmpq %r14, %rdi
je 0x4a9d1
movq (%rdi), %rbx
callq 0x7370
movq %rbx, %rdi
cmpq %r14, %rbx
jne 0x4a9c1
movq %r14, 0x98(%r15)
movq %r14, 0x90(%r15)
movq $0x0, 0xa0(%r15)
movl 0x2c(%rsp), %eax
testl %eax, %eax
setne %al
andb %bpl, %al
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop