// File: /workspace/github_cpp_makefile_star2_O1/NishadSaraf[P]Championship-Simulator/src/ooo_cpu.cc
// Function: O3_CPU::add_load_queue(unsigned int, unsigned int)
void O3_CPU::add_load_queue(uint32_t rob_index, uint32_t data_index)
{
    // search for an empty slot 
    uint32_t lq_index = LQ.SIZE;
    for (uint32_t i=0; i<LQ.SIZE; i++) {
        if (LQ.entry[i].virtual_address == 0) {
            lq_index = i;
            break;
        }
    }

    // sanity check
    if (lq_index == LQ.SIZE) {
        cerr << "instr_id: " << ROB.entry[rob_index].instr_id << " no empty slot in the load queue!!!" << endl;
        assert(0);
    }

    // add it to the load queue
    ROB.entry[rob_index].lq_index[data_index] = lq_index;
    LQ.entry[lq_index].instr_id = ROB.entry[rob_index].instr_id;
    LQ.entry[lq_index].virtual_address = ROB.entry[rob_index].source_memory[data_index];
    LQ.entry[lq_index].ip = ROB.entry[rob_index].ip;
    LQ.entry[lq_index].data_index = data_index;
    LQ.entry[lq_index].rob_index = rob_index;
    LQ.entry[lq_index].asid[0] = ROB.entry[rob_index].asid[0];
    LQ.entry[lq_index].asid[1] = ROB.entry[rob_index].asid[1];
    LQ.entry[lq_index].event_cycle = current_core_cycle[cpu] + SCHEDULING_LATENCY;
    LQ.occupancy++;

    // check RAW dependency
    int prior = rob_index - 1;
    if (prior < 0)
        prior = ROB.SIZE - 1;

    if (rob_index != ROB.head) {
        if ((int)ROB.head <= prior) {
            for (int i=prior; i>=(int)ROB.head; i--) {
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
        }
        else {
            for (int i=prior; i>=0; i--) {
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
            for (int i=ROB.SIZE-1; i>=(int)ROB.head; i--) { 
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
        }
    }

    // check
    // 1) if store-to-load forwarding is possible
    // 2) if there is WAR that are not correctly executed
    uint32_t forwarding_index = SQ.SIZE;
    for (uint32_t i=0; i<SQ.SIZE; i++) {

        // skip empty slot
        if (SQ.entry[i].virtual_address == 0)
            continue;

        // forwarding should be done by the SQ entry that holds the same producer_id from RAW dependency check
        if (SQ.entry[i].virtual_address == LQ.entry[lq_index].virtual_address) { // store-to-load forwarding check

            // forwarding store is in the SQ
            if ((rob_index != ROB.head) && (LQ.entry[lq_index].producer_id == SQ.entry[i].instr_id)) { // RAW
                forwarding_index = i;
                break; // should be break
            }

            if ((LQ.entry[lq_index].producer_id == UINT64_MAX) && (LQ.entry[lq_index].instr_id <= SQ.entry[i].instr_id)) { // WAR 
                // a load is about to be added in the load queue and we found a store that is 
                // "logically later in the program order but already executed" => this is not correctly executed WAR
                // due to out-of-order execution, this case is possible, for example
                // 1) application is load intensive and load queue is full
                // 2) we have loads that can't be added in the load queue
                // 3) subsequent stores logically behind in the program order are added in the store queue first

                // thanks to the store buffer, data is not written back to the memory system until retirement
                // also due to in-order retirement, this "already executed store" cannot be retired until we finish the prior load instruction 
                // if we detect WAR when a load is added in the load queue, just let the load instruction to access the memory system
                // no need to mark any dependency because this is actually WAR not RAW

                // do not forward data from the store queue since this is WAR
                // just read correct data from data cache

                LQ.entry[lq_index].physical_address = 0;
                LQ.entry[lq_index].translated = 0;
                LQ.entry[lq_index].fetched = 0;
                
                DP(if(warmup_complete[cpu]) {
                cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " reset fetched: " << +LQ.entry[lq_index].fetched;
                cout << " to obey WAR store instr_id: " << SQ.entry[i].instr_id << " cycle: " << current_core_cycle[cpu] << endl; });
            }
        }
    }

    if (forwarding_index != SQ.SIZE) { // we have a store-to-load forwarding

        if ((SQ.entry[forwarding_index].fetched == COMPLETED) && (SQ.entry[forwarding_index].event_cycle <= current_core_cycle[cpu])) {
            LQ.entry[lq_index].physical_address = (SQ.entry[forwarding_index].physical_address & ~(uint64_t) ((1 << LOG2_BLOCK_SIZE) - 1)) | (LQ.entry[lq_index].virtual_address & ((1 << LOG2_BLOCK_SIZE) - 1));
            LQ.entry[lq_index].translated = COMPLETED;
            LQ.entry[lq_index].fetched = COMPLETED;

            uint32_t fwr_rob_index = LQ.entry[lq_index].rob_index;
            ROB.entry[fwr_rob_index].num_mem_ops--;
            ROB.entry[fwr_rob_index].event_cycle = current_core_cycle[cpu];
            if (ROB.entry[fwr_rob_index].num_mem_ops < 0) {
                cerr << "instr_id: " << ROB.entry[fwr_rob_index].instr_id << endl;
                assert(0);
            }
            if (ROB.entry[fwr_rob_index].num_mem_ops == 0)
                inflight_mem_executions++;

            DP(if(warmup_complete[cpu]) {
            cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << hex;
            cout << " full_addr: " << LQ.entry[lq_index].physical_address << dec << " is forwarded by store instr_id: ";
            cout << SQ.entry[forwarding_index].instr_id << " remain_num_ops: " << ROB.entry[fwr_rob_index].num_mem_ops << " cycle: " << current_core_cycle[cpu] << endl; });

            release_load_queue(lq_index);
        }
        else
            ; // store is not executed yet, forwarding will be handled by execute_store()
    }

    // succesfully added to the load queue
    ROB.entry[rob_index].source_added[data_index] = 1;

    if (LQ.entry[lq_index].virtual_address && (LQ.entry[lq_index].producer_id == UINT64_MAX)) { // not released and no forwarding
        RTL0[RTL0_tail] = lq_index;
        RTL0_tail++;
        if (RTL0_tail == LQ_SIZE)
            RTL0_tail = 0;

        DP (if (warmup_complete[cpu]) {
        cout << "[RTL0] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " rob_index: " << LQ.entry[lq_index].rob_index << " is added to RTL0";
        cout << " head: " << RTL0_head << " tail: " << RTL0_tail << endl; }); 
    }

    DP(if(warmup_complete[cpu]) {
    cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id;
    cout << " is added in the LQ address: " << hex << LQ.entry[lq_index].virtual_address << dec << " translated: " << +LQ.entry[lq_index].translated;
    cout << " fetched: " << +LQ.entry[lq_index].fetched << " index: " << lq_index << " occupancy: " << LQ.occupancy << " cycle: " << current_core_cycle[cpu] << endl; });
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %r15d
movl %esi, %r14d
movq %rdi, %rbx
movl 0x9e0(%rdi), %eax
movl %eax, %ebp
testl %eax, %eax
je 0xe4d1
movq 0x9f0(%rbx), %rcx
addq $0x10, %rcx
xorl %ebp, %ebp
cmpq $0x0, (%rcx)
je 0xe4d1
incl %ebp
addq $0x140, %rcx            # imm = 0x140
cmpl %ebp, %eax
jne 0xe4bc
movl %eax, %ebp
movl %r14d, %r12d
cmpl %eax, %ebp
je 0xe8a1
movq 0x9b8(%rbx), %rax
movl %r15d, %r8d
imulq $0x758, %r12, %r9       # imm = 0x758
leaq (%rax,%r9), %rcx
movl %ebp, 0x728(%rcx,%r8,4)
movq (%rax,%r9), %rdx
movq 0x9f0(%rbx), %rsi
movl %ebp, %edi
movq %rdi, (%rsp)
shlq $0x6, %rdi
leaq (%rdi,%rdi,4), %rdi
movq %rdx, (%rsi,%rdi)
movq %r8, 0x10(%rsp)
movq 0x5c8(%rcx,%r8,8), %rcx
movq %rcx, 0x10(%rsi,%rdi)
movq 0x8(%rax,%r9), %rcx
movq %rcx, 0x20(%rsi,%rdi)
movl %r15d, 0x34(%rsi,%rdi)
movl %r14d, 0x30(%rsi,%rdi)
movb 0x5b(%rax,%r9), %al
movb %al, 0x3e(%rsi,%rdi)
movq 0x9b8(%rbx), %rax
movq 0x9f0(%rbx), %rcx
movq %r9, 0x8(%rsp)
movb 0x5c(%rax,%r9), %al
movb %al, 0x3f(%rcx,%rdi)
movl (%rbx), %eax
leaq 0x72956(%rip), %rdx     # 0x80ec0
movl 0x72960(%rip), %ecx     # 0x80ed0
addq (%rdx,%rax,8), %rcx
movq 0x9f0(%rbx), %rax
movq %rcx, 0x28(%rax,%rdi)
incl 0x9e4(%rbx)
movl 0x958(%rbx), %eax
cmpl %r14d, %eax
jne 0xe629
movl 0xa18(%rbx), %eax
testq %rax, %rax
je 0xe6e2
movq 0xa28(%rbx), %rdx
movq 0x9f0(%rbx), %rcx
movq (%rsp), %r15
leaq (%r15,%r15,4), %r8
shlq $0x6, %r8
leaq (%rcx,%r8), %rsi
movl 0x958(%rbx), %edi
addq %rcx, %r8
addq $0x3c, %r8
xorl %r9d, %r9d
xorl %ecx, %ecx
movq 0x10(%rdx), %r10
testq %r10, %r10
je 0xe613
cmpq 0x10(%rsi), %r10
jne 0xe613
cmpl %r14d, %edi
je 0xe5f5
movq 0x8(%rsi), %r10
cmpq (%rdx), %r10
je 0xe6e8
cmpq $-0x1, 0x8(%rsi)
jne 0xe613
movq (%rsi), %r10
cmpq (%rdx), %r10
ja 0xe613
movq $0x0, 0x18(%rsi)
movb %r9b, (%r8)
movb %r9b, 0x1(%r8)
incq %rcx
addq $0x140, %rdx            # imm = 0x140
cmpq %rcx, %rax
jne 0xe5d4
movl %eax, %ecx
jmp 0xe6e8
leal -0x1(%r14), %ecx
movl 0x950(%rbx), %r12d
decl %r12d
testl %ecx, %ecx
cmovnsl %ecx, %r12d
cmpl %r12d, %eax
jle 0xe84b
testl %r12d, %r12d
js 0xe687
movq (%rsp), %rax
leaq (%rax,%rax,4), %r13
shlq $0x6, %r13
movq 0x9f0(%rbx), %rax
cmpq $-0x1, 0x8(%rax,%r13)
jne 0xe687
movq %rbx, %rdi
movl %r12d, %esi
movl %r14d, %edx
movl %r15d, %ecx
movl %ebp, %r8d
callq 0xeab8
leal -0x1(%r12), %eax
testl %r12d, %r12d
movl %eax, %r12d
jg 0xe657
movl 0x950(%rbx), %r12d
decl %r12d
cmpl 0x958(%rbx), %r12d
jl 0xe595
movq (%rsp), %rax
leaq (%rax,%rax,4), %r13
shlq $0x6, %r13
movq 0x9f0(%rbx), %rax
cmpq $-0x1, 0x8(%rax,%r13)
jne 0xe595
movq %rbx, %rdi
movl %r12d, %esi
movl %r14d, %edx
movl %r15d, %ecx
movl %ebp, %r8d
callq 0xeab8
decl %r12d
cmpl 0x958(%rbx), %r12d
jge 0xe6aa
jmp 0xe595
movl %eax, %ecx
movq (%rsp), %r15
cmpl %eax, %ecx
je 0xe7e2
movq 0xa28(%rbx), %rdx
movl %ecx, %eax
leaq (%rax,%rax,4), %rax
shlq $0x6, %rax
cmpb $0x2, 0x3d(%rdx,%rax)
jne 0xe7e2
addq %rax, %rdx
movq 0x28(%rdx), %rcx
movl (%rbx), %eax
leaq 0x727a4(%rip), %rsi     # 0x80ec0
cmpq (%rsi,%rax,8), %rcx
ja 0xe7e2
movq 0x18(%rdx), %rsi
andq $-0x40, %rsi
movq 0x9f0(%rbx), %rcx
leaq (%r15,%r15,4), %rdx
shlq $0x6, %rdx
movq 0x10(%rcx,%rdx), %rdi
andl $0x3f, %edi
orq %rsi, %rdi
movq %rdi, 0x18(%rcx,%rdx)
movw $0x202, 0x3c(%rcx,%rdx) # imm = 0x202
movl 0x30(%rcx,%rdx), %esi
movq 0x9b8(%rbx), %rdi
imulq $0x758, %rsi, %r14      # imm = 0x758
movl 0x70(%rdi,%r14), %r8d
leal -0x1(%r8), %esi
movl %esi, 0x70(%rdi,%r14)
leaq 0x72745(%rip), %r9      # 0x80ec0
movq (%r9,%rax,8), %rax
movq %rax, 0x40(%rdi,%r14)
testl %r8d, %r8d
jle 0xe904
leaq (%rcx,%rdx), %rdi
leaq (%rcx,%rdx), %rax
addq $0x10, %rax
testl %esi, %esi
jne 0xe7a3
incl 0x924(%rbx)
xorl %ecx, %ecx
movq %rcx, (%rdi)
movq $-0x1, 0x8(%rdi)
movq %rcx, 0x20(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x10(%rax)
movups %xmm0, (%rax)
movabsq $-0xffff00000001, %rax  # imm = 0xFFFF0000FFFFFFFF
movq %rax, 0x38(%rdi)
addq $0x40, %rdi
movl $0x100, %edx            # imm = 0x100
xorl %esi, %esi
callq 0x3130
decl 0x9e4(%rbx)
movq 0x8(%rsp), %rcx
addq 0x9b8(%rbx), %rcx
movq 0x10(%rsp), %rax
movb $0x1, 0x4e(%rax,%rcx)
movq 0x9f0(%rbx), %rax
leaq (%r15,%r15,4), %rcx
shlq $0x6, %rcx
cmpq $0x0, 0x10(%rax,%rcx)
je 0xe83c
addq %rcx, %rax
cmpq $-0x1, 0x8(%rax)
jne 0xe83c
movl 0x3374(%rbx), %eax
movl %ebp, 0x3250(%rbx,%rax,4)
movl 0x3374(%rbx), %eax
incl %eax
xorl %ecx, %ecx
cmpl $0x48, %eax
cmovnel %eax, %ecx
movl %ecx, 0x3374(%rbx)
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
cmpl 0x958(%rbx), %r12d
jl 0xe595
movq (%rsp), %rax
leaq (%rax,%rax,4), %r13
shlq $0x6, %r13
movq 0x9f0(%rbx), %rax
cmpq $-0x1, 0x8(%rax,%r13)
jne 0xe595
movq %rbx, %rdi
movl %r12d, %esi
movl %r14d, %edx
movl %r15d, %ecx
movl %ebp, %r8d
callq 0xeab8
leal -0x1(%r12), %eax
cmpl 0x958(%rbx), %r12d
movl %eax, %r12d
jg 0xe864
jmp 0xe595
movq 0xb748(%rip), %rdi      # 0x19ff0
leaq 0x6672(%rip), %rsi      # 0x14f21
callq 0x3250
movq 0x9b8(%rbx), %rcx
imulq $0x758, %r12, %rdx      # imm = 0x758
movq (%rcx,%rdx), %rsi
movq %rax, %rdi
callq 0x3090
leaq 0x654d(%rip), %rsi      # 0x14e22
movq %rax, %rdi
callq 0x3250
movq %rax, %rdi
callq 0x3110
leaq 0x577b(%rip), %rdi      # 0x14067
leaq 0x63c3(%rip), %rsi      # 0x14cb6
leaq 0x654c(%rip), %rcx      # 0x14e46
movl $0x369, %edx            # imm = 0x369
callq 0x3160
movq 0xb6e5(%rip), %rdi      # 0x19ff0
leaq 0x660f(%rip), %rsi      # 0x14f21
callq 0x3250
movq 0x9b8(%rbx), %rcx
movq (%rcx,%r14), %rsi
movq %rax, %rdi
callq 0x3090
movq %rax, %rdi
callq 0x3110
leaq 0x572e(%rip), %rdi      # 0x14067
leaq 0x6376(%rip), %rsi      # 0x14cb6
leaq 0x64ff(%rip), %rcx      # 0x14e46
movl $0x3d0, %edx            # imm = 0x3D0
callq 0x3160
nop