// File: /workspace/github_c_makefile_star2_O1/markdryan[P]subtilis/arch/arm32/vfp_alloc.c
// Function: prv_alloc_vfp_stran_instr
static void prv_alloc_vfp_stran_instr(void *user_data, subtilis_arm_op_t *op,
				      subtilis_arm_instr_type_t type,
				      subtilis_vfp_stran_instr_t *instr,
				      subtilis_error_t *err)
{
	int dist_dest;
	int dist_base;
	size_t vreg_base;
	bool fixed_reg_base;
	size_t vreg_dest = 0;
	subtilis_arm_reg_ud_t *ud = user_data;

	/*
	 * The function calling code can generate LDFNV and STFNV when
	 * preserving fpa registers.  These instructions should be
	 * ignored for the purposes of register allocation.
	 */

	if (instr->ccode == SUBTILIS_ARM_CCODE_NV) {
		ud->instr_count++;
		return;
	}

	if (type == SUBTILIS_VFP_INSTR_FSTS ||
	    type == SUBTILIS_VFP_INSTR_FLDS) {
		subtilis_error_set_assertion_failed(err);
	}

	if (type == SUBTILIS_VFP_INSTR_FSTD) {
		vreg_dest = instr->dest;
		(void)subtilis_arm_reg_alloc_ensure(
		    ud, op, ud->int_regs, ud->real_regs, &instr->dest, err);
		if (err->type != SUBTILIS_ERROR_OK)
			return;
	}

	vreg_base = instr->base;
	fixed_reg_base = subtilis_arm_reg_alloc_ensure(
	    ud, op, ud->int_regs, ud->int_regs, &instr->base, err);
	if (err->type != SUBTILIS_ERROR_OK)
		return;

	if (!fixed_reg_base) {
		dist_base = subtilis_arm_reg_alloc_calculate_dist(
		    ud, vreg_base, op, &ud->int_regs->dist_walker,
		    ud->int_regs);
		if (dist_base == -1)
			ud->int_regs->phys_to_virt[instr->base] = INT_MAX;
	}

	if (type == SUBTILIS_VFP_INSTR_FSTD) {
		dist_dest = subtilis_arm_reg_alloc_calculate_dist(
		    ud, vreg_dest, op, &ud->real_regs->dist_walker,
		    ud->real_regs);
		if (dist_dest == -1)
			ud->real_regs->phys_to_virt[instr->dest] = INT_MAX;
		ud->real_regs->next[instr->dest] = dist_dest;
	} else {
		subtilis_arm_reg_alloc_alloc_fp_dest(ud, op, &instr->dest, err);
		if (err->type != SUBTILIS_ERROR_OK)
			return;
	}

	if (!fixed_reg_base)
		ud->int_regs->next[instr->base] = dist_base;

	ud->instr_count++;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
cmpl $0xf, (%rcx)
jne 0x6c373
incq 0x20(%rbx)
jmp 0x6c402
movq %r8, %r15
movq %rcx, %r14
movl %edx, %ebp
movq %rsi, %r12
movl %edx, %eax
andl $-0x2, %eax
cmpl $0x46, %eax
jne 0x6c3a1
leaq 0xac87(%rip), %rdx      # 0x77016
movq %r15, %rdi
movl $0xf, %esi
movl $0x69, %ecx
callq 0x13604
cmpl $0x48, %ebp
jne 0x6c3d1
leaq 0x8(%r14), %r8
movq 0x8(%r14), %rax
movq %rax, 0x10(%rsp)
movq 0x8(%rbx), %rdx
movq 0x10(%rbx), %rcx
movq %rbx, %rdi
movq %r12, %rsi
movq %r15, %r9
callq 0x5216a
cmpl $0x0, (%r15)
jne 0x6c402
jmp 0x6c3da
movq $0x0, 0x10(%rsp)
leaq 0x10(%r14), %r8
movq 0x10(%r14), %r13
movq 0x8(%rbx), %rcx
movq %rbx, %rdi
movq %r12, %rsi
movq %rcx, %rdx
movq %r8, 0x8(%rsp)
movq %r15, %r9
callq 0x5216a
cmpl $0x0, (%r15)
je 0x6c411
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movb %al, 0x3(%rsp)
testb %al, %al
jne 0x6c45b
movq 0x8(%rbx), %r8
leaq 0x90(%r8), %rcx
movq %rbx, %rdi
movq %r13, %rsi
movq %r12, %rdx
callq 0x51f18
movl %eax, 0x4(%rsp)
cmpl $-0x1, %eax
jne 0x6c45b
movq 0x8(%rbx), %rax
movq 0x8(%rax), %rax
movq 0x8(%rsp), %rcx
movq (%rcx), %rcx
movq $0x7fffffff, (%rax,%rcx,8) # imm = 0x7FFFFFFF
movl $0xffffffff, 0x4(%rsp)  # imm = 0xFFFFFFFF
cmpl $0x48, %ebp
jne 0x6c4a9
movq 0x10(%rbx), %r8
leaq 0x90(%r8), %rcx
movq %rbx, %rdi
movq 0x10(%rsp), %rsi
movq %r12, %rdx
callq 0x51f18
cmpl $-0x1, %eax
jne 0x6c494
movq 0x10(%rbx), %rcx
movq 0x8(%rcx), %rcx
movq 0x8(%r14), %rdx
movq $0x7fffffff, (%rcx,%rdx,8) # imm = 0x7FFFFFFF
movq 0x10(%rbx), %rcx
movq 0x10(%rcx), %rcx
movq 0x8(%r14), %rdx
movl %eax, (%rcx,%rdx,4)
movb 0x3(%rsp), %al
jmp 0x6c4cc
addq $0x8, %r14
movq %rbx, %rdi
movq %r12, %rsi
movq %r14, %rdx
movq %r15, %rcx
callq 0x52427
cmpl $0x0, (%r15)
movb 0x3(%rsp), %al
jne 0x6c402
testb %al, %al
jne 0x6c36a
movq 0x8(%rbx), %rax
movq 0x10(%rax), %rax
movq 0x8(%rsp), %rcx
movq (%rcx), %rcx
movl 0x4(%rsp), %edx
movl %edx, (%rax,%rcx,4)
jmp 0x6c36a