// File: /workspace/github_c_makefile_star2_O2/Ihsoh[P]ilang/compiler/assembler/ins_enc.c
// Function: ins_enc_mov_rxX_Ib
void ins_enc_mov_rxX_Ib(
	Instruction *ins,
	InstructionEncoderData *data
) {
	_CHECK_PARAMS(2);

	ParserASTNode *ins_node = data->ins_node;

	ParserASTNode *target = data->ins_node->childs[0];

	ParserASTNode *source = data->ins_node->childs[1];

	EncoderInstruction enc_ins;

	ins_init(data->ctx, ins, ins_node, &enc_ins);

	InsRegister *ins_target_reg = ASM_REG_AST_NODE_GET_REG(target);
	assert(ins_target_reg);

	switch (ASM_PARSER_CONTEXT_DATA_GET_ARCH(data->ctx)) {
		case ASM_ARCH_BIT16: {
			switch (ins_target_reg->type) {
				case INS_REGISTER_GENERAL_2BYTE: {
					ins_fill_imm16(data->ctx, ins, source, &enc_ins);
					break;
				}
				case INS_REGISTER_GENERAL_4BYTE: {
					enc_ins.legacy_prefix.operand_size_override = true;

					ins_fill_imm32(data->ctx, ins, source, &enc_ins);
					break;
				}
				case INS_REGISTER_GENERAL_8BYTE: {
					data->ctx->syntax_error_node_msg(
						data->ctx,
						ins_node,
						"instruction not supported in 64-bit mode."
					);
					break;
				}
				default: {
					assert(0);
					break;
				}
			}
			break;
		}
		case ASM_ARCH_BIT32: {
			switch (ins_target_reg->type) {
				case INS_REGISTER_GENERAL_2BYTE: {
					enc_ins.legacy_prefix.operand_size_override = true;

					ins_fill_imm16(data->ctx, ins, source, &enc_ins);
					break;
				}
				case INS_REGISTER_GENERAL_4BYTE: {
					ins_fill_imm32(data->ctx, ins, source, &enc_ins);
					break;
				}
				case INS_REGISTER_GENERAL_8BYTE: {
					data->ctx->syntax_error_node_msg(
						data->ctx,
						ins_node,
						"instruction not supported in 64-bit mode."
					);
					break;
				}
				default: {
					assert(0);
					break;
				}
			}
			break;
		}
		case ASM_ARCH_BIT64: {
			switch (ins_target_reg->type) {
				case INS_REGISTER_GENERAL_2BYTE: {
					enc_ins.legacy_prefix.operand_size_override = true;

					ins_fill_imm16(data->ctx, ins, source, &enc_ins);
					break;
				}
				case INS_REGISTER_GENERAL_4BYTE: {
					ins_fill_imm32(data->ctx, ins, source, &enc_ins);
					break;
				}
				case INS_REGISTER_GENERAL_8BYTE: {
					ins_fill_imm32(data->ctx, ins, source, &enc_ins);
					break;
				}
				default: {
					assert(0);
					break;
				}
			}
			break;
		}
		default: {
			assert(0);
			break;
		}
	}

	_output(data, &enc_ins);
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
testq %rdi, %rdi
je 0x18d10
movq %rsi, %rbx
testq %rsi, %rsi
je 0x18d19
movq (%rbx), %r12
testq %r12, %r12
je 0x18d22
cmpl $0x2, 0x44(%r12)
jne 0x18d2b
movq %rdi, %r14
movq 0x48(%r12), %rax
movq (%rax), %r13
movq 0x8(%rax), %r15
movq 0x8(%rbx), %rdi
leaq -0x88(%rbp), %rcx
movq %r14, %rsi
movq %r12, %rdx
callq 0x1470f
movq 0x60(%r13), %rax
testq %rax, %rax
je 0x18d4a
movq 0x8(%rbx), %rdi
movl 0xb0(%rdi), %ecx
cmpl $0x4, %ecx
je 0x18c96
cmpl $0x2, %ecx
je 0x18c65
cmpl $0x1, %ecx
jne 0x18d69
movl 0xc(%rax), %eax
cmpl $0x5, %eax
je 0x18ccd
cmpl $0x4, %eax
je 0x18cdc
cmpl $0x3, %eax
jne 0x18d88
leaq -0x88(%rbp), %rcx
jmp 0x18cb7
movl 0xc(%rax), %eax
cmpl $0x5, %eax
je 0x18ccd
cmpl $0x4, %eax
je 0x18cc4
cmpl $0x3, %eax
je 0x18cac
leaq 0x146f2(%rip), %rdi     # 0x2d370
leaq 0x17fcf(%rip), %rsi     # 0x30c54
leaq 0x18796(%rip), %rcx     # 0x31422
movl $0x470, %edx            # imm = 0x470
callq 0xa0b0
movl 0xc(%rax), %eax
cmpl $0x5, %eax
je 0x18cc4
cmpl $0x4, %eax
je 0x18cc4
cmpl $0x3, %eax
jne 0x18da7
leaq -0x88(%rbp), %rcx
movb $0x1, 0xb(%rcx)
movq %r14, %rsi
movq %r15, %rdx
callq 0x151f8
jmp 0x18cf2
leaq -0x88(%rbp), %rcx
jmp 0x18ce7
leaq 0x182be(%rip), %rdx     # 0x30f92
movq %r12, %rsi
callq *0x58(%rdi)
jmp 0x18cf2
leaq -0x88(%rbp), %rcx
movb $0x1, 0xb(%rcx)
movq %r14, %rsi
movq %r15, %rdx
callq 0x152ee
leaq -0x88(%rbp), %rsi
movq %rbx, %rdi
callq 0x17180
addq $0x68, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x16a23(%rip), %rdi     # 0x2f73a
jmp 0x18d32
leaq 0x1c8cb(%rip), %rdi     # 0x355eb
jmp 0x18d32
leaq 0x17f88(%rip), %rdi     # 0x30cb1
jmp 0x18d32
leaq 0x17f8e(%rip), %rdi     # 0x30cc0
leaq 0x17f1b(%rip), %rsi     # 0x30c54
leaq 0x186e2(%rip), %rcx     # 0x31422
movl $0x430, %edx            # imm = 0x430
callq 0xa0b0
leaq 0x18712(%rip), %rdi     # 0x31463
leaq 0x17efc(%rip), %rsi     # 0x30c54
leaq 0x186c3(%rip), %rcx     # 0x31422
movl $0x43d, %edx            # imm = 0x43D
callq 0xa0b0
leaq 0x14600(%rip), %rdi     # 0x2d370
leaq 0x17edd(%rip), %rsi     # 0x30c54
leaq 0x186a4(%rip), %rcx     # 0x31422
movl $0x48e, %edx            # imm = 0x48E
callq 0xa0b0
leaq 0x145e1(%rip), %rdi     # 0x2d370
leaq 0x17ebe(%rip), %rsi     # 0x30c54
leaq 0x18685(%rip), %rcx     # 0x31422
movl $0x455, %edx            # imm = 0x455
callq 0xa0b0
leaq 0x145c2(%rip), %rdi     # 0x2d370
leaq 0x17e9f(%rip), %rsi     # 0x30c54
leaq 0x18666(%rip), %rcx     # 0x31422
movl $0x487, %edx            # imm = 0x487
callq 0xa0b0