// File: /workspace/github_c_makefile_star2_O2/xiane[P]libvphevcodec/AML_HEVCEncoder.cpp
// Function: Wave4VpuEncSeqSet(AMVHEVCEncHandle_s*)
AMVEnc_Status Wave4VpuEncSeqSet(AMVHEVCEncHandle *Handle) {
    int coreIdx = 0;
    Uint32 addr_report_buf = 0;    // [31:0]
    Uint32 report_buf_size = 0;    // [31:0]
    unsigned char report_endian = 0;    // [ 3:0]
    Uint32 use_sec_axi = 0;    // [31:0]
    Uint32 sec_axi_buf_size = 0x00012800;   // 74KB
    Uint32 temp;   // [31:0]
    Uint32 rd_ptr, wr_ptr, src_num, fb_num, i, j;   // [31:0]

    rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    VLOG(DEBUG, "Wave4VpuEnCSeqSet, rd:0x%x, wr:0x%x\n", rd_ptr, wr_ptr);

    temp = 0;
    temp |= (0 << 24); // [27:24] codec_std_aux
    temp |= (1 << 16); // [23:16] codec_std
    temp |= (Handle->instance_id << 0);  // [15: 0] Handle->instance_id
    VpuWriteReg(Handle->instance_id, W4_INST_INDEX, temp);

    // Work Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_WORK_BASE, Handle->work_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_WORK_SIZE, Handle->work_vb.size);
    VpuWriteReg(Handle->instance_id, W4_WORK_PARAM, 0);

    // Temp Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_TEMP_BASE, Handle->temp_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_TEMP_SIZE, Handle->temp_vb.size);
    VpuWriteReg(Handle->instance_id, W4_TEMP_PARAM, gol_endian);

    VpuWriteReg(Handle->instance_id, W4_ADDR_SEC_AXI, 0);
    VpuWriteReg(Handle->instance_id, W4_SEC_AXI_SIZE, sec_axi_buf_size);
    VpuWriteReg(Handle->instance_id, W4_USE_SEC_AXI, use_sec_axi);

    // Bitstream Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_BS_START_ADDR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_SIZE, Handle->bs_vb.size - 0x8000);
    VpuWriteReg(Handle->instance_id, W4_BS_PARAM, 0xf);
    VpuWriteReg(Handle->instance_id, W4_BS_OPTION, 0);

    VpuWriteReg(Handle->instance_id, W4_BS_RD_PTR, rd_ptr);
    VpuWriteReg(Handle->instance_id, W4_BS_WR_PTR, wr_ptr);

    // Report Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_ADDR_REPORT_BASE, addr_report_buf);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_SIZE, report_buf_size);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_PARAM, report_endian);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SET_PARAM_OPTION, 1);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SET_PARAM_ENABLE, (unsigned int )0xffffffff);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_CUSTOM_GOP_PARAM, 0x11);
    for (i = 0; i < 1; i++) {
        VpuWriteReg(coreIdx, W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (i*4), 0x785);
        VpuWriteReg(coreIdx, W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_0 + (i*4), 0);
    }

    for (j = i; j < 8; j++) {
        VpuWriteReg(coreIdx, W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (j*4), 0);
        VpuWriteReg(coreIdx, W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_0 + (j*4), 0);
    }

    // issue command request
    VpuWriteReg(Handle->instance_id, W4_VPU_BUSY_STATUS, 1);
    VpuWriteReg(Handle->instance_id, W4_RET_SUCCESS, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_CORE_INDEX, 0);
    //VpuWriteReg(Handle->instance_id, W4_INST_INDEX,  (Handle->instance_id&0xffff)|(1<<16));

    VpuWriteReg(Handle->instance_id, W4_COMMAND, SET_PARAM);
    VpuWriteReg(Handle->instance_id, W4_VPU_HOST_INT_REQ, 1);
    temp = VpuReadReg(Handle->instance_id, W4_VPU_BUSY_STATUS);
    VLOG(DEBUG, "W4_VPU_BUSY_STATUS :0x%x\n", temp);
    if (vdi_wait_interrupt(Handle->instance_id, VPU_BUSY_CHECK_TIMEOUT) == -1) {
        VLOG(ERR, "Wave4VpuEnCSeqInit error time out\n");
        return AMVENC_TIMEOUT;
    }

    if (VpuReadReg(Handle->instance_id, W4_RET_SUCCESS) == 0) {
        uint32_t reasonCode = VpuReadReg(Handle->instance_id, W4_RET_FAIL_REASON);
        VLOG(ERR, "Wave4VpuEnCSeqSet failedREASON CODE(%08x)\n", reasonCode);
        return AMVENC_HARDWARE;
    }
    temp = VpuReadReg(Handle->instance_id, W4_RET_SUCCESS);
    VLOG(DEBUG, "W4_RET_SUCCESS %x\n", temp);
    rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    src_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_SRC_BUF_NUM);
    fb_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_FB_NUM);
    VLOG(DEBUG, "Wave4VpuEnCSeqSet, rd:0x%x, wr:0x%x, src:%d, fb:%d\n", rd_ptr, wr_ptr, src_num, fb_num);
    VLOG(DEBUG, "Wave4VpuEnCSeqSet- End\n");
    return AMVENC_SUCCESS;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl (%rdi), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2210
movl %eax, %ebp
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl %eax, %r14d
movl (%rbx), %edi
movl %edi, %edx
orl $0x10000, %edx          # imm = 0x10000
movl $0x108, %esi            # imm = 0x108
callq 0x2160
movl (%rbx), %edi
movl 0x48(%rbx), %edx
movl $0x138, %esi            # imm = 0x138
callq 0x2160
movl (%rbx), %edi
movl 0x40(%rbx), %edx
movl $0x13c, %esi            # imm = 0x13C
callq 0x2160
movl (%rbx), %edi
movl $0x140, %esi            # imm = 0x140
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl 0x68(%rbx), %edx
movl $0x144, %esi            # imm = 0x144
callq 0x2160
movl (%rbx), %edi
movl 0x60(%rbx), %edx
movl $0x148, %esi            # imm = 0x148
callq 0x2160
movl (%rbx), %edi
pushq $0xf
popq %r15
movl $0x14c, %esi            # imm = 0x14C
movl %r15d, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x150, %esi            # imm = 0x150
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x154, %esi            # imm = 0x154
movl $0x12800, %edx          # imm = 0x12800
callq 0x2160
movl (%rbx), %edi
movl $0x158, %esi            # imm = 0x158
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x120, %esi            # imm = 0x120
callq 0x2160
movl (%rbx), %edi
movl $0xffff8000, %edx       # imm = 0xFFFF8000
addl 0x80(%rbx), %edx
movl $0x124, %esi            # imm = 0x124
callq 0x2160
movl (%rbx), %edi
movl $0x128, %esi            # imm = 0x128
movl %r15d, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x12c, %esi            # imm = 0x12C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
movl %r14d, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x15c, %esi            # imm = 0x15C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x160, %esi            # imm = 0x160
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x164, %esi            # imm = 0x164
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x1
popq %rdx
movl $0x10c, %esi            # imm = 0x10C
callq 0x2160
movl (%rbx), %edi
pushq $-0x1
popq %rdx
movl $0x15c, %esi            # imm = 0x15C
callq 0x2160
movl (%rbx), %edi
pushq $0x11
popq %rdx
movl $0x160, %esi            # imm = 0x160
callq 0x2160
xorl %edi, %edi
movl $0x164, %esi            # imm = 0x164
movl $0x785, %edx            # imm = 0x785
callq 0x2160
xorl %edi, %edi
movl $0x188, %esi            # imm = 0x188
xorl %edx, %edx
callq 0x2160
movl $0x168, %r14d           # imm = 0x168
cmpl $0x184, %r14d           # imm = 0x184
je 0x520a
xorl %edi, %edi
movl %r14d, %esi
xorl %edx, %edx
callq 0x2160
leal 0x24(%r14), %esi
xorl %edi, %edi
xorl %edx, %edx
callq 0x2160
addl $0x4, %r14d
jmp 0x51e2
movl (%rbx), %edi
pushq $0x70
popq %r14
pushq $0x1
popq %rbp
movl %r14d, %esi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x104, %esi            # imm = 0x104
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x2
popq %rdx
movl $0x100, %esi            # imm = 0x100
callq 0x2160
movl (%rbx), %edi
pushq $0x38
popq %rsi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl %r14d, %esi
callq 0x2210
movl (%rbx), %edi
movl $0x1388, %esi           # imm = 0x1388
callq 0x2360
cmpl $-0x1, %eax
je 0x52c9
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
testl %eax, %eax
je 0x52e1
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x1d8, %esi            # imm = 0x1D8
callq 0x2210
movl (%rbx), %edi
movl $0x1cc, %esi            # imm = 0x1CC
callq 0x2210
jmp 0x5306
leaq 0x26e2b(%rip), %rdi     # 0x2c0fb
callq 0x2290
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x24
jmp 0x5305
movl $0x114, %esi            # imm = 0x114
callq 0x2210
leaq 0x26bac(%rip), %rdi     # 0x2be9e
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x25
popq %rbp
movl %ebp, %eax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq