// File: /workspace/github_c_makefile_star2_O0/nh13[P]ksw/src/parasail/src/nw_diag_avx2_256_32.c
// Function: arr_store_rowcol
static inline void arr_store_rowcol(
        int *row,
        int *col,
        __m256i vWH,
        int32_t i,
        int32_t s1Len,
        int32_t j,
        int32_t s2Len)
{
    if (i+0 == s1Len-1 && 0 <= j-0 && j-0 < s2Len) {
        row[j-0] = (int32_t)_mm256_extract_epi32_rpl(vWH, 7);
    }
    if (j-0 == s2Len-1 && 0 <= i+0 && i+0 < s1Len) {
        col[(i+0)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 7);
    }
    if (i+1 == s1Len-1 && 0 <= j-1 && j-1 < s2Len) {
        row[j-1] = (int32_t)_mm256_extract_epi32_rpl(vWH, 6);
    }
    if (j-1 == s2Len-1 && 0 <= i+1 && i+1 < s1Len) {
        col[(i+1)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 6);
    }
    if (i+2 == s1Len-1 && 0 <= j-2 && j-2 < s2Len) {
        row[j-2] = (int32_t)_mm256_extract_epi32_rpl(vWH, 5);
    }
    if (j-2 == s2Len-1 && 0 <= i+2 && i+2 < s1Len) {
        col[(i+2)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 5);
    }
    if (i+3 == s1Len-1 && 0 <= j-3 && j-3 < s2Len) {
        row[j-3] = (int32_t)_mm256_extract_epi32_rpl(vWH, 4);
    }
    if (j-3 == s2Len-1 && 0 <= i+3 && i+3 < s1Len) {
        col[(i+3)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 4);
    }
    if (i+4 == s1Len-1 && 0 <= j-4 && j-4 < s2Len) {
        row[j-4] = (int32_t)_mm256_extract_epi32_rpl(vWH, 3);
    }
    if (j-4 == s2Len-1 && 0 <= i+4 && i+4 < s1Len) {
        col[(i+4)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 3);
    }
    if (i+5 == s1Len-1 && 0 <= j-5 && j-5 < s2Len) {
        row[j-5] = (int32_t)_mm256_extract_epi32_rpl(vWH, 2);
    }
    if (j-5 == s2Len-1 && 0 <= i+5 && i+5 < s1Len) {
        col[(i+5)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 2);
    }
    if (i+6 == s1Len-1 && 0 <= j-6 && j-6 < s2Len) {
        row[j-6] = (int32_t)_mm256_extract_epi32_rpl(vWH, 1);
    }
    if (j-6 == s2Len-1 && 0 <= i+6 && i+6 < s1Len) {
        col[(i+6)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 1);
    }
    if (i+7 == s1Len-1 && 0 <= j-7 && j-7 < s2Len) {
        row[j-7] = (int32_t)_mm256_extract_epi32_rpl(vWH, 0);
    }
    if (j-7 == s2Len-1 && 0 <= i+7 && i+7 < s1Len) {
        col[(i+7)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 0);
    }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
andq $-0x20, %rsp
subq $0x60, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
vmovdqa %ymm0, 0x20(%rsp)
movl %edx, 0x1c(%rsp)
movl %ecx, 0x18(%rsp)
movl %r8d, 0x14(%rsp)
movl %r9d, 0x10(%rsp)
movl 0x1c(%rsp), %eax
addl $0x0, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaece50
movl 0x14(%rsp), %ecx
subl $0x0, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaece50
movl 0x14(%rsp), %eax
subl $0x0, %eax
cmpl 0x10(%rsp), %eax
jge 0xaece50
movl 0x3c(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x0, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x0, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaece92
movl 0x1c(%rsp), %ecx
addl $0x0, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaece92
movl 0x1c(%rsp), %eax
addl $0x0, %eax
cmpl 0x18(%rsp), %eax
jge 0xaece92
movl 0x3c(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x0, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x1, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaeced4
movl 0x14(%rsp), %ecx
subl $0x1, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaeced4
movl 0x14(%rsp), %eax
subl $0x1, %eax
cmpl 0x10(%rsp), %eax
jge 0xaeced4
movl 0x38(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x1, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x1, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaecf16
movl 0x1c(%rsp), %ecx
addl $0x1, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaecf16
movl 0x1c(%rsp), %eax
addl $0x1, %eax
cmpl 0x18(%rsp), %eax
jge 0xaecf16
movl 0x38(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x1, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x2, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaecf58
movl 0x14(%rsp), %ecx
subl $0x2, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaecf58
movl 0x14(%rsp), %eax
subl $0x2, %eax
cmpl 0x10(%rsp), %eax
jge 0xaecf58
movl 0x34(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x2, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x2, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaecf9a
movl 0x1c(%rsp), %ecx
addl $0x2, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaecf9a
movl 0x1c(%rsp), %eax
addl $0x2, %eax
cmpl 0x18(%rsp), %eax
jge 0xaecf9a
movl 0x34(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x2, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x3, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaecfdc
movl 0x14(%rsp), %ecx
subl $0x3, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaecfdc
movl 0x14(%rsp), %eax
subl $0x3, %eax
cmpl 0x10(%rsp), %eax
jge 0xaecfdc
movl 0x30(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x3, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x3, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed01e
movl 0x1c(%rsp), %ecx
addl $0x3, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed01e
movl 0x1c(%rsp), %eax
addl $0x3, %eax
cmpl 0x18(%rsp), %eax
jge 0xaed01e
movl 0x30(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x3, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x4, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed060
movl 0x14(%rsp), %ecx
subl $0x4, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed060
movl 0x14(%rsp), %eax
subl $0x4, %eax
cmpl 0x10(%rsp), %eax
jge 0xaed060
movl 0x2c(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x4, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x4, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed0a2
movl 0x1c(%rsp), %ecx
addl $0x4, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed0a2
movl 0x1c(%rsp), %eax
addl $0x4, %eax
cmpl 0x18(%rsp), %eax
jge 0xaed0a2
movl 0x2c(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x4, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x5, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed0e4
movl 0x14(%rsp), %ecx
subl $0x5, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed0e4
movl 0x14(%rsp), %eax
subl $0x5, %eax
cmpl 0x10(%rsp), %eax
jge 0xaed0e4
movl 0x28(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x5, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x5, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed126
movl 0x1c(%rsp), %ecx
addl $0x5, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed126
movl 0x1c(%rsp), %eax
addl $0x5, %eax
cmpl 0x18(%rsp), %eax
jge 0xaed126
movl 0x28(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x5, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x6, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed168
movl 0x14(%rsp), %ecx
subl $0x6, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed168
movl 0x14(%rsp), %eax
subl $0x6, %eax
cmpl 0x10(%rsp), %eax
jge 0xaed168
movl 0x24(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x6, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x6, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed1aa
movl 0x1c(%rsp), %ecx
addl $0x6, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed1aa
movl 0x1c(%rsp), %eax
addl $0x6, %eax
cmpl 0x18(%rsp), %eax
jge 0xaed1aa
movl 0x24(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x6, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x1c(%rsp), %eax
addl $0x7, %eax
movl 0x18(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed1ec
movl 0x14(%rsp), %ecx
subl $0x7, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed1ec
movl 0x14(%rsp), %eax
subl $0x7, %eax
cmpl 0x10(%rsp), %eax
jge 0xaed1ec
movl 0x20(%rsp), %edx
movq 0x48(%rsp), %rax
movl 0x14(%rsp), %ecx
subl $0x7, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movl 0x14(%rsp), %eax
subl $0x7, %eax
movl 0x10(%rsp), %ecx
subl $0x1, %ecx
cmpl %ecx, %eax
jne 0xaed22e
movl 0x1c(%rsp), %ecx
addl $0x7, %ecx
xorl %eax, %eax
cmpl %ecx, %eax
jg 0xaed22e
movl 0x1c(%rsp), %eax
addl $0x7, %eax
cmpl 0x18(%rsp), %eax
jge 0xaed22e
movl 0x20(%rsp), %edx
movq 0x40(%rsp), %rax
movl 0x1c(%rsp), %ecx
addl $0x7, %ecx
movslq %ecx, %rcx
movl %edx, (%rax,%rcx,4)
movq %rbp, %rsp
popq %rbp
vzeroupper
retq
nopw %cs:(%rax,%rax)