// File: NishadSaraf[P]Championship-Simulator/src/drc_controller.cc
// Function: DRC_MEMORY_CONTROLLER::return_data(PACKET*)
void DRC_MEMORY_CONTROLLER::return_data(PACKET *packet)
{
    // check MSHR information
    int mshr_index = check_mshr(packet);

    // sanity check
    if (mshr_index == -1) {
        cerr << "[" << NAME << "_MSHR] " << __func__ << " instr_id: " << packet->instr_id << " cannot find a matching entry!";
        cerr << " full_addr: " << hex << packet->full_addr;
        cerr << " address: " << packet->address << dec;
        cerr << " event: " << packet->event_cycle << " current: " << current_core_cycle[packet->cpu] << endl;
        assert(0);
    }

    // MSHR holds the most updated information about this request
    // no need to do memcpy
    MSHR.num_returned++;
    MSHR.entry[mshr_index].returned = COMPLETED;
    MSHR.entry[mshr_index].data = packet->data;

    // ADD LATENCY
    MSHR.entry[mshr_index].event_cycle = current_core_cycle[packet->cpu];
    packet->event_cycle = current_core_cycle[packet->cpu];
    /*
    if (MSHR.entry[mshr_index].event_cycle < current_core_cycle[packet->cpu])
        MSHR.entry[mshr_index].event_cycle = current_core_cycle[packet->cpu] + LATENCY;
    else
        MSHR.entry[mshr_index].event_cycle += LATENCY;
    */

    // we need to immediately return these data to upper level memory
    // if we don't, it takes a very long time to 
    // 1) change the DRC mode from read to write
    // 2) fill in missing cache blocks in DRC
    // 3) finally return data to upper level cache
    // which eventually stalls the main core pipeline

    // FIXME: need to consider DRC dbus congestion
    // first add it to the wq and make one more function that can return data to on-chip caches

    // check fill level
    if (packet->fill_level < fill_level) {

        if (packet->instruction) 
            upper_level_icache[packet->cpu]->return_data(packet);
        else // data
            upper_level_dcache[packet->cpu]->return_data(packet);

        // since it is now returned to the upper level memory we must reset the fill_level
        // if we don't, when the DRC mode changes to the write mode and this block gets filled in the DRC
        // it will try to retun data again to the upper level memory
        packet->fill_level = FILL_DRC;
    }

    // before we add returned packet to DRC WQ, we must reset scheduled bit in this packet
    // since this packet once scheduled while it was sitting in DRC RQ to be processed
    packet->scheduled = 0;

    // add it to the WQ
    add_wq(packet); 
    update_schedule_cycle(&WQ);

    // even though it is not filled in the DRC yet, we can safely release MSHR resource
    MSHR.remove_queue(&MSHR.entry[mshr_index]);

    DP (if (warmup_complete[packet->cpu]) {
    cout << "[" << NAME << "_MSHR] " <<  __func__ << " instr_id: " << MSHR.entry[mshr_index].instr_id;
    cout << " address: " << hex << MSHR.entry[mshr_index].address << " full_addr: " << MSHR.entry[mshr_index].full_addr;
    cout << " data: " << MSHR.entry[mshr_index].data << dec << " num_returned: " << MSHR.num_returned;
    cout << " index: " << mshr_index << " occupancy: " << MSHR.occupancy;
    cout << " event: " << MSHR.entry[mshr_index].event_cycle << " current: " << current_core_cycle[packet->cpu] << " next: " << MSHR.next_fill_cycle << endl; });
}

// Assembly:
subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x18(%rsp), %rsi
callq 0x217f0
movl %eax, 0x14(%rsp)
cmpl $-0x1, 0x14(%rsp)
jne 0x21e78
movq 0x72d8(%rip), %rdi      # 0x28ff0
leaq 0x130e(%rip), %rsi      # 0x2302d
callq 0x3220
movq 0x8(%rsp), %rsi
movq %rax, %rdi
addq $0x7348, %rsi           # imm = 0x7348
callq 0x31c0
movq %rax, %rdi
leaq 0x14fa(%rip), %rsi      # 0x2323c
callq 0x3220
movq %rax, %rdi
leaq 0x14f3(%rip), %rsi      # 0x23244
callq 0x3220
movq %rax, %rdi
leaq 0x20bf(%rip), %rsi      # 0x23e1f
callq 0x3220
movq %rax, %rdi
movq 0x18(%rsp), %rax
movq 0x368(%rax), %rsi
callq 0x3080
movq %rax, %rdi
leaq 0x14cd(%rip), %rsi      # 0x23250
callq 0x3220
movq 0x7261(%rip), %rdi      # 0x28ff0
leaq 0x1395(%rip), %rsi      # 0x2312b
callq 0x3220
movq %rax, %rdi
leaq -0x184f5(%rip), %rsi    # 0x98b0
callq 0x30d0
movq %rax, %rdi
movq 0x18(%rsp), %rax
movq 0x348(%rax), %rsi
callq 0x3080
movq 0x722b(%rip), %rdi      # 0x28ff0
leaq 0x1354(%rip), %rsi      # 0x23120
callq 0x3220
movq %rax, %rdi
movq 0x18(%rsp), %rax
movq 0x340(%rax), %rsi
callq 0x3080
movq %rax, %rdi
leaq -0x1851f(%rip), %rsi    # 0x98d0
callq 0x30d0
movq 0x71f5(%rip), %rdi      # 0x28ff0
leaq 0x1336(%rip), %rsi      # 0x23138
callq 0x3220
movq %rax, %rdi
movq 0x18(%rsp), %rax
movq 0x378(%rax), %rsi
callq 0x3080
movq %rax, %rdi
leaq 0x144a(%rip), %rsi      # 0x2326f
callq 0x3220
movq %rax, %rdi
movq 0x18(%rsp), %rax
movl 0x330(%rax), %eax
movl %eax, %ecx
leaq 0x6e07f(%rip), %rax     # 0x8fec0
movq (%rax,%rcx,8), %rsi
callq 0x3080
movq %rax, %rdi
movq 0x7164(%rip), %rsi      # 0x28fb8
callq 0x3250
leaq 0x11a4(%rip), %rdi      # 0x23004
leaq 0x2108(%rip), %rsi      # 0x23f6f
movl $0x381, %edx            # imm = 0x381
leaq 0x21f7(%rip), %rcx      # 0x2406a
callq 0x3160
movq 0x8(%rsp), %rcx
movl 0x4073a8(%rcx), %eax
addl $0x1, %eax
movl %eax, 0x4073a8(%rcx)
movq 0x407408(%rcx), %rax
movslq 0x14(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movb $0x2, 0x32c(%rax)
movq 0x18(%rsp), %rax
movq 0x360(%rax), %rdx
movq 0x407408(%rcx), %rax
movslq 0x14(%rsp), %rsi
imulq $0x380, %rsi, %rsi      # imm = 0x380
addq %rsi, %rax
movq %rdx, 0x360(%rax)
movq 0x18(%rsp), %rax
movl 0x330(%rax), %eax
movl %eax, %edx
leaq 0x6dfda(%rip), %rax     # 0x8fec0
movq (%rax,%rdx,8), %rdx
movq 0x407408(%rcx), %rax
movslq 0x14(%rsp), %rsi
imulq $0x380, %rsi, %rsi      # imm = 0x380
addq %rsi, %rax
movq %rdx, 0x378(%rax)
movq 0x18(%rsp), %rax
movl 0x330(%rax), %eax
movl %eax, %edx
leaq 0x6dfa5(%rip), %rax     # 0x8fec0
movq (%rax,%rdx,8), %rdx
movq 0x18(%rsp), %rax
movq %rdx, 0x378(%rax)
movq 0x18(%rsp), %rax
movl 0x8(%rax), %eax
cmpl 0x40946c(%rcx), %eax
jge 0x21f93
movq 0x18(%rsp), %rax
cmpb $0x0, (%rax)
je 0x21f67
movq 0x8(%rsp), %rax
movq 0x18(%rsp), %rcx
movl 0x330(%rcx), %ecx
movq 0x8(%rax,%rcx,8), %rdi
movq 0x18(%rsp), %rsi
movq (%rdi), %rax
callq *0x18(%rax)
jmp 0x21f87
movq 0x8(%rsp), %rax
movq 0x18(%rsp), %rcx
movl 0x330(%rcx), %ecx
movq 0x10(%rax,%rcx,8), %rdi
movq 0x18(%rsp), %rsi
movq (%rdi), %rax
callq *0x18(%rax)
movq 0x18(%rsp), %rax
movl $0x8, 0x8(%rax)
movq 0x8(%rsp), %rdi
movq 0x18(%rsp), %rax
movb $0x0, 0x2(%rax)
movq 0x18(%rsp), %rsi
movq (%rdi), %rax
callq *0x8(%rax)
movq 0x8(%rsp), %rdi
movq %rdi, %rsi
addq $0x40a870, %rsi         # imm = 0x40A870
callq 0x1e6f0
movq 0x8(%rsp), %rax
movq %rax, %rdi
addq $0x407370, %rdi         # imm = 0x407370
movq 0x407408(%rax), %rsi
movslq 0x14(%rsp), %rax
imulq $0x380, %rax, %rax      # imm = 0x380
addq %rax, %rsi
callq 0x150e0
addq $0x28, %rsp
retq
nop