// File: /workspace/github_c_makefile_star2_O2/xiane[P]libvphevcodec/AML_HEVCEncoder.cpp
// Function: Wave4VpuEncFiniSeq(AMVHEVCEncHandle_s*)
AMVEnc_Status Wave4VpuEncFiniSeq(AMVHEVCEncHandle *Handle) {
    Uint32 temp;
    VLOG(0, "Wave4VpuEncFiniSeq enter\n");
    temp = VpuReadReg(Handle->instance_id, W4_ADDR_WORK_BASE);
    VLOG(DEBUG, "W4_ADDR_WORK_BASE %x\n", temp);
    temp = VpuReadReg(Handle->instance_id, W4_WORK_SIZE);
    VLOG(DEBUG, "W4_WORK_SIZE %x\n", temp);

    VpuWriteReg(Handle->instance_id, W4_ADDR_WORK_BASE, Handle->work_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_WORK_SIZE, Handle->work_vb.size);
    VpuWriteReg(Handle->instance_id, W4_WORK_PARAM, 0);

    VpuWriteReg(Handle->instance_id, W4_VPU_BUSY_STATUS, 1);
    VpuWriteReg(Handle->instance_id, W4_RET_SUCCESS, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_CORE_INDEX, 0);
    VpuWriteReg(Handle->instance_id, W4_INST_INDEX, (Handle->instance_id & 0xffff) | (1 << 16));
    VpuWriteReg(Handle->instance_id, W4_COMMAND, FINI_SEQ);
    VpuWriteReg(Handle->instance_id, W4_VPU_HOST_INT_REQ, 1);
    //Wave4BitIssueCommand(0,4, FINI_SEQ);
    temp = VpuReadReg(Handle->instance_id, W4_VPU_BUSY_STATUS);
    VLOG(DEBUG, "W4_VPU_BUSY_STATUS :0x%x\n", temp);
    if (vdi_wait_interrupt(Handle->instance_id, VPU_BUSY_CHECK_TIMEOUT) == -1) {
        //vdi_free_dma_memory(0, &vb);
        VLOG(ERR, "Wave4VpuEncFiniSeq error time out\n");
        return AMVENC_TIMEOUT;
    }
    //if (vdi_wait_vpu_busy(0, VPU_BUSY_CHECK_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
    //     return AMVENC_TIMEOUT;
    temp = VpuReadReg(Handle->instance_id, W4_RET_SUCCESS);
    VLOG(DEBUG, "W4_RET_SUCCESS %x\n", temp);
    VLOG(DEBUG, "Wave4VpuEncFiniSeq ret\n");
    if (VpuReadReg(Handle->instance_id, W4_RET_SUCCESS) == 0) {
        uint32_t reasonCode = VpuReadReg(Handle->instance_id, W4_RET_FAIL_REASON);
        VLOG(ERR, "Wave4VpuEncFiniSeq failedREASON CODE(%08x)\n", reasonCode);
        return AMVENC_HARDWARE;
    }
    VLOG(DEBUG, "Wave4VpuEncFiniSeq succes\n");
    return AMVENC_SUCCESS;
}

// Assembly:
pushq %rbp
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl (%rdi), %edi
movl $0x138, %esi            # imm = 0x138
callq 0x2210
movl (%rbx), %edi
movl $0x13c, %esi            # imm = 0x13C
callq 0x2210
movl (%rbx), %edi
movl 0x48(%rbx), %edx
movl $0x138, %esi            # imm = 0x138
callq 0x2160
movl (%rbx), %edi
movl 0x40(%rbx), %edx
movl $0x13c, %esi            # imm = 0x13C
callq 0x2160
movl (%rbx), %edi
movl $0x140, %esi            # imm = 0x140
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x70
popq %r14
pushq $0x1
popq %rbp
movl %r14d, %esi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x104, %esi            # imm = 0x104
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movzwl %di, %edx
orl $0x10000, %edx          # imm = 0x10000
movl $0x108, %esi            # imm = 0x108
callq 0x2160
movl (%rbx), %edi
pushq $0x4
popq %rdx
movl $0x100, %esi            # imm = 0x100
callq 0x2160
movl (%rbx), %edi
pushq $0x38
popq %rsi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl %r14d, %esi
callq 0x2210
movl (%rbx), %edi
movl $0x1388, %esi           # imm = 0x1388
callq 0x2360
cmpl $-0x1, %eax
je 0x62f7
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2210
testl %eax, %eax
jne 0x630e
movl (%rbx), %edi
movl $0x114, %esi            # imm = 0x114
callq 0x2210
leaq 0x25c95(%rip), %rdi     # 0x2bf7f
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
pushq $-0x25
jmp 0x6305
leaq 0x25fe5(%rip), %rdi     # 0x2c2e3
callq 0x2290
pushq $-0x24
popq %rbp
pushq $0xa
popq %rdi
callq 0x2230
movl %ebp, %eax
popq %rbx
popq %r14
popq %rbp
retq