// File: /workspace/github_c_makefile_star2_O0/hamsternz[P]emulate-risc-v/riscv.c
// Function: op_unified
static int op_unified(void) {
  uint32_t op1, op2, res, csr_res; 
  uint32_t pc_next_i, pc_cond_jump, pc_rel_jump, pc_indirect; 

  /*******************************************************
   * Build local variables based on global state 
   ******************************************************/
  /* Options for next PC value */
  pc_next_i    = pc + 4;
  pc_cond_jump = pc + broffset;
  pc_rel_jump  = pc + jmpoffset;
  pc_indirect  = (regs[rs1] + imm12) & (~1);

  /* Operands */
  op1 = regs[rs1];
  op2 = op->op2_immediate ? imm12 : regs[rs2];

  /* Find the results */
  switch(op->alu_mode) {
    case ALU_ADD:    res = op1 + op2;                                               break;
    case ALU_SUB:    res = op1 - op2;                                               break;
    case ALU_SLL:    res = op1 << (op2 & 0x1f);                                     break;
    case ALU_XOR:    res = op1 ^ op2;                                               break;
    case ALU_SRL:    res = (uint32_t)op1 >> (op2 & 0x1f);                           break;
    case ALU_SRA:    res =  (int32_t)op1 >> (op2 & 0x1f);                           break;
    case ALU_OR:     res = op1 | op2;                                               break;
    case ALU_AND:    res = op1 & op2;                                               break;
  
    case ALU_SEQ:    res = (op1 == op2)                     ? 1 : 0;                break;
    case ALU_SLT:    res = ((int32_t)  op1 <  (int32_t)op2) ? 1 : 0;                break;
    case ALU_SLTU:   res = ((uint32_t) op1 < (uint32_t)op2) ? 1 : 0;                break;

    case ALU_MUL:    res = ((uint64_t)op1 * (uint64_t)op2);                         break;
    case ALU_MULH:   res = ( (int64_t)op1 *  (int64_t)op2) >> 32;                   break;
    case ALU_MULHSU: res = ( (int64_t)op1 * (uint64_t)op2) >> 32;                   break;
    case ALU_MULHU:  res = ((uint64_t)op1 * (uint64_t)op2) >> 32;                   break;
    case ALU_DIV:    res = (op2 == 0) ? 0xFFFFFFFF : (int32_t)op1 / (int32_t)op2;   break;
    case ALU_DIVU:   res = (op2 == 0) ? 0xFFFFFFFF : (uint32_t)op1 / (uint32_t)op2; break;
    case ALU_REM:    res = (op2 == 0) ? 0xFFFFFFFF : (int32_t)op1 % (int32_t)op2;   break;
    case ALU_REMU:   res = (op2 == 0) ? 0xFFFFFFFF : (uint32_t)op1 % (uint32_t)op2; break;

    // Maybe seperate
    case ALU_NEXT_I: res = pc_next_i;                                             break;
    case ALU_PC_U20: res = pc + upper20;                                          break;
    case ALU_U20:    res = upper20;                                               break;
    case ALU_CSR:    res = csr[csrid];                                            break;
    default:         res = 0;                                                     break; 
  }

  switch(op->csr_mode) {
    case CSR_RW:  csr_res = regs[rs1];               break;
    case CSR_RS:  csr_res = csr[csrid] | regs[rs1];  break;
    case CSR_RC:  csr_res = csr[csrid] & ~regs[rs1]; break;
    case CSR_RWI: csr_res = uimm;                    break;
    case CSR_RSI: csr_res = csr[csrid] | uimm;       break;
    case CSR_RCI: csr_res = csr[csrid] & ~uimm;      break;
    default:      csr_res = 0;                       break;
  }

  if(op->csr_mode != CSR_NOP) { 
    char buffer[100];
    sprintf(buffer,"CSR 0x%03x accessed",csrid);
    display_log(buffer);
  }

  /* And now do the write */
  if(op->memory_mode == MEM_STORE) {
    if(memory_write_full()) {
      stalled = 1;
    } else {
      uint32_t addr;
      int unaligned = 0;
      addr = regs[rs1]+imm12wr;
      stalled = 0;

      switch(addr & 3) {
        case 1:
          if(op->memory_mask  == 0xFFFFFFFF) {
            unaligned = 1;
          }
          break;
        case 2:
          if(op->memory_mask  == 0xFFFFFFFF) {
            unaligned = 1;
          }
          break;
        case 3:
          if(op->memory_mask  != 0xFF) {
            unaligned = 1;
          }
          break;
      }
      if(unaligned) {
        char buffer[100];
        sprintf(buffer,"Unaligned write at %08x %08x",addr, op->memory_mask);
        display_log(buffer);
      }

      if(!memory_write_request(addr, op->memory_mask, regs[rs2])) {
        return 0;
      }
    }
  }
  
  /* do we need to do a load? */
  if(op->memory_mode == MEM_LOAD) {
    if(rd != 0) {
      if(!read_dispatched) {
        uint32_t addr;
        int unaligned = 0;
        addr = regs[rs1]+imm12;
        stalled = 1;

        switch(addr & 3) {
          case 1:
            if(op->memory_mask  == 0xFFFFFFFF) {
              unaligned = 1;
            }
            break;
          case 2:
            if(op->memory_mask  == 0xFFFFFFFF) {
              unaligned = 1;
            }
            break;
          case 3:
            if(op->memory_mask  != 0xFF) {
              unaligned = 1;
            }
            break;
        }
        if(unaligned) {
          char buffer[100];
          sprintf(buffer,"Unaligned read at %08x %08x",addr, op->memory_mask);
          display_log(buffer);
        }

        if(memory_read_request(regs[rs1]+imm12)) {
          read_dispatched = 1;
        } 
        /* Unable to queue request -  will retry */
      } else {
        /* To get here we are stalled waiting for data */
        if(!memory_read_data_empty())  {
          stalled = 0;
          res = memory_read_data() & op->memory_mask;
          /* Sign extend */
          res |= (res & op->load_sign_check) ? ~op->memory_mask : 0;
        }
      }
    }
  }

  /******************************************************************
   * All assignments from local to global state variables below here
   *****************************************************************/

  /* Store the results? */
  if(!stalled) {
    if(op->store_result && rd != 0)
      regs[rd] = res;

    /* Any CSR updates? */
    switch(op->csr_mode) {
      case CSR_RW:  if(rs1 != 0) csr[csrid] = csr_res;  break;
      case CSR_RS:  if(rs1 != 0) csr[csrid] = csr_res;  break;
      case CSR_RC:  if(rs1 != 0) csr[csrid] = csr_res;  break;
      case CSR_RWI: csr[csrid] = csr_res;               break;
      case CSR_RSI: csr[csrid] = csr_res;               break;
      case CSR_RCI: csr[csrid] = csr_res;               break;
      default:                                          break;
    }

    /* Which instruction next? */
    switch(op->pc_mode) {
      case PC_NEXT_I:        pc = pc_next_i;                      break;
      case PC_COND_JUMP:     pc = res ? pc_cond_jump : pc_next_i; break;
      case PC_COND_JUMP_INV: pc = res ? pc_next_i : pc_cond_jump; break;
      case PC_REL_JUMP:      pc = pc_rel_jump;                    break;
      case PC_INDIRECT:      pc = pc_indirect;                    break;
      default:                                                    break;
    }
  }
  return 1;
}

// Assembly:
subq $0x1b8, %rsp            # imm = 0x1B8
movl 0xb5b3(%rip), %eax      # 0xea00
addl $0x4, %eax
movl %eax, 0x1a0(%rsp)
movl 0xb5a3(%rip), %eax      # 0xea00
addl 0xf659(%rip), %eax      # 0x12abc
movl %eax, 0x19c(%rsp)
movl 0xb590(%rip), %eax      # 0xea00
addl 0xf64a(%rip), %eax      # 0x12ac0
movl %eax, 0x198(%rsp)
movzbl 0xf640(%rip), %eax      # 0x12ac4
movl %eax, %ecx
leaq 0xf593(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %eax
addl 0xf632(%rip), %eax      # 0x12ac8
andl $-0x2, %eax
movl %eax, 0x194(%rsp)
movzbl 0xf61d(%rip), %eax      # 0x12ac4
movl %eax, %ecx
leaq 0xf570(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %eax
movl %eax, 0x1b0(%rsp)
movq 0xf5e7(%rip), %rax      # 0x12aa8
movzbl 0x10(%rax), %eax
cmpl $0x0, %eax
je 0x34d6
movl 0xf5f8(%rip), %eax      # 0x12ac8
movl %eax, 0x4c(%rsp)
jmp 0x34ed
movzbl 0xf5ef(%rip), %eax      # 0x12acc
movl %eax, %ecx
leaq 0xf53a(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %eax
movl %eax, 0x4c(%rsp)
movl 0x4c(%rsp), %eax
movl %eax, 0x1ac(%rsp)
movq 0xf5a9(%rip), %rax      # 0x12aa8
movzbl 0x11(%rax), %eax
movq %rax, 0x40(%rsp)
subq $0x16, %rax
ja 0x382a
movq 0x40(%rsp), %rax
leaq 0x6b8e(%rip), %rcx      # 0xa0ac
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl 0x1b0(%rsp), %eax
addl 0x1ac(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
subl 0x1ac(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
andl $0x1f, %ecx
shll %cl, %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
xorl 0x1ac(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
andl $0x1f, %ecx
shrl %cl, %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
andl $0x1f, %ecx
sarl %cl, %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
orl 0x1ac(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
andl 0x1ac(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %edx
movl 0x1ac(%rsp), %esi
xorl %eax, %eax
movl $0x1, %ecx
cmpl %esi, %edx
cmovel %ecx, %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %edx
movl 0x1ac(%rsp), %esi
xorl %eax, %eax
movl $0x1, %ecx
cmpl %esi, %edx
cmovll %ecx, %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %edx
movl 0x1ac(%rsp), %esi
xorl %eax, %eax
movl $0x1, %ecx
cmpl %esi, %edx
cmovbl %ecx, %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
imulq %rcx, %rax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
imulq %rcx, %rax
sarq $0x20, %rax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
imulq %rcx, %rax
shrq $0x20, %rax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1b0(%rsp), %eax
movl 0x1ac(%rsp), %ecx
imulq %rcx, %rax
shrq $0x20, %rax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
cmpl $0x0, 0x1ac(%rsp)
jne 0x3711
movl $0xffffffff, %eax       # imm = 0xFFFFFFFF
movl %eax, 0x3c(%rsp)
jmp 0x3724
movl 0x1b0(%rsp), %eax
cltd
idivl 0x1ac(%rsp)
movl %eax, 0x3c(%rsp)
movl 0x3c(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
cmpl $0x0, 0x1ac(%rsp)
jne 0x3749
movl $0xffffffff, %eax       # imm = 0xFFFFFFFF
movl %eax, 0x38(%rsp)
jmp 0x375d
movl 0x1b0(%rsp), %eax
xorl %edx, %edx
divl 0x1ac(%rsp)
movl %eax, 0x38(%rsp)
movl 0x38(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
cmpl $0x0, 0x1ac(%rsp)
jne 0x3782
movl $0xffffffff, %edx       # imm = 0xFFFFFFFF
movl %edx, 0x34(%rsp)
jmp 0x3795
movl 0x1b0(%rsp), %eax
cltd
idivl 0x1ac(%rsp)
movl %edx, 0x34(%rsp)
movl 0x34(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
cmpl $0x0, 0x1ac(%rsp)
jne 0x37ba
movl $0xffffffff, %edx       # imm = 0xFFFFFFFF
movl %edx, 0x30(%rsp)
jmp 0x37ce
movl 0x1b0(%rsp), %eax
xorl %edx, %edx
divl 0x1ac(%rsp)
movl %edx, 0x30(%rsp)
movl 0x30(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0x1a0(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0xb20f(%rip), %eax      # 0xea00
addl 0xf2bd(%rip), %eax      # 0x12ab4
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0xf2ae(%rip), %eax      # 0x12ab4
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl 0xf2bb(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xb1f2(%rip), %rax      # 0xea10
movl (%rax,%rcx,4), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3835
movl $0x0, 0x1a8(%rsp)
movq 0xf26c(%rip), %rax      # 0x12aa8
movzbl 0x14(%rax), %eax
decl %eax
movl %eax, %ecx
movq %rcx, 0x28(%rsp)
subl $0x5, %eax
ja 0x3940
movq 0x28(%rsp), %rax
leaq 0x68aa(%rip), %rcx      # 0xa108
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movzbl 0xf256(%rip), %eax      # 0x12ac4
movl %eax, %ecx
leaq 0xf1a9(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %eax
movl %eax, 0x1a4(%rsp)
jmp 0x394b
movl 0xf244(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xb17b(%rip), %rax      # 0xea10
movl (%rax,%rcx,4), %eax
movzbl 0xf225(%rip), %ecx      # 0x12ac4
movl %ecx, %edx
leaq 0xf178(%rip), %rcx      # 0x12a20
orl (%rcx,%rdx,4), %eax
movl %eax, 0x1a4(%rsp)
jmp 0x394b
movl 0xf213(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xb14a(%rip), %rax      # 0xea10
movl (%rax,%rcx,4), %eax
movzbl 0xf1f4(%rip), %ecx      # 0x12ac4
movl %ecx, %edx
leaq 0xf147(%rip), %rcx      # 0x12a20
movl (%rcx,%rdx,4), %ecx
xorl $-0x1, %ecx
andl %ecx, %eax
movl %eax, 0x1a4(%rsp)
jmp 0x394b
movl 0xf1e4(%rip), %eax      # 0x12ad4
movl %eax, 0x1a4(%rsp)
jmp 0x394b
movl 0xf1d1(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xb108(%rip), %rax      # 0xea10
movl (%rax,%rcx,4), %eax
orl 0xf1c3(%rip), %eax      # 0x12ad4
movl %eax, 0x1a4(%rsp)
jmp 0x394b
movl 0xf1b0(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xb0e7(%rip), %rax      # 0xea10
movl (%rax,%rcx,4), %eax
movl 0xf1a2(%rip), %ecx      # 0x12ad4
xorl $-0x1, %ecx
andl %ecx, %eax
movl %eax, 0x1a4(%rsp)
jmp 0x394b
movl $0x0, 0x1a4(%rsp)
movq 0xf156(%rip), %rax      # 0x12aa8
movzbl 0x14(%rax), %eax
cmpl $0x0, %eax
je 0x3984
leaq 0x130(%rsp), %rdi
movl 0xf167(%rip), %edx      # 0x12ad0
leaq 0x6f6a(%rip), %rsi      # 0xa8da
movb $0x0, %al
callq 0x21e0
leaq 0x130(%rsp), %rdi
callq 0x6b20
movq 0xf11d(%rip), %rax      # 0x12aa8
movzbl 0x15(%rax), %eax
cmpl $0x2, %eax
jne 0x3ade
callq 0x8fe0
cmpl $0x0, %eax
je 0x39ae
movb $0x1, 0xf10f(%rip)      # 0x12ab8
jmp 0x3adc
movl $0x0, 0x128(%rsp)
movzbl 0xf104(%rip), %eax      # 0x12ac4
movl %eax, %ecx
leaq 0xf057(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %eax
movl 0xf106(%rip), %ecx      # 0x12ad8
addl %ecx, %eax
movl %eax, 0x12c(%rsp)
movb $0x0, 0xf0d6(%rip)      # 0x12ab8
movl 0x12c(%rsp), %eax
andl $0x3, %eax
movl %eax, 0x24(%rsp)
subl $0x1, %eax
je 0x3a0d
jmp 0x39f7
movl 0x24(%rsp), %eax
subl $0x2, %eax
je 0x3a27
jmp 0x3a02
movl 0x24(%rsp), %eax
subl $0x3, %eax
je 0x3a41
jmp 0x3a5e
movq 0xf094(%rip), %rax      # 0x12aa8
cmpl $-0x1, 0x18(%rax)
jne 0x3a25
movl $0x1, 0x128(%rsp)
jmp 0x3a5e
movq 0xf07a(%rip), %rax      # 0x12aa8
cmpl $-0x1, 0x18(%rax)
jne 0x3a3f
movl $0x1, 0x128(%rsp)
jmp 0x3a5e
movq 0xf060(%rip), %rax      # 0x12aa8
cmpl $0xff, 0x18(%rax)
je 0x3a5c
movl $0x1, 0x128(%rsp)
jmp 0x3a5e
cmpl $0x0, 0x128(%rsp)
je 0x3a9c
leaq 0xc0(%rsp), %rdi
movl 0x12c(%rsp), %edx
movq 0xf02a(%rip), %rax      # 0x12aa8
movl 0x18(%rax), %ecx
leaq 0x6e66(%rip), %rsi      # 0xa8ee
movb $0x0, %al
callq 0x21e0
leaq 0xc0(%rsp), %rdi
callq 0x6b20
movl 0x12c(%rsp), %edi
movq 0xeffe(%rip), %rax      # 0x12aa8
movl 0x18(%rax), %esi
movzbl 0xf018(%rip), %eax      # 0x12acc
movl %eax, %ecx
leaq 0xef63(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %edx
callq 0x8ff0
cmpl $0x0, %eax
jne 0x3ada
movl $0x0, 0x1b4(%rsp)
jmp 0x3e97
jmp 0x3adc
jmp 0x3ade
movq 0xefc3(%rip), %rax      # 0x12aa8
movzbl 0x15(%rax), %eax
cmpl $0x1, %eax
jne 0x3c93
movzbl 0xefb7(%rip), %eax      # 0x12ab0
cmpl $0x0, %eax
je 0x3c91
cmpb $0x0, 0xefd3(%rip)      # 0x12adc
jne 0x3c23
movl $0x0, 0xb8(%rsp)
movzbl 0xefa3(%rip), %eax      # 0x12ac4
movl %eax, %ecx
leaq 0xeef6(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %eax
movl 0xef95(%rip), %ecx      # 0x12ac8
addl %ecx, %eax
movl %eax, 0xbc(%rsp)
movb $0x1, 0xef75(%rip)      # 0x12ab8
movl 0xbc(%rsp), %eax
andl $0x3, %eax
movl %eax, 0x20(%rsp)
subl $0x1, %eax
je 0x3b6e
jmp 0x3b58
movl 0x20(%rsp), %eax
subl $0x2, %eax
je 0x3b88
jmp 0x3b63
movl 0x20(%rsp), %eax
subl $0x3, %eax
je 0x3ba2
jmp 0x3bbf
movq 0xef33(%rip), %rax      # 0x12aa8
cmpl $-0x1, 0x18(%rax)
jne 0x3b86
movl $0x1, 0xb8(%rsp)
jmp 0x3bbf
movq 0xef19(%rip), %rax      # 0x12aa8
cmpl $-0x1, 0x18(%rax)
jne 0x3ba0
movl $0x1, 0xb8(%rsp)
jmp 0x3bbf
movq 0xeeff(%rip), %rax      # 0x12aa8
cmpl $0xff, 0x18(%rax)
je 0x3bbd
movl $0x1, 0xb8(%rsp)
jmp 0x3bbf
cmpl $0x0, 0xb8(%rsp)
je 0x3bf7
leaq 0x50(%rsp), %rdi
movl 0xbc(%rsp), %edx
movq 0xeecc(%rip), %rax      # 0x12aa8
movl 0x18(%rax), %ecx
leaq 0x6d25(%rip), %rsi      # 0xa90b
movb $0x0, %al
callq 0x21e0
leaq 0x50(%rsp), %rdi
callq 0x6b20
movzbl 0xeec6(%rip), %eax      # 0x12ac4
movl %eax, %ecx
leaq 0xee19(%rip), %rax      # 0x12a20
movl (%rax,%rcx,4), %edi
addl 0xeeb8(%rip), %edi      # 0x12ac8
callq 0x8da0
cmpl $0x0, %eax
je 0x3c21
movb $0x1, 0xeebb(%rip)      # 0x12adc
jmp 0x3c8f
callq 0x8ea0
cmpl $0x0, %eax
jne 0x3c8d
movb $0x0, 0xee84(%rip)      # 0x12ab8
callq 0x8ec0
movq 0xee68(%rip), %rcx      # 0x12aa8
andl 0x18(%rcx), %eax
movl %eax, 0x1a8(%rsp)
movl 0x1a8(%rsp), %eax
movq 0xee50(%rip), %rcx      # 0x12aa8
andl 0x1c(%rcx), %eax
cmpl $0x0, %eax
je 0x3c73
movq 0xee41(%rip), %rax      # 0x12aa8
movl 0x18(%rax), %eax
xorl $-0x1, %eax
movl %eax, 0x1c(%rsp)
jmp 0x3c7b
xorl %eax, %eax
movl %eax, 0x1c(%rsp)
jmp 0x3c7b
movl 0x1c(%rsp), %eax
orl 0x1a8(%rsp), %eax
movl %eax, 0x1a8(%rsp)
jmp 0x3c8f
jmp 0x3c91
jmp 0x3c93
cmpb $0x0, 0xee1e(%rip)      # 0x12ab8
jne 0x3e8c
movq 0xee01(%rip), %rax      # 0x12aa8
movzbl 0x12(%rax), %eax
cmpl $0x0, %eax
je 0x3cd6
movzbl 0xedf9(%rip), %eax      # 0x12ab0
cmpl $0x0, %eax
je 0x3cd6
movl 0x1a8(%rsp), %edx
movzbl 0xede6(%rip), %eax      # 0x12ab0
movl %eax, %ecx
leaq 0xed4d(%rip), %rax      # 0x12a20
movl %edx, (%rax,%rcx,4)
movq 0xedcb(%rip), %rax      # 0x12aa8
movzbl 0x14(%rax), %eax
decl %eax
movl %eax, %ecx
movq %rcx, 0x10(%rsp)
subl $0x5, %eax
ja 0x3dd1
movq 0x10(%rsp), %rax
leaq 0x6421(%rip), %rcx      # 0xa120
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movzbl 0xedb5(%rip), %eax      # 0x12ac4
cmpl $0x0, %eax
je 0x3d2d
movl 0x1a4(%rsp), %edx
movl 0xedaf(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xace6(%rip), %rax      # 0xea10
movl %edx, (%rax,%rcx,4)
jmp 0x3dd3
movzbl 0xed8b(%rip), %eax      # 0x12ac4
cmpl $0x0, %eax
je 0x3d57
movl 0x1a4(%rsp), %edx
movl 0xed85(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xacbc(%rip), %rax      # 0xea10
movl %edx, (%rax,%rcx,4)
jmp 0x3dd3
movzbl 0xed64(%rip), %eax      # 0x12ac4
cmpl $0x0, %eax
je 0x3d7e
movl 0x1a4(%rsp), %edx
movl 0xed5e(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xac95(%rip), %rax      # 0xea10
movl %edx, (%rax,%rcx,4)
jmp 0x3dd3
movl 0x1a4(%rsp), %edx
movl 0xed43(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xac7a(%rip), %rax      # 0xea10
movl %edx, (%rax,%rcx,4)
jmp 0x3dd3
movl 0x1a4(%rsp), %edx
movl 0xed28(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xac5f(%rip), %rax      # 0xea10
movl %edx, (%rax,%rcx,4)
jmp 0x3dd3
movl 0x1a4(%rsp), %edx
movl 0xed0d(%rip), %eax      # 0x12ad0
movl %eax, %ecx
leaq 0xac44(%rip), %rax      # 0xea10
movl %edx, (%rax,%rcx,4)
jmp 0x3dd3
jmp 0x3dd3
movq 0xecce(%rip), %rax      # 0x12aa8
movzbl 0x13(%rax), %eax
movq %rax, 0x8(%rsp)
subq $0x4, %rax
ja 0x3e88
movq 0x8(%rsp), %rax
leaq 0x633f(%rip), %rcx      # 0xa138
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl 0x1a0(%rsp), %eax
movl %eax, 0xabf1(%rip)      # 0xea00
jmp 0x3e8a
cmpl $0x0, 0x1a8(%rsp)
je 0x3e28
movl 0x19c(%rsp), %eax
movl %eax, 0x4(%rsp)
jmp 0x3e33
movl 0x1a0(%rsp), %eax
movl %eax, 0x4(%rsp)
movl 0x4(%rsp), %eax
movl %eax, 0xabc3(%rip)      # 0xea00
jmp 0x3e8a
cmpl $0x0, 0x1a8(%rsp)
je 0x3e55
movl 0x1a0(%rsp), %eax
movl %eax, (%rsp)
jmp 0x3e5f
movl 0x19c(%rsp), %eax
movl %eax, (%rsp)
movl (%rsp), %eax
movl %eax, 0xab98(%rip)      # 0xea00
jmp 0x3e8a
movl 0x198(%rsp), %eax
movl %eax, 0xab89(%rip)      # 0xea00
jmp 0x3e8a
movl 0x194(%rsp), %eax
movl %eax, 0xab7a(%rip)      # 0xea00
jmp 0x3e8a
jmp 0x3e8a
jmp 0x3e8c
movl $0x1, 0x1b4(%rsp)
movl 0x1b4(%rsp), %eax
addq $0x1b8, %rsp            # imm = 0x1B8
retq
nopw %cs:(%rax,%rax)