// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]ramulator/src/Controller.h
// Function: ramulator::Controller<ramulator::DDR3>::tick()
void tick()
    {
        clk++;
        req_queue_length_sum += readq.size() + writeq.size() + pending.size();
        read_req_queue_length_sum += readq.size() + pending.size();
        write_req_queue_length_sum += writeq.size();

        /*** 1. Serve completed reads ***/
        if (pending.size()) {
            Request& req = pending[0];
            if (req.depart <= clk) {
                if (req.depart - req.arrive > 1) { // this request really accessed a row
                  read_latency_sum += req.depart - req.arrive;
                  channel->update_serving_requests(
                      req.addr_vec.data(), -1, clk);
                }
                req.callback(req);
                pending.pop_front();
            }
        }

        /*** 2. Refresh scheduler ***/
        refresh->tick_ref();

        /*** 3. Should we schedule writes? ***/
        if (!write_mode) {
            // yes -- write queue is almost full or read queue is empty
            if (writeq.size() > int(wr_high_watermark * writeq.max) || readq.size() == 0)
                write_mode = true;
        }
        else {
            // no -- write queue is almost empty and read queue is not empty
            if (writeq.size() < int(wr_low_watermark * writeq.max) && readq.size() != 0)
                write_mode = false;
        }

        /*** 4. Find the best command to schedule, if any ***/

        // First check the actq (which has higher priority) to see if there
        // are requests available to service in this cycle
        Queue* queue = &actq;
        typename T::Command cmd;
        auto req = scheduler->get_head(queue->q);

        bool is_valid_req = (req != queue->q.end());

        if(is_valid_req) {
            cmd = get_first_cmd(req);
            is_valid_req = is_ready(cmd, req->addr_vec);
        }

        if (!is_valid_req) {
            queue = !write_mode ? &readq : &writeq;

            if (otherq.size())
                queue = &otherq;  // "other" requests are rare, so we give them precedence over reads/writes

            req = scheduler->get_head(queue->q);

            is_valid_req = (req != queue->q.end());

            if(is_valid_req){
                cmd = get_first_cmd(req);
                is_valid_req = is_ready(cmd, req->addr_vec);
            }
        }

        if (!is_valid_req) {
            // we couldn't find a command to schedule -- let's try to be speculative
            auto cmd = T::Command::PRE;
            vector<int> victim = rowpolicy->get_victim(cmd);
            if (!victim.empty()){
                issue_cmd(cmd, victim);
            }
            return;  // nothing more to be done this cycle
        }

        if (req->is_first_command) {
            req->is_first_command = false;
            int coreid = req->coreid;
            if (req->type == Request::Type::READ || req->type == Request::Type::WRITE) {
              channel->update_serving_requests(req->addr_vec.data(), 1, clk);
            }
            int tx = (channel->spec->prefetch_size * channel->spec->channel_width / 8);
            if (req->type == Request::Type::READ) {
                if (is_row_hit(req)) {
                    ++read_row_hits[coreid];
                    ++row_hits;
                } else if (is_row_open(req)) {
                    ++read_row_conflicts[coreid];
                    ++row_conflicts;
                } else {
                    ++read_row_misses[coreid];
                    ++row_misses;
                }
              read_transaction_bytes += tx;
            } else if (req->type == Request::Type::WRITE) {
              if (is_row_hit(req)) {
                  ++write_row_hits[coreid];
                  ++row_hits;
              } else if (is_row_open(req)) {
                  ++write_row_conflicts[coreid];
                  ++row_conflicts;
              } else {
                  ++write_row_misses[coreid];
                  ++row_misses;
              }
              write_transaction_bytes += tx;
            }
        }

        // issue command on behalf of request
        issue_cmd(cmd, get_addr_vec(cmd, req));

        // check whether this is the last command (which finishes the request)
        //if (cmd != channel->spec->translate[int(req->type)]){
        if (cmd != channel->spec->translate[int(req->type)]) {
            if(channel->spec->is_opening(cmd)) {
                // promote the request that caused issuing activation to actq
                actq.q.push_back(*req);
                queue->q.erase(req);
            }

            return;
        }

        // set a future completion time for read requests
        if (req->type == Request::Type::READ) {
            req->depart = clk + channel->spec->read_latency;
            pending.push_back(*req);
        }

        if (req->type == Request::Type::WRITE) {
            channel->update_serving_requests(req->addr_vec.data(), -1, clk);
            // req->callback(*req);
        }

        // remove request from queue
        queue->q.erase(req);
    }

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rdi, %rbx
incq 0x1090(%rdi)
movl 0x10f0(%rdi), %r14d
addl 0x10d0(%rdi), %r14d
leaq 0x1140(%rdi), %r13
movq %r13, %rdi
callq 0x1eebc
addq %r14, %rax
movq %rax, %xmm0
punpckldq 0xb212f(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd 0xb2137(%rip), %xmm0    # 0xd1050
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1            # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
addsd 0x9e8(%rbx), %xmm1
movsd %xmm1, 0x9e8(%rbx)
movl 0x10d0(%rbx), %r14d
movq %r13, %rdi
callq 0x1eebc
addq %r14, %rax
movq %rax, %xmm0
punpckldq 0xb20ec(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd 0xb20f4(%rip), %xmm0    # 0xd1050
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1            # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
addsd 0xb18(%rbx), %xmm1
movsd %xmm1, 0xb18(%rbx)
movl 0x10f0(%rbx), %eax
cvtsi2sd %rax, %xmm0
addsd 0xc48(%rbx), %xmm0
movsd %xmm0, 0xc48(%rbx)
movq %r13, %rdi
callq 0x1eebc
testq %rax, %rax
je 0x1f00a
leaq 0x1150(%rbx), %rdi
xorl %esi, %esi
callq 0x1fb5c
movq %rax, %r14
movq 0x38(%rax), %rax
movq 0x1090(%rbx), %rcx
cmpq %rcx, %rax
jg 0x1f00a
subq 0x30(%r14), %rax
cmpq $0x2, %rax
jl 0x1eff3
cvtsi2sd %rax, %xmm0
addsd 0x8b8(%rbx), %xmm0
movsd %xmm0, 0x8b8(%rbx)
movq 0x1098(%rbx), %rdi
movq 0x10(%r14), %rsi
pushq $-0x1
popq %rdx
callq 0x1f3c2
movq %r14, %rdi
addq $0x40, %rdi
movq %r14, %rsi
callq 0x1f5d6
movq %r13, %rdi
callq 0x1f5ea
movq 0x10b8(%rbx), %rdi
callq 0x1f614
movl 0x10f8(%rbx), %eax
cvtsi2ss %rax, %xmm0
movl 0x10d0(%rbx), %ecx
movl 0x10f0(%rbx), %eax
cmpb $0x0, 0x1190(%rbx)
je 0x1f055
testq %rcx, %rcx
mulss 0x1198(%rbx), %xmm0
cvttss2si %xmm0, %ecx
sete %dl
cmpl %ecx, %eax
setae %al
orb %dl, %al
jne 0x1f078
xorl %eax, %eax
jmp 0x1f072
testq %rcx, %rcx
mulss 0x1194(%rbx), %xmm0
sete %cl
cvttss2si %xmm0, %edx
cmpl %edx, %eax
seta %al
orb %cl, %al
movb $0x1, %al
je 0x1f078
movb %al, 0x1190(%rbx)
leaq 0x1100(%rbx), %r14
movq 0x10a0(%rbx), %rdi
movq %r14, %rsi
callq 0x1f64a
cmpq %r14, %rax
je 0x1f0bd
movq %rax, %r15
movq %rbx, %rdi
movq %rax, %rsi
callq 0x1b470
movl %eax, %ebp
movq %r15, %rdx
addq $0x20, %rdx
movq %rbx, %rdi
movl %eax, %esi
callq 0x1bbb4
testb %al, %al
je 0x1f0bd
movq %r14, %r12
jmp 0x1f122
movzbl 0x1190(%rbx), %eax
shll $0x5, %eax
orq $0x10c0, %rax           # imm = 0x10C0
cmpl $0x0, 0x1130(%rbx)
movl $0x1120, %r12d          # imm = 0x1120
cmoveq %rax, %r12
addq %rbx, %r12
movq 0x10a0(%rbx), %rdi
movq %r12, %rsi
callq 0x1f64a
cmpq %r12, %rax
je 0x1f1c1
movq %rax, %r15
movq %rbx, %rdi
movq %rax, %rsi
callq 0x1b470
movl %eax, %ebp
movq %r15, %rdx
addq $0x20, %rdx
movq %rbx, %rdi
movl %eax, %esi
callq 0x1bbb4
testb %al, %al
je 0x1f1c1
cmpb $0x1, 0x10(%r15)
movq %r13, 0x30(%rsp)
movq %r14, 0x28(%rsp)
jne 0x1f2ae
movb $0x0, 0x10(%r15)
movl 0x38(%r15), %r14d
movl 0x3c(%r15), %ecx
cmpl $0x1, %ecx
ja 0x1f167
movq 0x1090(%rbx), %rcx
movq 0x1098(%rbx), %rdi
movq 0x20(%r15), %rsi
pushq $0x1
popq %rdx
callq 0x1f3c2
movl 0x3c(%r15), %ecx
movq 0x1098(%rbx), %rax
movq 0x390(%rax), %rdx
movl 0x2744(%rdx), %eax
imull 0x2740(%rdx), %eax
pushq $0x8
popq %rsi
cltd
idivl %esi
cmpl $0x1, %ecx
je 0x1f200
testl %ecx, %ecx
jne 0x1f2ae
movl %eax, 0x8(%rsp)
movl %r14d, 0xc(%rsp)
movq %rbx, %rdi
movq %r15, %rsi
callq 0x1ba2a
pushq $0x70
popq %r14
testb %al, %al
je 0x1f22b
movl $0x1a0, %r13d           # imm = 0x1A0
movl $0x2f8, %edi            # imm = 0x2F8
jmp 0x1f26e
movq 0x10a8(%rbx), %rsi
leaq 0x10(%rsp), %r14
pushq $0x1
popq %rdx
movq %r14, %rdi
callq 0x1f8ac
movq (%r14), %rax
cmpq 0x8(%r14), %rax
je 0x1f1f1
pushq $0x1
popq %rsi
leaq 0x10(%rsp), %rdx
movq %rbx, %rdi
callq 0x1f8ca
leaq 0x10(%rsp), %rdi
callq 0x1b7dc
jmp 0x1f35b
movl %eax, 0x8(%rsp)
movl %r14d, 0xc(%rsp)
movq %rbx, %rdi
movq %r15, %rsi
callq 0x1ba2a
movl $0x108, %r14d           # imm = 0x108
testb %al, %al
je 0x1f244
movl $0x1a0, %r13d           # imm = 0x1A0
movl $0x508, %edi            # imm = 0x508
jmp 0x1f26e
movq %rbx, %rdi
movq %r15, %rsi
callq 0x1faf4
testb %al, %al
movl $0x458, %eax            # imm = 0x458
movl $0x3a8, %edi            # imm = 0x3A8
jmp 0x1f25b
movq %rbx, %rdi
movq %r15, %rsi
callq 0x1faf4
testb %al, %al
movl $0x668, %eax            # imm = 0x668
movl $0x5b8, %edi            # imm = 0x5B8
cmovneq %rax, %rdi
movl $0x2d0, %eax            # imm = 0x2D0
movl $0x238, %r13d           # imm = 0x238
cmovneq %rax, %r13
addq %rbx, %rdi
movl 0xc(%rsp), %esi
callq 0x21130
movsd 0xb1df6(%rip), %xmm0    # 0xd1078
movsd 0x70(%rax), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 0x70(%rax)
addsd (%rbx,%r13), %xmm0
cvtsi2sdl 0x8(%rsp), %xmm1
movsd %xmm0, (%rbx,%r13)
addsd (%rbx,%r14), %xmm1
movsd %xmm1, (%rbx,%r14)
leaq 0x20(%r15), %r14
leaq 0x10(%rsp), %r13
movq %r13, %rdi
movq %r14, %rsi
callq 0x1bbca
movq %rbx, %rdi
movl %ebp, %esi
movq %r13, %rdx
callq 0x1f8ca
leaq 0x10(%r15), %r13
leaq 0x10(%rsp), %rdi
callq 0x1b7dc
movq 0x1098(%rbx), %rax
movq 0x390(%rax), %rcx
movslq 0x3c(%r15), %rax
cmpl 0x1c4(%rcx,%rax,4), %ebp
jne 0x1f33f
testl %eax, %eax
jne 0x1f31f
movslq 0x2dd8(%rcx), %rax
addq 0x1090(%rbx), %rax
movq %rax, 0x48(%r15)
movq 0x30(%rsp), %rdi
movq %r13, %rsi
callq 0x1fb32
movl 0x3c(%r15), %eax
cmpl $0x1, %eax
jne 0x1f350
movq 0x1090(%rbx), %rcx
movq 0x1098(%rbx), %rdi
movq (%r14), %rsi
pushq $-0x1
popq %rdx
callq 0x1f3c2
jmp 0x1f350
testl %ebp, %ebp
jne 0x1f35b
movq 0x28(%rsp), %rdi
movq %r13, %rsi
callq 0x1fb18
movq %r12, %rdi
movq %r15, %rsi
callq 0x1fb24
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
jmp 0x1f36c
movq %rax, %rbx
leaq 0x10(%rsp), %rdi
callq 0x1b7dc
movq %rbx, %rdi
callq 0xb4d0