// File: /workspace/github_cpp_makefile_star2_O3/j-faria[P]kima/eigen/Eigen/src/Core/util/Memory.h
// Function: Eigen::internal::queryCacheSizes_intel_codes(int&, int&, int&)
inline void queryCacheSizes_intel_codes(int& l1, int& l2, int& l3)
{
  int abcd[4];
  abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;
  l1 = l2 = l3 = 0;
  EIGEN_CPUID(abcd,0x00000002,0);
  unsigned char * bytes = reinterpret_cast<unsigned char *>(abcd)+2;
  bool check_for_p2_core2 = false;
  for(int i=0; i<14; ++i)
  {
    switch(bytes[i])
    {
      case 0x0A: l1 = 8; break;   // 0Ah   data L1 cache, 8 KB, 2 ways, 32 byte lines
      case 0x0C: l1 = 16; break;  // 0Ch   data L1 cache, 16 KB, 4 ways, 32 byte lines
      case 0x0E: l1 = 24; break;  // 0Eh   data L1 cache, 24 KB, 6 ways, 64 byte lines
      case 0x10: l1 = 16; break;  // 10h   data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
      case 0x15: l1 = 16; break;  // 15h   code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
      case 0x2C: l1 = 32; break;  // 2Ch   data L1 cache, 32 KB, 8 ways, 64 byte lines
      case 0x30: l1 = 32; break;  // 30h   code L1 cache, 32 KB, 8 ways, 64 byte lines
      case 0x60: l1 = 16; break;  // 60h   data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored
      case 0x66: l1 = 8; break;   // 66h   data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored
      case 0x67: l1 = 16; break;  // 67h   data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored
      case 0x68: l1 = 32; break;  // 68h   data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored
      case 0x1A: l2 = 96; break;   // code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64)
      case 0x22: l3 = 512; break;   // code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored
      case 0x23: l3 = 1024; break;   // code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x25: l3 = 2048; break;   // code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x29: l3 = 4096; break;   // code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x39: l2 = 128; break;   // code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored
      case 0x3A: l2 = 192; break;   // code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored
      case 0x3B: l2 = 128; break;   // code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored
      case 0x3C: l2 = 256; break;   // code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored
      case 0x3D: l2 = 384; break;   // code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored
      case 0x3E: l2 = 512; break;   // code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored
      case 0x40: l2 = 0; break;   // no integrated L2 cache (P6 core) or L3 cache (P4 core)
      case 0x41: l2 = 128; break;   // code and data L2 cache, 128 KB, 4 ways, 32 byte lines
      case 0x42: l2 = 256; break;   // code and data L2 cache, 256 KB, 4 ways, 32 byte lines
      case 0x43: l2 = 512; break;   // code and data L2 cache, 512 KB, 4 ways, 32 byte lines
      case 0x44: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 4 ways, 32 byte lines
      case 0x45: l2 = 2048; break;   // code and data L2 cache, 2048 KB, 4 ways, 32 byte lines
      case 0x46: l3 = 4096; break;   // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines
      case 0x47: l3 = 8192; break;   // code and data L3 cache, 8192 KB, 8 ways, 64 byte lines
      case 0x48: l2 = 3072; break;   // code and data L2 cache, 3072 KB, 12 ways, 64 byte lines
      case 0x49: if(l2!=0) l3 = 4096; else {check_for_p2_core2=true; l3 = l2 = 4096;} break;// code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or L2 for core2
      case 0x4A: l3 = 6144; break;   // code and data L3 cache, 6144 KB, 12 ways, 64 byte lines
      case 0x4B: l3 = 8192; break;   // code and data L3 cache, 8192 KB, 16 ways, 64 byte lines
      case 0x4C: l3 = 12288; break;   // code and data L3 cache, 12288 KB, 12 ways, 64 byte lines
      case 0x4D: l3 = 16384; break;   // code and data L3 cache, 16384 KB, 16 ways, 64 byte lines
      case 0x4E: l2 = 6144; break;   // code and data L2 cache, 6144 KB, 24 ways, 64 byte lines
      case 0x78: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 4 ways, 64 byte lines
      case 0x79: l2 = 128; break;   // code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x7A: l2 = 256; break;   // code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x7B: l2 = 512; break;   // code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x7C: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored
      case 0x7D: l2 = 2048; break;   // code and data L2 cache, 2048 KB, 8 ways, 64 byte lines
      case 0x7E: l2 = 256; break;   // code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64)
      case 0x7F: l2 = 512; break;   // code and data L2 cache, 512 KB, 2 ways, 64 byte lines
      case 0x80: l2 = 512; break;   // code and data L2 cache, 512 KB, 8 ways, 64 byte lines
      case 0x81: l2 = 128; break;   // code and data L2 cache, 128 KB, 8 ways, 32 byte lines
      case 0x82: l2 = 256; break;   // code and data L2 cache, 256 KB, 8 ways, 32 byte lines
      case 0x83: l2 = 512; break;   // code and data L2 cache, 512 KB, 8 ways, 32 byte lines
      case 0x84: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 8 ways, 32 byte lines
      case 0x85: l2 = 2048; break;   // code and data L2 cache, 2048 KB, 8 ways, 32 byte lines
      case 0x86: l2 = 512; break;   // code and data L2 cache, 512 KB, 4 ways, 64 byte lines
      case 0x87: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines
      case 0x88: l3 = 2048; break;   // code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64)
      case 0x89: l3 = 4096; break;   // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64)
      case 0x8A: l3 = 8192; break;   // code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64)
      case 0x8D: l3 = 3072; break;   // code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64)

      default: break;
    }
  }
  if(check_for_p2_core2 && l2 == l3)
    l3 = 0;
  l1 *= 1024;
  l2 *= 1024;
  l3 *= 1024;
}

// Assembly:
movq %rdx, %r8
xorl %r9d, %r9d
movl %r9d, (%rdx)
movl %r9d, (%rsi)
movl %r9d, (%rdi)
movl $0x2, %eax
xorl %ecx, %ecx
xchgq %rbx, %r10
cpuid
xchgq %rbx, %r10
movl %eax, -0x18(%rsp)
movl %r10d, -0x14(%rsp)
movl %ecx, -0x10(%rsp)
movl %edx, -0xc(%rsp)
leaq 0x21e52(%rip), %rax     # 0x3d7e0
xorl %ecx, %ecx
addq $-0xe, %r9
movzbl -0x8(%rsp,%r9), %edx
addl $-0xa, %edx
cmpl $0x83, %edx
ja 0x1ba99
movslq (%rax,%rdx,4), %rdx
addq %rax, %rdx
jmpq *%rdx
movl $0x200, (%rsi)          # imm = 0x200
jmp 0x1ba99
movl $0x400, (%rsi)          # imm = 0x400
jmp 0x1ba99
movl $0x100, (%rsi)          # imm = 0x100
jmp 0x1ba99
movl $0x80, (%rsi)
jmp 0x1ba99
movl $0x10, (%rdi)
jmp 0x1ba99
movl $0x20, (%rdi)
jmp 0x1ba99
movl $0x2000, (%r8)          # imm = 0x2000
jmp 0x1ba99
movl $0x800, (%rsi)          # imm = 0x800
jmp 0x1ba99
movl $0x800, (%r8)           # imm = 0x800
jmp 0x1ba99
movl $0x8, (%rdi)
jmp 0x1ba99
movl $0xc00, (%rsi)          # imm = 0xC00
jmp 0x1ba99
movl $0xc00, (%r8)           # imm = 0xC00
jmp 0x1ba99
movl $0x3000, (%r8)          # imm = 0x3000
jmp 0x1ba99
movl $0x0, (%rsi)
jmp 0x1ba99
movl $0x400, (%r8)           # imm = 0x400
jmp 0x1ba99
movl $0xc0, (%rsi)
jmp 0x1ba99
movl $0x18, (%rdi)
jmp 0x1ba99
movl $0x180, (%rsi)          # imm = 0x180
jmp 0x1ba99
movl $0x200, (%r8)           # imm = 0x200
jmp 0x1ba99
movl $0x4000, (%r8)          # imm = 0x4000
jmp 0x1ba99
movl $0x60, (%rsi)
jmp 0x1ba99
movl $0x1800, (%rsi)         # imm = 0x1800
jmp 0x1ba99
movl $0x1800, (%r8)          # imm = 0x1800
jmp 0x1ba99
cmpl $0x0, (%rsi)
je 0x1baa4
movl $0x1000, (%r8)          # imm = 0x1000
incq %r9
jne 0x1b994
jmp 0x1bac3
movl $0x1000, %ecx           # imm = 0x1000
movl %ecx, (%rsi)
movl %ecx, (%r8)
leaq 0xf(%r9), %rdx
movb $0x1, %cl
cmpq $-0x1, %r9
movq %rdx, %r9
jne 0x1b990
jmp 0x1bac8
testb $0x1, %cl
je 0x1bad6
movl (%rsi), %eax
cmpl (%r8), %eax
jne 0x1bad6
movl $0x0, (%r8)
shll $0xa, (%rdi)
shll $0xa, (%rsi)
shll $0xa, (%r8)
retq
nop