// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/ooo_cpu.cc
// Function: O3_CPU::add_load_queue(unsigned int, unsigned int)
void O3_CPU::add_load_queue(uint32_t rob_index, uint32_t data_index)
{
    // search for an empty slot 
    uint32_t lq_index = LQ.SIZE;
    for (uint32_t i=0; i<LQ.SIZE; i++) {
        if (LQ.entry[i].virtual_address == 0) {
            lq_index = i;
            break;
        }
    }

    // sanity check
    if (lq_index == LQ.SIZE) {
        cerr << "instr_id: " << ROB.entry[rob_index].instr_id << " no empty slot in the load queue!!!" << endl;
        assert(0);
    }

    // add it to the load queue
    ROB.entry[rob_index].lq_index[data_index] = lq_index;
    LQ.entry[lq_index].instr_id = ROB.entry[rob_index].instr_id;
    LQ.entry[lq_index].virtual_address = ROB.entry[rob_index].source_memory[data_index];
    LQ.entry[lq_index].ip = ROB.entry[rob_index].ip;
    LQ.entry[lq_index].data_index = data_index;
    LQ.entry[lq_index].rob_index = rob_index;
    LQ.entry[lq_index].asid[0] = ROB.entry[rob_index].asid[0];
    LQ.entry[lq_index].asid[1] = ROB.entry[rob_index].asid[1];
    LQ.entry[lq_index].event_cycle = current_core_cycle[cpu] + SCHEDULING_LATENCY;
    LQ.occupancy++;

    // check RAW dependency
    int prior = rob_index - 1;
    if (prior < 0)
        prior = ROB.SIZE - 1;

    if (rob_index != ROB.head) {
        if ((int)ROB.head <= prior) {
            for (int i=prior; i>=(int)ROB.head; i--) {
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
        }
        else {
            for (int i=prior; i>=0; i--) {
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
            for (int i=ROB.SIZE-1; i>=(int)ROB.head; i--) { 
                if (LQ.entry[lq_index].producer_id != UINT64_MAX)
                    break;

                    mem_RAW_dependency(i, rob_index, data_index, lq_index);
            }
        }
    }

    // check
    // 1) if store-to-load forwarding is possible
    // 2) if there is WAR that are not correctly executed
    uint32_t forwarding_index = SQ.SIZE;
    for (uint32_t i=0; i<SQ.SIZE; i++) {

        // skip empty slot
        if (SQ.entry[i].virtual_address == 0)
            continue;

        // forwarding should be done by the SQ entry that holds the same producer_id from RAW dependency check
        if (SQ.entry[i].virtual_address == LQ.entry[lq_index].virtual_address) { // store-to-load forwarding check

            // forwarding store is in the SQ
            if ((rob_index != ROB.head) && (LQ.entry[lq_index].producer_id == SQ.entry[i].instr_id)) { // RAW
                forwarding_index = i;
                break; // should be break
            }

            if ((LQ.entry[lq_index].producer_id == UINT64_MAX) && (LQ.entry[lq_index].instr_id <= SQ.entry[i].instr_id)) { // WAR 
                // a load is about to be added in the load queue and we found a store that is 
                // "logically later in the program order but already executed" => this is not correctly executed WAR
                // due to out-of-order execution, this case is possible, for example
                // 1) application is load intensive and load queue is full
                // 2) we have loads that can't be added in the load queue
                // 3) subsequent stores logically behind in the program order are added in the store queue first

                // thanks to the store buffer, data is not written back to the memory system until retirement
                // also due to in-order retirement, this "already executed store" cannot be retired until we finish the prior load instruction 
                // if we detect WAR when a load is added in the load queue, just let the load instruction to access the memory system
                // no need to mark any dependency because this is actually WAR not RAW

                // do not forward data from the store queue since this is WAR
                // just read correct data from data cache

                LQ.entry[lq_index].physical_address = 0;
                LQ.entry[lq_index].translated = 0;
                LQ.entry[lq_index].fetched = 0;
                
                DP(if(warmup_complete[cpu]) {
                cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " reset fetched: " << +LQ.entry[lq_index].fetched;
                cout << " to obey WAR store instr_id: " << SQ.entry[i].instr_id << " cycle: " << current_core_cycle[cpu] << endl; });
            }
        }
    }

    if (forwarding_index != SQ.SIZE) { // we have a store-to-load forwarding

        if ((SQ.entry[forwarding_index].fetched == COMPLETED) && (SQ.entry[forwarding_index].event_cycle <= current_core_cycle[cpu])) {
            LQ.entry[lq_index].physical_address = (SQ.entry[forwarding_index].physical_address & ~(uint64_t) ((1 << LOG2_BLOCK_SIZE) - 1)) | (LQ.entry[lq_index].virtual_address & ((1 << LOG2_BLOCK_SIZE) - 1));
            LQ.entry[lq_index].translated = COMPLETED;
            LQ.entry[lq_index].fetched = COMPLETED;

            uint32_t fwr_rob_index = LQ.entry[lq_index].rob_index;
            ROB.entry[fwr_rob_index].num_mem_ops--;
            ROB.entry[fwr_rob_index].event_cycle = current_core_cycle[cpu];
            if (ROB.entry[fwr_rob_index].num_mem_ops < 0) {
                cerr << "instr_id: " << ROB.entry[fwr_rob_index].instr_id << endl;
                assert(0);
            }
            if (ROB.entry[fwr_rob_index].num_mem_ops == 0)
                inflight_mem_executions++;

            DP(if(warmup_complete[cpu]) {
            cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << hex;
            cout << " full_addr: " << LQ.entry[lq_index].physical_address << dec << " is forwarded by store instr_id: ";
            cout << SQ.entry[forwarding_index].instr_id << " remain_num_ops: " << ROB.entry[fwr_rob_index].num_mem_ops << " cycle: " << current_core_cycle[cpu] << endl; });

            release_load_queue(lq_index);
        }
        else
            ; // store is not executed yet, forwarding will be handled by execute_store()
    }

    // succesfully added to the load queue
    ROB.entry[rob_index].source_added[data_index] = 1;

    if (LQ.entry[lq_index].virtual_address && (LQ.entry[lq_index].producer_id == UINT64_MAX)) { // not released and no forwarding
        RTL0[RTL0_tail] = lq_index;
        RTL0_tail++;
        if (RTL0_tail == LQ_SIZE)
            RTL0_tail = 0;

        DP (if (warmup_complete[cpu]) {
        cout << "[RTL0] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " rob_index: " << LQ.entry[lq_index].rob_index << " is added to RTL0";
        cout << " head: " << RTL0_head << " tail: " << RTL0_tail << endl; }); 
    }

    DP(if(warmup_complete[cpu]) {
    cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id;
    cout << " is added in the LQ address: " << hex << LQ.entry[lq_index].virtual_address << dec << " translated: " << +LQ.entry[lq_index].translated;
    cout << " fetched: " << +LQ.entry[lq_index].fetched << " index: " << lq_index << " occupancy: " << LQ.occupancy << " cycle: " << current_core_cycle[cpu] << endl; });
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
movl 0x9e0(%rdi), %ecx
movq 0x9f0(%rdi), %rax
imulq $0x140, %rcx, %rcx      # imm = 0x140
xorl %r14d, %r14d
xorl %r13d, %r13d
movl %r15d, %r12d
cmpq %r13, %rcx
je 0xb9a7
cmpq $0x0, 0x10(%rax,%r13)
je 0xb6dc
addq $0x140, %r13            # imm = 0x140
incl %r14d
jmp 0xb6bc
movq 0x9b8(%rbx), %rcx
movl %ebp, %edi
imulq $0x758, %r12, %r8       # imm = 0x758
leaq (%rcx,%r8), %rdx
movl %r14d, 0x728(%rdx,%rdi,4)
movq (%rcx,%r8), %rsi
movq %rsi, (%rax,%r13)
movq %rdi, 0x10(%rsp)
movq 0x5c8(%rdx,%rdi,8), %rdx
movq %rdx, 0x10(%rax,%r13)
movq 0x8(%rcx,%r8), %rdx
movq %rdx, 0x20(%rax,%r13)
movl %ebp, 0x34(%rax,%r13)
movl %r15d, 0x30(%rax,%r13)
movb 0x5b(%rcx,%r8), %cl
movb %cl, 0x3e(%rax,%r13)
movq 0x9b8(%rbx), %rax
movq 0x9f0(%rbx), %rcx
movq %r8, 0x8(%rsp)
movb 0x5c(%rax,%r8), %al
movb %al, 0x3f(%rcx,%r13)
movl (%rbx), %eax
leaq 0x7175a(%rip), %rdx     # 0x7ceb0
movl 0x71764(%rip), %ecx     # 0x7cec0
addq (%rdx,%rax,8), %rcx
movq 0x9f0(%rbx), %rax
movq %rcx, 0x28(%rax,%r13)
incl 0x9e4(%rbx)
movl 0x958(%rbx), %ecx
movl %r15d, %eax
cmpl %r15d, %ecx
jne 0xb7f1
movl 0xa18(%rbx), %edx
movq 0xa28(%rbx), %rcx
movq 0x9f0(%rbx), %rsi
imulq $0x140, %rdx, %rdi      # imm = 0x140
xorl %edx, %edx
cmpq %rdx, %rdi
je 0xb947
movq 0x10(%rcx,%rdx), %r8
testq %r8, %r8
je 0xb7e8
cmpq 0x10(%rsi,%r13), %r8
jne 0xb7e8
movq 0x8(%rsi,%r13), %r8
cmpl %r15d, %eax
je 0xb7cb
cmpq (%rcx,%rdx), %r8
je 0xb8b3
cmpq $-0x1, %r8
jne 0xb7e8
movq (%rsi,%r13), %r8
cmpq (%rcx,%rdx), %r8
ja 0xb7e8
andq $0x0, 0x18(%rsi,%r13)
andw $0x0, 0x3c(%rsi,%r13)
addq $0x140, %rdx            # imm = 0x140
jmp 0xb79d
leal -0x1(%r15), %eax
movl 0x950(%rbx), %r12d
decl %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
cmpl %r12d, %ecx
jle 0xb836
testl %r12d, %r12d
js 0xb872
movq 0x9f0(%rbx), %rax
cmpq $-0x1, 0x8(%rax,%r13)
jne 0xb872
movq %rbx, %rdi
movl %r12d, %esi
movl %r15d, %edx
movl %ebp, %ecx
movl %r14d, %r8d
callq 0xbbac
decl %r12d
jmp 0xb80a
movl %ecx, %eax
cmpl %eax, %r12d
jl 0xb780
movq 0x9f0(%rbx), %rcx
cmpq $-0x1, 0x8(%rcx,%r13)
jne 0xb780
movq %rbx, %rdi
movl %r12d, %esi
movl %r15d, %edx
movl %ebp, %ecx
movl %r14d, %r8d
callq 0xbbac
decl %r12d
movl 0x958(%rbx), %eax
jmp 0xb838
movl 0x950(%rbx), %r12d
decl %r12d
movl 0x958(%rbx), %eax
cmpl %eax, %r12d
jl 0xb780
movq 0x9f0(%rbx), %rcx
cmpq $-0x1, 0x8(%rcx,%r13)
jne 0xb780
movq %rbx, %rdi
movl %r12d, %esi
movl %r15d, %edx
movl %ebp, %ecx
movl %r14d, %r8d
callq 0xbbac
jmp 0xb879
cmpb $0x2, 0x3d(%rcx,%rdx)
jne 0xb947
movq 0x28(%rcx,%rdx), %rsi
movl (%rbx), %eax
leaq 0x715e4(%rip), %rdi     # 0x7ceb0
cmpq (%rdi,%rax,8), %rsi
ja 0xb947
movq 0x18(%rcx,%rdx), %rcx
andq $-0x40, %rcx
movq 0x9f0(%rbx), %rdx
movq 0x10(%rdx,%r13), %rsi
andl $0x3f, %esi
orq %rcx, %rsi
movq %rsi, 0x18(%rdx,%r13)
movw $0x202, 0x3c(%rdx,%r13) # imm = 0x202
movl 0x30(%rdx,%r13), %ecx
movq 0x9b8(%rbx), %rdx
imulq $0x758, %rcx, %r15      # imm = 0x758
movl 0x70(%rdx,%r15), %esi
leal -0x1(%rsi), %ecx
movl %ecx, 0x70(%rdx,%r15)
leaq 0x7158f(%rip), %rdi     # 0x7ceb0
movq (%rdi,%rax,8), %rax
movq %rax, 0x40(%rdx,%r15)
testl %esi, %esi
jle 0xba0a
testl %ecx, %ecx
jne 0xb93c
incl 0x924(%rbx)
movq %rbx, %rdi
movl %r14d, %esi
callq 0xbc36
movq 0x8(%rsp), %rcx
addq 0x9b8(%rbx), %rcx
movq 0x10(%rsp), %rax
movb $0x1, 0x4e(%rax,%rcx)
movq 0x9f0(%rbx), %rax
cmpq $0x0, 0x10(%rax,%r13)
je 0xb998
cmpq $-0x1, 0x8(%rax,%r13)
jne 0xb998
movl 0x3374(%rbx), %eax
movl %r14d, 0x3250(%rbx,%rax,4)
movl 0x3374(%rbx), %eax
incl %eax
xorl %ecx, %ecx
cmpl $0x48, %eax
cmovnel %eax, %ecx
movl %ecx, 0x3374(%rbx)
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0xa642(%rip), %rdi      # 0x15ff0
leaq 0x54a4(%rip), %rsi      # 0x10e59
callq 0x2230
movq 0x9b8(%rbx), %rcx
imulq $0x758, %r12, %rdx      # imm = 0x758
movq (%rcx,%rdx), %rsi
movq %rax, %rdi
callq 0x2080
leaq 0x537f(%rip), %rsi      # 0x10d5a
movq %rax, %rdi
callq 0x2230
movq %rax, %rdi
callq 0x2110
leaq 0x4675(%rip), %rdi      # 0x10067
leaq 0x51f5(%rip), %rsi      # 0x10bee
leaq 0x537e(%rip), %rcx      # 0x10d7e
movl $0x369, %edx            # imm = 0x369
callq 0x2160
movq 0xa5df(%rip), %rdi      # 0x15ff0
leaq 0x5441(%rip), %rsi      # 0x10e59
callq 0x2230
movq 0x9b8(%rbx), %rcx
movq (%rcx,%r15), %rsi
movq %rax, %rdi
callq 0x2080
movq %rax, %rdi
callq 0x2110
leaq 0x4628(%rip), %rdi      # 0x10067
leaq 0x51a8(%rip), %rsi      # 0x10bee
leaq 0x5331(%rip), %rcx      # 0x10d7e
movl $0x3d0, %edx            # imm = 0x3D0
callq 0x2160
nop