// File: /workspace/github_c_makefile_star2_O2/Ihsoh[P]ilang/compiler/assembler/ins_enc.c
// Function: ins_enc_xchg_rAX_XXX
void ins_enc_xchg_rAX_XXX(
	Instruction *ins,
	InstructionEncoderData *data
) {
	_CHECK_PARAMS(2);

	ParserASTNode *ins_node = data->ins_node;

	ParserASTNode *target = data->ins_node->childs[0];

	ParserASTNode *source = data->ins_node->childs[1];

	ins_check_operand_type(data->ctx, ins, target, source, NULL);

	EncoderInstruction enc_ins;

	ins_init(data->ctx, ins, ins_node, &enc_ins);

	InsRegister *ins_reg_target = ASM_REG_AST_NODE_GET_REG(target);
	InsRegister *ins_reg_source = ASM_REG_AST_NODE_GET_REG(source);
	InsRegister *ins_reg_another = NULL;
	if (ins_reg_target->index == INS_REGISTER_INDEX_AX) {
		ins_reg_another = ins_reg_source;
	} else {
		ins_reg_another = ins_reg_target;
	}

	int arch = ASM_PARSER_CONTEXT_DATA_GET_ARCH(data->ctx);

	switch (arch) {
		case ASM_ARCH_BIT16: {
			if (!(ins_reg_another->arch & ASM_ARCH_BIT16)) {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 16-bit mode."
				);
			}

			if (ins_reg_another->type == INS_REGISTER_GENERAL_2BYTE) {

			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_4BYTE) {
				enc_ins.legacy_prefix.operand_size_override = true;
			} else {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 16-bit mode."
				);
			}
			break;
		}
		case ASM_ARCH_BIT32: {
			if (!(ins_reg_another->arch & ASM_ARCH_BIT32)) {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 32-bit mode."
				);
			}

			if (ins_reg_another->type == INS_REGISTER_GENERAL_2BYTE) {
				enc_ins.legacy_prefix.operand_size_override = true;
			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_4BYTE) {

			} else {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 32-bit mode."
				);
			}
			break;
		}
		case ASM_ARCH_BIT64: {
			if (!(ins_reg_another->arch & ASM_ARCH_BIT64)) {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 64-bit mode."
				);
			}

			if (ins_reg_another->index & 0x08) {
				enc_ins.rex_prefix_used = true;
				enc_ins.rex_prefix.r = true;
			}

			if (ins_reg_another->type == INS_REGISTER_GENERAL_2BYTE) {
				enc_ins.legacy_prefix.operand_size_override = true;
			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_4BYTE) {

			} else if (ins_reg_another->type == INS_REGISTER_GENERAL_8BYTE) {
				
			} else {
				data->ctx->syntax_error_node_msg(
					data->ctx,
					ins_node,
					"instruction not supported in 64-bit mode."
				);
			}
			break;
		}
		default: {
			assert(0);
			break;
		}
	}

	_output(data, &enc_ins);
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
testq %rdi, %rdi
je 0x18618
movq %rsi, %rbx
testq %rsi, %rsi
je 0x18621
movq (%rbx), %r14
testq %r14, %r14
je 0x1862a
cmpl $0x2, 0x44(%r14)
jne 0x18633
movq %rdi, %r15
movq 0x48(%r14), %rax
movq (%rax), %r13
movq 0x8(%rax), %r12
movq 0x8(%rbx), %rdi
movq %r15, %rsi
movq %r13, %rdx
movq %r12, %rcx
xorl %r8d, %r8d
callq 0x15ae1
movq 0x8(%rbx), %rdi
leaq -0x88(%rbp), %rcx
movq %r15, %rsi
movq %r14, %rdx
callq 0x1470f
movq 0x60(%r13), %r15
cmpl $0x0, 0x10(%r15)
jne 0x18530
movq 0x60(%r12), %r15
movq 0x8(%rbx), %rdi
movl 0xb0(%rdi), %eax
cmpl $0x4, %eax
je 0x185af
cmpl $0x2, %eax
je 0x18580
cmpl $0x1, %eax
jne 0x18652
testb $0x1, 0x14(%r15)
jne 0x18561
leaq 0x18905(%rip), %rdx     # 0x30e60
movq %r14, %rsi
callq *0x58(%rdi)
movl 0xc(%r15), %eax
cmpl $0x3, %eax
je 0x185fa
cmpl $0x4, %eax
je 0x185e3
movq 0x8(%rbx), %rdi
leaq 0x188e2(%rip), %rdx     # 0x30e60
jmp 0x185f4
testb $0x2, 0x14(%r15)
jne 0x18594
leaq 0x188fc(%rip), %rdx     # 0x30e8a
movq %r14, %rsi
callq *0x58(%rdi)
movl 0xc(%r15), %eax
cmpl $0x4, %eax
je 0x185fa
cmpl $0x3, %eax
je 0x185e3
movq 0x8(%rbx), %rdi
leaq 0x188dd(%rip), %rdx     # 0x30e8a
jmp 0x185f4
testb $0x4, 0x14(%r15)
jne 0x185c3
leaq 0x189d5(%rip), %rdx     # 0x30f92
movq %r14, %rsi
callq *0x58(%rdi)
testb $0x8, 0x10(%r15)
je 0x185d2
movb $0x1, %al
movb %al, -0x7b(%rbp)
movb %al, -0x79(%rbp)
movl 0xc(%r15), %eax
leal -0x4(%rax), %ecx
cmpl $0x2, %ecx
jb 0x185fa
cmpl $0x3, %eax
jne 0x185e9
movb $0x1, -0x7d(%rbp)
jmp 0x185fa
movq 0x8(%rbx), %rdi
leaq 0x1899e(%rip), %rdx     # 0x30f92
movq %r14, %rsi
callq *0x58(%rdi)
leaq -0x88(%rbp), %rsi
movq %rbx, %rdi
callq 0x17180
addq $0x68, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x1711b(%rip), %rdi     # 0x2f73a
jmp 0x1863a
leaq 0x1cfc3(%rip), %rdi     # 0x355eb
jmp 0x1863a
leaq 0x18680(%rip), %rdi     # 0x30cb1
jmp 0x1863a
leaq 0x18686(%rip), %rdi     # 0x30cc0
leaq 0x18613(%rip), %rsi     # 0x30c54
leaq 0x18be0(%rip), %rcx     # 0x31228
movl $0x2ec, %edx            # imm = 0x2EC
callq 0xa0b0
leaq 0x14d17(%rip), %rdi     # 0x2d370
leaq 0x185f4(%rip), %rsi     # 0x30c54
leaq 0x18bc1(%rip), %rcx     # 0x31228
movl $0x350, %edx            # imm = 0x350
callq 0xa0b0