// File: /workspace/github_cpp_makefile_star2_O2/CMU-SAFARI[P]MQSim/src/ssd/Data_Cache_Manager_Flash_Advanced.cpp
// Function: SSD_Components::Data_Cache_Manager_Flash_Advanced::write_to_destage_buffer(SSD_Components::User_Request*)
void Data_Cache_Manager_Flash_Advanced::write_to_destage_buffer(User_Request* user_request)
	{
		//To eliminate race condition, MQSim assumes the management information and user data are stored in separate DRAM modules
		unsigned int cache_eviction_read_size_in_sectors = 0;//The size of data evicted from cache
		unsigned int flash_written_back_write_size_in_sectors = 0;//The size of data that is both written back to flash and written to DRAM
		unsigned int dram_write_size_in_sectors = 0;//The size of data written to DRAM (must be >= flash_written_back_write_size_in_sectors)
		std::list<NVM_Transaction*>* evicted_cache_slots = new std::list<NVM_Transaction*>;
		std::list<NVM_Transaction*> writeback_transactions;
		auto it = user_request->Transaction_list.begin();

		int queue_id = user_request->Stream_id;
		if (shared_dram_request_queue) {
			queue_id = 0;
		}

		while (it != user_request->Transaction_list.end() 
			&& (back_pressure_buffer_depth[queue_id] + cache_eviction_read_size_in_sectors + flash_written_back_write_size_in_sectors) < back_pressure_buffer_max_depth) {
			NVM_Transaction_Flash_WR* tr = (NVM_Transaction_Flash_WR*)(*it);
			//If the logical address already exists in the cache
			if (per_stream_cache[tr->Stream_id]->Exists(tr->Stream_id, tr->LPA)) {
				/*MQSim should get rid of writting stale data to the cache.
				* This situation may result from out-of-order transaction execution*/
				Data_Cache_Slot_Type slot = per_stream_cache[tr->Stream_id]->Get_slot(tr->Stream_id, tr->LPA);
				sim_time_type timestamp = slot.Timestamp;
				NVM::memory_content_type content = slot.Content;
				if (tr->DataTimeStamp > timestamp) {
					timestamp = tr->DataTimeStamp;
					content = tr->Content;
				}
				per_stream_cache[tr->Stream_id]->Update_data(tr->Stream_id, tr->LPA, content, timestamp, tr->write_sectors_bitmap | slot.State_bitmap_of_existing_sectors);
			} else {//the logical address is not in the cache
				if (!per_stream_cache[tr->Stream_id]->Check_free_slot_availability()) {
					Data_Cache_Slot_Type evicted_slot = per_stream_cache[tr->Stream_id]->Evict_one_slot_lru();
					if (evicted_slot.Status == Cache_Slot_Status::DIRTY_NO_FLASH_WRITEBACK) {
						evicted_cache_slots->push_back(new NVM_Transaction_Flash_WR(Transaction_Source_Type::CACHE,
							tr->Stream_id, count_sector_no_from_status_bitmap(evicted_slot.State_bitmap_of_existing_sectors) * SECTOR_SIZE_IN_BYTE,
							evicted_slot.LPA, NULL, IO_Flow_Priority_Class::URGENT, evicted_slot.Content, evicted_slot.State_bitmap_of_existing_sectors, evicted_slot.Timestamp));
						cache_eviction_read_size_in_sectors += count_sector_no_from_status_bitmap(evicted_slot.State_bitmap_of_existing_sectors);
						//DEBUG2("Evicting page" << evicted_slot.LPA << " from write buffer ")
					}
				}
				per_stream_cache[tr->Stream_id]->Insert_write_data(tr->Stream_id, tr->LPA, tr->Content, tr->DataTimeStamp, tr->write_sectors_bitmap);
			}
			dram_write_size_in_sectors += count_sector_no_from_status_bitmap(tr->write_sectors_bitmap);
			//hot/cold data separation
			if (bloom_filter[tr->Stream_id].find(tr->LPA) == bloom_filter[tr->Stream_id].end()) {
				per_stream_cache[tr->Stream_id]->Change_slot_status_to_writeback(tr->Stream_id, tr->LPA); //Eagerly write back cold data
				flash_written_back_write_size_in_sectors += count_sector_no_from_status_bitmap(tr->write_sectors_bitmap);
				bloom_filter[user_request->Stream_id].insert(tr->LPA);
				writeback_transactions.push_back(tr);
			}
			user_request->Transaction_list.erase(it++);
		}
		
		user_request->Sectors_serviced_from_cache += dram_write_size_in_sectors;//This is very important update. It is used to decide when all data sectors of a user request are serviced
		back_pressure_buffer_depth[queue_id] += cache_eviction_read_size_in_sectors + flash_written_back_write_size_in_sectors;

		//Issue memory read for cache evictions
		if (evicted_cache_slots->size() > 0) {
			Memory_Transfer_Info* read_transfer_info = new Memory_Transfer_Info;
			read_transfer_info->Size_in_bytes = cache_eviction_read_size_in_sectors * SECTOR_SIZE_IN_BYTE;
			read_transfer_info->Related_request = evicted_cache_slots;
			read_transfer_info->next_event_type = Data_Cache_Simulation_Event_Type::MEMORY_READ_FOR_CACHE_EVICTION_FINISHED;
			read_transfer_info->Stream_id = user_request->Stream_id;
			service_dram_access_request(read_transfer_info);
		}

		//Issue memory write to write data to DRAM
		if (dram_write_size_in_sectors) {
			Memory_Transfer_Info* write_transfer_info = new Memory_Transfer_Info;
			write_transfer_info->Size_in_bytes = dram_write_size_in_sectors * SECTOR_SIZE_IN_BYTE;
			write_transfer_info->Related_request = user_request;
			write_transfer_info->next_event_type = Data_Cache_Simulation_Event_Type::MEMORY_WRITE_FOR_USERIO_FINISHED;
			write_transfer_info->Stream_id = user_request->Stream_id;
			service_dram_access_request(write_transfer_info);
		}

		//If any writeback should be performed, then issue flash write transactions
		if (writeback_transactions.size() > 0) {
					static_cast<FTL*>(nvm_firmware)->Address_Mapping_Unit->Translate_lpa_to_ppa_and_dispatch(writeback_transactions);
		}
		
		//Reset control data structures used for hot/cold separation 
		if (Simulator->Time() > next_bloom_filter_reset_milestone) {
			bloom_filter[user_request->Stream_id].clear();
			next_bloom_filter_reset_milestone = Simulator->Time() + bloom_filter_reset_step;
		}
	}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rsi, %r14
movq %rdi, %rbx
pushq $0x18
popq %rdi
callq 0x7370
movq %rax, 0x8(%rax)
movq %rax, (%rax)
movq %rax, 0x18(%rsp)
andq $0x0, 0x10(%rax)
leaq 0x70(%rsp), %rax
movq %rax, 0x8(%rax)
movq %rax, (%rax)
andq $0x0, 0x10(%rax)
leaq 0x40(%r14), %r12
movq 0x40(%r14), %rbp
movq %r14, (%rsp)
movzwl 0x68(%r14), %eax
xorl %r15d, %r15d
cmpb $0x0, 0xe0(%rbx)
movl $0x0, %ecx
cmoveq %rax, %rcx
movq %rcx, 0x28(%rsp)
movq $0x0, 0x10(%rsp)
movq $0x0, 0x8(%rsp)
movq %r12, 0x20(%rsp)
movq 0xf0(%rbx), %rax
cmpq %r12, %rbp
je 0x2a844
movq 0x8(%rsp), %rcx
movq 0x10(%rsp), %rdx
addl %edx, %ecx
movq 0x28(%rsp), %rdx
movl (%rax,%rdx,4), %edx
addl %ecx, %edx
cmpl 0xe8(%rbx), %edx
jae 0x2a84d
movq %r15, 0x60(%rsp)
movq 0x10(%rbp), %r13
movq 0xc0(%rbx), %rax
movzwl (%r13), %esi
movq (%rax,%rsi,8), %rdi
movq 0x58(%r13), %rdx
callq 0x287ce
testb %al, %al
je 0x2a66f
movq 0xc0(%rbx), %rax
movzwl (%r13), %edx
movq (%rax,%rdx,8), %rsi
movq 0x58(%r13), %rcx
leaq 0x30(%rsp), %rdi
callq 0x28822
movq 0x48(%rsp), %r8
movq 0xa0(%r13), %rax
cmpq %r8, %rax
jbe 0x2a74d
movq 0x80(%r13), %rcx
movq %rax, %r8
jmp 0x2a752
movq 0xc0(%rbx), %rax
movzwl (%r13), %ecx
movq (%rax,%rcx,8), %rdi
callq 0x288ba
testb %al, %al
jne 0x2a71d
movq 0xc0(%rbx), %rax
movzwl (%r13), %ecx
movq (%rax,%rcx,8), %rsi
leaq 0x30(%rsp), %rdi
callq 0x28994
cmpl $0x2, 0x50(%rsp)
jne 0x2a71d
movl $0xb0, %edi
callq 0x7370
movq %rax, %r15
movzwl (%r13), %r14d
movq 0x30(%rsp), %rdi
callq 0x2661d
shll $0x9, %eax
movq 0x38(%rsp), %r8
movq %r15, %rdi
pushq $0x1
popq %rsi
movl %r14d, %edx
movl %eax, %ecx
xorl %r9d, %r9d
pushq 0x48(%rsp)
pushq 0x38(%rsp)
pushq 0x50(%rsp)
pushq $0x0
callq 0x3a310
addq $0x20, %rsp
movq %r15, 0x68(%rsp)
movq 0x18(%rsp), %rdi
leaq 0x68(%rsp), %rsi
callq 0x2ab40
movq 0x30(%rsp), %rdi
callq 0x2661d
addl 0x8(%rsp), %eax
movq %rax, 0x8(%rsp)
movq 0xc0(%rbx), %rax
movzwl (%r13), %esi
movq (%rax,%rsi,8), %rdi
movq 0x58(%r13), %rdx
movq 0x80(%r13), %rcx
movq 0xa0(%r13), %r8
movq 0x98(%r13), %r9
callq 0x28b60
jmp 0x2a777
movq 0x40(%rsp), %rcx
movq 0xc0(%rbx), %rax
movzwl (%r13), %esi
movq (%rax,%rsi,8), %rdi
movq 0x58(%r13), %rdx
movq 0x30(%rsp), %r9
orq 0x98(%r13), %r9
callq 0x28c6e
leaq 0x58(%r13), %r12
movq 0x98(%r13), %rdi
callq 0x2661d
movl %eax, %r15d
movzwl (%r13), %eax
imulq $0x30, %rax, %rdi
addq 0xf8(%rbx), %rdi
movq %r12, %rsi
callq 0x275aa
movq 0xf8(%rbx), %rcx
movzwl (%r13), %esi
imulq $0x30, %rsi, %rdx
addq %rdx, %rcx
addq $0x8, %rcx
cmpq %rcx, %rax
jne 0x2a81d
movq 0xc0(%rbx), %rax
movq (%rax,%rsi,8), %rdi
movq (%r12), %rdx
callq 0x28a0c
movq 0x98(%r13), %rdi
callq 0x2661d
movl %eax, %r14d
movq (%rsp), %rax
movzwl 0x68(%rax), %eax
imulq $0x30, %rax, %rdi
addq 0xf8(%rbx), %rdi
movq %r12, %rsi
callq 0x1c49c
movq %r13, 0x30(%rsp)
leaq 0x70(%rsp), %rdi
leaq 0x30(%rsp), %rsi
callq 0x2ab40
addl 0x10(%rsp), %r14d
movl %r14d, %eax
movq %rax, 0x10(%rsp)
movq 0x20(%rsp), %r12
movq 0x60(%rsp), %rax
addl %r15d, %eax
movq %rax, %r15
movq (%rbp), %r14
movq %r12, %rdi
movq %rbp, %rsi
callq 0x2ab26
movq %r14, %rbp
jmp 0x2a5d5
movq 0x10(%rsp), %rcx
addl 0x8(%rsp), %ecx
movq (%rsp), %rdx
addl %r15d, 0x58(%rdx)
movq 0x28(%rsp), %rdx
addl %ecx, (%rax,%rdx,4)
movq 0x18(%rsp), %rax
cmpq $0x0, 0x10(%rax)
je 0x2a89f
pushq $0x18
popq %rdi
callq 0x7370
movq 0x8(%rsp), %rcx
shll $0x9, %ecx
movl %ecx, (%rax)
movq 0x18(%rsp), %rcx
movq %rcx, 0x8(%rax)
andl $0x0, 0x10(%rax)
movq (%rsp), %rcx
movzwl 0x68(%rcx), %ecx
movw %cx, 0x14(%rax)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x2a4a2
testl %r15d, %r15d
je 0x2a8d5
pushq $0x18
popq %rdi
callq 0x7370
shll $0x9, %r15d
movl %r15d, (%rax)
movq (%rsp), %rcx
movq %rcx, 0x8(%rax)
movl $0x3, 0x10(%rax)
movzwl 0x68(%rcx), %ecx
movw %cx, 0x14(%rax)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x2a4a2
cmpq $0x0, 0x80(%rsp)
je 0x2a8f3
movq 0x38(%rbx), %rax
movq 0x38(%rax), %rdi
movq (%rdi), %rax
leaq 0x70(%rsp), %rsi
callq *0x60(%rax)
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
cmpq 0x108(%rbx), %rax
jbe 0x2a93c
movq (%rsp), %rax
movzwl 0x68(%rax), %eax
imulq $0x30, %rax, %rdi
addq 0xf8(%rbx), %rdi
callq 0x2b1e0
callq 0x1f784
movq %rax, %rdi
callq 0x1fafc
addq 0x100(%rbx), %rax
movq %rax, 0x108(%rbx)
leaq 0x70(%rsp), %rdi
callq 0x2adc4
addq $0x88, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
jmp 0x2a977
jmp 0x2a977
movq %rax, %rbx
movq %r15, %rdi
callq 0x7340
jmp 0x2a97a
jmp 0x2a977
jmp 0x2a977
jmp 0x2a977
jmp 0x2a977
jmp 0x2a977
jmp 0x2a977
jmp 0x2a977
movq %rax, %rbx
leaq 0x70(%rsp), %rdi
callq 0x2adc4
movq %rbx, %rdi
callq 0x75d0