// File: /workspace/github_cpp_makefile_star2_O2/Sooryakiran[P]dotV/src/verilog.cpp
// Function: CARRY_RIPPLE_ADDER::CARRY_RIPPLE_ADDER(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, std::vector<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>>>, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, int)
CARRY_RIPPLE_ADDER::CARRY_RIPPLE_ADDER(string name, vector<wire> input_wires, wire output_wire, int n_bits){
    /*------------------------------------------------------------------------------------------
    First we set up inputs and output vectors. The Chip parent expects everything to be of type
    vector<string>, so we set up that accordingly. 

    We also set up the bit width and name of the instance.    
    ------------------------------------------------------------------------------------------*/
    this->name = name;
    this->inputs = input_wires;
    this->outputs.push_back(output_wire);
    this->n_bits = n_bits;

    /*------------------------------------------------------------------------------------------
    Now we declare input and output ports. Note that these are generic input ports and instance
    independent where as the previous 'input_wires' will be different for each instance. 
    ------------------------------------------------------------------------------------------*/
    this->declare("A", CHIP_INPUTS);
    this->declare("B", CHIP_INPUTS);
    this->declare("out", CHIP_OUTPUTS);

    /*------------------------------------------------------------------------------------------
    We define a wire as carry wire. Note that we need to specify the bit width for wires only an
    d not input/output. This is because the bit width of input/output are expected to be equal to
    the bit width. 
    ------------------------------------------------------------------------------------------*/
    wire carry_wire = "CRA_carry_wire";
    this->add_wire("[" + to_string(n_bits) + ":0] " + carry_wire);

    /*------------------------------------------------------------------------------------------
    We need to assign the first bit of the carry wire to be zero. We use verilog("") function to
    embed verilog code inside our module.
    ------------------------------------------------------------------------------------------*/
    this->verilog("assign " + carry_wire + "[0] = 0;");

    /*------------------------------------------------------------------------------------------
    Now we configure wiring for each bits
    ------------------------------------------------------------------------------------------*/
    for(int i =0; i< n_bits; i++){
        string slice = "["+ to_string(i) + "]";
        string next_slice = "[" + to_string(i+1) + "]";

        FULL_ADDER fa("CRA_FA_" + to_string(i),
                      {"A" + slice, "B" + slice, carry_wire + slice},
                      {"out" + slice, carry_wire + next_slice});
        this->add_submodule(fa);
    }

    /*------------------------------------------------------------------------------------------
    After building the module we can use the auto_gen() funtion to automatically generate the m-
    odule definition.
    ------------------------------------------------------------------------------------------*/
    this->definition = this->auto_gen("module CARRY_RIPPLE_ADDER_" + to_string(this->n_bits) + "_BIT");

    /*------------------------------------------------------------------------------------------
    Then we can instruct how each instance has to be generated.
    ------------------------------------------------------------------------------------------*/
    this->generate =  "CARRY_RIPPLE_ADDER_" + to_string(this->n_bits) + "_BIT " + this->name  + " (" + this->inputs.at(0) + ", " + this->inputs.at(1) + ", " + this->outputs.at(0) + ");";
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x628, %rsp            # imm = 0x628
movl %r8d, %r13d
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
callq 0xa690
movq %r12, %rdi
movq %r15, %rsi
callq 0xa410
leaq 0x80(%r12), %rdi
movq %rdi, -0xa8(%rbp)
movq %r14, %rsi
callq 0xa810
leaq 0x98(%r12), %rdi
movq %rdi, -0xa0(%rbp)
movq %rbx, %rsi
callq 0xa3e0
movl %r13d, 0x190(%r12)
leaq 0xed8c(%rip), %rsi      # 0x1f6f2
leaq -0x308(%rbp), %rdi
leaq -0x4b8(%rbp), %rdx
callq 0xac60
leaq -0x308(%rbp), %rsi
movq %r12, %rdi
xorl %edx, %edx
callq 0xa270
leaq -0x308(%rbp), %rdi
callq 0xa370
leaq 0xeb1b(%rip), %rsi      # 0x1f4b8
leaq -0x2e8(%rbp), %rdi
leaq -0x4b8(%rbp), %rdx
callq 0xac60
leaq -0x2e8(%rbp), %rsi
movq %r12, %rdi
xorl %edx, %edx
callq 0xa270
leaq -0x2e8(%rbp), %rdi
callq 0xa370
leaq 0xeaed(%rip), %rsi      # 0x1f4c1
leaq -0x2c8(%rbp), %rdi
leaq -0x4b8(%rbp), %rdx
callq 0xac60
leaq -0x2c8(%rbp), %rsi
pushq $0x1
popq %rdx
movq %r12, %rdi
callq 0xa270
leaq -0x2c8(%rbp), %rdi
callq 0xa370
leaq 0xeb4c(%rip), %rsi      # 0x1f558
leaq -0x110(%rbp), %rdi
leaq -0x4b8(%rbp), %rdx
callq 0xac60
leaq -0x78(%rbp), %rdi
movl %r13d, %esi
callq 0xa9a0
leaq 0xe781(%rip), %rsi      # 0x1f1b3
leaq -0x170(%rbp), %rdi
leaq -0x78(%rbp), %rdx
movq %r12, -0x30(%rbp)
callq 0xac40
leaq 0xeb5c(%rip), %rdx      # 0x1f5a9
leaq -0x4b8(%rbp), %rdi
leaq -0x170(%rbp), %rsi
callq 0xa150
leaq -0x2a8(%rbp), %rdi
leaq -0x4b8(%rbp), %rsi
leaq -0x110(%rbp), %rdx
callq 0xaaf0
leaq 0xb0(%r12), %rdi
leaq -0x2a8(%rbp), %rsi
callq 0xa3e0
leaq -0x2a8(%rbp), %rdi
callq 0xa370
leaq -0x4b8(%rbp), %rdi
callq 0xa370
leaq -0x170(%rbp), %rdi
callq 0xa370
leaq -0x78(%rbp), %rdi
callq 0xa370
leaq 0xeaa5(%rip), %rsi      # 0x1f567
leaq -0x4b8(%rbp), %rdi
leaq -0x110(%rbp), %rdx
callq 0xa6c0
leaq 0xeb28(%rip), %rdx      # 0x1f604
leaq -0x288(%rbp), %rdi
leaq -0x4b8(%rbp), %rsi
callq 0xa150
leaq 0xc8(%r12), %rdi
leaq -0x288(%rbp), %rsi
callq 0xa3e0
leaq -0x288(%rbp), %rdi
callq 0xa370
leaq -0x4b8(%rbp), %r14
movq %r14, %rdi
callq 0xa370
leaq 0x68(%r12), %rax
movq %rax, -0xb0(%rbp)
xorl %ebx, %ebx
testl %r13d, %r13d
cmovlel %ebx, %r13d
movl %r13d, -0x34(%rbp)
leaq -0x170(%rbp), %r13
cmpl -0x34(%rbp), %ebx
je 0x10d7a
movq %r13, %rdi
movl %ebx, %esi
callq 0xa9a0
movq %r14, %rdi
leaq 0xe658(%rip), %rsi      # 0x1f1b3
movq %r13, %rdx
callq 0xac40
leaq -0x98(%rbp), %rdi
movq %r14, %rsi
leaq 0xe6af(%rip), %rdx      # 0x1f223
callq 0xa150
movq %r14, %rdi
callq 0xa370
movq %r13, %rdi
callq 0xa370
leal 0x1(%rbx), %r15d
movq %r13, %rdi
movl %r15d, %esi
callq 0xa9a0
movq %r14, %rdi
leaq 0xe611(%rip), %rsi      # 0x1f1b3
movq %r13, %rdx
callq 0xac40
leaq -0xd0(%rbp), %rdi
movq %r14, %rsi
leaq 0xe668(%rip), %rdx      # 0x1f223
callq 0xa150
movq %r14, %rdi
callq 0xa370
movq %r13, %rdi
callq 0xa370
leaq -0xf0(%rbp), %r12
movq %r12, %rdi
movl %ebx, %esi
callq 0xa9a0
leaq -0x268(%rbp), %rdi
leaq 0xe980(%rip), %rsi      # 0x1f56f
movq %r12, %rdx
callq 0xac40
leaq -0x98(%rbp), %r12
movq %r13, %rdi
leaq 0xeaea(%rip), %rsi      # 0x1f6f2
movq %r12, %rdx
callq 0xa6c0
leaq -0x150(%rbp), %rdi
movq %rdi, %rbx
leaq 0xe897(%rip), %rsi      # 0x1f4b8
movq %r12, %rdx
callq 0xa6c0
leaq -0x130(%rbp), %rdi
movq %rdi, %rbx
leaq -0x110(%rbp), %rsi
movq %r12, %rdx
callq 0xae70
leaq -0x188(%rbp), %rdi
movq %r13, %rsi
pushq $0x3
popq %rdx
leaq -0x1c8(%rbp), %rcx
callq 0xa170
leaq -0x78(%rbp), %rdi
leaq 0xe85b(%rip), %rsi      # 0x1f4c1
leaq -0x98(%rbp), %rdx
callq 0xa6c0
leaq -0x58(%rbp), %rdi
leaq -0x110(%rbp), %rsi
leaq -0xd0(%rbp), %rdx
callq 0xae70
leaq -0x320(%rbp), %rbx
movq %rbx, %rdi
leaq -0x78(%rbp), %rsi
pushq $0x2
popq %rdx
leaq -0x1a8(%rbp), %rcx
callq 0xa170
movq %r14, %rdi
leaq -0x268(%rbp), %rsi
leaq -0x188(%rbp), %rdx
movq %rbx, %rcx
callq 0xa480
movq %rbx, %rdi
callq 0xa550
pushq $0x20
popq %rbx
leaq (%rbx,%rbp), %rdi
addq $-0x78, %rdi
callq 0xa370
addq $-0x20, %rbx
cmpq $-0x20, %rbx
jne 0x10cca
leaq -0x188(%rbp), %rdi
callq 0xa550
pushq $0x40
popq %rbx
leaq (%rbx,%rbp), %rdi
addq $-0x170, %rdi           # imm = 0xFE90
callq 0xa370
addq $-0x20, %rbx
cmpq $-0x20, %rbx
jne 0x10cf0
leaq -0x268(%rbp), %rdi
callq 0xa370
leaq -0xf0(%rbp), %rdi
callq 0xa370
leaq -0x650(%rbp), %rbx
movq %rbx, %rdi
movq %r14, %rsi
callq 0xa850
movq -0xb0(%rbp), %rdi
movq %rbx, %rsi
callq 0xa600
movq %rbx, %rdi
leaq -0x98(%rbp), %rbx
callq 0xa230
movq %r14, %rdi
callq 0xa230
leaq -0xd0(%rbp), %rdi
callq 0xa370
movq %rbx, %rdi
callq 0xa370
movl %r15d, %ebx
movq -0x30(%rbp), %r12
jmp 0x10b3e
movl 0x190(%r12), %esi
leaq -0x78(%rbp), %rdi
callq 0xa9a0
leaq 0xe7e5(%rip), %rsi      # 0x1f577
leaq -0x170(%rbp), %rdi
leaq -0x78(%rbp), %rdx
callq 0xac40
leaq 0xe7e9(%rip), %rdx      # 0x1f592
leaq -0x248(%rbp), %rdi
leaq -0x170(%rbp), %rsi
callq 0xa150
leaq -0x4b8(%rbp), %rdi
leaq -0x248(%rbp), %rdx
movq %r12, %rsi
callq 0xa3f0
leaq 0x20(%r12), %rdi
leaq -0x4b8(%rbp), %rbx
movq %rbx, %rsi
callq 0xa920
movq %rbx, %rdi
callq 0xa370
leaq -0x248(%rbp), %rdi
callq 0xa370
leaq -0x170(%rbp), %rdi
callq 0xa370
leaq -0x78(%rbp), %rdi
callq 0xa370
movl 0x190(%r12), %esi
leaq -0x1e8(%rbp), %rdi
callq 0xa9a0
leaq 0xe754(%rip), %rsi      # 0x1f57e
leaq -0x208(%rbp), %rdi
leaq -0x1e8(%rbp), %rdx
callq 0xac40
movq -0xa8(%rbp), %rbx
leaq 0xe37b(%rip), %rdx      # 0x1f1c6
leaq -0x228(%rbp), %rdi
leaq -0x208(%rbp), %rsi
callq 0xa150
leaq -0x1a8(%rbp), %rdi
leaq -0x228(%rbp), %rsi
movq %r12, %rdx
callq 0xaaf0
leaq 0xe1f2(%rip), %rdx      # 0x1f06d
leaq -0x1c8(%rbp), %rdi
leaq -0x1a8(%rbp), %rsi
callq 0xa150
movq %rbx, %rdi
xorl %esi, %esi
callq 0xa200
leaq -0xf0(%rbp), %rdi
leaq -0x1c8(%rbp), %rsi
movq %rax, %rdx
callq 0xaaf0
leaq 0xe1bb(%rip), %rdx      # 0x1f070
leaq -0xd0(%rbp), %rdi
leaq -0xf0(%rbp), %rsi
callq 0xa150
pushq $0x1
popq %rsi
movq %rbx, %rdi
callq 0xa200
leaq -0x98(%rbp), %rdi
leaq -0xd0(%rbp), %rsi
movq %rax, %rdx
callq 0xaaf0
leaq 0xe180(%rip), %rdx      # 0x1f070
leaq -0x78(%rbp), %rdi
leaq -0x98(%rbp), %rsi
callq 0xa150
movq -0xa0(%rbp), %rdi
xorl %esi, %esi
callq 0xa200
leaq -0x170(%rbp), %rdi
leaq -0x78(%rbp), %rsi
movq %rax, %rdx
callq 0xaaf0
leaq 0xe7e9(%rip), %rdx      # 0x1f711
leaq -0x4b8(%rbp), %rdi
leaq -0x170(%rbp), %rsi
callq 0xa150
addq $0x40, %r12
leaq -0x4b8(%rbp), %rbx
movq %r12, %rdi
movq %rbx, %rsi
callq 0xa920
movq %rbx, %rdi
callq 0xa370
leaq -0x170(%rbp), %rdi
callq 0xa370
leaq -0x78(%rbp), %rdi
callq 0xa370
leaq -0x98(%rbp), %rdi
callq 0xa370
leaq -0xd0(%rbp), %rdi
callq 0xa370
leaq -0xf0(%rbp), %rdi
callq 0xa370
leaq -0x1c8(%rbp), %rdi
callq 0xa370
leaq -0x1a8(%rbp), %rdi
callq 0xa370
leaq -0x228(%rbp), %rdi
callq 0xa370
leaq -0x208(%rbp), %rdi
callq 0xa370
leaq -0x1e8(%rbp), %rdi
callq 0xa370
leaq -0x110(%rbp), %rdi
callq 0xa370
addq $0x628, %rsp            # imm = 0x628
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq %rax, %r14
leaq -0x170(%rbp), %rdi
callq 0xa370
jmp 0x110f7
movq %rax, %r14
jmp 0x11100
movq %rax, %r14
jmp 0x1111d
movq %rax, %r14
jmp 0x1113a
movq %rax, %r14
jmp 0x11146
movq %rax, %r14
jmp 0x11152
movq %rax, %r14
jmp 0x1115e
movq %rax, %r14
jmp 0x1120c
movq %rax, %r14
leaq -0x248(%rbp), %rdi
jmp 0x1108d
jmp 0x11094
jmp 0x110a5
jmp 0x111e4
movq %rax, %r14
leaq -0x288(%rbp), %rdi
callq 0xa370
jmp 0x11061
movq %rax, %r14
leaq -0x4b8(%rbp), %rdi
jmp 0x11207
jmp 0x111e4
movq %rax, %r14
leaq -0x2a8(%rbp), %rdi
callq 0xa370
jmp 0x11086
movq %rax, %r14
leaq -0x4b8(%rbp), %rdi
callq 0xa370
jmp 0x11097
movq %rax, %r14
leaq -0x170(%rbp), %rdi
callq 0xa370
jmp 0x110a8
movq %rax, %r14
leaq -0x78(%rbp), %rdi
jmp 0x11207
jmp 0x111e4
jmp 0x1116a
movq %rax, %r14
leaq -0x2c8(%rbp), %rdi
jmp 0x112d4
jmp 0x1116a
movq %rax, %r14
leaq -0x2e8(%rbp), %rdi
jmp 0x112d4
jmp 0x1116a
movq %rax, %r14
leaq -0x308(%rbp), %rdi
jmp 0x112d4
jmp 0x1116a
movq %rax, %r14
leaq -0x78(%rbp), %rdi
callq 0xa370
leaq -0x98(%rbp), %rdi
callq 0xa370
jmp 0x11111
movq %rax, %r14
leaq -0xd0(%rbp), %rdi
callq 0xa370
leaq -0xf0(%rbp), %rdi
callq 0xa370
jmp 0x1112e
movq %rax, %r14
leaq -0x1c8(%rbp), %rdi
callq 0xa370
leaq -0x1a8(%rbp), %rdi
callq 0xa370
leaq -0x228(%rbp), %rdi
callq 0xa370
leaq -0x208(%rbp), %rdi
callq 0xa370
leaq -0x1e8(%rbp), %rdi
jmp 0x11207
movq %rax, %r14
jmp 0x112d9
movq %rax, %r14
leaq -0x650(%rbp), %rdi
callq 0xa230
jmp 0x111c7
movq %rax, %r14
jmp 0x1119c
movq %rax, %r14
jmp 0x111d3
movq %rax, %r14
leaq -0x320(%rbp), %rdi
callq 0xa550
pushq $0x20
popq %rbx
leaq (%rbx,%rbp), %rdi
addq $-0x78, %rdi
callq 0xa370
addq $-0x20, %rbx
cmpq $-0x20, %rbx
jne 0x1119f
jmp 0x11235
movq %rax, %r14
movq -0x30(%rbp), %r12
jmp 0x112a9
movq %rax, %r14
leaq -0x4b8(%rbp), %rdi
callq 0xa230
movq -0x30(%rbp), %r12
jmp 0x112b5
movq %rax, %r14
jmp 0x11299
movq %rax, %r14
jmp 0x112cd
movq %rax, %r14
jmp 0x11200
movq %rax, %r14
leaq -0x4b8(%rbp), %rdi
callq 0xa370
leaq -0x170(%rbp), %rdi
callq 0xa370
movq -0x30(%rbp), %r12
jmp 0x112cd
movq %rax, %r14
jmp 0x11241
movq %rax, %r14
jmp 0x1127f
movq %rax, %r14
jmp 0x11235
movq %rax, %r14
jmp 0x11273
movq %rax, %r14
leaq -0x78(%rbp), %rdi
callq 0xa370
leaq -0x188(%rbp), %rdi
callq 0xa550
movq -0x30(%rbp), %r12
pushq $0x40
popq %rbx
leaq (%rbx,%rbp), %rdi
addq $-0x170, %rdi           # imm = 0xFE90
callq 0xa370
addq $-0x20, %rbx
cmpq $-0x20, %rbx
jne 0x11248
jmp 0x1129d
movq %rax, %r14
leaq -0x4b8(%rbp), %rdi
callq 0xa370
leaq -0x170(%rbp), %rdi
callq 0xa370
movq -0x30(%rbp), %r12
jmp 0x112c1
movq %rax, %r14
addq $-0x20, %rbx
movq %rbx, %rdi
callq 0xa370
cmpq %r13, %rbx
jne 0x11288
movq -0x30(%rbp), %r12
leaq -0x268(%rbp), %rdi
callq 0xa370
leaq -0xf0(%rbp), %rdi
callq 0xa370
leaq -0xd0(%rbp), %rdi
callq 0xa370
leaq -0x98(%rbp), %rdi
callq 0xa370
leaq -0x110(%rbp), %rdi
callq 0xa370
movq %r12, %rdi
callq 0xa230
movq %r14, %rdi
callq 0xad00
nop