// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/dram_controller.cc
// Function: MEMORY_CONTROLLER::schedule(PACKET_QUEUE*)
void MEMORY_CONTROLLER::schedule(PACKET_QUEUE *queue)
{
    uint64_t read_addr;
    uint32_t read_channel, read_rank, read_bank, read_row;
    uint8_t  row_buffer_hit = 0;

    int oldest_index = -1;
    uint64_t oldest_cycle = UINT64_MAX;

    // first, search for the oldest open row hit
    for (uint32_t i=0; i<queue->SIZE; i++) {

        // already scheduled
        if (queue->entry[i].scheduled) 
            continue;

        // empty entry
        read_addr = queue->entry[i].address;
        if (read_addr == 0) 
            continue;

        read_channel = dram_get_channel(read_addr);
        read_rank = dram_get_rank(read_addr);
        read_bank = dram_get_bank(read_addr);

        // bank is busy
        if (bank_request[read_channel][read_rank][read_bank].working) { // should we check this or not? how do we know if bank is busy or not for all requests in the queue?

            //DP ( if (warmup_complete[0]) {
            //cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " bank is busy";
            //cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            //cout << " write: " << +bank_request[read_channel][read_rank][read_bank].is_write << " read: " << +bank_request[read_channel][read_rank][read_bank].is_read << hex;
            //cout << " address: " << queue->entry[i].address << dec << " channel: " << read_channel << " rank: " << read_rank << " bank: " << read_bank << endl; });

            continue;
        }

        read_row = dram_get_row(read_addr);
        //read_column = dram_get_column(read_addr);

        // check open row
        if (bank_request[read_channel][read_rank][read_bank].open_row != read_row) {

            /*
            DP ( if (warmup_complete[0]) {
            cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " row is inactive";
            cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            cout << " write: " << +bank_request[read_channel][read_rank][read_bank].is_write << " read: " << +bank_request[read_channel][read_rank][read_bank].is_read << hex;
            cout << " address: " << queue->entry[i].address << dec << " channel: " << read_channel << " rank: " << read_rank << " bank: " << read_bank << endl; });
            */

            continue;
        }

        // select the oldest entry
        if (queue->entry[i].event_cycle < oldest_cycle) {
            oldest_cycle = queue->entry[i].event_cycle;
            oldest_index = i;
            row_buffer_hit = 1;
        }	  
    }

    if (oldest_index == -1) { // no matching open_row (row buffer miss)

        oldest_cycle = UINT64_MAX;
        for (uint32_t i=0; i<queue->SIZE; i++) {

            // already scheduled
            if (queue->entry[i].scheduled)
                continue;

            // empty entry
            read_addr = queue->entry[i].address;
            if (read_addr == 0) 
                continue;

            // bank is busy
            read_channel = dram_get_channel(read_addr);
            read_rank = dram_get_rank(read_addr);
            read_bank = dram_get_bank(read_addr);
            if (bank_request[read_channel][read_rank][read_bank].working) 
                continue;

            //read_row = dram_get_row(read_addr);
            //read_column = dram_get_column(read_addr);

            // select the oldest entry
            if (queue->entry[i].event_cycle < oldest_cycle) {
                oldest_cycle = queue->entry[i].event_cycle;
                oldest_index = i;
            }
        }
    }

    // at this point, the scheduler knows which bank to access and if the request is a row buffer hit or miss
    if (oldest_index != -1) { // scheduler might not find anything if all requests are already scheduled or all banks are busy

        uint64_t LATENCY = 0;
        if (row_buffer_hit)  
            LATENCY = tCAS;
        else 
            LATENCY = tRP + tRCD + tCAS;

        uint64_t op_addr = queue->entry[oldest_index].address;
        uint32_t op_cpu = queue->entry[oldest_index].cpu,
                 op_channel = dram_get_channel(op_addr), 
                 op_rank = dram_get_rank(op_addr), 
                 op_bank = dram_get_bank(op_addr), 
                 op_row = dram_get_row(op_addr);
#ifdef DEBUG_PRINT
        uint32_t op_column = dram_get_column(op_addr);
#endif

        // this bank is now busy
        bank_request[op_channel][op_rank][op_bank].working = 1;
        bank_request[op_channel][op_rank][op_bank].working_type = queue->entry[oldest_index].type;
        bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu] + LATENCY;

        bank_request[op_channel][op_rank][op_bank].request_index = oldest_index;
        bank_request[op_channel][op_rank][op_bank].row_buffer_hit = row_buffer_hit;
        if (queue->is_WQ) {
            bank_request[op_channel][op_rank][op_bank].is_write = 1;
            bank_request[op_channel][op_rank][op_bank].is_read = 0;
            scheduled_writes++;
        }
        else {
            bank_request[op_channel][op_rank][op_bank].is_write = 0;
            bank_request[op_channel][op_rank][op_bank].is_read = 1;
            scheduled_reads++;
        }

        // update open row
        bank_request[op_channel][op_rank][op_bank].open_row = op_row;

        queue->entry[oldest_index].scheduled = 1;
        queue->entry[oldest_index].event_cycle = current_core_cycle[op_cpu] + LATENCY;

        update_schedule_cycle(queue);
        update_process_cycle(queue);

        DP (if (warmup_complete[op_cpu]) {
        cout << "[" << queue->NAME << "] " <<  __func__ << " instr_id: " << queue->entry[oldest_index].instr_id;
        cout << " row buffer: " << (row_buffer_hit ? (int)bank_request[op_channel][op_rank][op_bank].open_row : -1) << hex;
        cout << " address: " << queue->entry[oldest_index].address << " full_addr: " << queue->entry[oldest_index].full_addr << dec;
        cout << " index: " << oldest_index << " occupancy: " << queue->occupancy;
        cout << " ch: " << op_channel << " rank: " << op_rank << " bank: " << op_bank; // wrong from here
        cout << " row: " << op_row << " col: " << op_column;
        cout << " current: " << current_core_cycle[op_cpu] << " event: " << queue->entry[oldest_index].event_cycle << endl; });
    }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movl 0x20(%rsi), %esi
leaq 0x7858(%rdi), %rax
pushq $-0x1
popq %rdx
pushq $-0x1
popq %r10
movl $0x378, %r8d            # imm = 0x378
xorl %r9d, %r9d
xorl %ecx, %ecx
cmpq %r9, %rsi
je 0x9590
movq 0x98(%rbx), %r11
cmpb $0x0, -0x376(%r11,%r8)
je 0x9537
incq %r9
addq $0x380, %r8             # imm = 0x380
jmp 0x9514
movq -0x38(%r11,%r8), %r14
testq %r14, %r14
je 0x952b
movl %r14d, %r15d
shrl $0x8, %r15d
andl $0x7, %r15d
movl %r14d, %r12d
andl $0x7, %r12d
imulq $0x140, %r15, %r15      # imm = 0x140
addq %rax, %r15
imulq $0x28, %r12, %r12
cmpb $0x0, 0x1c(%r12,%r15)
jne 0x952b
addq %r12, %r15
shrl $0xb, %r14d
andl $0x7fff, %r14d          # imm = 0x7FFF
cmpl %r14d, 0x18(%r15)
jne 0x952b
movq (%r11,%r8), %r11
cmpq %r10, %r11
jae 0x952b
movb $0x1, %cl
movq %r11, %r10
movl %r9d, %edx
jmp 0x952b
cmpl $-0x1, %edx
jne 0x9611
pushq $-0x1
popq %rdx
pushq $-0x1
popq %r8
movl $0x378, %r9d            # imm = 0x378
xorl %r10d, %r10d
cmpq %r10, %rsi
je 0x9608
movq 0x98(%rbx), %r11
cmpb $0x0, -0x376(%r11,%r9)
je 0x95c8
incq %r10
addq $0x380, %r9             # imm = 0x380
jmp 0x95a5
movq -0x38(%r11,%r9), %r14
testq %r14, %r14
je 0x95bc
movl %r14d, %r15d
shrl $0x8, %r15d
andl $0x7, %r15d
andl $0x7, %r14d
imulq $0x140, %r15, %r15      # imm = 0x140
addq %rax, %r15
imulq $0x28, %r14, %r14
cmpb $0x0, 0x1c(%r14,%r15)
jne 0x95bc
movq (%r11,%r9), %r11
cmpq %r8, %r11
cmovbq %r11, %r8
cmovbl %r10d, %edx
jmp 0x95bc
cmpl $-0x1, %edx
je 0x9708
testb %cl, %cl
je 0x961d
movl 0xebf1(%rip), %esi      # 0x1820c
jmp 0x962f
movl 0xebe5(%rip), %esi      # 0x18208
addl 0xebdb(%rip), %esi      # 0x18204
addl 0xebdd(%rip), %esi      # 0x1820c
movl %esi, %esi
movq 0x98(%rbx), %r8
movslq %edx, %r15
imulq $0x380, %r15, %rdx      # imm = 0x380
movq 0x340(%r8,%rdx), %r10
movl 0x330(%r8,%rdx), %r9d
movl %r10d, %r11d
shrl $0x8, %r11d
andl $0x7, %r11d
movl %r10d, %r14d
andl $0x7, %r14d
shrl $0xb, %r10d
andl $0x7fff, %r10d          # imm = 0x7FFF
imulq $0x140, %r11, %r11      # imm = 0x140
addq %r11, %rax
imulq $0x28, %r14, %r12
leaq (%rax,%r12), %r11
movb $0x1, 0x1c(%r12,%rax)
movb 0x32f(%r8,%rdx), %bpl
movb %bpl, 0x1d(%r12,%rax)
leaq 0x73815(%rip), %r14     # 0x7ceb0
movq (%r14,%r9,8), %r13
addq %rsi, %r13
movq %r13, (%r12,%rax)
movl %r15d, 0x24(%r12,%rax)
movb %cl, 0x1e(%r12,%rax)
cmpb $0x0, 0x25(%rbx)
je 0x96c2
incl 0x784c(%rdi)
movb $0x1, %cl
xorl %eax, %eax
jmp 0x96cc
incl 0x7848(%rdi)
movb $0x1, %al
xorl %ecx, %ecx
movb %cl, 0x20(%r11)
movb %al, 0x21(%r11)
movl %r10d, 0x18(%r11)
movb $0x1, 0x2(%r8,%rdx)
addq (%r14,%r9,8), %rsi
movq %rsi, 0x378(%r8,%rdx)
movq %rbx, %rsi
callq 0x9270
movq %rbx, %rsi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x92c4
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop