// File: /workspace/github_c_makefile_star2_O0/samtools[P]htslib/htscodecs/htscodecs/rANS_static32x16pr_avx512.c
// Function: rans_compress_O1_32x16_avx512
unsigned char *rans_compress_O1_32x16_avx512(unsigned char *in,
                                             unsigned int in_size,
                                             unsigned char *out,
                                             unsigned int *out_size) {
    unsigned char *cp, *out_end, *out_free = NULL;
    unsigned int tab_size;
    uint32_t bound = rans_compress_bound_4x16(in_size,1)-20;
    int z;
    RansState ransN[32] __attribute__((aligned(64)));

    if (in_size < 32) // force O0 instead
        return NULL;

    if (!out) {
        *out_size = bound;
        out = malloc(*out_size);
    }
    if (!out || bound > *out_size)
        return NULL;

    if (((size_t)out)&1)
        bound--;
    out_end = out + bound;

    RansEncSymbol (*syms)[256] = htscodecs_tls_alloc(256 * (sizeof(*syms)));
    if (!syms) {
        free(out_free);
        return NULL;
    }

    cp = out;
    int shift = encode_freq1(in, in_size, 32, syms, &cp);
    if (shift < 0) {
        free(out_free);
        htscodecs_tls_free(syms);
        return NULL;
    }
    tab_size = cp - out;

    for (z = 0; z < 32; z++)
      RansEncInit(&ransN[z]);

    uint8_t* ptr = out_end;

    int iN[32] __attribute__((aligned(64)));
    int isz4 = in_size/32;
    for (z = 0; z < 32; z++)
        iN[z] = (z+1)*isz4-2;

    uint32_t lN[32] __attribute__((aligned(64)));
    for (z = 0; z < 32; z++)
        lN[z] = in[iN[z]+1];

    // Deal with the remainder
    z = 32-1;
    lN[z] = in[in_size-1];
    for (iN[z] = in_size-2; iN[z] > 32*isz4-2; iN[z]--) {
        unsigned char c = in[iN[z]];
        RansEncPutSymbol(&ransN[z], &ptr, &syms[c][lN[z]]);
        lN[z] = c;
    }

    LOAD512(Rv, ransN);

    uint16_t *ptr16 = (uint16_t *)ptr;
    LOAD512(iN, iN);
    LOAD512(last, lN);

    __m512i c1 = _mm512_i32gather_epi32x1(iN1, in);
    __m512i c2 = _mm512_i32gather_epi32x1(iN2, in);

    // We cache the next 64-bytes locally and transpose.
    // This means we can load 32 ints from t32[x] with load instructions
    // instead of gathers.  The copy, transpose and expand is easier done
    // in scalar code.
#define BATCH 64
    uint8_t t32[BATCH][32] __attribute__((aligned(64)));
    int next_batch;
    if (iN[0] > BATCH) {
        int i, j;
        for (i = 0; i < BATCH; i++)
            // memcpy(c[i], &in[iN[i]-32], 32); fast mode
            for (j = 0; j < 32; j++)
                t32[BATCH-1-i][j] = in[iN[j]-1-i];
        next_batch = BATCH;
    } else {
        next_batch = -1;
    }

    for (; iN[0] >= 0; iN[0]--) {
        // Note, consider doing the same approach for the AVX2 encoder.
        // Maybe we can also get gather working well there?
        // Gather here is still a major latency bottleneck, consuming
        // around 40% of CPU cycles overall.

        // FIXME: maybe we need to cope with in[31] read over-flow
        // on loop cycles 0, 1, 2 where gather reads 32-bits instead of
        // 8 bits.  Use set instead there on c2?

        // index into syms[0][0] array, used for x_max, rcp_freq, and bias
        __m512i vidx1 = _mm512_slli_epi32(c1, 8);
        __m512i vidx2 = _mm512_slli_epi32(c2, 8);
        vidx1 = _mm512_add_epi32(vidx1, last1);
        vidx2 = _mm512_add_epi32(vidx2, last2);
        vidx1 = _mm512_slli_epi32(vidx1, 2);
        vidx2 = _mm512_slli_epi32(vidx2, 2);

        // ------------------------------------------------------------
        //      for (z = NX-1; z >= 0; z--) {
        //          if (ransN[z] >= x_max[z]) {
        //              *--ptr16 = ransN[z] & 0xffff;
        //              ransN[z] >>= 16;
        //          }
        //      }

#define SET512x(a,x) \
        __m512i a##1 = _mm512_i32gather_epi32x(vidx1, &syms[0][0].x, 4); \
        __m512i a##2 = _mm512_i32gather_epi32x(vidx2, &syms[0][0].x, 4)

        // Start of next loop, moved here to remove latency.
        // last[z] = c[z]
        // iN[z]--
        // c[z] = in[iN[z]]
        last1 = c1;
        last2 = c2;
        iN1 = _mm512_sub_epi32(iN1, _mm512_set1_epi32(1));
        iN2 = _mm512_sub_epi32(iN2, _mm512_set1_epi32(1));

        // Code below is equivalent to this:
        // c1 = _mm512_i32gather_epi32(iN1, in, 1);
        // c2 = _mm512_i32gather_epi32(iN2, in, 1);

        // Better when we have a power of 2
        if (next_batch >= 0) {
            if (--next_batch < 0 && iN[0] > BATCH) {
                // Load 32 BATCH blocks of data.
                // Executed once every BATCH cycles
                int i, j;
                uint8_t c[32][BATCH];
                iN[0] += BATCH;
                for (j = 0; j < 32; j++) {
                    iN[j] -= BATCH;
                    memcpy(c[j], &in[iN[j]-BATCH], BATCH);
                }
                // transpose matrix from 32xBATCH to BATCHx32
                for (j = 0; j < 32; j++) {
                    for (i = 0; i < BATCH; i+=16) {
                        int z;
                        for (z = 0; z < 16; z++)
                            t32[i+z][j] = c[j][i+z];
                    }
                }
                next_batch = BATCH-1;
            }
            if (next_batch >= 0) {
                // Copy from our of our pre-loaded BATCHx32 tables
                // Executed every cycles
                __m128i c1_ = _mm_load_si128((__m128i *)&t32[next_batch][0]);
                __m128i c2_ = _mm_load_si128((__m128i *)&t32[next_batch][16]);
                c1 = _mm512_cvtepu8_epi32(c1_);
                c2 = _mm512_cvtepu8_epi32(c2_);
            }
        }

        if (next_batch < 0 && iN[0]) {
            // no pre-loaded data as within BATCHx32 of input end
            c1 = _mm512_i32gather_epi32x1(iN1, in);
            c2 = _mm512_i32gather_epi32x1(iN2, in);

            // Speeds up clang, even though not needed any more.
            // Harmless to leave here.
            c1 = _mm512_and_si512(c1, _mm512_set1_epi32(0xff));
            c2 = _mm512_and_si512(c2, _mm512_set1_epi32(0xff));
        }
        // End of "equivalent to" code block

        SET512x(xmax, x_max); // high latency

        uint16_t gt_mask1 = _mm512_cmpgt_epi32_mask(Rv1, xmax1);
        int pc1 = _mm_popcnt_u32(gt_mask1);
        __m512i Rp1 = _mm512_and_si512(Rv1, _mm512_set1_epi32(0xffff));
        __m512i Rp2 = _mm512_and_si512(Rv2, _mm512_set1_epi32(0xffff));
        uint16_t gt_mask2 = _mm512_cmpgt_epi32_mask(Rv2, xmax2);
        SET512x(SDv, cmpl_freq); // good
        int pc2 = _mm_popcnt_u32(gt_mask2);

        Rp1 = _mm512_maskz_compress_epi32(gt_mask1, Rp1);
        Rp2 = _mm512_maskz_compress_epi32(gt_mask2, Rp2);

        _mm512_mask_cvtepi32_storeu_epi16(ptr16-pc2, (1<<pc2)-1, Rp2);
        ptr16 -= pc2;
        _mm512_mask_cvtepi32_storeu_epi16(ptr16-pc1, (1<<pc1)-1, Rp1);
        ptr16 -= pc1;

        Rv1 = _mm512_mask_srli_epi32(Rv1, gt_mask1, Rv1, 16);
        Rv2 = _mm512_mask_srli_epi32(Rv2, gt_mask2, Rv2, 16);

        // ------------------------------------------------------------
        // uint32_t q = (uint32_t) (((uint64_t)ransN[z] * rcp_freq[z])
        //                          >> rcp_shift[z]);
        // ransN[z] = ransN[z] + bias[z] + q * cmpl_freq[z];
        SET512x(rfv, rcp_freq); // good-ish

        __m512i rf1_hm = _mm512_mul_epu32(_mm512_srli_epi64(Rv1, 32),
                                          _mm512_srli_epi64(rfv1, 32));
        __m512i rf2_hm = _mm512_mul_epu32(_mm512_srli_epi64(Rv2, 32),
                                          _mm512_srli_epi64(rfv2, 32));
        __m512i rf1_lm = _mm512_srli_epi64(_mm512_mul_epu32(Rv1, rfv1), 32);
        __m512i rf2_lm = _mm512_srli_epi64(_mm512_mul_epu32(Rv2, rfv2), 32);

        const __m512i top32 = _mm512_set1_epi64((uint64_t)0xffffffff00000000);
        rf1_hm = _mm512_and_epi32(rf1_hm, top32);
        rf2_hm = _mm512_and_epi32(rf2_hm, top32);
        rfv1 = _mm512_or_epi32(rf1_lm, rf1_hm);
        rfv2 = _mm512_or_epi32(rf2_lm, rf2_hm);

        SET512x(biasv, bias); // good
        __m512i shiftv1 = _mm512_srli_epi32(SDv1, 16);
        __m512i shiftv2 = _mm512_srli_epi32(SDv2, 16);

        shiftv1 = _mm512_sub_epi32(shiftv1, _mm512_set1_epi32(32));
        shiftv2 = _mm512_sub_epi32(shiftv2, _mm512_set1_epi32(32));

        __m512i qv1 = _mm512_srlv_epi32(rfv1, shiftv1);
        __m512i qv2 = _mm512_srlv_epi32(rfv2, shiftv2);

        const __m512i bot16 = _mm512_set1_epi32(0xffff);
        qv1 = _mm512_mullo_epi32(qv1, _mm512_and_si512(SDv1, bot16));
        qv2 = _mm512_mullo_epi32(qv2, _mm512_and_si512(SDv2, bot16));

        qv1 = _mm512_add_epi32(qv1, biasv1);
        Rv1 = _mm512_add_epi32(Rv1, qv1);

        qv2 = _mm512_add_epi32(qv2, biasv2);
        Rv2 = _mm512_add_epi32(Rv2, qv2);
    }

    STORE512(Rv, ransN);
    STORE512(last, lN);

    ptr = (uint8_t *)ptr16;

    for (z = 32-1; z>=0; z--)
        RansEncPutSymbol(&ransN[z], &ptr, &syms[0][lN[z]]);

    for (z = 32-1; z >= 0; z--)
        RansEncFlush(&ransN[z], &ptr);

    // Finalise block size and return it
    *out_size = (out_end - ptr) + tab_size;

//    cp = out;
//    *cp++ = (in_size>> 0) & 0xff;
//    *cp++ = (in_size>> 8) & 0xff;
//    *cp++ = (in_size>>16) & 0xff;
//    *cp++ = (in_size>>24) & 0xff;

    memmove(out + tab_size, ptr, out_end-ptr);

    htscodecs_tls_free(syms);
    return out;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
andq $-0x40, %rsp
subq $0x3cc0, %rsp           # imm = 0x3CC0
movq %rdi, 0x1bd0(%rsp)
movl %esi, 0x1bcc(%rsp)
movq %rdx, 0x1bc0(%rsp)
movq %rcx, 0x1bb8(%rsp)
movq $0x0, 0x1ba0(%rsp)
movl 0x1bcc(%rsp), %edi
movl $0x1, %esi
callq 0x8e2d0
subl $0x14, %eax
movl %eax, 0x1b98(%rsp)
cmpl $0x20, 0x1bcc(%rsp)
jae 0xaab30
movq $0x0, 0x1bd8(%rsp)
jmp 0xac67a
cmpq $0x0, 0x1bc0(%rsp)
jne 0xaab65
movl 0x1b98(%rsp), %ecx
movq 0x1bb8(%rsp), %rax
movl %ecx, (%rax)
movq 0x1bb8(%rsp), %rax
movl (%rax), %eax
movl %eax, %edi
callq 0x4650
movq %rax, 0x1bc0(%rsp)
cmpq $0x0, 0x1bc0(%rsp)
je 0xaab83
movl 0x1b98(%rsp), %eax
movq 0x1bb8(%rsp), %rcx
cmpl (%rcx), %eax
jbe 0xaab94
movq $0x0, 0x1bd8(%rsp)
jmp 0xac67a
movq 0x1bc0(%rsp), %rax
andq $0x1, %rax
cmpq $0x0, %rax
je 0xaabb7
movl 0x1b98(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x1b98(%rsp)
movq 0x1bc0(%rsp), %rax
movl 0x1b98(%rsp), %ecx
addq %rcx, %rax
movq %rax, 0x1ba8(%rsp)
movl $0x100000, %edi         # imm = 0x100000
callq 0xce6a0
movq %rax, 0x1af8(%rsp)
cmpq $0x0, 0x1af8(%rsp)
jne 0xaac0c
movq 0x1ba0(%rsp), %rdi
callq 0x45a0
movq $0x0, 0x1bd8(%rsp)
jmp 0xac67a
movq 0x1bc0(%rsp), %rax
movq %rax, 0x1bb0(%rsp)
movq 0x1bd0(%rsp), %rdi
movl 0x1bcc(%rsp), %esi
movq 0x1af8(%rsp), %rcx
movl $0x20, %edx
leaq 0x1bb0(%rsp), %r8
callq 0xac690
movl %eax, 0x1af4(%rsp)
cmpl $0x0, 0x1af4(%rsp)
jge 0xaac81
movq 0x1ba0(%rsp), %rdi
callq 0x45a0
movq 0x1af8(%rsp), %rdi
callq 0xce8f0
movq $0x0, 0x1bd8(%rsp)
jmp 0xac67a
movq 0x1bb0(%rsp), %rax
movq 0x1bc0(%rsp), %rcx
subq %rcx, %rax
movl %eax, 0x1b9c(%rsp)
movl $0x0, 0x1b94(%rsp)
cmpl $0x20, 0x1b94(%rsp)
jge 0xaacdf
movslq 0x1b94(%rsp), %rax
leaq 0x1b00(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
callq 0xa9160
movl 0x1b94(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x1b94(%rsp)
jmp 0xaaca6
movq 0x1ba8(%rsp), %rax
movq %rax, 0x1ae8(%rsp)
movl 0x1bcc(%rsp), %eax
shrl $0x5, %eax
movl %eax, 0x1a3c(%rsp)
movl $0x0, 0x1b94(%rsp)
cmpl $0x20, 0x1b94(%rsp)
jge 0xaad4c
movl 0x1b94(%rsp), %ecx
addl $0x1, %ecx
imull 0x1a3c(%rsp), %ecx
subl $0x2, %ecx
movslq 0x1b94(%rsp), %rax
movl %ecx, 0x1a40(%rsp,%rax,4)
movl 0x1b94(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x1b94(%rsp)
jmp 0xaad0b
movl $0x0, 0x1b94(%rsp)
cmpl $0x20, 0x1b94(%rsp)
jge 0xaada4
movq 0x1bd0(%rsp), %rax
movslq 0x1b94(%rsp), %rcx
movl 0x1a40(%rsp,%rcx,4), %ecx
addl $0x1, %ecx
movslq %ecx, %rcx
movzbl (%rax,%rcx), %ecx
movslq 0x1b94(%rsp), %rax
movl %ecx, 0x1980(%rsp,%rax,4)
movl 0x1b94(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x1b94(%rsp)
jmp 0xaad57
movl $0x1f, 0x1b94(%rsp)
movq 0x1bd0(%rsp), %rax
movl 0x1bcc(%rsp), %ecx
subl $0x1, %ecx
movl %ecx, %ecx
movzbl (%rax,%rcx), %ecx
movslq 0x1b94(%rsp), %rax
movl %ecx, 0x1980(%rsp,%rax,4)
movl 0x1bcc(%rsp), %ecx
subl $0x2, %ecx
movslq 0x1b94(%rsp), %rax
movl %ecx, 0x1a40(%rsp,%rax,4)
movslq 0x1b94(%rsp), %rax
movl 0x1a40(%rsp,%rax,4), %eax
movl 0x1a3c(%rsp), %ecx
shll $0x5, %ecx
subl $0x2, %ecx
cmpl %ecx, %eax
jle 0xaaebb
movq 0x1bd0(%rsp), %rax
movslq 0x1b94(%rsp), %rcx
movslq 0x1a40(%rsp,%rcx,4), %rcx
movb (%rax,%rcx), %al
movb %al, 0x197f(%rsp)
movslq 0x1b94(%rsp), %rax
leaq 0x1b00(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
movq 0x1af8(%rsp), %rdx
movzbl 0x197f(%rsp), %eax
shlq $0xc, %rax
addq %rax, %rdx
movslq 0x1b94(%rsp), %rax
movl 0x1980(%rsp,%rax,4), %eax
shlq $0x4, %rax
addq %rax, %rdx
leaq 0x1ae8(%rsp), %rsi
callq 0xa9180
movzbl 0x197f(%rsp), %ecx
movslq 0x1b94(%rsp), %rax
movl %ecx, 0x1980(%rsp,%rax,4)
movslq 0x1b94(%rsp), %rax
movl 0x1a40(%rsp,%rax,4), %ecx
addl $-0x1, %ecx
movl %ecx, 0x1a40(%rsp,%rax,4)
jmp 0xaadef
leaq 0x1b00(%rsp), %rax
movq %rax, 0x1c08(%rsp)
movq 0x1c08(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x1900(%rsp)
leaq 0x1b00(%rsp), %rax
addq $0x40, %rax
movq %rax, 0x1c00(%rsp)
movq 0x1c00(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x18c0(%rsp)
movq 0x1ae8(%rsp), %rax
movq %rax, 0x18b8(%rsp)
leaq 0x1a40(%rsp), %rax
movq %rax, 0x1bf8(%rsp)
movq 0x1bf8(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x1840(%rsp)
leaq 0x1a40(%rsp), %rax
addq $0x40, %rax
movq %rax, 0x1bf0(%rsp)
movq 0x1bf0(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x1800(%rsp)
leaq 0x1980(%rsp), %rax
movq %rax, 0x1be8(%rsp)
movq 0x1be8(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x17c0(%rsp)
leaq 0x1980(%rsp), %rax
addq $0x40, %rax
movq %rax, 0x1be0(%rsp)
movq 0x1be0(%rsp), %rax
vmovdqa64 (%rax), %zmm0
vmovdqa64 %zmm0, 0x1780(%rsp)
vmovdqa64 0x1840(%rsp), %zmm0
movq 0x1bd0(%rsp), %rdi
callq 0xacb40
vmovdqa64 %zmm0, 0x1740(%rsp)
vmovdqa64 0x1800(%rsp), %zmm0
movq 0x1bd0(%rsp), %rdi
callq 0xacb40
vmovdqa64 %zmm0, 0x1700(%rsp)
cmpl $0x40, 0x1a40(%rsp)
jle 0xab0b9
movl $0x0, 0xef8(%rsp)
cmpl $0x40, 0xef8(%rsp)
jge 0xab0ac
movl $0x0, 0xef4(%rsp)
cmpl $0x20, 0xef4(%rsp)
jge 0xab094
movq 0x1bd0(%rsp), %rax
movslq 0xef4(%rsp), %rcx
movl 0x1a40(%rsp,%rcx,4), %ecx
subl $0x1, %ecx
subl 0xef8(%rsp), %ecx
movslq %ecx, %rcx
movb (%rax,%rcx), %dl
movl $0x3f, %eax
subl 0xef8(%rsp), %eax
movslq %eax, %rcx
leaq 0xf00(%rsp), %rax
shlq $0x5, %rcx
addq %rcx, %rax
movslq 0xef4(%rsp), %rcx
movb %dl, (%rax,%rcx)
movl 0xef4(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xef4(%rsp)
jmp 0xab027
jmp 0xab096
movl 0xef8(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xef8(%rsp)
jmp 0xab00e
movl $0x40, 0xefc(%rsp)
jmp 0xab0c4
movl $0xffffffff, 0xefc(%rsp) # imm = 0xFFFFFFFF
jmp 0xab0c6
cmpl $0x0, 0x1a40(%rsp)
jl 0xac43b
vmovdqa64 0x1740(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3980(%rsp)
movl $0x8, 0x397c(%rsp)
vmovdqa64 0x3980(%rsp), %zmm0
vmovd 0x397c(%rsp), %xmm1
vpslld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xe80(%rsp)
vmovdqa64 0x1700(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3900(%rsp)
movl $0x8, 0x38fc(%rsp)
vmovdqa64 0x3900(%rsp), %zmm0
vmovd 0x38fc(%rsp), %xmm1
vpslld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xe40(%rsp)
vmovdqa64 0xe80(%rsp), %zmm1
vmovdqa64 0x17c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x35c0(%rsp)
vmovdqa64 %zmm0, 0x3580(%rsp)
vmovdqa64 0x35c0(%rsp), %zmm0
vmovdqa64 0x3580(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xe80(%rsp)
vmovdqa64 0xe40(%rsp), %zmm1
vmovdqa64 0x1780(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3540(%rsp)
vmovdqa64 %zmm0, 0x3500(%rsp)
vmovdqa64 0x3540(%rsp), %zmm0
vmovdqa64 0x3500(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xe40(%rsp)
vmovdqa64 0xe80(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3880(%rsp)
movl $0x2, 0x387c(%rsp)
vmovdqa64 0x3880(%rsp), %zmm0
vmovd 0x387c(%rsp), %xmm1
vpslld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xe80(%rsp)
vmovdqa64 0xe40(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3800(%rsp)
movl $0x2, 0x37fc(%rsp)
vmovdqa64 0x3800(%rsp), %zmm0
vmovd 0x37fc(%rsp), %xmm1
vpslld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xe40(%rsp)
vmovdqa64 0x1740(%rsp), %zmm0
vmovdqa64 %zmm0, 0x17c0(%rsp)
vmovdqa64 0x1700(%rsp), %zmm0
vmovdqa64 %zmm0, 0x1780(%rsp)
vmovdqa64 0x1840(%rsp), %zmm1
movl $0x1, 0x23bc(%rsp)
vpbroadcastd 0x23bc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2340(%rsp)
vmovdqa64 0x2340(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3b80(%rsp)
vmovdqa64 %zmm0, 0x3b40(%rsp)
vmovdqa64 0x3b80(%rsp), %zmm0
vmovdqa64 0x3b40(%rsp), %zmm1
vpsubd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x1840(%rsp)
vmovdqa64 0x1800(%rsp), %zmm1
movl $0x1, 0x233c(%rsp)
vpbroadcastd 0x233c(%rsp), %zmm0
vmovdqa64 %zmm0, 0x22c0(%rsp)
vmovdqa64 0x22c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3b00(%rsp)
vmovdqa64 %zmm0, 0x3ac0(%rsp)
vmovdqa64 0x3b00(%rsp), %zmm0
vmovdqa64 0x3ac0(%rsp), %zmm1
vpsubd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x1800(%rsp)
cmpl $0x0, 0xefc(%rsp)
jl 0xab5e8
movl 0xefc(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0xefc(%rsp)
cmpl $0x0, %eax
jge 0xab51a
cmpl $0x40, 0x1a40(%rsp)
jle 0xab51a
movl 0x1a40(%rsp), %eax
addl $0x40, %eax
movl %eax, 0x1a40(%rsp)
movl $0x0, 0xe38(%rsp)
cmpl $0x20, 0xe38(%rsp)
jge 0xab42f
movslq 0xe38(%rsp), %rax
movl 0x1a40(%rsp,%rax,4), %ecx
subl $0x40, %ecx
movl %ecx, 0x1a40(%rsp,%rax,4)
movslq 0xe38(%rsp), %rax
leaq 0x630(%rsp), %rdi
shlq $0x6, %rax
addq %rax, %rdi
movq 0x1bd0(%rsp), %rsi
movslq 0xe38(%rsp), %rax
movl 0x1a40(%rsp,%rax,4), %eax
subl $0x40, %eax
cltq
addq %rax, %rsi
movl $0x40, %edx
vzeroupper
callq 0x43b0
movl 0xe38(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xe38(%rsp)
jmp 0xab3b6
movl $0x0, 0xe38(%rsp)
cmpl $0x20, 0xe38(%rsp)
jge 0xab50f
movl $0x0, 0xe3c(%rsp)
cmpl $0x40, 0xe3c(%rsp)
jge 0xab4f7
movl $0x0, 0x62c(%rsp)
cmpl $0x10, 0x62c(%rsp)
jge 0xab4df
movslq 0xe38(%rsp), %rcx
leaq 0x630(%rsp), %rax
shlq $0x6, %rcx
addq %rcx, %rax
movl 0xe3c(%rsp), %ecx
addl 0x62c(%rsp), %ecx
movslq %ecx, %rcx
movb (%rax,%rcx), %dl
movl 0xe3c(%rsp), %eax
addl 0x62c(%rsp), %eax
movslq %eax, %rcx
leaq 0xf00(%rsp), %rax
shlq $0x5, %rcx
addq %rcx, %rax
movslq 0xe38(%rsp), %rcx
movb %dl, (%rax,%rcx)
movl 0x62c(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x62c(%rsp)
jmp 0xab46c
jmp 0xab4e1
movl 0xe3c(%rsp), %eax
addl $0x10, %eax
movl %eax, 0xe3c(%rsp)
jmp 0xab453
jmp 0xab4f9
movl 0xe38(%rsp), %eax
addl $0x1, %eax
movl %eax, 0xe38(%rsp)
jmp 0xab43a
movl $0x3f, 0xefc(%rsp)
cmpl $0x0, 0xefc(%rsp)
jl 0xab5e6
movslq 0xefc(%rsp), %rcx
leaq 0xf00(%rsp), %rax
shlq $0x5, %rcx
addq %rcx, %rax
movq %rax, 0x3bf8(%rsp)
movq 0x3bf8(%rsp), %rax
vmovdqa (%rax), %xmm0
vmovdqa %xmm0, 0x610(%rsp)
movslq 0xefc(%rsp), %rcx
leaq 0xf00(%rsp), %rax
shlq $0x5, %rcx
addq %rcx, %rax
addq $0x10, %rax
movq %rax, 0x3bf0(%rsp)
movq 0x3bf0(%rsp), %rax
vmovdqa (%rax), %xmm0
vmovdqa %xmm0, 0x600(%rsp)
vmovdqa 0x610(%rsp), %xmm0
vmovdqa %xmm0, 0x1c20(%rsp)
vmovdqa 0x1c20(%rsp), %xmm0
vpmovzxbd %xmm0, %zmm0    # zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
vmovdqa64 %zmm0, 0x1740(%rsp)
vmovdqa 0x600(%rsp), %xmm0
vmovdqa %xmm0, 0x1c10(%rsp)
vmovdqa 0x1c10(%rsp), %xmm0
vpmovzxbd %xmm0, %zmm0    # zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
vmovdqa64 %zmm0, 0x1700(%rsp)
jmp 0xab5e8
cmpl $0x0, 0xefc(%rsp)
jge 0xab6fc
cmpl $0x0, 0x1a40(%rsp)
je 0xab6fc
vmovdqa64 0x1840(%rsp), %zmm0
movq 0x1bd0(%rsp), %rdi
callq 0xacb40
vmovdqa64 %zmm0, 0x1740(%rsp)
vmovdqa64 0x1800(%rsp), %zmm0
movq 0x1bd0(%rsp), %rdi
callq 0xacb40
vmovdqa64 %zmm0, 0x1700(%rsp)
vmovdqa64 0x1740(%rsp), %zmm1
movl $0xff, 0x22bc(%rsp)
vpbroadcastd 0x22bc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2240(%rsp)
vmovdqa64 0x2240(%rsp), %zmm0
vmovdqa64 %zmm1, 0x1f00(%rsp)
vmovdqa64 %zmm0, 0x1ec0(%rsp)
vmovdqa64 0x1f00(%rsp), %zmm0
vmovdqa64 0x1ec0(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x1740(%rsp)
vmovdqa64 0x1700(%rsp), %zmm1
movl $0xff, 0x223c(%rsp)
vpbroadcastd 0x223c(%rsp), %zmm0
vmovdqa64 %zmm0, 0x21c0(%rsp)
vmovdqa64 0x21c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x1e80(%rsp)
vmovdqa64 %zmm0, 0x1e40(%rsp)
vmovdqa64 0x1e80(%rsp), %zmm0
vpandq 0x1e40(%rsp), %zmm0, %zmm0
vmovdqa64 %zmm0, 0x1700(%rsp)
vmovdqa64 0xe80(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
movl $0x4, %esi
movl %esi, 0x3c(%rsp)
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x5c0(%rsp)
vmovdqa64 0xe40(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x580(%rsp)
vmovdqa64 0x1900(%rsp), %zmm0
vmovdqa64 0x5c0(%rsp), %zmm1
vpcmpgtd %zmm1, %zmm0, %k0
kmovw %k0, 0x57e(%rsp)
movzwl 0x57e(%rsp), %eax
movl %eax, 0x1c3c(%rsp)
popcntl 0x1c3c(%rsp), %eax
movl %eax, 0x578(%rsp)
vmovdqa64 0x1900(%rsp), %zmm1
movl $0xffff, 0x21bc(%rsp) # imm = 0xFFFF
vpbroadcastd 0x21bc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2140(%rsp)
vmovdqa64 0x2140(%rsp), %zmm0
vmovdqa64 %zmm1, 0x1e00(%rsp)
vmovdqa64 %zmm0, 0x1dc0(%rsp)
vmovdqa64 0x1e00(%rsp), %zmm0
vmovdqa64 0x1dc0(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x500(%rsp)
vmovdqa64 0x18c0(%rsp), %zmm1
movl $0xffff, 0x213c(%rsp) # imm = 0xFFFF
vpbroadcastd 0x213c(%rsp), %zmm0
vmovdqa64 %zmm0, 0x20c0(%rsp)
vmovdqa64 0x20c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x1d80(%rsp)
vmovdqa64 %zmm0, 0x1d40(%rsp)
vmovdqa64 0x1d80(%rsp), %zmm0
vmovdqa64 0x1d40(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x4c0(%rsp)
vmovdqa64 0x18c0(%rsp), %zmm0
vmovdqa64 0x580(%rsp), %zmm1
vpcmpgtd %zmm1, %zmm0, %k0
kmovw %k0, 0x4be(%rsp)
vmovdqa64 0xe80(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
addq $0xc, %rdi
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x440(%rsp)
vmovdqa64 0xe40(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
addq $0xc, %rdi
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x400(%rsp)
movzwl 0x4be(%rsp), %eax
movl %eax, 0x1c38(%rsp)
popcntl 0x1c38(%rsp), %eax
movl %eax, 0x3fc(%rsp)
movw 0x57e(%rsp), %ax
vmovdqa64 0x500(%rsp), %zmm0
movw %ax, 0x24be(%rsp)
vmovdqa64 %zmm0, 0x2440(%rsp)
vmovdqa64 0x2440(%rsp), %zmm2
vxorps %xmm0, %xmm0, %xmm0
vmovdqa64 %zmm0, 0x3c00(%rsp)
vmovdqa64 0x3c00(%rsp), %zmm1
kmovw 0x24be(%rsp), %k1
vpcompressd %zmm2, %zmm1 {%k1}
vmovdqa64 %zmm1, 0x500(%rsp)
movw 0x4be(%rsp), %ax
vmovdqa64 0x4c0(%rsp), %zmm1
movw %ax, 0x243e(%rsp)
vmovdqa64 %zmm1, 0x23c0(%rsp)
vmovdqa64 0x23c0(%rsp), %zmm1
vmovdqa64 %zmm0, 0x3c40(%rsp)
vmovdqa64 0x3c40(%rsp), %zmm0
kmovw 0x243e(%rsp), %k1
vpcompressd %zmm1, %zmm0 {%k1}
vmovdqa64 %zmm0, 0x4c0(%rsp)
movq 0x18b8(%rsp), %rdx
movslq 0x3fc(%rsp), %rax
movq %rax, %rcx
addq %rcx, %rcx
subq %rcx, %rdx
movb %al, %cl
movl $0x1, %eax
movl %eax, %edi
shll %cl, %edi
movl %edi, %ecx
decl %ecx
vmovdqa64 0x4c0(%rsp), %zmm0
movq %rdx, 0x25b0(%rsp)
movw %cx, 0x25ae(%rsp)
vmovdqa64 %zmm0, 0x2540(%rsp)
movq 0x25b0(%rsp), %rcx
vmovdqa64 0x2540(%rsp), %zmm0
kmovw 0x25ae(%rsp), %k1
vpmovdw %zmm0, (%rcx) {%k1}
movslq 0x3fc(%rsp), %rdx
movq 0x18b8(%rsp), %rcx
addq %rdx, %rdx
subq %rdx, %rcx
movq %rcx, 0x18b8(%rsp)
movq 0x18b8(%rsp), %rdx
movslq 0x578(%rsp), %rcx
movq %rcx, %rdi
addq %rdi, %rdi
subq %rdi, %rdx
movq %rdx, 0x30(%rsp)
shll %cl, %eax
movq 0x30(%rsp), %rcx
decl %eax
vmovdqa64 0x500(%rsp), %zmm0
movq %rcx, 0x2538(%rsp)
movw %ax, 0x2536(%rsp)
vmovdqa64 %zmm0, 0x24c0(%rsp)
movq 0x2538(%rsp), %rax
vmovdqa64 0x24c0(%rsp), %zmm0
kmovw 0x2536(%rsp), %k1
vpmovdw %zmm0, (%rax) {%k1}
movslq 0x578(%rsp), %rcx
movq 0x18b8(%rsp), %rax
addq %rcx, %rcx
subq %rcx, %rax
movq %rax, 0x18b8(%rsp)
vmovdqa64 0x1900(%rsp), %zmm0
movw 0x57e(%rsp), %ax
vmovdqa64 %zmm0, 0x2740(%rsp)
movw %ax, 0x273e(%rsp)
vmovdqa64 %zmm0, 0x26c0(%rsp)
movl $0x10, 0x26bc(%rsp)
vmovdqa64 0x26c0(%rsp), %zmm0
movl 0x26bc(%rsp), %eax
kmovw 0x273e(%rsp), %k1
vmovdqa64 %zmm0, 0x2f40(%rsp)
movl %eax, 0x2f3c(%rsp)
vmovdqa64 0x2f40(%rsp), %zmm1
vmovd 0x2f3c(%rsp), %xmm2
vmovdqa64 0x2740(%rsp), %zmm0
vpsrld %xmm2, %zmm1, %zmm0 {%k1}
vmovdqa64 %zmm0, 0x1900(%rsp)
vmovdqa64 0x18c0(%rsp), %zmm0
movw 0x4be(%rsp), %ax
vmovdqa64 %zmm0, 0x2640(%rsp)
movw %ax, 0x263e(%rsp)
vmovdqa64 %zmm0, 0x25c0(%rsp)
movl $0x10, 0x25bc(%rsp)
vmovdqa64 0x25c0(%rsp), %zmm0
movl 0x25bc(%rsp), %eax
kmovw 0x263e(%rsp), %k1
vmovdqa64 %zmm0, 0x2fc0(%rsp)
movl %eax, 0x2fbc(%rsp)
vmovdqa64 0x2fc0(%rsp), %zmm1
vmovd 0x2fbc(%rsp), %xmm2
vmovdqa64 0x2640(%rsp), %zmm0
vpsrld %xmm2, %zmm1, %zmm0 {%k1}
vmovdqa64 %zmm0, 0x18c0(%rsp)
vmovdqa64 0xe80(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
addq $0x4, %rdi
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x380(%rsp)
vmovdqa64 0xe40(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
addq $0x4, %rdi
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x340(%rsp)
vmovdqa64 0x1900(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2c40(%rsp)
movl $0x20, 0x2c3c(%rsp)
vmovdqa64 0x2c40(%rsp), %zmm0
vmovd 0x2c3c(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm1
vmovdqa64 0x380(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2bc0(%rsp)
movl $0x20, 0x2bbc(%rsp)
vmovdqa64 0x2bc0(%rsp), %zmm0
vmovd 0x2bbc(%rsp), %xmm2
vpsrlq %xmm2, %zmm0, %zmm0
vmovdqa64 %zmm1, 0x2940(%rsp)
vmovdqa64 %zmm0, 0x2900(%rsp)
vmovdqa64 0x2940(%rsp), %zmm0
vmovdqa64 0x2900(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x300(%rsp)
vmovdqa64 0x18c0(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2b40(%rsp)
movl $0x20, 0x2b3c(%rsp)
vmovdqa64 0x2b40(%rsp), %zmm0
vmovd 0x2b3c(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm1
vmovdqa64 0x340(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2ac0(%rsp)
movl $0x20, 0x2abc(%rsp)
vmovdqa64 0x2ac0(%rsp), %zmm0
vmovd 0x2abc(%rsp), %xmm2
vpsrlq %xmm2, %zmm0, %zmm0
vmovdqa64 %zmm1, 0x28c0(%rsp)
vmovdqa64 %zmm0, 0x2880(%rsp)
vmovdqa64 0x28c0(%rsp), %zmm0
vmovdqa64 0x2880(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x2c0(%rsp)
vmovdqa64 0x1900(%rsp), %zmm1
vmovdqa64 0x380(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2840(%rsp)
vmovdqa64 %zmm0, 0x2800(%rsp)
vmovdqa64 0x2840(%rsp), %zmm0
vmovdqa64 0x2800(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x2a40(%rsp)
movl $0x20, 0x2a3c(%rsp)
vmovdqa64 0x2a40(%rsp), %zmm0
vmovd 0x2a3c(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x280(%rsp)
vmovdqa64 0x18c0(%rsp), %zmm1
vmovdqa64 0x340(%rsp), %zmm0
vmovdqa64 %zmm1, 0x27c0(%rsp)
vmovdqa64 %zmm0, 0x2780(%rsp)
vmovdqa64 0x27c0(%rsp), %zmm0
vmovdqa64 0x2780(%rsp), %zmm1
vpmuludq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x29c0(%rsp)
movl $0x20, 0x29bc(%rsp)
vmovdqa64 0x29c0(%rsp), %zmm0
vmovd 0x29bc(%rsp), %xmm1
vpsrlq %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x240(%rsp)
movabsq $-0x100000000, %rax     # imm = 0xFFFFFFFF00000000
movq %rax, 0x2df8(%rsp)
vpbroadcastq 0x2df8(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2d80(%rsp)
vmovdqa64 0x2d80(%rsp), %zmm0
vmovdqa64 %zmm0, 0x200(%rsp)
vmovdqa64 0x300(%rsp), %zmm1
vmovdqa64 0x200(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2d40(%rsp)
vmovdqa64 %zmm0, 0x2d00(%rsp)
vmovdqa64 0x2d40(%rsp), %zmm0
vmovdqa64 0x2d00(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x300(%rsp)
vmovdqa64 0x2c0(%rsp), %zmm1
vmovdqa64 0x200(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2cc0(%rsp)
vmovdqa64 %zmm0, 0x2c80(%rsp)
vmovdqa64 0x2cc0(%rsp), %zmm0
vmovdqa64 0x2c80(%rsp), %zmm1
vpandq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x2c0(%rsp)
vmovdqa64 0x280(%rsp), %zmm1
vmovdqa64 0x300(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2ec0(%rsp)
vmovdqa64 %zmm0, 0x2e80(%rsp)
vmovdqa64 0x2ec0(%rsp), %zmm0
vmovdqa64 0x2e80(%rsp), %zmm1
vporq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x380(%rsp)
vmovdqa64 0x240(%rsp), %zmm1
vmovdqa64 0x2c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x2e40(%rsp)
vmovdqa64 %zmm0, 0x2e00(%rsp)
vmovdqa64 0x2e40(%rsp), %zmm0
vmovdqa64 0x2e00(%rsp), %zmm1
vporq %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x340(%rsp)
vmovdqa64 0xe80(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
addq $0x8, %rdi
callq 0xa9240
movl 0x3c(%rsp), %esi
vmovdqa64 %zmm0, 0x1c0(%rsp)
vmovdqa64 0xe40(%rsp), %zmm0
movq 0x1af8(%rsp), %rdi
addq $0x8, %rdi
callq 0xa9240
vmovdqa64 %zmm0, 0x180(%rsp)
vmovdqa64 0x440(%rsp), %zmm0
vmovdqa64 %zmm0, 0x30c0(%rsp)
movl $0x10, 0x30bc(%rsp)
vmovdqa64 0x30c0(%rsp), %zmm0
vmovd 0x30bc(%rsp), %xmm1
vpsrld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x140(%rsp)
vmovdqa64 0x400(%rsp), %zmm0
vmovdqa64 %zmm0, 0x3040(%rsp)
movl $0x10, 0x303c(%rsp)
vmovdqa64 0x3040(%rsp), %zmm0
vmovd 0x303c(%rsp), %xmm1
vpsrld %xmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x100(%rsp)
vmovdqa64 0x140(%rsp), %zmm1
movl $0x20, 0x20bc(%rsp)
vpbroadcastd 0x20bc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x2040(%rsp)
vmovdqa64 0x2040(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3a80(%rsp)
vmovdqa64 %zmm0, 0x3a40(%rsp)
vmovdqa64 0x3a80(%rsp), %zmm0
vmovdqa64 0x3a40(%rsp), %zmm1
vpsubd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x140(%rsp)
vmovdqa64 0x100(%rsp), %zmm1
movl $0x20, 0x203c(%rsp)
vpbroadcastd 0x203c(%rsp), %zmm0
vmovdqa64 %zmm0, 0x1fc0(%rsp)
vmovdqa64 0x1fc0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3a00(%rsp)
vmovdqa64 %zmm0, 0x39c0(%rsp)
vmovdqa64 0x3a00(%rsp), %zmm0
vmovdqa64 0x39c0(%rsp), %zmm1
vpsubd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x100(%rsp)
vmovdqa64 0x380(%rsp), %zmm1
vmovdqa64 0x140(%rsp), %zmm0
vmovdqa64 %zmm1, 0x31c0(%rsp)
vmovdqa64 %zmm0, 0x3180(%rsp)
vmovdqa64 0x31c0(%rsp), %zmm0
vmovdqa64 0x3180(%rsp), %zmm1
vpsrlvd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xc0(%rsp)
vmovdqa64 0x340(%rsp), %zmm1
vmovdqa64 0x100(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3140(%rsp)
vmovdqa64 %zmm0, 0x3100(%rsp)
vmovdqa64 0x3140(%rsp), %zmm0
vmovdqa64 0x3100(%rsp), %zmm1
vpsrlvd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x80(%rsp)
movl $0xffff, 0x1fbc(%rsp) # imm = 0xFFFF
vpbroadcastd 0x1fbc(%rsp), %zmm0
vmovdqa64 %zmm0, 0x1f40(%rsp)
vmovdqa64 0x1f40(%rsp), %zmm0
vmovdqa64 %zmm0, 0x40(%rsp)
vmovdqa64 0xc0(%rsp), %zmm1
vmovdqa64 0x440(%rsp), %zmm2
vmovdqa64 0x40(%rsp), %zmm0
vmovdqa64 %zmm2, 0x1d00(%rsp)
vmovdqa64 %zmm0, 0x1cc0(%rsp)
vmovdqa64 0x1d00(%rsp), %zmm0
vpandq 0x1cc0(%rsp), %zmm0, %zmm0
vmovdqa64 %zmm1, 0x32c0(%rsp)
vmovdqa64 %zmm0, 0x3280(%rsp)
vmovdqa64 0x32c0(%rsp), %zmm0
vmovdqa64 0x3280(%rsp), %zmm1
vpmulld %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xc0(%rsp)
vmovdqa64 0x80(%rsp), %zmm1
vmovdqa64 0x400(%rsp), %zmm2
vmovdqa64 0x40(%rsp), %zmm0
vmovdqa64 %zmm2, 0x1c80(%rsp)
vmovdqa64 %zmm0, 0x1c40(%rsp)
vmovdqa64 0x1c80(%rsp), %zmm0
vpandq 0x1c40(%rsp), %zmm0, %zmm0
vmovdqa64 %zmm1, 0x3240(%rsp)
vmovdqa64 %zmm0, 0x3200(%rsp)
vmovdqa64 0x3240(%rsp), %zmm0
vmovdqa64 0x3200(%rsp), %zmm1
vpmulld %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x80(%rsp)
vmovdqa64 0xc0(%rsp), %zmm1
vmovdqa64 0x1c0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x34c0(%rsp)
vmovdqa64 %zmm0, 0x3480(%rsp)
vmovdqa64 0x34c0(%rsp), %zmm0
vmovdqa64 0x3480(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0xc0(%rsp)
vmovdqa64 0x1900(%rsp), %zmm1
vmovdqa64 0xc0(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3440(%rsp)
vmovdqa64 %zmm0, 0x3400(%rsp)
vmovdqa64 0x3440(%rsp), %zmm0
vmovdqa64 0x3400(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x1900(%rsp)
vmovdqa64 0x80(%rsp), %zmm1
vmovdqa64 0x180(%rsp), %zmm0
vmovdqa64 %zmm1, 0x33c0(%rsp)
vmovdqa64 %zmm0, 0x3380(%rsp)
vmovdqa64 0x33c0(%rsp), %zmm0
vmovdqa64 0x3380(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x80(%rsp)
vmovdqa64 0x18c0(%rsp), %zmm1
vmovdqa64 0x80(%rsp), %zmm0
vmovdqa64 %zmm1, 0x3340(%rsp)
vmovdqa64 %zmm0, 0x3300(%rsp)
vmovdqa64 0x3340(%rsp), %zmm0
vmovdqa64 0x3300(%rsp), %zmm1
vpaddd %zmm1, %zmm0, %zmm0
vmovdqa64 %zmm0, 0x18c0(%rsp)
movl 0x1a40(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x1a40(%rsp)
jmp 0xab0c6
leaq 0x1b00(%rsp), %rax
vmovdqa64 0x1900(%rsp), %zmm0
movq %rax, 0x37f0(%rsp)
vmovdqa64 %zmm0, 0x3780(%rsp)
vmovdqa64 0x3780(%rsp), %zmm0
movq 0x37f0(%rsp), %rax
vmovdqa64 %zmm0, (%rax)
leaq 0x1b00(%rsp), %rax
addq $0x40, %rax
vmovdqa64 0x18c0(%rsp), %zmm0
movq %rax, 0x3778(%rsp)
vmovdqa64 %zmm0, 0x3700(%rsp)
vmovdqa64 0x3700(%rsp), %zmm0
movq 0x3778(%rsp), %rax
vmovdqa64 %zmm0, (%rax)
leaq 0x1980(%rsp), %rax
vmovdqa64 0x17c0(%rsp), %zmm0
movq %rax, 0x36f8(%rsp)
vmovdqa64 %zmm0, 0x3680(%rsp)
vmovdqa64 0x3680(%rsp), %zmm0
movq 0x36f8(%rsp), %rax
vmovdqa64 %zmm0, (%rax)
leaq 0x1980(%rsp), %rax
addq $0x40, %rax
vmovdqa64 0x1780(%rsp), %zmm0
movq %rax, 0x3678(%rsp)
vmovdqa64 %zmm0, 0x3600(%rsp)
vmovdqa64 0x3600(%rsp), %zmm0
movq 0x3678(%rsp), %rax
vmovdqa64 %zmm0, (%rax)
movq 0x18b8(%rsp), %rax
movq %rax, 0x1ae8(%rsp)
movl $0x1f, 0x1b94(%rsp)
cmpl $0x0, 0x1b94(%rsp)
jl 0xac5b0
movslq 0x1b94(%rsp), %rax
leaq 0x1b00(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
movq 0x1af8(%rsp), %rdx
movslq 0x1b94(%rsp), %rax
movl 0x1980(%rsp,%rax,4), %eax
shlq $0x4, %rax
addq %rax, %rdx
leaq 0x1ae8(%rsp), %rsi
vzeroupper
callq 0xa9180
movl 0x1b94(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x1b94(%rsp)
jmp 0xac54e
movl $0x1f, 0x1b94(%rsp)
cmpl $0x0, 0x1b94(%rsp)
jl 0xac5ff
movslq 0x1b94(%rsp), %rax
leaq 0x1b00(%rsp), %rdi
shlq $0x2, %rax
addq %rax, %rdi
leaq 0x1ae8(%rsp), %rsi
vzeroupper
callq 0xa9760
movl 0x1b94(%rsp), %eax
addl $-0x1, %eax
movl %eax, 0x1b94(%rsp)
jmp 0xac5bb
movq 0x1ba8(%rsp), %rax
movq 0x1ae8(%rsp), %rcx
subq %rcx, %rax
movl 0x1b9c(%rsp), %ecx
addq %rcx, %rax
movl %eax, %ecx
movq 0x1bb8(%rsp), %rax
movl %ecx, (%rax)
movq 0x1bc0(%rsp), %rdi
movl 0x1b9c(%rsp), %eax
addq %rax, %rdi
movq 0x1ae8(%rsp), %rsi
movq 0x1ba8(%rsp), %rdx
movq 0x1ae8(%rsp), %rax
subq %rax, %rdx
vzeroupper
callq 0x4810
movq 0x1af8(%rsp), %rdi
callq 0xce8f0
movq 0x1bc0(%rsp), %rax
movq %rax, 0x1bd8(%rsp)
movq 0x1bd8(%rsp), %rax
movq %rbp, %rsp
popq %rbp
retq
nopw (%rax,%rax)