// File: NishadSaraf[P]Championship-Simulator/src/ooo_cpu.cc
// Function: O3_CPU::execute_store(unsigned int, unsigned int, unsigned int)
void O3_CPU::execute_store(uint32_t rob_index, uint32_t sq_index, uint32_t data_index)
{
    SQ.entry[sq_index].fetched = COMPLETED;
    SQ.entry[sq_index].event_cycle = current_core_cycle[cpu];

    ROB.entry[rob_index].num_mem_ops--;
    ROB.entry[rob_index].event_cycle = current_core_cycle[cpu];
    if (ROB.entry[rob_index].num_mem_ops < 0) {
        cerr << "instr_id: " << ROB.entry[rob_index].instr_id << endl;
        assert(0);
    }
    if (ROB.entry[rob_index].num_mem_ops == 0)
        inflight_mem_executions++;

    DP (if (warmup_complete[cpu]) {
    cout << "[SQ1] " << __func__ << " instr_id: " << SQ.entry[sq_index].instr_id << hex;
    cout << " full_address: " << SQ.entry[sq_index].physical_address << dec << " remain_mem_ops: " << ROB.entry[rob_index].num_mem_ops;
    cout << " event_cycle: " << SQ.entry[sq_index].event_cycle << endl; });

    // resolve RAW dependency after DTLB access
    // check if this store has dependent loads
    if (ROB.entry[rob_index].is_producer) {

        for (uint32_t dependent=0; dependent<ROB_SIZE; dependent++) {
            if (ROB.entry[rob_index].memory_instrs_depend_on_me[dependent]) {

                // check if dependent loads are already added in the load queue
                for (uint32_t j=0; j<NUM_INSTR_SOURCES; j++) { // which one is dependent?
                    if (ROB.entry[dependent].source_memory[j] && ROB.entry[dependent].source_added[j]) {
                        if (ROB.entry[dependent].source_memory[j] == SQ.entry[sq_index].virtual_address) { // this is required since a single instruction can issue multiple loads

                            // now we can resolve RAW dependency
                            uint32_t lq_index = ROB.entry[dependent].lq_index[j];
#ifdef SANITY_CHECK
                            if (lq_index >= LQ.SIZE)
                                assert(0);
                            if (LQ.entry[lq_index].producer_id != SQ.entry[sq_index].instr_id) {
                                cerr << "[SQ2] " << __func__ << " lq_index: " << lq_index << " producer_id: " << LQ.entry[lq_index].producer_id;
                                cerr << " does not match to the store instr_id: " << SQ.entry[sq_index].instr_id << endl;
                                assert(0);
                            }
#endif

                            // update correspodning LQ entry
                            LQ.entry[lq_index].physical_address = (SQ.entry[sq_index].physical_address & ~(uint64_t) ((1 << LOG2_BLOCK_SIZE) - 1)) | (LQ.entry[lq_index].virtual_address & ((1 << LOG2_BLOCK_SIZE) - 1));
                            LQ.entry[lq_index].translated = COMPLETED;
                            LQ.entry[lq_index].fetched = COMPLETED;
                            LQ.entry[lq_index].event_cycle = current_core_cycle[cpu];

                            uint32_t fwr_rob_index = LQ.entry[lq_index].rob_index;
                            ROB.entry[fwr_rob_index].num_mem_ops--;
                            ROB.entry[fwr_rob_index].event_cycle = current_core_cycle[cpu];
#ifdef SANITY_CHECK
                            if (ROB.entry[fwr_rob_index].num_mem_ops < 0) {
                                cerr << "instr_id: " << ROB.entry[fwr_rob_index].instr_id << endl;
                                assert(0);
                            }
#endif
                            if (ROB.entry[fwr_rob_index].num_mem_ops == 0)
                                inflight_mem_executions++;

                            DP(if(warmup_complete[cpu]) {
                            cout << "[LQ3] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << hex;
                            cout << " full_addr: " << LQ.entry[lq_index].physical_address << dec << " is forwarded by store instr_id: ";
                            cout << SQ.entry[sq_index].instr_id << " remain_num_ops: " << ROB.entry[fwr_rob_index].num_mem_ops << " cycle: " << current_core_cycle[cpu] << endl; });

                            release_load_queue(lq_index);

                            // clear dependency bit
                            if (j == (NUM_INSTR_SOURCES-1))
                                ROB.entry[rob_index].memory_instrs_depend_on_me[dependent] = 0;
                        }
                    }
                }
            }
        }
    }
}

// Assembly:
subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movl %esi, 0x2c(%rsp)
movl %edx, 0x28(%rsp)
movl %ecx, 0x24(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0xa28(%rax), %rcx
movl 0x28(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movb $0x2, 0x3d(%rcx)
movl (%rax), %ecx
movl %ecx, %edx
leaq 0x76c3d(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movq 0xa28(%rax), %rcx
movl 0x28(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x28(%rcx)
movq 0x9b8(%rax), %rcx
movl 0x2c(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movl 0x70(%rcx), %edx
addl $-0x1, %edx
movl %edx, 0x70(%rcx)
movl (%rax), %ecx
movl %ecx, %edx
leaq 0x76bf7(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movq 0x9b8(%rax), %rcx
movl 0x2c(%rsp), %esi
imulq $0x758, %rsi, %rsi      # imm = 0x758
addq %rsi, %rcx
movq %rdx, 0x40(%rcx)
movq 0x9b8(%rax), %rax
movl 0x2c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpl $0x0, 0x70(%rax)
jge 0x19367
movq 0xfce8(%rip), %rdi      # 0x28ff0
leaq 0xab11(%rip), %rsi      # 0x23e20
callq 0x3220
movq %rax, %rdi
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x2c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movq (%rax), %rsi
callq 0x3080
movq %rax, %rdi
movq 0xfc75(%rip), %rsi      # 0x28fb8
callq 0x3250
leaq 0x9cb5(%rip), %rdi      # 0x23004
leaq 0xa85f(%rip), %rsi      # 0x23bb5
movl $0x4fc, %edx            # imm = 0x4FC
leaq 0xaa44(%rip), %rcx      # 0x23da6
callq 0x3160
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x2c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpl $0x0, 0x70(%rax)
jne 0x1939b
movq 0x8(%rsp), %rax
movl 0x924(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x924(%rax)
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x2c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpb $0x0, 0x56(%rax)
je 0x1984a
movl $0x0, 0x20(%rsp)
cmpl $0x100, 0x20(%rsp)      # imm = 0x100
jae 0x19848
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x2c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movl 0x20(%rsp), %ecx
cmpb $0x0, 0x628(%rax,%rcx)
je 0x19836
movl $0x0, 0x1c(%rsp)
cmpl $0x4, 0x1c(%rsp)
jae 0x19834
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x20(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
cmpq $0x0, 0x5c8(%rax,%rcx,8)
je 0x19822
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x20(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movl 0x1c(%rsp), %ecx
cmpb $0x0, 0x4e(%rax,%rcx)
je 0x19822
movq 0x8(%rsp), %rcx
movq 0x9b8(%rcx), %rax
movl 0x20(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rax
movl 0x1c(%rsp), %edx
movq 0x5c8(%rax,%rdx,8), %rax
movq 0xa28(%rcx), %rcx
movl 0x28(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
cmpq 0x10(%rcx), %rax
jne 0x19820
movq 0x8(%rsp), %rcx
movq 0x9b8(%rcx), %rax
movl 0x20(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rax
movl 0x1c(%rsp), %edx
movl 0x728(%rax,%rdx,4), %eax
movl %eax, 0x18(%rsp)
movl 0x18(%rsp), %eax
cmpl 0x9e0(%rcx), %eax
jb 0x19503
leaq 0x9b19(%rip), %rdi      # 0x23004
leaq 0xa6c3(%rip), %rsi      # 0x23bb5
movl $0x516, %edx            # imm = 0x516
leaq 0xa8a8(%rip), %rcx      # 0x23da6
callq 0x3160
movq 0x8(%rsp), %rcx
movq 0x9f0(%rcx), %rax
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movq 0x8(%rax), %rax
movq 0xa28(%rcx), %rcx
movl 0x28(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
cmpq (%rcx), %rax
je 0x19617
movq 0xfaaa(%rip), %rdi      # 0x28ff0
leaq 0xa892(%rip), %rsi      # 0x23ddf
callq 0x3220
movq %rax, %rdi
leaq 0xa88a(%rip), %rsi      # 0x23de6
callq 0x3220
movq %rax, %rdi
leaq 0xa0bd(%rip), %rsi      # 0x23628
callq 0x3220
movq %rax, %rdi
movl 0x18(%rsp), %esi
callq 0x32c0
movq %rax, %rdi
leaq 0xa86e(%rip), %rsi      # 0x23df4
callq 0x3220
movq %rax, %rdi
movq 0x8(%rsp), %rax
movq 0x9f0(%rax), %rax
movl 0x18(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movq 0x8(%rax), %rsi
callq 0x3080
movq 0xfa38(%rip), %rdi      # 0x28ff0
leaq 0xa844(%rip), %rsi      # 0x23e03
callq 0x3220
movq %rax, %rdi
movq 0x8(%rsp), %rax
movq 0xa28(%rax), %rax
movl 0x28(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movq (%rax), %rsi
callq 0x3080
movq %rax, %rdi
movq 0xf9c5(%rip), %rsi      # 0x28fb8
callq 0x3250
leaq 0x9a05(%rip), %rdi      # 0x23004
leaq 0xa5af(%rip), %rsi      # 0x23bb5
movl $0x51a, %edx            # imm = 0x51A
leaq 0xa794(%rip), %rcx      # 0x23da6
callq 0x3160
movq 0x8(%rsp), %rax
movq 0xa28(%rax), %rcx
movl 0x28(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movq 0x18(%rcx), %rdx
andq $-0x40, %rdx
movq 0x9f0(%rax), %rcx
movl 0x18(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq 0x10(%rcx), %rcx
andq $0x3f, %rcx
orq %rcx, %rdx
movq 0x9f0(%rax), %rcx
movl 0x18(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x18(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movb $0x2, 0x3c(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movb $0x2, 0x3d(%rcx)
movl (%rax), %ecx
movl %ecx, %edx
leaq 0x76811(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movq 0x9f0(%rax), %rcx
movl 0x18(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movq %rdx, 0x28(%rcx)
movq 0x9f0(%rax), %rcx
movl 0x18(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x30(%rcx), %ecx
movl %ecx, 0x14(%rsp)
movq 0x9b8(%rax), %rcx
movl 0x14(%rsp), %edx
imulq $0x758, %rdx, %rdx      # imm = 0x758
addq %rdx, %rcx
movl 0x70(%rcx), %edx
addl $-0x1, %edx
movl %edx, 0x70(%rcx)
movl (%rax), %ecx
movl %ecx, %edx
leaq 0x767af(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
movq 0x9b8(%rax), %rcx
movl 0x14(%rsp), %esi
imulq $0x758, %rsi, %rsi      # imm = 0x758
addq %rsi, %rcx
movq %rdx, 0x40(%rcx)
movq 0x9b8(%rax), %rax
movl 0x14(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpl $0x0, 0x70(%rax)
jge 0x197af
movq 0xf8a0(%rip), %rdi      # 0x28ff0
leaq 0xa6c9(%rip), %rsi      # 0x23e20
callq 0x3220
movq %rax, %rdi
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x14(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movq (%rax), %rsi
callq 0x3080
movq %rax, %rdi
movq 0xf82d(%rip), %rsi      # 0x28fb8
callq 0x3250
leaq 0x986d(%rip), %rdi      # 0x23004
leaq 0xa417(%rip), %rsi      # 0x23bb5
movl $0x52a, %edx            # imm = 0x52A
leaq 0xa5fc(%rip), %rcx      # 0x23da6
callq 0x3160
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x14(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
cmpl $0x0, 0x70(%rax)
jne 0x197e3
movq 0x8(%rsp), %rax
movl 0x924(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x924(%rax)
movq 0x8(%rsp), %rdi
movl 0x18(%rsp), %esi
callq 0x191c0
cmpl $0x3, 0x1c(%rsp)
jne 0x1981e
movq 0x8(%rsp), %rax
movq 0x9b8(%rax), %rax
movl 0x2c(%rsp), %ecx
imulq $0x758, %rcx, %rcx      # imm = 0x758
addq %rcx, %rax
movl 0x20(%rsp), %ecx
movb $0x0, 0x628(%rax,%rcx)
jmp 0x19820
jmp 0x19822
jmp 0x19824
movl 0x1c(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x1c(%rsp)
jmp 0x19409
jmp 0x19836
jmp 0x19838
movl 0x20(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x20(%rsp)
jmp 0x193c7
jmp 0x1984a
addq $0x38, %rsp
retq
nop