// File: NishadSaraf[P]Championship-Simulator/src/dram_controller.cc
// Function: MEMORY_CONTROLLER::schedule(PACKET_QUEUE*)
void MEMORY_CONTROLLER::schedule(PACKET_QUEUE *queue)
{
    uint64_t read_addr;
    uint32_t read_channel, read_rank, read_bank, read_row;
    uint8_t  row_buffer_hit = 0;

    int oldest_index = -1;
    uint64_t oldest_cycle = UINT64_MAX;

    // first, search for the oldest open row hit
    for (uint32_t i=0; i<queue->SIZE; i++) {

        // already scheduled
        if (queue->entry[i].scheduled) 
            continue;

        // empty entry
        read_addr = queue->entry[i].address;
        if (read_addr == 0) 
            continue;

        read_channel = dram_get_channel(read_addr);
        read_rank = dram_get_rank(read_addr);
        read_bank = dram_get_bank(read_addr);

        // bank is busy
        if (bank_request[read_channel][read_rank][read_bank].working) { // should we check this or not? how do we know if bank is busy or not for all requests in the queue?

            //DP ( if (warmup_complete[0]) {
            //cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " bank is busy";
            //cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            //cout << " write: " << +bank_request[read_channel][read_rank][read_bank].is_write << " read: " << +bank_request[read_channel][read_rank][read_bank].is_read << hex;
            //cout << " address: " << queue->entry[i].address << dec << " channel: " << read_channel << " rank: " << read_rank << " bank: " << read_bank << endl; });

            continue;
        }

        read_row = dram_get_row(read_addr);
        //read_column = dram_get_column(read_addr);

        // check open row
        if (bank_request[read_channel][read_rank][read_bank].open_row != read_row) {

            /*
            DP ( if (warmup_complete[0]) {
            cout << queue->NAME << " " << __func__ << " instr_id: " << queue->entry[i].instr_id << " row is inactive";
            cout << " swrites: " << scheduled_writes << " sreads: " << scheduled_reads;
            cout << " write: " << +bank_request[read_channel][read_rank][read_bank].is_write << " read: " << +bank_request[read_channel][read_rank][read_bank].is_read << hex;
            cout << " address: " << queue->entry[i].address << dec << " channel: " << read_channel << " rank: " << read_rank << " bank: " << read_bank << endl; });
            */

            continue;
        }

        // select the oldest entry
        if (queue->entry[i].event_cycle < oldest_cycle) {
            oldest_cycle = queue->entry[i].event_cycle;
            oldest_index = i;
            row_buffer_hit = 1;
        }	  
    }

    if (oldest_index == -1) { // no matching open_row (row buffer miss)

        oldest_cycle = UINT64_MAX;
        for (uint32_t i=0; i<queue->SIZE; i++) {

            // already scheduled
            if (queue->entry[i].scheduled)
                continue;

            // empty entry
            read_addr = queue->entry[i].address;
            if (read_addr == 0) 
                continue;

            // bank is busy
            read_channel = dram_get_channel(read_addr);
            read_rank = dram_get_rank(read_addr);
            read_bank = dram_get_bank(read_addr);
            if (bank_request[read_channel][read_rank][read_bank].working) 
                continue;

            //read_row = dram_get_row(read_addr);
            //read_column = dram_get_column(read_addr);

            // select the oldest entry
            if (queue->entry[i].event_cycle < oldest_cycle) {
                oldest_cycle = queue->entry[i].event_cycle;
                oldest_index = i;
            }
        }
    }

    // at this point, the scheduler knows which bank to access and if the request is a row buffer hit or miss
    if (oldest_index != -1) { // scheduler might not find anything if all requests are already scheduled or all banks are busy

        uint64_t LATENCY = 0;
        if (row_buffer_hit)  
            LATENCY = tCAS;
        else 
            LATENCY = tRP + tRCD + tCAS;

        uint64_t op_addr = queue->entry[oldest_index].address;
        uint32_t op_cpu = queue->entry[oldest_index].cpu,
                 op_channel = dram_get_channel(op_addr), 
                 op_rank = dram_get_rank(op_addr), 
                 op_bank = dram_get_bank(op_addr), 
                 op_row = dram_get_row(op_addr);
#ifdef DEBUG_PRINT
        uint32_t op_column = dram_get_column(op_addr);
#endif

        // this bank is now busy
        bank_request[op_channel][op_rank][op_bank].working = 1;
        bank_request[op_channel][op_rank][op_bank].working_type = queue->entry[oldest_index].type;
        bank_request[op_channel][op_rank][op_bank].cycle_available = current_core_cycle[op_cpu] + LATENCY;

        bank_request[op_channel][op_rank][op_bank].request_index = oldest_index;
        bank_request[op_channel][op_rank][op_bank].row_buffer_hit = row_buffer_hit;
        if (queue->is_WQ) {
            bank_request[op_channel][op_rank][op_bank].is_write = 1;
            bank_request[op_channel][op_rank][op_bank].is_read = 0;
            scheduled_writes++;
        }
        else {
            bank_request[op_channel][op_rank][op_bank].is_write = 0;
            bank_request[op_channel][op_rank][op_bank].is_read = 1;
            scheduled_reads++;
        }

        // update open row
        bank_request[op_channel][op_rank][op_bank].open_row = op_row;

        queue->entry[oldest_index].scheduled = 1;
        queue->entry[oldest_index].event_cycle = current_core_cycle[op_cpu] + LATENCY;

        update_schedule_cycle(queue);
        update_process_cycle(queue);

        DP (if (warmup_complete[op_cpu]) {
        cout << "[" << queue->NAME << "] " <<  __func__ << " instr_id: " << queue->entry[oldest_index].instr_id;
        cout << " row buffer: " << (row_buffer_hit ? (int)bank_request[op_channel][op_rank][op_bank].open_row : -1) << hex;
        cout << " address: " << queue->entry[oldest_index].address << " full_addr: " << queue->entry[oldest_index].full_addr << dec;
        cout << " index: " << oldest_index << " occupancy: " << queue->occupancy;
        cout << " ch: " << op_channel << " rank: " << op_rank << " bank: " << op_bank; // wrong from here
        cout << " row: " << op_row << " col: " << op_column;
        cout << " current: " << current_core_cycle[op_cpu] << " event: " << queue->entry[oldest_index].event_cycle << endl; });
    }
}

// Assembly:
subq $0x78, %rsp
movq %rdi, 0x70(%rsp)
movq %rsi, 0x68(%rsp)
movq 0x70(%rsp), %rax
movq %rax, 0x8(%rsp)
movb $0x0, 0x4f(%rsp)
movl $0xffffffff, 0x48(%rsp) # imm = 0xFFFFFFFF
movq $-0x1, 0x40(%rsp)
movl $0x0, 0x3c(%rsp)
movl 0x3c(%rsp), %eax
movq 0x68(%rsp), %rcx
cmpl 0x20(%rcx), %eax
jae 0x13c37
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
cmpb $0x0, 0x2(%rax)
je 0x13acd
jmp 0x13c27
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x60(%rsp)
cmpq $0x0, 0x60(%rsp)
jne 0x13b00
jmp 0x13c27
movq 0x8(%rsp), %rdi
movq 0x60(%rsp), %rsi
callq 0x13490
movq 0x8(%rsp), %rdi
movl %eax, 0x5c(%rsp)
movq 0x60(%rsp), %rsi
callq 0x134a0
movq 0x8(%rsp), %rdi
movl %eax, 0x58(%rsp)
movq 0x60(%rsp), %rsi
callq 0x134d0
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x54(%rsp)
addq $0x7858, %rax           # imm = 0x7858
movl 0x5c(%rsp), %ecx
imulq $0xa00, %rcx, %rcx      # imm = 0xA00
addq %rcx, %rax
movl 0x58(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movl 0x54(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
cmpb $0x0, 0x1c(%rax)
je 0x13b78
jmp 0x13c27
movq 0x8(%rsp), %rdi
movq 0x60(%rsp), %rsi
callq 0x13500
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x50(%rsp)
addq $0x7858, %rax           # imm = 0x7858
movl 0x5c(%rsp), %ecx
imulq $0xa00, %rcx, %rcx      # imm = 0xA00
addq %rcx, %rax
movl 0x58(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movl 0x54(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
movl 0x18(%rax), %eax
cmpl 0x50(%rsp), %eax
je 0x13bca
jmp 0x13c27
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
cmpq 0x40(%rsp), %rax
jae 0x13c25
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x3c(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
movq %rax, 0x40(%rsp)
movl 0x3c(%rsp), %eax
movl %eax, 0x48(%rsp)
movb $0x1, 0x4f(%rsp)
jmp 0x13c27
movl 0x3c(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x3c(%rsp)
jmp 0x13a96
cmpl $-0x1, 0x48(%rsp)
jne 0x13d9c
movq $-0x1, 0x40(%rsp)
movl $0x0, 0x38(%rsp)
movl 0x38(%rsp), %eax
movq 0x68(%rsp), %rcx
cmpl 0x20(%rcx), %eax
jae 0x13d9a
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
cmpb $0x0, 0x2(%rax)
je 0x13c8a
jmp 0x13d8a
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x60(%rsp)
cmpq $0x0, 0x60(%rsp)
jne 0x13cbd
jmp 0x13d8a
movq 0x8(%rsp), %rdi
movq 0x60(%rsp), %rsi
callq 0x13490
movq 0x8(%rsp), %rdi
movl %eax, 0x5c(%rsp)
movq 0x60(%rsp), %rsi
callq 0x134a0
movq 0x8(%rsp), %rdi
movl %eax, 0x58(%rsp)
movq 0x60(%rsp), %rsi
callq 0x134d0
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x54(%rsp)
addq $0x7858, %rax           # imm = 0x7858
movl 0x5c(%rsp), %ecx
imulq $0xa00, %rcx, %rcx      # imm = 0xA00
addq %rcx, %rax
movl 0x58(%rsp), %ecx
imulq $0x140, %rcx, %rcx      # imm = 0x140
addq %rcx, %rax
movl 0x54(%rsp), %ecx
imulq $0x28, %rcx, %rcx
addq %rcx, %rax
cmpb $0x0, 0x1c(%rax)
je 0x13d32
jmp 0x13d8a
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
cmpq 0x40(%rsp), %rax
jae 0x13d88
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movl 0x38(%rsp), %ecx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x378(%rax), %rax
movq %rax, 0x40(%rsp)
movl 0x38(%rsp), %eax
movl %eax, 0x48(%rsp)
jmp 0x13d8a
movl 0x38(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x38(%rsp)
jmp 0x13c53
jmp 0x13d9c
cmpl $-0x1, 0x48(%rsp)
je 0x14175
movq $0x0, 0x30(%rsp)
cmpb $0x0, 0x4f(%rsp)
je 0x13dc4
movl 0x1745f(%rip), %eax     # 0x2b21c
movq %rax, 0x30(%rsp)
jmp 0x13ddd
movl 0x1744a(%rip), %eax     # 0x2b214
addl 0x17448(%rip), %eax     # 0x2b218
addl 0x17446(%rip), %eax     # 0x2b21c
movl %eax, %eax
movq %rax, 0x30(%rsp)
movq 0x8(%rsp), %rdi
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movq 0x340(%rax), %rax
movq %rax, 0x28(%rsp)
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movl 0x330(%rax), %eax
movl %eax, 0x24(%rsp)
movq 0x28(%rsp), %rsi
callq 0x13490
movq 0x8(%rsp), %rdi
movl %eax, 0x20(%rsp)
movq 0x28(%rsp), %rsi
callq 0x134a0
movq 0x8(%rsp), %rdi
movl %eax, 0x1c(%rsp)
movq 0x28(%rsp), %rsi
callq 0x134d0
movq 0x8(%rsp), %rdi
movl %eax, 0x18(%rsp)
movq 0x28(%rsp), %rsi
callq 0x13500
movl %eax, %ecx
movq 0x8(%rsp), %rax
movl %ecx, 0x14(%rsp)
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x1, 0x1c(%rcx)
movq 0x68(%rsp), %rcx
movq 0x98(%rcx), %rcx
movslq 0x48(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rcx
movb 0x32f(%rcx), %dl
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %esi
imulq $0xa00, %rsi, %rsi      # imm = 0xA00
addq %rsi, %rcx
movl 0x1c(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movl 0x18(%rsp), %esi
imulq $0x28, %rsi, %rsi
addq %rsi, %rcx
movb %dl, 0x1d(%rcx)
movl 0x24(%rsp), %ecx
movl %ecx, %edx
leaq 0x7bfad(%rip), %rcx     # 0x8fec0
movq (%rcx,%rdx,8), %rdx
addq 0x30(%rsp), %rdx
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %esi
imulq $0xa00, %rsi, %rsi      # imm = 0xA00
addq %rsi, %rcx
movl 0x1c(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movl 0x18(%rsp), %esi
imulq $0x28, %rsi, %rsi
addq %rsi, %rcx
movq %rdx, (%rcx)
movl 0x48(%rsp), %edx
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %esi
imulq $0xa00, %rsi, %rsi      # imm = 0xA00
addq %rsi, %rcx
movl 0x1c(%rsp), %esi
imulq $0x140, %rsi, %rsi      # imm = 0x140
addq %rsi, %rcx
movl 0x18(%rsp), %esi
imulq $0x28, %rsi, %rsi
addq %rsi, %rcx
movl %edx, 0x24(%rcx)
movb 0x4f(%rsp), %cl
addq $0x7858, %rax           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rax
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rax
movb %cl, 0x1e(%rax)
movq 0x68(%rsp), %rax
cmpb $0x0, 0x25(%rax)
je 0x1404b
movq 0x8(%rsp), %rax
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x1, 0x20(%rcx)
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x0, 0x21(%rcx)
movl 0x784c(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x784c(%rax)
jmp 0x140c9
movq 0x8(%rsp), %rax
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x0, 0x20(%rcx)
movq %rax, %rcx
addq $0x7858, %rcx           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rcx
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rcx
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rcx
movb $0x1, 0x21(%rcx)
movl 0x7848(%rax), %ecx
addl $0x1, %ecx
movl %ecx, 0x7848(%rax)
movq 0x8(%rsp), %rdi
movl 0x14(%rsp), %ecx
movq %rdi, %rax
addq $0x7858, %rax           # imm = 0x7858
movl 0x20(%rsp), %edx
imulq $0xa00, %rdx, %rdx      # imm = 0xA00
addq %rdx, %rax
movl 0x1c(%rsp), %edx
imulq $0x140, %rdx, %rdx      # imm = 0x140
addq %rdx, %rax
movl 0x18(%rsp), %edx
imulq $0x28, %rdx, %rdx
addq %rdx, %rax
movl %ecx, 0x18(%rax)
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rcx
imulq $0x380, %rcx, %rcx      # imm = 0x380
addq %rcx, %rax
movb $0x1, 0x2(%rax)
movl 0x24(%rsp), %eax
movl %eax, %ecx
leaq 0x7bd8f(%rip), %rax     # 0x8fec0
movq (%rax,%rcx,8), %rcx
addq 0x30(%rsp), %rcx
movq 0x68(%rsp), %rax
movq 0x98(%rax), %rax
movslq 0x48(%rsp), %rdx
imulq $0x380, %rdx, %rdx      # imm = 0x380
addq %rdx, %rax
movq %rcx, 0x378(%rax)
movq 0x68(%rsp), %rsi
callq 0x13530
movq 0x8(%rsp), %rdi
movq 0x68(%rsp), %rsi
callq 0x13650
addq $0x78, %rsp
retq
nopw (%rax,%rax)