// File: /workspace/github_cpp_makefile_star2_O2/martinferianc[P]CPUSimulator-EIE2/src/test_mips.cpp
// Function: main
int main(){
  mips_test_begin_suite();
  vector<test> instructions;
  mips_error err;

  //Test #1 if the cpu was created correctly
  mips_mem_h mem = mips_mem_create_ram(4096);
  mips_cpu_h cpu = mips_cpu_create(mem);
  int testId = mips_test_begin_test("<INTERNAL>");
  if (cpu!=0){
    mips_test_end_test(testId, true, "CPU Created");
  } else{
    mips_test_end_test(testId, false, "CPU Creation error");
    mips_test_end_suite();
  }
  //ENDTEST

  //Test #2 writing to register 0
  testId = mips_test_begin_test("<INTERNAL>");
  err = mips_cpu_set_register(cpu, 0, 1);
  uint32_t *r0 = new uint32_t;
  mips_cpu_get_register(cpu, 0, r0);
  if ((err!=mips_Success) || (*r0==0))
    mips_test_end_test(testId, true, "R[0] unchanged");
  else
    mips_test_end_test(testId, false, "R[0] changed");
  delete r0;
  //ENDTEST

  //Test #3 checking if registers are 0
  testId = mips_test_begin_test("<INTERNAL>");
  uint32_t *v = new uint32_t;
  for (int i = 0; i < 32; ++i){
    mips_cpu_get_register(cpu,i,v);
    if (v!=0)
    break;
  }
  if (v!=0)
    mips_test_end_test(testId, true, "Registers are zero");
  else
    mips_test_end_test(testId, false, "Registers are non-zero");
  *v=0;
  //ENDTEST


  //Test #4 Accessing invalid index
  testId = mips_test_begin_test("<INTERNAL>");
  err = mips_cpu_get_register(cpu, 32, v);
  if (err!=mips_Success)
    mips_test_end_test(testId, true, "Register could not be loaded");
  else
    mips_test_end_test(testId, false, "Register index error");
  //ENDTEST

  //Test #5 Test the CPU RESET
  testId = mips_test_begin_test("<INTERNAL>");
  mips_cpu_reset(cpu);
  for (int i = 0; i < 32; ++i){
    mips_cpu_get_register(cpu,i,v);
    if (v!=0)
    break;
  }
  if (v!=0)
    mips_test_end_test(testId, true, "Registers are zero");
  else
    mips_test_end_test(testId, false, "Registers are non-zero");
  delete v;

  //////////TEST SUITE//////////////////
  //ALWAYS R1(result), R2, R3(operands)

  //mips_cpu_set_debug_level(cpu, 2, NULL);

  err = load_instructions(instructions);
  err = load_memory(mem, instructions);
  if (err!=mips_Success){
    cout<<"!   (Error) Instructions could not be loaded from the file please check mips_cpu_instructions.txt"<<endl;
    mips_test_end_suite();
    mips_cpu_free(cpu);
    mips_mem_free(mem);
    return 0;
  }

  int skip_count = 0; //To skip the SKIP parts
  for (uint32_t i = 0; i < instructions.size(); ++i){
    uint32_t *pc = new uint32_t;
    mips_cpu_get_pc(cpu,pc);
    if (instructions[i].instruction_code==0){ //In case the CPU tries to execute the skip
      if (*pc==i*4)
        mips_cpu_set_pc(cpu,*pc+4);
      skip_count++;
      continue;
    }
    uint32_t regs_before [32];
    uint32_t regs_after [32];

    bool success = false;
    int testId = mips_test_begin_test(instructions[i].instruction_name.c_str());

    mips_cpu_set_register(cpu, 2, instructions[i].instruction_r1);
    mips_cpu_set_register(cpu, 3, instructions[i].instruction_r2);
    load_registers(regs_before, cpu);

    err = mips_cpu_step(cpu);
    load_registers(regs_after, cpu);

    mips_cpu_get_pc(cpu,pc);
    switch(instructions[i].instruction_name[0]){
      case 'B':
        //Branch should be taken, expected result == 1, pc changed in the next instruction
        if ((*pc==(i+1)*4) && (instructions[i].instruction_result==1) && (err==mips_Success)){
          if (instructions[i].instruction_name.length() > 4) {
            if(regs_after[31] != (i+2)*4)
            break;
          }
          err = mips_cpu_step(cpu); //Step to the instruction from where branch is performed
          if (err!=mips_Success)
            break;

          mips_cpu_get_pc(cpu,pc);
          if ((*pc==(i+3)*4) && (err==mips_Success)) //Branches always by 2
            success = true;

          break;
        }
        //Branch should not be taken, expected result == 0, pc = pc + 4
        if ((*pc==(i+1)*4) && (instructions[i].instruction_result==0) && (err==mips_Success)){

          err = mips_cpu_step(cpu); //Step to the instruction from where branch is performed
          if (err!=mips_Success)
            break;

          mips_cpu_get_pc(cpu,pc);

          if ((*pc==(i+2)*4) && (err==mips_Success))
            success = true;

          break;
          }

      case '<':
        if (err!=mips_Success)
          success = true;
        break;

      case 'J':
        if ((*pc==(i+1)*4) && (err==mips_Success)){
          if (instructions[i].instruction_name.length() >= 3) {
            if(regs_after[31] != (i+2)*4)
            break;
          }
          err = mips_cpu_step(cpu);
          if (err!=mips_Success)
            break;

          err = mips_cpu_get_pc(cpu,pc);
          if ((*pc==(i+3)*4) && (err==mips_Success))
            success = true;

          break;
        }
      break;
      default:

      //Test all other instructions
      if (regs_after[1] == instructions[i].instruction_result)
        success = true;

    }
    if (success){
      mips_test_end_test(testId, true, instructions[i].instruction_name.c_str());
      if (err==mips_ExceptionArithmeticOverflow)
        mips_cpu_set_pc(cpu, *pc + 4);

      switch (instructions[i].instruction_name[0]) {
        case '<':
          //Manually adjust the PC because the instruction resulted in an error
          mips_cpu_set_pc(cpu, *pc + 4);
          break;

        case 'B':
          if (instructions[i].instruction_result==1) {
            i=i+2;
            skip_count=skip_count+2;
          } else {
            i=i+1;
            skip_count=skip_count+1;
          }
          break;

        case 'J':
          i=i+2;
          skip_count=skip_count+2;
          break;
      }
    } else {
      cout<<"-----------------------------------------------------------------------"<<endl;
      cout<<"| Test: "<<i+1-skip_count<<"| To memory: "<<instructions[i].str()<<"|"<<endl;
      cout<<"-----------------------REGISTERS BEFORE-------------------------------"<<endl;
      print_registers(regs_before);
      cout<<endl<<"----------------------REGISTERS AFTER---------------------------"<<endl;
      print_registers(regs_after);
      mips_cpu_get_pc(cpu,pc);
      mips_test_end_test(testId, false, instructions[i].instruction_name.c_str());
      switch (instructions[i].instruction_name[0]) {
        case '<':
          cout<<endl<<"!   (Error) Instruction should have not been executed: Instruction is invalid!"<<endl;
          if (err != mips_Success)
            mips_cpu_set_pc(cpu, *pc + 4);
        break;

        case 'B':
          if (instructions[i].instruction_result==1){
            if (instructions[i].instruction_name.length() > 4) {
              if(regs_after[31] != (i+2)*4)
                cout<<endl<<"!   (Error) PC + 8 not in R[31]:"<<regs_after[31]<<" PC Awaited: "<<(i+3)*4<<endl;
            }
            cout<<endl<<"!   (Error) PC: "<<*pc<<" PC Awaited: "<<(i+3)*4<<endl;
          }else{
            cout<<endl<<"!   (Error) PC: "<<*pc<<" PC Awaited: "<<(i+1)*4<<endl;
          }
          mips_cpu_set_pc(cpu, (i+3)*4);
          i=i+2;
          skip_count=skip_count+2;
        break;

        case 'J':
          cout<<endl<<"!   (Error) PC: "<<*pc<<" PC Awaited: "<<(i+2)*4<<endl;
          mips_cpu_set_pc(cpu, (i+3)*4);
          i=i+2;
          skip_count=skip_count+2;
        break;

        default:
          cout<<endl<<"!   (Error) Got:"<<regs_after[1]<<" Actual Result: "<<instructions[i].instruction_result<<endl;
          if (err != mips_Success)
            mips_cpu_set_pc(cpu, *pc + 4);
        break;
      }
      cout<<"!    Going to the next memory location PC + 4:"<<endl;
      cout<<"-----------------------------------------------------"<<endl;

      delete pc;
    }
  }
  //////////END TEST SUITE//////////////////
  mips_test_end_suite();
  mips_cpu_free(cpu);
  mips_mem_free(mem);
  return 0;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp            # imm = 0x188
callq 0x35bc
xorps %xmm0, %xmm0
movaps %xmm0, 0x10(%rsp)
andq $0x0, 0x20(%rsp)
movl $0x1000, %edi           # imm = 0x1000
callq 0x46f8
movq %rax, 0x40(%rsp)
movq %rax, 0x30(%rsp)
movq %rax, %rdi
callq 0x4800
movq %rax, (%rsp)
leaq 0x1c24(%rip), %rdi      # 0x94fb
callq 0x366c
cmpq $0x0, (%rsp)
je 0x78f6
leaq 0x240c(%rip), %rdx      # 0x9cf6
pushq $0x1
popq %rsi
movl %eax, %edi
callq 0x37d6
jmp 0x790b
leaq 0x2405(%rip), %rdx      # 0x9d02
movl %eax, %edi
xorl %esi, %esi
callq 0x37d6
callq 0x3887
leaq 0x1be9(%rip), %rdi      # 0x94fb
callq 0x366c
movl %eax, %ebx
pushq $0x1
popq %rbp
movq (%rsp), %rdi
xorl %esi, %esi
movl %ebp, %edx
callq 0x4884
movl %eax, %r12d
pushq $0x4
popq %rdi
callq 0x31d0
movq %rax, %r15
movq (%rsp), %rdi
xorl %esi, %esi
movq %rax, %rdx
callq 0x4864
testl %r12d, %r12d
je 0x7953
leaq 0x23c4(%rip), %rdx      # 0x9d15
jmp 0x7962
cmpl $0x0, (%r15)
je 0x794a
leaq 0x23c4(%rip), %rdx      # 0x9d24
xorl %ebp, %ebp
movl %ebx, %edi
movl %ebp, %esi
callq 0x37d6
pushq $0x4
popq %rsi
movq %r15, %rdi
callq 0x31e0
leaq 0x1b7e(%rip), %rdi      # 0x94fb
callq 0x366c
movl %eax, %ebp
pushq $0x4
popq %rdi
callq 0x31d0
movq %rax, %rbx
movq (%rsp), %rdi
xorl %esi, %esi
movq %rax, %rdx
callq 0x4864
leaq 0x238d(%rip), %rdx      # 0x9d31
pushq $0x1
popq %rsi
movl %ebp, %edi
callq 0x37d6
andl $0x0, (%rbx)
leaq 0x1b43(%rip), %rdi      # 0x94fb
callq 0x366c
movl %eax, %ebp
pushq $0x20
popq %rsi
movq (%rsp), %rdi
movq %rbx, %rdx
callq 0x4864
xorl %esi, %esi
testl %eax, %eax
setne %sil
leaq 0x2367(%rip), %rax      # 0x9d44
leaq 0x237d(%rip), %rdx      # 0x9d61
cmovneq %rax, %rdx
movl %ebp, %edi
callq 0x37d6
leaq 0x1b05(%rip), %rdi      # 0x94fb
callq 0x366c
movl %eax, %ebp
movq (%rsp), %rdi
callq 0x483b
movq (%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq 0x4864
leaq 0x2316(%rip), %rdx      # 0x9d31
pushq $0x1
popq %rsi
movl %ebp, %edi
callq 0x37d6
pushq $0x4
popq %rsi
movq %rbx, %rdi
callq 0x31e0
leaq 0x10(%rsp), %rdi
callq 0x7498
leaq 0x48(%rsp), %rdi
leaq 0x10(%rsp), %rsi
callq 0x81a6
leaq 0x40(%rsp), %rdi
leaq 0x48(%rsp), %rsi
callq 0x772a
movl %eax, %ebx
leaq 0x48(%rsp), %rdi
callq 0x8200
testl %ebx, %ebx
je 0x7aa0
movq 0x6561(%rip), %rdi      # 0xdfd0
leaq 0x2300(%rip), %rsi      # 0x9d76
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
callq 0x3887
movq (%rsp), %rdi
callq 0x4c9a
movq 0x30(%rsp), %rdi
callq 0x47e4
jmp 0x8114
movl $0x0, 0xc(%rsp)
xorl %ebp, %ebp
movl %ebp, %ebx
movq 0x18(%rsp), %rax
subq 0x10(%rsp), %rax
cqto
pushq $0x38
popq %rcx
idivq %rcx
cmpq %rbx, %rax
jbe 0x80fc
pushq $0x4
popq %rdi
callq 0x31d0
movq %rax, %r13
movq (%rsp), %rdi
movq %rax, %rsi
callq 0x48bc
movq 0x10(%rsp), %rax
imulq $0x38, %rbx, %r14
cmpl $0x0, (%rax,%r14)
je 0x7bfe
addq %r14, %rax
movq 0x8(%rax), %rdi
callq 0x366c
movl %eax, 0x2c(%rsp)
movq 0x10(%rsp), %rax
movl 0x2c(%rax,%r14), %edx
movq (%rsp), %rdi
pushq $0x2
popq %rsi
callq 0x4884
movq 0x10(%rsp), %rax
movl 0x30(%rax,%r14), %edx
movq (%rsp), %rdi
pushq $0x3
popq %rsi
callq 0x4884
leaq 0x100(%rsp), %rdi
movq (%rsp), %rsi
callq 0x7835
movq (%rsp), %rdi
callq 0x48ce
movl %eax, %ebx
leaq 0x80(%rsp), %rdi
movq (%rsp), %rsi
callq 0x7835
movq (%rsp), %rdi
movq %r13, %rsi
callq 0x48bc
movq 0x10(%rsp), %rax
movq 0x8(%rax,%r14), %rcx
movzbl (%rcx), %ecx
cmpl $0x3c, %ecx
je 0x7cc4
addq %r14, %rax
cmpl $0x42, %ecx
je 0x7c20
cmpl $0x4a, %ecx
jne 0x7c82
leal 0x4(,%rbp,4), %ecx
xorl (%r13), %ecx
orl %ebx, %ecx
jne 0x7d35
leal (,%rbp,4), %r15d
cmpq $0x3, 0x10(%rax)
jb 0x7bc5
leal 0x8(%r15), %eax
cmpl %eax, 0xfc(%rsp)
jne 0x7d33
movq (%rsp), %rdi
callq 0x48ce
movl %eax, %ebx
testl %eax, %eax
jne 0x7d35
movq (%rsp), %rdi
movq %r13, %rsi
callq 0x48bc
addl $0xc, %r15d
xorl (%r13), %r15d
xorl %ebx, %ebx
orl %eax, %r15d
je 0x7cc8
movl %eax, %ebx
jmp 0x7d35
leal (,%rbp,4), %esi
cmpl %esi, (%r13)
jne 0x7c17
addl $0x4, %esi
movq (%rsp), %rdi
callq 0x48a6
incl 0xc(%rsp)
jmp 0x80ee
leal 0x4(,%rbp,4), %ecx
cmpl %ecx, (%r13)
jne 0x7cc4
leal (,%rbp,4), %r15d
movl 0x28(%rax), %ecx
movl %ecx, %edx
xorl $0x1, %edx
orl %ebx, %edx
jne 0x7c93
cmpq $0x5, 0x10(%rax)
jb 0x7c5d
leal 0x8(%r15), %eax
cmpl %eax, 0xfc(%rsp)
jne 0x7d33
movq (%rsp), %rdi
callq 0x48ce
movl %eax, %ebx
testl %eax, %eax
jne 0x7d35
movq (%rsp), %rdi
movq %r13, %rsi
callq 0x48bc
addl $0xc, %r15d
jmp 0x7cba
movl 0x84(%rsp), %ecx
cmpl 0x28(%rax), %ecx
je 0x7cc8
jmp 0x7d35
orl %ebx, %ecx
jne 0x7cc4
movq (%rsp), %rdi
callq 0x48ce
movl %eax, %ebx
testl %eax, %eax
jne 0x7d35
movq (%rsp), %rdi
movq %r13, %rsi
callq 0x48bc
addl $0x8, %r15d
xorl %ebx, %ebx
cmpl %r15d, (%r13)
je 0x7cc8
jmp 0x7d35
testl %ebx, %ebx
je 0x7d33
movq 0x10(%rsp), %rax
movq 0x8(%rax,%r14), %rdx
movl 0x2c(%rsp), %edi
pushq $0x1
popq %rsi
callq 0x37d6
cmpl $0x2006, %ebx           # imm = 0x2006
jne 0x7cf6
movl (%r13), %esi
addl $0x4, %esi
movq (%rsp), %rdi
callq 0x48a6
movq 0x10(%rsp), %rax
movq 0x8(%rax,%r14), %rcx
movzbl (%rcx), %ecx
cmpl $0x4a, %ecx
je 0x8039
cmpl $0x42, %ecx
je 0x802c
cmpl $0x3c, %ecx
jne 0x80ee
movl (%r13), %esi
addl $0x4, %esi
movq (%rsp), %rdi
callq 0x48a6
jmp 0x80ee
xorl %ebx, %ebx
movq 0x6294(%rip), %rdi      # 0xdfd0
leaq 0x2095(%rip), %rsi      # 0x9dd8
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
movq 0x6279(%rip), %rdi      # 0xdfd0
leaq 0x20c2(%rip), %rsi      # 0x9e20
callq 0x31c0
leal 0x1(%rbp), %esi
movq %rsi, 0x38(%rsp)
subl 0xc(%rsp), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
leaq 0x20a8(%rip), %rsi      # 0x9e29
callq 0x31c0
movq %rax, %r12
movq %r13, %r15
movq %rbp, %r13
movq 0x10(%rsp), %rsi
addq %r14, %rsi
leaq 0x60(%rsp), %rbp
movq %rbp, %rdi
callq 0x8222
movq %r12, %rdi
movq %rbp, %rsi
callq 0x31b0
movq %rax, %rdi
leaq 0x207e(%rip), %rsi      # 0x9e37
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
movq %rbp, %rdi
callq 0x30d0
movq 0x61fb(%rip), %rdi      # 0xdfd0
leaq 0x205d(%rip), %rsi      # 0x9e39
callq 0x31c0
movq %r13, %rbp
movq %rax, %rdi
callq 0x30e0
leaq 0x100(%rsp), %rdi
callq 0x778e
movq 0x61d0(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x2071(%rip), %rsi      # 0x9e80
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
leaq 0x80(%rsp), %rdi
callq 0x778e
movq (%rsp), %rdi
movq %r15, %rsi
callq 0x48bc
movq 0x10(%rsp), %rax
movq 0x8(%rax,%r14), %rdx
movl 0x2c(%rsp), %edi
xorl %esi, %esi
callq 0x37d6
movq 0x10(%rsp), %rax
movq 0x8(%rax,%r14), %rcx
movzbl (%rcx), %ecx
cmpl $0x3c, %ecx
je 0x7f98
cmpl $0x42, %ecx
je 0x7ecf
cmpl $0x4a, %ecx
jne 0x7fbd
movq 0x615b(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x20bb(%rip), %rsi      # 0x9f3f
callq 0x31c0
movl (%r15), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
leaq 0x2093(%rip), %rsi      # 0x9f31
callq 0x31c0
leal 0x8(,%rbp,4), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
callq 0x30e0
leal 0xc(,%rbp,4), %esi
movq (%rsp), %rdi
callq 0x48a6
jmp 0x80a5
addq %r14, %rax
cmpl $0x1, 0x28(%rax)
jne 0x8046
cmpq $0x5, 0x10(%rax)
jb 0x7f44
movl 0xfc(%rsp), %ebx
leal 0x8(,%rbp,4), %eax
cmpl %eax, %ebx
je 0x7f44
movq 0x60d4(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x2005(%rip), %rsi      # 0x9f10
callq 0x31c0
movq %rax, %rdi
movq %rbx, %rsi
callq 0x3120
movq %rax, %rdi
leaq 0x200c(%rip), %rsi      # 0x9f31
callq 0x31c0
leal (,%rbp,4), %esi
addl $0xc, %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
callq 0x30e0
movq 0x6085(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x1fe5(%rip), %rsi      # 0x9f3f
callq 0x31c0
movl (%r15), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
leaq 0x1fbd(%rip), %rsi      # 0x9f31
callq 0x31c0
leal 0xc(,%rbp,4), %ebx
movq %rax, %rdi
movq %rbx, %rsi
callq 0x3120
movq %rax, %rdi
callq 0x30e0
jmp 0x809a
movq 0x6031(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x1f13(%rip), %rsi      # 0x9ec1
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
jmp 0x8010
movq 0x600c(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x1f7d(%rip), %rsi      # 0x9f50
callq 0x31c0
movl 0x84(%rsp), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
leaq 0x1f70(%rip), %rsi      # 0x9f61
callq 0x31c0
movq 0x10(%rsp), %rcx
movl 0x28(%rcx,%r14), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
callq 0x30e0
testl %ebx, %ebx
je 0x80ad
movl (%r15), %esi
addl $0x4, %esi
movq (%rsp), %rdi
callq 0x48a6
jmp 0x80ad
addq %r14, %rax
cmpl $0x1, 0x28(%rax)
jne 0x80f5
addl $0x2, %ebp
addl $0x2, 0xc(%rsp)
jmp 0x80ee
movq 0x5f83(%rip), %rdi      # 0xdfd0
callq 0x30e0
movq %rax, %rdi
leaq 0x1ee3(%rip), %rsi      # 0x9f3f
callq 0x31c0
movl (%r15), %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
leaq 0x1ebb(%rip), %rsi      # 0x9f31
callq 0x31c0
movq 0x38(%rsp), %rsi
shll $0x2, %esi
movq %rax, %rdi
callq 0x3120
movq %rax, %rdi
callq 0x30e0
leal 0xc(,%rbp,4), %ebx
movq (%rsp), %rdi
movl %ebx, %esi
callq 0x48a6
addl $0x2, %ebp
addl $0x2, 0xc(%rsp)
movq 0x5f1c(%rip), %rdi      # 0xdfd0
leaq 0x1eb7(%rip), %rsi      # 0x9f72
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
movq 0x5f01(%rip), %rdi      # 0xdfd0
leaq 0x1d14(%rip), %rsi      # 0x9dea
callq 0x31c0
movq %rax, %rdi
callq 0x30e0
movq %r15, %rdi
pushq $0x4
popq %rsi
callq 0x31e0
incl %ebp
jmp 0x7aaa
incl %ebp
jmp 0x7c17
callq 0x3887
movq (%rsp), %rdi
callq 0x4c9a
movq 0x30(%rsp), %rdi
callq 0x47e4
leaq 0x10(%rsp), %rdi
callq 0x8200
xorl %eax, %eax
addq $0x188, %rsp            # imm = 0x188
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq %rax, %rbx
leaq 0x48(%rsp), %rdi
callq 0x8200
jmp 0x8167
jmp 0x8164
jmp 0x8164
jmp 0x8164
jmp 0x8164
jmp 0x8164
jmp 0x8164
jmp 0x8164
jmp 0x8164
movq %rax, %rbx
leaq 0x60(%rsp), %rdi
callq 0x30d0
jmp 0x8167
jmp 0x8164
jmp 0x8164
movq %rax, %rbx
leaq 0x10(%rsp), %rdi
callq 0x8200
movq %rbx, %rdi
callq 0x3330
nop