// File: jkingan[P]ladyheather/heathgps.cpp
// Function: set_x72_discipline(int)
void set_x72_discipline(int val)
{
   // set the X72 PPS discipline mode
   // 0=off, 1=enabled, lock pin normal mode,  2=enabled, lock pin indicates Rb and disipline locked
   // 3=enable SW discipline on units with firmware capability
   if(read_only) return;

   if(val < 0) val = 0;
   else if(val > 3) val = 3;
//if(debug_file) fprintf(debug_file, "set dmode %d  have_pps:%d  hw:%d\n", val, have_x72_pps, x72_fw_discipline());  //burp
//sprintf(debug_text, "set dmode %d  have_pps:%d  hw:%d", val, have_x72_pps, x72_fw_discipline());

   if(have_x72_pps && val && (x72_fw_discipline() == 0)) {  // can only do software discipline
      val = 3;
   }

   have_x72_dmode = 1;
   user_set_x72_dmode = 1;
   x72_dmode_val = val;
   last_x72_dmode = val;

   save_x72_state();

   if(val > 2) {
      if(x72_fw_discipline()) {  // disable firmware disciplining
         sprintf(out, "g%d", 0);
         queue_x72_cmd(out, X72_SET_DMODE_MSG);
      }
      x72_user_dis = val; // enable SW disciplining
      x72_start_discipline();
   }
   else if(val) {  // enabling discipline
      if(x72_fw_discipline()) {  // firmware disciplining
         sprintf(out, "g%d", val);
         queue_x72_cmd(out, X72_SET_DMODE_MSG);
         x72_user_dis = 0;
      }
      else {  // enable software discipline algorithm
         x72_user_dis = val;
         x72_start_discipline();
      }
   }
   else {  // disabling disipline
      if(x72_fw_discipline()) {  // disable firmware disciplining
         sprintf(out, "g%d", val);
         queue_x72_cmd(out, X72_SET_DMODE_MSG);
      }
      x72_user_dis = val; // disable SW disciplining
   }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
subq $0x10, %rsp
movl %edi, -0x4(%rbp)
leaq 0x300928(%rip), %rax    # 0x3961fa
cmpb $0x0, (%rax)
je 0x958dc
jmp 0x95a3e
cmpl $0x0, -0x4(%rbp)
jge 0x958eb
movl $0x0, -0x4(%rbp)
jmp 0x958fa
cmpl $0x3, -0x4(%rbp)
jle 0x958f8
movl $0x3, -0x4(%rbp)
jmp 0x958fa
leaq 0x1e45af(%rip), %rax    # 0x279eb0
cmpl $0x0, (%rax)
je 0x9591d
cmpl $0x0, -0x4(%rbp)
je 0x9591d
callq 0x94230
cmpl $0x0, %eax
jne 0x9591d
movl $0x3, -0x4(%rbp)
leaq 0x1e45d8(%rip), %rax    # 0x279efc
movl $0x1, (%rax)
leaq 0x1e47b3(%rip), %rax    # 0x27a0e4
movl $0x1, (%rax)
movl -0x4(%rbp), %ecx
leaq 0x1e46ab(%rip), %rax    # 0x279fec
movl %ecx, (%rax)
movl -0x4(%rbp), %ecx
leaq 0x1e47b3(%rip), %rax    # 0x27a100
movl %ecx, (%rax)
callq 0x92e20
cmpl $0x2, -0x4(%rbp)
jle 0x959a2
callq 0x94230
cmpl $0x0, %eax
je 0x9598c
leaq 0x305a95(%rip), %rdi    # 0x39b400
leaq 0xf18c0(%rip), %rsi     # 0x187232
xorl %edx, %edx
movb $0x0, %al
callq 0x9060
leaq 0x305a7e(%rip), %rdi    # 0x39b400
movl $0x2be, %esi            # imm = 0x2BE
callq 0x82fd0
movl -0x4(%rbp), %ecx
leaq 0x1e473a(%rip), %rax    # 0x27a0d0
movl %ecx, (%rax)
callq 0xc4ec0
jmp 0x95a3e
cmpl $0x0, -0x4(%rbp)
je 0x959fd
callq 0x94230
cmpl $0x0, %eax
je 0x959ea
movl -0x4(%rbp), %edx
leaq 0x305a44(%rip), %rdi    # 0x39b400
leaq 0xf186f(%rip), %rsi     # 0x187232
movb $0x0, %al
callq 0x9060
leaq 0x305a2f(%rip), %rdi    # 0x39b400
movl $0x2be, %esi            # imm = 0x2BE
callq 0x82fd0
leaq 0x1e46ee(%rip), %rax    # 0x27a0d0
movl $0x0, (%rax)
jmp 0x959fb
movl -0x4(%rbp), %ecx
leaq 0x1e46dc(%rip), %rax    # 0x27a0d0
movl %ecx, (%rax)
callq 0xc4ec0
jmp 0x95a3c
callq 0x94230
cmpl $0x0, %eax
je 0x95a30
movl -0x4(%rbp), %edx
leaq 0x3059ef(%rip), %rdi    # 0x39b400
leaq 0xf181a(%rip), %rsi     # 0x187232
movb $0x0, %al
callq 0x9060
leaq 0x3059da(%rip), %rdi    # 0x39b400
movl $0x2be, %esi            # imm = 0x2BE
callq 0x82fd0
movl -0x4(%rbp), %ecx
leaq 0x1e4696(%rip), %rax    # 0x27a0d0
movl %ecx, (%rax)
jmp 0x95a3e
addq $0x10, %rsp
popq %rbp
retq
nopw %cs:(%rax,%rax)