// File: /workspace/github_c_makefile_star2_O2/shifengbin[P]bishe/Output/../Persistence/sqlite3.c
// Function: computeLimitRegisters
static void computeLimitRegisters(Parse *pParse, Select *p, int iBreak){
  Vdbe *v = 0;
  int iLimit = 0;
  int iOffset;
  int n;
  if( p->iLimit ) return;

  /* 
  ** "LIMIT -1" always shows all rows.  There is some
  ** controversy about what the correct behavior should be.
  ** The current implementation interprets "LIMIT 0" to mean
  ** no rows.
  */
  sqlite3ExprCacheClear(pParse);
  assert( p->pOffset==0 || p->pLimit!=0 );
  if( p->pLimit ){
    p->iLimit = iLimit = ++pParse->nMem;
    v = sqlite3GetVdbe(pParse);
    assert( v!=0 );
    if( sqlite3ExprIsInteger(p->pLimit, &n) ){
      sqlite3VdbeAddOp2(v, OP_Integer, n, iLimit);
      VdbeComment((v, "LIMIT counter"));
      if( n==0 ){
        sqlite3VdbeGoto(v, iBreak);
      }else if( n>=0 && p->nSelectRow>(u64)n ){
        p->nSelectRow = n;
      }
    }else{
      sqlite3ExprCode(pParse, p->pLimit, iLimit);
      sqlite3VdbeAddOp1(v, OP_MustBeInt, iLimit); VdbeCoverage(v);
      VdbeComment((v, "LIMIT counter"));
      sqlite3VdbeAddOp2(v, OP_IfNot, iLimit, iBreak); VdbeCoverage(v);
    }
    if( p->pOffset ){
      p->iOffset = iOffset = ++pParse->nMem;
      pParse->nMem++;   /* Allocate an extra register for limit+offset */
      sqlite3ExprCode(pParse, p->pOffset, iOffset);
      sqlite3VdbeAddOp1(v, OP_MustBeInt, iOffset); VdbeCoverage(v);
      VdbeComment((v, "OFFSET counter"));
      sqlite3VdbeAddOp3(v, OP_SetIfNotPos, iOffset, iOffset, 0);
      sqlite3VdbeAddOp3(v, OP_Add, iLimit, iOffset, iOffset+1);
      VdbeComment((v, "LIMIT+OFFSET"));
      sqlite3VdbeAddOp3(v, OP_SetIfNotPos, iLimit, iOffset+1, -1);
    }
  }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
cmpl $0x0, 0xc(%rsi)
je 0x5393c
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl %edx, %r13d
movq %rsi, %r12
movq %rdi, %r15
callq 0x5721e
cmpq $0x0, 0x60(%r12)
je 0x5392d
movl 0x54(%r15), %ebx
incl %ebx
movl %ebx, 0x54(%r15)
movl %ebx, 0xc(%r12)
movq %r15, %rdi
callq 0x49f90
movq %rax, %r14
movq 0x60(%r12), %rdi
leaq -0x30(%rbp), %rsi
callq 0x4de36
testl %eax, %eax
movq %r14, -0x38(%rbp)
je 0x539b5
movl %r13d, -0x2c(%rbp)
movq %r14, %r13
movl -0x30(%rbp), %r14d
pushq $0x17
popq %rsi
movq %r13, %rdi
movl %r14d, %edx
movl %ebx, %ecx
callq 0x4a1ab
testq %r14, %r14
je 0x539e3
testl %r14d, %r14d
js 0x539ee
cmpq %r14, 0x20(%r12)
jbe 0x539ee
movq %r14, 0x20(%r12)
jmp 0x539ee
movq 0x60(%r12), %rsi
movq %r15, %rdi
movl %ebx, %edx
callq 0x4a07d
pushq $0x27
popq %rsi
movq %r14, %rdi
movl %ebx, %edx
callq 0x4b9b3
pushq $0x2f
popq %rsi
movq %r14, %rdi
movl %ebx, %edx
movl %r13d, %ecx
callq 0x4a1ab
jmp 0x539ee
movq %r13, %rdi
movl -0x2c(%rbp), %esi
callq 0x4a0cb
movq 0x68(%r12), %rsi
testq %rsi, %rsi
je 0x5392d
movl 0x54(%r15), %r13d
leal 0x1(%r13), %r14d
movl %r14d, 0x10(%r12)
addl $0x2, %r13d
movl %r13d, 0x54(%r15)
movq %r15, %rdi
movl %r14d, %edx
callq 0x4a07d
pushq $0x27
popq %rsi
movq -0x38(%rbp), %r15
movq %r15, %rdi
movl %r14d, %edx
callq 0x4b9b3
movq %r15, %rdi
movl $0x8c, %esi
movl %r14d, %edx
movl %r14d, %ecx
xorl %r8d, %r8d
callq 0x385b6
pushq $0x59
popq %rsi
movq %r15, %rdi
movl %ebx, %edx
movl %r14d, %ecx
movl %r13d, %r8d
callq 0x385b6
pushq $-0x1
popq %r8
movq %r15, %rdi
movl $0x8c, %esi
movl %ebx, %edx
movl %r13d, %ecx
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x385b6