// File: /workspace/github_cpp_makefile_star2_O2/luooofan[P]hblzbd_compiler/src/Pass/generate_arm_from_ssa.cpp
// Function: GenerateArmFromSSA::ConvertDiv2Shift(ArmBasicBlock*, arm::Reg*, Value*, int)
bool GenerateArmFromSSA::ConvertDiv2Shift(ArmBasicBlock* armbb, Reg* rd, Value* val, int imm) {
  // 如果除数是0 应该生成报错
  if (0 == imm) {
    MyAssert(0);
  }
  auto eval_n = [](int imm) {
    int n = 0;
    while (imm > 1) {
      imm >>= 1;
      ++n;
    }
    return n;
  };
  auto cal = [](int b) {
    if (b < 0) b = -b;
    long long k = std::log2(b);
    long long m = (1.0 * (1ll << (k + 32)) / b + 1);
    return std::make_pair(k, m);
  };
  // 如果除数是2的幂次方 生成一条mov rd rm A(L)SR n的指令 允许1-32位
  // FIXME: 这样做并不适用于被除数是负数的情况
  // if (0 == (imm & (imm - 1))) {
  //   std::cout << "Warning Div" << std::endl;
  //   auto op2 = new Operand2(ResolveValue2Reg(armbb, val), new Shift(Shift::OpCode::ASR, eval_n(imm)));
  //   new Move(rd, op2, armbb);
  //   return true;
  // }
  // 考虑负数情况
  if (0 == (imm & (imm - 1))) {
    // 1. asr vreg, rn, #31;  i.e. mov vreg, rn, ASR #31;
    auto vreg = NewVirtualReg();
    auto rn = ResolveValue2Reg(armbb, val);
    new Move(vreg, new Operand2(rn, new Shift(Shift::OpCode::ASR, 31)), armbb);
    // 2. add vreg2, rn, vreg, lsr #(32-n);
    auto vreg2 = NewVirtualReg();
    auto n = eval_n(imm);
    auto op2 = new Operand2(vreg, new Shift(Shift::OpCode::LSR, 32 - n));
    new BinaryInst(BinaryInst::OpCode::ADD, vreg2, rn, op2, armbb);
    // 3. asr rd, vreg2, #n;  i.e. mov rd, vreg2, ASR #n;
    new Move(rd, new Operand2(vreg2, new Shift(Shift::OpCode::ASR, n)), armbb);
    return true;
  }
  // 除其他常数优化
  // a/b的情况下，b为常数
  // (sub t0 0 a)   // b<0则有，b>0则无
  // smmul t1 t0/a m // t0和a看有无上一句
  // mov t2 t1 asr k
  // add t2 t2 t1 lsr 31
  else {
    return false;
    auto [k, m] = cal(imm);
    std::cout << "除常数优化" << imm << " " << k << " " << m << std::endl;
    if (imm == 30) {
      k = 4;
      m = 2290649225;
    } else if (imm == 998244353) {
      k = 26;
      m = 288737297;
    } else {
      return false;
    }
    Reg* vreg0;
    if (imm < 0) {
      vreg0 = NewVirtualReg();
      new BinaryInst(BinaryInst::OpCode::RSB, vreg0, ResolveValue2Reg(armbb, val), new Operand2(0), armbb);
    } else {
      vreg0 = ResolveValue2Reg(armbb, val);
    }
    auto vreg1 = NewVirtualReg();
    new BinaryInst(BinaryInst::OpCode::SMMUL, vreg1, vreg0, ResolveImm2Operand2(armbb, m), armbb);
    auto vreg3 = NewVirtualReg();
    if (imm == 30) {
      new BinaryInst(BinaryInst::OpCode::ADD, vreg3, vreg0, new Operand2(vreg1), armbb);
    }
    auto vreg2 = NewVirtualReg();
    if (imm == 30) {
      new Move(vreg2, new Operand2(vreg3, new Shift(Shift::OpCode::ASR, k)), armbb);
    } else {
      new Move(vreg2, new Operand2(vreg1, new Shift(Shift::OpCode::ASR, k)), armbb);
    }
    new BinaryInst(BinaryInst::OpCode::ADD, rd, vreg2, new Operand2(vreg1, new Shift(Shift::OpCode::LSR, 31)), armbb);
    return true;
  }
  return false;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, 0x20(%rsp)
movq %rsi, 0x8(%rsp)
testl %r8d, %r8d
je 0x3d68b
movl %r8d, %ebp
movq %rcx, %r14
movl %r8d, %eax
shrl %eax
andl $0x55555555, %eax       # imm = 0x55555555
movl %r8d, %ecx
subl %eax, %ecx
movl $0x33333333, %eax       # imm = 0x33333333
movl %ecx, %edx
andl %eax, %edx
shrl $0x2, %ecx
andl %eax, %ecx
addl %edx, %ecx
movl %ecx, %eax
shrl $0x4, %eax
addl %ecx, %eax
andl $0xf0f0f0f, %eax        # imm = 0xF0F0F0F
imull $0x1010101, %eax, %r12d # imm = 0x1010101
shrl $0x18, %r12d
cmpl $0x1, %r12d
ja 0x3d675
movq %rdi, %r13
callq 0x3cb82
movq %rax, 0x10(%rsp)
movq %r13, %rdi
movq 0x8(%rsp), %rsi
movq %r14, %rdx
callq 0x3d242
movq %rax, 0x18(%rsp)
pushq $0x28
popq %rdi
callq 0x8250
movq %rax, %r14
pushq $0x18
popq %rdi
callq 0x8250
movq %rax, %r15
pushq $0x18
popq %rdi
callq 0x8250
andl $0x0, (%rax)
movb $0x1, 0x4(%rax)
movl $0x1f, 0x8(%rax)
andq $0x0, 0x10(%rax)
movb $0x0, (%r15)
andl $0x0, 0x4(%r15)
movq 0x18(%rsp), %rcx
movq %rcx, 0x8(%r15)
movq %rax, 0x10(%r15)
xorl %ebx, %ebx
pushq $0x1
popq %r9
movq %r14, %rdi
movq 0x10(%rsp), %rsi
movq %r15, %rdx
movq 0x8(%rsp), %rcx
xorl %r8d, %r8d
callq 0x3fbc8
movq %r13, %rdi
callq 0x3cb82
movq %rax, %r13
cmpl $0x2, %ebp
jl 0x3d5b2
shrl %ebp
incl %ebx
jmp 0x3d5a7
pushq $0x18
popq %r15
movq %r15, %rdi
callq 0x8250
movq %rax, %r14
movq %r15, %rdi
callq 0x8250
pushq $0x20
popq %rcx
subl %ebx, %ecx
movl $0x2, (%rax)
movb $0x1, 0x4(%rax)
movl %ecx, 0x8(%rax)
andq $0x0, 0x10(%rax)
movb $0x0, (%r14)
andl $0x0, 0x4(%r14)
movq 0x10(%rsp), %rcx
movq %rcx, 0x8(%r14)
movq %rax, 0x10(%r14)
pushq $0x38
popq %rdi
callq 0x8250
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movq %r13, %rdx
movq 0x18(%rsp), %rcx
movq %r14, %r8
movq 0x8(%rsp), %r9
callq 0x3fd3c
pushq $0x28
popq %rdi
callq 0x8250
movq %rax, %r14
pushq $0x18
popq %rdi
callq 0x8250
movq %rax, %r15
pushq $0x18
popq %rdi
callq 0x8250
andl $0x0, (%rax)
movb $0x1, 0x4(%rax)
movl %ebx, 0x8(%rax)
andq $0x0, 0x10(%rax)
movb $0x0, (%r15)
andl $0x0, 0x4(%r15)
movq %r13, 0x8(%r15)
movq %rax, 0x10(%r15)
pushq $0x1
popq %r9
movq %r14, %rdi
movq 0x20(%rsp), %rsi
movq %r15, %rdx
movq 0x8(%rsp), %rcx
xorl %r8d, %r8d
callq 0x3fbc8
cmpl $0x2, %r12d
setb %al
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0x43956(%rip), %rdi     # 0x80fe8
leaq 0x18a4f(%rip), %rsi     # 0x560e8
callq 0x8240
leaq 0x1c14f(%rip), %rsi     # 0x597f4
movq %rax, %rdi
callq 0x8240
leaq 0x19c6c(%rip), %rsi     # 0x57320
movq %rax, %rdi
callq 0x8240
movq %rax, %rdi
movl $0xa0, %esi
callq 0x84b0
movq %rax, %rdi
callq 0x8170
movl $0xff, %edi
callq 0x8300
jmp 0x3d6ef
movq %rax, %rbx
pushq $0x38
popq %rsi
movq %r15, %rdi
jmp 0x3d70a
movq %rax, %rbx
pushq $0x18
jmp 0x3d706
movq %rax, %rbx
pushq $0x18
popq %rsi
movq %r15, %rdi
callq 0x8260
jmp 0x3d704
jmp 0x3d701
movq %rax, %rbx
pushq $0x28
popq %rsi
movq %r14, %rdi
callq 0x8260
movq %rbx, %rdi
callq 0x84d0
nop