// File: /workspace/github_c_makefile_star2_O1/nh13[P]ksw/src/parasail/src/nw_stats_diag_avx2_256_32.c
// Function: arr_store_rowcol
static inline void arr_store_rowcol(
        int *row,
        int *col,
        __m256i vWH,
        int32_t i,
        int32_t s1Len,
        int32_t j,
        int32_t s2Len)
{
    if (i+0 == s1Len-1 && 0 <= j-0 && j-0 < s2Len) {
        row[j-0] = (int32_t)_mm256_extract_epi32_rpl(vWH, 7);
    }
    if (j-0 == s2Len-1 && 0 <= i+0 && i+0 < s1Len) {
        col[(i+0)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 7);
    }
    if (i+1 == s1Len-1 && 0 <= j-1 && j-1 < s2Len) {
        row[j-1] = (int32_t)_mm256_extract_epi32_rpl(vWH, 6);
    }
    if (j-1 == s2Len-1 && 0 <= i+1 && i+1 < s1Len) {
        col[(i+1)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 6);
    }
    if (i+2 == s1Len-1 && 0 <= j-2 && j-2 < s2Len) {
        row[j-2] = (int32_t)_mm256_extract_epi32_rpl(vWH, 5);
    }
    if (j-2 == s2Len-1 && 0 <= i+2 && i+2 < s1Len) {
        col[(i+2)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 5);
    }
    if (i+3 == s1Len-1 && 0 <= j-3 && j-3 < s2Len) {
        row[j-3] = (int32_t)_mm256_extract_epi32_rpl(vWH, 4);
    }
    if (j-3 == s2Len-1 && 0 <= i+3 && i+3 < s1Len) {
        col[(i+3)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 4);
    }
    if (i+4 == s1Len-1 && 0 <= j-4 && j-4 < s2Len) {
        row[j-4] = (int32_t)_mm256_extract_epi32_rpl(vWH, 3);
    }
    if (j-4 == s2Len-1 && 0 <= i+4 && i+4 < s1Len) {
        col[(i+4)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 3);
    }
    if (i+5 == s1Len-1 && 0 <= j-5 && j-5 < s2Len) {
        row[j-5] = (int32_t)_mm256_extract_epi32_rpl(vWH, 2);
    }
    if (j-5 == s2Len-1 && 0 <= i+5 && i+5 < s1Len) {
        col[(i+5)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 2);
    }
    if (i+6 == s1Len-1 && 0 <= j-6 && j-6 < s2Len) {
        row[j-6] = (int32_t)_mm256_extract_epi32_rpl(vWH, 1);
    }
    if (j-6 == s2Len-1 && 0 <= i+6 && i+6 < s1Len) {
        col[(i+6)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 1);
    }
    if (i+7 == s1Len-1 && 0 <= j-7 && j-7 < s2Len) {
        row[j-7] = (int32_t)_mm256_extract_epi32_rpl(vWH, 0);
    }
    if (j-7 == s2Len-1 && 0 <= i+7 && i+7 < s1Len) {
        col[(i+7)] = (int32_t)_mm256_extract_epi32_rpl(vWH, 0);
    }
}

// Assembly:
pushq %rbp
pushq %r14
pushq %rbx
leal -0x1(%rcx), %eax
cmpl %edx, %eax
setne %r10b
testl %r8d, %r8d
sets %r11b
cmpl %r9d, %r8d
setge %bl
orb %r11b, %bl
orb %r10b, %bl
vextractf128 $0x1, %ymm0, %xmm1
movl %r8d, %r10d
jne 0x554ad5
vextractps $0x3, %xmm1, (%rdi,%r10,4)
cmpl %ecx, %edx
jge 0x554af0
testl %edx, %edx
js 0x554af0
leal -0x1(%r9), %r11d
cmpl %r8d, %r11d
jne 0x554af0
movl %edx, %r11d
vextractps $0x3, %xmm1, (%rsi,%r11,4)
leal 0x1(%rdx), %r11d
cmpl %eax, %r11d
setne %bl
testl %r8d, %r8d
setle %bpl
cmpl %r9d, %r8d
setg %r14b
orb %bpl, %r14b
orb %bl, %r14b
jne 0x554b18
vextractps $0x2, %xmm1, -0x4(%rdi,%r10,4)
cmpl %ecx, %r11d
jge 0x554b31
cmpl $-0x1, %edx
jl 0x554b31
cmpl %r9d, %r8d
jne 0x554b31
movl %r11d, %r10d
vextractps $0x2, %xmm1, (%rsi,%r10,4)
leal 0x2(%rdx), %r10d
cmpl %eax, %r10d
jne 0x554b5f
leal -0x2(%r8), %r11d
cmpl $0x2, %r8d
setge %bl
cmpl %r9d, %r11d
setl %bpl
andb %bl, %bpl
cmpb $0x1, %bpl
jne 0x554b5f
movl %r11d, %r11d
vextractps $0x1, %xmm1, (%rdi,%r11,4)
cmpl %ecx, %r10d
jge 0x554b7c
cmpl $-0x2, %edx
jl 0x554b7c
leal -0x1(%r8), %r11d
cmpl %r9d, %r11d
jne 0x554b7c
movl %r10d, %r10d
vextractps $0x1, %xmm1, (%rsi,%r10,4)
leal 0x3(%rdx), %r10d
cmpl %eax, %r10d
jne 0x554ba9
leal -0x3(%r8), %r11d
cmpl $0x3, %r8d
setge %bl
cmpl %r9d, %r11d
setl %bpl
andb %bl, %bpl
cmpb $0x1, %bpl
jne 0x554ba9
movl %r11d, %r11d
vmovss %xmm1, (%rdi,%r11,4)
cmpl %ecx, %r10d
jge 0x554bc5
cmpl $-0x3, %edx
jl 0x554bc5
leal -0x2(%r8), %r11d
cmpl %r9d, %r11d
jne 0x554bc5
movl %r10d, %r10d
vmovss %xmm1, (%rsi,%r10,4)
leal 0x4(%rdx), %r10d
cmpl %eax, %r10d
jne 0x554bf3
leal -0x4(%r8), %r11d
cmpl $0x4, %r8d
setge %bl
cmpl %r9d, %r11d
setl %bpl
andb %bl, %bpl
cmpb $0x1, %bpl
jne 0x554bf3
movl %r11d, %r11d
vextractps $0x3, %xmm0, (%rdi,%r11,4)
cmpl %ecx, %r10d
jge 0x554c10
cmpl $-0x4, %edx
jl 0x554c10
leal -0x3(%r8), %r11d
cmpl %r9d, %r11d
jne 0x554c10
movl %r10d, %r10d
vextractps $0x3, %xmm0, (%rsi,%r10,4)
leal 0x5(%rdx), %r10d
cmpl %eax, %r10d
jne 0x554c3e
leal -0x5(%r8), %r11d
cmpl $0x5, %r8d
setge %bl
cmpl %r9d, %r11d
setl %bpl
andb %bl, %bpl
cmpb $0x1, %bpl
jne 0x554c3e
movl %r11d, %r11d
vextractps $0x2, %xmm0, (%rdi,%r11,4)
cmpl %ecx, %r10d
jge 0x554c5b
cmpl $-0x5, %edx
jl 0x554c5b
leal -0x4(%r8), %r11d
cmpl %r9d, %r11d
jne 0x554c5b
movl %r10d, %r10d
vextractps $0x2, %xmm0, (%rsi,%r10,4)
leal 0x6(%rdx), %r10d
cmpl %eax, %r10d
jne 0x554c89
leal -0x6(%r8), %r11d
cmpl $0x6, %r8d
setge %bl
cmpl %r9d, %r11d
setl %bpl
andb %bl, %bpl
cmpb $0x1, %bpl
jne 0x554c89
movl %r11d, %r11d
vextractps $0x1, %xmm0, (%rdi,%r11,4)
cmpl %ecx, %r10d
jge 0x554ca6
cmpl $-0x6, %edx
jl 0x554ca6
leal -0x5(%r8), %r11d
cmpl %r9d, %r11d
jne 0x554ca6
movl %r10d, %r10d
vextractps $0x1, %xmm0, (%rsi,%r10,4)
leal 0x7(%rdx), %r10d
cmpl %eax, %r10d
jne 0x554cd0
leal -0x7(%r8), %eax
cmpl $0x7, %r8d
setge %r11b
cmpl %r9d, %eax
setl %bl
andb %r11b, %bl
cmpb $0x1, %bl
jne 0x554cd0
movl %eax, %eax
vmovss %xmm0, (%rdi,%rax,4)
cmpl %ecx, %r10d
jge 0x554ceb
cmpl $-0x7, %edx
jl 0x554ceb
addl $-0x6, %r8d
cmpl %r9d, %r8d
jne 0x554ceb
movl %r10d, %eax
vmovss %xmm0, (%rsi,%rax,4)
popq %rbx
popq %r14
popq %rbp
vzeroupper
retq
nop