// File: /workspace/github_c_makefile_star2_O2/xiane[P]libvphevcodec/AML_HEVCEncoder.cpp
// Function: Wave4VpuEncRegisterFrame(AMVHEVCEncHandle_s*, int)
AMVEnc_Status Wave4VpuEncRegisterFrame(AMVHEVCEncHandle *Handle, int alloc) {
    //Uint32 addr_report_buf = 0;    // [31:0]
    //Uint32 report_buf_size = 0;    // [31:0]
    //unsigned char report_endian = 0;    // [ 3:0]
    //Uint32 use_sec_axi = 0;    // [31:0]
    //Uint32 sec_axi_buf_size = 0x00012800;   // 74KB
    Uint32 temp;   // [31:0]
    Uint32 rd_ptr, wr_ptr, src_num, fb_num, i;   // [31:0
    Uint32 src_stride;
    Uint32 luma_stride, chroma_stride;
    Uint32 size_src_luma, size_src_chroma;
    Uint32 fb_width, fb_height, fb_stride;
    Uint32 fbc_luma_stride, fbc_chroma_stride;
    Uint32 size_fbc_luma, size_fbc_chroma;
    Uint32 size_fbc_luma_offset, size_fbc_chroma_offset;
    Uint32 size_mv_col, size_s2;

    Uint32 src_fb_addr[4][3];
    //Uint32 s2_addr;
    Uint32 fbc_fb_addr[32][4];

    Uint32 fb_set_start, fb_set_end;
    Uint32 fb_start_idx, fb_end_idx;
    //Uint32 addr_fb_arr[32];
    //Uint32 addr_mv_arr[8];
    rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);

    src_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_SRC_BUF_NUM);
    fb_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_FB_NUM);
    VLOG(DEBUG, "Wave4VpuEncRegisterFrame, rd:0x%x, wr:0x%x, src:%d, fb:%d\n", rd_ptr, wr_ptr, src_num, fb_num);
    if (src_num > 4)
        src_num = 4;
    if (fb_num > 4)
        fb_num = 4;
    Handle->src_num = src_num;
    Handle->fb_num = fb_num;

    if (alloc) {
        memset((void*) &Handle->src_pics[i], 0, sizeof(hevc_picture_t));
        for (i = 0; i < 4; i++) {
            memset((void*) &Handle->src_pics[i].vb, 0, sizeof(vpu_buffer_t));
            memset((void*) &Handle->fb_vb[i], 0, sizeof(vpu_buffer_t));
        }
        memset((void*) &Handle->fbc_ltable_vb, 0, sizeof(vpu_buffer_t));
        memset((void*) &Handle->fbc_ctable_vb, 0, sizeof(vpu_buffer_t));
        memset((void*) &Handle->fbc_mv_vb, 0, sizeof(vpu_buffer_t));
        memset((void*) &Handle->subsample_vb, 0, sizeof(vpu_buffer_t));
    }

    src_stride = wave420l_align32(Handle->enc_width);
    luma_stride = (src_format & 0x4) ? src_stride * 2 : src_stride;
    chroma_stride = src_stride;

    // set frame buffers

    // calculate required buffer size
    size_src_luma = luma_stride * wave420l_align32(Handle->enc_height);

    size_src_chroma = luma_stride * (wave420l_align16(Handle->enc_height) / 2);

    fb_width = wave420l_align32(Handle->enc_width);
    fb_height = wave420l_align8(Handle->enc_height);
    fb_stride = src_stride;

    // bit-depth = 8
    fbc_luma_stride = wave420l_align32(wave420l_align16(fb_width&0x3fff)*4);
    fbc_chroma_stride = wave420l_align32(wave420l_align16((fb_width>>1)&0x1fff)*4);

    size_fbc_luma = fbc_luma_stride * (fb_height / 4);
    size_fbc_chroma = fbc_chroma_stride * (fb_height / 4);
    size_fbc_luma_offset = wave420l_align256(fb_width ) * wave420l_align16(fb_height) / 32;
    size_fbc_luma_offset = wave420l_align16(size_fbc_luma_offset);
    size_fbc_chroma_offset = wave420l_align256(fb_width/2) * wave420l_align16(fb_height) / 32;
    size_fbc_chroma_offset = wave420l_align16(size_fbc_chroma_offset);

    size_mv_col = wave420l_align64(fb_width) * wave420l_align64(fb_height) / 16 + 64;
    size_mv_col = wave420l_align16(size_mv_col);
    size_s2 = wave420l_align16((fb_width>>2)&0xfff) * wave420l_align8((fb_height >> 2) & 0xfff);
    size_s2 = wave420l_align16(size_s2);
    for (i = 0; i < src_num; i++) {
        if (alloc) {
            memset((void*) &Handle->src_pics[i].vb, 0, sizeof(vpu_buffer_t));
            Handle->src_pics[i].vb.size = size_src_luma + size_src_chroma;
            Handle->src_pics[i].vb.size = ((Handle->src_pics[i].vb.size + 4095) & ~4095) + 4096;
            Handle->src_pics[i].vb.cached = 1;
            if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->src_pics[i].vb) < 0) {
                VLOG(ERR, "Wave4VpuEncRegisterFrame  error Handle->src_pics.vb alloc\n");
                return AMVENC_MEMORY_FAIL;
            }
            vdi_clear_memory(Handle->instance_id, Handle->src_pics[i].vb.phys_addr, Handle->src_pics[i].vb.size);
        }
        src_fb_addr[i][0] = Handle->src_pics[i].vb.phys_addr;
        src_fb_addr[i][1] = Handle->src_pics[i].vb.phys_addr + size_src_luma;
        src_fb_addr[i][2] = 0;
    }

    for (i = 0; i < fb_num; i++) {
        if (alloc) {
            memset((void*) &Handle->fb_vb[i], 0, sizeof(vpu_buffer_t));
            Handle->fb_vb[i].size = size_fbc_luma + size_fbc_chroma;
            Handle->fb_vb[i].size = ((Handle->fb_vb[i].size + 4095) & ~4095) + 4096;
            if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->fb_vb[i]) < 0) {
                VLOG(ERR, "Wave4VpuEncRegisterFrame  error Handle->fb_vb alloc\n");
                return AMVENC_MEMORY_FAIL;
            }
            vdi_clear_memory(Handle->instance_id, Handle->fb_vb[i].phys_addr, Handle->fb_vb[i].size);
        }
        fbc_fb_addr[i][0] = Handle->fb_vb[i].phys_addr;
        fbc_fb_addr[i][1] = Handle->fb_vb[i].phys_addr + size_fbc_luma;
        fbc_fb_addr[i][2] = 0;
    }

    if (alloc) {
        memset((void*) &Handle->fbc_ltable_vb, 0, sizeof(vpu_buffer_t));
        Handle->fbc_ltable_vb.size = ((size_fbc_luma_offset * fb_num + 4095) & ~4095) + 4096;
        if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->fbc_ltable_vb) < 0) {
            VLOG(ERR, "Wave4VpuEncRegisterFrame  error Handle->fbc_ltable_vb alloc\n");
            return AMVENC_MEMORY_FAIL;
        }
        vdi_clear_memory(Handle->instance_id, Handle->fbc_ltable_vb.phys_addr, Handle->fbc_ltable_vb.size);

        memset((void*) &Handle->fbc_ctable_vb, 0, sizeof(vpu_buffer_t));
        Handle->fbc_ctable_vb.size = ((size_fbc_chroma_offset * fb_num + 4095) & ~4095) + 4096;
        if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->fbc_ctable_vb) < 0) {
            VLOG(ERR, "Wave4VpuEncRegisterFrame  error Handle->fbc_ctable_vb alloc\n");
            return AMVENC_MEMORY_FAIL;
        }
        vdi_clear_memory(Handle->instance_id, Handle->fbc_ctable_vb.phys_addr, Handle->fbc_ctable_vb.size);

        memset((void*) &Handle->fbc_mv_vb, 0, sizeof(vpu_buffer_t));
        Handle->fbc_mv_vb.size = ((size_mv_col * fb_num + 4095) & ~4095) + 4096;
        if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->fbc_mv_vb) < 0) {
            VLOG(ERR, "Wave4VpuEncRegisterFrame  error Handle->fbc_mv_vb alloc\n");
            return AMVENC_MEMORY_FAIL;
        }
        vdi_clear_memory(Handle->instance_id, Handle->fbc_mv_vb.phys_addr, Handle->fbc_mv_vb.size);

        memset((void*) &Handle->subsample_vb, 0, sizeof(vpu_buffer_t));
        Handle->subsample_vb.size = ((size_s2 + 4095) & ~4095) + 4096;
        if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->subsample_vb) < 0) {
            VLOG(ERR, "Wave4VpuEncRegisterFrame  error Handle->subsample_vb alloc\n");
            return AMVENC_MEMORY_FAIL;
        }
        vdi_clear_memory(Handle->instance_id, Handle->subsample_vb.phys_addr, Handle->subsample_vb.size);
    }

    temp = 0;
    temp |= (0 << 24); // [27:24] codec_std_aux
    temp |= (1 << 16); // [23:16] codec_std
    temp |= (Handle->instance_id << 0);  // [15: 0] Handle->instance_id
    VpuWriteReg(Handle->instance_id, W4_INST_INDEX, temp);

    // Work Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_WORK_BASE, Handle->work_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_WORK_SIZE, Handle->work_vb.size);
    VpuWriteReg(Handle->instance_id, W4_WORK_PARAM, 0);

    fb_set_end = 1;
    fb_set_start = 1;
    fb_start_idx = 0;
    fb_end_idx = fb_num - 1;
    temp = 0;
    temp |= ((fbc_luma_stride & 0xffff) << 16); // [31:16] fbc_luma_stride
    temp |= ((fbc_chroma_stride & 0xffff) << 0);  // [15: 0] fbc_chroma_stride
    VpuWriteReg(Handle->instance_id, W4_FBC_STRIDE, temp);

    temp = 0;
    temp |= (0 << 30); // [   30] fbc_disable
    temp |= (0 << 29); // [   29] nv21_flag
    temp |= (0 << 28); // [   28] bwb_flag
    temp |= (0 << 24); // [27:24] axi_id
    temp |= ((0 & 0xf) << 20); // [23:20] bwb_format[3:0]
    temp |= (0 << 16); // [   16] cbcr_interlv
    temp |= ((fb_stride & 0xffff) << 0);  // [15: 0] fb_stride
    VpuWriteReg(Handle->instance_id, W4_COMMON_PIC_INFO, temp);

    temp = 0;
    temp |= (wave420l_align32(Handle->enc_width) << 16); // [31:16]
    temp |= (wave420l_align8(Handle->enc_height) << 0);  // [15: 0]
    VpuWriteReg(Handle->instance_id, W4_PIC_SIZE, temp);

    temp = 0;
    temp |= (0xc << 20); // [25:20] fbc_mode[5:0]
    temp |= (gol_endian << 16); // [19:16] fb_endian[3:0]
    temp |= (fb_set_end << 4);  // [    4] fb_set_end
    temp |= (fb_set_start << 3);  // [    3] fb_set_start
    VpuWriteReg(Handle->instance_id, W4_SFB_OPTION, temp);
    temp = 0;
    temp |= (fb_start_idx << 8);  // [12: 8]
    temp |= (fb_end_idx << 0);  // [ 4: 0]
    VpuWriteReg(Handle->instance_id, W4_SET_FB_NUM, temp);

    for (i = 0; i < fb_num; i++) {
        VpuWriteReg(Handle->instance_id, W4_ADDR_LUMA_BASE0 +(i*16), fbc_fb_addr[i][0]);
        VpuWriteReg(Handle->instance_id, W4_ADDR_CB_BASE0 +(i*16), fbc_fb_addr[i][1]);
        VpuWriteReg(Handle->instance_id, W4_ADDR_FBC_Y_OFFSET0 +(i*16), Handle->fbc_ltable_vb.phys_addr + size_fbc_luma_offset * i);
        VpuWriteReg(Handle->instance_id, W4_ADDR_FBC_C_OFFSET0 +(i*16), Handle->fbc_ctable_vb.phys_addr + size_fbc_chroma_offset * i);
        VpuWriteReg(Handle->instance_id, W4_ADDR_MV_COL0+(i*4), Handle->fbc_mv_vb.phys_addr + size_mv_col * i);
    }

    VpuWriteReg(Handle->instance_id, W4_ADDR_SUB_SAMPLED_FB_BASE, Handle->subsample_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_SUB_SAMPLED_ONE_FB_SIZE, size_s2);

    // issue command request
    VpuWriteReg(Handle->instance_id, W4_VPU_BUSY_STATUS, 1);
    VpuWriteReg(Handle->instance_id, W4_RET_SUCCESS, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_CORE_INDEX, 0);
    VpuWriteReg(Handle->instance_id, W4_COMMAND, SET_FRAMEBUF);
    VpuWriteReg(Handle->instance_id, W4_VPU_HOST_INT_REQ, 1);
    temp = VpuReadReg(Handle->instance_id, W4_VPU_BUSY_STATUS);
    VLOG(DEBUG, "W4_VPU_BUSY_STATUS :0x%x\n", temp);
    if (vdi_wait_interrupt(Handle->instance_id, VPU_BUSY_CHECK_TIMEOUT) == -1) {
        VLOG(ERR, "Wave4VpuEncRegisterFrame error time out\n");
        return AMVENC_TIMEOUT;
    }

    if (VpuReadReg(Handle->instance_id, W4_RET_SUCCESS) == 0) {
        uint32_t reasonCode = VpuReadReg(Handle->instance_id, W4_RET_FAIL_REASON);
        VLOG(ERR, "Wave4VpuEncRegisterFrame failedREASON CODE(%08x)\n", reasonCode);
        return AMVENC_HARDWARE;
    }
    temp = VpuReadReg(Handle->instance_id, W4_RET_SUCCESS);
    VLOG(DEBUG, "W4_RET_SUCCESS %x\n", temp);
    rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    src_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_SRC_BUF_NUM);
    fb_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_FB_NUM);
    VLOG(DEBUG, "Wave4VpuEncRegisterFrame, rd:0x%x, wr:0x%x, src:%d, fb:%d\n", rd_ptr, wr_ptr, src_num, fb_num);
    VLOG(DEBUG, "Wave4VpuEncRegisterFrame- End\n");
    return AMVENC_SUCCESS;
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x268, %rsp            # imm = 0x268
movl %esi, %r12d
movq %rdi, %rbx
movl (%rdi), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x1d8, %esi            # imm = 0x1D8
callq 0x2210
movl %eax, %r15d
movl (%rbx), %edi
movl $0x1cc, %esi            # imm = 0x1CC
callq 0x2210
pushq $0x4
popq %rsi
cmpl %esi, %r15d
cmovael %esi, %r15d
cmpl $0x4, %eax
cmovbl %eax, %esi
movl %r15d, 0x24(%rbx)
movl %esi, 0x28(%rbx)
testl %r12d, %r12d
je 0x540f
xorps %xmm0, %xmm0
movups %xmm0, 0xe0(%rbx)
movups %xmm0, 0xd0(%rbx)
movups %xmm0, 0xc0(%rbx)
movups %xmm0, 0xb0(%rbx)
movups %xmm0, 0xa0(%rbx)
leaq 0x1e0(%rbx), %rax
movq $-0x140, %rcx           # imm = 0xFEC0
movq %rax, %rdx
testq %rcx, %rcx
je 0x53d4
movups %xmm0, 0x30(%rax,%rcx)
movups %xmm0, 0x20(%rax,%rcx)
movups %xmm0, 0x10(%rdx)
movups %xmm0, (%rdx)
addq $0x50, %rcx
addq $0x20, %rdx
jmp 0x53b4
xorps %xmm0, %xmm0
movups %xmm0, 0x2d0(%rbx)
movups %xmm0, 0x2c0(%rbx)
movups %xmm0, 0x2b0(%rbx)
movups %xmm0, 0x2a0(%rbx)
movups %xmm0, 0x290(%rbx)
movups %xmm0, 0x280(%rbx)
movups %xmm0, 0x270(%rbx)
movups %xmm0, 0x260(%rbx)
movl %esi, 0x14(%rsp)
movl 0xc(%rbx), %eax
movl 0x10(%rbx), %ebp
leal 0x1f(%rax), %r8d
movl %r8d, %ecx
andl $-0x20, %ecx
leal 0x1f(%rbp), %edx
andl $0x7ffffe0, %edx        # imm = 0x7FFFFE0
leal 0xf(%rbp), %r13d
shrl %r13d
andl $0x7fffff8, %r13d       # imm = 0x7FFFFF8
addl %edx, %r13d
addl $0x7, %ebp
movl %ebp, %edi
andl $-0x8, %edi
movl %edi, %r14d
movl $0xff, %edx
leal (%rcx,%rdx), %esi
movl %esi, 0x10(%rsp)
movl %esi, %r10d
andl $0xffffff00, %r10d      # imm = 0xFFFFFF00
leal 0xf(%rdi), %esi
movl %esi, 0x3c(%rsp)
andl $-0x10, %esi
imull %esi, %r10d
leal 0x3f(%rcx), %r9d
imull %ecx, %r13d
shrl %ecx
addl %edx, %ecx
movl %ecx, 0xc(%rsp)
movl %ecx, %r11d
andl $0xfffff00, %r11d       # imm = 0xFFFFF00
imull %esi, %r11d
movl %r9d, 0x34(%rsp)
movl %r9d, %ecx
andl $-0x40, %ecx
addl $0x3f, %edi
movq %rdi, 0x20(%rsp)
movl %edi, %edx
andl $0x3ffffc0, %edx        # imm = 0x3FFFFC0
imull %ecx, %edx
movl %r8d, 0x38(%rsp)
movl %r8d, %ecx
shrl $0x2, %ecx
andl $0xff8, %ecx            # imm = 0xFF8
addl $0xf, %ecx
andl $-0x10, %ecx
shrl $0x2, %ebp
andl $0xffe, %ebp            # imm = 0xFFE
addl $0x7, %ebp
andl $-0x8, %ebp
imull %ecx, %ebp
leal 0x7c(,%rax,4), %ecx
andl $0xff80, %ecx           # imm = 0xFF80
leal 0x3e(,%rax,2), %eax
andl $0x7fc0, %eax           # imm = 0x7FC0
movq %rax, 0x50(%rsp)
shrl $0x2, %r14d
movl %r14d, 0x18(%rsp)
movq %rcx, 0x58(%rsp)
imull %ecx, %r14d
movl %r14d, 0x44(%rsp)
shrl $0x5, %r10d
movl %r10d, 0x40(%rsp)
shrl $0x5, %r11d
movl %r11d, 0x30(%rsp)
shrl $0x4, %edx
orl $0x40, %edx
movl %edx, 0x2c(%rsp)
addl $0xfff, %r13d           # imm = 0xFFF
andl $0xfffff000, %r13d      # imm = 0xFFFFF000
addl $0x1000, %r13d          # imm = 0x1000
movl %r15d, %r14d
leaq 0xc0(%rbx), %r15
subq $0x1, %r14
jb 0x558a
testl %r12d, %r12d
je 0x5584
andq $0x0, 0x18(%r15)
xorps %xmm0, %xmm0
movups %xmm0, 0x8(%r15)
movl %r13d, (%r15)
movl $0x1, 0x4(%r15)
movl (%rbx), %edi
movq %r15, %rsi
callq 0x2270
testl %eax, %eax
js 0x5935
movl (%rbx), %edi
movl (%r15), %edx
movl 0x8(%r15), %esi
callq 0x2170
addq $0x50, %r15
jmp 0x5541
movq %rbp, 0x48(%rsp)
leaq 0x1e0(%rbx), %r15
movq 0x58(%rsp), %rax
movq 0x50(%rsp), %rcx
leal (%rax,%rcx), %r13d
imull 0x18(%rsp), %r13d
addl $0xfff, %r13d           # imm = 0xFFF
andl $0xfffff000, %r13d      # imm = 0xFFFFF000
addl $0x1000, %r13d          # imm = 0x1000
movl 0x14(%rsp), %r14d
leaq 0x68(%rsp), %rbp
movq %r14, 0x18(%rsp)
subq $0x1, %r14
jb 0x5625
testl %r12d, %r12d
je 0x5609
xorps %xmm0, %xmm0
movups %xmm0, 0x10(%r15)
movups %xmm0, 0x4(%r15)
movl %r13d, (%r15)
movl (%rbx), %edi
movq %r15, %rsi
callq 0x2270
testl %eax, %eax
js 0x5941
movl (%rbx), %edi
movl (%r15), %edx
movl 0x8(%r15), %esi
callq 0x2170
movl 0x8(%r15), %eax
movl %eax, -0x8(%rbp)
addl 0x44(%rsp), %eax
movl %eax, -0x4(%rbp)
andl $0x0, (%rbp)
addq $0x20, %r15
addq $0x10, %rbp
jmp 0x55ce
testl %r12d, %r12d
movl 0x14(%rsp), %ebp
je 0x5788
leaq 0x260(%rbx), %rsi
xorps %xmm0, %xmm0
movups %xmm0, 0x270(%rbx)
movups %xmm0, 0x264(%rbx)
movl 0x40(%rsp), %eax
imull %ebp, %eax
addl $0xfff, %eax            # imm = 0xFFF
andl $0x7ffff000, %eax       # imm = 0x7FFFF000
addl $0x1000, %eax           # imm = 0x1000
movl %eax, 0x260(%rbx)
movl (%rbx), %edi
callq 0x2270
testl %eax, %eax
js 0x5a2d
movl (%rbx), %edi
movl 0x268(%rbx), %esi
movl 0x260(%rbx), %edx
callq 0x2170
leaq 0x280(%rbx), %rsi
xorps %xmm0, %xmm0
movups %xmm0, 0x284(%rbx)
movups %xmm0, 0x290(%rbx)
movl 0x30(%rsp), %eax
imull %ebp, %eax
addl $0xfff, %eax            # imm = 0xFFF
andl $0x7ffff000, %eax       # imm = 0x7FFFF000
addl $0x1000, %eax           # imm = 0x1000
movl %eax, 0x280(%rbx)
movl (%rbx), %edi
callq 0x2270
testl %eax, %eax
js 0x5a4e
movl (%rbx), %edi
movl 0x288(%rbx), %esi
movl 0x280(%rbx), %edx
callq 0x2170
leaq 0x2a0(%rbx), %rsi
xorps %xmm0, %xmm0
movups %xmm0, 0x2a4(%rbx)
movups %xmm0, 0x2b0(%rbx)
movl 0x2c(%rsp), %eax
imull %ebp, %eax
addl $0xfff, %eax            # imm = 0xFFF
andl $0x7ffff000, %eax       # imm = 0x7FFFF000
addl $0x1000, %eax           # imm = 0x1000
movl %eax, 0x2a0(%rbx)
movl (%rbx), %edi
callq 0x2270
testl %eax, %eax
js 0x5a7d
movl (%rbx), %edi
movl 0x2a8(%rbx), %esi
movl 0x2a0(%rbx), %edx
callq 0x2170
leaq 0x2c0(%rbx), %rsi
xorps %xmm0, %xmm0
movups %xmm0, 0x2c4(%rbx)
movups %xmm0, 0x2d0(%rbx)
movq 0x48(%rsp), %rax
addl $0xfff, %eax            # imm = 0xFFF
andl $0x7fff000, %eax        # imm = 0x7FFF000
addl $0x1000, %eax           # imm = 0x1000
movl %eax, 0x2c0(%rbx)
movl (%rbx), %edi
callq 0x2270
testl %eax, %eax
js 0x5a86
movl (%rbx), %edi
movl 0x2c8(%rbx), %esi
movl 0x2c0(%rbx), %edx
callq 0x2170
movl (%rbx), %edi
movl %edi, %edx
orl $0x10000, %edx          # imm = 0x10000
movl $0x108, %esi            # imm = 0x108
callq 0x2160
movl (%rbx), %edi
movl 0x48(%rbx), %edx
movl $0x138, %esi            # imm = 0x138
callq 0x2160
movl (%rbx), %edi
movl 0x40(%rbx), %edx
movl $0x13c, %esi            # imm = 0x13C
callq 0x2160
movl (%rbx), %edi
xorl %r14d, %r14d
movl $0x140, %esi            # imm = 0x140
xorl %edx, %edx
callq 0x2160
decl %ebp
movq 0x58(%rsp), %rdx
shll $0x10, %edx
addl 0x50(%rsp), %edx
movl (%rbx), %edi
movl $0x154, %esi            # imm = 0x154
callq 0x2160
movl 0x38(%rsp), %edx
andl $0xffe0, %edx           # imm = 0xFFE0
movl (%rbx), %edi
movl $0x120, %esi            # imm = 0x120
callq 0x2160
movl (%rbx), %edi
movl 0xc(%rbx), %eax
shll $0x10, %eax
addl $0x1f0000, %eax         # imm = 0x1F0000
andl $0xffe00000, %eax       # imm = 0xFFE00000
movl 0x10(%rbx), %edx
addl $0x7, %edx
andl $-0x8, %edx
orl %eax, %edx
movl $0x124, %esi            # imm = 0x124
callq 0x2160
movl (%rbx), %edi
movl $0x10c, %esi            # imm = 0x10C
movl $0xcf0018, %edx         # imm = 0xCF0018
callq 0x2160
movl (%rbx), %edi
movl $0x128, %esi            # imm = 0x128
movl %ebp, %edx
callq 0x2160
movl 0x34(%rsp), %ecx
shrl $0x6, %ecx
movq 0x20(%rsp), %rax
shrl $0x6, %eax
imull %ecx, %eax
shll $0x8, %eax
andl $0xfffff00, %eax        # imm = 0xFFFFF00
orl $0x40, %eax
movq %rax, 0x20(%rsp)
movl 0xc(%rsp), %ecx
shrl $0x8, %ecx
movl 0x3c(%rsp), %edx
shrl $0x4, %edx
imull %edx, %ecx
shll $0x7, %ecx
movl $0x7ffff80, %eax        # imm = 0x7FFFF80
andl %eax, %ecx
movl %ecx, 0xc(%rsp)
movl 0x10(%rsp), %ecx
shrl $0x8, %ecx
imull %edx, %ecx
shll $0x7, %ecx
andl %eax, %ecx
movl %ecx, 0x10(%rsp)
shlq $0x4, 0x18(%rsp)
movl $0x1e0, %ebp            # imm = 0x1E0
xorl %r15d, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
movl (%rbx), %edi
cmpq %r14, 0x18(%rsp)
je 0x594d
movl 0x60(%rsp,%r14), %edx
leal 0x160(%r14), %esi
callq 0x2160
movl (%rbx), %edi
movl 0x64(%rsp,%r14), %edx
leal 0x164(%r14), %esi
callq 0x2160
movl (%rbx), %edi
movl 0x268(%rbx), %edx
addl %r15d, %edx
leal 0x168(%r14), %esi
callq 0x2160
movl (%rbx), %edi
movl 0x288(%rbx), %edx
addl %r12d, %edx
leal 0x16c(%r14), %esi
callq 0x2160
movl (%rbx), %edi
movl 0x2a8(%rbx), %edx
addl %r13d, %edx
movl %ebp, %esi
callq 0x2160
addl $0x4, %ebp
addl 0x20(%rsp), %r13d
addl 0xc(%rsp), %r12d
addl 0x10(%rsp), %r15d
addq $0x10, %r14
jmp 0x58a9
leaq 0x26928(%rip), %rdi     # 0x2c264
jmp 0x5a8d
leaq 0x268e8(%rip), %rdi     # 0x2c230
jmp 0x5a8d
movl 0x2c8(%rbx), %edx
movl $0x158, %esi            # imm = 0x158
callq 0x2160
movl (%rbx), %edi
movl $0x15c, %esi            # imm = 0x15C
movq 0x48(%rsp), %rdx
callq 0x2160
movl (%rbx), %edi
pushq $0x70
popq %r14
pushq $0x1
popq %rbp
movl %r14d, %esi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x104, %esi            # imm = 0x104
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x10
popq %rdx
movl $0x100, %esi            # imm = 0x100
callq 0x2160
movl (%rbx), %edi
pushq $0x38
popq %rsi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl %r14d, %esi
callq 0x2210
movl (%rbx), %edi
movl $0x1388, %esi           # imm = 0x1388
callq 0x2360
cmpl $-0x1, %eax
je 0x5a36
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
testl %eax, %eax
je 0x5a57
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x1d8, %esi            # imm = 0x1D8
callq 0x2210
movl (%rbx), %edi
movl $0x1cc, %esi            # imm = 0x1CC
callq 0x2210
jmp 0x5a9d
leaq 0x267c0(%rip), %rdi     # 0x2c1f4
jmp 0x5a8d
leaq 0x266e0(%rip), %rdi     # 0x2c11d
callq 0x2290
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x24
jmp 0x5a9c
leaq 0x26763(%rip), %rdi     # 0x2c1b8
jmp 0x5a8d
movl $0x114, %esi            # imm = 0x114
callq 0x2210
leaq 0x26461(%rip), %rdi     # 0x2bec9
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x25
jmp 0x5a9c
leaq 0x266fc(%rip), %rdi     # 0x2c180
jmp 0x5a8d
leaq 0x266b8(%rip), %rdi     # 0x2c145
callq 0x2290
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x1
popq %rbp
movl %ebp, %eax
addq $0x268, %rsp            # imm = 0x268
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq