// File: /workspace/github_cpp_makefile_star2_O1/akshayrajput[P]ARMV8_Simulator/./SUBS.cpp
// Function: SUBS()
void SUBS()
{
    int sf = IR.getLowerData() & 0x80000000;
    int op = IR.getLowerData() & 0x40000000;
    int S =  IR.getLowerData() & 0x20000000;
    int mod = (IR.getLowerData() & 0x1f000000) >> 24;
    int shift = (IR.getLowerData() & 0x00c00000) >> 22;
    int imm12 = (IR.getLowerData() & 0x003ffc00) >>10;
    int imm6 = (IR.getLowerData() & 0x0000fc00) >>10;
    int rm = (IR.getLowerData() & 0x001f0000) >> 16;
    int rn = (IR.getLowerData() & 0x000003e0) >> 5;
    int rd = (IR.getLowerData() & 0x0000001f);
    bool sub_op = false;
    uint64_t imm;
    int amount =1;

    if(rd == 31)
    {
	    CMP();
	    return;
    }	
    if(op)  sub_op = true;

    printf("[log] - SUBS instruction\n");

    if(shift == 0)
    {
        if (sf)
        {
             imm = (uint64_t)imm12;
        }
        else
        {
             imm = imm12;
        }
    }
    
    else if(shift == 1)
    {
        if(sf)
        {
            imm = (uint64_t)imm12;
            imm = imm << 12;
        }
        else
        {
            imm = imm12;
            imm = imm << 12;
        }
    }
    bool setFlag = false;
    if(S == 1) setFlag = true;
    if(mod == 17) // SUBS immediate
    {
	printf("[log]- SUBS immediate\n");
        if(sf)  //64 bit
        {
            int carry = 0;
            if(sub_op)
            {
                imm = ~imm;
                carry = 1;   
            }
            uint64_t rn_data = R[rn].getData();
            uint64_t dat = rn_data + imm + carry;
            
            
                if(rn_data > 0 && imm < 0 && dat < 0)
                    OFLAG = true;
                
                if(rn_data < 0 && imm > 0 && dat > 0)
                    OFLAG = true;
                
                ZFLAG = (dat == 0);
                NFLAG = (dat < 0);
                
                CFLAG = rn_data > (0xffffffffffffffff - (imm + carry));
                
            if(rd == 31 && !S)
                R[31].setData(dat);
            else
                R[rd].setData(dat);
        }
        
        else//32 bit
        {
            int carry = 0;
            if(sub_op)
            {
                imm = ~imm;
                carry = 1;   
            }
            
            int rn_data = R[rn].getLowerData();
            int dat = rn_data + imm + carry;
            
            
            if(rn_data > 0 && imm < 0 && dat < 0)
                OFLAG = true;
            
            if(rn_data < 0 && imm > 0 && dat > 0)
                OFLAG = true;
             
            
            if(dat == 0)
                ZFLAG = true;
            
            if(dat < 0)
                NFLAG = true;
            
            CFLAG = rn_data > (0xffffffff - (imm + carry));
            
            if(rd == 31 && !S)
                R[31].setLowerData(dat);
            else
                R[rd].setLowerData(dat);
        }
    }
    
    if(mod == 11)   //shifted register
    {
	printf("[log]- SUBS register\n");
        if(sf)      //64 bit registers
        {
            uint64_t op1 = R[rn].getData();
            
            uint64_t op2 = R[rm].getData();
            if(shift == 0)
                op2 = op2 << amount;
            else if(shift == 1 && shift == 2)
                op2 = op2 >> amount;
            uint64_t carry = 0;
            if(sub_op)
            {
                op2 = ~op2;
                carry = 1;
            }
            
            uint64_t dat = op1 + op2 + carry;
            if(rd == 31 && !S)
                R[31].setData(dat);
            else
                R[rd].setData(dat);
           
            if(op1 > 0 && op2 < 0 && dat < 0)
	    {
                OFLAG = true;
		printf("[log] -Carry flag set \n");

            }
            if(op1 < 0 && op2 > 0 && dat > 0)
	    {
                OFLAG = true;
		printf("[log] -Overflow flag set \n");

            }

            if(dat == 0)
	    {
                ZFLAG = true;
		printf("[log] -Zero flag set \n");
	    }
            
            if(dat < 0)
	    {
                NFLAG = true;
		printf("[log] -Negative flag set \n");
	    }
                
            CFLAG = op1 > (0xffffffffffffffff - (op2 + carry));
	    if(CFLAG)
		    printf("[log] -Carry flag set \n");

        }
       
        else     //32 bit registers
        {
            int op1 = R[rn].getLowerData();
            
            int op2 = R[rm].getLowerData();
            if(shift == 0)
                op2 = op2 << amount;
            else if(shift == 1 && shift == 2)
                op2 = op2 >> amount;
            int carry = 0;
            if(sub_op)
            {
                op2 = ~op2;
                carry = 1;
            }
            
            int dat = op1 + op2 + carry;
            if(rd == 31 && !S)
                R[31].setLowerData(dat);
            else
                R[rd].setLowerData(dat);
           
            if(op1 > 0 && op2 < 0 && dat < 0)
	    {
                OFLAG = true;
		printf("[log] -Carry flag set \n");

            }
            if(op1 < 0 && op2 > 0 && dat > 0 )
	    {
                OFLAG = true;
		printf("[log] - Overflow flag set \n");

            }
            ZFLAG = (dat == 0);
	    if(ZFLAG)
		    printf("[log] - Zero flag set\n");
            NFLAG = (dat < 0); 
	    if(NFLAG)
                printf("[log] - Negative flag set\n");
 
            CFLAG = op1 > (0xffffffff - (op2 + carry));
            if(CFLAG)
		    printf("[log] - Carry flag set \n");
        }
       
    }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
leaq 0x17989(%rip), %rbp     # 0x1a1f0
movq %rbp, %rdi
callq 0x5c8a
movl %eax, 0xc(%rsp)
movq %rbp, %rdi
callq 0x5c8a
movl %eax, %ebx
movq %rbp, %rdi
callq 0x5c8a
movq %rbp, %rdi
callq 0x5c8a
movl %eax, %r13d
movq %rbp, %rdi
callq 0x5c8a
movl %eax, %r15d
movq %rbp, %rdi
callq 0x5c8a
movl %eax, %r12d
movq %rbp, %rdi
callq 0x5c8a
movq %rbp, %rdi
callq 0x5c8a
movl %eax, 0x14(%rsp)
movq %rbp, %rdi
callq 0x5c8a
movl %eax, %r14d
movq %rbp, %rdi
callq 0x5c8a
movl %eax, %ebp
andl $0x1f, %ebp
cmpl $0x1f, %ebp
jne 0x28ea
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1f8b
shrl $0x18, %r13d
andl $0x1f, %r13d
shrl $0x16, %r15d
andl $0x3, %r15d
shrl $0xa, %r12d
andl $0xfff, %r12d           # imm = 0xFFF
shrl $0x5, %r14d
leaq 0x3de2(%rip), %rdi      # 0x66f2
callq 0x1140
testl %r15d, %r15d
je 0x2926
cmpl $0x1, %r15d
jne 0x2929
shll $0xc, %r12d
jmp 0x2929
movl %r12d, %r12d
andl $0x1f, %r14d
andl $0x40000000, %ebx       # imm = 0x40000000
cmpl $0xb, %r13d
je 0x2a45
cmpl $0x11, %r13d
jne 0x2bda
leaq 0x3dbd(%rip), %rdi      # 0x670b
callq 0x1140
movl %ebx, %edx
shrl $0x1e, %ebx
btl $0x1f, 0xc(%rsp)
movl %edx, 0x10(%rsp)
jb 0x29ef
xorl %ecx, %ecx
movl %edx, %eax
negl %eax
sbbq %rcx, %rcx
movq %r12, %rax
movq %rcx, 0x18(%rsp)
xorq %rcx, %rax
movq %rax, 0x20(%rsp)
movl %r14d, %eax
leaq 0x7765(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
callq 0x5c8a
movq 0x20(%rsp), %rcx
leal (%rbx,%rcx), %esi
addl %eax, %esi
testl %eax, %eax
jns 0x29b4
cmpq 0x18(%rsp), %r12
je 0x29b4
testl %esi, %esi
jle 0x29b4
movb $0x1, 0x772e(%rip)      # 0xa0e2
testl %esi, %esi
jne 0x29bf
movb $0x1, 0x7722(%rip)      # 0xa0e1
cltq
testl %esi, %esi
jns 0x29cc
movb $0x1, 0x7717(%rip)      # 0xa0e3
notl %ebx
subq %rcx, %rbx
cmpq %rax, %rbx
setb 0x7709(%rip)            # 0xa0e4
movl %ebp, %eax
leaq 0x770c(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
callq 0x5c94
jmp 0x2a37
movl %ebx, %eax
xorl %ecx, %ecx
negl %edx
sbbq %rcx, %rcx
xorq %rcx, %r12
addq %rax, %r12
movl %r14d, %eax
leaq 0x76e8(%rip), %rbx      # 0xa0f0
leaq (%rbx,%rax,8), %rdi
callq 0x5c86
addq %rax, %r12
sete 0x76c6(%rip)            # 0xa0e1
setb 0x76c2(%rip)            # 0xa0e4
movb $0x0, 0x76ba(%rip)      # 0xa0e3
movl %ebp, %eax
leaq (%rbx,%rax,8), %rdi
movq %r12, %rsi
callq 0x5c8e
cmpl $0xb, %r13d
movl 0x10(%rsp), %ebx
jne 0x2bda
movl 0x14(%rsp), %r12d
shrl $0x10, %r12d
andl $0x1f, %r12d
leaq 0x3cc8(%rip), %rdi      # 0x6721
callq 0x1140
movl %ebx, %r13d
shrl $0x1e, %r13d
btl $0x1f, 0xc(%rsp)
movl %r14d, %eax
leaq 0x767b(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
movl %r12d, %eax
leaq (%rcx,%rax,8), %r12
jb 0x2b56
testl %r15d, %r15d
sete %r15b
callq 0x5c8a
movl %eax, %r14d
movq %r12, %rdi
callq 0x5c8a
movl %r15d, %ecx
shll %cl, %eax
xorl %r15d, %r15d
negl %ebx
sbbl %r15d, %r15d
xorl %eax, %r15d
leal (%r14,%r13), %ebx
addl %r15d, %ebx
movl %ebp, %eax
leaq 0x7633(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
movl %ebx, %esi
callq 0x5c94
testl %r14d, %r14d
jle 0x2ae7
movl %ebx, %eax
andl %r15d, %eax
jns 0x2ae7
movb $0x1, 0x7607(%rip)      # 0xa0e2
leaq 0x3ccd(%rip), %rdi      # 0x67af
callq 0x1140
testl %r14d, %r14d
jns 0x2b08
testl %r15d, %r15d
jle 0x2b08
testl %ebx, %ebx
jle 0x2b08
movb $0x1, 0x75e6(%rip)      # 0xa0e2
leaq 0x3c33(%rip), %rdi      # 0x6736
callq 0x1140
testl %ebx, %ebx
sete 0x75d0(%rip)            # 0xa0e1
jne 0x2b1f
leaq 0x3c37(%rip), %rdi      # 0x6751
callq 0x1140
movl %ebx, %eax
shrl $0x1f, %eax
movb %al, 0x75b9(%rip)       # 0xa0e3
testl %ebx, %ebx
jns 0x2b3a
leaq 0x3c32(%rip), %rdi      # 0x6767
callq 0x1140
addl %r13d, %r15d
addl %r14d, %r15d
setb 0x759d(%rip)            # 0xa0e4
jae 0x2bda
leaq 0x3c2d(%rip), %rdi      # 0x6781
jmp 0x2bc7
testl %r15d, %r15d
sete %r15b
callq 0x5c86
movq %rax, %r14
movq %r12, %rdi
callq 0x5c86
movl %r15d, %ecx
shlq %cl, %rax
xorl %ecx, %ecx
negl %ebx
sbbq %rcx, %rcx
xorq %rax, %rcx
movl %r13d, %ebx
addq %rcx, %rbx
movl %ebp, %eax
leaq 0x7564(%rip), %rcx      # 0xa0f0
leaq (%rcx,%rax,8), %rdi
leaq (%rbx,%r14), %rsi
callq 0x5c8e
movq %rbx, %rax
addq %r14, %rax
jne 0x2bb4
movb $0x1, 0x7539(%rip)      # 0xa0e1
leaq 0x3bea(%rip), %rdi      # 0x6799
callq 0x1140
addq %r14, %rbx
setb 0x7526(%rip)            # 0xa0e4
jae 0x2bda
leaq 0x3be8(%rip), %rdi      # 0x67af
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1140
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq