// File: /workspace/github_cpp_makefile_star2_O1/Lupo-CalPoly[P]cpe315-thumbsim/execute.cpp
// Function: execute()
void execute() {
  Data16 instr = imem[PC];
  Data16 instr2;
  Data32 temp(0); // Use this for STRB instructions
  Thumb_Types itype;
  // the following counts as a read to PC
  unsigned int pctarget = PC + 2;
  unsigned int addr;
  int i, n, offset;
  unsigned int list, mask;
  int num1, num2, result, BitCount;
  unsigned int bit;

  /* Convert instruction to correct type */
  /* Types are described in Section A5 of the armv7 manual */
  BL_Type blupper(instr);
  ALU_Type alu(instr);
  SP_Type sp(instr);
  DP_Type dp(instr);
  LD_ST_Type ld_st(instr);
  MISC_Type misc(instr);
  COND_Type cond(instr);
  UNCOND_Type uncond(instr);
  LDM_Type ldm(instr);
  STM_Type stm(instr);
  LDRL_Type ldrl(instr);
  ADD_SP_Type addsp(instr);

  BL_Ops bl_ops;
  ALU_Ops add_ops;
  DP_Ops dp_ops;
  SP_Ops sp_ops;
  LD_ST_Ops ldst_ops;
  MISC_Ops misc_ops;

  // This counts as a write to the PC register
  rf.write(PC_REG, pctarget);

  itype = decode(ALL_Types(instr));

  // CPE 315: The bulk of your work is in the following switch statement
  // All instructions will need to have stats and cache access info added
  // as appropriate for that instruction.
  switch(itype) {
    case ALU:
      add_ops = decode(alu);
      switch(add_ops) {
        case ALU_LSLI:
          break;
        case ALU_ADDR:
          // needs stats and flags
          rf.write(alu.instr.addr.rd, rf[alu.instr.addr.rn] + rf[alu.instr.addr.rm]);
          break;
        case ALU_SUBR:
          break;
        case ALU_ADD3I:
          // needs stats and flags
          rf.write(alu.instr.add3i.rd, rf[alu.instr.add3i.rn] + alu.instr.add3i.imm);
          break;
        case ALU_SUB3I:
          break;
        case ALU_MOV:
          // needs stats and flags
          rf.write(alu.instr.mov.rdn, alu.instr.mov.imm);
          break;
        case ALU_CMP:
          break;
        case ALU_ADD8I:
          // needs stats and flags
          rf.write(alu.instr.add8i.rdn, rf[alu.instr.add8i.rdn] + alu.instr.add8i.imm);
          break;
        case ALU_SUB8I:
          break;
        default:
          cout << "instruction not implemented" << endl;
          exit(1);
          break;
      }
      break;
    case BL: 
      // This instruction is complete, nothing needed here
      bl_ops = decode(blupper);
      if (bl_ops == BL_UPPER) {
        // PC has already been incremented above
        instr2 = imem[PC];
        BL_Type bllower(instr2);
        if (blupper.instr.bl_upper.s) {
          addr = static_cast<unsigned int>(0xff<<24) | 
            ((~(bllower.instr.bl_lower.j1 ^ blupper.instr.bl_upper.s))<<23) |
            ((~(bllower.instr.bl_lower.j2 ^ blupper.instr.bl_upper.s))<<22) |
            ((blupper.instr.bl_upper.imm10)<<12) |
            ((bllower.instr.bl_lower.imm11)<<1);
        }
        else {
          addr = ((blupper.instr.bl_upper.imm10)<<12) |
            ((bllower.instr.bl_lower.imm11)<<1);
        }
        // return address is 4-bytes away from the start of the BL insn
        rf.write(LR_REG, PC + 2);
        // Target address is also computed from that point
        rf.write(PC_REG, PC + 2 + addr);

        stats.numRegReads += 1;
        stats.numRegWrites += 2; 
      }
      else {
        cerr << "Bad BL format." << endl;
        exit(1);
      }
      break;
    case DP:
      dp_ops = decode(dp);
      switch(dp_ops) {
        case DP_CMP:
          // need to implement
          break;
      }
      break;
    case SPECIAL:
      sp_ops = decode(sp);
      switch(sp_ops) {
        case SP_MOV:
          // needs stats and flags
          rf.write((sp.instr.mov.d << 3 ) | sp.instr.mov.rd, rf[sp.instr.mov.rm]);
          break;
        case SP_ADD:
          break;
        case SP_CMP:
          // need to implement these
          break;
      }
      break;
    case LD_ST:
      // You'll want to use these load and store models
      // to implement ldrb/strb, ldm/stm and push/pop
      ldst_ops = decode(ld_st);
      switch(ldst_ops) {
        case STRI:
          // functionally complete, needs stats
          addr = rf[ld_st.instr.ld_st_imm.rn] + ld_st.instr.ld_st_imm.imm * 4;
          dmem.write(addr, rf[ld_st.instr.ld_st_imm.rt]);
          break;
        case LDRI:
          // functionally complete, needs stats
          addr = rf[ld_st.instr.ld_st_imm.rn] + ld_st.instr.ld_st_imm.imm * 4;
          rf.write(ld_st.instr.ld_st_imm.rt, dmem[addr]);
          break;
        case STRR:
          // need to implement
          break;
        case LDRR:
          // need to implement
          break;
        case STRBI:
          // functionally complete, needs stats
          addr = rf[ld_st.instr.ld_st_imm.rn] + ld_st.instr.ld_st_imm.imm;
          temp = dmem[addr];
          temp.set_data_ubyte4(0, rf[ld_st.instr.ld_st_imm.rt]&0xFF);
          dmem.write(addr, temp);
          break;
        case LDRBI:
          // need to implement
          break;
        case STRBR:
          // need to implement
          break;
        case LDRBR:
          // need to implement
          break;
      }
      break;
    case MISC:
      misc_ops = decode(misc);
      switch(misc_ops) {
        case MISC_PUSH:
          // need to implement
          break;
        case MISC_POP:
          // need to implement
          break;
        case MISC_SUB:
          // functionally complete, needs stats
          rf.write(SP_REG, SP - (misc.instr.sub.imm*4));
          break;
        case MISC_ADD:
          // functionally complete, needs stats
          rf.write(SP_REG, SP + (misc.instr.add.imm*4));
          break;
      }
      break;
    case COND:
      decode(cond);
      // Once you've completed the checkCondition function,
      // this should work for all your conditional branches.
      // needs stats
      if (checkCondition(cond.instr.b.cond)){
        rf.write(PC_REG, PC + 2 * signExtend8to32ui(cond.instr.b.imm) + 2);
      }
      break;
    case UNCOND:
      // Essentially the same as the conditional branches, but with no
      // condition check, and an 11-bit immediate field
      decode(uncond);
      break;
    case LDM:
      decode(ldm);
      // need to implement
      break;
    case STM:
      decode(stm);
      // need to implement
      break;
    case LDRL:
      // This instruction is complete, nothing needed
      decode(ldrl);
      // Need to check for alignment by 4
      if (PC & 2) {
        addr = PC + 2 + (ldrl.instr.ldrl.imm)*4;
      }
      else {
        addr = PC + (ldrl.instr.ldrl.imm)*4;
      }
      // Requires two consecutive imem locations pieced together
      temp = imem[addr] | (imem[addr+2]<<16);  // temp is a Data32
      rf.write(ldrl.instr.ldrl.rt, temp);

      // One write for updated reg
      stats.numRegWrites++;
      // One read of the PC
      stats.numRegReads++;
      // One mem read, even though it's imem, and there's two of them
      stats.numMemReads++;
      break;
    case ADD_SP:
      // needs stats
      decode(addsp);
      rf.write(addsp.instr.add.rd, SP + (addsp.instr.add.imm*4));
      break;
    default:
      cout << "[ERROR] Unknown Instruction to be executed" << endl;
      exit(1);
      break;
  }
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
leaq 0x39f2(%rip), %r14      # 0x91a8
movq %r14, %rdi
movl $0xf, %esi
callq 0x46ec
leaq 0x398e(%rip), %rdi      # 0x9158
movl %eax, %esi
callq 0x46d8
movl %eax, %ebx
movq %r14, %rdi
movl $0xf, %esi
callq 0x46ec
leal 0x2(%rax), %edx
movq %r14, %rdi
movl $0xf, %esi
callq 0x4694
movl %ebx, %edi
callq 0x3028
cmpl $0xb, %eax
ja 0x5d07
movl %eax, %eax
leaq 0xc93(%rip), %rcx       # 0x649c
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl %ebx, %edi
callq 0x3106
cmpl $0xa, %eax
ja 0x5d3c
movl %eax, %eax
leaq 0xca1(%rip), %rcx       # 0x64cc
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl %ebx, %r14d
andl $0x7, %r14d
movl %ebx, %esi
shrl $0x3, %esi
andl $0x7, %esi
leaq 0x395e(%rip), %r15      # 0x91a8
movq %r15, %rdi
callq 0x46ec
movl %eax, %r12d
shrl $0x6, %ebx
andl $0x7, %ebx
movq %r15, %rdi
movl %ebx, %esi
callq 0x46ec
addl %eax, %r12d
movq %r15, %rdi
movl %r14d, %esi
movl %r12d, %edx
jmp 0x5c13
movl %ebx, %edi
callq 0x4298
testl %eax, %eax
jne 0x5d17
leaq 0x391c(%rip), %rdi      # 0x91a8
movl $0xf, %esi
callq 0x46ec
leaq 0x38bb(%rip), %rdi      # 0x9158
movl %eax, %esi
callq 0x46d8
btl $0xa, %ebx
jb 0x5b31
andl $0x3ff, %ebx            # imm = 0x3FF
shll $0xc, %ebx
andl $0x7ff, %eax            # imm = 0x7FF
leal (%rbx,%rax,2), %r14d
jmp 0x5b57
movl %ebx, %edi
callq 0x39d0
testl %eax, %eax
je 0x5bb8
cmpl $0x1, %eax
jne 0x5ba9
leaq 0x38c4(%rip), %r14      # 0x91a8
movq %r14, %rdi
movl $0xd, %esi
callq 0x46ec
andl $0x7f, %ebx
shll $0x2, %ebx
subl %ebx, %eax
movq %r14, %rdi
movl $0xd, %esi
jmp 0x5c11
movl %ebx, %edi
callq 0x4338
leaq 0x3894(%rip), %r14      # 0x91a8
movq %r14, %rdi
movl $0xf, %esi
callq 0x46ec
movl %eax, %r15d
movq %r14, %rdi
movl $0xf, %esi
callq 0x46ec
movl %eax, %r12d
movzbl %bl, %eax
andl $0x2, %r15d
leal (%r15,%rax,4), %r14d
leal (%r12,%r14), %esi
leaq 0x380e(%rip), %r15      # 0x9158
movq %r15, %rdi
callq 0x46d8
movzwl %ax, %r13d
leal (%r12,%r14), %esi
addl $0x2, %esi
movq %r15, %rdi
callq 0x46d8
shll $0x10, %eax
shrl $0x8, %ebx
andl $0x7, %ebx
movl %eax, %ecx
andl $0xff000000, %ecx       # imm = 0xFF000000
andl $0xff0000, %eax         # imm = 0xFF0000
orl %eax, %r13d
orl %ecx, %r13d
leaq 0x3820(%rip), %rdi      # 0x91a8
movl %ebx, %esi
movl %r13d, %edx
callq 0x4694
incl 0x3860(%rip)            # 0x91f8
incl 0x385e(%rip)            # 0x91fc
incl 0x384c(%rip)            # 0x91f0
jmp 0x5ba9
movl %ebx, %edi
callq 0x3409
cmpl $0x2, %eax
jne 0x5ba9
movl %ebx, %eax
shrl $0x4, %eax
andl $0x8, %eax
movl %ebx, %r14d
andl $0x7, %r14d
orl %eax, %r14d
shrl $0x3, %ebx
andl $0xf, %ebx
leaq 0x37d0(%rip), %r15      # 0x91a8
movq %r15, %rdi
movl %ebx, %esi
callq 0x46ec
movq %r15, %rdi
movl %r14d, %esi
jmp 0x5c11
movl %ebx, %edi
callq 0x3671
cmpl $0xa, %eax
je 0x5c26
cmpl $0x9, %eax
je 0x5bdc
cmpl $0x8, %eax
jne 0x5ba9
movl %ebx, %esi
shrl $0x3, %esi
andl $0x7, %esi
leaq 0x378a(%rip), %r14      # 0x91a8
movq %r14, %rdi
callq 0x46ec
movl %ebx, %r15d
shrl $0x4, %r15d
andl $0x7c, %r15d
addl %eax, %r15d
andl $0x7, %ebx
movq %r14, %rdi
movl %ebx, %esi
callq 0x46ec
leaq 0x3738(%rip), %rdi      # 0x9180
movl %r15d, %esi
movl %eax, %edx
jmp 0x5c83
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x4322
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x33cc
movl %ebx, %edi
callq 0x400d
movl %ebx, %eax
shrl $0x8, %eax
andl $0xf, %eax
cmpw $0xe, %ax
je 0x5aa6
testl %eax, %eax
jne 0x5ba9
cmpb $0x1, 0x3791(%rip)      # 0x9231
jne 0x5ba9
leaq 0x36fb(%rip), %r14      # 0x91a8
movq %r14, %rdi
movl $0xf, %esi
callq 0x46ec
movsbl %bl, %ecx
leal (%rax,%rcx,2), %edx
addl $0x2, %edx
movq %r14, %rdi
movl $0xf, %esi
jmp 0x5c13
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x41f6
movl %ebx, %edi
callq 0x4343
movl %ebx, %r14d
shrl $0x8, %r14d
andl $0x7, %r14d
leaq 0x36aa(%rip), %r15      # 0x91a8
movq %r15, %rdi
movl $0xd, %esi
callq 0x46ec
movzbl %bl, %ecx
leal (%rax,%rcx,4), %edx
movq %r15, %rdi
movl %r14d, %esi
jmp 0x5c13
movl %ebx, %edi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x432d
movl %eax, %ecx
shll $0xb, %ecx
andl $0x7c00000, %ecx        # imm = 0x7C00000
andl $0x3ff, %ebx            # imm = 0x3FF
shll $0xc, %ebx
orl %ecx, %ebx
andl $0x7ff, %eax            # imm = 0x7FF
leal (%rbx,%rax,2), %r14d
orl $0xff800000, %r14d      # imm = 0xFF800000
leaq 0x364a(%rip), %rbx      # 0x91a8
movq %rbx, %rdi
movl $0xf, %esi
callq 0x46ec
leal 0x2(%rax), %edx
movq %rbx, %rdi
movl $0xe, %esi
callq 0x4694
movq %rbx, %rdi
movl $0xf, %esi
callq 0x46ec
leal (%r14,%rax), %edx
addl $0x2, %edx
movq %rbx, %rdi
movl $0xf, %esi
callq 0x4694
incl 0x365a(%rip)            # 0x91fc
addl $0x2, 0x364f(%rip)      # 0x91f8
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x35e9(%rip), %r14      # 0x91a8
movq %r14, %rdi
movl $0xd, %esi
callq 0x46ec
andl $0x7f, %ebx
leal (%rax,%rbx,4), %edx
movq %r14, %rdi
movl $0xd, %esi
jmp 0x5c13
movl %ebx, %esi
shrl $0x3, %esi
andl $0x7, %esi
leaq 0x35bd(%rip), %r14      # 0x91a8
movq %r14, %rdi
callq 0x46ec
movl %ebx, %esi
shrl $0x4, %esi
andl $0x7c, %esi
addl %eax, %esi
andl $0x7, %ebx
leaq 0x3579(%rip), %rdi      # 0x9180
callq 0x46a4
movq %r14, %rdi
movl %ebx, %esi
movl %eax, %edx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x4694
movl %ebx, %esi
shrl $0x3, %esi
andl $0x7, %esi
leaq 0x3573(%rip), %r14      # 0x91a8
movq %r14, %rdi
callq 0x46ec
movl %ebx, %r15d
shrl $0x6, %r15d
andl $0x1f, %r15d
addl %eax, %r15d
leaq 0x352e(%rip), %r12      # 0x9180
movq %r12, %rdi
movl %r15d, %esi
callq 0x46a4
movl %eax, %r13d
andl $0x7, %ebx
movq %r14, %rdi
movl %ebx, %esi
callq 0x46ec
shll $0x18, %eax
andl $0xffffff, %r13d        # imm = 0xFFFFFF
orl %eax, %r13d
movq %r12, %rdi
movl %r15d, %esi
movl %r13d, %edx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x43e4
movl %ebx, %r14d
andl $0x7, %r14d
movl %ebx, %esi
shrl $0x3, %esi
andl $0x7, %esi
leaq 0x34fc(%rip), %r15      # 0x91a8
movq %r15, %rdi
callq 0x46ec
shrl $0x6, %ebx
andl $0x7, %ebx
addl %eax, %ebx
movq %r15, %rdi
movl %r14d, %esi
movl %ebx, %edx
jmp 0x5c13
movl %ebx, %r14d
shrl $0x8, %r14d
andl $0x7, %r14d
leaq 0x34cd(%rip), %r15      # 0x91a8
movq %r15, %rdi
movl %r14d, %esi
callq 0x46ec
movzbl %bl, %edx
addl %eax, %edx
jmp 0x5b11
movl %ebx, %esi
shrl $0x8, %esi
andl $0x7, %esi
movzbl %bl, %edx
leaq 0x34a6(%rip), %rdi      # 0x91a8
jmp 0x5c13
movq 0x32c2(%rip), %rdi      # 0x8fd0
leaq 0x839(%rip), %rsi       # 0x654e
jmp 0x5d25
movq 0x32d2(%rip), %rdi      # 0x8ff0
leaq 0x81a(%rip), %rsi       # 0x653f
callq 0x2130
movq %rax, %rdi
callq 0x2090
movl $0x1, %edi
callq 0x2180
movq 0x328d(%rip), %rdi      # 0x8fd0
leaq 0x7d9(%rip), %rsi       # 0x6523
jmp 0x5d25