// File: /workspace/github_cpp_makefile_star2_O3/NishadSaraf[P]Championship-Simulator/src/cache.cc
// Function: CACHE::handle_fill()
void CACHE::handle_fill()
{
    // handle fill
    uint32_t fill_cpu = (MSHR.next_fill_index == MSHR_SIZE) ? NUM_CPUS : MSHR.entry[MSHR.next_fill_index].cpu;
    if (fill_cpu == NUM_CPUS)
        return;

    if (MSHR.next_fill_cycle <= current_core_cycle[fill_cpu]) {

#ifdef SANITY_CHECK
        if (MSHR.next_fill_index >= MSHR.SIZE)
            assert(0);
#endif

        uint32_t mshr_index = MSHR.next_fill_index;

        // find victim
        uint32_t set = get_set(MSHR.entry[mshr_index].address), way;
        if (cache_type == IS_LLC) {
            way = llc_find_victim(fill_cpu, MSHR.entry[mshr_index].instr_id, set, block[set], MSHR.entry[mshr_index].ip, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].type);
        }
        else
            way = find_victim(fill_cpu, MSHR.entry[mshr_index].instr_id, set, block[set], MSHR.entry[mshr_index].ip, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].type);

#ifdef LLC_BYPASS
        if ((cache_type == IS_LLC) && (way == LLC_WAY)) { // this is a bypass that does not fill the LLC

            // update replacement policy
            if (cache_type == IS_LLC) {
                llc_update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, 0, MSHR.entry[mshr_index].type, 0);

            }
            else
                update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, 0, MSHR.entry[mshr_index].type, 0);

            // COLLECT STATS
            sim_miss[fill_cpu][MSHR.entry[mshr_index].type]++;
            sim_access[fill_cpu][MSHR.entry[mshr_index].type]++;

            // check fill level
            if (MSHR.entry[mshr_index].fill_level < fill_level) {

                if (MSHR.entry[mshr_index].instruction) 
                    upper_level_icache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
                else // data
                    upper_level_dcache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
            }

            MSHR.remove_queue(&MSHR.entry[mshr_index]);
            MSHR.num_returned--;

            update_fill_cycle();

            return; // return here, no need to process further in this function
        }
#endif

        uint8_t  do_fill = 1;

        // is this dirty?
        if (block[set][way].dirty) {

            // check if the lower level WQ has enough room to keep this writeback request
            if (lower_level) {
                if (lower_level->get_occupancy(2) == lower_level->get_size(2)) {

                    // lower level WQ is full, cannot replace this victim
                    do_fill = 0;
                    lower_level->increment_WQ_FULL();
                    STALL[MSHR.entry[mshr_index].type]++;

                    DP ( if (warmup_complete[fill_cpu]) {
                    cout << "[" << NAME << "] " << __func__ << "do_fill: " << +do_fill;
                    cout << " lower level wq is full!" << " fill_addr: " << hex << MSHR.entry[mshr_index].address;
                    cout << " victim_addr: " << block[set][way].tag << dec << endl; });
                }
                else {
                    PACKET writeback_packet;

                    writeback_packet.fill_level = fill_level << 1;
                    writeback_packet.cpu = fill_cpu;
                    writeback_packet.address = block[set][way].address;
                    writeback_packet.full_addr = block[set][way].full_addr;
                    writeback_packet.data = block[set][way].data;
                    writeback_packet.instr_id = MSHR.entry[mshr_index].instr_id;
                    writeback_packet.ip = 0; // writeback does not have ip
                    writeback_packet.type = WRITEBACK;
                    writeback_packet.event_cycle = current_core_cycle[fill_cpu];

                    lower_level->add_wq(&writeback_packet);
                }
            }
#ifdef SANITY_CHECK
            else {
                // sanity check
                if (cache_type != IS_STLB)
                    assert(0);
            }
#endif
        }

        if (do_fill) {
            // update prefetcher
            if (cache_type == IS_L1D)
                l1d_prefetcher_cache_fill(MSHR.entry[mshr_index].full_addr, set, way, (MSHR.entry[mshr_index].type == PREFETCH) ? 1 : 0, block[set][way].full_addr);
            if  (cache_type == IS_L2C)
                l2c_prefetcher_cache_fill(MSHR.entry[mshr_index].full_addr, set, way, (MSHR.entry[mshr_index].type == PREFETCH) ? 1 : 0, block[set][way].full_addr);

            // update replacement policy
            if (cache_type == IS_LLC) {
                llc_update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, block[set][way].full_addr, MSHR.entry[mshr_index].type, 0);

            }
            else
                update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, block[set][way].full_addr, MSHR.entry[mshr_index].type, 0);

            // COLLECT STATS
            sim_miss[fill_cpu][MSHR.entry[mshr_index].type]++;
            sim_access[fill_cpu][MSHR.entry[mshr_index].type]++;

            fill_cache(set, way, &MSHR.entry[mshr_index]);

            // RFO marks cache line dirty
            if (cache_type == IS_L1D) {
                if (MSHR.entry[mshr_index].type == RFO)
                    block[set][way].dirty = 1;
            }

            // check fill level
            if (MSHR.entry[mshr_index].fill_level < fill_level) {

                if (MSHR.entry[mshr_index].instruction) 
                    upper_level_icache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
                else // data
                    upper_level_dcache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
            }

            // update processed packets
            if (cache_type == IS_ITLB) { 
                MSHR.entry[mshr_index].instruction_pa = block[set][way].data;
                if (PROCESSED.occupancy < PROCESSED.SIZE)
                    PROCESSED.add_queue(&MSHR.entry[mshr_index]);
            }
            else if (cache_type == IS_DTLB) {
                MSHR.entry[mshr_index].data_pa = block[set][way].data;
                if (PROCESSED.occupancy < PROCESSED.SIZE)
                    PROCESSED.add_queue(&MSHR.entry[mshr_index]);
            }
            else if (cache_type == IS_L1I) {
                if (PROCESSED.occupancy < PROCESSED.SIZE)
                    PROCESSED.add_queue(&MSHR.entry[mshr_index]);
            }
            //else if (cache_type == IS_L1D) {
            else if ((cache_type == IS_L1D) && (MSHR.entry[mshr_index].type != PREFETCH)) {
                if (PROCESSED.occupancy < PROCESSED.SIZE)
                    PROCESSED.add_queue(&MSHR.entry[mshr_index]);
            }

            MSHR.remove_queue(&MSHR.entry[mshr_index]);
            MSHR.num_returned--;

            update_fill_cycle();
        }
    }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x398, %rsp            # imm = 0x398
movl 0xc9c4(%rdi), %eax
cmpl 0x7388(%rdi), %eax
je 0x3f78
movq %rdi, %rbx
movq 0xca20(%rdi), %rcx
imulq $0x380, %rax, %r14      # imm = 0x380
movl 0x330(%rcx,%r14), %r12d
cmpq $0x1, %r12
je 0x3f78
movq 0xc9d0(%rbx), %rdx
leaq 0x7d540(%rip), %rsi     # 0x80ec0
cmpq (%rsi,%r12,8), %rdx
ja 0x3f78
cmpl 0xc9a8(%rbx), %eax
jae 0x3f8a
movl 0x340(%rcx,%r14), %ebp
movl 0x7370(%rbx), %edi
callq 0x9203
movl $0xffffffff, %r13d      # imm = 0xFFFFFFFF
movl %eax, %ecx
shll %cl, %r13d
notl %r13d
andl %ebp, %r13d
cmpb $0x6, 0x73a4(%rbx)
movq 0xca20(%rbx), %rcx
movq 0x348(%rcx,%r14), %rax
movq 0x368(%rcx,%r14), %rdx
movq 0x7390(%rbx), %rsi
movq (%rsi,%r13,8), %r8
movq 0x370(%rcx,%r14), %r9
movzbl 0x32f(%rcx,%r14), %r10d
movq %rbx, %rdi
movl %r12d, %esi
movl %r13d, %ecx
jne 0x3a09
pushq %r10
pushq %rax
callq 0x136ce
jmp 0x3a11
pushq %r10
pushq %rax
callq 0x134d4
addq $0x10, %rsp
movl %eax, %ebp
leaq 0xc988(%rbx), %r15
movb 0x73a4(%rbx), %al
cmpb $0x6, %al
setne %cl
cmpl $0x10, %ebp
setne %dl
orb %cl, %dl
je 0x3ac2
movq 0x7390(%rbx), %rcx
movl %r13d, %edx
movq %rdx, 0x8(%rsp)
movq (%rcx,%rdx,8), %rcx
movl %ebp, %edx
leaq (%rdx,%rdx,4), %rdx
shlq $0x4, %rdx
movq %rdx, (%rsp)
cmpb $0x0, 0x2(%rcx,%rdx)
je 0x3c99
movq 0x18(%rbx), %rdi
testq %rdi, %rdi
je 0x3b84
movq %r15, 0x10(%rsp)
movq (%rdi), %rax
movl $0x2, %esi
callq *0x30(%rax)
movl %eax, %r15d
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
movl $0x2, %esi
callq *0x38(%rax)
cmpl %eax, %r15d
jne 0x3bab
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
callq *0x28(%rax)
movq 0xca20(%rbx), %rax
movzbl 0x32f(%rax,%r14), %eax
incq 0x7328(%rbx,%rax,8)
jmp 0x3f78
movq 0xca20(%rbx), %rax
movq 0x348(%rax,%r14), %r8
movq 0x370(%rax,%r14), %r9
movzbl 0x32f(%rax,%r14), %eax
subq $0x8, %rsp
movq %rbx, %rdi
movl %r12d, %esi
movl %r13d, %edx
movl $0x10, %ecx
pushq $0x0
pushq %rax
pushq $0x0
callq 0x136d4
addq $0x20, %rsp
movq 0xca20(%rbx), %rsi
movzbl 0x32f(%rsi,%r14), %eax
movq %r12, %rcx
shlq $0x5, %rcx
addq %rbx, %rcx
incq 0x10328(%rcx,%rax,8)
incq 0x102e8(%rcx,%rax,8)
movl 0x8(%rsi,%r14), %eax
cmpl 0x7398(%rbx), %eax
jge 0x3b53
addq %r14, %rsi
xorl %eax, %eax
cmpb $0x0, (%rsi)
sete %al
leaq (%rbx,%rax,8), %rax
movq 0x8(%rax,%r12,8), %rdi
movq (%rdi), %rax
callq *0x18(%rax)
addq 0xca20(%rbx), %r14
movq %r15, %rdi
movq %r14, %rsi
callq 0xc41a
decl 0xc9c0(%rbx)
movq %rbx, %rdi
addq $0x398, %rsp            # imm = 0x398
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x3fca
cmpb $0x2, %al
je 0x3d8e
leaq 0x104d4(%rip), %rdi     # 0x14067
leaq 0x104cf(%rip), %rsi     # 0x14069
leaq 0x104d5(%rip), %rcx     # 0x14076
movl $0x65, %edx
callq 0x3160
leaq 0x30(%rsp), %r15
movw $0xff00, 0x314(%r15)    # imm = 0xFF00
xorl %eax, %eax
movl %eax, -0x18(%r15)
movl %eax, -0x15(%r15)
movb $-0x1, 0x316(%r15)
pcmpeqd %xmm0, %xmm0
movdqu %xmm0, -0x10(%r15)
movl $0x314, %edx            # imm = 0x314
movq %r15, %rdi
xorl %esi, %esi
callq 0x3130
pxor %xmm0, %xmm0
movdqu %xmm0, 0x31c(%r15)
movdqu %xmm0, 0x32c(%r15)
xorl %eax, %eax
movl %eax, 0x33c(%r15)
movl 0x7398(%rbx), %eax
addl %eax, %eax
movl %eax, -0x10(%r15)
movl %r12d, 0x318(%r15)
movq 0x7390(%rbx), %rax
movq 0x8(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq (%rsp), %rcx
movups 0x18(%rax,%rcx), %xmm0
movups %xmm0, 0x328(%r15)
movq 0x30(%rax,%rcx), %rax
movq %rax, 0x348(%r15)
movq 0xca20(%rbx), %rax
movq 0x368(%rax,%r14), %rax
movq %rax, 0x350(%r15)
movq $0x0, 0x358(%r15)
movb $0x3, 0x317(%r15)
leaq 0x7d24c(%rip), %rax     # 0x80ec0
movq (%rax,%r12,8), %rax
movq %rax, 0x360(%r15)
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
leaq 0x18(%rsp), %rsi
callq *0x8(%rax)
movb 0x73a4(%rbx), %al
movq 0x10(%rsp), %r15
cmpb $0x4, %al
jne 0x3ce8
movq 0xca20(%rbx), %rax
movq 0x348(%rax,%r14), %rsi
xorl %r8d, %r8d
cmpb $0x2, 0x32f(%rax,%r14)
sete %r8b
movq 0x7390(%rbx), %rax
movq 0x8(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq (%rsp), %rcx
movq 0x20(%rax,%rcx), %r9
movq %rbx, %rdi
movl %r13d, %edx
movl %ebp, %ecx
callq 0x13814
movb 0x73a4(%rbx), %al
cmpb $0x5, %al
jne 0x3d37
movq 0xca20(%rbx), %rax
movq 0x348(%rax,%r14), %rsi
xorl %r8d, %r8d
cmpb $0x2, 0x32f(%rax,%r14)
sete %r8b
movq 0x7390(%rbx), %rax
movq 0x8(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq (%rsp), %rcx
movq 0x20(%rax,%rcx), %r9
movq %rbx, %rdi
movl %r13d, %edx
movl %ebp, %ecx
callq 0x1380c
movb 0x73a4(%rbx), %al
cmpb $0x6, %al
jne 0x3d8e
movq 0xca20(%rbx), %rax
movq 0x348(%rax,%r14), %r8
movq 0x370(%rax,%r14), %r9
movq 0x7390(%rbx), %rcx
movq 0x8(%rsp), %rdx
movq (%rcx,%rdx,8), %r10
movzbl 0x32f(%rax,%r14), %eax
subq $0x8, %rsp
movq %rbx, %rdi
movl %r12d, %esi
movl %r13d, %edx
movl %ebp, %ecx
pushq $0x0
pushq %rax
movq 0x18(%rsp), %rax
pushq 0x20(%r10,%rax)
callq 0x136d4
jmp 0x3ddf
movq 0xca20(%rbx), %rax
movq 0x348(%rax,%r14), %r8
movq 0x370(%rax,%r14), %r9
movq 0x7390(%rbx), %rcx
movq 0x8(%rsp), %rdx
movq (%rcx,%rdx,8), %r10
movzbl 0x32f(%rax,%r14), %eax
subq $0x8, %rsp
movq %rbx, %rdi
movl %r12d, %esi
movl %r13d, %edx
movl %ebp, %ecx
pushq $0x0
pushq %rax
movq 0x18(%rsp), %rax
pushq 0x20(%r10,%rax)
callq 0x135ee
addq $0x20, %rsp
movq 0xca20(%rbx), %rcx
movzbl 0x32f(%rcx,%r14), %eax
movq %r12, %rdx
shlq $0x5, %rdx
addq %rbx, %rdx
incq 0x10328(%rdx,%rax,8)
addq %r14, %rcx
incq 0x102e8(%rdx,%rax,8)
movq %rbx, %rdi
movl %r13d, %esi
movl %ebp, %edx
callq 0x402a
cmpb $0x4, 0x73a4(%rbx)
movq 0xca20(%rbx), %rsi
jne 0x3e51
cmpb $0x1, 0x32f(%rsi,%r14)
jne 0x3e51
movq 0x7390(%rbx), %rax
movq 0x8(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq (%rsp), %rcx
movb $0x1, 0x2(%rax,%rcx)
movl 0x8(%rsi,%r14), %eax
cmpl 0x7398(%rbx), %eax
jge 0x3e78
addq %r14, %rsi
xorl %eax, %eax
cmpb $0x0, (%rsi)
sete %al
leaq (%rbx,%rax,8), %rax
movq 0x8(%rax,%r12,8), %rdi
movq (%rdi), %rax
callq *0x18(%rax)
movzbl 0x73a4(%rbx), %eax
cmpq $0x4, %rax
ja 0x3f58
leaq 0x10174(%rip), %rcx     # 0x14004
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x7390(%rbx), %rax
movq 0x8(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq (%rsp), %rcx
movq 0x30(%rax,%rcx), %rax
movq 0xca20(%rbx), %rsi
movq %rax, 0x350(%rsi,%r14)
jmp 0x3f0d
movl 0xe65c(%rbx), %eax
cmpl 0xe648(%rbx), %eax
jae 0x3f58
leaq 0xe628(%rbx), %rdi
movq 0xca20(%rbx), %rsi
jmp 0x3f22
movq 0x7390(%rbx), %rax
movq 0x8(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq (%rsp), %rcx
movq 0x30(%rax,%rcx), %rax
movq 0xca20(%rbx), %rsi
movq %rax, 0x358(%rsi,%r14)
movl 0xe65c(%rbx), %eax
cmpl 0xe648(%rbx), %eax
jae 0x3f58
leaq 0xe628(%rbx), %rdi
addq %r14, %rsi
callq 0xc3b6
jmp 0x3f58
movq 0xca20(%rbx), %rsi
cmpb $0x2, 0x32f(%rsi,%r14)
je 0x3f58
movl 0xe65c(%rbx), %eax
cmpl 0xe648(%rbx), %eax
jae 0x3f58
addq %r14, %rsi
leaq 0xe628(%rbx), %rdi
jmp 0x3f25
addq 0xca20(%rbx), %r14
movq %r15, %rdi
movq %r14, %rsi
callq 0xc41a
decl 0xc9c0(%rbx)
movq %rbx, %rdi
callq 0x3fca
addq $0x398, %rsp            # imm = 0x398
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x100d6(%rip), %rdi     # 0x14067
leaq 0x100d1(%rip), %rsi     # 0x14069
leaq 0x100d7(%rip), %rcx     # 0x14076
movl $0x10, %edx
callq 0x3160
nop