// File: /workspace/github_c_makefile_star2_O2/xiane[P]libvphevcodec/AML_HEVCEncoder.cpp
// Function: Wave4VpuEncSeqInit(AMVHEVCEncHandle_s*, int)
AMVEnc_Status Wave4VpuEncSeqInit(AMVHEVCEncHandle *Handle, int alloc) {
    int coreIdx = Handle->instance_id;
    Uint32 use_sec_axi = 0;    // [31:0]
    Uint32 sec_axi_buf_size = 0x00012800;   // 74KB
    Uint32 temp;   // [31:0]
    Uint32 rd_ptr, wr_ptr, src_num, fb_num;   // [31:0]
    VLOG(DEBUG, "Wave4VpuEnCSeqInit- start\n");
    // instance information
    if (alloc) {
        memset((void*) &Handle->temp_vb, 0, sizeof(vpu_buffer_t));
        Handle->temp_vb.size = WAVE420L_TEMP_BUF_SIZE;
        if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->temp_vb) < 0) {
            VLOG(ERR, "Wave4VpuEnCSeqInit  error temp alloc\n");
            return AMVENC_MEMORY_FAIL;
        }
    }

    vdi_clear_memory(Handle->instance_id, Handle->temp_vb.phys_addr, Handle->temp_vb.size);

    temp = 0;
    temp |= (0 << 24); // [27:24] codec_std_aux
    temp |= (1 << 16); // [23:16] codec_std
    temp |= (Handle->instance_id << 0);  // [15: 0] Handle->instance_id
    VpuWriteReg(Handle->instance_id, W4_INST_INDEX, temp);

    // Work Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_WORK_BASE, Handle->work_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_WORK_SIZE, Handle->work_vb.size);
    VpuWriteReg(Handle->instance_id, W4_WORK_PARAM, 0);

    // Temp Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_ADDR_TEMP_BASE, Handle->temp_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_TEMP_SIZE, Handle->temp_vb.size);
    VpuWriteReg(Handle->instance_id, W4_TEMP_PARAM, gol_endian);

    VpuWriteReg(Handle->instance_id, W4_ADDR_SEC_AXI, 0);
    VpuWriteReg(Handle->instance_id, W4_SEC_AXI_SIZE, sec_axi_buf_size);
    VpuWriteReg(Handle->instance_id, W4_USE_SEC_AXI, use_sec_axi);

    if (alloc) {
        memset((void*) &Handle->bs_vb, 0, sizeof(vpu_buffer_t));
        Handle->bs_vb.size = WAVE420L_STREAM_BUF_SIZE;
        Handle->bs_vb.cached = 1;
        if (vdi_allocate_dma_memory(Handle->instance_id, &Handle->bs_vb) < 0) {
            VLOG(ERR, "Wave4VpuEnCSeqInit  error Handle->bs_vb alloc\n");
            return AMVENC_MEMORY_FAIL;
        }
        /*TODO whether should indcude vdi_clear_memory */
        vdi_clear_memory(Handle->instance_id, Handle->bs_vb.phys_addr, Handle->bs_vb.size);
    }

    // Bitstream Buffer Setting
    VpuWriteReg(Handle->instance_id, W4_BS_START_ADDR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_SIZE, Handle->bs_vb.size - 0x8000);
    VpuWriteReg(Handle->instance_id, W4_BS_PARAM, 0xf);
    VpuWriteReg(Handle->instance_id, W4_BS_OPTION, 0);

    VpuWriteReg(Handle->instance_id, W4_BS_RD_PTR, Handle->bs_vb.phys_addr);
    VpuWriteReg(Handle->instance_id, W4_BS_WR_PTR, Handle->bs_vb.phys_addr);

    // Report Buffer Setting
    //VpuWriteReg(Handle->instance_id, W4_CMD_ENC_ADDR_REPORT_BASE,   addr_report_buf);
    //VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_SIZE,        report_buf_size);
    //VpuWriteReg(Handle->instance_id, W4_CMD_ENC_REPORT_PARAM,       report_endian);

    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SET_PARAM_OPTION, 0);
    VpuWriteReg(Handle->instance_id, W4_CMD_ENC_SET_PARAM_ENABLE, (unsigned int )0xffffffff);

    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_SRC_SIZE, (wave420l_align8(Handle->enc_height) << 16) | Handle->enc_width);
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_PARAM, 0x00020001); //8bit, profile 1:main, firmware determines a level, main tier.
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_GOP_PARAM, Handle->mGopIdx);

    temp = 0;
    temp |= Handle->idrPeriod << 16;
    temp |= 30 << 3;
    temp |= Handle->mEncParams->refresh_type; //[2:0] refresh type of intra picutre
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_INTRA_PARAM, temp);
    //VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_INTRA_PARAM, (Handle->idrPeriod << 16) | 0xf1);

    if (Handle->enc_height % 8)
        VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, (Handle->enc_height % 8) << 16);
    else
        VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_FRAME_RATE, Handle->frame_rate);
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_INDEPENDENT_SLICE, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_DEPENDENT_SLICE, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_SEQ_INTRA_REFRESH, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_PARAM, 0x080104b0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_RESERVED, 0);
    if (Handle->enc_counter > 0)
        VpuWriteReg(coreIdx,
                W4_CMD_ENC_RC_PARAM,
                (200 << 20) | (32 << 14) | (0 << 13) | (1 << 9) | (0 << 7) | (2 << 4) | 0xf);
        //enable rc, disable roi, initdelay 3000, initrc QP 63
    else
        VpuWriteReg(coreIdx, W4_CMD_ENC_RC_PARAM, 0xbb8fc22f); //enable rc, disable roi, initdelay 3000, initrc QP 63
    enable_roi = (0xbb8fc22f & (1 << 13)) >> 13;  // need check with cnm for bit13 or bit14
    VpuWriteReg(coreIdx, W4_CMD_ENC_RC_MIN_MAX_QP, 0x0000acc8);
    VpuWriteReg(coreIdx, W4_CMD_ENC_RC_BIT_RATIO_LAYER_0_3, 0x01010101);
    VpuWriteReg(coreIdx, W4_CMD_ENC_RC_BIT_RATIO_LAYER_4_7, 0x01010101);
    VpuWriteReg(coreIdx, W4_CMD_ENC_NR_PARAM, 0x00000008);
    VpuWriteReg(coreIdx, W4_CMD_ENC_NR_WEIGHT, 0x08421ce7);
    VpuWriteReg(coreIdx, W4_CMD_ENC_NUM_UNITS_IN_TICK, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_TIME_SCALE, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_NUM_TICKS_POC_DIFF_ONE, 0);
    VpuWriteReg(coreIdx, W4_CMD_ENC_RC_TRANS_RATE, Handle->bitrate * 6 / 5);
    VpuWriteReg(coreIdx, W4_CMD_ENC_RC_TARGET_RATE, Handle->bitrate);
    //VpuWriteReg(coreIdx, W4_CMD_ENC_RC_TRANS_RATE,  bitrate + bitrate / 5);
    //VpuWriteReg(coreIdx, W4_CMD_ENC_RC_TARGET_RATE,  bitrate);
    VpuWriteReg(coreIdx, W4_CMD_ENC_ROT_PARAM, rotMirMode);

    // issue command request
    VpuWriteReg(Handle->instance_id, W4_VPU_BUSY_STATUS, 1);
    VpuWriteReg(Handle->instance_id, W4_RET_SUCCESS, 0);  //for debug
    VpuWriteReg(Handle->instance_id, W4_CORE_INDEX, 0);
    //VpuWriteReg(Handle->instance_id, W4_INST_INDEX,  (Handle->instance_id&0xffff)|(1<<16));

    VpuWriteReg(Handle->instance_id, W4_COMMAND, SET_PARAM);
    VpuWriteReg(Handle->instance_id, W4_VPU_HOST_INT_REQ, 1);
    //Wave4BitIssueCommand(0, 4, CREATE_INSTANCE);
    temp = VpuReadReg(Handle->instance_id, W4_VPU_BUSY_STATUS);
    VLOG(NONE, "W4_VPU_BUSY_STATUS :0x%x\n", temp);
    if (vdi_wait_interrupt(Handle->instance_id, VPU_BUSY_CHECK_TIMEOUT) == -1) {
        VLOG(ERR, "Wave4VpuEnCSeqInit error time out\n");
        return AMVENC_TIMEOUT;
    }

    if (VpuReadReg(Handle->instance_id, W4_RET_SUCCESS) == 0) {
        uint32_t reasonCode = VpuReadReg(Handle->instance_id, W4_RET_FAIL_REASON);
        VLOG(ERR, "Wave4VpuEnCSeqInit failedREASON CODE(%08x)\n", reasonCode);
        return AMVENC_HARDWARE;
    }
    temp = VpuReadReg(Handle->instance_id, W4_RET_SUCCESS);
    VLOG(DEBUG, "W4_RET_SUCCESS %x\n", temp);
    rd_ptr = VpuReadReg(Handle->instance_id, W4_BS_RD_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    wr_ptr = VpuReadReg(Handle->instance_id, W4_BS_WR_PTR);
    src_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_SRC_BUF_NUM);
    fb_num = VpuReadReg(Handle->instance_id, W4_RET_ENC_MIN_FB_NUM);
    VLOG(DEBUG, "Wave4VpuEnCSeqInit, rd:0x%x, wr:0x%x, src:%d, fb:%d\n", rd_ptr, wr_ptr, src_num, fb_num);
    VLOG(DEBUG, "Wave4VpuEnCSeqInit- End\n");
    return AMVENC_SUCCESS;
}

// Assembly:
pushq %rbp
pushq %r14
pushq %rbx
movl %esi, %r14d
movq %rdi, %rbx
movl (%rdi), %ebp
movl %ebp, %edi
testl %esi, %esi
je 0x4be8
leaq 0x60(%rbx), %rsi
xorps %xmm0, %xmm0
movups %xmm0, 0x70(%rbx)
movups %xmm0, 0x64(%rbx)
movl $0xa00000, 0x60(%rbx)   # imm = 0xA00000
movl %ebp, %edi
callq 0x2270
testl %eax, %eax
js 0x4fd9
movl (%rbx), %edi
movl 0x60(%rbx), %edx
movl 0x68(%rbx), %esi
callq 0x2170
movl (%rbx), %edi
movl %edi, %edx
orl $0x10000, %edx          # imm = 0x10000
movl $0x108, %esi            # imm = 0x108
callq 0x2160
movl (%rbx), %edi
movl 0x48(%rbx), %edx
movl $0x138, %esi            # imm = 0x138
callq 0x2160
movl (%rbx), %edi
movl 0x40(%rbx), %edx
movl $0x13c, %esi            # imm = 0x13C
callq 0x2160
movl (%rbx), %edi
movl $0x140, %esi            # imm = 0x140
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl 0x68(%rbx), %edx
movl $0x144, %esi            # imm = 0x144
callq 0x2160
movl (%rbx), %edi
movl 0x60(%rbx), %edx
movl $0x148, %esi            # imm = 0x148
callq 0x2160
movl (%rbx), %edi
pushq $0xf
popq %rdx
movl $0x14c, %esi            # imm = 0x14C
callq 0x2160
movl (%rbx), %edi
movl $0x150, %esi            # imm = 0x150
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x154, %esi            # imm = 0x154
movl $0x12800, %edx          # imm = 0x12800
callq 0x2160
movl (%rbx), %edi
movl $0x158, %esi            # imm = 0x158
xorl %edx, %edx
callq 0x2160
testl %r14d, %r14d
je 0x4cde
leaq 0x80(%rbx), %rsi
xorps %xmm0, %xmm0
andq $0x0, 0x98(%rbx)
movups %xmm0, 0x88(%rbx)
movabsq $0x100b00000, %rax      # imm = 0x100B00000
movq %rax, 0x80(%rbx)
movl (%rbx), %edi
callq 0x2270
testl %eax, %eax
js 0x4ffa
movl 0x88(%rbx), %esi
movl (%rbx), %edi
movl 0x80(%rbx), %edx
callq 0x2170
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x120, %esi            # imm = 0x120
callq 0x2160
movl (%rbx), %edi
movl $0xffff8000, %edx       # imm = 0xFFFF8000
addl 0x80(%rbx), %edx
movl $0x124, %esi            # imm = 0x124
callq 0x2160
movl (%rbx), %edi
pushq $0xf
popq %rdx
movl $0x128, %esi            # imm = 0x128
callq 0x2160
movl (%rbx), %edi
movl $0x12c, %esi            # imm = 0x12C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x130, %esi            # imm = 0x130
callq 0x2160
movl (%rbx), %edi
movl 0x88(%rbx), %edx
movl $0x134, %esi            # imm = 0x134
callq 0x2160
movl (%rbx), %edi
movl $0x10c, %esi            # imm = 0x10C
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $-0x1
popq %rdx
movl $0x15c, %esi            # imm = 0x15C
callq 0x2160
movl 0x10(%rbx), %edx
shll $0x10, %edx
addl $0x70000, %edx          # imm = 0x70000
andl $0xfff80000, %edx       # imm = 0xFFF80000
orl 0xc(%rbx), %edx
movl %ebp, %edi
movl $0x160, %esi            # imm = 0x160
callq 0x2160
movl %ebp, %edi
movl $0x16c, %esi            # imm = 0x16C
movl $0x20001, %edx          # imm = 0x20001
callq 0x2160
movl 0x304(%rbx), %edx
movl %ebp, %edi
movl $0x170, %esi            # imm = 0x170
callq 0x2160
movl 0x1c(%rbx), %edx
shll $0x10, %edx
movq 0x2e0(%rbx), %rax
orl 0x5c(%rax), %edx
orl $0xf0, %edx
movl %ebp, %edi
movl $0x174, %esi            # imm = 0x174
callq 0x2160
movl 0x10(%rbx), %edx
andl $0x7, %edx
shll $0x10, %edx
movl %ebp, %edi
movl $0x178, %esi            # imm = 0x178
callq 0x2160
movl %ebp, %edi
movl $0x17c, %esi            # imm = 0x17C
xorl %edx, %edx
callq 0x2160
movl 0x18(%rbx), %edx
movl %ebp, %edi
movl $0x180, %esi            # imm = 0x180
callq 0x2160
movl %ebp, %edi
movl $0x184, %esi            # imm = 0x184
xorl %edx, %edx
callq 0x2160
movl %ebp, %edi
movl $0x188, %esi            # imm = 0x188
xorl %edx, %edx
callq 0x2160
movl %ebp, %edi
movl $0x18c, %esi            # imm = 0x18C
xorl %edx, %edx
callq 0x2160
movl %ebp, %edi
movl $0x190, %esi            # imm = 0x190
movl $0x80104b0, %edx        # imm = 0x80104B0
callq 0x2160
movl %ebp, %edi
movl $0x194, %esi            # imm = 0x194
xorl %edx, %edx
callq 0x2160
cmpl $0x0, 0x2c(%rbx)
movl $0xbb8fc22f, %eax       # imm = 0xBB8FC22F
movl $0xc88022f, %edx        # imm = 0xC88022F
cmovel %eax, %edx
movl %ebp, %edi
movl $0x198, %esi            # imm = 0x198
callq 0x2160
movl %ebp, %edi
movl $0x19c, %esi            # imm = 0x19C
movl $0xacc8, %edx           # imm = 0xACC8
callq 0x2160
movl %ebp, %edi
movl $0x1a0, %esi            # imm = 0x1A0
movl $0x1010101, %edx        # imm = 0x1010101
callq 0x2160
movl %ebp, %edi
movl $0x1a4, %esi            # imm = 0x1A4
movl $0x1010101, %edx        # imm = 0x1010101
callq 0x2160
pushq $0x8
popq %rdx
movl %ebp, %edi
movl $0x1a8, %esi            # imm = 0x1A8
callq 0x2160
movl %ebp, %edi
movl $0x1ac, %esi            # imm = 0x1AC
movl $0x8421ce7, %edx        # imm = 0x8421CE7
callq 0x2160
movl %ebp, %edi
movl $0x1b0, %esi            # imm = 0x1B0
xorl %edx, %edx
callq 0x2160
movl %ebp, %edi
movl $0x1b4, %esi            # imm = 0x1B4
xorl %edx, %edx
callq 0x2160
movl %ebp, %edi
movl $0x1b8, %esi            # imm = 0x1B8
xorl %edx, %edx
callq 0x2160
imull $0x6, 0x14(%rbx), %eax
pushq $0x5
popq %rcx
xorl %edx, %edx
divl %ecx
movl %ebp, %edi
movl $0x1bc, %esi            # imm = 0x1BC
movl %eax, %edx
callq 0x2160
movl 0x14(%rbx), %edx
movl %ebp, %edi
movl $0x1c0, %esi            # imm = 0x1C0
callq 0x2160
movl %ebp, %edi
movl $0x1c4, %esi            # imm = 0x1C4
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x70
popq %r14
pushq $0x1
popq %rbp
movl %r14d, %esi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
movl $0x104, %esi            # imm = 0x104
xorl %edx, %edx
callq 0x2160
movl (%rbx), %edi
pushq $0x2
popq %rdx
movl $0x100, %esi            # imm = 0x100
callq 0x2160
movl (%rbx), %edi
pushq $0x38
popq %rsi
movl %ebp, %edx
callq 0x2160
movl (%rbx), %edi
movl %r14d, %esi
callq 0x2210
movl (%rbx), %edi
movl $0x1388, %esi           # imm = 0x1388
callq 0x2360
cmpl $-0x1, %eax
je 0x4fe2
movl (%rbx), %edi
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
testl %eax, %eax
je 0x5012
movl $0x110, %esi            # imm = 0x110
callq 0x2210
movl (%rbx), %edi
movl $0x130, %esi            # imm = 0x130
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x134, %esi            # imm = 0x134
callq 0x2210
movl (%rbx), %edi
movl $0x1d8, %esi            # imm = 0x1D8
callq 0x2210
movl (%rbx), %edi
movl $0x1cc, %esi            # imm = 0x1CC
callq 0x2210
jmp 0x5037
leaq 0x270f6(%rip), %rdi     # 0x2c0d6
jmp 0x5001
leaq 0x27112(%rip), %rdi     # 0x2c0fb
callq 0x2290
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x24
jmp 0x5036
leaq 0x270a7(%rip), %rdi     # 0x2c0a8
callq 0x2290
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x1
jmp 0x5036
movl $0x114, %esi            # imm = 0x114
callq 0x2210
leaq 0x26e4f(%rip), %rdi     # 0x2be72
movl %eax, %esi
xorl %eax, %eax
callq 0x2050
pushq $0xa
popq %rdi
callq 0x2230
pushq $-0x25
popq %rbp
movl %ebp, %eax
popq %rbx
popq %r14
popq %rbp
retq