// File: /workspace/github_cpp_makefile_star2_O2/NishadSaraf[P]Championship-Simulator/src/cache.cc
// Function: CACHE::handle_writeback()
void CACHE::handle_writeback()
{
    // handle write
    uint32_t writeback_cpu = WQ.entry[WQ.head].cpu;
    if (writeback_cpu == NUM_CPUS)
        return;

    // handle the oldest entry
    if ((WQ.entry[WQ.head].event_cycle <= current_core_cycle[writeback_cpu]) && (WQ.occupancy > 0)) {
        int index = WQ.head;

        // access cache
        uint32_t set = get_set(WQ.entry[index].address);
        int way = check_hit(&WQ.entry[index]);
        
        if (way >= 0) { // writeback hit (or RFO hit for L1D)

            if (cache_type == IS_LLC) {
                llc_update_replacement_state(writeback_cpu, set, way, block[set][way].full_addr, WQ.entry[index].ip, 0, WQ.entry[index].type, 1);

            }
            else
                update_replacement_state(writeback_cpu, set, way, block[set][way].full_addr, WQ.entry[index].ip, 0, WQ.entry[index].type, 1);

            // COLLECT STATS
            sim_hit[writeback_cpu][WQ.entry[index].type]++;
            sim_access[writeback_cpu][WQ.entry[index].type]++;

            // mark dirty
            block[set][way].dirty = 1;

            if (cache_type == IS_ITLB)
                WQ.entry[index].instruction_pa = block[set][way].data;
            else if (cache_type == IS_DTLB)
                WQ.entry[index].data_pa = block[set][way].data;
            else if (cache_type == IS_STLB)
                WQ.entry[index].data = block[set][way].data;

            // check fill level
            if (WQ.entry[index].fill_level < fill_level) {

                if (WQ.entry[index].instruction) 
                    upper_level_icache[writeback_cpu]->return_data(&WQ.entry[index]);
                else // data
                    upper_level_dcache[writeback_cpu]->return_data(&WQ.entry[index]);
            }

            HIT[WQ.entry[index].type]++;
            ACCESS[WQ.entry[index].type]++;

            // remove this entry from WQ
            WQ.remove_queue(&WQ.entry[index]);
        }
        else { // writeback miss (or RFO miss for L1D)
            
            DP ( if (warmup_complete[writeback_cpu]) {
            cout << "[" << NAME << "] " << __func__ << " type: " << +WQ.entry[index].type << " miss";
            cout << " instr_id: " << WQ.entry[index].instr_id << " address: " << hex << WQ.entry[index].address;
            cout << " full_addr: " << WQ.entry[index].full_addr << dec;
            cout << " cycle: " << WQ.entry[index].event_cycle << endl; });

            if (cache_type == IS_L1D) { // RFO miss

                // check mshr
                uint8_t miss_handled = 1;
                int mshr_index = check_mshr(&WQ.entry[index]);

                if ((mshr_index == -1) && (MSHR.occupancy < MSHR_SIZE)) { // this is a new miss

                    // add it to mshr (RFO miss)
                    add_mshr(&WQ.entry[index]);

                    // add it to the next level's read queue
                    //if (lower_level) // L1D always has a lower level cache
                        lower_level->add_rq(&WQ.entry[index]);
                }
                else {
                    if ((mshr_index == -1) && (MSHR.occupancy == MSHR_SIZE)) { // not enough MSHR resource
                        
                        // cannot handle miss request until one of MSHRs is available
                        miss_handled = 0;
                        STALL[WQ.entry[index].type]++;
                    }
                    else if (mshr_index != -1) { // already in-flight miss

                        // update fill_level
                        if (WQ.entry[index].fill_level < MSHR.entry[mshr_index].fill_level)
                            MSHR.entry[mshr_index].fill_level = WQ.entry[index].fill_level;

                        // update request
                        if (MSHR.entry[mshr_index].type == PREFETCH) {
                            uint8_t  prior_returned = MSHR.entry[mshr_index].returned;
                            uint64_t prior_event_cycle = MSHR.entry[mshr_index].event_cycle;
                            memcpy(&MSHR.entry[mshr_index], &WQ.entry[index], sizeof(PACKET));

                            // in case request is already returned, we should keep event_cycle and retunred variables
                            MSHR.entry[mshr_index].returned = prior_returned;
                            MSHR.entry[mshr_index].event_cycle = prior_event_cycle;
                        }

                        MSHR_MERGED[WQ.entry[index].type]++;

                        DP ( if (warmup_complete[writeback_cpu]) {
                        cout << "[" << NAME << "] " << __func__ << " mshr merged";
                        cout << " instr_id: " << WQ.entry[index].instr_id << " prior_id: " << MSHR.entry[mshr_index].instr_id; 
                        cout << " address: " << hex << WQ.entry[index].address;
                        cout << " full_addr: " << WQ.entry[index].full_addr << dec;
                        cout << " cycle: " << WQ.entry[index].event_cycle << endl; });
                    }
                    else { // WE SHOULD NOT REACH HERE
                        cerr << "[" << NAME << "] MSHR errors" << endl;
                        assert(0);
                    }
                }

                if (miss_handled) {

                    MISS[WQ.entry[index].type]++;
                    ACCESS[WQ.entry[index].type]++;

                    // remove this entry from WQ
                    WQ.remove_queue(&WQ.entry[index]);
                }

            }
            else {
                // find victim
                uint32_t set = get_set(WQ.entry[index].address), way;
                if (cache_type == IS_LLC) {
                    way = llc_find_victim(writeback_cpu, WQ.entry[index].instr_id, set, block[set], WQ.entry[index].ip, WQ.entry[index].full_addr, WQ.entry[index].type);
                }
                else
                    way = find_victim(writeback_cpu, WQ.entry[index].instr_id, set, block[set], WQ.entry[index].ip, WQ.entry[index].full_addr, WQ.entry[index].type);

#ifdef LLC_BYPASS
                if ((cache_type == IS_LLC) && (way == LLC_WAY)) {
                    cerr << "LLC bypassing for writebacks is not allowed!" << endl;
                    assert(0);
                }
#endif

                uint8_t  do_fill = 1;

                // is this dirty?
                if (block[set][way].dirty) {

                    // check if the lower level WQ has enough room to keep this writeback request
                    if (lower_level) { 
                        if (lower_level->get_occupancy(2) == lower_level->get_size(2)) {

                            // lower level WQ is full, cannot replace this victim
                            do_fill = 0;
                            lower_level->increment_WQ_FULL();
                            STALL[WQ.entry[index].type]++;

                            DP ( if (warmup_complete[writeback_cpu]) {
                            cout << "[" << NAME << "] " << __func__ << "do_fill: " << +do_fill;
                            cout << " lower level wq is full!" << " fill_addr: " << hex << WQ.entry[index].address;
                            cout << " victim_addr: " << block[set][way].tag << dec << endl; });
                        }
                        else { 
                            PACKET writeback_packet;

                            writeback_packet.fill_level = fill_level << 1;
                            writeback_packet.cpu = writeback_cpu;
                            writeback_packet.address = block[set][way].address;
                            writeback_packet.full_addr = block[set][way].full_addr;
                            writeback_packet.data = block[set][way].data;
                            writeback_packet.instr_id = WQ.entry[index].instr_id;
                            writeback_packet.ip = 0;
                            writeback_packet.type = WRITEBACK;
                            writeback_packet.event_cycle = current_core_cycle[writeback_cpu];

                            lower_level->add_wq(&writeback_packet);
                        }
                    }
#ifdef SANITY_CHECK
                    else {
                        // sanity check
                        if (cache_type != IS_STLB)
                            assert(0);
                    }
#endif
                }

                if (do_fill) {
                    // update prefetcher
                    if (cache_type == IS_L1D)
                        l1d_prefetcher_cache_fill(WQ.entry[index].full_addr, set, way, 0, block[set][way].full_addr);
                    else if (cache_type == IS_L2C)
                        l2c_prefetcher_cache_fill(WQ.entry[index].full_addr, set, way, 0, block[set][way].full_addr);

                    // update replacement policy
                    if (cache_type == IS_LLC) {
                        llc_update_replacement_state(writeback_cpu, set, way, WQ.entry[index].full_addr, WQ.entry[index].ip, block[set][way].full_addr, WQ.entry[index].type, 0);

                    }
                    else
                        update_replacement_state(writeback_cpu, set, way, WQ.entry[index].full_addr, WQ.entry[index].ip, block[set][way].full_addr, WQ.entry[index].type, 0);

                    // COLLECT STATS
                    sim_miss[writeback_cpu][WQ.entry[index].type]++;
                    sim_access[writeback_cpu][WQ.entry[index].type]++;

                    fill_cache(set, way, &WQ.entry[index]);

                    // mark dirty
                    block[set][way].dirty = 1; 

                    // check fill level
                    if (WQ.entry[index].fill_level < fill_level) {

                        if (WQ.entry[index].instruction) 
                            upper_level_icache[writeback_cpu]->return_data(&WQ.entry[index]);
                        else // data
                            upper_level_dcache[writeback_cpu]->return_data(&WQ.entry[index]);
                    }

                    MISS[WQ.entry[index].type]++;
                    ACCESS[WQ.entry[index].type]++;

                    // remove this entry from WQ
                    WQ.remove_queue(&WQ.entry[index]);
                }
            }
        }
    }
}

// Assembly:
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3a8, %rsp            # imm = 0x3A8
movq 0x7440(%rdi), %rax
movl 0x73d4(%rdi), %ecx
imulq $0x380, %rcx, %rdx      # imm = 0x380
movl 0x330(%rax,%rdx), %r15d
cmpq $0x1, %r15
jne 0x3031
addq $0x3a8, %rsp            # imm = 0x3A8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
addq %rax, %rdx
movq 0x378(%rdx), %rdx
leaq 0x79e6e(%rip), %r13     # 0x7ceb0
cmpq (%r13,%r15,8), %rdx
ja 0x301f
movq %rdi, %rbx
cmpl $0x0, 0x73dc(%rdi)
je 0x301f
leaq 0x73a8(%rbx), %rdx
movq %rdx, 0x18(%rsp)
movslq %ecx, %rcx
imulq $0x380, %rcx, %r14      # imm = 0x380
movq 0x340(%rax,%r14), %rsi
movq %rbx, %rdi
callq 0x2e58
movl %eax, %ebp
movq 0x7440(%rbx), %rsi
addq %r14, %rsi
movq %rbx, %rdi
callq 0x3772
movb 0x73a4(%rbx), %cl
testl %eax, %eax
js 0x30f1
movl %eax, %edx
imulq $0x50, %rdx, %r12
movl %ebp, %r13d
movq 0x7390(%rbx), %rdx
movq 0x7440(%rbx), %rsi
movq (%rdx,%r13,8), %rdx
movq 0x20(%rdx,%r12), %r8
movq 0x370(%rsi,%r14), %r9
movzbl 0x32f(%rsi,%r14), %r10d
subq $0x8, %rsp
cmpb $0x6, %cl
jne 0x319c
movq %rbx, %rdi
movl %r15d, %esi
movl %ebp, %edx
movl %eax, %ecx
pushq $0x1
pushq %r10
pushq $0x0
callq 0xfcc8
jmp 0x31b1
movq 0x7440(%rbx), %r12
cmpb $0x4, %cl
jne 0x3223
leaq (%r12,%r14), %r15
movq %rbx, %rdi
movq %r15, %rsi
callq 0x3908
cmpl $-0x1, %eax
je 0x33b8
movl 0x8(%r12,%r14), %ecx
movq 0xca20(%rbx), %rdi
cltq
imulq $0x380, %rax, %r13      # imm = 0x380
cmpl 0x8(%rdi,%r13), %ecx
jge 0x313f
leaq (%rdi,%r13), %rax
addq $0x8, %rax
movl %ecx, (%rax)
cmpb $0x2, 0x32f(%rdi,%r13)
jne 0x3186
addq %r13, %rdi
movb 0x32c(%rdi), %bpl
movq 0x378(%rdi), %r12
movl $0x380, %edx            # imm = 0x380
movq %r15, %rsi
callq 0x21b0
movq 0xca20(%rbx), %rax
movb %bpl, 0x32c(%rax,%r13)
movq %r12, 0x378(%rax,%r13)
movq 0x7440(%rbx), %r12
movzbl 0x32f(%r12,%r14), %eax
incq 0x7308(%rbx,%rax,8)
jmp 0x33f8
movq %rbx, %rdi
movl %r15d, %esi
movl %ebp, %edx
movl %eax, %ecx
pushq $0x1
pushq %r10
pushq $0x0
callq 0xfc4e
addq $0x20, %rsp
movq 0x7440(%rbx), %rsi
movzbl 0x32f(%rsi,%r14), %eax
movq %r15, %rcx
shlq $0x5, %rcx
addq %rbx, %rcx
incq 0x10308(%rcx,%rax,8)
incq 0x102e8(%rcx,%rax,8)
movq 0x7390(%rbx), %rax
movq (%rax,%r13,8), %rax
movb $0x1, 0x2(%rax,%r12)
movzbl 0x73a4(%rbx), %ecx
cmpl $0x2, %ecx
je 0x32a5
cmpl $0x1, %ecx
je 0x3296
testl %ecx, %ecx
jne 0x32b2
movq 0x30(%rax,%r12), %rax
movq %rax, 0x350(%rsi,%r14)
jmp 0x32b2
movq 0x340(%r12,%r14), %rsi
movq %rbx, %rdi
callq 0x2e58
cmpb $0x6, 0x73a4(%rbx)
movq 0x7440(%rbx), %rcx
movq 0x348(%rcx,%r14), %r11
movq 0x368(%rcx,%r14), %rdx
movq 0x7390(%rbx), %rsi
movl %eax, 0xc(%rsp)
movl %eax, %edi
movq %rdi, 0x10(%rsp)
movq (%rsi,%rdi,8), %r8
movq 0x370(%rcx,%r14), %r9
movzbl 0x32f(%rcx,%r14), %r10d
movq %rbx, %rdi
movl %r15d, %esi
jne 0x3318
movl 0xc(%rsp), %ecx
pushq %r10
pushq %r11
callq 0xfcc2
jmp 0x3325
movq 0x30(%rax,%r12), %rax
movq %rax, 0x358(%rsi,%r14)
jmp 0x32b2
movq 0x30(%rax,%r12), %rax
movq %rax, 0x360(%rsi,%r14)
movl 0x8(%rsi,%r14), %eax
cmpl 0x7398(%rbx), %eax
jge 0x32d9
addq %r14, %rsi
xorl %eax, %eax
cmpb $0x0, (%rsi)
sete %al
leaq (%rbx,%rax,8), %rax
movq 0x8(%rax,%r15,8), %rdi
movq (%rdi), %rax
callq *0x18(%rax)
movq 0x7440(%rbx), %rax
movzbl 0x32f(%rax,%r14), %ecx
incq 0x72c8(%rbx,%rcx,8)
incq 0x72a8(%rbx,%rcx,8)
leaq (%rax,%r14), %rsi
movq 0x18(%rsp), %rdi
addq $0x3a8, %rsp            # imm = 0x3A8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x9cc0
movl 0xc(%rsp), %ecx
pushq %r10
pushq %r11
callq 0xfb58
popq %rcx
popq %rdx
movl %eax, %r12d
movb 0x73a4(%rbx), %al
cmpb $0x6, %al
setne %cl
cmpl $0x10, %r12d
setne %dl
orb %cl, %dl
je 0x36dd
movq 0x7390(%rbx), %rcx
movq 0x10(%rsp), %rdx
movq (%rcx,%rdx,8), %rcx
movl %r12d, %edx
imulq $0x50, %rdx, %r11
cmpb $0x0, 0x2(%rcx,%r11)
je 0x34dc
movq 0x18(%rbx), %rdi
testq %rdi, %rdi
je 0x3418
movq %r11, 0x20(%rsp)
movq (%rdi), %rax
pushq $0x2
popq %rsi
callq *0x30(%rax)
movl %eax, %ebp
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
pushq $0x2
popq %rsi
callq *0x38(%rax)
cmpl %eax, %ebp
jne 0x3447
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
callq *0x28(%rax)
movq 0x7440(%rbx), %rax
movzbl 0x32f(%rax,%r14), %eax
jmp 0x36d0
movl 0x7388(%rbx), %eax
cmpl %eax, 0xc9bc(%rbx)
jae 0x36c5
movq %rbx, %rdi
movq %r15, %rsi
callq 0x3940
movq 0x18(%rbx), %rdi
movq 0x7440(%rbx), %rsi
addq %r14, %rsi
movq (%rdi), %rax
callq *(%rax)
movq 0x7440(%rbx), %r12
movzbl 0x32f(%r12,%r14), %eax
incq 0x72e8(%rbx,%rax,8)
incq 0x72a8(%rbx,%rax,8)
addq %r14, %r12
movq 0x18(%rsp), %rdi
movq %r12, %rsi
jmp 0x3302
movl %r12d, %r13d
cmpb $0x2, %al
movq 0x10(%rsp), %r12
je 0x35c7
leaq 0xcc38(%rip), %rdi      # 0x10067
leaq 0xcc33(%rip), %rsi      # 0x10069
leaq 0xcc63(%rip), %rcx      # 0x100a0
movl $0x15f, %edx            # imm = 0x15F
callq 0x2160
leaq 0x28(%rsp), %rbp
movq %rbp, %rdi
callq 0x53f4
movl 0x7398(%rbx), %eax
addl %eax, %eax
movl %eax, 0x8(%rbp)
movl %r15d, 0x330(%rbp)
movq 0x7390(%rbx), %rax
movq 0x10(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq 0x20(%rsp), %rcx
movups 0x18(%rax,%rcx), %xmm0
movups %xmm0, 0x340(%rbp)
movq 0x30(%rax,%rcx), %rax
movq %rax, 0x360(%rbp)
movq 0x7440(%rbx), %rax
movq 0x368(%rax,%r14), %rax
movq %rax, 0x368(%rbp)
andq $0x0, 0x370(%rbp)
movb $0x3, 0x32f(%rbp)
movq (%r13,%r15,8), %rax
movq %rax, 0x378(%rbp)
movq 0x18(%rbx), %rdi
movq (%rdi), %rax
movq %rbp, %rsi
callq *0x8(%rax)
movq 0x20(%rsp), %r11
movb 0x73a4(%rbx), %al
cmpb $0x5, %al
je 0x352a
movl %r12d, %r13d
movzbl %al, %ecx
cmpl $0x4, %ecx
movq 0x10(%rsp), %r12
jne 0x3574
movq 0x7390(%rbx), %rax
movq 0x7440(%rbx), %rcx
movq 0x348(%rcx,%r14), %rsi
movq (%rax,%r12,8), %rax
movq %r11, %rbp
movq 0x20(%rax,%r11), %r9
movq %rbx, %rdi
movl 0xc(%rsp), %edx
movl %r13d, %ecx
xorl %r8d, %r8d
callq 0xfde0
jmp 0x3566
movq 0x7390(%rbx), %rax
movq 0x7440(%rbx), %rcx
movq 0x348(%rcx,%r14), %rsi
movq 0x10(%rsp), %rcx
movq (%rax,%rcx,8), %rax
movq %r11, %rbp
movq 0x20(%rax,%r11), %r9
movq %rbx, %rdi
movl 0xc(%rsp), %edx
movl %r12d, %r13d
movl %r12d, %ecx
xorl %r8d, %r8d
callq 0xfdd8
movb 0x73a4(%rbx), %al
movq %rbp, %r11
movq 0x10(%rsp), %r12
cmpb $0x6, %al
jne 0x35c7
movq 0x7390(%rbx), %rax
movq 0x7440(%rbx), %rcx
movq 0x348(%rcx,%r14), %r8
movq 0x370(%rcx,%r14), %r9
movq (%rax,%r12,8), %rax
movzbl 0x32f(%rcx,%r14), %r10d
subq $0x8, %rsp
movq %rbx, %rdi
movl %r15d, %esi
movl 0x14(%rsp), %edx
movl %r13d, %ecx
pushq $0x0
pushq %r10
pushq 0x20(%rax,%r11)
movq %r11, %rbp
callq 0xfcc8
jmp 0x3614
movq 0x7390(%rbx), %rax
movq 0x7440(%rbx), %rcx
movq 0x348(%rcx,%r14), %r8
movq 0x370(%rcx,%r14), %r9
movq (%rax,%r12,8), %rax
movzbl 0x32f(%rcx,%r14), %r10d
subq $0x8, %rsp
movq %rbx, %rdi
movl %r15d, %esi
movl 0x14(%rsp), %edx
movl %r13d, %ecx
pushq $0x0
pushq %r10
pushq 0x20(%rax,%r11)
movq %r11, %rbp
callq 0xfc4e
addq $0x20, %rsp
movq 0x7440(%rbx), %rcx
movzbl 0x32f(%rcx,%r14), %eax
movq %r15, %rdx
shlq $0x5, %rdx
addq %rbx, %rdx
incq 0x10328(%rdx,%rax,8)
addq %r14, %rcx
incq 0x102e8(%rdx,%rax,8)
movq %rbx, %rdi
movl 0xc(%rsp), %esi
movl %r13d, %edx
callq 0x2ec4
movq 0x7390(%rbx), %rax
movq (%rax,%r12,8), %rax
movb $0x1, 0x2(%rax,%rbp)
movq 0x7440(%rbx), %rsi
movl 0x8(%rsi,%r14), %eax
cmpl 0x7398(%rbx), %eax
jge 0x3692
addq %r14, %rsi
xorl %eax, %eax
cmpb $0x0, (%rsi)
sete %al
leaq (%rbx,%rax,8), %rax
movq 0x8(%rax,%r15,8), %rdi
movq (%rdi), %rax
callq *0x18(%rax)
movq 0x7440(%rbx), %rax
movzbl 0x32f(%rax,%r14), %ecx
incq 0x72e8(%rbx,%rcx,8)
leaq (%rax,%r14), %rsi
incq 0x72a8(%rbx,%rcx,8)
movq 0x18(%rsp), %rdi
callq 0x9cc0
jmp 0x301f
jne 0x3717
movzbl 0x32f(%r12,%r14), %eax
incq 0x7328(%rbx,%rax,8)
jmp 0x301f
movq 0x1290c(%rip), %rdi     # 0x15ff0
leaq 0xc9d4(%rip), %rsi      # 0x100bf
callq 0x2230
movq %rax, %rdi
callq 0x2110
leaq 0xc968(%rip), %rdi      # 0x10067
leaq 0xc963(%rip), %rsi      # 0x10069
leaq 0xc993(%rip), %rcx      # 0x100a0
movl $0x134, %edx            # imm = 0x134
callq 0x2160
movq 0x128d2(%rip), %rdi     # 0x15ff0
leaq 0xc96b(%rip), %rsi      # 0x10090
callq 0x2230
addq $0x7350, %rbx           # imm = 0x7350
movq %rax, %rdi
movq %rbx, %rsi
callq 0x21d0
leaq 0xc94f(%rip), %rsi      # 0x10092
movq %rax, %rdi
callq 0x2230
movq %rax, %rdi
callq 0x2110
leaq 0xc90d(%rip), %rdi      # 0x10067
leaq 0xc908(%rip), %rsi      # 0x10069
leaq 0xc938(%rip), %rcx      # 0x100a0
movl $0x11a, %edx            # imm = 0x11A
callq 0x2160