// File: /workspace/github_c_makefile_star2_O2/samtools[P]htslib/htscodecs/htscodecs/rANS_static32x16pr_avx2.c
// Function: rans_compress_O1_32x16_avx2
unsigned char *rans_compress_O1_32x16_avx2(unsigned char *in, unsigned int in_size,
                                           unsigned char *out, unsigned int *out_size) {
    unsigned char *cp, *out_end, *out_free = NULL;
    unsigned int tab_size;
    uint32_t bound = rans_compress_bound_4x16(in_size,1)-20;
    int z;
    RansState ransN[NX] __attribute__((aligned(32)));

    if (in_size < NX) // force O0 instead
        return NULL;

    if (!out) {
        *out_size = bound;
        out = malloc(*out_size);
    }
    if (!out || bound > *out_size)
        return NULL;

    if (((size_t)out)&1)
        bound--;
    out_end = out + bound;

    RansEncSymbol (*syms)[256] = htscodecs_tls_alloc(256 * (sizeof(*syms)));
    if (!syms) {
        free(out_free);
        return NULL;
    }

    cp = out;
    int shift = encode_freq1(in, in_size, 32, syms, &cp); 
    if (shift < 0) {
        free(out_free);
        htscodecs_tls_free(syms);
        return NULL;
    }
    tab_size = cp - out;

    for (z = 0; z < NX; z++)
      RansEncInit(&ransN[z]);

    uint8_t* ptr = out_end;

    int iN[NX], isz4 = in_size/NX;
    for (z = 0; z < NX; z++)
        iN[z] = (z+1)*isz4-2;

    unsigned char lN[NX];
    for (z = 0; z < NX; z++)
        lN[z] = in[iN[z]+1];

    // Deal with the remainder
    z = NX-1;
    lN[z] = in[in_size-1];
    for (iN[z] = in_size-2; iN[z] > NX*isz4-2; iN[z]--) {
        unsigned char c = in[iN[z]];
        RansEncPutSymbol(&ransN[z], &ptr, &syms[c][lN[z]]);
        lN[z] = c;
    }

    uint16_t *ptr16 = (uint16_t *)ptr;

//       clang16      clang10      gcc7         gcc13
//       587 435 381  588 438 403  504 386 415  527 381 394
// simT  611 432 402  475 401 367  472 422 386  486 353 324

    LOAD(Rv, ransN);

    for (; iN[0] >= 0; ) {
        // We need to gather sym[curr_char][last_char] structs.
        // These hold 4 32-bit values, so are 128 bit each, and
        // are loaded from 32 distinct addresses.
        //
        // We load them into 32 128-bit lanes and then combine to get
        // 16 avx-256 registers.
        // These are now ABCD ABCD ABCD ABCD... orientation
        // Code we can then "gather" from these registers via a combination
        // of shuffle / permutes / and / or operations.  This is less
        // IO than repeating 4 sets of gathers/loads 32-times over.

        // DCBA holding 4 elements in a syms[] array
        // -> 4-way rotate via shuffles
        // [0] DCBA  11 10 01 00  E4
        // [1] CBAD  10 01 00 11  93
        // [2] BADC  01 00 11 10  4E
        // [3] ADCB  00 11 10 01  39
        //
        // Then AND to select relevant lanes and OR
        // [0] ......A0
        // [1] ....A1..
        // [2] ..A2....
        // [3] A3......  OR to get A3A2A1A0
        //
        // or:
        // [0] ....B0..
        // [1] ..B1....
        // [2] B2......
        // [3] ......B3  OR to get B2B1B0B3 and shuffle to B3B2B1B0

        __m256i xmaxv[4];
        __m256i rfv[4];
        __m256i SDv[4];
        __m256i biasv[4];

        const __m256i xA = _mm256_set_epi32(0,0,0,-1, 0,0,0,-1);
        const __m256i xB = _mm256_set_epi32(0,0,-1,0, 0,0,-1,0);
        const __m256i xC = _mm256_set_epi32(0,-1,0,0, 0,-1,0,0);
        const __m256i xD = _mm256_set_epi32(-1,0,0,0, -1,0,0,0);

        for (z = 0; z < 32; z += 8) {
#define m128_to_256 _mm256_castsi128_si256
            __m128i *s0 = (__m128i *)(&syms[in[iN[z+0]]][lN[z+0]]);
            __m128i *s1 = (__m128i *)(&syms[in[iN[z+4]]][lN[z+4]]);
            __m128i *s2 = (__m128i *)(&syms[in[iN[z+1]]][lN[z+1]]);
            __m128i *s3 = (__m128i *)(&syms[in[iN[z+5]]][lN[z+5]]);

            __m256i t0, t1, t2, t3;
            t0 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s0)), 0xE4);
            t1 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s1)), 0xE4);
            t2 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s2)), 0x93);
            t3 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s3)), 0x93);

            __m256i sh0 = _mm256_permute2x128_si256(t0, t1, 0x20);
            __m256i sh1 = _mm256_permute2x128_si256(t2, t3, 0x20);

            lN[z+0] = in[iN[z+0]];
            lN[z+4] = in[iN[z+4]];
            lN[z+1] = in[iN[z+1]];
            lN[z+5] = in[iN[z+5]];

            // Initialise first half of xmax, rf, SD and bias vectors
            __m128i *s4 = (__m128i *)(&syms[in[iN[z+2]]][lN[z+2]]);
            __m128i *s5 = (__m128i *)(&syms[in[iN[z+6]]][lN[z+6]]);
            __m128i *s6 = (__m128i *)(&syms[in[iN[z+3]]][lN[z+3]]);
            __m128i *s7 = (__m128i *)(&syms[in[iN[z+7]]][lN[z+7]]);

            __m256i t4, t5, t6, t7;
            t4 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s4)), 0x4E);
            t5 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s5)), 0x4E);
            t6 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s6)), 0x39);
            t7 = _mm256_shuffle_epi32(m128_to_256(_mm_loadu_si128(s7)), 0x39);

            __m256i sh2 = _mm256_permute2x128_si256(t4, t5, 0x20);
            __m256i sh3 = _mm256_permute2x128_si256(t6, t7, 0x20);

            lN[z+2] = in[iN[z+2]];
            lN[z+6] = in[iN[z+6]];
            lN[z+3] = in[iN[z+3]];
            lN[z+7] = in[iN[z+7]];

#define SH_LOAD(A, B, C, D)                                        \
            _mm256_or_si256(_mm256_or_si256(_mm256_and_si256(sh0, A), \
                                            _mm256_and_si256(sh1, B)),\
                            _mm256_or_si256(_mm256_and_si256(sh2, C), \
                                            _mm256_and_si256(sh3, D)))
            xmaxv[z/8] = SH_LOAD(xA, xB, xC, xD);
            rfv  [z/8] = SH_LOAD(xB, xC, xD, xA);
            SDv  [z/8] = SH_LOAD(xD, xA, xB, xC);
            biasv[z/8] = SH_LOAD(xC, xD, xA, xB);

            rfv  [z/8] = _mm256_shuffle_epi32(rfv  [z/8],  0x39);
            SDv  [z/8] = _mm256_shuffle_epi32(SDv  [z/8],  0x93);
            biasv[z/8] = _mm256_shuffle_epi32(biasv[z/8],0x4E);
        }

        // ------------------------------------------------------------
        //      for (z = NX-1; z >= 0; z--) {
        //          if (ransN[z] >= x_max[z]) {
        //              *--ptr16 = ransN[z] & 0xffff;
        //              ransN[z] >>= 16;
        //          }
        //      }
        __m256i cv1 = _mm256_cmpgt_epi32(Rv1, xmaxv[0]);
        __m256i cv2 = _mm256_cmpgt_epi32(Rv2, xmaxv[1]);
        __m256i cv3 = _mm256_cmpgt_epi32(Rv3, xmaxv[2]);
        __m256i cv4 = _mm256_cmpgt_epi32(Rv4, xmaxv[3]);

        // Store bottom 16-bits at ptr16
        //
        // for (z = NX-1; z >= 0; z--) {
        //     if (cond[z]) *--ptr16 = (uint16_t )(ransN[z] & 0xffff);
        // }
        unsigned int imask1 = _mm256_movemask_ps((__m256)cv1);
        unsigned int imask2 = _mm256_movemask_ps((__m256)cv2);
        unsigned int imask3 = _mm256_movemask_ps((__m256)cv3);
        unsigned int imask4 = _mm256_movemask_ps((__m256)cv4);

        __m256i idx1 = _mm256_load_si256((const __m256i*)permutec[imask1]);
        __m256i idx2 = _mm256_load_si256((const __m256i*)permutec[imask2]);
        __m256i idx3 = _mm256_load_si256((const __m256i*)permutec[imask3]);
        __m256i idx4 = _mm256_load_si256((const __m256i*)permutec[imask4]);

        // Permute; to gather together the rans states that need flushing
        __m256i V1, V2, V3, V4;
        V1 = _mm256_permutevar8x32_epi32(_mm256_and_si256(Rv1, cv1), idx1);
        V2 = _mm256_permutevar8x32_epi32(_mm256_and_si256(Rv2, cv2), idx2);
        V3 = _mm256_permutevar8x32_epi32(_mm256_and_si256(Rv3, cv3), idx3);
        V4 = _mm256_permutevar8x32_epi32(_mm256_and_si256(Rv4, cv4), idx4);

        // We only flush bottom 16 bits, to squash 32-bit states into 16 bit.
        V1 = _mm256_and_si256(V1, _mm256_set1_epi32(0xffff));
        V2 = _mm256_and_si256(V2, _mm256_set1_epi32(0xffff));
        V3 = _mm256_and_si256(V3, _mm256_set1_epi32(0xffff));
        V4 = _mm256_and_si256(V4, _mm256_set1_epi32(0xffff));
        __m256i V12 = _mm256_packus_epi32(V1, V2);
        __m256i V34 = _mm256_packus_epi32(V3, V4);

        // It's BAba order, want BbAa so shuffle.
        V12 = _mm256_permute4x64_epi64(V12, 0xd8);
        V34 = _mm256_permute4x64_epi64(V34, 0xd8);

        // Now we have bottom N 16-bit values in each V12/V34 to flush
        __m128i f =  _mm256_extractf128_si256(V34, 1);
        _mm_storeu_si128((__m128i *)(ptr16-8), f);
        ptr16 -= _mm_popcnt_u32(imask4);

        f =  _mm256_extractf128_si256(V34, 0);
        _mm_storeu_si128((__m128i *)(ptr16-8), f);
        ptr16 -= _mm_popcnt_u32(imask3);

        f =  _mm256_extractf128_si256(V12, 1);
        _mm_storeu_si128((__m128i *)(ptr16-8), f);
        ptr16 -= _mm_popcnt_u32(imask2);

        f =  _mm256_extractf128_si256(V12, 0);
        _mm_storeu_si128((__m128i *)(ptr16-8), f);
        ptr16 -= _mm_popcnt_u32(imask1);

        __m256i Rs1, Rs2, Rs3, Rs4;
        Rs1 = _mm256_srli_epi32(Rv1,16);
        Rs2 = _mm256_srli_epi32(Rv2,16);
        Rs3 = _mm256_srli_epi32(Rv3,16);
        Rs4 = _mm256_srli_epi32(Rv4,16);

        Rv1 = _mm256_blendv_epi8(Rv1, Rs1, cv1);
        Rv2 = _mm256_blendv_epi8(Rv2, Rs2, cv2);
        Rv3 = _mm256_blendv_epi8(Rv3, Rs3, cv3);
        Rv4 = _mm256_blendv_epi8(Rv4, Rs4, cv4);

        // ------------------------------------------------------------
        // uint32_t q = (uint32_t) (((uint64_t)ransN[z] *
        //                           rcp_freq[z]) >> rcp_shift[z]);
        // ransN[z] = ransN[z] + bias[z] + q * cmpl_freq[z];

        // Cannot trivially replace the multiply as mulhi_epu32 doesn't exist
        // (only mullo).  However we can use _mm256_mul_epu32 twice to get
        // 64bit results (half our lanes) and shift/or to get the answer.
        //
        // (AVX512 allows us to hold it all in 64-bit lanes and use mullo_epi64
        // plus a shift.  KNC has mulhi_epi32, but not sure if this is
        // available.)
        rfv[0] = _mm256_mulhi_epu32(Rv1, rfv[0]);
        rfv[1] = _mm256_mulhi_epu32(Rv2, rfv[1]);
        rfv[2] = _mm256_mulhi_epu32(Rv3, rfv[2]);
        rfv[3] = _mm256_mulhi_epu32(Rv4, rfv[3]);

        __m256i shiftv1 = _mm256_srli_epi32(SDv[0], 16);
        __m256i shiftv2 = _mm256_srli_epi32(SDv[1], 16);
        __m256i shiftv3 = _mm256_srli_epi32(SDv[2], 16);
        __m256i shiftv4 = _mm256_srli_epi32(SDv[3], 16);

        shiftv1 = _mm256_sub_epi32(shiftv1, _mm256_set1_epi32(32));
        shiftv2 = _mm256_sub_epi32(shiftv2, _mm256_set1_epi32(32));
        shiftv3 = _mm256_sub_epi32(shiftv3, _mm256_set1_epi32(32));
        shiftv4 = _mm256_sub_epi32(shiftv4, _mm256_set1_epi32(32));

        __m256i qv1 = _mm256_srlv_epi32(rfv[0], shiftv1);
        __m256i qv2 = _mm256_srlv_epi32(rfv[1], shiftv2);

        __m256i freqv1 = _mm256_and_si256(SDv[0], _mm256_set1_epi32(0xffff));
        __m256i freqv2 = _mm256_and_si256(SDv[1], _mm256_set1_epi32(0xffff));
        qv1 = _mm256_mullo_epi32(qv1, freqv1);
        qv2 = _mm256_mullo_epi32(qv2, freqv2);

        __m256i qv3 = _mm256_srlv_epi32(rfv[2], shiftv3);
        __m256i qv4 = _mm256_srlv_epi32(rfv[3], shiftv4);

        __m256i freqv3 = _mm256_and_si256(SDv[2], _mm256_set1_epi32(0xffff));
        __m256i freqv4 = _mm256_and_si256(SDv[3], _mm256_set1_epi32(0xffff));
        qv3 = _mm256_mullo_epi32(qv3, freqv3);
        qv4 = _mm256_mullo_epi32(qv4, freqv4);

        qv1 = _mm256_add_epi32(qv1, biasv[0]);
        qv2 = _mm256_add_epi32(qv2, biasv[1]);
        qv3 = _mm256_add_epi32(qv3, biasv[2]);
        qv4 = _mm256_add_epi32(qv4, biasv[3]);

        for (z = 0; z < NX; z++)
            iN[z]--;

        Rv1 = _mm256_add_epi32(Rv1, qv1);
        Rv2 = _mm256_add_epi32(Rv2, qv2);
        Rv3 = _mm256_add_epi32(Rv3, qv3);
        Rv4 = _mm256_add_epi32(Rv4, qv4);
    }

    STORE(Rv, ransN);

    ptr = (uint8_t *)ptr16;

    for (z = NX-1; z>=0; z--)
        RansEncPutSymbol(&ransN[z], &ptr, &syms[0][lN[z]]);

    for (z = NX-1; z>=0; z--)
        RansEncFlush(&ransN[z], &ptr);

    *out_size = (out_end - ptr) + tab_size;

    cp = out;
    memmove(out + tab_size, ptr, out_end-ptr);

    htscodecs_tls_free(syms);
    return out;
}

// Assembly:
pushq %rbp
movq %rsp, %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
andq $-0x20, %rsp
subq $0xb80, %rsp            # imm = 0xB80
movq %rcx, %rbx
movq %rdx, %r12
movl %esi, %r14d
movq %rdi, %r15
pushq $0x1
popq %rsi
movl %r14d, %edi
callq 0x4edbc
movq %r14, 0xe0(%rsp)
cmpl $0x20, %r14d
jb 0x5477f
movl %eax, %ecx
movq %rbx, 0x70(%rsp)
leal -0x14(%rcx), %ebx
testq %r12, %r12
je 0x54151
movq 0x70(%rsp), %rax
cmpl (%rax), %ebx
jbe 0x54171
jmp 0x5477f
movq 0x70(%rsp), %rax
movl %ebx, (%rax)
movl %ebx, %edi
movq %rcx, %r14
callq 0x4680
movq %r14, %rcx
movq %rax, %r12
testq %rax, %rax
je 0x5477f
addl $-0x15, %ecx
testb $0x1, %r12b
cmovel %ebx, %ecx
movq %rcx, 0xb8(%rsp)
movl $0x100000, %edi         # imm = 0x100000
callq 0x6412c
movq %rax, 0x20(%rsp)
testq %rax, %rax
je 0x5477f
movl $0x100, %edi            # imm = 0x100
movl $0x400, %esi            # imm = 0x400
callq 0x6426c
testq %rax, %rax
je 0x54775
movq %rax, 0x80(%rsp)
leaq 0x340(%rsp), %rdi
movl $0x420, %edx            # imm = 0x420
xorl %esi, %esi
callq 0x4260
movq 0xe0(%rsp), %rax
movl %eax, %r14d
shrl $0x5, %r14d
movl %eax, %ebx
addq %r15, %rbx
cmpl $0x7a120, %eax          # imm = 0x7A120
movq %r12, 0x68(%rsp)
jbe 0x54328
movl $0x100, %edi            # imm = 0x100
movl $0x40c, %esi            # imm = 0x40C
callq 0x6426c
testq %rax, %rax
je 0x54738
leaq -0x8(%rbx), %rdx
xorl %esi, %esi
movq %r15, %rcx
movq 0x80(%rsp), %r11
cmpq %rdx, %rcx
jae 0x542c6
movzbl (%rcx), %r8d
movzbl 0x1(%rcx), %r9d
movzbl 0x2(%rcx), %r10d
movzbl 0x3(%rcx), %edi
movzbl %sil, %esi
shll $0xa, %esi
addq %r11, %rsi
incl (%rsi,%r8,4)
imulq $0x40c, %r8, %rsi       # imm = 0x40C
addq %rax, %rsi
incl (%rsi,%r9,4)
shll $0xa, %r9d
addq %r11, %r9
incl (%r9,%r10,4)
imulq $0x40c, %r10, %rsi      # imm = 0x40C
addq %rax, %rsi
incl (%rsi,%rdi,4)
movzbl 0x4(%rcx), %r8d
movzbl 0x5(%rcx), %r9d
movzbl 0x6(%rcx), %r10d
movzbl 0x7(%rcx), %esi
shll $0xa, %edi
addq %r11, %rdi
incl (%rdi,%r8,4)
imulq $0x40c, %r8, %rdi       # imm = 0x40C
addq %rax, %rdi
incl (%rdi,%r9,4)
addq $0x8, %rcx
shll $0xa, %r9d
addq %r11, %r9
incl (%r9,%r10,4)
imulq $0x40c, %r10, %rdi      # imm = 0x40C
addq %rax, %rdi
incl (%rdi,%rsi,4)
jmp 0x5421c
movzbl (%rcx), %esi
incq %rcx
shll $0xa, %edx
addq %r11, %rdx
incl (%rdx,%rsi,4)
movzbl %sil, %edx
cmpq %rbx, %rcx
jb 0x542b7
incl 0x340(%rsp,%rdx,4)
xorl %ecx, %ecx
movq %rax, %rdx
movq %r11, %rsi
cmpq $0x100, %rcx            # imm = 0x100
je 0x54416
xorl %edi, %edi
xorl %r8d, %r8d
cmpq $0x100, %rdi            # imm = 0x100
je 0x5430d
movl (%rsi,%rdi,4), %r9d
addl (%rdx,%rdi,4), %r9d
movl %r9d, (%rsi,%rdi,4)
addl %r9d, %r8d
incq %rdi
jmp 0x542f0
addl %r8d, 0x340(%rsp,%rcx,4)
incq %rcx
addq $0x400, %rsi            # imm = 0x400
addq $0x40c, %rdx            # imm = 0x40C
jmp 0x542de
leaq -0x8(%rbx), %rcx
xorl %edx, %edx
movq %r15, %rax
movq 0x80(%rsp), %r10
cmpq %rcx, %rax
jae 0x543d2
movzbl (%rax), %r8d
movzbl 0x1(%rax), %r9d
movzbl 0x2(%rax), %edi
movzbl 0x3(%rax), %esi
movzbl %dl, %edx
shll $0xa, %edx
addq %r10, %rdx
incl (%rdx,%r8,4)
shll $0xa, %r8d
addq %r10, %r8
incl (%r8,%r9,4)
shll $0xa, %r9d
addq %r10, %r9
incl (%r9,%rdi,4)
shll $0xa, %edi
addq %r10, %rdi
incl (%rdi,%rsi,4)
movzbl 0x4(%rax), %r8d
movzbl 0x5(%rax), %r9d
movzbl 0x6(%rax), %edi
movzbl 0x7(%rax), %edx
shll $0xa, %esi
addq %r10, %rsi
incl (%rsi,%r8,4)
shll $0xa, %r8d
addq %r10, %r8
incl (%r8,%r9,4)
addq $0x8, %rax
shll $0xa, %r9d
addq %r10, %r9
incl (%r9,%rdi,4)
shll $0xa, %edi
addq %r10, %rdi
incl (%rdi,%rdx,4)
jmp 0x54339
movzbl (%rax), %edx
incq %rax
shll $0xa, %ecx
addq %r10, %rcx
incl (%rcx,%rdx,4)
movzbl %dl, %ecx
cmpq %rbx, %rax
jb 0x543c3
incl 0x340(%rsp,%rcx,4)
xorl %eax, %eax
movq %r10, %rcx
cmpq $0x100, %rax            # imm = 0x100
je 0x54426
xorl %edx, %edx
xorl %esi, %esi
cmpq $0x100, %rdx            # imm = 0x100
je 0x54403
addl (%rcx,%rdx,4), %esi
incq %rdx
jmp 0x543f2
addl %esi, 0x340(%rsp,%rax,4)
incq %rax
addq $0x400, %rcx            # imm = 0x400
jmp 0x543e6
movq %rax, %rdi
callq 0x64291
movq 0x80(%rsp), %r10
movl %r14d, %eax
leaq (%r15,%rax), %rcx
pushq $0x1f
popq %rdx
subq $0x1, %rdx
jb 0x54442
movzbl (%rcx), %esi
incl (%r10,%rsi,4)
addq %rax, %rcx
jmp 0x54430
movq %r14, 0x58(%rsp)
movq %r15, 0x60(%rsp)
leaq 0x340(%rsp), %rbx
movl (%rbx), %r14d
addl $0x1f, %r14d
pushq $0x1
popq %r13
movl %r13d, (%rbx)
leaq 0x1(%r12), %rdi
movb $0x0, (%r12)
movq %rdi, 0x50(%rsp)
movq %rbx, %rsi
callq 0x56483
cltq
leaq (%r12,%rax), %r15
incq %r15
movl %r14d, (%rbx)
leaq 0x760(%rsp), %r14
movl $0x400, %edx            # imm = 0x400
movq %r14, %rdi
xorl %esi, %esi
callq 0x4260
movq %rbx, %rdi
movq 0x80(%rsp), %rsi
movq %rbx, %rdx
movq %r14, %rcx
xorl %r14d, %r14d
callq 0x4fa19
movq 0x80(%rsp), %rdi
movl %eax, %ecx
shll %cl, %r13d
movl %r13d, 0x78(%rsp)
movq 0x20(%rsp), %rax
movq %rdi, %r12
movl %ecx, 0xc0(%rsp)
cmpq $0x100, %r14            # imm = 0x100
je 0x54657
movl 0x340(%rsp,%r14,4), %esi
testl %esi, %esi
je 0x54642
movq %rax, 0x120(%rsp)
movl 0x760(%rsp,%r14,4), %eax
movl $0x400, %edx            # imm = 0x400
cmpl %edx, %eax
movl $0x400, %ebx            # imm = 0x400
cmovbl %eax, %ebx
cmpl $0xa, %ecx
cmovnel %eax, %ebx
movq %r14, %r13
shlq $0xa, %r13
addq %rdi, %r13
movq %r13, %rdi
movl %ebx, %edx
callq 0x537ee
testl %eax, %eax
js 0x5470c
movq %r14, 0x100(%rsp)
movl %ebx, 0x340(%rsp,%r14,4)
xorl %ebx, %ebx
movq %r15, 0x18(%rsp)
xorl %eax, %eax
cmpq $0x100, %rbx            # imm = 0x100
je 0x5459c
cmpl $0x0, 0x340(%rsp,%rbx,4)
je 0x54597
movl (%r12,%rbx,4), %esi
testl %esi, %esi
je 0x5458e
testl %eax, %eax
je 0x5457d
decl %eax
cltq
subq %rax, %r15
movb %al, (%r15)
incq %r15
movl (%r12,%rbx,4), %esi
movq %r15, %rdi
callq 0x56501
movl %eax, %eax
addq %rax, %r15
xorl %eax, %eax
jmp 0x54597
incl %eax
movb $0x0, (%r15)
incq %r15
incq %rbx
jmp 0x5454d
testl %eax, %eax
je 0x545ad
decl %eax
cltq
subq %rax, %r15
movb %al, (%r15)
incq %r15
subl 0x18(%rsp), %r15d
shlq $0x20, %r15
movq 0x100(%rsp), %r14
movl 0x340(%rsp,%r14,4), %esi
movq %r13, %rdi
movl 0x78(%rsp), %ebx
movl %ebx, %edx
callq 0x54045
movl %ebx, 0x340(%rsp,%r14,4)
xorl %r13d, %r13d
movq 0x120(%rsp), %r14
xorl %ebx, %ebx
cmpq $0x100, %r13            # imm = 0x100
je 0x54614
movl (%r12,%r13,4), %edx
movq %r14, %rdi
movl %ebx, %esi
movl 0xc0(%rsp), %ecx
callq 0x53911
addl (%r12,%r13,4), %ebx
incq %r13
addq $0x10, %r14
jmp 0x545e9
sarq $0x20, %r15
movq 0x18(%rsp), %rax
addq %r15, %rax
movq %rax, %r15
movq 0x80(%rsp), %rdi
movl 0xc0(%rsp), %ecx
movq 0x100(%rsp), %r14
movq 0x120(%rsp), %rax
incq %r14
addq $0x400, %r12            # imm = 0x400
addq $0x1000, %rax           # imm = 0x1000
jmp 0x544d6
movl %ecx, %eax
shlb $0x4, %al
movq 0x68(%rsp), %r12
movb %al, (%r12)
movq %r15, %rbx
subq %r12, %rbx
cmpq $0x3e9, %rbx            # imm = 0x3E9
movq %r15, 0x18(%rsp)
jl 0x54725
movq 0x50(%rsp), %rdi
subl %edi, %r15d
leaq 0x140(%rsp), %rcx
movl %r15d, %esi
xorl %edx, %edx
callq 0x4ee61
movq %rax, %r14
testq %rax, %rax
je 0x546f0
movl 0x140(%rsp), %r13d
leal 0x6(%r13), %eax
cmpq %rax, %rbx
jbe 0x546f0
orb $0x1, (%r12)
movq 0x50(%rsp), %rdi
movl %r15d, %esi
callq 0x56501
movl %eax, %ebx
addq 0x50(%rsp), %rbx
movq %rbx, %rdi
movl %r13d, %esi
callq 0x56501
movl %eax, %r15d
addq %rbx, %r15
movq %r15, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq 0x43c0
addq %r13, %r15
movq %r15, 0x18(%rsp)
movq %r14, %rdi
callq 0x45c0
movq 0x60(%rsp), %r15
movq 0x58(%rsp), %r14
movq 0x80(%rsp), %rdi
jmp 0x5472f
movq 0x68(%rsp), %r12
movq %r12, 0x18(%rsp)
pushq $-0x1
popq %rbx
movq 0x60(%rsp), %r15
movq 0x58(%rsp), %r14
jmp 0x54740
movq 0x60(%rsp), %r15
movq 0x58(%rsp), %r14
movl 0xc0(%rsp), %ebx
jmp 0x54748
movq %r12, 0x18(%rsp)
pushq $-0x1
popq %rbx
movq 0x80(%rsp), %rdi
callq 0x64291
testl %ebx, %ebx
js 0x54775
movq 0xb8(%rsp), %rax
leaq (%r12,%rax), %rdx
xorl %eax, %eax
cmpq $0x20, %rax
je 0x54794
movl $0x8000, 0x340(%rsp,%rax,4) # imm = 0x8000
incq %rax
jmp 0x5475f
movq 0x20(%rsp), %rdi
callq 0x64291
xorl %r12d, %r12d
movq %r12, %rax
leaq -0x28(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq %rdx, 0x28(%rsp)
leal -0x2(%r14), %eax
xorl %ecx, %ecx
cmpq $0x20, %rcx
je 0x547b4
movl %eax, 0x760(%rsp,%rcx,4)
incq %rcx
addl %r14d, %eax
jmp 0x5479f
xorl %eax, %eax
cmpq $0x20, %rax
je 0x547d2
movslq 0x760(%rsp,%rax,4), %rcx
movb 0x1(%r15,%rcx), %cl
movb %cl, 0x30(%rsp,%rax)
incq %rax
jmp 0x547b6
movq %rdx, 0x78(%rsp)
movq 0xe0(%rsp), %rbx
leal -0x1(%rbx), %eax
movq %r15, %r14
movb (%r15,%rax), %al
leal -0x2(%rbx), %r12d
andl $-0x20, %ebx
addl $-0x2, %ebx
leaq 0x28(%rsp), %r15
cmpl %ebx, %r12d
jle 0x54831
movl %r12d, %ecx
movzbl (%r14,%rcx), %r13d
movl %r13d, %ecx
shll $0xc, %ecx
movzbl %al, %edx
shll $0x4, %edx
addq 0x20(%rsp), %rdx
addq %rcx, %rdx
leaq 0x3bc(%rsp), %rdi
movq %r15, %rsi
callq 0x53a08
decl %r12d
movl %r13d, %eax
jmp 0x547f8
movl %r12d, 0x7dc(%rsp)
movb %al, 0x4f(%rsp)
movq 0x28(%rsp), %rax
vmovdqa 0x340(%rsp), %ymm1
vmovdqa 0x360(%rsp), %ymm2
vmovdqa 0x380(%rsp), %ymm4
vmovdqa 0x3a0(%rsp), %ymm3
vpxor %xmm0, %xmm0, %xmm0
leaq 0x294af(%rip), %rcx     # 0x7dd20
movq 0x68(%rsp), %r12
movq 0x70(%rsp), %rbx
movq 0x20(%rsp), %r13
cmpl $0x0, 0x760(%rsp)
js 0x54ded
xorl %edx, %edx
cmpq $0x1f, %rdx
ja 0x54af2
movslq 0x760(%rsp,%rdx,4), %rsi
movzbl (%r14,%rsi), %esi
movzbl 0x30(%rsp,%rdx), %r8d
movl %esi, %r9d
shll $0xc, %r9d
addq %r13, %r9
shll $0x4, %r8d
movslq 0x770(%rsp,%rdx,4), %rdi
movzbl (%r14,%rdi), %edi
movzbl 0x34(%rsp,%rdx), %r10d
movl %edi, %r11d
shll $0xc, %r11d
addq %r13, %r11
shll $0x4, %r10d
vmovdqu (%r8,%r9), %xmm5
movslq 0x764(%rsp,%rdx,4), %r8
movzbl (%r14,%r8), %r8d
movzbl 0x31(%rsp,%rdx), %r9d
vinserti128 $0x1, (%r10,%r11), %ymm5, %ymm5
movl %r8d, %r10d
shll $0xc, %r10d
addq %r13, %r10
shll $0x4, %r9d
movslq 0x774(%rsp,%rdx,4), %r11
movzbl (%r14,%r11), %r11d
vmovdqu (%r9,%r10), %xmm6
movzbl 0x35(%rsp,%rdx), %r9d
movl %r11d, %r10d
shll $0xc, %r10d
addq %r13, %r10
shll $0x4, %r9d
vinserti128 $0x1, (%r9,%r10), %ymm6, %ymm6
movb %sil, 0x30(%rsp,%rdx)
movb %dil, 0x34(%rsp,%rdx)
movb %r8b, 0x31(%rsp,%rdx)
movb %r11b, 0x35(%rsp,%rdx)
movslq 0x768(%rsp,%rdx,4), %rsi
movzbl (%r14,%rsi), %esi
movzbl 0x32(%rsp,%rdx), %r10d
movl %esi, %r11d
shll $0xc, %r11d
addq %r13, %r11
shll $0x4, %r10d
movslq 0x778(%rsp,%rdx,4), %rdi
movzbl (%r14,%rdi), %edi
movzbl 0x36(%rsp,%rdx), %r9d
movslq 0x76c(%rsp,%rdx,4), %r8
movzbl (%r14,%r8), %r8d
vmovdqu (%r10,%r11), %xmm7
movzbl 0x33(%rsp,%rdx), %r10d
movl %r8d, %r11d
shll $0xc, %r11d
addq %r13, %r11
shll $0x4, %r10d
vmovdqu (%r10,%r11), %xmm8
movl %edi, %r10d
shll $0xc, %r10d
addq %r13, %r10
shll $0x4, %r9d
movslq 0x77c(%rsp,%rdx,4), %r11
movzbl (%r14,%r11), %r11d
vinserti128 $0x1, (%r9,%r10), %ymm7, %ymm7
movzbl 0x37(%rsp,%rdx), %r9d
movl %r11d, %r10d
shll $0xc, %r10d
addq %r13, %r10
shll $0x4, %r9d
vinserti128 $0x1, (%r9,%r10), %ymm8, %ymm8
movb %sil, 0x32(%rsp,%rdx)
movb %dil, 0x36(%rsp,%rdx)
movb %r8b, 0x33(%rsp,%rdx)
movb %r11b, 0x37(%rsp,%rdx)
vpshufd $0x93, %ymm6, %ymm9     # ymm9 = ymm6[3,0,1,2,7,4,5,6]
vpshufd $0x4e, %ymm7, %ymm10    # ymm10 = ymm7[2,3,0,1,6,7,4,5]
vpshufd $0x39, %ymm8, %ymm11    # ymm11 = ymm8[1,2,3,0,5,6,7,4]
vpblendd $0x11, %ymm5, %ymm0, %ymm12 # ymm12 = ymm5[0],ymm0[1,2,3],ymm5[4],ymm0[5,6,7]
vpblendd $0x22, %ymm9, %ymm0, %ymm13 # ymm13 = ymm0[0],ymm9[1],ymm0[2,3,4],ymm9[5],ymm0[6,7]
vpor %ymm12, %ymm13, %ymm12
vpblendd $0x44, %ymm10, %ymm0, %ymm10 # ymm10 = ymm0[0,1],ymm10[2],ymm0[3,4,5],ymm10[6],ymm0[7]
vpslldq $0xc, %ymm8, %ymm13     # ymm13 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm8[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm8[16,17,18,19]
vpor %ymm13, %ymm10, %ymm10
vpor %ymm10, %ymm12, %ymm10
vmovdqa %ymm10, 0x140(%rsp,%rdx,4)
vpblendd $0x44, %ymm5, %ymm0, %ymm10 # ymm10 = ymm0[0,1],ymm5[2],ymm0[3,4,5],ymm5[6],ymm0[7]
vpblendd $0x88, %ymm9, %ymm0, %ymm9 # ymm9 = ymm0[0,1,2],ymm9[3],ymm0[4,5,6],ymm9[7]
vpblendd $0x22, %ymm11, %ymm0, %ymm12 # ymm12 = ymm0[0],ymm11[1],ymm0[2,3,4],ymm11[5],ymm0[6,7]
vpblendd $0x22, %ymm6, %ymm0, %ymm13 # ymm13 = ymm0[0],ymm6[1],ymm0[2,3,4],ymm6[5],ymm0[6,7]
vpshufd $0x55, %ymm5, %ymm14    # ymm14 = ymm5[1,1,1,1,5,5,5,5]
vpblendd $0x11, %ymm14, %ymm0, %ymm14 # ymm14 = ymm14[0],ymm0[1,2,3],ymm14[4],ymm0[5,6,7]
vpor %ymm14, %ymm13, %ymm13
vpshufd $0x55, %ymm7, %ymm14    # ymm14 = ymm7[1,1,1,1,5,5,5,5]
vpblendd $0x44, %ymm14, %ymm0, %ymm14 # ymm14 = ymm0[0,1],ymm14[2],ymm0[3,4,5],ymm14[6],ymm0[7]
vpslldq $0xc, %ymm11, %ymm11    # ymm11 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm11[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm11[16,17,18,19]
vpor %ymm11, %ymm14, %ymm11
vpor %ymm11, %ymm13, %ymm11
vmovdqa %ymm11, 0x2c0(%rsp,%rdx,4)
vpshufd $0xff, %ymm6, %ymm6     # ymm6 = ymm6[3,3,3,3,7,7,7,7]
vpblendd $0x22, %ymm6, %ymm0, %ymm6 # ymm6 = ymm0[0],ymm6[1],ymm0[2,3,4],ymm6[5],ymm0[6,7]
vpsrldq $0xc, %ymm5, %ymm5      # ymm5 = ymm5[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm5[28,29,30,31],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
vpor %ymm5, %ymm6, %ymm5
vpshufd $0xff, %ymm7, %ymm6     # ymm6 = ymm7[3,3,3,3,7,7,7,7]
vpblendd $0x44, %ymm6, %ymm0, %ymm6 # ymm6 = ymm0[0,1],ymm6[2],ymm0[3,4,5],ymm6[6],ymm0[7]
vpor %ymm6, %ymm5, %ymm5
vpblendd $0x88, %ymm8, %ymm5, %ymm5 # ymm5 = ymm5[0,1,2],ymm8[3],ymm5[4,5,6],ymm8[7]
vmovdqa %ymm5, 0x240(%rsp,%rdx,4)
vpshufd $0x4e, %ymm10, %ymm5    # ymm5 = ymm10[2,3,0,1,6,7,4,5]
vpshufd $0x4e, %ymm9, %ymm6     # ymm6 = ymm9[2,3,0,1,6,7,4,5]
vpblendd $0xbb, %ymm0, %ymm7, %ymm7 # ymm7 = ymm0[0,1],ymm7[2],ymm0[3,4,5],ymm7[6],ymm0[7]
vpor %ymm7, %ymm5, %ymm5
vpor %ymm5, %ymm6, %ymm5
vpshufd $0x4e, %ymm12, %ymm6    # ymm6 = ymm12[2,3,0,1,6,7,4,5]
vpor %ymm6, %ymm5, %ymm5
vmovdqa %ymm5, 0x1c0(%rsp,%rdx,4)
addq $0x8, %rdx
jmp 0x54890
vpcmpgtd 0x140(%rsp), %ymm1, %ymm5
vpcmpgtd 0x160(%rsp), %ymm2, %ymm6
vmovmskps %ymm5, %r9d
vmovmskps %ymm6, %r8d
vpcmpgtd 0x180(%rsp), %ymm4, %ymm7
vmovmskps %ymm7, %edi
vpcmpgtd 0x1a0(%rsp), %ymm3, %ymm8
vmovmskps %ymm8, %esi
popcntl %r9d, %edx
shll $0x5, %r9d
vmovdqa (%r9,%rcx), %ymm9
popcntl %r8d, %r9d
shll $0x5, %r8d
vmovdqa (%r8,%rcx), %ymm10
popcntl %edi, %r8d
shll $0x5, %edi
vmovdqa (%rdi,%rcx), %ymm11
popcntl %esi, %edi
shll $0x5, %esi
vmovdqa (%rsi,%rcx), %ymm12
vpand %ymm1, %ymm5, %ymm13
vpermd %ymm13, %ymm9, %ymm9
vpand %ymm2, %ymm6, %ymm13
vpermd %ymm13, %ymm10, %ymm10
vpand %ymm4, %ymm7, %ymm13
vpermd %ymm13, %ymm11, %ymm11
vpand %ymm3, %ymm8, %ymm13
vpermd %ymm13, %ymm12, %ymm12
vpblendw $0xaa, %ymm0, %ymm9, %ymm9 # ymm9 = ymm9[0],ymm0[1],ymm9[2],ymm0[3],ymm9[4],ymm0[5],ymm9[6],ymm0[7],ymm9[8],ymm0[9],ymm9[10],ymm0[11],ymm9[12],ymm0[13],ymm9[14],ymm0[15]
vpblendw $0xaa, %ymm0, %ymm10, %ymm10 # ymm10 = ymm10[0],ymm0[1],ymm10[2],ymm0[3],ymm10[4],ymm0[5],ymm10[6],ymm0[7],ymm10[8],ymm0[9],ymm10[10],ymm0[11],ymm10[12],ymm0[13],ymm10[14],ymm0[15]
vpackusdw %ymm10, %ymm9, %ymm9
vpblendw $0xaa, %ymm0, %ymm11, %ymm10 # ymm10 = ymm11[0],ymm0[1],ymm11[2],ymm0[3],ymm11[4],ymm0[5],ymm11[6],ymm0[7],ymm11[8],ymm0[9],ymm11[10],ymm0[11],ymm11[12],ymm0[13],ymm11[14],ymm0[15]
vpblendw $0xaa, %ymm0, %ymm12, %ymm11 # ymm11 = ymm12[0],ymm0[1],ymm12[2],ymm0[3],ymm12[4],ymm0[5],ymm12[6],ymm0[7],ymm12[8],ymm0[9],ymm12[10],ymm0[11],ymm12[12],ymm0[13],ymm12[14],ymm0[15]
vpackusdw %ymm11, %ymm10, %ymm10
vpermq $0xd8, %ymm10, %ymm10   # ymm10 = ymm10[0,2,1,3]
vextracti128 $0x1, %ymm10, -0x10(%rax)
addl %edi, %edi
subq %rdi, %rax
vmovdqu %xmm10, -0x10(%rax)
addl %r8d, %r8d
subq %r8, %rax
vpermq $0xd8, %ymm9, %ymm9     # ymm9 = ymm9[0,2,1,3]
vextracti128 $0x1, %ymm9, -0x10(%rax)
addl %r9d, %r9d
subq %r9, %rax
vmovdqu %xmm9, -0x10(%rax)
negq %rdx
vpsrld $0x10, %ymm1, %ymm9
vpsrld $0x10, %ymm2, %ymm10
vpsrld $0x10, %ymm4, %ymm11
vblendvps %ymm5, %ymm9, %ymm1, %ymm1
vblendvps %ymm6, %ymm10, %ymm2, %ymm2
vblendvps %ymm7, %ymm11, %ymm4, %ymm4
vpsrld $0x10, %ymm3, %ymm5
vblendvps %ymm8, %ymm5, %ymm3, %ymm3
vpsrlq $0x20, %ymm1, %ymm5
vmovdqa 0x2c0(%rsp), %ymm6
vmovdqa 0x2e0(%rsp), %ymm7
vmovdqa 0x300(%rsp), %ymm8
vmovdqa 0x320(%rsp), %ymm9
vpsrlq $0x20, %ymm6, %ymm10
vpmuludq %ymm5, %ymm10, %ymm5
vpmuludq %ymm1, %ymm6, %ymm6
vpsrlq $0x20, %ymm6, %ymm6
vpblendd $0xaa, %ymm5, %ymm6, %ymm5 # ymm5 = ymm6[0],ymm5[1],ymm6[2],ymm5[3],ymm6[4],ymm5[5],ymm6[6],ymm5[7]
vpsrlq $0x20, %ymm2, %ymm6
vpsrlq $0x20, %ymm7, %ymm10
vpmuludq %ymm6, %ymm10, %ymm6
vpmuludq %ymm2, %ymm7, %ymm7
vpsrlq $0x20, %ymm7, %ymm7
vpblendd $0xaa, %ymm6, %ymm7, %ymm6 # ymm6 = ymm7[0],ymm6[1],ymm7[2],ymm6[3],ymm7[4],ymm6[5],ymm7[6],ymm6[7]
vmovdqa %ymm6, 0xc0(%rsp)
vpsrlq $0x20, %ymm4, %ymm6
vpsrlq $0x20, %ymm8, %ymm7
vpmuludq %ymm6, %ymm7, %ymm6
vpmuludq %ymm4, %ymm8, %ymm7
vpsrlq $0x20, %ymm7, %ymm7
vpblendd $0xaa, %ymm6, %ymm7, %ymm6 # ymm6 = ymm7[0],ymm6[1],ymm7[2],ymm6[3],ymm7[4],ymm6[5],ymm7[6],ymm6[7]
vpsrlq $0x20, %ymm3, %ymm7
vpsrlq $0x20, %ymm9, %ymm8
vpmuludq %ymm7, %ymm8, %ymm7
vpmuludq %ymm3, %ymm9, %ymm8
vpsrlq $0x20, %ymm8, %ymm8
vpblendd $0xaa, %ymm7, %ymm8, %ymm7 # ymm7 = ymm8[0],ymm7[1],ymm8[2],ymm7[3],ymm8[4],ymm7[5],ymm8[6],ymm7[7]
vmovdqa %ymm7, 0x120(%rsp)
vmovdqa 0x240(%rsp), %ymm8
vmovdqa 0x260(%rsp), %ymm11
vmovdqa 0x280(%rsp), %ymm9
vmovdqa 0x2a0(%rsp), %ymm7
vpsrld $0x10, %ymm8, %ymm12
vpsrld $0x10, %ymm9, %ymm13
vpbroadcastd 0x28fd2(%rip), %ymm10 # 0x7dcc0
vpaddd %ymm10, %ymm12, %ymm12
vpsrlvd %ymm12, %ymm5, %ymm5
vmovdqa %ymm5, 0x100(%rsp)
vpaddd %ymm10, %ymm13, %ymm5
vpsrlvd %ymm5, %ymm6, %ymm5
vmovdqa %ymm5, 0x80(%rsp)
vpblendw $0xaa, %ymm0, %ymm8, %ymm5 # ymm5 = ymm8[0],ymm0[1],ymm8[2],ymm0[3],ymm8[4],ymm0[5],ymm8[6],ymm0[7],ymm8[8],ymm0[9],ymm8[10],ymm0[11],ymm8[12],ymm0[13],ymm8[14],ymm0[15]
vmovdqa %ymm5, 0xe0(%rsp)
vpblendw $0xaa, %ymm0, %ymm11, %ymm8 # ymm8 = ymm11[0],ymm0[1],ymm11[2],ymm0[3],ymm11[4],ymm0[5],ymm11[6],ymm0[7],ymm11[8],ymm0[9],ymm11[10],ymm0[11],ymm11[12],ymm0[13],ymm11[14],ymm0[15]
vpblendw $0xaa, %ymm0, %ymm9, %ymm13 # ymm13 = ymm9[0],ymm0[1],ymm9[2],ymm0[3],ymm9[4],ymm0[5],ymm9[6],ymm0[7],ymm9[8],ymm0[9],ymm9[10],ymm0[11],ymm9[12],ymm0[13],ymm9[14],ymm0[15]
vpblendw $0xaa, %ymm0, %ymm7, %ymm15 # ymm15 = ymm7[0],ymm0[1],ymm7[2],ymm0[3],ymm7[4],ymm0[5],ymm7[6],ymm0[7],ymm7[8],ymm0[9],ymm7[10],ymm0[11],ymm7[12],ymm0[13],ymm7[14],ymm0[15]
vmovdqa 0x1c0(%rsp), %ymm14
xorl %esi, %esi
vmovdqa 0x1e0(%rsp), %ymm9
vmovdqa 0x200(%rsp), %ymm5
vmovdqa 0x220(%rsp), %ymm6
cmpq $0x20, %rsi
je 0x54d6d
decl 0x760(%rsp,%rsi,4)
incq %rsi
jmp 0x54d5b
vpsrld $0x10, %ymm11, %ymm11
vpaddd %ymm10, %ymm11, %ymm11
vmovdqa 0xc0(%rsp), %ymm12
vpsrlvd %ymm11, %ymm12, %ymm11
vpmulld %ymm8, %ymm11, %ymm8
vpsrld $0x10, %ymm7, %ymm7
vpaddd %ymm7, %ymm10, %ymm7
vmovdqa 0x120(%rsp), %ymm10
vpsrlvd %ymm7, %ymm10, %ymm7
vpmulld %ymm15, %ymm7, %ymm7
vmovdqa 0xe0(%rsp), %ymm10
vpmulld 0x100(%rsp), %ymm10, %ymm10
vpmulld 0x80(%rsp), %ymm13, %ymm11
vpaddd %ymm1, %ymm10, %ymm1
vpaddd %ymm1, %ymm14, %ymm1
vpaddd %ymm2, %ymm9, %ymm2
vpaddd %ymm2, %ymm8, %ymm2
vpaddd %ymm4, %ymm11, %ymm4
vpaddd %ymm5, %ymm4, %ymm4
vpaddd %ymm6, %ymm3, %ymm3
vpaddd %ymm3, %ymm7, %ymm3
leaq (%rax,%rdx,2), %rax
jmp 0x54880
vmovdqa %ymm1, 0x340(%rsp)
vmovdqa %ymm2, 0x360(%rsp)
vmovdqa %ymm4, 0x380(%rsp)
vmovdqa %ymm3, 0x3a0(%rsp)
leaq 0x28(%rsp), %r14
movq %rax, (%r14)
pushq $0x1f
popq %r15
testl %r15d, %r15d
js 0x54e4b
movl %r15d, %eax
leaq (%rsp,%rax,4), %rdi
addq $0x340, %rdi            # imm = 0x340
movzbl 0x30(%rsp,%rax), %edx
shll $0x4, %edx
addq %r13, %rdx
movq %r14, %rsi
vzeroupper
callq 0x53a08
decl %r15d
jmp 0x54e1d
pushq $0x1f
popq %rcx
movq 0x28(%rsp), %rsi
xorl %eax, %eax
movq 0x18(%rsp), %rdi
testl %ecx, %ecx
js 0x54e73
movl %ecx, %edx
movl 0x340(%rsp,%rdx,4), %edx
movl %edx, -0x4(%rsi,%rax)
decl %ecx
addq $-0x4, %rax
jmp 0x54e5a
movq 0xb8(%rsp), %rcx
addl %edi, %ecx
subl %r12d, %edi
movq 0x78(%rsp), %rdx
subq %rsi, %rdx
subq %rax, %rdx
subl %esi, %ecx
subl %eax, %ecx
movl %ecx, (%rbx)
addq %r12, %rdi
addq %rax, %rsi
vzeroupper
callq 0x4830
movq %r13, %rdi
callq 0x64291
jmp 0x54782