// File: gvaumour[P]cache-simulator/src/Cerebron.cc
// Function: CerebronPredictor::classifyRD(int, int, bool)
RD_TYPE
CerebronPredictor::classifyRD(int set , int index, bool inNVM)
{
	vector<CacheEntry*> line;
	int64_t ref_rd = 0;
	if(inNVM)
	{
		ref_rd = m_tableNVM[set][index]->policyInfo;
		line = m_tableNVM[set];
	}
	else
	{
		line = m_tableSRAM[set];
		ref_rd = m_tableSRAM[set][index]->policyInfo;
	}
	
	int position = 0;
	/* Determine the position of the cache line in the LRU stack */
//	debug_file << "classifyRD, cpt_time =  " << cpt_time << ", set = " << set << " col = " << index << ", ref_rd = " << ref_rd << endl;
	for(unsigned i = 0 ; i < line.size() ; i ++)
	{
//		debug_file << "\tPolicy[" << i << "] = " << line[i]->policyInfo << endl;
		if(line[i]->policyInfo > ref_rd && line[i]->isValid)
			position++;
	}	
//	debug_file << "Position = " << position << endl;

	if(simu_parameters.nvm_assoc > simu_parameters.sram_assoc)
	{
		if(position < simu_parameters.mediumrd_def)
			return RD_SHORT;
		else
			return RD_MEDIUM;	
	}
	else
	{
		if(position < simu_parameters.mediumrd_def)
			return RD_SHORT;
		else
			return RD_MEDIUM;
	}
}

// Assembly:
subq $0x68, %rsp
movb %cl, %al
movq %rdi, 0x58(%rsp)
movl %esi, 0x54(%rsp)
movl %edx, 0x50(%rsp)
andb $0x1, %al
movb %al, 0x4f(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x30(%rsp), %rdi
callq 0xfe30
movq $0x0, 0x28(%rsp)
testb $0x1, 0x4f(%rsp)
je 0xaaed
movq 0x8(%rsp), %rax
movq 0x10(%rax), %rdi
movslq 0x54(%rsp), %rsi
callq 0xf9a0
movq %rax, %rdi
movslq 0x50(%rsp), %rsi
callq 0xf9c0
movq %rax, %rcx
movq 0x8(%rsp), %rax
movq (%rcx), %rcx
movslq 0x38(%rcx), %rcx
movq %rcx, 0x28(%rsp)
movq 0x10(%rax), %rdi
movslq 0x54(%rsp), %rsi
callq 0xf9a0
movq %rax, %rsi
leaq 0x30(%rsp), %rdi
callq 0xfe40
jmp 0xaace
jmp 0xab3b
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 0x20(%rsp)
movl %eax, 0x1c(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x10120
jmp 0xac4e
movq 0x8(%rsp), %rax
movq 0x8(%rax), %rdi
movslq 0x54(%rsp), %rsi
callq 0xf9a0
movq %rax, %rsi
leaq 0x30(%rsp), %rdi
callq 0xfe40
jmp 0xab0f
movq 0x8(%rsp), %rax
movq 0x8(%rax), %rdi
movslq 0x54(%rsp), %rsi
callq 0xf9a0
movq %rax, %rdi
movslq 0x50(%rsp), %rsi
callq 0xf9c0
movq (%rax), %rax
movslq 0x38(%rax), %rax
movq %rax, 0x28(%rsp)
movl $0x0, 0x18(%rsp)
movl $0x0, 0x14(%rsp)
movl 0x14(%rsp), %eax
movq %rax, (%rsp)
leaq 0x30(%rsp), %rdi
callq 0x10100
movq %rax, %rcx
movq (%rsp), %rax
cmpq %rcx, %rax
jae 0xabb9
movl 0x14(%rsp), %eax
movl %eax, %esi
leaq 0x30(%rsp), %rdi
callq 0xf9c0
movq (%rax), %rax
movslq 0x38(%rax), %rax
cmpq 0x28(%rsp), %rax
jle 0xabaa
movl 0x14(%rsp), %eax
movl %eax, %esi
leaq 0x30(%rsp), %rdi
callq 0xf9c0
movq (%rax), %rax
testb $0x1, (%rax)
je 0xabaa
movl 0x18(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x18(%rsp)
jmp 0xabac
movl 0x14(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x14(%rsp)
jmp 0xab4b
leaq 0x89430(%rip), %rax     # 0x93ff0
movl 0x40(%rax), %eax
leaq 0x89426(%rip), %rcx     # 0x93ff0
cmpl 0x38(%rcx), %eax
jle 0xac06
movl 0x18(%rsp), %eax
leaq 0x89416(%rip), %rcx     # 0x93ff0
cmpl 0x1fc(%rcx), %eax
jge 0xabf4
movl $0x0, 0x64(%rsp)
movl $0x1, 0x10(%rsp)
jmp 0xac3b
movl $0x1, 0x64(%rsp)
movl $0x1, 0x10(%rsp)
jmp 0xac3b
movl 0x18(%rsp), %eax
leaq 0x893df(%rip), %rcx     # 0x93ff0
cmpl 0x1fc(%rcx), %eax
jge 0xac2b
movl $0x0, 0x64(%rsp)
movl $0x1, 0x10(%rsp)
jmp 0xac3b
movl $0x1, 0x64(%rsp)
movl $0x1, 0x10(%rsp)
leaq 0x30(%rsp), %rdi
callq 0x10120
movl 0x64(%rsp), %eax
addq $0x68, %rsp
retq
movq 0x20(%rsp), %rdi
callq 0x5690
nopl (%rax,%rax)