Peer review of: Nonvolatile ferroelectric field-effect transistors (2020)

Reviewers' Comments: 
 
Reviewer #1: 
Remarks to the Author: 
This manuscript describes the study of transistors produced from domain walls in Mg-doped 
LiNbO3. The document reports significantly enhanced diode-like wall currents, using gating that 
erases/creates the conducting domain walls. The authors refer to them as junctionless transistors 
and suggest they have low leakage, fast operating speeds, high currents, and abrupt on/off states. 
 
This manuscript is positioned at an interesting point. First, from a topical point of view, there is 
growing interest in non-traditional materials for next generation logic applications; this work is well 
positioned in that capacity. It builds from over a decade of work on conducting domain walls in 
ferroelectrics, but pushes it in a new direction with some rather impressive nanofabrication and 
realistic device demonstrations. This said, the manuscript also sits in a bit of an awkward position 
in that the physics of domain wall conduction is essentially a “done” topic at this point and the 
manuscript provides no real advancement of the science of domain wall conduction. Instead, the 
merits seem to be fully placed on the demonstration of device performance as a transistor. In that 
regard, to be clear, the results here are not “competitive” with current state of the art. First, the 
voltages of operation are very large – currently devices operate at 500-600 mV range – while this 
work is well into the many V range. Second, the subthreshold swing of current devices bottoms 
out at 60 mV/dec – the authors report 216 mV/dec in one part and then (in passing) suggest 0 
mV/dec later without really making a strong statement or point about this. In this regard, the 
question as to what this paper really accomplishes could be brought up? For this reviewer, despite 
these limitations, it is likely meritorious for publication in some form. This said, the authors would 
be well served not to mislead the reader as to the performance because of the advanced 
nanofabrication and the extensive data it reports – which to the best of my knowledge seems of 
high quality. Direct and honest comparison and acknowledgement of the limitations would be 
welcomed – this reviewer does not expect the authors to “solve” the entire challenge in one paper. 
Perhaps more helpful, in fact, would be recommendations on what could be done to improve the 
performance of these devices (perhaps it is just scaling things down, but these devices are already 
fairly small). What are the potential limits of what can be accomplished using domain wall 
structures as the active device? At the same time, perhaps some more scientific understanding of 
the observations is warranted. Right now, the manuscript comes across a bit “device-heavy” in 
that it just reports the observations by doesn’t really show a level of control of the materials 
physics to achieve a specific goal. 
 
In addition to these points, there are a few additional questions to be considered: 
- Is Figure 1a really a phase field simulation? It looks like a powerpoint drawing. 
- What is the thickness of the LiNbO3 crystal? How thick is the “blue” domain or how far away from 
the gate is the D-S wall in Figure 1? How would varying this thickness change the device 
performance? 
- Why was LAADF-STEM done and not simple diffraction contrast? The latter – when done with the 
right diffraction condition - would have clearly shown contrast between the oppositely poled 
domains. Instead, the data relies on the extraction of local polarization from the unit cell distortion 
which cannot be seen in the figure in b, c, and e. 
- What is meant by the statement “These stripe regions are rich with anti-dipoles…” What are the 
stripe regions – the domain wall width? What do the authors mean by anti-dipoles? 
- What is the point of Figure 4? The data is provided, first, to show the true nature of the domain 
structure – which is fine and acceptable. But beyond this, the analysis of this figure seems to be 
lacking. Is there something learned from this that could be used to improve the performance of 
the material? What does the next generation of device have to look like to be more useful? 
 
 
 
Reviewer #2: 
Remarks to the Author: 
Domain wall electronics is a hot research direction, providing a possible solution to next-generation 
nanoelectronics. The authors follow this trend to demonstrate a domain device architecture based 
on ferroelectric LiNbO3 crystals. A three terminal similiar to traditional field effect transistor is used 
to control the generation of domain wall. The devices they showed possess two critical 
characteristics:1. Vg controlled transistor without subthreshold swing, 2. Vs controlled non-volatile 
transistor. An extensive electrical characterization was implemented with the theoretical support 
(phase field simulation) and microscopic evidence (TEM). I do believe this study represent an 
important step for the realization of domain wall nanoelectronics. However, before I recommend 
the publication of this manuscript. Here are some issues to be addressed: 
1. for the logic operation: it is very important to address the switching speed especially compared 
with current CMOS technology. 
2. for low-power operation: how low energy will be used to control a bit should be calculated and 
the authors should also address how far they are. 
3. for memory applications: ferroelectric fatigue and retention should be measured in such a 
configuration since the key part of device relies on a ferroelectric head-to-head domain 
configuration, which is not a stable state. 
 
 
 
Reviewer #3: 
Remarks to the Author: 
A key feature of ferroelectric (FE) domain wall is their electrical conductivity. Electric bias not only 
generates stable FE domains with strongly oriented domain walls, but also can induce reversible 
transition between the conducting and insulating states of the domain walls as a result of 
electrically induced wall bending near the sample surface. 
 
The authors here exploit that feature to create a terminal device which acts like a single pole 
double throw switch with reasonable repeatability. 
 
Unfortunately, the manuscript makes a poor attempt to present this device as a) logic transistor 
and b) 3-terminal non-volatile memory. And fails in both aspects. 
I recommend the authors to focus on only one application of the proposed device and perform a 
more detailed study of the domain wall device from that perspective. 
 
Logic transistor: To qualify as a transistor and to perform as a useful compute device, the device 
needs to show the following: 
a) hysteresis free (or negligible) Ids-Vgs transfer characteristics for any given Vds. The threshold 
voltage should not vary as a function of Vds (like the device presented here). Repeated cycling 
should not shift the Id-Vg curves. 
b) Saturation in the Ids-Vds output characteristics for a given Vgs: There should be clear transition 
from low Vds to high Vds, and the device should transition from low impedance (at low Vds) to a 
high impedance state (at high Vds). Unfortunately, this device does not conduct at low Vds, which 
will slow down circuits. 
c) Speed of switching between off and on-states should be in the range of sub pico-second to 
compete with CMOS: Domain wall velocity in MgO doped LN is typically in the range of 0.015 to 5 
μm/s with the applied electric field ranging from 6 to 40 kV/cm. this is too slow for logic 
applications. 
d) Complementary operation in terms of a pull-up device and a pull down device is very important 
to build an inverter - a basic building block for logic. The proposed domain wall device does not 
address such functionality. 
e) Cascaded logic: one should be able to connect the inverter gate in series with the succeeding 
gate, and signal restoration needs to be guaranteed. This device which acts as a single pole double 
throw switch does not meet the criterion. 
Let us now discuss application of the domain wall FET for non-volatile memory application. 
a) demonstrate write and read operation clearly: Fig. 3 tries to address this, but falls short. a 
memory device needs to be placed in an array with world-line and bit-line clearly identified first. 
Then write and read operation need to be demonstrated by using the write terminal for access, 
program and erase; and read terminal for read out of the programmed state. It's very important 
to demonstrate that neighboring cells do not get disturbed (or written into) when the target cell is 
being accessed. Thus, inhibition schemes need to identified clearly. 
b) retention time measurement need to be shown to claim non volatility: after programming pulse, 
a non-destructive read pulse sequence at specified time interval need to be applied to see how the 
stored conductance state is maintained. Such measurement was not shown. For practical 
applications, both room temperature and 85C data need to be shown. 
c) write and read time: with programming and erase pulse of different pulse width for a given 
pulse amplitude, the memory window (for example conductance ratio) need to be characterized. 
Then pulse amplitude need to be varied for a given pulse width and the memory window 
quantified. Only then, we will be able to understand the read and write latency as a function of the 
write energy for the proposed memory. Short pulse height and short pulse duration may not only 
affect memory read window, but also affect retention. That needs to be characterized. 
d) variation is the most important attribute after demonstration of basic memory operation as 
noted above. It's not clear how the nucleation and growth of the domains is guaranteed for 
reproducible characteristics as a function of repeated switching. Endurance measurement is also 
advised to ascertain the application space of the proposed FE domain wall non-volatile memory. 
 
In summary, a detailed effort focusing on one type of device (logic or memory) is being 
recommended to markedly improve the quality of the manuscript.