logic test pattern generation using linear codes logic testing of today s integrated circuits is a task of increasing difficulty as the number of circuits or transistors packed onto a single chip grows higher and higher exhaustive pattern testing with adequate partitioning of logic has been explored regarding its potential in solving the problems in test pattern generation and fault coverage in this paper we propose a new method of simultaneously generating exhaustive test patterns for all possible input subsets each corresponding to an output up tq a specified size the method is based on the structure of linear polynomial codes and can be easily implemented by modifying existing shift registers in an lssd or scan path design to embody additional feedback connections this is particularly attractive since the implementation is compatible with the approach of self testing using pseudorandom patterns thus a very reasonable strategy is to combine limited exhaustive pattern testing with pseudorandom pattern testing ini cases where complete exhaustive testing is not practical

linear dependencies in linear feedback shift registers linear feedback shift registers have been proposed to generate test patterns for the self test of logic networks the probability of linear dependence among k bit positions of a subset of k bits in a maximum length shift register sequence is an outstanding problem in this correspondence we derive a formula for the calculation of the probability

optimal codes for minimax criterion on error detection nonlinear quadratic codes that are optimal for the minimax error detection are presented characteristic functions for these codes are asymptotically bent for a given block size n and the number of codewords mod c mod these codes minimize max q e e not 0 where q e is the conditional error masking probability given the error pattern e the codewords are blocks of n symbols from gf q encoding and decoding procedures for the codes are described

disturbed exploitation compact differential evolution for limited memory optimization problems this paper proposes a novel and unconventional memetic computing approach for solving continuous optimization problems characterized by memory limitations the proposed algorithm unlike employing an explorative evolutionary framework and a set of local search algorithms employs multiple exploitative search within the main framework and performs a multiple step global search by means of a randomized perturbation of the virtual population corresponding to a periodical randomization of the search for the exploitative operators the proposed memetic computing approach is based on a populationless compact evolutionary framework which instead of processing a population of solutions handles its statistical model this evolutionary framework is based on a differential evolution which cooperatively employs two exploitative search operators the first is based on a standard differential evolution mutation and exponential crossover and the second is the trigonometric mutation these two search operators have an exploitative action on the algorithmic framework and thus contribute to the rapid convergence of the virtual population towards promising candidate solutions the action of these search operators is counterbalanced by a periodical stochastic perturbation of the virtual population which has the role of disturbing the excessively exploitative action of the framework and thus inhibits its premature convergence the proposed algorithm namely disturbed exploitation compact differential evolution is a simple and memory wise cheap structure that makes use of the memetic computing paradigm in order to solve complex optimization problems the proposed approach has been tested on a set of various test problems and compared with state of the art compact algorithms and with some modern population based meta heuristics numerical results show that disturbed exploitation compact differential evolution significantly outperforms all the other compact algorithms present in literature and reaches a competitive performance with respect to modern population algorithms including some memetic approaches and complex modern differential evolution based algorithms in order to show the potential of the proposed approach in real world applications disturbed exploitation compact differential evolution has been implemented for performing the control of a space robot by simulating the implementation within the robot micro controller numerical results show the superiority of the proposed algorithm with respect to other modern compact algorithms present in literature

soliton solutions of the kadomtsev petviashvili ii equation we study a general class of line soliton solutions of the kadomtsev petviashvili ii kpii equation by investigating the wronskian form of its tau function we show that in addition to the previously known line soliton solutions of kpii this class also contains a large variety of multisoliton solutions many of which exhibit nontrivial spatial interaction patterns we also show that in general such solutions consist of unequal numbers of incoming and outgoing line solitons from the asymptotic analysis of the tau function we explicitly characterize the incoming and outgoing line solitons of this class of solutions we illustrate these results by discussing several examples

test pattern generation based on reed muller coefficients reed muller coefficients are used to generate a test pattern selection procedure for detecting single stuck at faults this procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults the changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits the proposed pattern generating procedure does not need a simulation of the circuit for each of the possible stuck at faults and its complexity is proportional to the number of gates in the circuit the proportionality constant increases exponentially as the number of inputs in the circuit increases to evaluate the performance of the proposed method its application to some benchmark circuits including the alu 74181 is presented

the complexity of fault detection problems for combinational logic circuits in this correspondence we analyze the computational complexity of fault detection problems for combinational circuits and propose an approach to design for testability although major fault detection problems have been known to be in general np complete they were proven for rather complex circuits in this correspondence we show that these are still np complete even for monotone circuits and thus for unate circuits we show that for k level k 3 monotone unate circuits these problems are still np complete but that these are solvable in polynomial time for 2 level monotone unate circuits a class of circuits for which these fault detection problems are solvable in polynomial time is presented ripple carry adders decoder circuits linear circuits etc belong to this class a design approach is also presented in which an arbitrary given circuit is changed to such an easily testable circuit by inserting a few additional test points

vector sets for exhaustive testing of logic circuits l d universal sets are useful for exhaustively testing logic circuits with a large number of functional components designed so that every functional component depends on at most d inputs randomized and deterministic constructions of l d universal test sets are presented and lower and upper bounds on the optimal sizes of such sets are proven it is also proven that the design of an optimal exhaustive test set for an arbitrary logic circuit is an np complete problem

on polynomial time testable combinational circuits the problems of identifying several nontrivial classes of polynomial time testable ptt circuits are shown to be np complete or harder first ptt classes obtained by using circuit decompositions proposed by fujiwara 1988 and chakradhar et al 1990 are considered another type of decompositions based on fanout reconvergent f r pairs which also lead to ptt classes are proposed the problems of obtaining these decompositions and also some structurally similar general graph decompositions are shown to be np complete or harder then the problems of recognizing ptt classes formed by the boolean formulae belonging to the weakly positive weakly negative bijunctive and affine classes are shown to be np complete

a hybrid immune multiobjective optimization algorithm in this paper we develop a hybrid immune multiobjective optimization algorithm himo based on clonal selection principle in himo a hybrid mutation operator is proposed with the combination of gaussian and polynomial mutations gp hm operator the gp hm operator adopts an adaptive switching parameter to control the mutation process which uses relative large steps in high probability for boundary individuals and less crowded individuals with the generation running the probability to perform relative large steps is reduced gradually by this means the exploratory capabilities are enhanced by keeping a desirable balance between global search and local search so as to accelerate the convergence speed to the true pareto optimal front in the global space with many local pareto optimal fronts when comparing himo with various state of the art multiobjective optimization algorithms developed recently simulation results show that himo performs better evidently

computations over finite monoids and their test complexity abstract we consider the test pattern generation problem for circuits which compute expressions over some algebraic structure the relation between algebraic properties of this structure and test complexity i e the best possible test size is analyzed here this relation is looked at in detail for the family of all finite monoids the test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit in a certain computational model solving the problem two important computations over finite monoids namely expression evaluation and parallel prefix computation are considered the relation between algebraic properties of a monoid and its test complexity with respect to these problems is studied in both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant logarithmic and linear test complexity respectively these classes are characterized using algebraic properties for example groups are exactly the monoids with constant test complexity for each class we provide circuits with optimal test sets and efficient methods which decide the membership problem for a given finite monoid m i e determine the test complexity for m

an implicit enumeration algorithm to generate tests for combinational logic circuits the d algorithm dalg is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation ecat functions podem path oriented decision making is a new test generation algorithm for combinational logic circuits podem uses an implicit enumeration approach analogous to that used for solving 0 1 integer programming problems it is shown that podem is very efficient for ecat circuits and is significantly more efficient than dalg over the general spectrum of combinational logic circuits a distinctive feature of podem is its simplicity when compared to the d algorithm podem is a complete algorithm in that it will generate a test if one exists heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted

novel test pattern generators for pseudoexhaustive testing pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones the testing ensures detection of all detectable multiple stuck at faults in the circuit and all detectable combinational faults within individual cones test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information they usually generate test sets that are several orders of magnitude larger than the minimum size pseudoexhaustive test set required for a specific circuit in this paper we describe hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets using our techniques we have designed generators that generate minimum size test sets for the iscas benchmark circuits

balancing exploration and exploitation with adaptive variation for evolutionary multi objective optimization abstract although recent studies have shown that evolutionary algorithms are effective tools for solving multi objective optimization problems their performances are often bottlenecked by the suitability of the evolutionary operators with respect to the optimization problem at hand and their corresponding parametric settings to adapt the search dynamic of evolutionary operation in multi objective optimization this paper proposes an adaptive variation operator that exploits the chromosomal structure of binary representation and synergizes the function of crossover and mutation the overall search ability is deterministically tuned online to maintain a balance between extensive exploration and local fine tuning at different stages of the evolutionary search also the coordination between the two variation operators is achieved by means of an adaptive control that ensures an efficient exchange of information between the different chromosomal sub structures throughout the evolutionary search extensive comparative studies with several representative variation operators are performed on different benchmark problems and significant algorithmic performance improvements in terms of proximity uniformity and diversity are obtained with the incorporation of the proposed adaptive variation operator into the evolutionary multi objective optimization process

interpolation and approximation of sparse multivariate polynomials over gf 2 a function f 0 1 n to 0 1 is called t sparse if the n variable polynomial representation of f over gf 2 contains at most t monomials such functions are uniquely determined by their values at the so called critical set of all binary n tuples of hamming weight geqq n lfloor log 2 t rfloor 1 an algorithm is presented for interpolating any t sparse function f given the values of f at the critical set the time complexity of the proposed algorithm is proportional to n t and the size of the critical set then the more general problem of approximating 1 sparse functions is considered in which case the approximating function may differ from f at a fraction varepsilon of the space 0 1 n it is shown that o t varepsilon cdot n evaluation points are sufficient for the deterministic varepsilon approximation of any t sparse function and that an order t varepsilon alpha t varepsilon cdot log n points are necessary for this purpose wh

a combinatorial approach to x tolerant compaction circuits test response compaction for integrated circuits ics with scan based design for testability dft support in the presence of unknown logic values xs is investigated from a combinatorial viewpoint the theoretical foundations of x codes employed in an x tolerant compaction technique called x compact are examined through the formulation of a combinatorial model of x compact novel design techniques are developed for x codes to detect a specified maximum number of errors in the presence of a specified maximum number of unknown logic values while requiring only small fan out the special class of x codes that results leads to an avoidance problem for configurations in combinatorial designs general design methods and nonconstructive existence theorems to estimate the compaction ratio of an optimal x compactor are also derived

exhaustive test pattern generation using cyclic codes the generation of exhaustive test patterns for vlsi circuits using linear feedback shift registers is described in terms of cyclic codes punctured cyclic codes are used to generate exhaustive test patterns of any length a techniques for the generation of punctured cyclic codes is presented a technique is also presented to reduce the size of test sets obtained from punctured cyclic codes

vector space theoretic analysis of additive cellular automata and its application for pseudoexhaustive test pattern generation a novel scheme for utilizing the regular structure of three neighborhood additive cellular automata cas for pseudoexhaustive test pattern generation is introduced the vector space generated by a ca can be decomposed into several cyclic subspaces a cycle corresponding to an m dimensional cyclic subspace has been shown to pseudoexhaustively test an n input circuit n or m such a cycle is shown to supply a m 1 bit exhaustive pattern including the all zeros m 1 tuple schemes have been reported specifying how one or more subsets of m 1 cell positions of an n cell ca can be identified to generate exhaustive patterns in an m dimensional cyclic subspace

design of test sequences for vlsi self testing using lfsr consider a shift register sr of length n and a collection of designated subsets of 0 1 n 1 the problem is how to add feedback to the sr such that the resulting linear feedback shift register lfsr exercises almost exhaustively each of the designated subsets and is of small period several previously known results for maximum length lfsr are extended to more general lfsr and in particular a previously known algorithm is simplified and extended applications to the problems of vlsi self testing are discussed and illustrated

design of universal test sequences for vlsi a test sequence is called s t universal if it exercises every function depending on t or fewer inputs on a very large scale integration vlsi chip with s inputs randomized and deterministic procedures are deseribed for the design of s t universal sequences and for the signature analysis of the test outputs

pseudorandom arrays for built in tests parallel pseudorandom sequences for use in built in test are discussed the two dimensional nature of these sequences makes it natural to consider the resulting binary arrays some of the desired properties of such arrays are discussed as well as some of the problems generators for such arrays are described a conventional lfsr with parallel output is shown to be a poor choice for such a generator several compact generators are described which are shown to be compromises between complexity and varying degrees of implementation of the desired properties in the resulting sequences one of the compact generators produces sequences which have the desired properties for built in tests

fault detection analysis of boolean control networks in this technical note we address the fault detection problem for boolean control networks bcns we first investigate completeness and t completeness of the set of input output trajectories next we introduce the concept of meaningful fault and prove necessary and sufficient conditions under which meaningful faults can be detected from the input output trajectories of the bcn two fault detection algorithms are provided

brief paper boolean derivative calculation with application to fault detection of combinational circuits via the semi tensor product method using the semi tensor product method this paper investigates the boolean derivative calculation with application to fault detection of combinational circuits and presents a number of new results first a new set of formulas is obtained to calculate the boolean derivative by the semi tensor product method then the obtained new results are applied to detecting the multiple faults of combinational circuits and a new detection method is proposed finally two illustrative examples are studied by using the results obtained in this paper the study of illustrative examples shows that the new detection method can be used for detection of more than two faults effectively

exhaustive test pattern generation with constant weight vectors we develop in this paper a simple way of generating a test set which simultaneously provides exhaustive pattern testing with respect to all input subsets of a logic circuit up to a certain size it is shown that such a test set may be formed with vectors of a particular set of weights main theorems and examples are established and illustrated in the binary case for 2 value logic circuits and then generalized to nonbinary cases for multivalue logic circuits such test sets are simple in structure and become optimal in size in certain cases it is also shown that such a test set can be effectively implemented via a scan path type shifter

on greedy algorithms in coding theory we study a wide class of problems in coding theory for which we consider two different formulations in terms of incidence matrices and in terms of hypergraphs these problems are dealt with using a greedy algorithm due to stein 1974 and lovasz 1975 some examples including constructing covering codes codes for conflict resolution separating systems source encoding with distortion etc are given a unified treatment under certain conditions derandomization can be performed leading to an essential reduction in the complexity of the constructions

recursive pseudoexhaustive test pattern generation a recursive technique for generating exhaustive patterns is presented the method is optimal i e in one experiment it covers exhaustively every block of k adjacent inputs in the first 2 sup k vectors implementation methods based on characteristic functions of test vectors are provided they include a parallel pattern generator employing an exclusive or array and two serial generators that can be easily adopted in a scan based built in self test environment

the deodhar decomposition of the grassmannian and the regularity of kp solitons abstract given a point a in the real grassmannian it is well known that one can construct a soliton solution u a x y t to the kp equation the contour plot of such a solution provides a tropical approximation to the solution when the variables x y and t are considered on a large scale and the time t is fixed in this paper we use several decompositions of the grassmannian in order to gain an understanding of the contour plots of the corresponding soliton solutions first we use the positroid stratification of the real grassmannian in order to characterize the unbounded line solitons in the contour plots at y 0 and y 0 next we use the deodhar decomposition of the grassmannian a refinement of the positroid stratification to study contour plots at t 0 more specifically we index the components of the deodhar decomposition of the grassmannian by certain tableaux which we call go diagrams and then use these go diagrams to characterize the contour plots of solitons solutions when t 0 finally we use these results to show that a soliton solution u a x y t is regular for all times t if and only if a comes from the totally non negative part of the grassmannian

complexity reduction for sign configurations through the kp ii equation and its information theoretic aspects we provide a combinatorial setting to explore the information content associated with the fulfillment of the kadomtsev petviashvili kp ii equation we start from a special family of solutions of kp ii namely tau functions of wronskian type a solution in this class can be expressed as a sum of exponentials and we look at combinations of signs signatures for the nonvanishing terms in this sum we prove a characterization of the signatures that return another solution of the kp ii equation they can be represented as choices of signs for columns and rows of a coefficient matrix so we recover a function satisfying the whole kp hierarchy from this single constraint the redundancy of this representation for different choices of the initial solution is investigated enumerative information theoretic and geometric aspects of this construction are discussed we provide a combinatorial setting to explore the information content associated with the fulfillment of the kadomtsev petviashvili kp ii equation we start from a special family of solutions of kp ii namely tau functions of wronskian type a solution in this class can be expressed as a sum of exponentials and we look at combinations of signs signatures for the nonvanishing terms in this sum we prove a characterization of the signatures that return another solution of the kp ii equation they can be represented as choices of signs for columns and rows of a coefficient matrix so we recover a function satisfying the whole kp hierarchy from this single constraint the redundancy of this representation for different choices of the initial solution is investigated enumerative information theoretic and geometric aspects of this construction are discussed

a characterization of binary decision diagrams binary decision diagrams bdds are a representation of boolean functions its use in the synthesis simulation and testing of boolean circuits has been proposed by various researchers in all these applications of bdds solutions to some fundamental computational problems are needed a characterization of bdds in terms of the complexity of these computational problems is presented a tighter bound on the size of an ordered bdd that can be computed from a given boolean circuit is presented on the basis of the results a case is made for exploring the use of repeated bdds with a small number of repeated variables and free bdds for some applications for which only ordered bdds have been used so far

the weighted syndrome sums approach to vlsi testing with the advent of vlsi testing has become one of the most costly complicated and time consuming problems the method of syndrome testing is applicable toward vlsi testing since it does not require test generation and fault simulation it can also be considered as a vehicle for self testing in order to employ syndrome testing in vlsi we electronically partition the chip into macros in test mode the macros are then syndrome tested in sequence

the use of linear sums in exhaustive testing the increasing role of exhaustive testing techniques in vlsi has prompted a number of investigations into methods for achieving locally exhaustive testing of the components of a large digital circuit using a comparatively small number of test signals this paper examines the possibility of introducing linear sums of the test signals into this testing process it is shown that with the addition of a relatively small amount of additional circuitry significant reductions in the number of required test signals and tests can often be achieved in particular it is shown that for any specific combinational circuit the number of required test signals can be made to be independent of the number of inputs and to depend only logarithmically on the number of outputs the role of these linear sums in the generation of universal test sets is also discussed

pseudoexhaustive test pattern generator with enhanced fault coverage a method of pseudoexhaustive test pattern generation is proposed that is suitable above all for circuits using random access scan two linear feedback shift registers are used to generate scan addresses and test patterns to be scanned into these addresses it is shown that the method gives better results than random testing

finite dimensional kadomtsev petviashvili τ functions i finite grassmannians we study functions of the kadomtsev petviashvili hierarchy in terms of abelian group actions on finite dimensional grassmannians viewed as subquotients of the hilbert space grassmannians of sato segal and wilson a determinantal formula of gekhtman and kasman involving exponentials of finite dimensional matrices is shown to follow naturally from such reductions all reduced flows of exponential type generated by matrices with arbitrary nondegenerate jordan forms are derived both in the grassmannian setting and within the fermionic operator formalism a slightly more general determinantal formula involving resolvents of the matrices generating the flow valid on the big cell of the grassmannian is also derived an explicit expression is deduced for the plucker coordinates appearing as coefficients in the schur function expansion of the function

on closedness and test complexity of logic circuits the concept of closedness of a set of logic functions under stuck type faults is introduced all sets of logic functions closed under stuck type faults are classified for the sets of logic functions closed under stuck type faults the test complexity and the universal test sets are considered it is shown that for each class of linear functions or functions and and functions both the minimum numbers of multiple fault detection tests and multiple fault location tests are exactly n 1 where n is the number of inputs of the circuits and that there exists universal test sets with n 1 tests to detect and locate all multiple faults in such circuits

new bounds for binary covering arrays using simulated annealing covering arrays cas are combinatorial structures specified as a matrix of n rows and k columns over an alphabet on v symbols such that for each set of t columns called the strength of the array every t tuple of symbols is covered recently they have been used to represent interaction test suites for software testing given that they provide economical sized test cases while still preserving important fault detection capabilities this paper introduces an improved implementation of a simulated annealing algorithm called isa for constructing cas of strengths three through six over a binary alphabet i e binary cas extensive experimentation is carried out using 127 well known benchmark instances for assessing its performance with respect to an existing simulated annealing implementation a greedy method and five state of the art algorithms the results show that our algorithm attains 104 new bounds and equals the best known solutions for the other 23 instances consuming reasonable computational time furthermore the implications of using these results as ingredients to recursive constructions are also analyzed

bounds on the linear span of bent sequences recently olsen scholtz and welch presented families of binary sequences called bent function sequences which can be generated through nonlinear operations on m sequences these families of sequences possess asymptotically optimum correlation properties and large equivalent linear span els upper and lower bounds to the els of bent function sequences are derived the upper bound improves upon key s upper bound and the lower bound obtained through construction and exceeds left stackrel n 2 n 4 right cdot 2 n 4 where n is the length of the shift register generating the m sequence an interesting general result contained in the derivation is the exhibition of a class of nonlinear sequences whose els is guaranteed to be large

the cell probe complexity of succinct data structures we consider time space tradeoffs for static data structure problems in the cell probe model with word size 1 the bit probe model in this model the goal is to represent n bit data with s n r bits such that queries of a certain type about the data can be answered by reading at most t bits of the representation ideally we would like to keep both s and t small but there are tradeoffs between the values of s and t that limit the possibilities of keeping both parameters small in this paper we consider the case of succinct representations where s n r for some email protected n for a boolean version of the problem of polynomial evaluation with preprocessing of coefficients we show a lower bound on the redundancy query time tradeoff of the form r 1 t email protected n logn in particular for very small redundancies r we get an almost optimal lower bound stating that the query algorithm has to inspect almost the entire data structure up to a logarithmic factor we show similar lower bounds for problems satisfying a certain combinatorial properties of a coding theoretic flavor and obtain r 1 t email protected n for certain problems previously no w m lower bounds were known on t in the general model for explicit boolean problems even for very small redundancies by restricting our attention to systematic or index structures f satisfying f x email protected email protected x for some map f where denotes concatenation we show similar lower bounds on the redundancy query time tradeoff for the natural data structuring problems of prefix sum and substring search

a coding algorithm for constant weight vectors a geometric approach based on dissections we present a novel technique for encoding and decoding constant weight binary vectors that uses a geometric interpretation of the codebook our technique is based on embedding the codebook in a euclidean space of dimension equal to the weight of the code the encoder and decoder mappings are then interpreted as a bijection between a certain hyper rectangle and a polytope in this euclidean space an inductive dissection algorithm is developed for constructing such a bijection we prove that the algorithm is correct and then analyze its complexity the complexity depends on the weight of the vector rather than on the block length as in other algorithms this approach is advantageous when the weight is smaller than the square root of the block length

on synthesis of easily testable k k circuits a k k circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than k external inputs such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line is a partial k tree k k circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit and are useful if the constants k and k are small we demonstrate a procedure to synthesise k k circuits from a special class of boolean expressions

computational complexity of controllability observability problems for combinational circuits the computational complexity of fault detection problems and various controllability and observability problems for combinational logic circuits are analyzed it is shown that the fault detection problem is still np complete for monotone circuits limited in fanout i e when the number of signal lines which can out from a signal line is limited to two it is also shown that the observability problem for unate circuits is np complete but that the controllability problem for unate circuits can be solved in time complexity o m where m is the number of lines in a circuit two classes of circuits called k binate bounded circuits and k bounded circuits are then introduced for k binate bounded circuits the controllability problem is solvable in polynomial time and for k bounded circuits the fault detection problem is solvable in polynomial time when k

evolving better population distribution and exploration in evolutionary multi objective optimization the aim of multi objective evolutionary optimization is to minimize the distance between the solution set and the true pareto front to distribute the solutions evenly and to maximize the spread of solution set this paper addresses these issues by presenting two features that enhance the optimization ability of multi objective evolutionary algorithms the first feature is a variant of the mutation operator that adapts the mutation rate along the evolution process to maintain a balance between the introduction of diversity and local fine tuning in addition this adaptive mutation operator adopts a new approach to strike a compromise between the preservation and disruption of genetic information the second feature is an enhanced exploration strategy that encourages the exploration towards less populated areas and hence achieves better discovery of gaps in the generated front the strategy also preserves non dominated solutions in the evolving population to achieve a good convergence for the optimization comparative studies of some well known diversity operators mutation operators and multi objective evolutionary algorithms are performed on different benchmark problems which illustrate the effectiveness and efficiency of the proposed features

the k distinct language parameterized automata constructions abstract in this paper we pioneer a study of parameterized automata constructions for languages related to the design of parameterized algorithms we focus on the k distinct language l k k defined as the set of words of length k over an alphabet whose symbols are all distinct this language is implicitly related to several breakthrough techniques developed during the last two decades to design parameterized algorithms for fundamental problems such as k path and r dimensional k matching building upon the color coding divide and color and narrow sieves techniques we obtain the following automata constructions for l k we develop non deterministic automata nfas of sizes 4 k o k n o 1 and 2 e k o k n o 1 where the latter satisfies a bounded ambiguity property relevant to approximate counting as well as a non deterministic xor automaton nxa of size 2 k n o 1 where n we show that our constructions can be used to develop both deterministic and randomized algorithms for k path r dimensional k matching and module motif in a natural manner considering also their approximate counting variants our framework is modular and consists of two parts designing an automaton for k distinct and designing a problem specific automaton as well as an algorithm for deciding whether the intersection automaton s language is empty or for counting the number of accepting paths in it

multiple seed tpg structures linear feedback shift registers lfsrs are popular mechanisms for built in test pattern generation tpg they are normally used with a primitive characteristic polynomial because in that case only one initialization state seed is required we show that if the characteristic polynomial is nonprimitive irreducible the required seeds can still be efficiently generated we establish a formula that shows how the seeds of any nonprimitive irreducible polynomial relate to each other this leads to an efficient hardware implementation with small hardware overhead irrespective of the number of seeds and enhances the choices available for the design of appropriate tpg structures in the case of pseudoexhaustive tpg that were previously limited to primitive characteristic polynomials only

on the complexity of estimating the size of a test set most np completeness results for test generation problems involve a reduction to the redundancy problem which explicitly encodes the satisfiability problem in this correspondence we investigate the complexity of a more modest problem that of estimating the size of a test set under the constraint that the circuit is irredundant we show that even this constrained problem is np hard in the strong sense

the full kostant toda hierarchy on the positive flag variety we study some geometric and combinatorial aspects of the solution to the full kostant toda f kt hierarchy when the initial data is given by an arbitrary point on the totally non negative tnn flag variety of sl n mathbb r the f kt flows on the tnn flag variety are complete and we show that their asymptotics are completely determined by the cell decomposition of the tnn flag variety given by rietsch total positivity and real flag varieties ph d thesis massachusetts institute of technology cambridge 1998 our results represent the first results on the asymptotics of the f kt hierarchy and even the f kt lattice moreover our results are not confined to the generic flow but cover non generic flows as well we define the f kt flow on the weight space via the moment map and show that the closure of each f kt flow forms an interesting convex polytope which we call a bruhat interval polytope in particular the bruhat interval polytope for the generic flow is the permutohedron of the symmetric group mathfrak s n we also prove analogous results for the full symmetric toda hierarchy by mapping our f kt solutions to those of the full symmetric toda hierarchy in the appendix we show that bruhat interval polytopes are generalized permutohedra in the sense of postnikov int math res not imrn 6 1026 1106 2009

the complexity of very simple boolean formulas with applications the concepts of textbf sat hardness and textbf sat completeness modulo npolylogn time and linear size reducibility denoted by textbf sat hard npolylogn n and textbf sat complete npolylogn n respectively are introduced regardless of whether textbf p textbf np or textbf p neq textbf np it is shown that intuitivelyeach textbf sat hard npolylogn n problem requires essentially at least as much deterministic time as andeach textbf sat complete npolylogn n problem requires essentially the same deterministic time as the satisfiability problem for 3cnf formulas it is proved that the leqq satisfiability tautology unique satisfiability equivalence and minimization problems are already textbf sat complete npolylogn n for very simple boolean formulas and for very simple systems of boolean equations these completeness results are used to characterize the deterministic time complexities of a number of problems for lattices propositional calculi

young diagrams and n soliton solutions of the kp equation we consider n soliton solutions of the kp equation an n soliton solution is a solution u x y t which has the same set of n line soliton solutions in both asymptotics y and y the n soliton solutions include all possible resonant interactions among those line solitons we then classify those n soliton solutions by defining a pair of n numbers n n with n n 1 n n n j 1 2n which labels n line solitons in the solution the classification is related to the schubert decomposition of the grassmann manifolds gr n 2n where the solution of the kp equation is defined as a torus orbit then the interaction pattern of n soliton solution can be described by the pair of young diagrams associated with n n we also show that n soliton solutions of the kdv equation obtained by the constraint u y 0 cannot have resonant interaction

the complexity of generating minimum test sets for pla s and monotone combinational circuits the authors show that the problem of obtaining a minimum complete test set is np complete for monotone plas even when each product term of the pla contains at most two literals using the ideas developed in the proof of this result they resolve an open question due to b krishnamurthy and s b akers 1984 the authors also show that given a complete test set t the problem of obtaining a minimum test set contained in t is np complete even for two level monotone circuits

covering arrays avoiding forbidden edges covering arrays cas can be used to detect the existence of faulty pairwise interactions between parameters or components in a software system the generalization considered here applies to the situation in which some input combinations are invalid a requirement quite common in software testing in this paper we study covering arrays avoiding forbidden edges cafes where certain pairwise interactions are forbidden while all others must be covered and we aim to minimize the number of tests we establish a theoretical framework for this problem by providing connections to the edge clique covering problem lower and upper bounds complexity results and a recursive construction we also give an algorithm for the case of binary alphabets

wave fronts and cascades of soliton interactions in the periodic two dimensional volterra system in the paper we develop the dressing method for the solution of the two dimensional periodic volterra system with a period n we derive soliton solutions of arbitrary rank k and give a full classification of rank 1 solutions we have found a new class of exact solutions corresponding to wave fronts which represent smooth interfaces between two nonlinear periodic waves or a periodic wave and a trivial zero solution the wave fronts are non stationary and they propagate with a constant average velocity the system also has soliton solutions similar to breathers which resembles soliton webs in the kp theory we associate the classification of soliton solutions with the schubert decomposition of the grassmannians grr k n and grc k n

efficient vlsi fault simulation let c be an acyclic boolean circuit with n gates and n inputs a circuit manufacture error may result in a stuck at s a fault in a circuit identical to c except a gate v only outputs a fixed boolean value the s a fault simulation problem for c is to determine all possible s a faults which can be detected i e faults circuit and c would give distinct outputs by a given test pattern input we consider the case where c is a tree i e has fan out 1 we give a practical algorithm for fault simulation which simultaneously determines all detectable s a faults for every gate in the circuit tree c our algorithm required only the evaluation of a circuit fs c which has 7n gates and has depth 3 d 1 when d is the depth of c thus the sequential time of our algorithm is 7n and the parallel time is 3 d 1 furthermore fs c requires only a small constant factor more vlsi area than does the original circuit c we also extend our results to get efficient methods for fault simulation of oblivious vlsi circuits with feedback lines

on a family of solutions of the kadomtsev petviashvili equation which also satisfy the toda lattice hierarchy we describe the interaction pattern in the x y plane for a family of soliton solutions of the kadomtsev petviashvili kp equation the solutions considered also satisfy the finite toda lattice hierarchy we determine completely their asymptotic patterns for y and we show that all the solutions except the 1 soliton solution are of resonant type consisting of arbitrary numbers of line solitons in both asymptotics that is arbitrary n incoming solitons for y interact to form arbitrary n outgoing solitons for y we also discuss the interaction process of those solitons and show that the resonant interaction creates a web like structure having n 1 n 1 holes

intersecting codes and independent families a binary intersecting code is a linear code with the property that any two nonzero codewords have intersecting supports these codes appear in a wide variety of contexts and applications e g multiple access cryptography and information theory this paper is devoted partly to the study of intersecting codes and partly to their use in constructing large t independent families of binary vectors the latter subject has by now been extensively studied and has application in vlsi testing defect correction e biased probability spaces and derandomization by concatenation methods we construct codes with the highest known fate asymptotically we then generalize the concept to t wise intersecting codes we give bounds on the achievable rate of such codes both existential and constructive we show how t wise intersecting codes can be used to obtain t 1 independent families with this method we obtain improved asymptotical constructions of t independent families complexity issues are discussed

exhaustive generation of bit patterns with applications to vlsi self testing one has a shift register of length n and a collection of designated subsets of 0 1 n 1 the problem is to devise a method for feeding a string of bits into the shift register in such an order that for each designated subset s k1 kr if one keeps track of the bit patterns appearing at the corresponding positions k1 krof the shift register all 2r possible bit patterns will ultimately appear at those positions a simple and efficient solution to this problem derived from the connections between polynomials over finite fields and linear feedback shift registers is presented applications of this solution to the problem of vlsi self testing are discussed and illustrated