block recombination approach for subquadratic space complexity binary field multiplication based on toeplitz matrix vector product in this paper we present a new method for parallel binary finite field multiplication which results in subquadratic space complexity the method is based on decomposing the building blocks of the fan hasan subquadratic toeplitz matrix vector multiplier we reduce the space complexity of their architecture by recombining the building blocks in comparison to other similar schemes available in the literature our proposal presents a better space complexity while having the same time complexity we also show that block recombination can be used for efficient implementation of the ghash function of galois counter mode gcm

new block recombination for subquadratic space complexity polynomial multiplication based on overlap free approach in this paper we present new parallel polynomial multiplication formulas which result in subquadratic space complexity the schemes are based on a recently proposed block recombination of polynomial multiplication formula the proposed two way three way and four way split polynomial multiplication formulas achieve the smallest space complexities moreover by providing area time tradeoff method the proposed formulas enable one to choose a parallel formula for polynomial multiplication which is suited for a design environment

on the arithmetic operations over finite fields of characteristic three with low complexity in this paper the hermite polynomial representation is adapted as a new way to represent certain finite fields of characteristic three we give the multiplication method to multiply two elements of f 3 n in the hermite polynomial representation with subquadratic computational complexity by using a divide and conquer idea we show that in some cases there is a set of irreducible binomials in the hermite polynomial representation to obtain modular reduction with a lower addition complexity than the standard polynomial representation we also investigate the matrix vector product method for the multiplication of the field elements represented by hermite polynomials

wohlfahrt s theorem for the hecke group g5 abstract let k be a subgroup of the inhomogeneous hecke group g 5 of geometric level r then k is congruence if and only if k contains the principal congruence subgroup g 2 r in the case r 0 mod 4 k is congruence if and only if k contains the principal congruence subgroup g r

high speed architectures for multiplication using reordered normal basis normal basis has been widely used for the representation of binary field elements mainly due to its low cost squaring operation optimal normal basis type ii is a special class of normal basis exhibiting very low multiplication complexity and is considered as a safe choice for hardware implementation of cryptographic applications in this paper high speed architectures for binary field multiplication using reordered normal basis are proposed where reordered normal basis is referred to as a certain permutation of optimal normal basis type ii complexity comparison shows that the proposed architectures are faster compared to previously presented architectures in the open literature using either an optimal normal basis type ii or a reordered normal basis one advantage of the new word level architectures is that the critical path delay is a constant not a function of word size this enables the multipliers to operate at very high clock rates regardless of the field size or the number of words hardware implementation of some practical size multipliers for elliptic curve cryptography is also included

design of a linear systolic array for computing modular multiplication and squaring in gf 2m abstract one of the main operations for the public key cryptosystem is the modular exponentiation in this paper we analyze the montgomery s algorithm and design a linear systolic array for performing both modular multiplication and modular squaring simultaneously the proposed systolic array with less hardware complexity can be designed by making use of common multiplicand multiplication in the right to left modular exponentiation over gf 2 m for the fast computation of the modular exponentiation the proposed systolic array has 1 25 times improvement in area time complexity when compared to existing multipliers the proposed systolic array suffers a little loss in time complexity but it has 1 44 times improvement in area complexity since it executes the common parts that exist in the simultaneous computation of both modular multiplication and squaring only once it could be designed on vlsi hardware and used in ic cards

schmi gf 2 n shifted polynomial basis multipliers based on subquadratic toeplitz matrix vector product approach for all irreducible pentanomials besides karatsuba s algorithm optimal toeplitz matrix vector product tmvp formulae is another approach to design gf 2 n subquadratic multipliers however when gf 2 n elements are represented using a polynomial basis or its generalization shifted polynomial basis this approach is currently appliable only to fields gf 2 n generated by an irreducible trinomial or a special type of irreducible pentanomials but not to a general irreducible pentanomial the reason is that no transformation matrix which transforms the mastrovito matrix into a toeplitz matrix has been found in this article we propose such a transformation matrix and its inverse matrix for an arbitrary irreducible pentanomial

a new architecture for a parallel finite field multiplier with low complexity based on composite fields a bit parallel structure for a multiplier with low complexity in galois fields is introduced the multiplier operates over composite fields gf 2 sup n sup m with k nm the karatsuba ofman algorithm a karatsuba and y ofmanis 1963 is investigated and applied to the multiplication of polynomials over gf 2 sup n it is shown that this operation has a complexity of order o k sup log23 under certain constraints regarding k a complete set of primitive field polynomials for composite fields is provided which perform module reduction with low complexity as a result multipliers for fields gf 2 sup k up to k 32 with low gate counts and low delays are listed the architectures are highly modular and thus well suited for vlsi implementation

structure of parallel multipliers for a class of fields gf 2 m abstract this paper presents a configuration of parallel multipliers for gf 2 m based on canonical bases the possible parallel multipliers by the proposed configuration are limited to a class of fields gf 2 m however they can be constructed by o m 2 and gates and o m 2 eor gates with the structural modularity this is a desirable feature for the hardware implementation and their operation time is about log m t where m is the dimension of gf 2 m and t is the delay time of an eor gate in order to construct such parallel multipliers we define two types of polynomials of special form over gf 2 one is called all one polynomial denoted by aop and the other is called equally spaced polynomial denoted by esp furthermore we show a necessary and sufficient condition for esps to be irreducible over gf 2 and the uniqueness of the irreducible esps over gf 2 finally we propose the configuration of parallel multipliers for a class of fields gf 2 m based on irreducible aops and esps over gf 2

fault tolerant decoders for cyclic error correcting codes high speed cyclic code decoders which are central to modern communication systems when implemented in dense very large scale integration vlsi are susceptible to pernicious momentary internal soft fails presenting a demanding error control challenge however special structures inherent in such decoders offer new methods for incorporating distributed error control throughout their designs the underlying design principles and motivations are emphasized providing a variety of options to meet various requirements bose chaudhuri hocquenghem bch codes are used to exemplify the new techniques as applied to the usual three standard subsystems present in a decoder the first and last parts syndrome calculations and transform inversion both involve finite field transforms suggesting the effective application of fast transform algorithms error control features are based upon the chord properties of the transform coefficients including even fast algorithms the third subsystem the berlekamp massey algorithm can be protected through a chord recursion property affiliated with the error location connection polynomial the propagation and spread of internal errors are studied and a special sink register compares several quantities available in close proximity to their easily recomputed counterparts most of these results are applicable to generalized to decoders for codes over higher ordered alphabets such as reed solomon codes

comments on a new architecture for a parallel finite field multiplier with low complexity based on composite field in this comment we show that the gate complexity of karatsuba polynomial multipliers presented in the above paper can be reduced by exploring the common subexpressions

a vlsi design for computing exponentiations in gf 2 sup m and its application to generate pseudorandom number sequences a vlsi design for computing exponentiation in finite fields is developed an algorithm to generate a relatively long pseudorandom number sequence is presented it is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme

on computing multiplicative inverses in gf 2 sup m the design of a modular standard basis inversion for galois fields gf 2 sup m based on euclid s algorithm for computing the greatest common divisor of two polynomials is presented the asymptotic complexity is linear with m both in computation time and area requirement thus resulting in an at complexity of o m sup 2 this is a significant improvement over the best previous proposal which achieves at complexity of only o m sup 3

hardware and software normal basis arithmetic for pairing based cryptography in characteristic three although identity based cryptography offers a number of functional advantages over conventional public key methods the computational costs are significantly greater the dominant part of this cost is the tate pairing which in characteristic three is best computed using the algorithm of duursma and lee however in hardware and constrained environments this algorithm is unattractive since it requires online computation of cube roots or enough storage space to precompute required results we examine the use of normal basis arithmetic in characteristic three in an attempt to get the best of both worlds an efficient method for computing the tate pairing that requires no precomputation and that may also be implemented in hardware to accelerate devices such as smart cards

modular construction of low complexity parallel multipliers for a class of finite fields gf 2 sup m structures for parallel multipliers of a class of fields gf 2 sup m based on irreducible all one polynomials aop and equally spaced polynomials esp are presented the structures are simple and modular which is important for hardware realization relationships between an irreducible aop and the corresponding irreducible esps have been exploited to construct esp based multipliers of large fields by a regular expansion of the basic modules of the aop based multiplier of a small field some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible it is shown that if for a certain degree an irreducible aop as well as an irreducible esp exist then from the complexity point of view it is advantageous to use the esp based parallel multiplier

provably sublinear point multiplication on koblitz curves and its hardware implementation we describe algorithms for point multiplication on koblitz curves using multiple base expansions of the form k sigmaplusmntaua tau 1 b and k sigmaplusmntaua tau mu b tau2 mutau 1 c we prove that the number of terms in the second type is sublinear in the bit length of k which leads to the first provably sublinear point multiplication algorithm on koblitz curves for the first type we conjecture that the number of terms is sublinear and provide numerical evidence demonstrating that the number of terms is significantly less than that of tau adic nonadjacent form expansions we present details of an innovative fpga implementation of our algorithm and performance data demonstrating the efficiency of our method we also show that implementations with very low computation latency are possible with the proposed method because parallel processing can be exploited efficiently

high speed low complexity systolic designs of novel iterative division algorithms in gf 2 sup m we extend the binary algorithm invented by stein and propose novel iterative division algorithms over gf 2 sup m for systolic vlsi realization while algorithm ebg is a basic prototype with guaranteed convergence in at most 2m 1 iterations its variants algorithms ebd and ebdf are designed for reduced complexity and fixed critical path delay respectively we show that algorithms ebd and ebdf can be mapped to parallel in parallel out systolic circuits with low area time complexities of o m sup 2 loglogm and o m sup 2 respectively compared to the systolic designs based on the extended euclid s algorithm our circuits exhibit significant speed and area advantages

non similar normal oscillations in a strongly non linear discrete system abstract the free oscillations of a strongly non linear discrete oscillator are examined by computing its non similar non linear normal modes these are motions represented by curves in the configuration space of the system and they are not encountered in classical linear vibration theory or in existing non linear perturbation techniques the mikhlin manevich asymptotic methodology is used for solving the singular functional equation describing the non similar modes and approximate analytical expressions are derived for an oscillator with weak coupling stiffness and mistuning both localized and non localized modes are detected occurring in small neighborhoods of degenerate and global similar modes of the tuned system when strong coupling is considered only non localized modes were found to exist an interesting result of this work is the detection of mode localization in the tuned periodic system a result with no counterpart in existing theories on linear mode localization as a check of the analytical results numerical integrations of the equations of motion were carried out and the existence of the theoretically predicted non similar modes was verified

fast arithmetic for public key algorithms in galois fields with composite exponents the article describes a novel class of arithmetic architectures for galois fields gf 2 sup k the main applications of the architecture are public key systems which are based on the discrete logarithm problem for elliptic curves the architectures use a representation of the field gf 2 sup k as gf 2 sup n sup m where k n spl middot m the approach explores bit parallel arithmetic in the subfield gf 2 sup n and serial processing for the extension field arithmetic this mixed parallel serial hybrid approach can lead to fast implementations as the core module a hybrid multiplier is introduced and several optimizations are discussed we provide two different approaches to squaring we develop exact expressions for the complexity of parallel squarers in composite fields which can have a surprisingly low complexity the hybrid architectures are capable of exploring the time space trade off paradigm in a flexible manner in particular the number of clock cycles for one field multiplication which is the atomic operation in most public key schemes can be reduced by a factor of n compared to other known realizations the acceleration is achieved at the cost of an increased computational complexity we describe a proof of concept implementation of an asic for multiplication and squaring in gf 2 sup n sup m m variable

a new representation of elements of finite fields gf 2 sup m yielding small complexity arithmetic circuits let f sub 2 denote the binary field and f sub 2m an algebraic extension of degree m 1 over f sub 2 traditionally elements of f sub 2m are either represented as powers of a primitive element of f sub 2m together with 0 or by an expansion in a basis of the vector space f sub 2m over f sub 2 we propose a new representation based on an isomorphism from f sub 2m into the residue polynomial ring module x sup n 1 the new representation simultaneously satisfies the properties of various traditional representations which leads in some cases to architectures of parallel in parallel out arithmetic circuits adder multiplier exponentiator inverter squarer divider with average to small complexity we show that the implementation of all the arithmetic circuits designed for the new representation on an integrated circuit sometimes has smaller complexity than the implementation of all the arithmetic circuits designed for other representations in addition we derive a serial multiplier for the field f sub 2m which comprises the least number of gates of all the serial multipliers known to the author when m 1 is a prime such that 2 is primitive in the field z sub m 1

normalisers of subgroups of the modular group abstract let g be a subgroup of finite index of the modular group and let n g be the normaliser of g in psl2 r in this article we give an algorithm that determines n g

an algorithm to design finite field multipliers using a self dual normal basis the concept of using a self dual normal basis to design the massey omura finite field multiplier is presented an algorithm is given to locate a self dual normal basis for gf 2 sup m for odd m a method to construct the product function for designing the massey omura multiplier is developed it is shown that the construction of the product function based on a self dual basis is simpler than that based on an arbitrary normal basis

normal modes of vibration for non linear continuous systems a definition and a constructive methodology for normal nodes of motion are developed for a class of vibratory systems the dynamics of which are governed by non linear partial differential equations the definition for normal modes is given in terms of the dynamics on two dimensional invariant manifolds in the system phase space these manifolds are a continuation of the planes which represent the well known normal modes of the linearized system a local asymptotic approximation of the geometric structure of these manifolds can be obtained by using an approach which follows that used for generating center manifolds the procedure also provides the non linear ordinary differential equations which govern individual modal dynamics and a physical description of the system configuration when it is undergoing a modal motion in this paper the general theory is described for the application of vibrations of continuous media but it can easily be extended to other situations in order to demonstrate the power of the approach and its unique procedural aspects three examples involving beam vibrations are worked out in detail the examples are conservative simply supported beams the first demonstrates the methodology for a linear beam model the second is a beam on a non linear elastic foundation and the third example is a beam with non linear torsional springs attached at each end in these examples the simplicity of the mode shapes of the linearized model yields relatively simple calculations that do not obscure the important features of the procedure

a comparison of vlsi architecture of finite field multipliers using dual normal or standard bases three different finite field multipliers are presented 1 a dual basis multiplier due to e r berlekamp 1982 the massey omura normal basis multiplier and 3 the scott tavares peppard standard basis multiplier these algorithms are chosen because each has its own distinct features that apply most suitably in particular areas they are implemented on silicon chips with nmos technology so that the multiplier most desirable for vlsi implementation can readily be ascertained

bit serial systolic divider and multiplier for finite fields gf 2 sup m a systolic structure for bit serial division over the field gf 2 sup m is developed consideration is given to avoid global data communications and dependency of the time step duration on m this is important for applications where the value of m is large the divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m sup 2 and m respectively it does not depend on the irreducible polynomial and can be expanded easily moreover with m additional simple processors a bit serial systolic multiplier is developed which uses part of the divider structure this is advantageous from the implementation point of view as both the divider and multiplier can be fabricated on a single chip resulting in a reduction of area

low complexity bit parallel systolic montgomery multipliers for special classes of gf 2 sup m recently cryptographic applications based on finite fields have attracted much interest this paper presents a transformation method to implement low complexity montgomery multipliers for all one polynomials and trinomials using this method we propose a new bit parallel systolic architecture for computing multiplications over gf 2 sup m these new multipliers have a latency m 1 clock cycles and each cell incorporates at most one 2 input and gate two 2 input xor gates and four 1 bit latches moreover these new multipliers are shown to exhibit significantly lower latency and circuit complexity than the related systolic multipliers and are highly appropriate for vlsi systems because of their regular interconnection pattern modular structure and fully inherent parallelism

low complexity bit parallel multipliers for a class of finite fields new implementations of bit parallel multipliers for a class of finite fields are proposed the class of finite fields is constructed with irreducible aops all one polynomials and esps equally spaced polynomials the size and time complexities of our proposed multipliers are lower than or equal to those of the previously proposed multipliers of the same class

a karatsuba based algorithm for polynomial multiplication in chebyshev form in this paper we present a new method for multiplying polynomials in chebyshev form our approach has two steps first the well known karatsuba s algorithm is applied to polynomials constructed by using chebyshev coefficients then from the obtained result extra arithmetic operations are used to write the final result in chebyshev form the proposed algorithm has a quadratic computational complexity we also compare our method to other approaches

fast inversion in schmi gf 2 m with normal basis using hybrid double multipliers fast inversion in finite fields is crucial for high performance cryptography and codes we present techniques to exploit the recently proposed hybrid double multipliers for fast inversions in binary fields gf 2m with normal bases a hybrid double multiplier computes a double multiplication the product of three elements in gf 2m with a latency comparable to the latency of single multiplication of two elements traditional approaches such as itoh tsujii cannot utilize hybrid double multipliers we devise a new inversion algorithm based on ternary representations that exploits their potential the algorithm reduces the latency of inversion significantly for the fields recommended by nist if hybrid double multipliers are employed for example the algorithm computes an inversion in gf 2163 with only five double multiplications whereas the itoh tsujii algorithm requires nine single or double multiplications we propose a new inverter architecture using this new algorithm and a hybrid double multiplier we show that it is faster than the existing techniques by providing asic synthesis results using 65 nm cmos technology for example our inverter for gf 2163 achieves about 34 percent shorter computation time than an inverter using the itoh tsujii algorithm and a single multiplier

fast bit parallel gf 2 sup n multiplier for all trinomials based on a new representation of gf 2 sup n we present two multipliers for all irreducible trinomials space complexities of the multipliers match the best results the time complexity of one multiplier is t sub a 1 log sub 2 n t sub x for all irreducible trinomials where t sub a and t sub x are the delay of one 2 input and and xor gates respectively

new architectures for digit level single hybrid double hybrid triple field multiplications and exponentiation using gaussian normal bases gaussian normal bases gnbs are special set of normal bases nbs which yield low complexity gf left 2 m right arithmetic operations in this paper we present new architectures for the digit level single hybrid double and hybrid triple multiplication of gf left 2 m right elements based on the gnb representation for odd values of m 1 the proposed fully serial in single multipliers perform multiplication of two field elements and offer high throughput when the data path capacity for entering inputs is limited the proposed hybrid double and hybrid triple digit level gnb multipliers perform respectively two and three field multiplications using the same latency required for a single digit level multiplier at the expense of increased area in addition we present a new eight ary field exponentiation architecture which does not require precomputed or stored intermediate values

a fast algorithm for multiplicative inversion in gf 2 sup m using normal basis a fast algorithm for multiplicative inversion in gf 2 sup m using normal basis is proposed it is an improvement on those proposed by itoh and tsujii and by chang et al which are based on fermat s theorem and require o logm multiplications the number of multiplications is reduced by decomposing m 1 into several factors and a small remainder

mastrovito multiplier for general irreducible polynomials we present a new formulation of the mastrovito multiplication matrix for the field gf 2 sup m generated by an arbitrary irreducible polynomial we study in detail several specific types of irreducible polynomials e g trinomials all one polynomials and equally spaced polynomials and obtain the time and space complexity of these designs particular examples illustrating the properties of the proposed architecture are also given the complexity results established in this paper match the best complexity results known to date the most important new result is the space complexity of the mastrovito multiplier for an equally spaced polynomial which is found as m sup 2 spl delta xor gates and m sup 2 and gates where spl delta is the spacing factor

on the decoding of the 24 12 8 golay code an improved syndrome shift register decoding algorithm called the syndrome weight decoding algorithm is proposed for decoding three possible errors and detecting four errors in the 24 12 8 golay code this method can also be extended to decode two other short codes such as the 15 5 7 cyclic code and the 31 16 7 quadratic residue qr code the proposed decoding algorithm makes use of the properties of cyclic codes the weight of syndrome and the syndrome decoder with a reduced size lookup table rslt in order to reduce the number of syndromes and their corresponding coset leaders this approach results in a significant reduction in the memory requirement for the lookup table thereby yielding a faster decoding algorithm simulation results show that the decoding speed of the proposed algorithm is approximately 3 6 times faster than that of the algebraic decoding algorithm

normal basis of the finite field f sub 2 p 1 p sup m over f sub 2 the determination of normal bases for finite fields particularly over the finite field f sub 2 is of importance in applications such as coding and cryptography this correspondence gives an explicit normal basis for a finite field f sub 2 p 1 p sup m over f sub 2 when 2 is a primitive element module p sup 2 in the case when p 3 an explicit dual basis is also obtained

a new approach to subquadratic space complexity parallel multipliers for extended binary fields based on toeplitz matrix vector products and coordinate transformation techniques we present a new scheme for subquadratic space complexity parallel multiplication in gf 2n using the shifted polynomial basis both the space complexity and the asymptotic gate delay of the proposed multiplier are better than those of the best existing subquadratic space complexity parallel multipliers for example with n being a power of 2 the space complexity is about 8 percent better while the asymptotic gate delay is about 33 percent better respectively another advantage of the proposed matrix vector product approach is that it can also be used to design subquadratic space complexity polynomial dual weakly dual and triangular basis parallel multipliers to the best of our knowledge this is the first time that subquadratic space complexity parallel multipliers are proposed for dual weakly dual and triangular bases a recursive design algorithm is also proposed for efficient construction of the proposed subquadratic space complexity multipliers this design algorithm can be modified for the construction of most of the subquadratic space complexity multipliers previously reported in the literature

a search of minimal key functions for normal basis multipliers the circuit complexity of a massey omura normal basis multiplier for a finite field gf 2 sup m depends on the key function for multiplication key functions with minimum complexity called minimal key functions are desirable this paper investigates the complexity of a key function and reports search results of minimal key functions a table of minimal key functions for m up to 31 is included

a systolic power sum circuit for gf 2 sup m a systolic power sum circuit designed to perform ab sup 2 c computations in the finite field gf 2 sup m is presented where a b and c are arbitrary elements of gf 2 sup m this new circuit is constructed by m sup 2 identical cells each of which consists of three 2 input and logical gates one 2 input xor gate one 3 input xor gate and ten latches the ab sup 2 c computation is required in decoding many error correcting codes the paper shows that a decoder implemented using the new power sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product sum multipliers

efficient subquadratic space complexity binary polynomial multipliers based on block recombination some applications like cryptography involve a large number of multiplications of binary polynomial in this paper we consider two three and four way methods for parallel implementation of binary polynomial multiplication we propose optimized three and four way split formulas which reduce the space and time complexity of the best known methods moreover we present a block recombination method which provides some further reduction in the space complexity of the considered two three and four way split multipliers

normal modes for non linear vibratory systems a methodology is presented which extends to non linear systems the concept of normal modes of motion which is well developed for linear systems the method is constructive for weakly non linear systems and provides the physical nature of the normal modes along with the non linear differential equations which govern their dynamics it also provides the non linear co ordinate transformation which relates the original system co ordinates to the modal co ordinates using this transformation we demonstrate how an approximate non linear version of superposition can be employed to reconstruct the overall motion from the individual non linear modal dynamics the results presented herein for non linear systems reduce to modal analysis for the linearized system when non linearities are neglected even though the approach is entirely different from the traditional one the tools employed are from the theory of invariant manifolds for dynamical systems and were inspired by the center manifold reduction technique in this paper the basic ideas are outlined a few examples are presented and some natural extensions and applications of the method are briefly described in the conclusions

look up table based large finite field multiplication in memory constrained cryptosystems many cryptographic systems use multiplication in the finite field gf 2 sup n for their underlying computations in the recent past a number of look up table based algorithms have been proposed for the software implementation of gf 2 sup n multiplication look up table based algorithms can provide speed advantages but they either require a large memory space or do not fully utilize the resources of the processor on which the software is executed in this work an algorithm for gf 2 sup n multiplication is proposed which can alleviate this problem in each iteration of the proposed algorithm a group of bits of one of the input operands are examined and two look up tables are accessed the groupsize determines the table sizes but does not affect the utilization of the processor resources it can be used for both software and hardware realizations and is particularly suitable for implementations in memory constrained environment such as smart cards and embedded cryptosystems

on the inherent space complexity of fast parallel multipliers for gf 2 sup m a lower bound to the number of and gates used in parallel multipliers for gf 2 sup m under the condition that time complexity be minimum is determined in particular the exact minimum number of and gates for primitive normal bases and optimal normal bases of type ii multipliers is evaluated this result indirectly suggests that space complexity is essentially a quadratic function of m when time complexity is kept minimum

a new algorithm for multiplication in finite fields a new algorithm is presented for computing the product of two elements in a finite field by means of sums and products in a fixed subfield the algorithm is based on a normal basis representation of fields and assumes that the dimension m of the finite field over the subfield is a highly composite number a very fast parallel implementation and a considerable reduction in the number of computations are allowed in comparison to some methods discussed in the literature

vlsi architectures for soft decision decoding of reed solomon codes soft decision decoding of reed solomon codes delivers significant coding gains over classical minimum distance decoding in this paper we present architectures for polynomial interpolation and factorization the two main steps of the soft decoding algorithm we introduce an algorithmic transformation for reducing the iterations required in generating the interpolation polynomial and present efficient architectures by sharing computations we also describe algorithmic transformations for further reducing the interpolation and factorization latency an area efficient folded pipelined version of the interpolation architecture is also described finally we present an example of a reed solomon soft decoder utilizing the presented architectures having a 250 mbps throughput

a word level finite field multiplier using normal basis hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost in this paper a new word level finite field multiplier using normal basis is proposed the proposed architecture takes d clock cycles to compute the product bits where the value for d 1 d m can be arbitrarily selected by the designer to set the tradeoff between area and speed when there exists an optimal normal basis it is shown that the proposed design has a smaller critical path delay than other word level normal basis multipliers found in the literature while its circuit complexities are moderate and comparable to the others different word size multipliers were implemented in hardware and implementation results are also presented

a modified massey omura parallel multiplier for a class of finite fields a massey omura parallel multiplier of finite fields gf 2 sup m contains m identical blocks whose inputs are cyclically shifted versions of one another it is shown that for fields gf 2 sup m generated by irreducible all one polynomials a portion of the block is independent of the input cyclic shift hence the multiplier contains redundancy by removing the redundancy a modified parallel multiplier is presented which is modular and has a lower circuit complexity

a matrix decomposition method for optimal normal basis multiplication we introduce a matrix decomposition method and prove that multiplication in gf 2 k with a type 1 optimal normal basis for can be performed using k 2 1 xor gates irrespective of the choice of the irreducible polynomial generating the field the previous results achieved this bound only with special irreducible polynomials furthermore the decomposition method performs the multiplication operation using 1 5k k 1 xor gates for type 2a and 2b optimal normal bases which matches previous bounds

systolic array implementation of euclid s algorithm for inversion and division in gf 2 sup m this paper presents two new systolic arrays to realize euclid s algorithm for computing inverses and divisions in finite fields gf 2 sup m with the standard basis representation one of these two schemes is parallel in parallel out and the other is serial in serial out the former employs o m sup 2 area complexity to provide the maximum throughput in the sense of producing one result every clock cycle while the latter achieves a throughput of one result per m clock cycles using o m log m area complexity both of the proposed architectures are highly regular and thus well suited to vlsi implementation as compared to existing related systolic architectures with the same throughput performance the proposed parallel in parallel out scheme reduces the hardware complexity and thus the area time product by a factor of o m and the proposed serial in serial out scheme by a factor of o m log sub 2 m

a new hardware architecture for operations in gf 2 sup n the efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented the common field representations are a polynomial basis representation and a normal basis representation in this paper we introduce a nonconventional basis and present a new bit parallel multiplier which is as efficient as the modified massey omura multiplier using the type i optimal normal basis

concurrent error detection and correction in gaussian normal basis multiplier over gf 2 m fault based cryptanalysis has been developed to effectively break both private key and public key cryptosystems making robust finite field multiplication a very important research topic in recent years however no robust normal basis multiplier has been proposed in the literature therefore this investigation presents a semisystolic gaussian normal basis multiplier based on the proposed gaussian normal basis multiplier both concurrent error detection and correction capabilities can be easily achieved using time redundancy technology with no hardware modification

better circuits for binary polynomial multiplication we develop a new and simple way to describe karatsuba like algorithms for multiplication of polynomials over mathbb f 2 f 2 we restrict the search of small circuits to a class of circuits we call symmetric bilinear these are circuits in which and gates only compute functions of the form sum i in s a i cdot sum i in s b i quad quad s subseteq lbrace 0 ldots n 1 rbrace i s a i i s b i s 0 n 1 these techniques yield improved recurrences for m kn m k n the number of gates used in a circuit that multiplies two kn k n term polynomials for k 4 5 6 k 4 5 6 and 7 we built and verified the circuits for n n term binary polynomial multiplication for values of n n of practical interest circuits for n n up to 100 are posted at http cs www cs yale edu homes peralta circuitstuff binpolmult tar gz

effects of base points and normalization schemes on the non linear normal modes of conservative systems abstract in this paper two factors that affect the behaviors of the non linear normal modes nnms of conservative vibratory systems are investigated the first factor is the base points which are equivalent to taylor series expanding points of the non linear normal modes and the second one is the normalization schemes of the corresponding linear modes for non linear systems in general only the approximated nnm manifolds are obtainable in practice so different base points may lead to different forms of nnm oscillators and different normalization schemes lead to different forward and backward transformations which in turn affect the numerical computation errors three different kinds of base points and two different normalization schemes are adopted for comparison respectively two examples of non linear systems with two and three degrees of freedom respectively are given as illustration simulations for various cases are made the analysis and the simulation results indicated that the best base points are the abstract base points determined via the linear normal mode which would eliminate the third order terms containing velocity for cubic systems or quadratic terms for quadratic systems in equations of the nnm oscillators a better invariance of the nnms would also be maintained with such base points the best scheme of normalization is the norm one scheme that would minimize the numerical errors

architectures for exponentiation over gd 2 sup n adopted for smartcard application two exponentiation circuits are proposed using the fact that squaring is a linear operation over gf 2 sup n a time space tradeoff in smartcard based circuitry is presented it is shown how multiplication is performed by a single shift based on replacing the public key alpha sup a in gf 2 sup n by its minimal polynomial other considerations related to structure regularity and the possible use of dynamic shift registers are also treated

vlsi architectures for computing multiplications and inverses in gf 2 m finite field arithmetic logic is central in the implementation of reed solomon coders and in some cryptographic algorithms there is a need for good multiplication and inversion algorithms that can be easily realized on vlsi chips massey and omura 1 recently developed a new multiplication algorithm for galois fields based on a normal basis representation in this paper a pipeline structure is developed to realize the massey omura multiplier in the finite field gf 2m with the simple squaring property of the normal basis representation used together with this multiplier a pipeline architecture is also developed for computing inverse elements in gf 2m the designs developed for the massey omura multiplier and the computation of inverse elements are regular simple expandable and therefore naturally suitable for vlsi implementation

a new finite field multiplier using redundant representation this article presents simple and highly regular architectures for finite field multipliers using a redundant representation the basic idea is to embed a finite field into a cyclotomic ring which is based on the elegant multiplicative structure of a cyclic group one important feature of our architectures is that they provide area time trade offs which enable us to implement the multipliers in a partial parallel hybrid fashion this hybrid architecture has great significance in its vlsi implementation in very large fields the squaring operation using the redundant representation is simply a permutation of the coordinates it is shown that when there is an optimal normal basis the proposed bit serial and hybrid multiplier architectures have very low space complexity constant multiplication is also considered and is shown to have an advantage in using the redundant representation

efficient multiplier architectures for galois fields gf 2 sup 4n this contribution introduces a new class of multipliers for finite fields gf 2 sup n sup 4 the architecture is based on a modified version of the karatsuba ofman algorithm koa by determining optimized field polynomials of degree four the last stage of the koa and the module reduction can be combined this saves computation and area in vlsi implementations the new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with koa based architectures with separate module reduction the new multipliers lead to highly modular architectures and are thus well suited for vlsi implementations three types of field polynomials are introduced and conditions for their existence are established for the small fields where n 2 3 8 which are of primary technical interest optimized field polynomials were determined by an exhaustive search for each field order exact space and time complexities are provided

mastrovito multiplier for all trinomials an efficient algorithm for the multiplication in gf 2 sup m was introduced by mastrovito the space complexity of the mastrovito multiplier for the irreducible trinomial x sup m x 1 was given as m sup 2 1 xor and m sup 2 and gales in this paper we describe an architecture based on a new formulation of the multiplication matrix and show that the mastrovito multiplier for the generating trinomial x sup m x sup n 1 where m spl ne 2n also requires m sup 2 1 xor and m sup 2 and gates however m sup 2 x sup m 2 xor gates are sufficient when the generating trinomial is of the form x sup m x sup m 2 1 for an even m we also calculate the time complexity of the proposed mastrovito multiplier and give design examples for the irreducible trinomials x sup 7 x sup 4 1 and x sup 6 x sup 3 1

a fast algorithm for computing multiplicative inverses in gf 2 m using normal bases abstract this paper proposes a fast algorithm for computing multiplicative inverses in gf 2 m using normal bases normal bases have the following useful property in the case that an element x in gf 2 m is represented by normal bases 2 k power operation of an element x in gf 2 m can be carried out by k times cyclic shift of its vector representation c c wang et al proposed an algorithm for computing multiplicative inverses using normal bases which requires m 2 multiplications in gf 2 m and m 1 cyclic shifts the fast algorithm proposed in this paper also uses normal bases and computes multiplicative inverses iterating multiplications in gf 2 m it requires at most 2 log 2 m 1 multiplications in gf 2 m and m 1 cyclic shifts which are much less than those required in the wang s method the same idea of the proposed fast algorithm is applicable to the general power operation in gf 2 m and the computation of multiplicative inverses in gf q m q 2 n

a generalization of addition chains and fast inversions in binary fields in this paper we study a generalization of addition chains where k previous values are summed together on each step instead of only two values as in traditional addition chains such chains are called k chains and we show that they have applications in finding efficient parallelizations in problems that are known to be difficult to parallelize in particular 3 chains improve computations of inversions in finite fields using hybrid double multipliers recently it was shown that this operation can be efficiently computed using a ternary algorithm but we show that 3 chains provide a significantly more efficient solution

relationship between gf 2 m montgomery and shifted polynomial basis multiplication algorithms applying the matrix vector product idea of the mastrovito multiplier to the gf 2m montgomery multiplication algorithm we present a new parallel multiplier for irreducible trinomials this multiplier and the corresponding shifted polynomial basis spb multiplier have the same circuit structure for the same set of parameters furthermore by establishing isomorphisms between the montgomery and the spb constructions of gf 2m we show that the montgomery algorithm can be used to perform the spb multiplication without any changes and vice versa

at sup 2 optimal galois field multiplier for vlsi vlsi designs for galois field multipliers which are central in many encoding and decoding procedures for error detecting and error correcting codes are presented an at sup 2 optimal galois field multiplier based on at sup 2 optimal integer multipliers for a synchronous vlsi model is exhibited galois field multiplication is done in two steps first two polynomials of degree n 1 over z sub p are multiplied and then the resulting polynomial is reduced modulo a fixed irreducible polynomial of degree n multiplication of polynomials is done by discrete fourier transform dft for p 2 the procedure is more involved for z sub p x than for z x an extension to the case of variable p is included and some open problems are stated

geodesics nonlinear normal modes of conservative vibratory systems and decomposition method in this paper the relationship between the nonlinear normal modes nnms of conservative vibratory systems and the geodesics of the corresponding riemannian manifolds with the jacobi metric is investigated and a modified adomian decomposition method for constructing the nnms is proposed it is indicated that nnms in the configuration space are special geodesics of the corresponding riemannian manifold these geodesics pass through the origin of the configuration space and with specific directions determined by the total energy of the system geodesic equations describing the nnms become singular at the intersection of the riemannian manifold and the energy level plane to solve these singular geodesic equations the adomian decomposition method is used with a slight modification the nnms of strongly nonlinear vibration systems are constructed via the analytic approximation of the solution of the geodesics higher order approximate nnms can be constructed by a recursive procedure and the solution series is convergent rapidly finally two examples of nonlinear vibratory systems with two and four degrees of freedom dof respectively are given as illustration simulation results verified the effectiveness of this method

efficient multiplication beyond optimal normal bases in cryptographic applications the use of normal bases to represent elements of the finite field gf 2 sup m is quite advantageous especially for hardware implementation in this article we consider an important field operation namely multiplication which is used in many cryptographic functions we present a class of algorithms for normal basis multiplication in gf 2 sup m our proposed multiplication algorithm for composite finite fields requires a significantly lower number of bit level operations and hence can reduce the space complexity of cryptographic systems

low space complexity multiplication over binary fields with dickson polynomial representation we study dickson bases for binary field representation such a representation seems interesting when no optimal normal basis exists for the field we express the product of two field elements as toeplitz or hankel matrix vector products this provides a parallel multiplier which is subquadratic in space and logarithmic in time using the matrix vector formulation of the field multiplication we also present sequential multiplier structures with linear space complexity

arithmetic and geometry of the hecke groups abstract we study the arithmetic and geometry properties of the hecke group g q in particular we prove that g q has a subgroup x of index d genus g with v cusps and 2 resp v r i conjugacy classes of elliptic elements that are conjugates of s resp r q r i if and only if i 2 g 2 2 2 i 1 k v r i 1 1 r i v d 1 2 1 q and ii m 0 4 g 4 2 2 v i 1 k v r i 2 q r i 0 is a multiple of q 2 note that if q is odd resp prime then m 0 q 2 z resp n 0 is a consequence of i

low complexity bit parallel canonical and normal basis multipliers for a class of finite fields we present a new low complexity bit parallel canonical basis multiplier for the field gf 2m generated by an all one polynomial the proposed canonical basis multiplier requires m sup 2 1 xor gates and m sup 2 and gates we also extend this canonical basis multiplier to obtain a new bit parallel normal basis multiplier

double basis multiplicative inversion over gf 2 sup m inversion over galois fields is much more difficult than the corresponding multiplication efficient computation of inverses in gf 2 sup m is considered by solving a set of linear equations over the ground field gf 2 the proposed algorithm uses two separate bases for the representation of its input and output elements and has low computational complexity the algorithm is also suitable for hardware implementation using vlsi technologies

systolic multipliers for finite fields gf 2 m two systolic architectures are developed for performing the product sum computation ab c in the finite field gf 2m of 2melements where a b and c are arbitrary elements of gf 2m the first multiplier is a serial in serial out one dimensional systolic array while the second multiplier is a parallel in parallel out two dimensional systolic array the first multiplier requires a smaller number of basic cells than the second multiplier the second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively to perform single computations both multipliers require the same computational time in both cases the architectures are simple and regular and possess the properties of concurrency and modularity as a consequence they are well suited for use in vlsi systems

a systolic architecture for computing inverses and divisions in finite fields gf 2 sup m a new serial in serial out systolic array is presented for performing the element inversion in gf 2 sup m with the standard basis representation the architecture is highly regular modular nearest neighbor connected and thus well suited to vlsi implementation it has a latency of 7m 3 clock cycles and a throughput rate of one result per 2m 1 clock cycles this speed performance is much better than those of the previous implementations without change in hardware design the proposed inversion array can be directly used for computing the division in gf 2 sup m

montgomery multiplier and squarer for a class of finite fields montgomery multiplication in gf 2 sup m is defined by a x b x r sup 1 x mod f x where the field is generated by a root of the irreducible polynomial f x a x and b x are two field elements in gf 2 sup m and r x is a fixed field element in gf 2 sup m in this paper first a slightly generalized montgomery multiplication algorithm in gf 2 sup m is presented then by choosing r x according to f x we show that efficient architectures of bit parallel montgomery multiplier and squarer can be obtained for the fields generated with an irreducible trinomial complexities of the montgomery multiplier and squarer in terms of gate counts and time delay of the circuits are investigated and found to be as good as or better than that of previous proposals for the same class of fields

efficient algorithms and architectures for field multiplication using gaussian normal bases recently implementations of normal basis multiplication over the extended binary field gf 2 sup m have received considerable attention a class of low complexity normal bases called gaussian normal bases has been included in a number of standards such as ieee and nist for an elliptic curve digital signature algorithm the multiplication algorithms presented there are slow in software since they rely on bit wise inner product operations in this paper we present two vector level software algorithms which essentially eliminate such bit wise operations for gaussian normal bases our analysis and timing results show that the software implementation of the proposed algorithm is faster than previously reported normal basis multiplication algorithms the proposed algorithm is also more memory efficient compared with its look up table based counterpart moreover two new digit level multiplier architectures are proposed and it is shown that they outperform the existing normal basis multiplier structures as compared with similar digit level normal basis multipliers the proposed multiplier with serial output requires the fewest number of xor gates and the one with parallel output is the fastest multiplier

low complexity word level sequential normal basis multipliers for efficient hardware implementation of finite field arithmetic units the use of a normal basis is advantageous in this paper two classes of architectures for multipliers over the finite field gf 2 sup m are proposed these multipliers are of sequential type i e after receiving the coordinates of the two input field elements they go through k 1 spl les k spl les m iterations i e clock cycles to finally yield all the coordinates of the product in parallel the value of k depends on the word size w spl lceil m k spl rceil for w 1 these multipliers are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multipliers available in the open literature this makes the proposed multipliers suitable for applications where the value of m is large but space is of concern e g resource constrained cryptographic systems additionally if the field dimension m is composite i e m kn then the extension of one class of the architectures yields a highly efficient multiplier over composite fields

comb architectures for finite field multiplication in f 2 m two high speed bit serial word parallel or comb style finite field multipliers are proposed in this paper the first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type ii optimal normal basis exists the proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same the proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis field programmable gate array fpga implementation results of the proposed multipliers are compared to those of the previous methods using the same basis which confirms that the proposed multipliers allow a much higher clock rate

a new construction of massey omura parallel multiplier over gf 2 sup m the massey omura multiplier of gf 2 sup m uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another in the past it was shown that for a class of finite fields defined by irreducible all one polynomials the parallel massey omura multiplier had redundancy and a modified architecture of lower circuit complexity was proposed in this article it is shown that not only does this type of multiplier contain redundancy in that special class of finite fields but it also has redundancy in fields gf 2 sup m defined by any irreducible polynomial by removing the redundancy we propose a new architecture for the normal basis parallel multiplier which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original massey omura normal basis parallel multiplier the proposed multiplier structure is also modular and hence suitable for vlsi realization when applied to fields defined by the irreducible all one polynomials the multiplier s circuit complexity matches the best result available in the open literature

an architecture for computing zech s logarithms in gf 2 sup m in this paper a new method for calculation of zech s logarithm in gf 2 sup m is presented for a given element the logarithm is calculated by bit operations performed on its binary representation no look up tables are used the proposed method makes feasible the implementation of an universal type device for finite field arithmetic

on rademacher s conjecture congruence subgroups of genus zero of the modular group we list all genus zero congruence subgroups of psl2 z there are altogether 132 of them up to conjugation in psl2 z geometrical invariants genus v2 v3 number of cusps index in psl2 z fundamental polygons farey symbol and independent generators of all such groups are determined generators of the function fields associated to such groups are also determined http www math nus edu sg matlml

primitive polynomials and m sequences over gf q sup m procedures for obtaining primitive polynomials and m sequences over gf q sup m in terms of primitive polynomials and m sequences over gf q are presented using a degree mn primitive polynomial g x in gf g x an m sequence over gf q sup m can be expressed as a vector m sequence whose component m sequences are shifted versions of the m sequence generated by g x the degree n primitive polynomials in gf q sup m x with root alpha q sup i that are factors of g x with root alpha when g x is viewed in gf q sup m x are then developed from the m sequence over gf q sup m expressions for the shifts and corresponding primitive polynomial for the m sequence generated by the uth decimation of the m sequence generated by the polynomials are also given expressions for the shifts and corresponding primitive polynomial factors of g x for different bases expressing gf q sup m over gf q are presented