parallel high radix nonrestoring division an algorithm for high radix nonrestoring division is proposed which combines a cost efficient quotient estimation technique with collapsing of the division into one operation each iteration the quotient estimation technique is a direct combinatorial algorithm which allows a more generalized partial remainder than similar studies in addition the successor partial remainder is calculated directly from the previous partial remainder the intermediate steps of calculating the next quotient estimate multiplying it by the divisor and then subtracting the result from the previous remainder are telescoped into one step this is possible due to the use of simple direct combinatorial equations for the quotient estimate thus one operation is used to generate the next remainder from the previous remainder this operation is similar to a multiplication with a reduced carry propagate adder this algorithm reduces the latency of each iteration to less than the delay of one multiplication thus high radix nonrestoring division is possible with a low latency and no need for an off chip rom to hold a quotient estimate

an interpolating memory unit for function evaluation analysis and design a technique for the evaluation of a general continuous function f x is presented and the design of an interpolating memory as an implementation of the technique is described the technique partitions the domain of f x into segments and defines an interpolating or approximating function for each the implementation is a memory subsystem that holds the parameters of the approximating functions and yields an interpolated function value on each read reference polynomial interpolating functions are considered in particular hardware requirements memory and computational logic are analyzed in terms of the required precision it is shown that as long as f x has d 1 derivatives where d is the degree of the interpolating polynomial d 1 additional bits of precision of the computed f x are obtained for each additional address bit used in the interpolating memory this establishes a tradeoff between memory and computational logic which can be exploited in the design of a unit for a specific function for any precision requirement furthermore a single unit can be designed for any class of functions that have the required derivatives two examples of implementations for particular functions are presented

powering by a table look up and a multiplication with operand modification an efficient method for generating a power of an operand i e x sup p for an operand x and a given p is proposed it is applicable to ps in the form of spl plusmn 2 sup k where k is any integer and of spl plusmn 2 k sub 1 spl plusmn 2 k sub 2 where k sub 1 is any integer and k sub 2 is any nonnegative integer the reciprocal the square root the reciprocal square root the reciprocal square the reciprocal cube and so forth are included the method is a modification of the piecewise linear approximation a power of an operand is generated through a table look up and a multiplication with operand modification the same accuracy is achieved as the piecewise linear approximation the multiplication and an addition required for the piecewise linear approximation are replaced by only one double sized multiplication with a slight modification of the operand and hence one clock cycle may be reduced the required table size is reduced because only one coefficient instead of two has to be stored

design of a radix 4 division unit with simple selection table a radix 4 division architecture is presented which partially overlaps the updating of the remainder with the digit selection procedure it is obtained by separating the radix 4 digit selection process into two concurrent substeps the proposed unit requires a simple selection table and involves a small extra expense for the additional hardware compared to the usual radix 4 division units four possible implementations are derived from the general model with different types of substeps the high level evaluation shows that the proposed architectures offer an efficient alternative

signed digit addition and related operations with threshold logic assuming signed digit number representations we investigate the implementation of some addition related operations assuming linear threshold networks we measure the depth and size of the networks in terms of linear threshold gates we show first that a depth 2 network with o n size weight and fan in complexities can perform signed digit symmetric functions consequently assuming radix 2 signed digit representation we show that the two operand addition can be performed by a threshold network of depth 2 having o n size complexity and o 1 weight and fan in complexities furthermore we show that assuming radix 2n 1 signed digit representations the multioperand addition can be computed by a depth 2 network with o n sup 3 size with the weight and fan in complexities being polynomially bounded finally we show that multiplication can be performed by a linear threshold network of depth 3 with the size of o n sup 3 requiring o n sup 3 weights and o n sup 2 log n fan in

multilevel codes based on partitioning following v v ginzburg 1984 a hierarchy of codes is proposed to match the geometric partitioning of a signal set the authors show that coset codes including ungerboeck lattice and binary codes and indeed any codes which rely on partitioning of the signal set are all subclasses of the proposed coding scheme the combination of such codes in a multilevel scheme often leads to reduced complexity in comparison with previously published schemes a variety of decoder structures is discussed

radix 2 division with over redundant quotient selection in this paper we present a new radix 2 division algorithm that uses a recurrence employing simple 3 to 2 digit carry free adders to perform carry free addition subtraction for computing the partial remainders in radix 2 signed digit form the quotient digit during any iteration of the division recursion is generated from the two most significant radix 2 digits of the partial remainder and independent of the divisor in over redundant radix 2 digit form i e with digits which belong to the digit set 2 1 0 1 2 the over redundant quotient digits are then converted to the conventional radix 2 digits belonging to the set 1 0 1 by using a reduction technique this division algorithm is well suited for ieee 754 standard operands belonging to the range 1 2 and is slightly faster than previously proposed radix 2 designs such as the radix 2 srt which do not employ input scaling since the quotient selection for such algorithms is a function of more than two most significant radix 2 digits of the partial remainder in comparison with the designs that employ input scaling the proposed design although slightly slower saves hardware required for scaling purposes

division using a logarithmic exponential transform to form a short reciprocal two trees are used sequentially to calculate an approximation to 1 a where 1 a 2 these trees calculate the logarithm and exponential and the division reciprocation process can be described by 1 a e lna for bit skip accuracy of six to 10 this logarithmic exponential method uses significantly less hardware with respect to the scheme in 3 and the delays may be greater or less than those of 3 depending on the method used and the minimum bit skip

power and area efficient unified computation of vector and elementary functions for handheld 3d graphics systems a unified computation method of vector and elementary functions is proposed for handheld 3d graphics systems it unifies vector operations like vector multiply multiply and add divide divide by square root and dot product and elementary functions like trigonometric inverse trigonometric hyperbolic inverse hyperbolic power xy with two variables and logarithm to an arbitrary base into a single four way arithmetic platform a number system called the fixed point hybrid number system fxp hns which combines the fixed point number system fxp and the logarithmic number system lns is proposed for the power and area efficient unification power and area efficient logarithmic and antilogarithmic conversion schemes are also proposed for the data conversions between fixed point and logarithmic numbers in the fxp hns and achieve 0 41 percent and 0 08 percent maximum conversion errors respectively the unified arithmetic unit based on the proposed schemes is presented with less than 6 3 percent operation error its fully pipelined architecture achieves single cycle throughput with maximum four cycle latency for all of the supported operations comparison results show that the proposed arithmetic unit achieves 30 percent power and 10 9 percent area reductions and runs two times faster than the previous approach

high speed double precision computation of reciprocal division square root and inverse square root a new method for the high speed computation of double precision floating point reciprocal division square root and inverse square root operations is presented in this paper this method employs a second degree minimax polynomial approximation to obtain an accurate initial estimate of the reciprocal and the inverse square root values and then performs a modified goldschmidt iteration the high accuracy of the initial approximation allows us to obtain double precision results by computing a single goldschmidt iteration significantly reducing the latency of the algorithm two unfolded architectures are proposed the first one computing only reciprocal and division operations and the second one also including the computation of square root and inverse square root the execution times and area costs for both architectures are estimated and a comparison with other multiplicative based methods is presented the results of this comparison show the achievement of a lower latency than these methods with similar hardware requirements

algorithm and architecture for logarithm exponential and powering computation an architecture for the computation of logarithm exponential and powering operations is presented in this paper based on a high radix composite algorithm for the computation of the powering function x sup y the algorithm consists of a sequence of overlapped operations 1 digit recurrence logarithm 2 left to right carry free lrcf multiplication and 3 online exponential a redundant number system is used and the selection in 1 and 3 is done by rounding except from the first iteration when selection by table look up is necessary to guarantee the convergence of the recurrences a sequential implementation of the algorithm with a control unit which allows the independent computation of logarithm and exponential is proposed and the execution times and hardware requirements are estimated for single and double precision floating point computations these estimates are obtained for radices from r 8 to r 1 024 according to an approximate model for the delay and area of the main logic blocks and help determining the radix values which lead to the most efficient implementations r 32 and r 128

over redundant digit sets and the design of digit by digit division units over redundant digit sets are defined as those ranging from spl minus s to s with s spl ges b b being the radix this paper presents new techniques for the direct computation of division that use an over redundant digit set for representing the quotient instead of simply redundant ones used previously in particular general criteria for synthesizing the digit selection rules and remainder updating are given for any radix and index of redundancy a methodology combining the use of over redundant digit sets with the prescaling of the divisor is also studied in order to achieve radix b division units with trivial digit selection functions it is also shown for the specific case of radix 4 that using a prescaling slightly wider than in a radix 4 unit by m d ercegovac and t lang 1990 possible to avoid the digit selection table the paper also presents a modified algorithm for on the fly conversion of the result into the irredundant form the proposed methodology can be considered as an alternative to existing division techniques

unified mixed radix 2 4 redundant cordic processor we present a unified mixed radix cordic algorithm with carry save arithmetic with a constant scale factor the pipelined architecture of the processor is determined by a unique sequence of microrotations for the two modes of operation rotation and vectoring in circular and hyperbolic coordinates the combination of radix 2 and radix 4 microrotations allows us to reduce the latency and size of the pipeline significantly the unified algorithm is based on the correcting microrotation method which we have extended to the vectoring mode in hyperbolic coordinates we have also generalized the use of radix 4 microrotations to the two operation modes and coordinate systems

a fast radix 4 division algorithm and its architecture in this paper we present a fast radix 4 division algorithm for floating point numbers this method is based on svoboda s division algorithm and the radix 4 redundant number system the algorithm involves a simple recurrence with carry free addition and employs prescaling of the operands in the proposed divider implementation each radix 4 digit belonging to set 3 3 of the quotient and partial remainder is encoded using two radix 2 digits belonging to the set 1 0 1 and this leads to hardware simplicity the quotient digits are determined by observing three most significant radix 2 digits of the partial remainder and independent of the divisor the architecture presented for the proposed algorithm is faster than previously proposed radix 4 dividers which require at least four digits of the partial remainder to be observed to determine quotient digits

very high radix division with prescaling and selection by rounding a division algorithm in which the quotient digit selection is performed by rounding the shifted residual in carry save form is presented to allow the use of this simple function the divisor and dividend is prescaled to a range close to one the implementation presented results in a fast iteration because of the use of carry save forms and suitable recodings the execution time is calculated and several convenient values of the radix are selected comparison with other dividers for radices 2 sup 9 to 2 sup 18 is performed using the same assumptions

multiplicative division employing independent factors we introduce a division procedure where a normalized quotient approximation is derived as a product of four independent closed form factors specific derivations of the method for ieee 754 standard binary single and double precision division are developed in detail theoretical error bounds are derived to prove correctness for obtaining properly rounded single precision quotients by rounding the product of these four factors the proofs include exhaustive verification for the single precision extremal cases for double precision quotient approximations the error bounds verify suitable accuracy so that further determination of the remainder sign is sufficient to obtain precisely rounded double precision quotients selected experimental results are provided to illustrate the double precision level quotient approximations a prescaling process is introduced to reduce the table size requirements for these double precision approximations to less than 5 kbytes

hardware implementation trade offs of polynomial approximations and interpolations this paper examines the hardware implementation trade offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits in polynomial approximations polynomials are evaluated using stored coefficients polynomial interpolations however require the coefficients to be computed on the fly by using stored function values although it is known that interpolations require less memory than approximations but at the expense of additional computations the trade offs in memory area delay and power consumption between the two approaches have not been examined in detail this work quantitatively analyzes these trade offs for optimized approximations and interpolations across different functions and target precisions hardware architectures for degree 1 and degree 2 approximations and interpolations are described the results show that the extent of memory savings realized by using interpolation is significantly lower than what is commonly believed furthermore experimental results on a field programmable gate array fpga show that for high output precision degree 1 interpolations offer considerable area and power savings over degree 1 approximations but similar savings are not realized when degree 2 interpolations and approximations are compared the availability of both interpolation based and approximation based designs offers a richer set of design trade offs than what is available using either interpolation or approximation alone

high speed function approximation using a minimax quadratic interpolator a table based method for high speed function approximation in single precision floating point format is presented in this paper our focus is the approximation of reciprocal square root square root reciprocal exponentials logarithms trigonometric functions powering with a fixed exponent p or special functions the algorithm presented here combines table look up an enhanced minimax quadratic approximation and an efficient evaluation of the second degree polynomial using a specialized squaring unit redundant arithmetic and multioperand addition the execution times and area costs of an architecture implementing our method are estimated showing the achievement of the fast execution times of linear approximation methods and the reduced area requirements of other second degree interpolation algorithms moreover the use of an enhanced minimax approximation which through an iterative process takes into account the effect of rounding the polynomial coefficients to a finite size allows for a further reduction in the size of the look up tables to be used making our method very suitable for the implementation of an elementary function generator in state of the art dsps or graphics processing units gpus

low latency floating point division and square root unit digit recurrence algorithms are widely used in actual microprocessors to compute floating point division and square root these iterative algorithms present a good trade off in terms of performance area and power we present a floating point division and square root unit which implements a radix 64 floating point division and a radix 16 floating point square root to have an affordable implementation each radix 64 division iteration and radix 16 square root iteration are made of simpler radix 4 iterations 3 radix 4 iterations in division and 2 in square root speculation is used between consecutive radix 4 iterations to get a reduced timing there are three different parts in digit recurrence implementations initialization digit iterations and rounding the digit iteration is the iterative part and it uses the same logic for several cycles division and square root share partially the initialization and rounding stages whereas each one has different logic for the digit iterations the result is a low latency floating point divider and square root requiring 11 6 and 4 cycles for double single and half precision division with normalized operands and result and 15 8 and 5 cycles for square root one or two additional cycles are needed in case of subnormal operand s or result

coset codes i introduction and geometrical classification practically all known good constructive coding techniques for bandlimited channels including lattice codes and various trellis coded modulation schemes can be characterized as coset codes a coset code is defined by a lattice partition lambda lambda and by a binary encoder c that selects a sequence of cosets of the lattice lambda the fundamental coding gain of a coset code as well as other important parameters such as the error coefficient the decoding complexity and the constellation expansion factor are purely geometric parameters determined by c lambda lambda the known types of coset codes as well as a number of new classes that systematize and generalize known codes are classified and compared in terms of these parameters

a remark on reducing iteration time when result digit is zero for radix 2 srt division and square root with redundant remainders in a previous paper by p montuschi and l ciminiera ibid vol 42 no 2 p239 246 feb 1993 an architecture for shared radix 2 division and square root has been presented whose main characteristic is the ability to avoid any addition subtraction when the digit 0 has been selected here we emphasize the characteristics of the digit selection mechanism used by montuschi and ciminiera by presenting a small modification of the digit selection hardware which has the benefit to further reduce the computation delay with respect to the time estimated in that work

new svoboda tung division the paper presents a general theory for developing new svoboda tung or simply nst division algorithms not suffering the drawbacks of the classical svoboda tung or simply st method nst avoids the drawbacks of st by proper recoding of the two most significant digits of the residual before selecting the most significant digit of this recoded residual as the quotient digit nst relies on the divisor being in the range 1 1 spl delta where spl delta is a positive fraction depending upon 1 the radix 2 the signed digit set used to represent the residual and 3 the recoding conditions of the two most significant digits of the residual if the operands belong to the ieee std range 1 2 they have to be conveniently prescaled in that case nst produces the correct quotient but the final residual is scaled by the same factor as the operands therefore nst is not useful in applications where the unsealed residual is necessary an analysis of nst shows that previously published algorithms can be derived from the general theory proposed in the paper moreover nst reveals a spectrum of new possibilities for the design of alternative division units for a given radix b the number of different algorithms of this kind is b sup 2 4

lipschitz stability of nonlinear systems of differential equations in s the authors introduced the notion of lipschitz stability in differential equations this notion lies somewhere between uniform stability on one side and the notions of asymptotic stability in variation 3 and uniform stability in variation 4 on the other side however lipschitz stability is new only as a nonliner phenomenon since it coincides with uniform stability in linear systems s an important feature of lipschitz stability is that unlike uniform stability the linearized system inherits the property of lipschitz stability from the original nonlinear system 5 in this paper we pursue the study of lipschitz stability that started in s using essentially the techniques of liapunov functions then we give sufficient conditions for the lipschitz stability of certain nonlinearly pertur bed nonlinear systems such systems include among other equations certain integrodifferential and functional differential equations then we give an example which can be investigated successfully using our results but cannot be handled by any previous techniques or results 9

higher radix square root with prescaling a scheme for performing higher radix square root based on prescaling of the radicand is presented to reduce the complexity of the result digit selection the scheme requires several steps namely multiplication for prescaling the radicand square root multiplication for prescaling for the division and division online algorithms are used to reduce the overall time and pipelining to reuse the different modules an estimate of the execution time for a radix 256 unit for double precision square root and a comparison with other implementations indicate that the proposed approach is an alternative to consider when designing a square root unit

a unified architecture for the accurate and high throughput implementation of six key elementary functions this paper presents a unified architecture for the compact implementation of several key elementary functions including reciprocal square root and logarithm in single precision floating point arithmetic the proposed high throughput design is based on uniform domain segmentation and curve fitting techniques numerically accurate least squares regression is utilized to calculate the polynomial coefficients the architecture is optimized by analyzing the trade off between the size of the required memory and the precision of intermediate variables to achieve the minimum 23 bit accuracy required for single precision floating point representation the efficiency of the proposed unified data path is demonstrated on a common field programmable gate array

algorithm architecture and floating point unit codesign of a matrix factorization accelerator this paper examines the mapping of algorithms encountered when solving dense linear systems and linear least squares problems to a custom linear algebra processor specifically the focus is on cholesky lu with partial pivoting and qr factorizations and their blocked algorithms as part of the study we expose the benefits of redesigning floating point units and their surrounding data paths to support these complicated operations we show how adding moderate complexity to the architecture greatly alleviates complexities in the algorithm we study design tradeoffs and the effectiveness of architectural modifications to demonstrate that we can improve power and performance efficiency to a level that can otherwise only be expected of full custom asic designs a feasibility study of inner kernels is extended to blocked level and shows that at block level the linear algebra core lac can achieve high efficiencies with up to 45 gflops w for both cholesky and lu factorization and over 35 gflops w for qr factorization while maintaining such efficiencies our extensions to the mac units can achieve up to 10 12 and 20 percent speedup for the blocked algorithms of cholesky lu and qr factorization respectively

on the fly conversion of redundant into conventional representations an algorithm to convert redundant number representations into conventional representations is presented the algorithm is performed concurrently with the digit by digit generation of redundant forms by schemes such as srt division it has a step delay roughly equivalent to the delay of a carry save adder and simple implementation the conversion scheme is applicable in arithmetic algorithms such as nonrestoring division square root and on line operations in which redundantly represented results are generated in a digit by digit manner from most significant to least significant

choices of operand truncation in the srt division algorithm the paper presents an analysis of the number of partial remainder digits and divisor bits that must be examined in the srt division algorithm the number of examined digits is found to be the same for both signed digit and 2s complement partial remainder representations and appears to increase as 3log sub 2 r approximately where r is the radix of the divider in some cases it proves advantageous to examine a fractional number of remainder digits by inspecting more positive than negative bits

fast hardware based algorithms for elementary function computations using rectangular multipliers as the name suggests elementary functions play a vital role in scientific computations yet due to their inherent nature they are a considerable computing task by themselves not surprisingly since the dawn of computing the goal of speeding up elementary function computation has been pursued this paper describes new hardware based algorithms for the computation of the common elementary functions namely division logarithm reciprocal square root arc tangent sine and cosine these algorithms exploit microscopic parallelism using specialized hardware with heavy use of truncation based on detailed accuracy analysis the contribution of this work lies in the fact that these algorithms are very fast and yet are accurate if we let the time to perform an ieee standard 754 double precision floating point multiplication be spl tau sub spl times our algorithms to achieve roughly 3 68 spl tau sub spl times 4 56 spl tau sub spl times 5 25 spl tau sub spl times 3 69 spl tau sub spl times 7 06 spl tau sub spl times and 6 5 spl tau sub spl times for division logarithm square root exponential are tangent and complex exponential sine and cosine respectively the trade off is the need for tables and some specialized hardware the total amount of tables required however is less than 128 kbytes we discuss the hardware algorithmic and accuracy aspects of these algorithms

simple radix 4 division with operands scaling a radix 4 division algorithm with operands scaling is proposed the algorithm uses a recurrence with redundant addition carry save or signed digit and combines simple scaling with a quotient selection function that depends only on the estimate of the partial remainder and is independent of the divisor the scheme results in a significant speedup with respect to both the radix 2 and radix 4 without scaling

iterative algorithm and architecture for exponential logarithm powering and root extraction an algorithm and architecture for powering computation and root extraction with fixed point and floating point exponents is presented in this paper the algorithm is based on an optimized iterative sequence of parallel and or overlapped operations 1 reciprocal 2 high radix digit recurrence logarithm 3 left to right carry free multiplication and 4 high radix online exponential a redundant number system is used to allow for the overlapping of the different operations of the algorithm as the logarithm and exponential are part of the sequence of operations some minor changes are made to allow for the independent computation of the logarithm and exponential functions a sequential implementation of the algorithm is proposed and the execution times and hardware requirements are estimated for single and double precision floating point computations these estimates are obtained for several radices according to an approximate model for the delay and area of the main logic blocks and help to determine the radix values which lead to the most efficient implementations

very high radix square root with prescaling and rounding and a combined division square root unit an algorithm for square root with prescaling and selection by rounding is developed and combined with a similar scheme for division since division is usually more frequent than square root the main concern of the combined implementation is to maintain the low execution time of division while accepting a somewhat larger execution time for square root the algorithm is presented in detail including the mathematical development of bounds for the first square root digit and for the scaling factor the proposed implementation is described evaluated and compared with other combined div sqrt units the comparisons show that the proposed scheme potentially produces a significant speed up for division whereas for square root the speed up is small

lattice codes and generalized minimum distance decoding for ofdm systems lattice coding of orthogonal frequency division multiplexing ofdm systems is considered mapping of multilevel construction lattices to ofdm blocks is shown and a methodology for probabilistic analysis of multistage generalized minimum distance gmd decoding of the received ofdm blocks is shown as a case study transmission of points from a 128 dimensional barnes wall lattice is considered tight approximations to the system error rate are obtained and verified by simulation it appears that gmd decoding of lattice encoded ofdm provides high coding gain at low complexity

generalized minimum distance decoding of euclidean space codes and lattices it is shown that multistage generalized minimum distance gmd decoding of euclidean space codes and lattices can provide an excellent tradeoff between performance and complexity we introduce a reliability metric for gaussian channels that is easily computed from an inner product and prove that a multistage gmd decoder using this metric is a bounded distance decoder up to the true packing radius the effective error coefficient of multistage gmd decoding is determined two simple modifications in the gmd decoding algorithm that drastically reduce this error coefficient are proposed it is shown that with these modifications gmd decoding achieves the error coefficient of maximum likelihood decoding for block codes and for generalized construction a lattices multistage gmd decoding of the lattices d sub 4 e sub 8 k sub 12 bw sub 16 and spl lambda sub 24 is investigated in detail for k sub 12 bw sub 16 and spl lambda sub 24 the gmd decoders have considerably lower complexity than the best known maximum likelihood or bounded distance decoding algorithms and appear to be the most practically attractive decoders available for high dimensional codes and lattices spl ges 64 dimensions maximum likelihood decoding becomes infeasible while gmd decoding algorithms remain quite practical as an example we devise a multistage gmd decoder for a 128 dimensional sphere packing with a nominal coding gain of 8 98 db that attains an effective error coefficient of 1365760 this decoder requires only about 400 real operations in addition to algebraic errors and erasures decoding of certain bch and hamming codes it therefore appears to be practically feasible to implement algebraic multistage gmd decoders for high dimensional sphere packings and thus achieve high effective coding gains

efficient initial approximation for multiplicative division and square root by a multiplication with operand modification an efficient initial approximation method for multiplicative division and square root is proposed it is a modification of the piecewise linear approximation the multiplication and the addition required for the linear approximation are replaced by only one multiplication with a slight modification of the operand the same accuracy is achieved the modification of the operand requires only a bit wise inversion and a one bit shift and can be implemented by a very simple circuit one clock cycle may be saved because the addition is removed the required table size is also reduced because only one coefficient instead of two has to be stored

a cost effective pipelined divider with a small lookup table current pipelinable dividers require very large lookup tables we propose a cost effective pipelinable divider that uses a modified taylor series expansion and has a smaller lookup table than other pipelinable dividers the proposed divider requires about 27 percent less area than the pipelinable divider based on normal taylor series expansion in single precision

modular multiplication without trial division let n 1 we present a method for multiplying two integers called n residues modulo n while avoiding division by n n residues are represented in a nonstandard way so this method is useful only if several computations are done modulo one n the addition and subtraction algorithms are unchanged 1 description some algorithms 1 2 4 5 require extensive modular arith metic we propose a representation of residue classes so as to speed modular multiplication without affecting the modular addition and subtraction algorithms other recent algorithms for modular arithmetic appear in 3 6 fix n 1 define an a residue to be a residue class modulo n select a radix r coprime to n possibly the machine word size or a power thereof such that r n and such that computations modulo r are inexpensive to process let r l and n be integers satisfying 0 n then return t n else return t to validate redc observe mn tn n tmod r so t is an integer also tr tmod n so t tr x mod n thirdly 0 t mn rn rn so 0 t 2n if r and n are large then t mn may exceed the largest double precision value one can circumvent this by adjusting m so r m 0 given two numbers x and y between 0 and n 1 inclusive let z redc xy then z xy r x mod n so xr l yr x zrx mod n also 0 z n so z is the product of x and y in this representation other algorithms for operating on n residues in this representation can be derived from the algorithms normally used the addition algorithm is unchanged since xr x yr x zr x mod n if and only if x y z mod n also unchanged are

improving goldschmidt division square root and square root reciprocal the aim of this paper is to accelerate division square root and square root reciprocal computations when the goldschmidt method is used on a pipelined multiplier this is done by replacing the last iteration by the addition of a correcting term that can be looked up during the early iterations we describe several variants of the goldschmidt algorithm assuming 4 cycle pipelined multiplier and discuss obtained number of cycles and error achieved extensions to other than 4 cycle multipliers are given if we call g sub m the goldschmidt algorithm with m iterations our variants allow us to reach an accuracy that is between that of g sub 3 and that of g sub 4 with a number of cycle equal to that of g sub 3

reciprocation square root inverse square root and some elementary functions using small multipliers this paper deals with the computation of reciprocals square roots inverse square roots and some elementary functions using small tables small multipliers and for some functions a final large almost full length multiplication we propose a method based on argument reduction and series expansion that allows fast evaluation of these functions in high precision the strength of this method is that the same scheme allows the computation of all these functions we estimate the delay the size number of tables and the size number of multipliers and compare with other related methods