low complexity bit parallel architectures for polynomial basis multiplication over gf 2m representing the field elements with respect to the polynomial or standard basis we consider bit parallel architectures for multiplication over the finite field gf 2m in this effect first we derive a new formulation for polynomial basis multiplication in terms of the reduction matrix q the main advantage of this new formulation is that it can be used with any field defining irreducible polynomial using this formulation we then develop a generalized architecture for the multiplier and analyze the time and gate complexities of the proposed multiplier as a function of degree m and the reduction matrix q to the best of our knowledge this is the first time that these complexities are given in terms of q unlike most other articles on bit parallel finite field multipliers here we also consider the number of signals to be routed in hardware implementation and we show that compared to the well known mastrovito s multiplier the proposed architecture has fewer routed signals the proposed generalized architecture is further optimized for three special types of polynomials namely equally spaced polynomials trinomials and pentanomials we have obtained explicit formulas and complexities of the multipliers for these three special irreducible polynomials this makes it very easy for a designer to implement the proposed multipliers using hardware description languages like vhdl and verilog with minimum knowledge of finite field arithmetic

an efficient optimal normal basis type ii multiplier this paper presents a new parallel multiplier for the galois field gf 2 sup m whose elements are represented using the optimal normal basis of type ii the proposed multiplier requires 1 5 m sup 2 m xor gates as compared to 2 m sup 2 m xor gates required by the massey omura multiplier the time complexities of the proposed and the massey omura multipliers are similar

mimo interaction measure and controller structure selection in this paper a mimo interaction measure is described and its use in structure selection of multivariable controllers is discussed the proposal is built upon a gramian based measure of interaction in multivariable plants and the results in this paper apply to stable processes this measure provides support for decentralized input output pairing as well as for a richer controller architecture selection in continuous and discrete time time frameworks including triangular block diagonal and sparse structures

mastrovito form of non recursive karatsuba multiplier for all trinomials we present a new type of bit parallel non recursive karatsuba multiplier over gf 2 m generated by an arbitrary irreducible trinomial this design effectively exploits mastrovito approach and shifted polynomial basis spb to reduce the time complexity and karatsuba algorithm to reduce its space complexity we show that this type of multiplier is only one t x slower than the fastest bit parallel multiplier for all trinomials where t x is the delay of one 2 input xor gate meanwhile its space complexity is roughly 3 4 of those multipliers to the best of our knowledge it is the first time that our scheme has reached such a time delay bound this result outperforms previously proposed non recursive karatsuba multipliers

computing derivatives in interval type 2 fuzzy logic systems this paper makes type 2 fuzzy logic systems much more accessible to fuzzy logic system designers because it provides mathematical formulas and computational flowcharts for computing the derivatives that are needed to implement steepest descent parameter tuning algorithms for such systems it explains why computing such derivatives is much more challenging than it is for a type 1 fuzzy logic system it provides derivative calculations that are applicable to any kind of type 2 membership functions since the calculations are performed without prespecifying the nature of those membership functions some calculations are then illustrated for specific type 2 membership functions

on km algorithms for solving type 2 fuzzy set problems computing the centroid and performing type reduction for type 2 fuzzy sets and systems are operations that must be taken into consideration karnik mendel km algorithms are the standard ways to do these operations however because these algorithms are iterative much research has been conducted during the past decade about centroid and type reduction computations this tutorial paper focuses on the research that has been conducted to 1 improve the km algorithms 2 understand the km algorithms leading to further improved algorithms 3 eliminate the need for km algorithms 4 use the km algorithms to solve other nonfuzzy logic system problems and 5 use or not use km algorithms for general type 2 fuzzy sets and fuzzy logic systems

the montgomery inverse and its applications the montgomery inverse of b module a is b sup 1 2 sup n mod a where n is the number of bits in a the right shifting binary algorithm for modular inversion is shown naturally to compute the new inverse in fewer operations than the ordinary modular inverse the new inverse facilitates recent work by koc on modular exponentiation and has other applications in cryptography

comments on application of fft and the conjugate gradient method for the solution of electromagnetic radiation from electrically large and small conducting bodies in the original paper ibid vol ap 34 no 5 p 635 40 1986 t k sarkar et al describe how the fast fourier transform fft and the conjugate gradient method cgm can be used to efficiently make use of the convolutional form of the electric field integral equation for straight wire antennas the commentators agree that the cgm converges more rapidly than the previously used method of steepest descent and the spectral iteration technique they also point out that experience with the dyadic green s function encountered in the two dimensional transverse electric te and three dimensional equations for dielectric bodies is not so encouraging it is found that for these cases the cgm convergence can be quite slow degrading the efficiency of the algorithm in addition the solution obtained using the pulse basis point matching method to discretize the integral equation are very inaccurate for the two dimensional te and three dimensional cases a reply to these comments from the authors of the original paper is included

low complexity bit parallel canonical and normal basis multipliers for a class of finite fields we present a new low complexity bit parallel canonical basis multiplier for the field gf 2m generated by an all one polynomial the proposed canonical basis multiplier requires m sup 2 1 xor gates and m sup 2 and gates we also extend this canonical basis multiplier to obtain a new bit parallel normal basis multiplier

application of conjugate gradient method for static problems involving conductors of arbitrary shape in this paper two implementations of the conjugate gradient method cgm for the solution of problems in electrostatics involving conductors of arbitrary shapes have been discussed the first method uses a least squares approximation for the computation of the pertinent integral operator and is referred to as lsd a second implementation referred to as point matching discretisation pmd effects considerable saving in the computer time since it uses the midpoint rule for the integral arising in lsd both these techniques require o n storage where n is the number of patches used to model the conductor further a matrix interpretation of the present formulation has been derived this has facilitated the comparison of the techniques described in this paper with the well known method of moments mom formulation and has led to better understanding of the convergence of the results using illustrative examples of canonical square and circular discs and arbitrary shape a pyramid mounted on a cube the convergence of and the computer time for both the implementations have been investigated it has been shown that both the techniques yielded monotonically convergent results for all the examples considered and that the lsd offers better estimate of the capacitance than pmd with lower number of patches

low complexity bit parallel systolic montgomery multipliers for special classes of gf 2 sup m recently cryptographic applications based on finite fields have attracted much interest this paper presents a transformation method to implement low complexity montgomery multipliers for all one polynomials and trinomials using this method we propose a new bit parallel systolic architecture for computing multiplications over gf 2 sup m these new multipliers have a latency m 1 clock cycles and each cell incorporates at most one 2 input and gate two 2 input xor gates and four 1 bit latches moreover these new multipliers are shown to exhibit significantly lower latency and circuit complexity than the related systolic multipliers and are highly appropriate for vlsi systems because of their regular interconnection pattern modular structure and fully inherent parallelism

new low complexity bit parallel finite field multipliers using weakly dual bases new structures of bit parallel weakly dual basis wdb multipliers over the binary ground field are proposed an upper bound on the size complexity of bit parallel multiplier using an arbitrary generating polynomial is given when the generating polynomial is an irreducible trinomial x sup m x sup k 1 1 spl les k spl les m 2 the structure of the proposed bit parallel multiplier requires only m sup 2 two input and gates and at most m sup 2 1 xor gates the time delay is no greater than t sub a log sub 2 m 2 t sub x where t sub a and t sub x are the time delays of an and gate and an xor gate respectively

a technique for organizing large moment calculations for use with iterative solution methods through a specific choice of evenly spaced basis and testing functions one can construct a moment matrix formulation wherein significant redundancy is embodied in the matrix a scheme that exploits this redundancy to effect substantial computer storage reduction in an iterative field solution such as the conjugate gradient method is described the expense incurred is a modest increase in computation time the redundancy results from translational similarity features of specific classes of geometries and leads to matrix equations that may be interpreted as discrete convolutions for illustration the analysis here is carried out on a planar scatterer but the strategy can be applied to spherical or cylindrical scatterers

the montgomery modular inverse revisited we modify an algorithm given by kaliski to compute the montgomery inverse of an integer modulo a prime number we also give a new definition of the montgomery inverse and introduce efficient algorithms for computing the classical modular inverse the kaliski montgomery inverse and the new montgomery inverse the proposed algorithms are suitable for software implementations on general purpose microprocessors

montgomery multiplier and squarer for a class of finite fields montgomery multiplication in gf 2 sup m is defined by a x b x r sup 1 x mod f x where the field is generated by a root of the irreducible polynomial f x a x and b x are two field elements in gf 2 sup m and r x is a fixed field element in gf 2 sup m in this paper first a slightly generalized montgomery multiplication algorithm in gf 2 sup m is presented then by choosing r x according to f x we show that efficient architectures of bit parallel montgomery multiplier and squarer can be obtained for the fields generated with an irreducible trinomial complexities of the montgomery multiplier and squarer in terms of gate counts and time delay of the circuits are investigated and found to be as good as or better than that of previous proposals for the same class of fields

bit serial and bit parallel montgomery multiplication and squaring over gf 2 m multiplication and squaring are main finite field operations in cryptographic computations and designing efficient multipliers and squarers affect the performance of cryptosystems in this paper we consider the montgomery multiplication in the binary extension fields and study different structures of bit serial and bit parallel multipliers for each of these structures we study the role of the montgomery factor and then by using appropriate factors propose new architectures specifically we propose two bit serial multipliers for general irreducible polynomials and then derive bit parallel montgomery multipliers for two important classes of irreducible polynomials in this regard first we consider trinomials and provide a way for finding efficient montgomery factors which results in a low time complexity then we consider type ii irreducible pentanomials and design two bit parallel multipliers which are comparable to the best finite field multipliers reported in the literature moreover we consider squaring using this family of irreducible polynomials and show that this operation can be performed very fast with the time complexity of two xor gates

elliptic curve cryptosystems we discuss analogs based on elliptic curves over finite fields of public key cryptosystems which use the multiplicative group of a finite field these elliptic curve cryptosystems may be more secure because the analog of the discrete logarithm problem on elliptic curves is likely to be harder than the classical discrete logarithm problem especially over gf 2 we discuss the question of primitive points on an elliptic curve modulo p and give a theorem on nonsmoothness of the order of the cyclic subgroup generated by a global point

interaction measures for control configuration selection based on interval type 2 takagi sugeno fuzzy model interaction measure determines decentralized and sparse control configurations for a multivariable process control this paper investigates interval type 2 takagi sugeno fuzzy it2tsf model based interaction measures using two different criteria one is controllability and observability gramians the other is relative normalized gain array rnga the main contributions are first a data driven it2tsf modeling method is introduced second explicit formulas to execute the two measures based on it2tsf models are given third two interaction indexes are defined from rnga to select sparse control configuration fourth the calculations to derive sensitivities of the two measures with respect to parametric variations in the it2tsf models are developed and fifth the discussion to compare the two measures is presented three multivariable processes are used as examples to show that the results calculated from it2tsf models are more accurate than that from their type 1 counterparts and compared to gramian based measure rnga selects more reasonable control configurations and is more robust to the parametric uncertainties

bipartite modular multiplication method this paper proposes a new modular multiplication method that uses montgomery residues defined by a modulus m and a montgomery radix r whose value is less than the modulus m this condition enables the operand multiplier to be split into two parts that can be processed separately in parallel increasing the calculation speed the upper part of the split multiplier can be processed by calculating a product modulo m of the multiplicand and this part of the split multiplier the lower part of the split multiplier can be processed by calculating a product modulo m of the multiplicand this part of the split multiplier and the inverse of a constant r two different implementations based on this method are proposed one uses a classical modular multiplier and a montgomery multiplier and the other generates partial products for each part of the split multiplier separately which are added and accumulated in a single pipelined unit a radix 4 version of a multiplier based on a radix 4 classical modular multiplier and a radix 4 montgomery multiplier has been designed and simulated the proposed method is also suitable for software implementation in a multiprocessor environment

multicore curve based cryptoprocessor with reconfigurable modular arithmetic logic units over gf 2 n this paper presents a reconfigurable curve based cryptoprocessor that accelerates scalar multiplication of elliptic curve cryptography ecc and hyperelliptic curve cryptography hecc of genus 2 over gf 2n by allocating a copies of processing cores that embed reconfigurable modular arithmetic logic units malus over gf 2n the scalar multiplication of ecc hecc can be accelerated by exploiting instruction level parallelism ilp the supported field size can be arbitrary up to a n 1 1 the superscaling feature is facilitated by defining a single instruction that can be used for all field operations and point divisor operations in addition the cryptoprocessor is fully programmable and it can handle various curve parameters and arbitrary irreducible polynomials the cost performance and security trade offs are thoroughly discussed for different hardware configurations and software programs the synthesis results with a 0 13 mum cmos technology show that the proposed reconfigurable cryptoprocessor runs at 292 mhz whereas the field sizes can be supported up to 587 bits the compact and fastest configuration of our design is also synthesized with a fixed field size and irreducible polynomial the results show that the scalar multiplication of ecc over gf 2163 and hecc over gf 283 can be performed in 29 and 63 mus respectively

high speed hybrid double multiplication architectures using new serial out bit level mastrovito multipliers the serial out bit level multiplication scheme is characterized by an important latency feature it has an ability to sequentially generate an output bit of the multiplication result in each clock cycle however the computational complexity of the existing serial out bit level multipliers in gf 2 m using normal basis representation limits its usefulness in many applications hence an optimized serial out bit level multiplier using polynomial basis representation is needed in this paper we propose new serial out bit level mastrovito multiplier schemes we show that in terms of the time complexities the proposed multiplier schemes outperform the existing serial out bit level schemes available in the literature in addition using the proposed multiplier schemes we present new hybrid double multiplication architectures to the best of our knowledge this is the first time such a hybrid multiplier structure using the polynomial basis is proposed prototypes of the presented serial out bit level schemes and the proposed hybrid double multiplication architectures 10 schemes in total are implemented over both gf 2 163 and gf 2 233 and experimental results are presented

speeding the pollard and elliptic curve methods of factorization since 1974 several algorithms have been developed that attempt to factor a large number n by doing extensive computations module n and occasionally taking gcds with n these began with pollard s p 1 and monte carlo methods more recently williams published a p 1 method and lenstra discovered an elliptic curve method ecm we present ways to speed all of these one improvement uses two tables during the second phases of p 1 and ecm looking for a match polynomial preconditioning lets us search a fixed table of size n with n 2 o n multiplications a parametrization of elliptic curves lets step 1 of ecm compute the x coordinate of np from that of p in about 9 3 1og2 n multiplications for arbitrary p

high performance architecture of elliptic curve scalar multiplication a high performance architecture of elliptic curve scalar multiplication based on the montgomery ladder method over finite field gf 2m is proposed a pseudo pipelined word serial finite field multiplier with word size w suitable for the scalar multiplication is also developed implemented in hardware this system performs a scalar multiplication in approximately 6lceilm wrceil m 1 clock cycles and the gate delay in the critical path is equal to tand lceillog2 w k rceiltxor where tand and txor are delays due to two input and and xor gates respectively and 1 les k lt w is used to shorten the critical path

recursive least squares identification algorithms with incomplete excitation convergence analysis and application to adaptive control the convergence properties of a fairly general class of adaptive recursive least squares algorithms are studied under the assumption that the data generation mechanism is deterministic and time invariant first the open loop identification case is considered by a suitable notion of excitation subspace the convergence analysis of the identification algorithm is carried out with no persistent excitation hypothesis i e it is proven that the projection of the parameter error on the excitation subspace tends to zero while the orthogonal component of the error remains bounded the convergence of an adaptive control scheme based on the minimum variance control law is then dealt with it is shown that under the standard minimum phase assumption the tracking error converges to zero whenever the reference signal is bounded furthermore the control variable turns out to be bounded

a scalable dual field elliptic curve cryptographic processor we propose an elliptic curve ec cryptographic processor architecture that can support galois fields gf p and gf 2 sup n for arbitrary prime numbers and irreducible polynomials by introducing a dual field multiplier a montgomery multiplier with an optimized data bus and an on the fly redundant binary converter boost the throughput of the ec scalar multiplication all popular cryptographic functions such as dsa ec dsa rsa crt and prime generation are also supported all commands are organized in a hierarchical structure according to their complexity our processor has high scalability and flexibility between speed hardware area and operand size in the hardware evaluation using a 0 13 spl mu m cmos standard cell library the high speed design using 117 5 kgates with a 64 bit multiplier achieved operation times of 1 21 ms and 0 19 ms for a 160 bit ec scalar multiplication in gf p and gf 2 sup n respectively a compact version with an 8 bit multiplier requires only 28 3 k gates and executes the operations in 7 47 ms and 2 79 ms not only 160 bit operations but any bit length can be supported by any hardware configuration so long as the memory capacity is sufficient

programmable cellular automata based montgomery hardware architecture abstract this study presents efficient hardware architectures for montgomery multiplication and squaring based on programmable cellular automata pca multiplication and squaring are the key operation in implementing circuits for various applications of error control coding such as reed solomon code thus we employ montgomery multiplication and squaring algorithms and construct simple hardware architectures based on pca in gf 2 m our architectures are highly optimized and have low complexity based on irreducible all one polynomial aop

bit parallel finite field multipliers for irreducible trinomials a new formulation for the canonical basis multiplication in the finite fields gf 2 sup m based on the use of a triangular basis and on the decomposition of a product matrix is presented from this algorithm a new method for multiplication named transpositional applicable to general irreducible polynomials is deduced the transpositional method is based on the computation of 1 cycles and 2 cycles given by a permutation defined by the coordinate of the product to be computed and by the cardinality of the field gf 2 sup m the obtained cycles define groups corresponding to subexpressions that can be shared among the different product coordinates this new multiplication method is applied to five types of irreducible trinomials these polynomials have been widely studied due to their low complexity implementations the theoretical complexity analysis of the corresponding bit parallel multipliers shows that the space complexities of our multipliers match the best results known to date for similar canonical gf 2 sup m multipliers the most important new result is the reduction in two of the five studied trinomials of the time complexity with respect to the best known results

a chinese remainder theorem approach to bit parallel gf 2 n polynomial basis multipliers for irreducible trinomials we show that the step modulo the degree n field generating irreducible polynomial in the classical definition of the gf 2 n multiplication operation can be avoided this leads to an alternative representation of the finite field multiplication operation combining this representation and the chinese remainder theorem we design bit parallel gf 2 n multipliers for irreducible trinomials u n u k 1 on gf 2 where 1 for some values of n our architectures have the same time complexity as the fastest bit parallel multipliers the quadratic multipliers but their space complexities are reduced take the special irreducible trinomial u 2k u k 1 for example the space complexity of the proposed design is reduced by about 1 8 while the time complexity matches the best result our experimental results show that among the 539 values of n such that 4 and x n x k 1 is irreducible over gf 2 for some k in the range 1 the proposed multipliers beat the current fastest parallel multipliers for 290 values of n when n 1 3 le k le n 2 they have the same time complexity but the space complexities are reduced by 8 4 percent on average

vlsi architectures for computing multiplications and inverses in gf 2 m finite field arithmetic logic is central in the implementation of reed solomon coders and in some cryptographic algorithms there is a need for good multiplication and inversion algorithms that can be easily realized on vlsi chips massey and omura 1 recently developed a new multiplication algorithm for galois fields based on a normal basis representation in this paper a pipeline structure is developed to realize the massey omura multiplier in the finite field gf 2m with the simple squaring property of the normal basis representation used together with this multiplier a pipeline architecture is also developed for computing inverse elements in gf 2m the designs developed for the massey omura multiplier and the computation of inverse elements are regular simple expandable and therefore naturally suitable for vlsi implementation

optimum digit serial gf 2 m multipliers for curve based cryptography digit serial multipliers are used extensively in hardware implementations of elliptic and hyperelliptic curve cryptography this contribution shows different architectural enhancements in least significant digit lsd multiplier for binary fields gf 2m we propose two different architectures the double accumulator multiplier dam and n accumulator multiplier nam which are both faster compared to traditional lsd multipliers our evaluation of the multipliers for different digit sizes gives optimum choices and shows that currently used digit sizes are the worst possible choices hence one of the most important results of this contribution is that digit sizes of the form 2l 1 where l is an integer are preferable for the digit multipliers furthermore one should always use the nam architecture to get the best timings considering the time area product dam or nam gives the best performance depending on the digit size

solution stability of iterative schemes utilizing the discrete fourier transform em scattering the fredholm integral equation of the first kind can be solved numerically using iterative schemes which minimize the integral square error when the kernal is of the convolution type the discrete fourier transform dft can be used when evaluating the operator equation in the iterative schemes however the dft imposes an artificial periodicity thus changing the nature of the problem the effect of this on the solution has been studied and convergence investigated by comparison with a method of moments solution a proposed method of avoiding the periodicity problem has been studied the effect of introducing losses in the medium surrounding the scatterer has been investigated provided losses are low there is little effect on the solution

fuzzy basis functions universal approximation and orthogonal least squares learning fuzzy systems are represented as series expansions of fuzzy basis functions which are algebraic superpositions of fuzzy membership functions using the stone weierstrass theorem it is proved that linear combinations of the fuzzy basis functions are capable of uniformly approximating any real continuous function on a compact set to arbitrary accuracy based on the fuzzy basis function representations an orthogonal least squares ols learning algorithm is developed for designing fuzzy systems based on given input output pairs then the ols algorithm is used to select significant fuzzy basis functions which are used to construct the final fuzzy system the fuzzy basis function expansion is used to approximate a controller for the nonlinear ball and beam system and the simulation results show that the control performance is improved by incorporating some common sense fuzzy control rules

efficient montgomery based semi systolic multiplier for even type gnb of gf 2 m efficient finite field multiplication is crucial for implementing public key cryptosystem to achieve this multipliers using gaussian normal basis have been widely explored in previous works in this paper based on proposed gaussian normal basis montgomery gnbm representation a semi systolic even type gnbm multiplier is developed analysis shows that the proposed architecture saves about 57 percent space complexity and 50 percent time complexity when compared with the only existing semi systolic even type gnb multiplier moreover due to properties of regularity and modularity the proposed multiplier is very suitable for vlsi implementation

efficient multiplier architectures for galois fields gf 2 sup 4n this contribution introduces a new class of multipliers for finite fields gf 2 sup n sup 4 the architecture is based on a modified version of the karatsuba ofman algorithm koa by determining optimized field polynomials of degree four the last stage of the koa and the module reduction can be combined this saves computation and area in vlsi implementations the new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with koa based architectures with separate module reduction the new multipliers lead to highly modular architectures and are thus well suited for vlsi implementations three types of field polynomials are introduced and conditions for their existence are established for the small fields where n 2 3 8 which are of primary technical interest optimized field polynomials were determined by an exhaustive search for each field order exact space and time complexities are provided

error and convergence in numerical implementations of the conjugate gradient method em problems the conjugate gradient method has previously been applied in electromagnetics in two ways to moment method matrices and directly to continuous operator equations numerical implementations of these two methods are shown here to be equivalent it is concluded that the advantage of the conjugate gradient method is therefore its potential computational efficiency as a solution procedure not its ability to achieve a more exact solution than the moment method

parallel multipliers based on special irreducible pentanomials the state of the art galois field gf 2 sup m multipliers offer advantageous space and time complexities when the field is generated by so special irreducible polynomial to date the best complexity results have been obtained when the irreducible polynomial is either a trinomial or an equally spaced polynomial esp unfortunately there exist only a few irreducible esps in the range of interest for most of the applications e g error correcting codes computer algebra and elliptic curve cryptography furthermore it is not always possible to find an irreducible trinomial of degree m in this range for those cases where neither an irreducible trinomial nor an irreducible esp exists the use of irreducible pentanomials has been suggested irreducible pentanomials are abundant and there are several eligible candidates for a given m we promote the use of two special types of irreducible pentanomials we propose new mastrovito and dual basis multiplier architectures based on these special irreducible pentanomials and give rigorous analyses of their space and time complexity

fast parallel gf 2 m polynomial multiplication for all degrees numerous works have addressed efficient parallel gf 2m multiplication based on polynomial basis or some of its variants for those field degrees where neither irreducible trinomials nor equally spaced polynomials epss exist the best area time performance has been achieved for special type irreducible pentanomials which however do not exist for all degrees in other words no multiplier architecture has been proposed so far achieving the best performance and at the same time being general enough to support any field degrees in this paper we propose a new representation based on what we called generalized polynomial bases gpbs covering polynomial bases and the so called shifted polynomial bases spbs as special cases in order to study the new representation we introduce a novel formulation for polynomial basis and its variants which is able to express concisely all implementation aspects of interest i e gate count subexpression sharing and time delay the methodology enabled by the new formulation is completely general and repetitive in its application allowing the development of an ad hoc software tool to derive proofs for area complexity and time delays automatically as the central contribution of this paper we introduce some new types of irreducible pentanomials and an associated gpb based on the above formulation we prove that carefully chosen gpbs yield multiplier architectures matching or even outperforming the best special type pentanomials from both the area and time point of view most importantly the proposed gpb architectures require pentanomials existing for all degrees of practical interest a list of suitable irreducible pentanomials for all degrees less than 1 000 is given in the appendix fig 5 and tables 4 11 are provided in a separate file containing the body of appendix which can be found on the computer society digital library at http doi ieeecomputersociety org 10 1109 tc 2012 63

mastrovito multiplier for all trinomials an efficient algorithm for the multiplication in gf 2 sup m was introduced by mastrovito the space complexity of the mastrovito multiplier for the irreducible trinomial x sup m x 1 was given as m sup 2 1 xor and m sup 2 and gales in this paper we describe an architecture based on a new formulation of the multiplication matrix and show that the mastrovito multiplier for the generating trinomial x sup m x sup n 1 where m spl ne 2n also requires m sup 2 1 xor and m sup 2 and gates however m sup 2 x sup m 2 xor gates are sufficient when the generating trinomial is of the form x sup m x sup m 2 1 for an even m we also calculate the time complexity of the proposed mastrovito multiplier and give design examples for the irreducible trinomials x sup 7 x sup 4 1 and x sup 6 x sup 3 1

fast bit parallel gf 2 sup n multiplier for all trinomials based on a new representation of gf 2 sup n we present two multipliers for all irreducible trinomials space complexities of the multipliers match the best results the time complexity of one multiplier is t sub a 1 log sub 2 n t sub x for all irreducible trinomials where t sub a and t sub x are the delay of one 2 input and and xor gates respectively

concurrent error detection in montgomery multiplication over binary extension fields multiplication is one of the most important operations in finite field arithmetic it is used in cryptographic and coding applications such as elliptic curve cryptography and reed solomon codes in this paper we consider the finite field multiplication used in elliptic curve cryptography and design concurrent error detection circuits it is shown in the literature that the montgomery multiplication can be used in cryptography to accelerate the scalar multiplication here we use a parity based concurrent error detection approach to increase the reliability of different montgomery multipliers available in the literature first we consider bit serial montgomery multiplication and propose an error detection circuit then we apply the same technique on the digit serial montgomery multiplication finally we consider low time complexity bit parallel montgomery multiplication and design the required components to implement the concurrent error detection circuits asic implementations have been completed to analyze the time and area overheads of the proposed schemes also the error detection capability is investigated by software simulations we show that our approach results in efficient error detection schemes with small time and area overheads

modular construction of low complexity parallel multipliers for a class of finite fields gf 2 sup m structures for parallel multipliers of a class of fields gf 2 sup m based on irreducible all one polynomials aop and equally spaced polynomials esp are presented the structures are simple and modular which is important for hardware realization relationships between an irreducible aop and the corresponding irreducible esps have been exploited to construct esp based multipliers of large fields by a regular expansion of the basic modules of the aop based multiplier of a small field some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible it is shown that if for a certain degree an irreducible aop as well as an irreducible esp exist then from the complexity point of view it is advantageous to use the esp based parallel multiplier

relationship between gf 2 m montgomery and shifted polynomial basis multiplication algorithms applying the matrix vector product idea of the mastrovito multiplier to the gf 2m montgomery multiplication algorithm we present a new parallel multiplier for irreducible trinomials this multiplier and the corresponding shifted polynomial basis spb multiplier have the same circuit structure for the same set of parameters furthermore by establishing isomorphisms between the montgomery and the spb constructions of gf 2m we show that the montgomery algorithm can be used to perform the spb multiplication without any changes and vice versa

modular multiplication without trial division let n 1 we present a method for multiplying two integers called n residues modulo n while avoiding division by n n residues are represented in a nonstandard way so this method is useful only if several computations are done modulo one n the addition and subtraction algorithms are unchanged 1 description some algorithms 1 2 4 5 require extensive modular arith metic we propose a representation of residue classes so as to speed modular multiplication without affecting the modular addition and subtraction algorithms other recent algorithms for modular arithmetic appear in 3 6 fix n 1 define an a residue to be a residue class modulo n select a radix r coprime to n possibly the machine word size or a power thereof such that r n and such that computations modulo r are inexpensive to process let r l and n be integers satisfying 0 n then return t n else return t to validate redc observe mn tn n tmod r so t is an integer also tr tmod n so t tr x mod n thirdly 0 t mn rn rn so 0 t 2n if r and n are large then t mn may exceed the largest double precision value one can circumvent this by adjusting m so r m 0 given two numbers x and y between 0 and n 1 inclusive let z redc xy then z xy r x mod n so xr l yr x zrx mod n also 0 z n so z is the product of x and y in this representation other algorithms for operating on n residues in this representation can be derived from the algorithms normally used the addition algorithm is unchanged since xr x yr x zr x mod n if and only if x y z mod n also unchanged are

resonance frequency of a rectangular microstrip patch the microstrip patch resonant frequency problem is formulated in terms of an integral equation using vector fourier transforms using galerkins s method in solving the integral equation the resonant frequency of the microstrip patch is studied with both chebyshev polynomials and sinusoidal functions as basis functions in the case of the chebyshev polynomials the edge singularity is included but it is not important for convergence furthermore the resonant frequency of the microstrip patch is ascertained with a perturbation calculation the results for galerkin s method and experiments are in good agreement the perturbation calculation agrees asymptotically with galerkin s method with the aim of developing a computer aided design formula the solutions obtained by galerkin s method are interpolated with a three variable polynomial

efficient bit parallel multiplier for irreducible pentanomials using a shifted polynomial basis in this paper we present a bit parallel multiplier for gf 2m defined by an irreducible pentanomial xm xk 3 xk 2 xk 1 1 where 1lesk 1 lesk2 lesk3 lesm 2 in order to design an efficient bit parallel multiplier we introduce a shifted polynomial basis and modify a reduction matrix presented by reyhani masoleh and hasan as a result the time complexity of the proposed multiplier is ta 3 log2 m 1 tx where ta and tx are the delay of one and and one xor gate respectively this result matches or outperforms the previously known results on the other hand the proposed multiplier has the same space complexity as the previously known multipliers except for special types of irreducible pentanomials note that its hardware architecture is similar to that presented by reyhani masoleh and hasan