on non archimedean recurrence equations and their applications in the present paper we study stability of recurrence equations which in particular case contain dynamics of rational functions generated by contractive functions defined on an arbitrary non archimedean algebra moreover multirecurrence equations are considered we also investigate reverse recurrence equations which have application in the study of p adic gibbs measures note that our results also provide the existence of unique solutions of nonlinear functional equations we should stress that the non archimedeanity of the algebra is essentially used therefore the methods applied in the present paper are not valid in the archimedean setting

p adic quantum mechanics with p adic valued functions an extension of the formalism of quantum mechanics to the case where the canonical variables and functions are valued in a field of p adic numbers is considered a new p adic integral calculus is used for the realization of the gauss representation in p adic quantum mechanics

on a class of rational p adic dynamical systems in this paper we investigate the behavior of trajectories of one class of rational p adic dynamical systems in complex p adic field cp we studied siegel disks and attractors of such dynamical systems we found the basin of the attractor of the system it is proved that such dynamical systems are not ergodic on a unit sphere with respect to the haar measure

on the decoding of the 24 12 8 golay code an improved syndrome shift register decoding algorithm called the syndrome weight decoding algorithm is proposed for decoding three possible errors and detecting four errors in the 24 12 8 golay code this method can also be extended to decode two other short codes such as the 15 5 7 cyclic code and the 31 16 7 quadratic residue qr code the proposed decoding algorithm makes use of the properties of cyclic codes the weight of syndrome and the syndrome decoder with a reduced size lookup table rslt in order to reduce the number of syndromes and their corresponding coset leaders this approach results in a significant reduction in the memory requirement for the lookup table thereby yielding a faster decoding algorithm simulation results show that the decoding speed of the proposed algorithm is approximately 3 6 times faster than that of the algebraic decoding algorithm

high speed low complexity systolic designs of novel iterative division algorithms in gf 2 sup m we extend the binary algorithm invented by stein and propose novel iterative division algorithms over gf 2 sup m for systolic vlsi realization while algorithm ebg is a basic prototype with guaranteed convergence in at most 2m 1 iterations its variants algorithms ebd and ebdf are designed for reduced complexity and fixed critical path delay respectively we show that algorithms ebd and ebdf can be mapped to parallel in parallel out systolic circuits with low area time complexities of o m sup 2 loglogm and o m sup 2 respectively compared to the systolic designs based on the extended euclid s algorithm our circuits exhibit significant speed and area advantages

at sup 2 optimal galois field multiplier for vlsi vlsi designs for galois field multipliers which are central in many encoding and decoding procedures for error detecting and error correcting codes are presented an at sup 2 optimal galois field multiplier based on at sup 2 optimal integer multipliers for a synchronous vlsi model is exhibited galois field multiplication is done in two steps first two polynomials of degree n 1 over z sub p are multiplied and then the resulting polynomial is reduced modulo a fixed irreducible polynomial of degree n multiplication of polynomials is done by discrete fourier transform dft for p 2 the procedure is more involved for z sub p x than for z x an extension to the case of variable p is included and some open problems are stated

normal basis of the finite field f sub 2 p 1 p sup m over f sub 2 the determination of normal bases for finite fields particularly over the finite field f sub 2 is of importance in applications such as coding and cryptography this correspondence gives an explicit normal basis for a finite field f sub 2 p 1 p sup m over f sub 2 when 2 is a primitive element module p sup 2 in the case when p 3 an explicit dual basis is also obtained

on measure preserving mathcal c1 transformations of compact open subsets of non archimedean local fields we introduce the notion of a locally scaling transformation defined on a compactopen subset of a non archimedean local field we show that this class encompasses the haar measure preserving transformations defined by c in particular polynomial maps and prove a structure theorem for locally scaling transformations we use the theory of polynomial approximation on compact open subsets of non archimedean local fields to demonstrate the existence of ergodic markov and mixing markov transformations defined by such polynomial maps we also give simple sufficient conditions on the mahler expansion of a continuous map zp zp for it to define a bernoulli transformation

polynomial division using left shift register abstract in this short note we describe a simple polynomial division circuit based on a left shift register the circuit essentially performs the modulo operation f x mod p x it is shown how the same circuit can be used to perform f x g x mod p x applications to standard basis multiplication and encoding and decoding of systematic cyclic codes are also described

a new approach to subquadratic space complexity parallel multipliers for extended binary fields based on toeplitz matrix vector products and coordinate transformation techniques we present a new scheme for subquadratic space complexity parallel multiplication in gf 2n using the shifted polynomial basis both the space complexity and the asymptotic gate delay of the proposed multiplier are better than those of the best existing subquadratic space complexity parallel multipliers for example with n being a power of 2 the space complexity is about 8 percent better while the asymptotic gate delay is about 33 percent better respectively another advantage of the proposed matrix vector product approach is that it can also be used to design subquadratic space complexity polynomial dual weakly dual and triangular basis parallel multipliers to the best of our knowledge this is the first time that subquadratic space complexity parallel multipliers are proposed for dual weakly dual and triangular bases a recursive design algorithm is also proposed for efficient construction of the proposed subquadratic space complexity multipliers this design algorithm can be modified for the construction of most of the subquadratic space complexity multipliers previously reported in the literature

a search of minimal key functions for normal basis multipliers the circuit complexity of a massey omura normal basis multiplier for a finite field gf 2 sup m depends on the key function for multiplication key functions with minimum complexity called minimal key functions are desirable this paper investigates the complexity of a key function and reports search results of minimal key functions a table of minimal key functions for m up to 31 is included

an efficient optimal normal basis type ii multiplier this paper presents a new parallel multiplier for the galois field gf 2 sup m whose elements are represented using the optimal normal basis of type ii the proposed multiplier requires 1 5 m sup 2 m xor gates as compared to 2 m sup 2 m xor gates required by the massey omura multiplier the time complexities of the proposed and the massey omura multipliers are similar

a new representation of elements of finite fields gf 2 sup m yielding small complexity arithmetic circuits let f sub 2 denote the binary field and f sub 2m an algebraic extension of degree m 1 over f sub 2 traditionally elements of f sub 2m are either represented as powers of a primitive element of f sub 2m together with 0 or by an expansion in a basis of the vector space f sub 2m over f sub 2 we propose a new representation based on an isomorphism from f sub 2m into the residue polynomial ring module x sup n 1 the new representation simultaneously satisfies the properties of various traditional representations which leads in some cases to architectures of parallel in parallel out arithmetic circuits adder multiplier exponentiator inverter squarer divider with average to small complexity we show that the implementation of all the arithmetic circuits designed for the new representation on an integrated circuit sometimes has smaller complexity than the implementation of all the arithmetic circuits designed for other representations in addition we derive a serial multiplier for the field f sub 2m which comprises the least number of gates of all the serial multipliers known to the author when m 1 is a prime such that 2 is primitive in the field z sub m 1

a systolic power sum circuit for gf 2 sup m a systolic power sum circuit designed to perform ab sup 2 c computations in the finite field gf 2 sup m is presented where a b and c are arbitrary elements of gf 2 sup m this new circuit is constructed by m sup 2 identical cells each of which consists of three 2 input and logical gates one 2 input xor gate one 3 input xor gate and ten latches the ab sup 2 c computation is required in decoding many error correcting codes the paper shows that a decoder implemented using the new power sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product sum multipliers

efficient multiplication beyond optimal normal bases in cryptographic applications the use of normal bases to represent elements of the finite field gf 2 sup m is quite advantageous especially for hardware implementation in this article we consider an important field operation namely multiplication which is used in many cryptographic functions we present a class of algorithms for normal basis multiplication in gf 2 sup m our proposed multiplication algorithm for composite finite fields requires a significantly lower number of bit level operations and hence can reduce the space complexity of cryptographic systems

bit parallel polynomial basis multiplier for new classes of finite fields in this paper three small classes of finite fields gf 2m are found for which low complexity bit parallel multipliers are proposed the proposed multipliers have lower complexities compared to those based on the irreducible pentanomials it is also shown that there does not always exist an irreducible all one polynomial equally spaced polynomial or trinomial for the new classes of fields

p adic dynamics the quadratic map overp adic numbers is studied in some detail we prove that near almost all indifferent fixed points it is topologically conjugate to a quasiperiodic linear map we also establish the existence of chaotic behavior and describe it using symbolic dynamics

low complexity bit parallel canonical and normal basis multipliers for a class of finite fields we present a new low complexity bit parallel canonical basis multiplier for the field gf 2m generated by an all one polynomial the proposed canonical basis multiplier requires m sup 2 1 xor gates and m sup 2 and gates we also extend this canonical basis multiplier to obtain a new bit parallel normal basis multiplier

modified redundant representation for designing arithmetic circuits with small complexity we give a modified redundant representation for designing arithmetic circuits with small complexity using our modified redundant representation we improve many of the complexity values significantly our method works for any finite field we also give some applications in cryptography

systematic design of original and modified mastrovito multipliers for general irreducible polynomials this paper considers the design of bit parallel dedicated finite field multipliers using standard basis an explicit algorithm is proposed for efficient construction of mastrovito product matrix based on which we present a systematic design of mastrovito multiplier applicable to gf 2 sup m generated by an arbitrary irreducible polynomial this design effectively exploits the spatial correlation of elements in mastrovito product matrix to reduce the complexity using a similar methodology we propose a systematic design of modified mastrovito multiplier which is suitable for gf 2 sup m generated by high hamming weight irreducible polynomials for both original and modified mastrovito multipliers the developed multiplier architectures are highly modular which is desirable for vlsi hardware implementation applying the proposed algorithm and design approach we study the mastrovito multipliers for several special irreducible polynomials such as trinomial and equally spaced polynomial and the obtained complexity results match the best known results moreover we have discovered several new special irreducible polynomials which also lead to low complexity mastrovito multipliers

look up table based large finite field multiplication in memory constrained cryptosystems many cryptographic systems use multiplication in the finite field gf 2 sup n for their underlying computations in the recent past a number of look up table based algorithms have been proposed for the software implementation of gf 2 sup n multiplication look up table based algorithms can provide speed advantages but they either require a large memory space or do not fully utilize the resources of the processor on which the software is executed in this work an algorithm for gf 2 sup n multiplication is proposed which can alleviate this problem in each iteration of the proposed algorithm a group of bits of one of the input operands are examined and two look up tables are accessed the groupsize determines the table sizes but does not affect the utilization of the processor resources it can be used for both software and hardware realizations and is particularly suitable for implementations in memory constrained environment such as smart cards and embedded cryptosystems

p adic 2 1 rational dynamical systems abstract we study the dynamics of an arbitrary 2 1 rational function f x x 2 a x b c x d on the field c p of complex p adic numbers we show that the p adic dynamical system generated by f has a very rich behavior siegel disks may either coincide or be disjoint for different fixed points of the dynamical system also we find the basin of the attractor of the system varying the parameters it is proven that there are periodic trajectories for some values of the parameters there are trajectories which go arbitrary far from fixed points

high speed architectures for multiplication using reordered normal basis normal basis has been widely used for the representation of binary field elements mainly due to its low cost squaring operation optimal normal basis type ii is a special class of normal basis exhibiting very low multiplication complexity and is considered as a safe choice for hardware implementation of cryptographic applications in this paper high speed architectures for binary field multiplication using reordered normal basis are proposed where reordered normal basis is referred to as a certain permutation of optimal normal basis type ii complexity comparison shows that the proposed architectures are faster compared to previously presented architectures in the open literature using either an optimal normal basis type ii or a reordered normal basis one advantage of the new word level architectures is that the critical path delay is a constant not a function of word size this enables the multipliers to operate at very high clock rates regardless of the field size or the number of words hardware implementation of some practical size multipliers for elliptic curve cryptography is also included

an algorithm to design finite field multipliers using a self dual normal basis the concept of using a self dual normal basis to design the massey omura finite field multiplier is presented an algorithm is given to locate a self dual normal basis for gf 2 sup m for odd m a method to construct the product function for designing the massey omura multiplier is developed it is shown that the construction of the product function based on a self dual basis is simpler than that based on an arbitrary normal basis

double basis multiplicative inversion over gf 2 sup m inversion over galois fields is much more difficult than the corresponding multiplication efficient computation of inverses in gf 2 sup m is considered by solving a set of linear equations over the ground field gf 2 the proposed algorithm uses two separate bases for the representation of its input and output elements and has low computational complexity the algorithm is also suitable for hardware implementation using vlsi technologies

a comparison of vlsi architecture of finite field multipliers using dual normal or standard bases three different finite field multipliers are presented 1 a dual basis multiplier due to e r berlekamp 1982 the massey omura normal basis multiplier and 3 the scott tavares peppard standard basis multiplier these algorithms are chosen because each has its own distinct features that apply most suitably in particular areas they are implemented on silicon chips with nmos technology so that the multiplier most desirable for vlsi implementation can readily be ascertained

systolic multipliers for finite fields gf 2 m two systolic architectures are developed for performing the product sum computation ab c in the finite field gf 2m of 2melements where a b and c are arbitrary elements of gf 2m the first multiplier is a serial in serial out one dimensional systolic array while the second multiplier is a parallel in parallel out two dimensional systolic array the first multiplier requires a smaller number of basic cells than the second multiplier the second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively to perform single computations both multipliers require the same computational time in both cases the architectures are simple and regular and possess the properties of concurrency and modularity as a consequence they are well suited for use in vlsi systems

bit serial systolic divider and multiplier for finite fields gf 2 sup m a systolic structure for bit serial division over the field gf 2 sup m is developed consideration is given to avoid global data communications and dependency of the time step duration on m this is important for applications where the value of m is large the divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m sup 2 and m respectively it does not depend on the irreducible polynomial and can be expanded easily moreover with m additional simple processors a bit serial systolic multiplier is developed which uses part of the divider structure this is advantageous from the implementation point of view as both the divider and multiplier can be fabricated on a single chip resulting in a reduction of area

new low complexity bit parallel finite field multipliers using weakly dual bases new structures of bit parallel weakly dual basis wdb multipliers over the binary ground field are proposed an upper bound on the size complexity of bit parallel multiplier using an arbitrary generating polynomial is given when the generating polynomial is an irreducible trinomial x sup m x sup k 1 1 spl les k spl les m 2 the structure of the proposed bit parallel multiplier requires only m sup 2 two input and gates and at most m sup 2 1 xor gates the time delay is no greater than t sub a log sub 2 m 2 t sub x where t sub a and t sub x are the time delays of an and gate and an xor gate respectively

a new algorithm for multiplication in finite fields a new algorithm is presented for computing the product of two elements in a finite field by means of sums and products in a fixed subfield the algorithm is based on a normal basis representation of fields and assumes that the dimension m of the finite field over the subfield is a highly composite number a very fast parallel implementation and a considerable reduction in the number of computations are allowed in comparison to some methods discussed in the literature

design of a linear systolic array for computing modular multiplication and squaring in gf 2m abstract one of the main operations for the public key cryptosystem is the modular exponentiation in this paper we analyze the montgomery s algorithm and design a linear systolic array for performing both modular multiplication and modular squaring simultaneously the proposed systolic array with less hardware complexity can be designed by making use of common multiplicand multiplication in the right to left modular exponentiation over gf 2 m for the fast computation of the modular exponentiation the proposed systolic array has 1 25 times improvement in area time complexity when compared to existing multipliers the proposed systolic array suffers a little loss in time complexity but it has 1 44 times improvement in area complexity since it executes the common parts that exist in the simultaneous computation of both modular multiplication and squaring only once it could be designed on vlsi hardware and used in ic cards

a word level finite field multiplier using normal basis hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost in this paper a new word level finite field multiplier using normal basis is proposed the proposed architecture takes d clock cycles to compute the product bits where the value for d 1 d m can be arbitrarily selected by the designer to set the tradeoff between area and speed when there exists an optimal normal basis it is shown that the proposed design has a smaller critical path delay than other word level normal basis multipliers found in the literature while its circuit complexities are moderate and comparable to the others different word size multipliers were implemented in hardware and implementation results are also presented

a systolic architecture for computing inverses and divisions in finite fields gf 2 sup m a new serial in serial out systolic array is presented for performing the element inversion in gf 2 sup m with the standard basis representation the architecture is highly regular modular nearest neighbor connected and thus well suited to vlsi implementation it has a latency of 7m 3 clock cycles and a throughput rate of one result per 2m 1 clock cycles this speed performance is much better than those of the previous implementations without change in hardware design the proposed inversion array can be directly used for computing the division in gf 2 sup m

generalised mersenne numbers revisited generalised mersenne numbers gmns were defined by solinas in 1999 and feature in the nist fips 186 2 and secg standards for use in elliptic curve cryptography their form is such that modular reduction is extremely efficient thus making them an attractive choice for modular multiplication implementation however the issue of residue multiplication efficiency seems to have been overlooked asymptotically using a cyclic rather than a linear convolution residue multiplication modulo a mersenne number is twice as fast as integer multiplication this property does not hold for prime gmns unless they are of mersenne s form in this work we exploit an alternative generalisation of mersenne numbers for which an analogue of the above property and hence the same efficiency ratio holds even at bitlengths for which schoolbook multiplication is optimal while also maintaining very efficient reduction moreover our proposed primes are abundant at any bitlength whereas gmns are extremely rare our multiplication and reduction algorithms can also be easily parallelised making our arithmetic particularly suitable for hardware implementation furthermore the field representation we propose also naturally protects against side channel attacks including timing attacks simple power analysis and differential power analysis which is essential in many cryptographic scenarios in constrast to gmns

on minimal decomposition of p adic polynomial dynamical systems abstract a polynomial of degree 2 with coefficients in the ring of p adic numbers z p is studied as a dynamical system on z p it is proved that the dynamical behavior of such a system is totally described by its minimal subsystems for an arbitrary quadratic polynomial on z 2 we exhibit all its minimal subsystems

a modified massey omura parallel multiplier for a class of finite fields a massey omura parallel multiplier of finite fields gf 2 sup m contains m identical blocks whose inputs are cyclically shifted versions of one another it is shown that for fields gf 2 sup m generated by irreducible all one polynomials a portion of the block is independent of the input cyclic shift hence the multiplier contains redundancy by removing the redundancy a modified parallel multiplier is presented which is modular and has a lower circuit complexity

systolic array implementation of euclid s algorithm for inversion and division in gf 2 sup m this paper presents two new systolic arrays to realize euclid s algorithm for computing inverses and divisions in finite fields gf 2 sup m with the standard basis representation one of these two schemes is parallel in parallel out and the other is serial in serial out the former employs o m sup 2 area complexity to provide the maximum throughput in the sense of producing one result every clock cycle while the latter achieves a throughput of one result per m clock cycles using o m log m area complexity both of the proposed architectures are highly regular and thus well suited to vlsi implementation as compared to existing related systolic architectures with the same throughput performance the proposed parallel in parallel out scheme reduces the hardware complexity and thus the area time product by a factor of o m and the proposed serial in serial out scheme by a factor of o m log sub 2 m

montgomery multiplier and squarer for a class of finite fields montgomery multiplication in gf 2 sup m is defined by a x b x r sup 1 x mod f x where the field is generated by a root of the irreducible polynomial f x a x and b x are two field elements in gf 2 sup m and r x is a fixed field element in gf 2 sup m in this paper first a slightly generalized montgomery multiplication algorithm in gf 2 sup m is presented then by choosing r x according to f x we show that efficient architectures of bit parallel montgomery multiplier and squarer can be obtained for the fields generated with an irreducible trinomial complexities of the montgomery multiplier and squarer in terms of gate counts and time delay of the circuits are investigated and found to be as good as or better than that of previous proposals for the same class of fields

a new hardware architecture for operations in gf 2 sup n the efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented the common field representations are a polynomial basis representation and a normal basis representation in this paper we introduce a nonconventional basis and present a new bit parallel multiplier which is as efficient as the modified massey omura multiplier using the type i optimal normal basis

efficient algorithms and architectures for field multiplication using gaussian normal bases recently implementations of normal basis multiplication over the extended binary field gf 2 sup m have received considerable attention a class of low complexity normal bases called gaussian normal bases has been included in a number of standards such as ieee and nist for an elliptic curve digital signature algorithm the multiplication algorithms presented there are slow in software since they rely on bit wise inner product operations in this paper we present two vector level software algorithms which essentially eliminate such bit wise operations for gaussian normal bases our analysis and timing results show that the software implementation of the proposed algorithm is faster than previously reported normal basis multiplication algorithms the proposed algorithm is also more memory efficient compared with its look up table based counterpart moreover two new digit level multiplier architectures are proposed and it is shown that they outperform the existing normal basis multiplier structures as compared with similar digit level normal basis multipliers the proposed multiplier with serial output requires the fewest number of xor gates and the one with parallel output is the fastest multiplier

concurrent error detection and correction in gaussian normal basis multiplier over gf 2 m fault based cryptanalysis has been developed to effectively break both private key and public key cryptosystems making robust finite field multiplication a very important research topic in recent years however no robust normal basis multiplier has been proposed in the literature therefore this investigation presents a semisystolic gaussian normal basis multiplier based on the proposed gaussian normal basis multiplier both concurrent error detection and correction capabilities can be easily achieved using time redundancy technology with no hardware modification

gf 2 sup m multiplication and division over the dual basis in this paper an algorithm for gf 2 sup m multiplication division is presented and a new more generalized definition of duality is proposed from these the bit serial berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers furthermore it is shown that hardware efficient bit parallel dual basis multipliers can also be designed these multipliers have a regular structure are easily extended to different gf 2 sup m and hence suitable for vlsi implementations as in the bit serial case these bit parallel multipliers can also be hardwired to carry out constant multiplication these constant multipliers have reduced hardware requirements and are also simple to design in addition the multiplication division algorithm also allows a bit serial systolic finite field divider to be designed this divider is modular independent of the defining irreducible polynomial for the field easily expanded to different gf 2 sup m and its longest delay path is independent of m

p adic models of ultrametric diffusion constrained by hierarchical energy landscapes we demonstrate that the p adic analysis is a natural basis for the construction of a wide variety of models of ultrametric diffusion constrained by hierarchical energy landscapes a general analytical description in terms of the p adic analysis is given for a class of models two exactly solvable examples i e the ultrametric diffusion constrained by the linear energy landscape and the ultrametric diffusion with a reaction sink are considered we show that such models can be applied to both the relaxation in complex systems and the rate processes coupled to rearrangement of the complex surrounding

a new architecture for a parallel finite field multiplier with low complexity based on composite fields a bit parallel structure for a multiplier with low complexity in galois fields is introduced the multiplier operates over composite fields gf 2 sup n sup m with k nm the karatsuba ofman algorithm a karatsuba and y ofmanis 1963 is investigated and applied to the multiplication of polynomials over gf 2 sup n it is shown that this operation has a complexity of order o k sup log23 under certain constraints regarding k a complete set of primitive field polynomials for composite fields is provided which perform module reduction with low complexity as a result multipliers for fields gf 2 sup k up to k 32 with low gate counts and low delays are listed the architectures are highly modular and thus well suited for vlsi implementation

low complexity word level sequential normal basis multipliers for efficient hardware implementation of finite field arithmetic units the use of a normal basis is advantageous in this paper two classes of architectures for multipliers over the finite field gf 2 sup m are proposed these multipliers are of sequential type i e after receiving the coordinates of the two input field elements they go through k 1 spl les k spl les m iterations i e clock cycles to finally yield all the coordinates of the product in parallel the value of k depends on the word size w spl lceil m k spl rceil for w 1 these multipliers are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multipliers available in the open literature this makes the proposed multipliers suitable for applications where the value of m is large but space is of concern e g resource constrained cryptographic systems additionally if the field dimension m is composite i e m kn then the extension of one class of the architectures yields a highly efficient multiplier over composite fields

structure of parallel multipliers for a class of fields gf 2 m abstract this paper presents a configuration of parallel multipliers for gf 2 m based on canonical bases the possible parallel multipliers by the proposed configuration are limited to a class of fields gf 2 m however they can be constructed by o m 2 and gates and o m 2 eor gates with the structural modularity this is a desirable feature for the hardware implementation and their operation time is about log m t where m is the dimension of gf 2 m and t is the delay time of an eor gate in order to construct such parallel multipliers we define two types of polynomials of special form over gf 2 one is called all one polynomial denoted by aop and the other is called equally spaced polynomial denoted by esp furthermore we show a necessary and sufficient condition for esps to be irreducible over gf 2 and the uniqueness of the irreducible esps over gf 2 finally we propose the configuration of parallel multipliers for a class of fields gf 2 m based on irreducible aops and esps over gf 2

low complexity bit parallel multiplier for gf 2 sup m defined by all one polynomials using redundant representation this paper presents a new bit parallel multiplier for the finite field gf 2 sup m defined by an irreducible all one polynomial in order to reduce the complexity of the multiplier we introduce a redundant representation and use the well known multiplication method proposed by karatsuba the main idea is to combine the redundant representation and the karatsuba method to design an efficient bit parallel multiplier as a result the proposed multiplier requires about 25 percent fewer and xor gates than the previously proposed multipliers using an all one polynomial while it has almost the same time delay as the previously proposed ones

low complexity bit parallel multipliers for a class of finite fields new implementations of bit parallel multipliers for a class of finite fields are proposed the class of finite fields is constructed with irreducible aops all one polynomials and esps equally spaced polynomials the size and time complexities of our proposed multipliers are lower than or equal to those of the previously proposed multipliers of the same class

wg a family of stream ciphers with designed randomness properties in this paper we present a family of stream ciphers which generate a keystream with ideal two level autocorrelation the design also guarantees other randomness properties i e balance long period ideal tuple distribution and high and exact linear complexity we discuss how these properties are achieved by the proposed design and show how to select various parameters to obtain an efficient stream cipher for the desired security level we also show that the proposed generators are secure against time memory data tradeoff attacks algebraic attacks and correlation attacks finally we present wg 128 as a concrete example of a wg stream cipher with a key size of 128bits

architectures for exponentiation over gd 2 sup n adopted for smartcard application two exponentiation circuits are proposed using the fact that squaring is a linear operation over gf 2 sup n a time space tradeoff in smartcard based circuitry is presented it is shown how multiplication is performed by a single shift based on replacing the public key alpha sup a in gf 2 sup n by its minimal polynomial other considerations related to structure regularity and the possible use of dynamic shift registers are also treated

bit parallel finite field multipliers for irreducible trinomials a new formulation for the canonical basis multiplication in the finite fields gf 2 sup m based on the use of a triangular basis and on the decomposition of a product matrix is presented from this algorithm a new method for multiplication named transpositional applicable to general irreducible polynomials is deduced the transpositional method is based on the computation of 1 cycles and 2 cycles given by a permutation defined by the coordinate of the product to be computed and by the cardinality of the field gf 2 sup m the obtained cycles define groups corresponding to subexpressions that can be shared among the different product coordinates this new multiplication method is applied to five types of irreducible trinomials these polynomials have been widely studied due to their low complexity implementations the theoretical complexity analysis of the corresponding bit parallel multipliers shows that the space complexities of our multipliers match the best results known to date for similar canonical gf 2 sup m multipliers the most important new result is the reduction in two of the five studied trinomials of the time complexity with respect to the best known results

vlsi architectures for computing multiplications and inverses in gf 2 m finite field arithmetic logic is central in the implementation of reed solomon coders and in some cryptographic algorithms there is a need for good multiplication and inversion algorithms that can be easily realized on vlsi chips massey and omura 1 recently developed a new multiplication algorithm for galois fields based on a normal basis representation in this paper a pipeline structure is developed to realize the massey omura multiplier in the finite field gf 2m with the simple squaring property of the normal basis representation used together with this multiplier a pipeline architecture is also developed for computing inverse elements in gf 2m the designs developed for the massey omura multiplier and the computation of inverse elements are regular simple expandable and therefore naturally suitable for vlsi implementation

fault tolerant decoders for cyclic error correcting codes high speed cyclic code decoders which are central to modern communication systems when implemented in dense very large scale integration vlsi are susceptible to pernicious momentary internal soft fails presenting a demanding error control challenge however special structures inherent in such decoders offer new methods for incorporating distributed error control throughout their designs the underlying design principles and motivations are emphasized providing a variety of options to meet various requirements bose chaudhuri hocquenghem bch codes are used to exemplify the new techniques as applied to the usual three standard subsystems present in a decoder the first and last parts syndrome calculations and transform inversion both involve finite field transforms suggesting the effective application of fast transform algorithms error control features are based upon the chord properties of the transform coefficients including even fast algorithms the third subsystem the berlekamp massey algorithm can be protected through a chord recursion property affiliated with the error location connection polynomial the propagation and spread of internal errors are studied and a special sink register compares several quantities available in close proximity to their easily recomputed counterparts most of these results are applicable to generalized to decoders for codes over higher ordered alphabets such as reed solomon codes

a new finite field multiplier using redundant representation this article presents simple and highly regular architectures for finite field multipliers using a redundant representation the basic idea is to embed a finite field into a cyclotomic ring which is based on the elegant multiplicative structure of a cyclic group one important feature of our architectures is that they provide area time trade offs which enable us to implement the multipliers in a partial parallel hybrid fashion this hybrid architecture has great significance in its vlsi implementation in very large fields the squaring operation using the redundant representation is simply a permutation of the coordinates it is shown that when there is an optimal normal basis the proposed bit serial and hybrid multiplier architectures have very low space complexity constant multiplication is also considered and is shown to have an advantage in using the redundant representation

comb architectures for finite field multiplication in f 2 m two high speed bit serial word parallel or comb style finite field multipliers are proposed in this paper the first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type ii optimal normal basis exists the proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same the proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis field programmable gate array fpga implementation results of the proposed multipliers are compared to those of the previous methods using the same basis which confirms that the proposed multipliers allow a much higher clock rate

a vlsi design for computing exponentiations in gf 2 sup m and its application to generate pseudorandom number sequences a vlsi design for computing exponentiation in finite fields is developed an algorithm to generate a relatively long pseudorandom number sequence is presented it is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme

on computing multiplicative inverses in gf 2 sup m the design of a modular standard basis inversion for galois fields gf 2 sup m based on euclid s algorithm for computing the greatest common divisor of two polynomials is presented the asymptotic complexity is linear with m both in computation time and area requirement thus resulting in an at complexity of o m sup 2 this is a significant improvement over the best previous proposal which achieves at complexity of only o m sup 3

fast inversion in schmi gf 2 m with normal basis using hybrid double multipliers fast inversion in finite fields is crucial for high performance cryptography and codes we present techniques to exploit the recently proposed hybrid double multipliers for fast inversions in binary fields gf 2m with normal bases a hybrid double multiplier computes a double multiplication the product of three elements in gf 2m with a latency comparable to the latency of single multiplication of two elements traditional approaches such as itoh tsujii cannot utilize hybrid double multipliers we devise a new inversion algorithm based on ternary representations that exploits their potential the algorithm reduces the latency of inversion significantly for the fields recommended by nist if hybrid double multipliers are employed for example the algorithm computes an inversion in gf 2163 with only five double multiplications whereas the itoh tsujii algorithm requires nine single or double multiplications we propose a new inverter architecture using this new algorithm and a hybrid double multiplier we show that it is faster than the existing techniques by providing asic synthesis results using 65 nm cmos technology for example our inverter for gf 2163 achieves about 34 percent shorter computation time than an inverter using the itoh tsujii algorithm and a single multiplier

efficient multiplier architectures for galois fields gf 2 sup 4n this contribution introduces a new class of multipliers for finite fields gf 2 sup n sup 4 the architecture is based on a modified version of the karatsuba ofman algorithm koa by determining optimized field polynomials of degree four the last stage of the koa and the module reduction can be combined this saves computation and area in vlsi implementations the new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with koa based architectures with separate module reduction the new multipliers lead to highly modular architectures and are thus well suited for vlsi implementations three types of field polynomials are introduced and conditions for their existence are established for the small fields where n 2 3 8 which are of primary technical interest optimized field polynomials were determined by an exhaustive search for each field order exact space and time complexities are provided

new systolic arrays for c ab sup 2 inversion and division in gf 2 sup m in this paper we present a new parallel in parallel out systolic array with unidirectional data flow for performing the power sum operation c ab sup 2 in finite fields gf 2 sup m the architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle it is highly regular modular and thus well suited to vlsi implementation as compared to a previous systolic power sum circuit with bidirectional data flow and the same throughput performance the proposed one has smaller latency consumes less chip area and can more easily incorporate fault tolerant design based on the new power sum circuit we also propose a parallel in parallel out systolic array with the maximum throughput for computing inverses divisions in gf 2 sup m the proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area latency and fault tolerance

a fast algorithm for computing multiplicative inverses in gf 2 m using normal bases abstract this paper proposes a fast algorithm for computing multiplicative inverses in gf 2 m using normal bases normal bases have the following useful property in the case that an element x in gf 2 m is represented by normal bases 2 k power operation of an element x in gf 2 m can be carried out by k times cyclic shift of its vector representation c c wang et al proposed an algorithm for computing multiplicative inverses using normal bases which requires m 2 multiplications in gf 2 m and m 1 cyclic shifts the fast algorithm proposed in this paper also uses normal bases and computes multiplicative inverses iterating multiplications in gf 2 m it requires at most 2 log 2 m 1 multiplications in gf 2 m and m 1 cyclic shifts which are much less than those required in the wang s method the same idea of the proposed fast algorithm is applicable to the general power operation in gf 2 m and the computation of multiplicative inverses in gf q m q 2 n

a new construction of massey omura parallel multiplier over gf 2 sup m the massey omura multiplier of gf 2 sup m uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another in the past it was shown that for a class of finite fields defined by irreducible all one polynomials the parallel massey omura multiplier had redundancy and a modified architecture of lower circuit complexity was proposed in this article it is shown that not only does this type of multiplier contain redundancy in that special class of finite fields but it also has redundancy in fields gf 2 sup m defined by any irreducible polynomial by removing the redundancy we propose a new architecture for the normal basis parallel multiplier which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original massey omura normal basis parallel multiplier the proposed multiplier structure is also modular and hence suitable for vlsi realization when applied to fields defined by the irreducible all one polynomials the multiplier s circuit complexity matches the best result available in the open literature

hardware and software normal basis arithmetic for pairing based cryptography in characteristic three although identity based cryptography offers a number of functional advantages over conventional public key methods the computational costs are significantly greater the dominant part of this cost is the tate pairing which in characteristic three is best computed using the algorithm of duursma and lee however in hardware and constrained environments this algorithm is unattractive since it requires online computation of cube roots or enough storage space to precompute required results we examine the use of normal basis arithmetic in characteristic three in an attempt to get the best of both worlds an efficient method for computing the tate pairing that requires no precomputation and that may also be implemented in hardware to accelerate devices such as smart cards

a generalization of addition chains and fast inversions in binary fields in this paper we study a generalization of addition chains where k previous values are summed together on each step instead of only two values as in traditional addition chains such chains are called k chains and we show that they have applications in finding efficient parallelizations in problems that are known to be difficult to parallelize in particular 3 chains improve computations of inversions in finite fields using hybrid double multipliers recently it was shown that this operation can be efficiently computed using a ternary algorithm but we show that 3 chains provide a significantly more efficient solution

on embedding certain partial orders into the p points under rudin keisler and tukey reducibility the study of the global structure of ultrafilters on the natural numbers with respect to the quasi orders of rudin keisler and rudin blass reducibility was initiated in the 1970s by blass keisler kunen and rudin in a 1973 paper blass studied the special class of p points under the quasiordering of rudin keisler reducibility he asked what partially ordered sets can be embedded into the p points when the p points are equipped with this ordering this question is of most interest under some hypothesis that guarantees the existence of many p points such as martin s axiom for centered posets in his 1973 paper he showed under this assumption that both 1 and the reals can be embedded analogous results were obtained later for the coarser notion of tukey reducibility we prove in this paper that martin s axiom for centered posets implies that the boolean algebra p fin equipped with its natural partial order can be embedded into the p points both under rudin keisler and tukey reducibility consequently the continuum hypothesis implies that every partial order of size at most continuum embeds into the p points under both notions of reducibility

aop arithmetic architectures over gf 2m this paper presents bit serial arithmetic architectures for gf 2 m based on an irreducible all one polynomial first modular multiplier and a squarer are designed with significantly less hardware complexity than previous architectures then two arithmetic architectures are proposed based on the modular multiplier and squarer they can be used as kernel architecture for modular exponentiations which is very important operation in the most of public key cryptosystem since the multipliers have low hardware requirements and regular structures they are suitable for vlsi implementation

new architectures for digit level single hybrid double hybrid triple field multiplications and exponentiation using gaussian normal bases gaussian normal bases gnbs are special set of normal bases nbs which yield low complexity gf left 2 m right arithmetic operations in this paper we present new architectures for the digit level single hybrid double and hybrid triple multiplication of gf left 2 m right elements based on the gnb representation for odd values of m 1 the proposed fully serial in single multipliers perform multiplication of two field elements and offer high throughput when the data path capacity for entering inputs is limited the proposed hybrid double and hybrid triple digit level gnb multipliers perform respectively two and three field multiplications using the same latency required for a single digit level multiplier at the expense of increased area in addition we present a new eight ary field exponentiation architecture which does not require precomputed or stored intermediate values

modular construction of low complexity parallel multipliers for a class of finite fields gf 2 sup m structures for parallel multipliers of a class of fields gf 2 sup m based on irreducible all one polynomials aop and equally spaced polynomials esp are presented the structures are simple and modular which is important for hardware realization relationships between an irreducible aop and the corresponding irreducible esps have been exploited to construct esp based multipliers of large fields by a regular expansion of the basic modules of the aop based multiplier of a small field some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible it is shown that if for a certain degree an irreducible aop as well as an irreducible esp exist then from the complexity point of view it is advantageous to use the esp based parallel multiplier

equivalence of families of functions on the natural numbers we present some consequences of the inequality u g among cardinal invariants of the continuum which has previously been shown to be consistent relative to zfc we are interested in its effects on two orderings of families of functions on the natural numbers in particular we show that under u g there are exactly five equivalence classes for both orderings excludint the families bounded by a fixed constant function this implies under the same hypothesis the existence of exactly four classes of rarefaction of measure zero sets

provably sublinear point multiplication on koblitz curves and its hardware implementation we describe algorithms for point multiplication on koblitz curves using multiple base expansions of the form k sigmaplusmntaua tau 1 b and k sigmaplusmntaua tau mu b tau2 mutau 1 c we prove that the number of terms in the second type is sublinear in the bit length of k which leads to the first provably sublinear point multiplication algorithm on koblitz curves for the first type we conjecture that the number of terms is sublinear and provide numerical evidence demonstrating that the number of terms is significantly less than that of tau adic nonadjacent form expansions we present details of an innovative fpga implementation of our algorithm and performance data demonstrating the efficiency of our method we also show that implementations with very low computation latency are possible with the proposed method because parallel processing can be exploited efficiently

a fast algorithm for multiplicative inversion in gf 2 sup m using normal basis a fast algorithm for multiplicative inversion in gf 2 sup m using normal basis is proposed it is an improvement on those proposed by itoh and tsujii and by chang et al which are based on fermat s theorem and require o logm multiplications the number of multiplications is reduced by decomposing m 1 into several factors and a small remainder

on minimal decomposition of p adic homographic dynamical systems abstract a homographic map in the field of p adic numbers q p is studied as a dynamical system on p 1 q p the projective line over q p if such a system admits one or two fixed points in q p then it is conjugate to an affine dynamics whose dynamical structure has been investigated by fan and fares in this paper we shall mainly solve the remaining case that the system admits no fixed point we shall prove that this system can be decomposed into a finite number of minimal subsystems which are topologically conjugate to each other all the minimal subsystems are exhibited and the unique invariant measure for each minimal subsystem is determined

perfect set properties inl r u abstract we study perfect set properties in the modell r u whenl r is elementarily equivalent to a solovay model anduis a selective ultrafilter on the integers generic overl r

near coherence of filters ii applications to operator ideals the stone cech remainder of a half line order ideals of sequences and slenderness of groups the set theoretic principle of near coherence of filters ncf is lnown to be neither provable nor refutable from the usual axioms of set theory we show that ncf is equivalent to the following statements among others 1 the ideal of compact operators on hilbert space is not the sum of two smaller ideals 2 the stone tech remainder of a half line has only one composant this was first proved by j mioduszewski 3 the partial ordering of slenderness classes of abelian groups minus its top element is directed upward and in fact has a top element thus 11 these statements are also consistent and independent