simulating the dynamics of inextensible vesicles by the penalty immersed boundary method in this paper we develop an immersed boundary ib method to simulate the dynamics of inextensible vesicles interacting with an incompressible fluid in order to take into account the inextensibility constraint of the vesicle the penalty immersed boundary pib method is used to virtually decouple the fluid and vesicle dynamics as numerical tests of our current pib method the dynamics of single and multiple inextensible vesicles under shear flows have been extensively explored and compared with the previous literature the method is also validated by a series of convergence study which confirms its consistent first order accuracy on the velocity field the vesicle configuration the vesicle area and the perimeter errors in addition the method is also applied to study a binary component vesicle problem

an effective built in self test scheme for parallel multipliers an effective built in self test bist scheme for parallel multipliers array and tree is proposed the new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks no modifications to the multiplier structure are required a guaranteed very high fault coverage of a comprehensive cellular fault model is achieved the results do not depend either on the gate level implementation of the multiplier cells or the architecture of the multiplier whether it is a carry propagate or carry save array multiplier or a tree multiplier or on the multiplier size a small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture the regularity of the test vectors allows for their on chip generation with a very small hardware overhead which is equivalent to the hardware overhead of pseudorandom testing

new runge jutta nystrom formula pairs of order 8 7 9 8 10 9 and 11 10 for differential equations of the form y f x y abstract for initial value problems in ordinary second order differential equations of the special form y f x y mew explicit direct runge kutta nystrom formula pairs of order 8 7 9 8 10 9 and 11 10 are presented using the mode of bettis dormand and prince two numerical examples demonstrate the efficiency of the new formula pairs

a partial carry save on the fly correction multispeculative multiplier functional units that are designed to receive inputs and produce outputs using a non redundant format typically exhibit an inferior performance in order to overcome this limitation the carry save and partial carry save formats have been proposed both approaches are very suitable when implementing addition trees nevertheless if there are multiplications in the datapath the inputs to the multiplier must be reduced to a non redundant form to avoid applying the distributive property in this paper we present a multiplier able to receive two numbers in partial carry save format and produce a result in partial carry save format as well this is done by modifying the booth encoder and leveraging the generate and propagate group signals that are available because of the partial carry save format hence this can allow to fully implement datapaths without additional penalty cycles due to reductions to non redundant forms experiments show that our proposed multiplier has 15 percent shorter delay with respect to a conventional booth radix 4 multiplier moreover when combining it with partial carry save adders it is possible to reduce 36 percent execution time on average for several benchmarks achieving a 32 7 percent reduction in the energy delay product at the same time

the complexity of fault detection problems for combinational logic circuits in this correspondence we analyze the computational complexity of fault detection problems for combinational circuits and propose an approach to design for testability although major fault detection problems have been known to be in general np complete they were proven for rather complex circuits in this correspondence we show that these are still np complete even for monotone circuits and thus for unate circuits we show that for k level k 3 monotone unate circuits these problems are still np complete but that these are solvable in polynomial time for 2 level monotone unate circuits a class of circuits for which these fault detection problems are solvable in polynomial time is presented ripple carry adders decoder circuits linear circuits etc belong to this class a design approach is also presented in which an arbitrary given circuit is changed to such an easily testable circuit by inserting a few additional test points

note on the performance of direct and indirect runge kutta nystro m methods abstract this paper deals with predictor corrector iteration of runge kutta nystrom rkn methods for integrating initial value problems for special second order ordinary differential equations we consider rkn correctors based on both direct and indirect collocation techniques the paper focuses on the convergence factors and stability regions of the iterated rkn correctors it turns out that the methods based on direct collocation rkn correctors possess smaller convergence factors than those based on indirect collocation rkn correctors both families of methods have sufficiently large stability boundaries for nonstiff problems

carry save multiplication schemes without final addition carry save multipliers require an adder at the last step to convert the carry sum representation of the most significant half of the result into a non redundant form this paper presents n spl times n multiplication schemes where this conversion is performed with a circuit operating in parallel with the carry save array the most relevant feature of the proposed multipliers is that the full 2n bit result is produced unlike similar multiplication schemes presented in the literature

precision aware self quantizing hardware architectures for the discrete wavelet transform this paper presents designs for both bit parallel bp and digit serial ds precision optimized implementations of the discrete wavelet transform dwt with specific consideration given to the impact of depth the number of levels of dwt on the overall computational accuracy these methods thus allow customizing the precision of a multilevel dwt to a given error tolerance requirement and ensuring an energy minimal implementation which increases the applicability of dwt based algorithms such as jpeg 2000 to energy constrained platforms and environments additionally quantization of dwt coefficients to a specific target step size is performed as an inherent part of the dwt computation thereby eliminating the need to have a separate downstream quantization step in applications such as jpeg 2000 experimental measurements of design performance in terms of area speed and power for 90 nm complementary metal oxide semiconductor implementation are presented results indicate that while bp designs exhibit inherent speed advantages ds designs require significantly fewer hardware resources with increasing precision and dwt level a four level dwt with medium precision for example while the bp design is four times faster than the digital serial design occupies twice the area in addition to the bp and ds designs a novel flexible dwt processor is presented which supports run time configurable dwt parameters

algorithm and architecture for logarithm exponential and powering computation an architecture for the computation of logarithm exponential and powering operations is presented in this paper based on a high radix composite algorithm for the computation of the powering function x sup y the algorithm consists of a sequence of overlapped operations 1 digit recurrence logarithm 2 left to right carry free lrcf multiplication and 3 online exponential a redundant number system is used and the selection in 1 and 3 is done by rounding except from the first iteration when selection by table look up is necessary to guarantee the convergence of the recurrences a sequential implementation of the algorithm with a control unit which allows the independent computation of logarithm and exponential is proposed and the execution times and hardware requirements are estimated for single and double precision floating point computations these estimates are obtained for radices from r 8 to r 1 024 according to an approximate model for the delay and area of the main logic blocks and help determining the radix values which lead to the most efficient implementations r 32 and r 128

dynamics of a closed rod with twist and bend in fluid we investigate the instability and subsequent dynamics of a closed rod with twist and bend in a viscous incompressible fluid a new version of the immersed boundary ib method is used in which the immersed boundary applies torque as well as force to the surrounding fluid and in which the equations of motion of the immersed boundary involve the local angular velocity as well as the local linear velocity of the fluid an important feature of the ib method in this context is that self crossing of the rod is automatically avoided because the rod moves in a continuous interpolated velocity field a rod with a uniformly distributed twist that has been slightly perturbed away from its circular equilibrium configuration is used as an initial condition with the fluid initially at rest if the twist in the rod is sufficiently small the rod simply returns to its circular equilibrium configuration but for larger twists that equilibrium configuration becomes unstable and the rod undergoes large excursions before relaxing to a stable coiled configuration

over redundant digit sets and the design of digit by digit division units over redundant digit sets are defined as those ranging from spl minus s to s with s spl ges b b being the radix this paper presents new techniques for the direct computation of division that use an over redundant digit set for representing the quotient instead of simply redundant ones used previously in particular general criteria for synthesizing the digit selection rules and remainder updating are given for any radix and index of redundancy a methodology combining the use of over redundant digit sets with the prescaling of the divisor is also studied in order to achieve radix b division units with trivial digit selection functions it is also shown for the specific case of radix 4 that using a prescaling slightly wider than in a radix 4 unit by m d ercegovac and t lang 1990 possible to avoid the digit selection table the paper also presents a modified algorithm for on the fly conversion of the result into the irredundant form the proposed methodology can be considered as an alternative to existing division techniques

computations over finite monoids and their test complexity abstract we consider the test pattern generation problem for circuits which compute expressions over some algebraic structure the relation between algebraic properties of this structure and test complexity i e the best possible test size is analyzed here this relation is looked at in detail for the family of all finite monoids the test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit in a certain computational model solving the problem two important computations over finite monoids namely expression evaluation and parallel prefix computation are considered the relation between algebraic properties of a monoid and its test complexity with respect to these problems is studied in both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant logarithmic and linear test complexity respectively these classes are characterized using algebraic properties for example groups are exactly the monoids with constant test complexity for each class we provide circuits with optimal test sets and efficient methods which decide the membership problem for a given finite monoid m i e determine the test complexity for m

explicit symmetric runge kutta nystrom methods for parallel computers abstract in this paper we are concerned with parallel predictor corrector pc iteration of runge kutta nystrom rkn methods in p ec m e mode for integrating initial value problems for the special second order equation y t f y t we consider symmetric runge kutta nystrom srkn corrector methods based on direct collocation techniques which optimize the rate of convergence of the pc iteration process the resulting pisrkn methods parallel iterated srkn methods are shown to be much more efficient when they are compared to the pc iteration process applied to the gauss legendre rkn correctors

a wave dynamics criterion for optimization of mammalian cardiovascular system the cardiovascular system in mammals follows various optimization criteria covering the heart the vascular network and the coupling of the two through a simple dimensional analysis we arrived at a non dimensional number wave condition number that can predict the optimum wave state in which the left ventricular lv pulsatile power lv workload is minimized in a mammalian cardiovascular system this number is also universal among all mammals independent of animal size maintaining a value of around 0 1 by utilizing a unique in vitro model of human aorta we tested our hypothesis against a wide range of aortic compliance pulse wave velocity we concluded that the optimum value of the wave condition number remains to be around 0 1 for a wide range of aorta compliance that we could simulate in our in vitro system

on the fly rounding computing arithmetic in implementations of operations based on digit recurrence algorithms such as division left to right multiplication and square root the result is obtained in digit serial form from most significant digit to least significant to reduce the complexity of the result digit selection and allow the use of redundant addition the result digit has values from a signed digit set as a consequence the result has to be converted to conventional representation which can be done on the fly as the digits are produced without the use of a carry propagate adder the authors describe three ways to modify this conversion process so that the result is rounded the resulting operation is fast because no carry propagate addition is needed the schemes described apply also to online arithmetic operations

fast multiplication without carry propagate addition conventional schemes for fast multiplication accumulate the partial products in redundant form carry save or signed digit and convert the result to conventional representation in the last step this step requires a carry propagate adder which is comparatively slow and occupies a significant area of the chip in a vlsi implementation a report is presented on a multiplication scheme left to right carry free lrcf that does not require this carry propagate step the lrcf scheme performs the multiplication most significant bit first and produces a conventional sign and magnitude product most significant n bits by means of an on the fly conversion the resulting implementation is fast and regular and is very well suited for vlsi the lrcf scheme for general radix r and a radix 4 signed digit implementation are presented

a general class of explicit pseudo two step rkn methods on parallel computers abstract the aim of this paper is to investigate a general class of explicit pseudo two step runge kutta nystrom methods rkn methods of arbitrarily high order for nonstiff problems for systems of special second order differential equations y t f y t order and stability considerations show that we can obtain for any given p a stable p th order explicit pseudo two step rkn method requiring p 2 right hand side evaluations per step of which each evaluation can be obtained in parallel consequently on a multiprocessor computer only one sequential right hand side evaluation per step is required by a few widely used test problems we show the superiority of the methods considered in this paper over both sequential and parallel methods available in the literature

design of testable structures defined by simple loops a methodology is given for generating combinational structures from high level descriptions using assignment statements if statements and single nested loops of register transfer rt level operators the generated structures are cellular and are interconnected in a tree structure a general algorithm is given to test cellular tree structures with a test length which grows only linearly with the size of the tree it is proved that this test length is optimal to within a constant factor ways of making the structures self checking are also indicated

testing in two dimensional iterative logic arrays abstract the test methods of two dimensional 2 d iterative logic arrays ilas composed of combinational cells are considered an ila which can be tested by a test whose size is a constant independent of the number of cells in the ila is referred to as a c testable ila an ila which can be tested in a number of vectors linear to the number of cells is referred to as a linear testable ila the fault model assumed is that faults in a cell can change a cell behavior in any arbitrary way as long as the cell remains a combinational circuit at the array level two fault models are considered in the single cell fault model scfm only one cell can be faulty and in the multiple cell fault model mcfm any number of cells can be faulty previous papers have shown the testing methods of c testable and linear testable one dimensional ilas under scfm and mcfm in this paper we extend those methods and use the concept of divide and conquer to generate test sets for 2 d ilas under scfm and mcfm the sufficient conditions and test complexities are derived futhermore some practical circuits are used for example

pulse wave propagation in a model human arterial network assessment of 1 d visco elastic simulations against in vitro measurements a numerical model based on the nonlinear one dimensional 1 d equations of pressure and flow wave propagation in conduit arteries is tested against a well defined experimental 1 1 replica of the human arterial tree the tree consists of 37 silicone branches representing the largest central systemic arteries in the human including the aorta carotid arteries and arteries that perfuse the upper and lower limbs and the main abdominal organs the set up is mounted horizontally and connected to a pulsatile pump delivering a periodic output similar to the aortic flow terminal branches end in simple resistance models consisting of stiff capillary tubes leading to an overflow reservoir that reflects a constant venous pressure the parameters required by the numerical algorithm are directly measured in the in vitro set up and no data fitting is involved comparison of experimental and numerical pressure and flow waveforms shows the ability of the 1 d time domain formulation to capture the main features of pulse wave propagation measured throughout the system test as a consequence of the simple resistive boundary conditions used to reduce the uncertainty of the parameters involved in the simulation the experimental set up generates waveforms at terminal branches with additional non physiological oscillations the frequencies of these oscillations are well captured by the 1 d model even though amplitudes are overestimated adding energy losses in bifurcations and including fluid inertia and compliance to the purely resistive terminal models does not reduce the underdamped effect suggesting that wall visco elasticity might play an important role in the experimental results nevertheless average relative root mean square errors between simulations and experimental waveforms are smaller than 4 for pressure and 19 for the flow at all 70 locations studied

two dimensional simulations of valveless pumping using the immersed boundary method flow driven by pumping without valves is examined motivated by biomedical applications cardiopulmonary resuscitation cpr and the human fetus before the development of the heart valves the direction of flow inside a loop of tubing which consists of almost rigid and flexible parts is investigated when the boundary of one end of the flexible segment is forced periodically in time despite the absence of valves net flow around the loop may appear in these simulations the magnitude and even the direction of this flow depend on the driving frequency of the periodic forcing

a minimum test set for multiple fault detection in ripple carry adders previous papers have shown that a ripple carry adder composed of several full adder cells can be completely tested by a minimum test set of size 8 independent of the number of cells in the ripple carry adder under single faulty cell assumption the fault model assumed is that faults in a cell can change the cell behavior in any arbitrary way as long as the cell remains a combinational circuit in this paper we assume that any number of cells can be faulty at any time a minimum test set of size 11 which can detect arbitrary length ripple carry adders under this fault model is presented for general n p adders in which each cell is a p bit adder a minimum test set of size 3 22p 1 is also presented

easily testable iterative logic arrays iterative logic arrays ilas are studied with respect to two testing problems first a variety of conditions is presented meeting these conditions guarantees an upper bound on the size of the test set for the ila under consideration second techniques for designing optimally testable ilas are presented the arrays treated are in some cases more general than those that have been reported by other researchers they include multidimensional and inhomogeneous arrays octagonally connected arrays and bilateral arrays are also discussed the results indicate that the characteristics of the individual cell functions e g whether they are bijective are a good guide to the test complexity of the overall array matrix multiplication as an example is shown to have several different optimally testable implementations the results are useful for combinational and pipelined arrays and for certain systolic arrays

testability of convergent tree circuits the testing properties of a class of regular circuits called convergent trees are investigated convergent trees include such practical circuits as comparators multiplexers and carry lookahead adders the conditions for the testability of these tree circuits are derived for a functional fault model the notion of l testability is introduced where the number of tests for a p level tree is directly proportional to p rather than exponential in p convergent trees that are c testable testable with a fixed number of tests regardless of the tree s size are also characterized two design techniques are also introduced that modify arbitrary tree modules in order to achieve land c testability finally we apply these techniques to the design of a large carry lookahead adder

explicit parallel two step runge kutta nystrom methods abstract the aim of this paper is to design a class of two step runge kutta nystrom methods of arbitrarily high order for the special second order equation y t f y t for use on parallel computers starting with an s stage implicit two step runge kutta nystrom method of order p with k p 2 implicit stages we apply the highly parallel predictor corrector iteration process in p ec me mode in this way we obtain an explicit two step runge kutta nystrom method that has order p for all m and that requires k m 1 right hand side evaluations per step of which each k evaluation can be computed in parallel by a number of numerical experiments we show the superiority of the parallel predictor corrector methods proposed in this paper over both sequential and parallel methods available in the literature

a modified partial product generator for redundant binary multipliers due to its high modularity and carry free addition a redundant binary rb representation can be used when designing high performance multipliers the conventional rb multiplier requires an additional rb partial product rbpp row because an error correcting word ecw is generated by both the radix 4 modified booth encoding mbe and the rb encoding this incurs in an additional rbpp accumulation stage for the mbe multiplier in this paper a new rb modified partial product generator rbmppg is proposed it removes the extra ecw and hence it saves one rbpp accumulation stage therefore the proposed rbmppg generates fewer partial product rows than a conventional rb mbe multiplier simulation results show that the proposed rbmppg based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits these reductions over previous nb multiplier designs incur in a modest delay increase approximately 5 percent the power delay product can be reduced by up to 59 percent using the proposed rb multipliers when compared with existing rb multipliers

rkn type parallel block pc methods with lagrange type predictors abstract this paper describes the construction of block predictor corrector methods based on runge kutta nystrom correctors our approach is to apply the predictor corrector method not only at step points but also at off step points block points so that in each step a whole block of approximations to the exact solution at off step points is computed in the next step these approximations are used to obtain a high order predictor formula using lagrange interpolation by suitable choice of the abscissas of the off step points a much more accurately predicted value is obtained than by predictor formulas based on last step values since the block of approximations at the off step points can be computed in parallel the sequential costs of these block predictor corrector methods are comparable with those of a conventional predictor corrector method furthermore by using runge kutta nystrom corrector methods the computation of the approximation at each off step point is also highly parallel application of the resulting block predictor corrector methods to a few widely used test problems reveals that the sequential costs are reduced by a factor ranging from 4 to 50 when compared with the best sequential methods from the literature

twostep by twostep continuous pirkn type pc methods for nonstiff ivps abstract in this paper we start with the consideration of direct collocation based runge kutta nystrom rkn methods with continuous output formulas for solving nonstiff initial value problems ivps for systems of special second order differential equations y t f t y t at n th step the continuous output formulas can be used for calculating the step values at n 2 th step and the integration processes can be proceeded twostep by twostep in this case we obtain twostep by twostep rkn methods with continuous output formulas continuous tbtrkn methods furthermore we consider a parallel predictor corrector pc iteration scheme using the continuous tbtrkn methods as corrector methods with predictor methods defined by the continuous output formulas the resulting twostep by twostep parallel iterated rkn type pc methods with continuous output formulas twostep by twostep continuous pirkn type pc methods or tbtcpirkn methods give us a faster integration processes numerical comparisons based on the solution of a few widely used test problems show that the new tbtcpirkn methods are much more efficient than the well known pirkn methods the famous nonstiff sequential odex2 dop853 codes and comparable with the cpirkn methods

on the fly conversion of redundant into conventional representations an algorithm to convert redundant number representations into conventional representations is presented the algorithm is performed concurrently with the digit by digit generation of redundant forms by schemes such as srt division it has a step delay roughly equivalent to the delay of a carry save adder and simple implementation the conversion scheme is applicable in arithmetic algorithms such as nonrestoring division square root and on line operations in which redundantly represented results are generated in a digit by digit manner from most significant to least significant

a testable design of iterative logic arrays testable design of unilateral iterative logic arrays ila of combinational cells under the assumption of a single cell failure is considered the concepts of one step testability and one step c testability are introduced methods to modify the basic cell flow table so as to facilitate fault detection and location are given it is shown that if no directly observable outputs from each cell are available then it is possible to augment the cell flow table by the addition of a fixed number 4 of columns and a row so that a faulty cell can be located by a test of length proportional to log2p where p is the number of cells in the array however if directly observable outputs are available from each cell then the test length is shown to be independent of the array length to locate a faulty cell

iterative algorithm and architecture for exponential logarithm powering and root extraction an algorithm and architecture for powering computation and root extraction with fixed point and floating point exponents is presented in this paper the algorithm is based on an optimized iterative sequence of parallel and or overlapped operations 1 reciprocal 2 high radix digit recurrence logarithm 3 left to right carry free multiplication and 4 high radix online exponential a redundant number system is used to allow for the overlapping of the different operations of the algorithm as the logarithm and exponential are part of the sequence of operations some minor changes are made to allow for the independent computation of the logarithm and exponential functions a sequential implementation of the algorithm is proposed and the execution times and hardware requirements are estimated for single and double precision floating point computations these estimates are obtained for several radices according to an approximate model for the delay and area of the main logic blocks and help to determine the radix values which lead to the most efficient implementations

hybrid signed digit number systems a unified framework for redundant number representations with bounded carry propagation chains a novel hybrid number representation is proposed it includes the two s complement representation and the signed digit representation as special cases the hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length the framework reveals a continuum of number representations between the two extremes of two s complement and signed digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders multipliers and alike we present several static cmos implementations of a two operand adder which employ the proposed representations we then derive quantitative estimates of area in terms of the required number of transistors and the maximum carry propagation delay for such an adder the analysis clearly illustrates the trade offs between area and execution time associated with each of the possible representations we also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times in practice the area available to a designer is often limited in such cases the designer can select the particular hybrid representation that yields the most suitable implementation fastest lowest power consumption etc while satisfying the area constraint similarly if the worst case delay is predetermined the designer can select a hybrid representation that minimizes area or power under the delay constraint

a high speed reduced size adder under left to right input arrival an efficient parallel adder under left to right input arrival is proposed making full use of the delay of the input arrival it produces the sum within a small constant delay after the arrival of the final bits its amount of hardware is proportional to the operand length it can be applied to the quotient conversion in an array divider

simulations of valveless pumping in an open elastic tube mathematical models and numerical simulations of flows driven by pumping without valves valveless pumping are presented this work has been originally motivated by a biomedical objective to explain the complicated valveless blood flow mechanism in the circulation for instance the fetal circulation before the formation of valves and blood circulation during cardiopulmonary resuscitation a mathematical model of valveless pumping either in a closed loop system or in an open system consists of a couple of tubes with different elasticities or radii in this work we develop new models which are not necessarily connected by two different materials only one open elastic tube and an open elastic tube contained in a closed almost rigid tank although only one soft material is used or the soft and rigid materials are not connected we have observed the existence of a net flow driven by the periodic compress and release action and the important features of valveless pumping that have been observed in earlier models or experiments we have also shown that there exist mostly one directional net flows inside the elastic tube if a long and thin tube is considered and the pumping is applied to the short portion near the edge of the tube this might explain why most earlier reports on the physical experiments could not easily observe the existence of both directional net flows depending on the parameters such as frequency another important result is that the direction and the magnitude of a net flow can be explained by the sign and the amount of power which is work done on the fluid by the fluid pressure and the elastic wall over one period respectively a new feature in this work is that only one elastic material is sufficient to show the existence of a net flow in a valveless pump system because of a simple structure in our new model it is much easier to construct a valveless pump system applicable to real world applications such as a microelectromechanical system device

high performance low power left to right array multiplier design we present a high performance low power design of linear array multipliers based on a combination of the following techniques signal flow optimization in 3 2 adder array for partial product reduction left to right leapfrog lrlf signal flow and splitting of the reduction array into upper lower parts the resulting upper lower lrlf ullrlf multiplier is compared with tree multipliers from automatic layout experiments we find that ullrlf multipliers have similar power delay and area as tree multipliers for n spl les 32 with more regularity and inherently shorter interconnects the ullrlf structure presents a competitive alternative to tree structures in the design of fast low power multipliers implemented in deep submicron vlsi technology

parallel iterated pseudo two step runge kutta nystrom methods for nonstiff second order ivps abstract the aim of this paper is to consider parallel iteration schemes for a general class of pseudo two step runge kutta nystrom rkn methods of arbitrary high order for solving nonstiff initial value problems y t f y t y t 0 y 0 y t 0 y 0 on parallel computers starting with an s stage pseudo two step rkn method of order p with w implicit stages we apply the highly parallel pc iteration process in p ec m e mode the resulting piptrkn method parallel iterated pseudo two step rkn method uses an optimal number of processors equal to w p 2 by a number of numerical experiments we show the superiority of the piptrkn methods proposed in this paper over both sequential and parallel methods available in the literature

the design of easily testable vlsi array multipliers array multipliers are well suited for vlsi implementation because of the regularity in their iterative structure however most vlsi circuits are difficult to test this correspondence shows that with appropriate cell design array multipliers can be designed to be very easily testable an array multiplier is called c testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns the testability of two well known array multiplier structures is studied in detail the conventional design of the carry save array multiplier is modified the modified design is shown to be c testable and requires only 16 test patterns similar results are obtained for the baugh wooley two s complement array multiplier a modified design of the baugh wooley array multiplier is shown to be c testable and requires 55 test patterns the c testability of two other array multipliers namely the carry propagate and the trw designs is also presented

detection of multiple faults in two dimensional ilas we provide test sets proportional to the sum of the two dimensions of the array for a large class of cells which allow us to test rows or columns of cells of the array independently constant length test sets for array multipliers have been found under the single faulty cell model if the array is modified and otherwise test sets are proportional to the number of cells we can verify the full adder array of a combinational n spl times m multiplier in o n m tests under the multiple faulty cell mfc model the entire multiplier including the and gates which generate the summands can be verified after applying the same modifications which make the multiplier c testable under the single faulty cell model