adaptive estimation of regression models via moment restrictions abstract this paper considers adaptive estimation of regression models by means of generalized method of moments estimators two models are considered one with an i i d disturbance that is independent of the regressors and one with a conditionally symmetric but possibly heteroskedastic disturbance for both cases the paper develops linearized estimators that are asymptotically efficient if the number and variety of moment conditions are allowed to grow at an appropriate rate with the sample size in the general symmetric case no other adaptive estimator has yet been proposed also results of a small monte carlo study indicate that in the independence case the small sample performance of the generalized method of moments estimator can be quite good vis a vis other estimators previously proposed

low complexity bit parallel architectures for polynomial basis multiplication over gf 2m representing the field elements with respect to the polynomial or standard basis we consider bit parallel architectures for multiplication over the finite field gf 2m in this effect first we derive a new formulation for polynomial basis multiplication in terms of the reduction matrix q the main advantage of this new formulation is that it can be used with any field defining irreducible polynomial using this formulation we then develop a generalized architecture for the multiplier and analyze the time and gate complexities of the proposed multiplier as a function of degree m and the reduction matrix q to the best of our knowledge this is the first time that these complexities are given in terms of q unlike most other articles on bit parallel finite field multipliers here we also consider the number of signals to be routed in hardware implementation and we show that compared to the well known mastrovito s multiplier the proposed architecture has fewer routed signals the proposed generalized architecture is further optimized for three special types of polynomials namely equally spaced polynomials trinomials and pentanomials we have obtained explicit formulas and complexities of the multipliers for these three special irreducible polynomials this makes it very easy for a designer to implement the proposed multipliers using hardware description languages like vhdl and verilog with minimum knowledge of finite field arithmetic

on the decoding of the 24 12 8 golay code an improved syndrome shift register decoding algorithm called the syndrome weight decoding algorithm is proposed for decoding three possible errors and detecting four errors in the 24 12 8 golay code this method can also be extended to decode two other short codes such as the 15 5 7 cyclic code and the 31 16 7 quadratic residue qr code the proposed decoding algorithm makes use of the properties of cyclic codes the weight of syndrome and the syndrome decoder with a reduced size lookup table rslt in order to reduce the number of syndromes and their corresponding coset leaders this approach results in a significant reduction in the memory requirement for the lookup table thereby yielding a faster decoding algorithm simulation results show that the decoding speed of the proposed algorithm is approximately 3 6 times faster than that of the algebraic decoding algorithm

high speed low complexity systolic designs of novel iterative division algorithms in gf 2 sup m we extend the binary algorithm invented by stein and propose novel iterative division algorithms over gf 2 sup m for systolic vlsi realization while algorithm ebg is a basic prototype with guaranteed convergence in at most 2m 1 iterations its variants algorithms ebd and ebdf are designed for reduced complexity and fixed critical path delay respectively we show that algorithms ebd and ebdf can be mapped to parallel in parallel out systolic circuits with low area time complexities of o m sup 2 loglogm and o m sup 2 respectively compared to the systolic designs based on the extended euclid s algorithm our circuits exhibit significant speed and area advantages

at sup 2 optimal galois field multiplier for vlsi vlsi designs for galois field multipliers which are central in many encoding and decoding procedures for error detecting and error correcting codes are presented an at sup 2 optimal galois field multiplier based on at sup 2 optimal integer multipliers for a synchronous vlsi model is exhibited galois field multiplication is done in two steps first two polynomials of degree n 1 over z sub p are multiplied and then the resulting polynomial is reduced modulo a fixed irreducible polynomial of degree n multiplication of polynomials is done by discrete fourier transform dft for p 2 the procedure is more involved for z sub p x than for z x an extension to the case of variable p is included and some open problems are stated

normal basis of the finite field f sub 2 p 1 p sup m over f sub 2 the determination of normal bases for finite fields particularly over the finite field f sub 2 is of importance in applications such as coding and cryptography this correspondence gives an explicit normal basis for a finite field f sub 2 p 1 p sup m over f sub 2 when 2 is a primitive element module p sup 2 in the case when p 3 an explicit dual basis is also obtained

polynomial division using left shift register abstract in this short note we describe a simple polynomial division circuit based on a left shift register the circuit essentially performs the modulo operation f x mod p x it is shown how the same circuit can be used to perform f x g x mod p x applications to standard basis multiplication and encoding and decoding of systematic cyclic codes are also described

fast arithmetic for public key algorithms in galois fields with composite exponents the article describes a novel class of arithmetic architectures for galois fields gf 2 sup k the main applications of the architecture are public key systems which are based on the discrete logarithm problem for elliptic curves the architectures use a representation of the field gf 2 sup k as gf 2 sup n sup m where k n spl middot m the approach explores bit parallel arithmetic in the subfield gf 2 sup n and serial processing for the extension field arithmetic this mixed parallel serial hybrid approach can lead to fast implementations as the core module a hybrid multiplier is introduced and several optimizations are discussed we provide two different approaches to squaring we develop exact expressions for the complexity of parallel squarers in composite fields which can have a surprisingly low complexity the hybrid architectures are capable of exploring the time space trade off paradigm in a flexible manner in particular the number of clock cycles for one field multiplication which is the atomic operation in most public key schemes can be reduced by a factor of n compared to other known realizations the acceleration is achieved at the cost of an increased computational complexity we describe a proof of concept implementation of an asic for multiplication and squaring in gf 2 sup n sup m m variable

a new approach to subquadratic space complexity parallel multipliers for extended binary fields based on toeplitz matrix vector products and coordinate transformation techniques we present a new scheme for subquadratic space complexity parallel multiplication in gf 2n using the shifted polynomial basis both the space complexity and the asymptotic gate delay of the proposed multiplier are better than those of the best existing subquadratic space complexity parallel multipliers for example with n being a power of 2 the space complexity is about 8 percent better while the asymptotic gate delay is about 33 percent better respectively another advantage of the proposed matrix vector product approach is that it can also be used to design subquadratic space complexity polynomial dual weakly dual and triangular basis parallel multipliers to the best of our knowledge this is the first time that subquadratic space complexity parallel multipliers are proposed for dual weakly dual and triangular bases a recursive design algorithm is also proposed for efficient construction of the proposed subquadratic space complexity multipliers this design algorithm can be modified for the construction of most of the subquadratic space complexity multipliers previously reported in the literature

a search of minimal key functions for normal basis multipliers the circuit complexity of a massey omura normal basis multiplier for a finite field gf 2 sup m depends on the key function for multiplication key functions with minimum complexity called minimal key functions are desirable this paper investigates the complexity of a key function and reports search results of minimal key functions a table of minimal key functions for m up to 31 is included

a new representation of elements of finite fields gf 2 sup m yielding small complexity arithmetic circuits let f sub 2 denote the binary field and f sub 2m an algebraic extension of degree m 1 over f sub 2 traditionally elements of f sub 2m are either represented as powers of a primitive element of f sub 2m together with 0 or by an expansion in a basis of the vector space f sub 2m over f sub 2 we propose a new representation based on an isomorphism from f sub 2m into the residue polynomial ring module x sup n 1 the new representation simultaneously satisfies the properties of various traditional representations which leads in some cases to architectures of parallel in parallel out arithmetic circuits adder multiplier exponentiator inverter squarer divider with average to small complexity we show that the implementation of all the arithmetic circuits designed for the new representation on an integrated circuit sometimes has smaller complexity than the implementation of all the arithmetic circuits designed for other representations in addition we derive a serial multiplier for the field f sub 2m which comprises the least number of gates of all the serial multipliers known to the author when m 1 is a prime such that 2 is primitive in the field z sub m 1

a systolic power sum circuit for gf 2 sup m a systolic power sum circuit designed to perform ab sup 2 c computations in the finite field gf 2 sup m is presented where a b and c are arbitrary elements of gf 2 sup m this new circuit is constructed by m sup 2 identical cells each of which consists of three 2 input and logical gates one 2 input xor gate one 3 input xor gate and ten latches the ab sup 2 c computation is required in decoding many error correcting codes the paper shows that a decoder implemented using the new power sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product sum multipliers

efficient multiplication beyond optimal normal bases in cryptographic applications the use of normal bases to represent elements of the finite field gf 2 sup m is quite advantageous especially for hardware implementation in this article we consider an important field operation namely multiplication which is used in many cryptographic functions we present a class of algorithms for normal basis multiplication in gf 2 sup m our proposed multiplication algorithm for composite finite fields requires a significantly lower number of bit level operations and hence can reduce the space complexity of cryptographic systems

low complexity bit parallel canonical and normal basis multipliers for a class of finite fields we present a new low complexity bit parallel canonical basis multiplier for the field gf 2m generated by an all one polynomial the proposed canonical basis multiplier requires m sup 2 1 xor gates and m sup 2 and gates we also extend this canonical basis multiplier to obtain a new bit parallel normal basis multiplier

derivation of reduced test vectors for bit parallel multipliers over gf 2 m this paper presents an algebraic testing method for detecting stuck at faults in the polynomial basis pb bit parallel bp multiplier circuits over gf 2m the proposed technique derives the test vectors from the expressions of the inner product ip variables without any requirement of the atpg tool this low complexity testing method requires 2m 1 test vectors for detecting single stuck at faults in the and part and multiple stuck at faults in the exor part of the multiplier circuits the test vectors are independent of the multiplier s structure as proposed in t a gulliver et al 1991 but are dependent on m for the multiplier circuits the test set is found to be smaller in size than the atpg generated test set the test set provides 100 percent single stuck at fault coverage

high speed architectures for multiplication using reordered normal basis normal basis has been widely used for the representation of binary field elements mainly due to its low cost squaring operation optimal normal basis type ii is a special class of normal basis exhibiting very low multiplication complexity and is considered as a safe choice for hardware implementation of cryptographic applications in this paper high speed architectures for binary field multiplication using reordered normal basis are proposed where reordered normal basis is referred to as a certain permutation of optimal normal basis type ii complexity comparison shows that the proposed architectures are faster compared to previously presented architectures in the open literature using either an optimal normal basis type ii or a reordered normal basis one advantage of the new word level architectures is that the critical path delay is a constant not a function of word size this enables the multipliers to operate at very high clock rates regardless of the field size or the number of words hardware implementation of some practical size multipliers for elliptic curve cryptography is also included

low complexity multiplier architectures for single and hybrid double multiplications in gaussian normal bases the extensive rise in the number of resource constrained wireless devices and the needs for secure communications with the servers imply fast and efficient cryptographic computations for both parties efficient hardware implementation of arithmetic operations over finite field using gaussian normal basis is attractive for public key cryptography as it provides free squarings in this paper we first present two low complexity digit level multiplier architectures it is shown that the proposed multipliers outperform the existing gaussian normal basis gnb multiplier structures available in the literature then for the first time using these two architectures we propose a new digit level hybrid multiplier which performs two successive multiplications with the same latency as the one for one multiplication we have studied the efficiency of the proposed hybrid architecture in terms of area and time delay for different digit sizes the main advantage of this new hybrid architecture is to speed up exponentiation and point multiplication whenever double multiplication is required and the traditional schemes fail due to the data dependencies we have investigated the applicability of the proposed hybrid structure to reduce the latency of exponentiation based cryptosystems our analysis and timing results show that the expected acceleration in double exponentiation is considerable prototypes of the presented low complexity multiplier architectures and the proposed hybrid architecture are implemented and experimental results are presented

an algorithm to design finite field multipliers using a self dual normal basis the concept of using a self dual normal basis to design the massey omura finite field multiplier is presented an algorithm is given to locate a self dual normal basis for gf 2 sup m for odd m a method to construct the product function for designing the massey omura multiplier is developed it is shown that the construction of the product function based on a self dual basis is simpler than that based on an arbitrary normal basis

convergence of hermite interpolants on the circle using two derivatives in this paper we deal with hermite interpolation problems on the unit circle considering up to the second derivative for the interpolation conditions and taking equally spaced points as nodal system in the extended fejer case which corresponds to take vanishing values for the first two derivatives we prove the uniform convergence for the interpolants related to continuous functions with smooth modulus of continuity we also consider the hermite case with non vanishing conditions for the derivatives for which we establish sufficient conditions on the interpolation conditions to obtain convergence

a comparison of vlsi architecture of finite field multipliers using dual normal or standard bases three different finite field multipliers are presented 1 a dual basis multiplier due to e r berlekamp 1982 the massey omura normal basis multiplier and 3 the scott tavares peppard standard basis multiplier these algorithms are chosen because each has its own distinct features that apply most suitably in particular areas they are implemented on silicon chips with nmos technology so that the multiplier most desirable for vlsi implementation can readily be ascertained

systolic multipliers for finite fields gf 2 m two systolic architectures are developed for performing the product sum computation ab c in the finite field gf 2m of 2melements where a b and c are arbitrary elements of gf 2m the first multiplier is a serial in serial out one dimensional systolic array while the second multiplier is a parallel in parallel out two dimensional systolic array the first multiplier requires a smaller number of basic cells than the second multiplier the second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively to perform single computations both multipliers require the same computational time in both cases the architectures are simple and regular and possess the properties of concurrency and modularity as a consequence they are well suited for use in vlsi systems

some improvements to the hermite fejer interpolation on the circle and bounded interval in this paper we study the convergence of the hermite fejer and the hermite interpolation polynomials which are constructed by taking equally spaced nodes on the unit circle the results that we obtain are concerned with the behaviour outside and inside the unit circle when we consider analytic functions on a suitable domain as a consequence we achieve some improvements on hermite interpolation problems on the real line since the hermite fejer and the hermite interpolation problems on 1 1 with nodal systems mainly based on sets of zeros of orthogonal polynomials have been widely studied in our contribution we develop a theory for three special nodal systems they are constituted by the zeros of the tchebychef polynomial of the second kind joint with the extremal points 1 and 1 the zeros of the tchebychef polynomial of the fourth kind joint with the point 1 and the zeros of the tchebychef polynomial of the third kind joint with the point 1 we present a simple and efficient method to compute these interpolation polynomials and we study the convergence properties

double basis multiplicative inversion over gf 2 sup m inversion over galois fields is much more difficult than the corresponding multiplication efficient computation of inverses in gf 2 sup m is considered by solving a set of linear equations over the ground field gf 2 the proposed algorithm uses two separate bases for the representation of its input and output elements and has low computational complexity the algorithm is also suitable for hardware implementation using vlsi technologies

bit serial systolic divider and multiplier for finite fields gf 2 sup m a systolic structure for bit serial division over the field gf 2 sup m is developed consideration is given to avoid global data communications and dependency of the time step duration on m this is important for applications where the value of m is large the divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m sup 2 and m respectively it does not depend on the irreducible polynomial and can be expanded easily moreover with m additional simple processors a bit serial systolic multiplier is developed which uses part of the divider structure this is advantageous from the implementation point of view as both the divider and multiplier can be fabricated on a single chip resulting in a reduction of area

closed form expression for the average weight of signed digit representations in radix r number system the minimal weight signed digit sd representation has minimal number of nonzero signed digits which belong to the set spl plusmn 1 spl plusmn 2 spl plusmn r 1 in this article we derive closed form expressions for the average number of nonzero digits in the minimal weight sd representation and for the average length of the canonical sd representation a special case of the minimal weight sd form of a positive integer whose radix r form is of length n n spl ges 1

a new algorithm for multiplication in finite fields a new algorithm is presented for computing the product of two elements in a finite field by means of sums and products in a fixed subfield the algorithm is based on a normal basis representation of fields and assumes that the dimension m of the finite field over the subfield is a highly composite number a very fast parallel implementation and a considerable reduction in the number of computations are allowed in comparison to some methods discussed in the literature

design of a linear systolic array for computing modular multiplication and squaring in gf 2m abstract one of the main operations for the public key cryptosystem is the modular exponentiation in this paper we analyze the montgomery s algorithm and design a linear systolic array for performing both modular multiplication and modular squaring simultaneously the proposed systolic array with less hardware complexity can be designed by making use of common multiplicand multiplication in the right to left modular exponentiation over gf 2 m for the fast computation of the modular exponentiation the proposed systolic array has 1 25 times improvement in area time complexity when compared to existing multipliers the proposed systolic array suffers a little loss in time complexity but it has 1 44 times improvement in area complexity since it executes the common parts that exist in the simultaneous computation of both modular multiplication and squaring only once it could be designed on vlsi hardware and used in ic cards

a word level finite field multiplier using normal basis hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost in this paper a new word level finite field multiplier using normal basis is proposed the proposed architecture takes d clock cycles to compute the product bits where the value for d 1 d m can be arbitrarily selected by the designer to set the tradeoff between area and speed when there exists an optimal normal basis it is shown that the proposed design has a smaller critical path delay than other word level normal basis multipliers found in the literature while its circuit complexities are moderate and comparable to the others different word size multipliers were implemented in hardware and implementation results are also presented

signed digit representations of minimal hamming weight the authors give an online algorithm for computing a canonical signed digit representation of minimal hamming weight for any integer n using combinatorial techniques the probability distributions pr k sub r h where k sub r is taken to be a random variable on the uniform probability space of k digit integers is computed also using a markov chain analysis it is shown that e k sub r approximately r 1 k r 1 as k to infinity

a systolic architecture for computing inverses and divisions in finite fields gf 2 sup m a new serial in serial out systolic array is presented for performing the element inversion in gf 2 sup m with the standard basis representation the architecture is highly regular modular nearest neighbor connected and thus well suited to vlsi implementation it has a latency of 7m 3 clock cycles and a throughput rate of one result per 2m 1 clock cycles this speed performance is much better than those of the previous implementations without change in hardware design the proposed inversion array can be directly used for computing the division in gf 2 sup m

a modified massey omura parallel multiplier for a class of finite fields a massey omura parallel multiplier of finite fields gf 2 sup m contains m identical blocks whose inputs are cyclically shifted versions of one another it is shown that for fields gf 2 sup m generated by irreducible all one polynomials a portion of the block is independent of the input cyclic shift hence the multiplier contains redundancy by removing the redundancy a modified parallel multiplier is presented which is modular and has a lower circuit complexity

systolic array implementation of euclid s algorithm for inversion and division in gf 2 sup m this paper presents two new systolic arrays to realize euclid s algorithm for computing inverses and divisions in finite fields gf 2 sup m with the standard basis representation one of these two schemes is parallel in parallel out and the other is serial in serial out the former employs o m sup 2 area complexity to provide the maximum throughput in the sense of producing one result every clock cycle while the latter achieves a throughput of one result per m clock cycles using o m log m area complexity both of the proposed architectures are highly regular and thus well suited to vlsi implementation as compared to existing related systolic architectures with the same throughput performance the proposed parallel in parallel out scheme reduces the hardware complexity and thus the area time product by a factor of o m and the proposed serial in serial out scheme by a factor of o m log sub 2 m

montgomery multiplier and squarer for a class of finite fields montgomery multiplication in gf 2 sup m is defined by a x b x r sup 1 x mod f x where the field is generated by a root of the irreducible polynomial f x a x and b x are two field elements in gf 2 sup m and r x is a fixed field element in gf 2 sup m in this paper first a slightly generalized montgomery multiplication algorithm in gf 2 sup m is presented then by choosing r x according to f x we show that efficient architectures of bit parallel montgomery multiplier and squarer can be obtained for the fields generated with an irreducible trinomial complexities of the montgomery multiplier and squarer in terms of gate counts and time delay of the circuits are investigated and found to be as good as or better than that of previous proposals for the same class of fields

a new hardware architecture for operations in gf 2 sup n the efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented the common field representations are a polynomial basis representation and a normal basis representation in this paper we introduce a nonconventional basis and present a new bit parallel multiplier which is as efficient as the modified massey omura multiplier using the type i optimal normal basis

efficient algorithms and architectures for field multiplication using gaussian normal bases recently implementations of normal basis multiplication over the extended binary field gf 2 sup m have received considerable attention a class of low complexity normal bases called gaussian normal bases has been included in a number of standards such as ieee and nist for an elliptic curve digital signature algorithm the multiplication algorithms presented there are slow in software since they rely on bit wise inner product operations in this paper we present two vector level software algorithms which essentially eliminate such bit wise operations for gaussian normal bases our analysis and timing results show that the software implementation of the proposed algorithm is faster than previously reported normal basis multiplication algorithms the proposed algorithm is also more memory efficient compared with its look up table based counterpart moreover two new digit level multiplier architectures are proposed and it is shown that they outperform the existing normal basis multiplier structures as compared with similar digit level normal basis multipliers the proposed multiplier with serial output requires the fewest number of xor gates and the one with parallel output is the fastest multiplier

concurrent error detection and correction in gaussian normal basis multiplier over gf 2 m fault based cryptanalysis has been developed to effectively break both private key and public key cryptosystems making robust finite field multiplication a very important research topic in recent years however no robust normal basis multiplier has been proposed in the literature therefore this investigation presents a semisystolic gaussian normal basis multiplier based on the proposed gaussian normal basis multiplier both concurrent error detection and correction capabilities can be easily achieved using time redundancy technology with no hardware modification

generalized signed digit number systems a unifying framework for redundant number representations signed digit sd number representation systems have been defined for any radix r or 3 with digit values ranging over the set alpha 1 0 1 alpha where alpha is an arbitrary integer in the range 1 2r

more efficient estimation under non normality when higher moments do not depend on the regressors using residual augmented least squares under normality least squares is efficient however if the errors are not normal we can gain efficiency from the assertion that higher moments do not depend on the regressors in this paper we show how the assumption that higher moments do not depend on the regressors can be exploited in a gmm framework and we provide simple estimators that are asymptotically equivalent to the gmm estimators these estimators can be calculated by linear regressions which have been augmented with functions of the least squares residuals

efficient exponentiation of a primitive root in gf 2 sup m in this paper exponentiation of a primitive root in gf 2 sup m is considered signed digit sd number representation is used to efficiently represent the exponent and the corresponding algorithms and structures for exponentiation are developed for primitive multiplications required in exponentiations extended bidirectional linear feedback shift registers are proposed and used for the cases where the exponent is represented as a binary or a radix 4 sd number comparisons are made with other methods on the bases of space time and possible power consumption since the proposed structures can effectively reduce power and area when implemented in vlsi they are especially suitable for battery powered portable devices

gf 2 sup m multiplication and division over the dual basis in this paper an algorithm for gf 2 sup m multiplication division is presented and a new more generalized definition of duality is proposed from these the bit serial berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers furthermore it is shown that hardware efficient bit parallel dual basis multipliers can also be designed these multipliers have a regular structure are easily extended to different gf 2 sup m and hence suitable for vlsi implementations as in the bit serial case these bit parallel multipliers can also be hardwired to carry out constant multiplication these constant multipliers have reduced hardware requirements and are also simple to design in addition the multiplication division algorithm also allows a bit serial systolic finite field divider to be designed this divider is modular independent of the defining irreducible polynomial for the field easily expanded to different gf 2 sup m and its longest delay path is independent of m

gibbs phenomenon in the hermite interpolation on the circle hermite fejer interpolation problems on the unit circle and bounded interval are usually studied in relation with continuous functions there are few references concerning these problems for functions with discontinuities thus the aim of this paper is to describe the behavior of the hermite fejer and hermite interpolants for piecewise continuous functions on the unit circle analyzing the corresponding gibbs phenomenon near the discontinuities and providing the asymptotic amplitude of the gibbs height

a new architecture for a parallel finite field multiplier with low complexity based on composite fields a bit parallel structure for a multiplier with low complexity in galois fields is introduced the multiplier operates over composite fields gf 2 sup n sup m with k nm the karatsuba ofman algorithm a karatsuba and y ofmanis 1963 is investigated and applied to the multiplication of polynomials over gf 2 sup n it is shown that this operation has a complexity of order o k sup log23 under certain constraints regarding k a complete set of primitive field polynomials for composite fields is provided which perform module reduction with low complexity as a result multipliers for fields gf 2 sup k up to k 32 with low gate counts and low delays are listed the architectures are highly modular and thus well suited for vlsi implementation

gibbs wilbraham phenomenon on lagrange interpolation based on analytic weights on the unit circle abstract this paper is devoted to study lagrange interpolation based on nodal systems constituted by the roots of para orthogonal polynomials with respect to analytic weights on the unit circle the presented results address in addition to algorithmic and convergence questions for continuous and discontinuous functions a detailed study of the gibbs wilbraham phenomenon

algorithms and convergence for hermite interpolation based on extended chebyshev nodal systems the chebyshev nodal systems play an important role in the theory of hermite interpolation on the interval 1 1 for the cases of nodal points corresponding to the chebyshev polynomials of the second kind u n x the third kind v n x and the fourth kind w n x it is usual to consider the extended systems that is to add the endpoints 1 and 1 to the nodal system related to u n x to add 1 to the nodal system related to v n x and to add 1 to the nodal system related to w n x the interpolation methods that are usually used in connection with these extended nodal systems are quasi hermite interpolation and extended hermite interpolation and it is well known that the performance of these two great methods is quite good when it comes to continuous functions this work attempts to complete the theory concerning these extended chebyshev nodal systems for this we have obtained a new formulation for the hermite interpolation polynomials based upon barycentric formulas the feature of this approach is that the derivatives of the function at the endpoints of the interval are also prescribed further some convergence results are obtained for these extended interpolants when apply to continuous functions

low complexity word level sequential normal basis multipliers for efficient hardware implementation of finite field arithmetic units the use of a normal basis is advantageous in this paper two classes of architectures for multipliers over the finite field gf 2 sup m are proposed these multipliers are of sequential type i e after receiving the coordinates of the two input field elements they go through k 1 spl les k spl les m iterations i e clock cycles to finally yield all the coordinates of the product in parallel the value of k depends on the word size w spl lceil m k spl rceil for w 1 these multipliers are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multipliers available in the open literature this makes the proposed multipliers suitable for applications where the value of m is large but space is of concern e g resource constrained cryptographic systems additionally if the field dimension m is composite i e m kn then the extension of one class of the architectures yields a highly efficient multiplier over composite fields

structure of parallel multipliers for a class of fields gf 2 m abstract this paper presents a configuration of parallel multipliers for gf 2 m based on canonical bases the possible parallel multipliers by the proposed configuration are limited to a class of fields gf 2 m however they can be constructed by o m 2 and gates and o m 2 eor gates with the structural modularity this is a desirable feature for the hardware implementation and their operation time is about log m t where m is the dimension of gf 2 m and t is the delay time of an eor gate in order to construct such parallel multipliers we define two types of polynomials of special form over gf 2 one is called all one polynomial denoted by aop and the other is called equally spaced polynomial denoted by esp furthermore we show a necessary and sufficient condition for esps to be irreducible over gf 2 and the uniqueness of the irreducible esps over gf 2 finally we propose the configuration of parallel multipliers for a class of fields gf 2 m based on irreducible aops and esps over gf 2

asymptotic efficiency in estimation with conditional moment restrictions abstract in this paper bounds on asymptotic efficiency are derived for a class of non parametric models the data are independent and identically distributed according to some unknown distribution f there is a given function of the data and a parameter the restrictions are that a conditional expectation of this function is zero at some point in the parameter space this point is to be estimated if f is assumed to be a multinomial distribution with known finite support then the problem becomes parametric and the bound can be obtained from the information matrix this bound turns out to depend only upon certain conditional moments and not upon the support of the distribution since a general f can be approximated by a multinomial distribution the multinomial bound applies to the general case

redundancy of moment conditions it is well known that adding moment conditions cannot decrease asymptotic efficiency however sometimes additional moment conditions are redundant in the sense that they do not increase the asymptotic efficiency of estimation for some or all of the parameters of interest this paper gives a general treatment of redundancy of moment conditions it provides necessary and sufficient conditions for redundancy in several equivalent forms the paper also provides interesting results for the case that there are three or more sets of moment conditions

monte carlo evidence on adaptive maximum likelihood estimation of a regression on examine la performance des estimateurs du maximum de vraisemblance adaptatifs lorsque ces parametres sont preselectionnes ou alternativement determines par une methode du bootstrap basee sur les donnees

low complexity bit parallel multipliers for a class of finite fields new implementations of bit parallel multipliers for a class of finite fields are proposed the class of finite fields is constructed with irreducible aops all one polynomials and esps equally spaced polynomials the size and time complexities of our proposed multipliers are lower than or equal to those of the previously proposed multipliers of the same class

wg a family of stream ciphers with designed randomness properties in this paper we present a family of stream ciphers which generate a keystream with ideal two level autocorrelation the design also guarantees other randomness properties i e balance long period ideal tuple distribution and high and exact linear complexity we discuss how these properties are achieved by the proposed design and show how to select various parameters to obtain an efficient stream cipher for the desired security level we also show that the proposed generators are secure against time memory data tradeoff attacks algebraic attacks and correlation attacks finally we present wg 128 as a concrete example of a wg stream cipher with a key size of 128bits

architectures for exponentiation over gd 2 sup n adopted for smartcard application two exponentiation circuits are proposed using the fact that squaring is a linear operation over gf 2 sup n a time space tradeoff in smartcard based circuitry is presented it is shown how multiplication is performed by a single shift based on replacing the public key alpha sup a in gf 2 sup n by its minimal polynomial other considerations related to structure regularity and the possible use of dynamic shift registers are also treated

algorithms for solving hermite interpolation problems using the fast fourier transform we present a method for computing the hermite interpolation polynomial based on equally spaced nodes on the unit circle with an arbitrary number of derivatives in the case of algebraic and laurent polynomials it is an adaptation of the method of the fast fourier transform fft for this type of problems with the following characteristics easy computation small number of operations and easy implementation in the second part of the paper we adapt the algorithm for computing the hermite interpolation polynomial based on the nodes of the tchebycheff polynomials and we also study hermite trigonometric interpolation problems

optimal left to right binary signed digit recoding this paper describes new methods for producing optimal binary signed digit representations this can be useful in the fast computation of exponentiations contrary to existing algorithms the digits are scanned from left to right i e from the most significant position to the least significant position this may lead to better performances in both hardware and software

vlsi architectures for computing multiplications and inverses in gf 2 m finite field arithmetic logic is central in the implementation of reed solomon coders and in some cryptographic algorithms there is a need for good multiplication and inversion algorithms that can be easily realized on vlsi chips massey and omura 1 recently developed a new multiplication algorithm for galois fields based on a normal basis representation in this paper a pipeline structure is developed to realize the massey omura multiplier in the finite field gf 2m with the simple squaring property of the normal basis representation used together with this multiplier a pipeline architecture is also developed for computing inverse elements in gf 2m the designs developed for the massey omura multiplier and the computation of inverse elements are regular simple expandable and therefore naturally suitable for vlsi implementation

fault tolerant decoders for cyclic error correcting codes high speed cyclic code decoders which are central to modern communication systems when implemented in dense very large scale integration vlsi are susceptible to pernicious momentary internal soft fails presenting a demanding error control challenge however special structures inherent in such decoders offer new methods for incorporating distributed error control throughout their designs the underlying design principles and motivations are emphasized providing a variety of options to meet various requirements bose chaudhuri hocquenghem bch codes are used to exemplify the new techniques as applied to the usual three standard subsystems present in a decoder the first and last parts syndrome calculations and transform inversion both involve finite field transforms suggesting the effective application of fast transform algorithms error control features are based upon the chord properties of the transform coefficients including even fast algorithms the third subsystem the berlekamp massey algorithm can be protected through a chord recursion property affiliated with the error location connection polynomial the propagation and spread of internal errors are studied and a special sink register compares several quantities available in close proximity to their easily recomputed counterparts most of these results are applicable to generalized to decoders for codes over higher ordered alphabets such as reed solomon codes

a new finite field multiplier using redundant representation this article presents simple and highly regular architectures for finite field multipliers using a redundant representation the basic idea is to embed a finite field into a cyclotomic ring which is based on the elegant multiplicative structure of a cyclic group one important feature of our architectures is that they provide area time trade offs which enable us to implement the multipliers in a partial parallel hybrid fashion this hybrid architecture has great significance in its vlsi implementation in very large fields the squaring operation using the redundant representation is simply a permutation of the coordinates it is shown that when there is an optimal normal basis the proposed bit serial and hybrid multiplier architectures have very low space complexity constant multiplication is also considered and is shown to have an advantage in using the redundant representation

comb architectures for finite field multiplication in f 2 m two high speed bit serial word parallel or comb style finite field multipliers are proposed in this paper the first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type ii optimal normal basis exists the proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same the proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis field programmable gate array fpga implementation results of the proposed multipliers are compared to those of the previous methods using the same basis which confirms that the proposed multipliers allow a much higher clock rate

a vlsi design for computing exponentiations in gf 2 sup m and its application to generate pseudorandom number sequences a vlsi design for computing exponentiation in finite fields is developed an algorithm to generate a relatively long pseudorandom number sequence is presented it is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme

architecture for a low complexity rate adaptive reed solomon encoder multiple error correcting reed solomon rs codes have many practical applications the complexity of an rs encoder depends on multiplications in the finite field over which the code is defined we consider a triangular basis for representing the field elements and present an architecture for a rate adaptive rs encoder using a triangular basis multiplication algorithm the architecture supports pipeline and bit serial operations and has a low circuit complexity

on computing multiplicative inverses in gf 2 sup m the design of a modular standard basis inversion for galois fields gf 2 sup m based on euclid s algorithm for computing the greatest common divisor of two polynomials is presented the asymptotic complexity is linear with m both in computation time and area requirement thus resulting in an at complexity of o m sup 2 this is a significant improvement over the best previous proposal which achieves at complexity of only o m sup 3

fast inversion in schmi gf 2 m with normal basis using hybrid double multipliers fast inversion in finite fields is crucial for high performance cryptography and codes we present techniques to exploit the recently proposed hybrid double multipliers for fast inversions in binary fields gf 2m with normal bases a hybrid double multiplier computes a double multiplication the product of three elements in gf 2m with a latency comparable to the latency of single multiplication of two elements traditional approaches such as itoh tsujii cannot utilize hybrid double multipliers we devise a new inversion algorithm based on ternary representations that exploits their potential the algorithm reduces the latency of inversion significantly for the fields recommended by nist if hybrid double multipliers are employed for example the algorithm computes an inversion in gf 2163 with only five double multiplications whereas the itoh tsujii algorithm requires nine single or double multiplications we propose a new inverter architecture using this new algorithm and a hybrid double multiplier we show that it is faster than the existing techniques by providing asic synthesis results using 65 nm cmos technology for example our inverter for gf 2163 achieves about 34 percent shorter computation time than an inverter using the itoh tsujii algorithm and a single multiplier

efficient multiplier architectures for galois fields gf 2 sup 4n this contribution introduces a new class of multipliers for finite fields gf 2 sup n sup 4 the architecture is based on a modified version of the karatsuba ofman algorithm koa by determining optimized field polynomials of degree four the last stage of the koa and the module reduction can be combined this saves computation and area in vlsi implementations the new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with koa based architectures with separate module reduction the new multipliers lead to highly modular architectures and are thus well suited for vlsi implementations three types of field polynomials are introduced and conditions for their existence are established for the small fields where n 2 3 8 which are of primary technical interest optimized field polynomials were determined by an exhaustive search for each field order exact space and time complexities are provided

improved instrumental variables and generalized method of moments estimators this paper considers gmm estimation with moment conditions of the usual type plus extra moment conditions that do not depend on the parameters the extra moment conditions improve efficiency if they are correlated with the original set of moment conditions this is true in linear and nonlinear models but in linear models we provide simple explicit formulas for the improved estimators our results may be useful in rational expectations models in which an equation s error is a forecast error and the extra moment conditions would be forecast errors in related variables

fault detection architectures for field multiplication using polynomial bases in many cryptographic schemes the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates some of these gates may become faulty in the field due to natural causes or malicious attacks which may lead to the generation of erroneous outputs by the multiplier in this paper we propose new architectures to detect erroneous outputs caused by certain types of faults in bit parallel and bit serial polynomial basis multipliers over finite fields of characteristic two in particular parity prediction schemes are developed for detecting errors due to single and certain multiple stuck at faults although the issue of detecting soft errors in registers is not considered the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field

new systolic arrays for c ab sup 2 inversion and division in gf 2 sup m in this paper we present a new parallel in parallel out systolic array with unidirectional data flow for performing the power sum operation c ab sup 2 in finite fields gf 2 sup m the architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle it is highly regular modular and thus well suited to vlsi implementation as compared to a previous systolic power sum circuit with bidirectional data flow and the same throughput performance the proposed one has smaller latency consumes less chip area and can more easily incorporate fault tolerant design based on the new power sum circuit we also propose a parallel in parallel out systolic array with the maximum throughput for computing inverses divisions in gf 2 sup m the proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area latency and fault tolerance

a fast algorithm for computing multiplicative inverses in gf 2 m using normal bases abstract this paper proposes a fast algorithm for computing multiplicative inverses in gf 2 m using normal bases normal bases have the following useful property in the case that an element x in gf 2 m is represented by normal bases 2 k power operation of an element x in gf 2 m can be carried out by k times cyclic shift of its vector representation c c wang et al proposed an algorithm for computing multiplicative inverses using normal bases which requires m 2 multiplications in gf 2 m and m 1 cyclic shifts the fast algorithm proposed in this paper also uses normal bases and computes multiplicative inverses iterating multiplications in gf 2 m it requires at most 2 log 2 m 1 multiplications in gf 2 m and m 1 cyclic shifts which are much less than those required in the wang s method the same idea of the proposed fast algorithm is applicable to the general power operation in gf 2 m and the computation of multiplicative inverses in gf q m q 2 n

a new construction of massey omura parallel multiplier over gf 2 sup m the massey omura multiplier of gf 2 sup m uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another in the past it was shown that for a class of finite fields defined by irreducible all one polynomials the parallel massey omura multiplier had redundancy and a modified architecture of lower circuit complexity was proposed in this article it is shown that not only does this type of multiplier contain redundancy in that special class of finite fields but it also has redundancy in fields gf 2 sup m defined by any irreducible polynomial by removing the redundancy we propose a new architecture for the normal basis parallel multiplier which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original massey omura normal basis parallel multiplier the proposed multiplier structure is also modular and hence suitable for vlsi realization when applied to fields defined by the irreducible all one polynomials the multiplier s circuit complexity matches the best result available in the open literature

hardware and software normal basis arithmetic for pairing based cryptography in characteristic three although identity based cryptography offers a number of functional advantages over conventional public key methods the computational costs are significantly greater the dominant part of this cost is the tate pairing which in characteristic three is best computed using the algorithm of duursma and lee however in hardware and constrained environments this algorithm is unattractive since it requires online computation of cube roots or enough storage space to precompute required results we examine the use of normal basis arithmetic in characteristic three in an attempt to get the best of both worlds an efficient method for computing the tate pairing that requires no precomputation and that may also be implemented in hardware to accelerate devices such as smart cards

a generalization of addition chains and fast inversions in binary fields in this paper we study a generalization of addition chains where k previous values are summed together on each step instead of only two values as in traditional addition chains such chains are called k chains and we show that they have applications in finding efficient parallelizations in problems that are known to be difficult to parallelize in particular 3 chains improve computations of inversions in finite fields using hybrid double multipliers recently it was shown that this operation can be efficiently computed using a ternary algorithm but we show that 3 chains provide a significantly more efficient solution

new architectures for digit level single hybrid double hybrid triple field multiplications and exponentiation using gaussian normal bases gaussian normal bases gnbs are special set of normal bases nbs which yield low complexity gf left 2 m right arithmetic operations in this paper we present new architectures for the digit level single hybrid double and hybrid triple multiplication of gf left 2 m right elements based on the gnb representation for odd values of m 1 the proposed fully serial in single multipliers perform multiplication of two field elements and offer high throughput when the data path capacity for entering inputs is limited the proposed hybrid double and hybrid triple digit level gnb multipliers perform respectively two and three field multiplications using the same latency required for a single digit level multiplier at the expense of increased area in addition we present a new eight ary field exponentiation architecture which does not require precomputed or stored intermediate values

modular construction of low complexity parallel multipliers for a class of finite fields gf 2 sup m structures for parallel multipliers of a class of fields gf 2 sup m based on irreducible all one polynomials aop and equally spaced polynomials esp are presented the structures are simple and modular which is important for hardware realization relationships between an irreducible aop and the corresponding irreducible esps have been exploited to construct esp based multipliers of large fields by a regular expansion of the basic modules of the aop based multiplier of a small field some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible it is shown that if for a certain degree an irreducible aop as well as an irreducible esp exist then from the complexity point of view it is advantageous to use the esp based parallel multiplier

provably sublinear point multiplication on koblitz curves and its hardware implementation we describe algorithms for point multiplication on koblitz curves using multiple base expansions of the form k sigmaplusmntaua tau 1 b and k sigmaplusmntaua tau mu b tau2 mutau 1 c we prove that the number of terms in the second type is sublinear in the bit length of k which leads to the first provably sublinear point multiplication algorithm on koblitz curves for the first type we conjecture that the number of terms is sublinear and provide numerical evidence demonstrating that the number of terms is significantly less than that of tau adic nonadjacent form expansions we present details of an innovative fpga implementation of our algorithm and performance data demonstrating the efficiency of our method we also show that implementations with very low computation latency are possible with the proposed method because parallel processing can be exploited efficiently

a fast algorithm for multiplicative inversion in gf 2 sup m using normal basis a fast algorithm for multiplicative inversion in gf 2 sup m using normal basis is proposed it is an improvement on those proposed by itoh and tsujii and by chang et al which are based on fermat s theorem and require o logm multiplications the number of multiplications is reduced by decomposing m 1 into several factors and a small remainder