an interpolating memory unit for function evaluation analysis and design a technique for the evaluation of a general continuous function f x is presented and the design of an interpolating memory as an implementation of the technique is described the technique partitions the domain of f x into segments and defines an interpolating or approximating function for each the implementation is a memory subsystem that holds the parameters of the approximating functions and yields an interpolated function value on each read reference polynomial interpolating functions are considered in particular hardware requirements memory and computational logic are analyzed in terms of the required precision it is shown that as long as f x has d 1 derivatives where d is the degree of the interpolating polynomial d 1 additional bits of precision of the computed f x are obtained for each additional address bit used in the interpolating memory this establishes a tradeoff between memory and computational logic which can be exploited in the design of a unit for a specific function for any precision requirement furthermore a single unit can be designed for any class of functions that have the required derivatives two examples of implementations for particular functions are presented

comments on high speed area efficient multiplier design using multiple valued current mode circuits s kawahito et al 1988 presented multiplier designs using the binary tree reduction feature of certain highly redundant radix 2 representations along with multiple valued current mode circuit techniques and shown them to compare favorably to those based on less redundant binary signed digit and carry save numbers we point out that these representation schemes and their potential advantages have been discussed in earlier publications and that a more general view of the parallel carries addition process exploited in these multipliers leads to other potentially useful representations the authors reply is also given

area time efficient sign detection technique for binary signed digit number system computer arithmetic operations based on the bsd binary signed digit number representation system lend themselves well to high speed computations due to the facilitation of limited carry addition subtraction we propose an area time efficient method for sign detection in a bsd number system based on optimized reverse tree structure when compared to other popular approaches such as the most significant carry detection based cla carry look ahead and mrc multilevel reverse carry implementations the proposed method is superior to both area and time costs in vlsi synthesis results for different word lengths show that the proposed approach to sign detection in the bsd number system continues to maintain its advantage over area and time measures

the differential cordic algorithm constant scale factor redundant implementation without correcting iterations the cordic algorithm is a well known iterative method for the efficient computation of vector rotations and trigonometric and hyperbolic functions basically cordic performs a vector rotation which is not a perfect rotation since the vector is also scaled by a constant factor this scaling has to be compensated for following the cordic iteration since cordic implementations using conventional number systems are relatively slow current research has focused on solutions employing redundant number systems which make a much faster implementation possible the problem with these methods is that either the scale factor becomes variable making additional operations necessary to compensate for the scaling or additional iterations are necessary compared to the original algorithm in contrast we developed transformations of the usual cordic algorithm which result in a constant scale factor redundant implementation without additional operations the resulting differential cordic algorithm dcordic makes use of on line most significant digit first redundant computation we derive parallel architectures for the radix 2 redundant number systems and present some implementation results based on logic synthesis of vhdl descriptions produced by a dcordic vhdl generator we finally prove that due to the lack of additional operations dcordic compares favorably with the previously known redundant methods in terms of latency and computational complexity

signed digit addition and related operations with threshold logic assuming signed digit number representations we investigate the implementation of some addition related operations assuming linear threshold networks we measure the depth and size of the networks in terms of linear threshold gates we show first that a depth 2 network with o n size weight and fan in complexities can perform signed digit symmetric functions consequently assuming radix 2 signed digit representation we show that the two operand addition can be performed by a threshold network of depth 2 having o n size complexity and o 1 weight and fan in complexities furthermore we show that assuming radix 2n 1 signed digit representations the multioperand addition can be computed by a depth 2 network with o n sup 3 size with the weight and fan in complexities being polynomially bounded finally we show that multiplication can be performed by a linear threshold network of depth 3 with the size of o n sup 3 requiring o n sup 3 weights and o n sup 2 log n fan in

division using a logarithmic exponential transform to form a short reciprocal two trees are used sequentially to calculate an approximation to 1 a where 1 a 2 these trees calculate the logarithm and exponential and the division reciprocation process can be described by 1 a e lna for bit skip accuracy of six to 10 this logarithmic exponential method uses significantly less hardware with respect to the scheme in 3 and the delays may be greater or less than those of 3 depending on the method used and the minimum bit skip

a radix 4 modular multiplication hardware algorithm for modular exponentiation a fast radix 4 modular multiplication hardware algorithm is proposed it is efficient for modular exponentiation with a large modulus used in public key cryptosystems such as the rsa cryptosystem the operands and the result of multiplication which are intermediate results in modular exponentiation are represented in a redundant representation the computation proceeds in serial parallel fashion each subtraction for the division for residue calculation is embedded in the repeated multiply add each intermediate result is represented in a more redundant representation than that for the operands and the result so that the number of the required addition subtractions is reduced all addition subtraction are carried out without carry propagation a serial parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature and is suitable for vlsi implementation

on the implementation of arithmetic support functions for generalized signed digit number systems ordinary signed digit osd number representation systems have been defined for any radix r or 3 with digit values ranging over the set alpha 1 0 1 alpha where alpha is an arbitrary integer in the range r 2 0 and beta 0 explicitly zero detection sign detection and overflow handling are also treated in depth

high speed multioperand decimal adders there is increasing interest in hardware support for decimal arithmetic as a result of recent growth in commercial financial and internet based applications consequently new specifications for decimal floating point arithmetic have been added to the draft revision of the ieee 754 standard for floating point arithmetic this paper introduces and analyzes three techniques for performing fast decimal addition on multiple binary coded decimal bcd operands two of the techniques speculate bcd correction values and correct intermediate results while adding the input operands the first speculates over one addition the second speculates over two additions the third technique uses a binary carry save adder tree and produces a binary sum combinational logic is then used to correct the sum and determine the carry into the next more significant digit multioperand adder designs are constructed and synthesized for four to 16 input operands analyses are performed on the synthesis results and the merits of each technique are discussed finally these techniques are compared to several previous techniques for high speed decimal addition

a general proof for overlapped multiple bit scanning multiplications because of recent advances in technology multibit scanning implementations can be considered that exceed three bit and four bit groupings the generalized proof for the multibit overlapped scanning multiplication is introduced and the multiplication process is discussed the proofs are intended to establish the correctness of the decode and the actions taken to produce the multiplication of any valid scheme proposed in the past and to dictate the correct decode and actions taken for any overlapped s bit scanning algorithm such that s is a natural number greater than or equal to two the multiplication is considered to be between two fractional numbers which are represented in two s complement form

leading guard digits in finite precision redundant representations redundant number representations are generally used to allow constant time additions based on the fact that only bounded carry ripples take place but carries may ripple out into positions which may not be needed to represent the final value of the result and thus a certain amount of leading guard digits are needed to correctly determine the result also when cancellation during subtractions occurs there may be nonzero digits in positions not needed to represent the result of the calculation it is shown here that for normal redundant digit sets with radix greater than two a single guard digit is sufficient to determine the value of such an arbitrary length prefix of leading nonzero digits this is also the case for the unsigned carry save representation whereas two guard digits are sufficient and may be necessary for additions in the binary signed digit and 2 s complement carry save representations thus only the guard digits need to be retained during sequences of additions and subtractions at suitable points the guard digits may then be converted into a single digit representing the complete prefix

comments on evaluation of a b k conditions without carry propagation a special carry free circuit for the evaluation of conditions of the type a b k is proposed by cortadella and llaberia 1992 and its usefulness for reducing the negative effects of conditional branches in pipelined architectures is noted it is shown that the same advantages are offered by another equally simple circuit based on carry save redundant numbers and 3 2 counters this alternative circuit has other potential applications and much of it may in fact be already present in some alu s

high speed vlsi multiplication algorithm with a redundant binary addition tree a high speed vlsi multiplication algorithm internally using redundant binary representation is proposed in n bit binary integer multiplication n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders since parallel addition of two n digit redundant binary numbers can be performed in a constant time independent of n without carry propagation n bit multiplication can be performed in a time proportional to log2 n the computation time is almost the same as that by a multiplier with a wallace tree in which three partial products will be converted into two in contrast to our two to one conversion and is much shorter than that by an array multiplier for longer operands the number of computation elements of an n bit multiplier based on the algorithm is proportional to n2 it is almost the same as those of conventional ones furthermore since the multiplier has a regular cellular array structure similar to an array multiplier it is suitable for vlsi implementation thus the multiplier is excellent in both computation speed and regularity in layout it can be implemented on a vlsi chip with an area proportional to n2 log2 n the algorithm can be directly applied to both unsigned and 2 s complement binary integer multiplication

new efficient structure for a modular multiplier for rns modular multiplication is a very important arithmetic operation in residue based real time computing systems in realizing these multipliers rom based structures are more efficient for small moduli due to the exponential growth of rom sizes implementations with arithmetic components are more suitable for medium and large moduli this paper presents a new modular multiplier that can deal efficiently with medium and large size moduli the design of this modular multiplier that multiplies two n bit residue digits consists basically of a n spl times n binary multiplier a n 1 k spl times k binary multiplier k n three n bit adders and a small size combinational circuit when compared with the most competitive published work the new multiplier reduces significantly both time delay and hardware requirements the design is very suitable for vlsi realization

generalized signed digit number systems a unifying framework for redundant number representations signed digit sd number representation systems have been defined for any radix r or 3 with digit values ranging over the set alpha 1 0 1 alpha where alpha is an arbitrary integer in the range 1 2r

comments on on adaptive inverse dynamics control of rigid robots with reply the commenters point out an error in the adaptive control approach for robotic manipulators given in the above named work by m w spong and r ortega see ibid vol 35 p 92 5 jan 1990 it is noted that the authors assert that their adaptive control scheme eliminates the restriction given in j j craig 1986 on the estimated inertia matrix however the commenters point out that a form of the inverse of the estimated inertia matrix must be bounded for the acceleration to be bounded in a reply the authors acknowledge the error in their paper

brief paper adaptive inverse dynamics control of robots with uncertain kinematics and dynamics it has been about two decades since the first globally convergent adaptive tracking controller was derived for robots with dynamic uncertainties however not until recently has the problem of concurrent adaptation to both the kinematic and dynamic uncertainties found its solution this adaptive controller belongs to passivity based control though passivity based controllers have many attractive properties in general they are not able to guarantee the uniform performance of the robot over the entire workspace even in the ideal case of perfect knowledge of the manipulator parameters the closed loop system remains nonlinear and coupled thus the closed loop tracking performance is difficult to quantify while the inverse dynamics controllers can overcome these deficiencies therefore in this work we will develop a new adaptive jacobian tracking controller based on the inverse manipulator dynamics using the lyapunov approach we have proved that the end effector motion tracking errors converge asymptotically to zero simulation results are presented to show the performance of the proposed controller

double step branching cordic a new algorithm for fast sine and cosine generation duprat and muller 1993 introduced the ingenious branching cordic algorithm it enables a fast implementation of cordic algorithm using signed digits and requires a constant normalization factor the speedup is achieved by performing two basic cordic rotations in parallel in two separate modules in their method both modules perform identical computation except when the algorithm is in a branching 1 we have improved the algorithm and show that it is possible to perform two circular mode rotations in a single step with little additional hardware in our method both modules perform distinct computations at each step which leads to a better utilization of the hardware and the possibility of further speedup over the original method architectures for vlsi implementation of our algorithm are discussed

a new symbolic substitution based addition algorithm symbolic substitution a parallel processing technique has been proposed in computing literature to perform fast carry free addition of numbers several algorithms and corresponding symbolic substitution tables have been developed for addition of two numbers represented in binary modified signed digit msd and canonical modified signed digit cmsd number systems in this paper however we present a new symbolic substitution based algorithm and corresponding substitution table for the addition of two numbers represented in canonical modified signed digit cmsd notation in contrast with the existing algorithm in this regard that derives the addition result in msd system our algorithm derives the result in cmsd notation and thus it could be employed to perform symbolic substitution based associative addition of a set of cmsd numbers

fault localization error correction and graceful degradation in radix 2 signed digit based adders in this paper a methodology for the development of fault tolerant adders based on the radix 2 signed digit sd representation is presented the use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection fault localization and repair errors caused by faults belonging to a considered stuck at fault set can be detected by a parity based technique in fact a carry free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker regarding fault localization the carry free property of the adder ensures the confinement of the error due to a permanent fault to only few digits the detection of the faulty digit has been obtained by using a recomputation with shifted operands method finally after the fault localization graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures the first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output while the second one is based on a reduced dynamic range approach which allows us to obtain the result in only one step but with fewer output digits

constant time addition and simultaneous format conversion based on redundant binary representations it is well known that constant time addition in which the execution delay is independent of operand lengths is feasible only if the output is expressed in a redundant representation there are many ways of introducing redundancy and the specifics of the redundant format employed can have a major impact on the performance of constant time addition and digit set conversion this paper presents a comprehensive analysis of constant time addition and simultaneous format conversion we consider full as well as partially redundant representations where not all digit positions are redundant the number of redundant digits and their positions can be arbitrary yielding many possible redundant representations format conversion refers to changing the number and or position of redundant digits in a representation it is shown that such a format conversion is feasible during ie simultaneous with constant time addition even if all three operands the two inputs and single output are represented in distinct redundant formats we exploit equal weight grouping ewg wherein bits having the same weight are grouped together to achieve the constant time addition and possible simultaneous format conversion the analysis and data show that ewg leads to efficient implementations we compare vlsi implementations of various constant time addition cells and demonstrate that the conventional 4 2 compressor is the most efficient way to execute constant time addition we show interesting connections to prior results and indicate possible directions for further extensions

a modified partial product generator for redundant binary multipliers due to its high modularity and carry free addition a redundant binary rb representation can be used when designing high performance multipliers the conventional rb multiplier requires an additional rb partial product rbpp row because an error correcting word ecw is generated by both the radix 4 modified booth encoding mbe and the rb encoding this incurs in an additional rbpp accumulation stage for the mbe multiplier in this paper a new rb modified partial product generator rbmppg is proposed it removes the extra ecw and hence it saves one rbpp accumulation stage therefore the proposed rbmppg generates fewer partial product rows than a conventional rb mbe multiplier simulation results show that the proposed rbmppg based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits these reductions over previous nb multiplier designs incur in a modest delay increase approximately 5 percent the power delay product can be reduced by up to 59 percent using the proposed rb multipliers when compared with existing rb multipliers

optimal left to right binary signed digit recoding this paper describes new methods for producing optimal binary signed digit representations this can be useful in the fast computation of exponentiations contrary to existing algorithms the digits are scanned from left to right i e from the most significant position to the least significant position this may lead to better performances in both hardware and software

sparse iteration 4d cordic algorithms for multiplying quaternions novel 4d cordic algorithms and hardware architecture for multiplying quaternions are presented aimed at constant coefficient multipliers in our solution microrotations are multiplications by hypercomplex numbers with only one non zero imaginary part such transformations can be described using sparse matrices and implemented using less hardware resources than the iteration of the known quaternion cordic algorithm chip area can be saved because sparse microrotations can be computed using a permutation network and two operand adders without four operand additions which are necessary in the known solution the obtainable area savings depend on the implementation technology and the architectures of adders and bit shifters but can be as large as 45 and 25 percent for asic and fpga circuits respectively the circuitry simplifications come at the cost of slowing down computations our approach improves the area delay product and a single sparse iteration can be executed up to 15 percent faster than the conventional one but more microrotations are usually necessary to achieve the required accuracy on the other hand a sparse 4d iteration can be identified with microrotations of two 2d cordics which work in parallel this makes convergence analysis easier than in the previous 4d solution as it is sufficient to consider only two dimensions

certain discrete dynamical systems number systems and related integral self affine sets we consider certain discrete dynamical systems conventional number systems and redundant number systems for z 2 which are associated with certain 2x2 integral expansive matrices and collinear digit sets for them using integral self affine sets in r n we also give a geometric characterization to attractors of certain discrete dynamical systems and associated redundant number systems for z n

the hilbert function of generic plane sections of curves of ℙ3 a characteristic condition is given on a zero dimensional differentiable 0 sequenceh hi i 0 h1 3 in order to be the hilbert function of a generic plane section of a reduced irreducible curve of 3 hence of points of 2 with the uniform position property in this way an answer is given to some question stated by harris in ha2

high radix multiplier dividers theory design and hardware this paper describes the theory and design of digital high radix multiplier dividers patent pending the theory of high radix division is extended to high radix multiplier dividers that can perform fused multiplication and division operations using a single recurrence relation with the fused implementation of multiplication and division the two operations can be executed using a single instruction implying only a single rounding operation the recurrence relation is described the quotient digit selection function derived and important design parameters together with their optimal values and relations are defined efficient design procedure and implementation hardware are described and important system parameter values for various radix systems computed compared to pure dividers the multiplier divider requires a slightly more complex data path and quotient digit selection function

reviewing high radix signed digit adders higher radix values of the form beta 2 r have been employed traditionally for recoding of multipliers and for determining quotient and root digits in iterative division and square root algorithms usually only for quite moderate values of r like 2 or 3 for fast additions in particular for the accumulation of many terms generally redundant representations are employed most often binary carry save or borrow save but in a number of publications it has been suggested to recode the addends into a higher radix it is shown that there are no speed advantages in doing so if the radix is a power of 2 on the contrary there are significant savings in using standard 4 to 2 adders even saving half of the operations in multi operand addition

hybrid signed digit number systems a unified framework for redundant number representations with bounded carry propagation chains a novel hybrid number representation is proposed it includes the two s complement representation and the signed digit representation as special cases the hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length the framework reveals a continuum of number representations between the two extremes of two s complement and signed digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders multipliers and alike we present several static cmos implementations of a two operand adder which employ the proposed representations we then derive quantitative estimates of area in terms of the required number of transistors and the maximum carry propagation delay for such an adder the analysis clearly illustrates the trade offs between area and execution time associated with each of the possible representations we also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times in practice the area available to a designer is often limited in such cases the designer can select the particular hybrid representation that yields the most suitable implementation fastest lowest power consumption etc while satisfying the area constraint similarly if the worst case delay is predetermined the designer can select a hybrid representation that minimizes area or power under the delay constraint

signed binary addition circuitry with inherent even parity outputs a signed binary se addition circuit is presented that always produces an even parity representation of the sum word the novelty of this design is that no extra check bits are generated or used the redundancy inherent in a se representation is further exploited to contain parity information

multiplexer based array multipliers a new algorithm for the multiplication of two n bit numbers based on the synchronous computation of the partial sums of the two operands is presented the proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays at the same time it permits high speed operation multiplier arrays for positive numbers and numbers in two s complement form based on the proposed technique are implemented also an efficient pipeline form of the proposed multiplication scheme is introduced all multipliers obtained have low circuit complexity permitting high speed operation and the interconnections of the cells are regular well suited for vlsi realization

prediction error based adaptive jacobian tracking of robots with uncertain kinematics and dynamics in this note we have proposed a prediction error based adaptive jacobian controller to solve the problem of concurrent adaptation to both uncertain kinematics and dynamics this controller is composed of a modified computed torque controller and two cushion floor least square estimators and in ideal case of perfect knowledge of the robot parameters it leads to linear and decoupled error dynamics the kinematic and dynamic parameters adaptations are driven by prediction errors using input output stability analysis we show that the end effector motion tracking errors converge asymptotically we have also derived an alternative adaptive jacobian controller that does not require the invertibility of the estimated inertia matrix simulation results are presented to show the performance of the proposed controllers

carry free addition of recoded binary signed digit numbers signed digital number representation systems have been defined for any radix r or 3 with digit values ranging over the set alpha 1 0 1 alpha where alpha is an arbitrary integer in the range r 2

uniform position properties and hilbert functions for points on a smooth quadric abstract if x is a set of points of p3 with the uniform position property we study the structure of the hilbert function of x with special care in the case when x lies on a smooth quadric q in this particular situation we also investigate the behaviour of the hilbert matrix of x when the uniform position property is enlarged to the divisors of q

on line error detectable high speed multiplier using redundant binary representation and three rail logic an on line error detectable high speed multiplier is described it is based on the multiplication algorithm which we have previously proposed in the algorithm the redundant binary representation each of whose digits is 0 1 or 1 is used the multiplier consists of an input encoder a multiplication block and an error checker the input encoder encodes each primary input bit into the 1 out of 2 code the multiplication block is designed by means of the three rail logic the three rail logic is a logic design technique in which three mutually exclusive conditions calculated in a circuit are encoded in 1 out of 3 code and the circuit is designed to be inverter free the error checker is a totally self checking two rail checker and produces a bit pair as an error indicator the multiplier can perform n bit multiplication in a time proportional to log 2 n and has a regular cellular array structure suitable for vlsi implementation furthermore we can detect any error caused by unidirectional stuck at faults on gate output lines in normal operation by observing the error indicator many errors caused by other faults can be also detected we can develop various on line error detectable high speed arithmetic circuits using the redundant binary representation and the three rail logic

high speed area efficient multiplier design using multiple valued current mode circuits presents a very large scale integration vlsi oriented high speed multiplier design method based on carry propagation free addition trees and a circuit technique so called multiple valued current mode mvcm circuits the carry propagation free addition method uses a redundant digit set such as spl lcub 0 1 2 3 spl rcub and spl lcub 0 1 2 3 4 spl rcub the number representations using such redundant digit sets are called redundant positive digit number representations the carry propagation free addition is written by three steps and the adder can be designed directly and efficiently from the algorithm using mvcm circuits the designed multiplier internally using the mvcm parallel adder with the digit set spl lcub 0 1 2 3 spl rcub in radix 2 has attractive features on speed regularity of the structure and reduced complexities of active elements and interconnections a prototype cmos integrated circuit of the mvcm parallel adder has been implemented and its stable operation has been confirmed other possible schemes of multipliers with redundant digit sets using mvcm technology are discussed

on the distribution of runs of ones in binary strings in this paper we derive the number of binary strings which contain for a given i k exactly i k runs of 1 s of length k in all possible binary strings of length n email protected email protected n such a knowledge about the distribution pattern of runs of 1 s in binary strings is useful in many engineering applications for example data compression bus encoding techniques to reduce crosstalk in vlsi chip design computer arithmetic using redundant binary number system and design of energy efficient communication schemes in wireless sensor networks by transformation of runs of 1 s into compressed information patterns among others we present here a generating function based approach to derive a solution to this counting problem our experimental results demonstrate that for most commonly used file formats the observed distributions of exactly i k runs of length k email protected email protected n closely follow the theoretically derived distributions for a given n for n 8 we find that the experimentally obtained values for most file formats agree within 5 of the theoretically obtained values for all i k runs of length k email protected email protected n also the root mean square rms values of these deviations across all file types studied in this paper are less than 5 for n 8 in view of these facts the results presented in this paper could be useful in various application domains like the ones mentioned above

comments on duprat and muller s branching cordic paper duprat and muller ieee trans computers vo1 42 no 2 p 168 178 feb 1993 introduced the ingenious branching cordic algorithm it enables a fast implementation of cordic algorithm using signed digits and requires a constant normalization factor this correspondence corrects some errors in the original paper

geometric consequences of extremal behavior in a theorem of macaulay f s macaulay gave necessary and sufficient conditions on the growth of a nonnegative integer valued function which determine when such a function can be the hilbert function of a standard graded k algebra we investigate some algebraic and geometric consequences which arise from the extremal cases of macaulay s theorem our work also builds on the fundamental work of g gotzmann our principal applications are to the study of hilbert functions of zeroschemes with uniformity conditions as a consequence we have new strong limitations on the possible hilbert functions of the points which arise as a general hyperplane section of an irreducible curve