an efficient optimal normal basis type ii multiplier this paper presents a new parallel multiplier for the galois field gf 2 sup m whose elements are represented using the optimal normal basis of type ii the proposed multiplier requires 1 5 m sup 2 m xor gates as compared to 2 m sup 2 m xor gates required by the massey omura multiplier the time complexities of the proposed and the massey omura multipliers are similar

mastrovito form of non recursive karatsuba multiplier for all trinomials we present a new type of bit parallel non recursive karatsuba multiplier over gf 2 m generated by an arbitrary irreducible trinomial this design effectively exploits mastrovito approach and shifted polynomial basis spb to reduce the time complexity and karatsuba algorithm to reduce its space complexity we show that this type of multiplier is only one t x slower than the fastest bit parallel multiplier for all trinomials where t x is the delay of one 2 input xor gate meanwhile its space complexity is roughly 3 4 of those multipliers to the best of our knowledge it is the first time that our scheme has reached such a time delay bound this result outperforms previously proposed non recursive karatsuba multipliers

the montgomery inverse and its applications the montgomery inverse of b module a is b sup 1 2 sup n mod a where n is the number of bits in a the right shifting binary algorithm for modular inversion is shown naturally to compute the new inverse in fewer operations than the ordinary modular inverse the new inverse facilitates recent work by koc on modular exponentiation and has other applications in cryptography

automata and the susceptibility of the square lattice ising model modulo powers of primes we study the full susceptibility of the ising model modulo powers of primes we find exact functional equations for the full susceptibility modulo these primes revisiting some lesser known results on discrete finite automata we show that these results can be seen as a consequence of the fact that modulo 2 r one cannot distinguish the full susceptibility from some simple diagonals of rational functions which reduce to algebraic functions modulo 2 r and consequently satisfy exact functional equations modulo 2 r we sketch a possible physical interpretation of these functional equations modulo 2 r as reductions of a master functional equation corresponding to infinite order symmetries such as the isogenies of elliptic curves one relevant example is the landen transformation which can be seen as an exact generator of the ising model renormalization group we underline the importance of studying a new class of functions corresponding to ratios of diagonals of rational functions they reduce to algebraic functions modulo powers of primes and they may have solutions with natural boundaries

low complexity bit parallel canonical and normal basis multipliers for a class of finite fields we present a new low complexity bit parallel canonical basis multiplier for the field gf 2m generated by an all one polynomial the proposed canonical basis multiplier requires m sup 2 1 xor gates and m sup 2 and gates we also extend this canonical basis multiplier to obtain a new bit parallel normal basis multiplier

new low complexity bit parallel finite field multipliers using weakly dual bases new structures of bit parallel weakly dual basis wdb multipliers over the binary ground field are proposed an upper bound on the size complexity of bit parallel multiplier using an arbitrary generating polynomial is given when the generating polynomial is an irreducible trinomial x sup m x sup k 1 1 spl les k spl les m 2 the structure of the proposed bit parallel multiplier requires only m sup 2 two input and gates and at most m sup 2 1 xor gates the time delay is no greater than t sub a log sub 2 m 2 t sub x where t sub a and t sub x are the time delays of an and gate and an xor gate respectively

low complexity bit parallel systolic montgomery multipliers for special classes of gf 2 sup m recently cryptographic applications based on finite fields have attracted much interest this paper presents a transformation method to implement low complexity montgomery multipliers for all one polynomials and trinomials using this method we propose a new bit parallel systolic architecture for computing multiplications over gf 2 sup m these new multipliers have a latency m 1 clock cycles and each cell incorporates at most one 2 input and gate two 2 input xor gates and four 1 bit latches moreover these new multipliers are shown to exhibit significantly lower latency and circuit complexity than the related systolic multipliers and are highly appropriate for vlsi systems because of their regular interconnection pattern modular structure and fully inherent parallelism

sharp bounds for the signless laplacian spectral radius of digraphs abstract let g v e be a digraph with n vertices and m arcs without loops and multiarcs and vertex set v v 1 v 2 v n denote the outdegree and average 2 outdegree of the vertex v i by d i and m i respectively let a g be the adjacency matrix and d g diag d 1 d 2 d n be the diagonal matrix with outdegree of the vertices of the digraph g then we call q g d g a g the signless laplacian matrix of g let q g denote the signless laplacian spectral radius of the digraph g in this paper we present several improved bounds in terms of outdegree and average 2 outdegree for the signless laplacian spectral radius of digraphs then we give an example to compare the bounds

the montgomery modular inverse revisited we modify an algorithm given by kaliski to compute the montgomery inverse of an integer modulo a prime number we also give a new definition of the montgomery inverse and introduce efficient algorithms for computing the classical modular inverse the kaliski montgomery inverse and the new montgomery inverse the proposed algorithms are suitable for software implementations on general purpose microprocessors

montgomery multiplier and squarer for a class of finite fields montgomery multiplication in gf 2 sup m is defined by a x b x r sup 1 x mod f x where the field is generated by a root of the irreducible polynomial f x a x and b x are two field elements in gf 2 sup m and r x is a fixed field element in gf 2 sup m in this paper first a slightly generalized montgomery multiplication algorithm in gf 2 sup m is presented then by choosing r x according to f x we show that efficient architectures of bit parallel montgomery multiplier and squarer can be obtained for the fields generated with an irreducible trinomial complexities of the montgomery multiplier and squarer in terms of gate counts and time delay of the circuits are investigated and found to be as good as or better than that of previous proposals for the same class of fields

bit serial and bit parallel montgomery multiplication and squaring over gf 2 m multiplication and squaring are main finite field operations in cryptographic computations and designing efficient multipliers and squarers affect the performance of cryptosystems in this paper we consider the montgomery multiplication in the binary extension fields and study different structures of bit serial and bit parallel multipliers for each of these structures we study the role of the montgomery factor and then by using appropriate factors propose new architectures specifically we propose two bit serial multipliers for general irreducible polynomials and then derive bit parallel montgomery multipliers for two important classes of irreducible polynomials in this regard first we consider trinomials and provide a way for finding efficient montgomery factors which results in a low time complexity then we consider type ii irreducible pentanomials and design two bit parallel multipliers which are comparable to the best finite field multipliers reported in the literature moreover we consider squaring using this family of irreducible polynomials and show that this operation can be performed very fast with the time complexity of two xor gates

bipartite modular multiplication method this paper proposes a new modular multiplication method that uses montgomery residues defined by a modulus m and a montgomery radix r whose value is less than the modulus m this condition enables the operand multiplier to be split into two parts that can be processed separately in parallel increasing the calculation speed the upper part of the split multiplier can be processed by calculating a product modulo m of the multiplicand and this part of the split multiplier the lower part of the split multiplier can be processed by calculating a product modulo m of the multiplicand this part of the split multiplier and the inverse of a constant r two different implementations based on this method are proposed one uses a classical modular multiplier and a montgomery multiplier and the other generates partial products for each part of the split multiplier separately which are added and accumulated in a single pipelined unit a radix 4 version of a multiplier based on a radix 4 classical modular multiplier and a radix 4 montgomery multiplier has been designed and simulated the proposed method is also suitable for software implementation in a multiprocessor environment

a scalable dual field elliptic curve cryptographic processor we propose an elliptic curve ec cryptographic processor architecture that can support galois fields gf p and gf 2 sup n for arbitrary prime numbers and irreducible polynomials by introducing a dual field multiplier a montgomery multiplier with an optimized data bus and an on the fly redundant binary converter boost the throughput of the ec scalar multiplication all popular cryptographic functions such as dsa ec dsa rsa crt and prime generation are also supported all commands are organized in a hierarchical structure according to their complexity our processor has high scalability and flexibility between speed hardware area and operand size in the hardware evaluation using a 0 13 spl mu m cmos standard cell library the high speed design using 117 5 kgates with a 64 bit multiplier achieved operation times of 1 21 ms and 0 19 ms for a 160 bit ec scalar multiplication in gf p and gf 2 sup n respectively a compact version with an 8 bit multiplier requires only 28 3 k gates and executes the operations in 7 47 ms and 2 79 ms not only 160 bit operations but any bit length can be supported by any hardware configuration so long as the memory capacity is sufficient

sharp bounds for the spectral radius of digraphs abstract let g v e be a digraph with n vertices and m arcs without loops and multiarcs the spectral radius g of g is the largest eigenvalue of its adjacency matrix in this paper the following sharp bounds on g have been obtained min t i t j v i v j e g max t i t j v i v j e where g is strongly connected and t i is the average 2 outdegree of vertex v i moreover each equality holds if and only if g is average 2 outdegree regular or average 2 outdegree semiregular

programmable cellular automata based montgomery hardware architecture abstract this study presents efficient hardware architectures for montgomery multiplication and squaring based on programmable cellular automata pca multiplication and squaring are the key operation in implementing circuits for various applications of error control coding such as reed solomon code thus we employ montgomery multiplication and squaring algorithms and construct simple hardware architectures based on pca in gf 2 m our architectures are highly optimized and have low complexity based on irreducible all one polynomial aop

vlsi architectures for computing multiplications and inverses in gf 2 m finite field arithmetic logic is central in the implementation of reed solomon coders and in some cryptographic algorithms there is a need for good multiplication and inversion algorithms that can be easily realized on vlsi chips massey and omura 1 recently developed a new multiplication algorithm for galois fields based on a normal basis representation in this paper a pipeline structure is developed to realize the massey omura multiplier in the finite field gf 2m with the simple squaring property of the normal basis representation used together with this multiplier a pipeline architecture is also developed for computing inverse elements in gf 2m the designs developed for the massey omura multiplier and the computation of inverse elements are regular simple expandable and therefore naturally suitable for vlsi implementation

efficient multiplier architectures for galois fields gf 2 sup 4n this contribution introduces a new class of multipliers for finite fields gf 2 sup n sup 4 the architecture is based on a modified version of the karatsuba ofman algorithm koa by determining optimized field polynomials of degree four the last stage of the koa and the module reduction can be combined this saves computation and area in vlsi implementations the new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with koa based architectures with separate module reduction the new multipliers lead to highly modular architectures and are thus well suited for vlsi implementations three types of field polynomials are introduced and conditions for their existence are established for the small fields where n 2 3 8 which are of primary technical interest optimized field polynomials were determined by an exhaustive search for each field order exact space and time complexities are provided

mastrovito multiplier for all trinomials an efficient algorithm for the multiplication in gf 2 sup m was introduced by mastrovito the space complexity of the mastrovito multiplier for the irreducible trinomial x sup m x 1 was given as m sup 2 1 xor and m sup 2 and gales in this paper we describe an architecture based on a new formulation of the multiplication matrix and show that the mastrovito multiplier for the generating trinomial x sup m x sup n 1 where m spl ne 2n also requires m sup 2 1 xor and m sup 2 and gates however m sup 2 x sup m 2 xor gates are sufficient when the generating trinomial is of the form x sup m x sup m 2 1 for an even m we also calculate the time complexity of the proposed mastrovito multiplier and give design examples for the irreducible trinomials x sup 7 x sup 4 1 and x sup 6 x sup 3 1

fast bit parallel gf 2 sup n multiplier for all trinomials based on a new representation of gf 2 sup n we present two multipliers for all irreducible trinomials space complexities of the multipliers match the best results the time complexity of one multiplier is t sub a 1 log sub 2 n t sub x for all irreducible trinomials where t sub a and t sub x are the delay of one 2 input and and xor gates respectively

concurrent error detection in montgomery multiplication over binary extension fields multiplication is one of the most important operations in finite field arithmetic it is used in cryptographic and coding applications such as elliptic curve cryptography and reed solomon codes in this paper we consider the finite field multiplication used in elliptic curve cryptography and design concurrent error detection circuits it is shown in the literature that the montgomery multiplication can be used in cryptography to accelerate the scalar multiplication here we use a parity based concurrent error detection approach to increase the reliability of different montgomery multipliers available in the literature first we consider bit serial montgomery multiplication and propose an error detection circuit then we apply the same technique on the digit serial montgomery multiplication finally we consider low time complexity bit parallel montgomery multiplication and design the required components to implement the concurrent error detection circuits asic implementations have been completed to analyze the time and area overheads of the proposed schemes also the error detection capability is investigated by software simulations we show that our approach results in efficient error detection schemes with small time and area overheads

modular construction of low complexity parallel multipliers for a class of finite fields gf 2 sup m structures for parallel multipliers of a class of fields gf 2 sup m based on irreducible all one polynomials aop and equally spaced polynomials esp are presented the structures are simple and modular which is important for hardware realization relationships between an irreducible aop and the corresponding irreducible esps have been exploited to construct esp based multipliers of large fields by a regular expansion of the basic modules of the aop based multiplier of a small field some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible it is shown that if for a certain degree an irreducible aop as well as an irreducible esp exist then from the complexity point of view it is advantageous to use the esp based parallel multiplier

relationship between gf 2 m montgomery and shifted polynomial basis multiplication algorithms applying the matrix vector product idea of the mastrovito multiplier to the gf 2m montgomery multiplication algorithm we present a new parallel multiplier for irreducible trinomials this multiplier and the corresponding shifted polynomial basis spb multiplier have the same circuit structure for the same set of parameters furthermore by establishing isomorphisms between the montgomery and the spb constructions of gf 2m we show that the montgomery algorithm can be used to perform the spb multiplication without any changes and vice versa

modular multiplication without trial division let n 1 we present a method for multiplying two integers called n residues modulo n while avoiding division by n n residues are represented in a nonstandard way so this method is useful only if several computations are done modulo one n the addition and subtraction algorithms are unchanged 1 description some algorithms 1 2 4 5 require extensive modular arith metic we propose a representation of residue classes so as to speed modular multiplication without affecting the modular addition and subtraction algorithms other recent algorithms for modular arithmetic appear in 3 6 fix n 1 define an a residue to be a residue class modulo n select a radix r coprime to n possibly the machine word size or a power thereof such that r n and such that computations modulo r are inexpensive to process let r l and n be integers satisfying 0 n then return t n else return t to validate redc observe mn tn n tmod r so t is an integer also tr tmod n so t tr x mod n thirdly 0 t mn rn rn so 0 t 2n if r and n are large then t mn may exceed the largest double precision value one can circumvent this by adjusting m so r m 0 given two numbers x and y between 0 and n 1 inclusive let z redc xy then z xy r x mod n so xr l yr x zrx mod n also 0 z n so z is the product of x and y in this representation other algorithms for operating on n residues in this representation can be derived from the algorithms normally used the addition algorithm is unchanged since xr x yr x zr x mod n if and only if x y z mod n also unchanged are