bkm a new hardware algorithm for complex elementary functions a new algorithm for computing the complex logarithm and exponential functions is proposed this algorithm is based on shift and add elementary steps and it generalizes some algorithms by briggs and de lugish 1970 as well as the cordic algorithm it can easily be used to compute the classical real elementary functions sin cos arctan ln exp this algorithm is more suitable for computations in a redundant number system than the cordic algorithm since there is no scaling factor when computing trigonometric functions

powering by a table look up and a multiplication with operand modification an efficient method for generating a power of an operand i e x sup p for an operand x and a given p is proposed it is applicable to ps in the form of spl plusmn 2 sup k where k is any integer and of spl plusmn 2 k sub 1 spl plusmn 2 k sub 2 where k sub 1 is any integer and k sub 2 is any nonnegative integer the reciprocal the square root the reciprocal square root the reciprocal square the reciprocal cube and so forth are included the method is a modification of the piecewise linear approximation a power of an operand is generated through a table look up and a multiplication with operand modification the same accuracy is achieved as the piecewise linear approximation the multiplication and an addition required for the piecewise linear approximation are replaced by only one double sized multiplication with a slight modification of the operand and hence one clock cycle may be reduced the required table size is reduced because only one coefficient instead of two has to be stored

design of a radix 4 division unit with simple selection table a radix 4 division architecture is presented which partially overlaps the updating of the remainder with the digit selection procedure it is obtained by separating the radix 4 digit selection process into two concurrent substeps the proposed unit requires a simple selection table and involves a small extra expense for the additional hardware compared to the usual radix 4 division units four possible implementations are derived from the general model with different types of substeps the high level evaluation shows that the proposed architectures offer an efficient alternative

division using a logarithmic exponential transform to form a short reciprocal two trees are used sequentially to calculate an approximation to 1 a where 1 a 2 these trees calculate the logarithm and exponential and the division reciprocation process can be described by 1 a e lna for bit skip accuracy of six to 10 this logarithmic exponential method uses significantly less hardware with respect to the scheme in 3 and the delays may be greater or less than those of 3 depending on the method used and the minimum bit skip

high speed double precision computation of reciprocal division square root and inverse square root a new method for the high speed computation of double precision floating point reciprocal division square root and inverse square root operations is presented in this paper this method employs a second degree minimax polynomial approximation to obtain an accurate initial estimate of the reciprocal and the inverse square root values and then performs a modified goldschmidt iteration the high accuracy of the initial approximation allows us to obtain double precision results by computing a single goldschmidt iteration significantly reducing the latency of the algorithm two unfolded architectures are proposed the first one computing only reciprocal and division operations and the second one also including the computation of square root and inverse square root the execution times and area costs for both architectures are estimated and a comparison with other multiplicative based methods is presented the results of this comparison show the achievement of a lower latency than these methods with similar hardware requirements

algorithm and architecture for logarithm exponential and powering computation an architecture for the computation of logarithm exponential and powering operations is presented in this paper based on a high radix composite algorithm for the computation of the powering function x sup y the algorithm consists of a sequence of overlapped operations 1 digit recurrence logarithm 2 left to right carry free lrcf multiplication and 3 online exponential a redundant number system is used and the selection in 1 and 3 is done by rounding except from the first iteration when selection by table look up is necessary to guarantee the convergence of the recurrences a sequential implementation of the algorithm with a control unit which allows the independent computation of logarithm and exponential is proposed and the execution times and hardware requirements are estimated for single and double precision floating point computations these estimates are obtained for radices from r 8 to r 1 024 according to an approximate model for the delay and area of the main logic blocks and help determining the radix values which lead to the most efficient implementations r 32 and r 128

convex relaxations of non convex mixed integer quadratically constrained programs extended formulations this paper addresses the problem of generating strong convex relaxations of mixed integer quadratically constrained programming miqcp problems miqcp problems are very difficult because they combine two kinds of non convexities integer variables and non convex quadratic constraints to produce strong relaxations of miqcp problems we use techniques from disjunctive programming and the lift and project methodology in particular we propose new methods for generating valid inequalities from the equation y x x t we use the non convex constraint y x x t preccurlyeq 0 to derive disjunctions of two types the first ones are directly derived from the eigenvectors of the matrix y x x t with positive eigenvalues the second type of disjunctions are obtained by combining several eigenvectors in order to minimize the width of the disjunction we also use the convex sdp constraint y x x t succcurlyeq 0 to derive convex quadratic cuts and we combine both approaches in a cutting plane algorithm we present computational results to illustrate our findings

computational difficulties of bilevel linear programming we show using small examples that two algorithms previously published for the bilevel linear programming problem blp may fail to find the optimal solution and thus must be considered to be heuristics a proof is given that solving blp problems is np hard which makes it unlikely that there is a good exact algorithm

square rooting algorithms for integer and floating point numbers an algorithm for evaluating the square root of integers and real numbers is developed the procedure consists of two parts one to obtain a close estimate of the square root and the other to modify the initial value iteratively until a precise root is evaluated the major effort in this development has been concentrated on two objectives high speed and no division operation other than division by 2 the first objective is achieved through a simple two step procedure for getting the first estimate and then modifying it by employing a fast converging iteration technique the second objective is also fulfilled through applying bit shift operation rather than division operation the algorithm is simulated for both integer and real numbers and the results are compared to two methods being widely used the results tabulated show considerable improvement in speed compared to these other two methods

a fast radix 4 division algorithm and its architecture in this paper we present a fast radix 4 division algorithm for floating point numbers this method is based on svoboda s division algorithm and the radix 4 redundant number system the algorithm involves a simple recurrence with carry free addition and employs prescaling of the operands in the proposed divider implementation each radix 4 digit belonging to set 3 3 of the quotient and partial remainder is encoded using two radix 2 digits belonging to the set 1 0 1 and this leads to hardware simplicity the quotient digits are determined by observing three most significant radix 2 digits of the partial remainder and independent of the divisor the architecture presented for the proposed algorithm is faster than previously proposed radix 4 dividers which require at least four digits of the partial remainder to be observed to determine quotient digits

very high radix division with prescaling and selection by rounding a division algorithm in which the quotient digit selection is performed by rounding the shifted residual in carry save form is presented to allow the use of this simple function the divisor and dividend is prescaled to a range close to one the implementation presented results in a fast iteration because of the use of carry save forms and suitable recodings the execution time is calculated and several convenient values of the radix are selected comparison with other dividers for radices 2 sup 9 to 2 sup 18 is performed using the same assumptions

statistical properties of the volatility of price fluctuations we study the statistical properties of volatility measured by locally averaging over a time window t the absolute value of price changes over a short time interval ensuremath delta t we analyze the s 500 stock index for the 13 year period jan 1984 to dec 1996 we find that the cumulative distribution of the volatility is consistent with a power law asymptotic behavior characterized by an exponent ensuremath mu ensuremath approx 3 similar to what is found for the distribution of price changes the volatility distribution retains the same functional form for a range of values of t further we study the volatility correlations by using the power spectrum analysis both methods support a power law decay of the correlation function and give consistent estimates of the relevant scaling exponents also both methods show the presence of a crossover at approximately 1 5 days in addition we extend these results to the volatility of individual companies by analyzing a data base comprising all trades for the largest 500 u s companies over the two year period jan 1994 to dec 1995

low latency floating point division and square root unit digit recurrence algorithms are widely used in actual microprocessors to compute floating point division and square root these iterative algorithms present a good trade off in terms of performance area and power we present a floating point division and square root unit which implements a radix 64 floating point division and a radix 16 floating point square root to have an affordable implementation each radix 64 division iteration and radix 16 square root iteration are made of simpler radix 4 iterations 3 radix 4 iterations in division and 2 in square root speculation is used between consecutive radix 4 iterations to get a reduced timing there are three different parts in digit recurrence implementations initialization digit iterations and rounding the digit iteration is the iterative part and it uses the same logic for several cycles division and square root share partially the initialization and rounding stages whereas each one has different logic for the digit iterations the result is a low latency floating point divider and square root requiring 11 6 and 4 cycles for double single and half precision division with normalized operands and result and 15 8 and 5 cycles for square root one or two additional cycles are needed in case of subnormal operand s or result

joint optimization of product family configuration and scaling design by stackelberg game abstract product family design is generally characterized by two types of approaches module based and scale based while the former aims to enable product variety based on module configuration the latter is to variegate product design by scaling up or down certain design parameters the prevailing practice is to treat module configuration and scaling design as separate decisions or aggregate two design problems as a single level all in one optimization problem in practice optimization of scaling variables is always enacted within a specific modular platform and meanwhile an optimal module configuration depends on how design parameters are to be scaled the key challenge is how to deal with explicitly the coupling of these two design optimization problems this paper formulates a stackelberg game theoretic model for joint optimization of product family configuration and scaling design in which a bilevel decision structure reveals coupled decision making between module configuration and parameter scaling a bilevel mixed 0 1 non linear programming model is developed and solved comprising an upper level optimization problem and a lower level optimization problem the upper level seeks for an optimal configuration of modules and module attributes by maximizing the shared surplus of an entire product family the lower level entails parametric optimization of attribute values for optimal technical performance of each individual module a case study of electric motors demonstrates that the bilevel joint optimization model excels in leveraging optimal scaling in conjunction with optimal module configuration which is advantageous over the existing paradigm of product family scaling design that cannot change the product family configuration

some results on a srt type division scheme a variation of a division method previously presented by the author 1990 is described the method is of the srt type this present scheme is based upon a system of recursion equations derived from the equation 1 a q its advantages are presented

a computational study for bilevel quadratic programs using semidefinite relaxations abstract in this paper we deal with bilevel quadratic programming problems with binary decision variables in the leader problem and convex quadratic programs in the follower problem for this purpose we transform the bilevel problems into equivalent quadratic single level formulations by replacing the follower problem with the equivalent karush kuhn tucker kkt conditions then we use the single level formulations to obtain mixed integer linear programming milp models and semidefinite programming sdp relaxations thus we compute optimal solutions and upper bounds using linear programming lp and sdp relaxations our numerical results indicate that the sdp relaxations are considerably tighter than the lp ones consequently the sdp relaxations allow finding tight feasible solutions for the problem especially when the number of variables in the leader problem is larger than in the follower problem moreover they are solved at a significantly lower computational cost for large scale instances

varieties of long memory models long memory is defined as a series having a slowly declining correlogram or equivalently an infinite spectrum at zero frequency fractional integrated processes have such properties but here it is pointed out that a number of other processes can also be long memory including generalized fractionally integrated models arising from aggregation time changing coefficient models and possibly nonlinear models it seems that there are many classes of processes that deserve further study the relevance of long memory is illustrated using absolute returns from a daily stock market index

salient features of dependence in daily us stock market indices abstract this paper deals with the analysis of long range dependence in the us stock market we focus first on the log values of the dow jones industrial average standard and poors 500 and nasdaq indices daily from february 1971 to february 2007 the volatility processes are examined based on the squared and the absolute values of the returns series and the stability of the parameters across time is also investigated in both the level and the volatility processes a method that permits us to estimate fractional differencing parameters in the context of structural breaks is conducted in this paper finally the day of the week effect is examined by looking at the order of integration for each day of the week providing also a new modeling approach to describe the dependence in this context

high radix multiplier dividers theory design and hardware this paper describes the theory and design of digital high radix multiplier dividers patent pending the theory of high radix division is extended to high radix multiplier dividers that can perform fused multiplication and division operations using a single recurrence relation with the fused implementation of multiplication and division the two operations can be executed using a single instruction implying only a single rounding operation the recurrence relation is described the quotient digit selection function derived and important design parameters together with their optimal values and relations are defined efficient design procedure and implementation hardware are described and important system parameter values for various radix systems computed compared to pure dividers the multiplier divider requires a slightly more complex data path and quotient digit selection function

efficient initial approximation for multiplicative division and square root by a multiplication with operand modification an efficient initial approximation method for multiplicative division and square root is proposed it is a modification of the piecewise linear approximation the multiplication and the addition required for the linear approximation are replaced by only one multiplication with a slight modification of the operand the same accuracy is achieved the modification of the operand requires only a bit wise inversion and a one bit shift and can be implemented by a very simple circuit one clock cycle may be saved because the addition is removed the required table size is also reduced because only one coefficient instead of two has to be stored

design of high speed digital divider units the division operation has proved to be a much more difficult function to generate efficiently than the other elementary arithmetic operations this is due primarily to the need to test the result of one iteration before proceeding to the next the technique described in this contribution reduces the iteration time by the use of a redundant quotient representation which avoids the need to complete the arithmetic operation a borrow save subtractor analogous to a carry save adder can then be used for the arithmetic further improvement is obtained by use of a lookahead decoding technique cost reductions are obtained either by use of uncommitted logic arrays or by a novel borrow save system using commercially available adder circuitry a comparison of a number of divider units with a wide range of cost and speed is included

square rooting algorithms for high speed digital circuits two binary algorithms for the square rooting of a number or of a sum of two numbers are presented they are based on the classical nonrestoring method the main difference lies in the replacement of subtractions and additions by a parallel reduction f three summands which may be positive and negative to two summands to eliminate the carry propagation two of three summands form the successive partial remainder their most significant bit triples sometimes together with a sign bit of the earlier partial remainder are used to determine digits 1 0 1 of a redundant square root notation these digits are transformed during the square rooting process into the conventional notation square root bits which are next used in further square rooting steps to form the third reduced summands

boosting very high radix division with prescaling and selection by rounding an extension of the very high radix division with prescaling and selection by rounding is presented this extension consists of increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration without increasing the complexity of the unit to obtain the prescaling factor or the delay of an iteration as a consequence for some values of the effective radix it permits an implementation with a smaller area and the same execution time of the original scheme details of the algorithm and the implementation are presented estimations of the execution time and area are given for 54 bit and 114 bit quotients and compared with those of other division units

improving goldschmidt division square root and square root reciprocal the aim of this paper is to accelerate division square root and square root reciprocal computations when the goldschmidt method is used on a pipelined multiplier this is done by replacing the last iteration by the addition of a correcting term that can be looked up during the early iterations we describe several variants of the goldschmidt algorithm assuming 4 cycle pipelined multiplier and discuss obtained number of cycles and error achieved extensions to other than 4 cycle multipliers are given if we call g sub m the goldschmidt algorithm with m iterations our variants allow us to reach an accuracy that is between that of g sub 3 and that of g sub 4 with a number of cycle equal to that of g sub 3

reciprocation square root inverse square root and some elementary functions using small multipliers this paper deals with the computation of reciprocals square roots inverse square roots and some elementary functions using small tables small multipliers and for some functions a final large almost full length multiplication we propose a method based on argument reduction and series expansion that allows fast evaluation of these functions in high precision the strength of this method is that the same scheme allows the computation of all these functions we estimate the delay the size number of tables and the size number of multipliers and compare with other related methods

low power unsigned divider and square root circuit designs using adaptive approximation in this paper an adaptive approximation approach is proposed for the design of a divider and a square root sqr circuit in this design the division sqr is computed by using a reduced width divider sqr circuit and a shifter by adaptively pruning some insignificant input bits specifically for a 2n n 2n n division 2k 2k and k k k n k n consecutive bits are selected starting from the most significant 1 in the dividend and divisor respectively at the same time redundant least significant bits lsbs are truncated or if the number of remaining bits after pruning is smaller than the number of bits to be kept 0 s are appended to the lsbs of the inputs to avoid overflow a 2 k 1 k 1 2 k 1 k 1 divider is used to compute the 2k k 2k k division finally an error correction circuit is proposed to recover the error caused by the shifter using or gates for a 2n 2n bit approximate sqr circuit similar pruning schemes are used to obtain a 2k 2k bit radicand a 2k 2k bit sqr circuit and a shifter are then utilized to compute the sqr this adaptive operation leads to very small maximum error distances of the approximate divider and sqr circuits as shown by a theoretical error analysis the proposed 16 8 approximate divider using an 8 4 exact array divider is 2 5 times 2 5 as fast but only consumes 34 42 percent of the power of the accurate design compared to the accurate 16 bit array sqr circuit the approximate design with a 6 bit radicand is 3 9 times 3 9 as fast and consumes 20 66 percent of the power the approximate sqr circuit using a 6 bit lookup table based sqr circuit consumes 7 15 percent of the power of its corresponding accurate design the proposed designs outperform other approximate designs in image processing applications including change detection for the divider envelope detection for the sqr circuit and image reconstruction for both designs

a fast segmentation algorithm for piecewise polynomial numeric function generators we give an efficient algorithm for partitioning the domain of a numeric function f into segments the function f is realized as a polynomial in each segment and a lookup table stores the coefficients of the polynomial such an algorithm is an essential part of the design of lookup table methods ercepovac et al 2000 5 lee et al 2003 7 nagayama et al 2007 12 paul et al 2007 6 and sasao et al 2004 8 for realizing numeric functions such as sin px ln x and ln x our algorithm requires many fewer steps than a previous algorithm given in frenzen et al 2010 10 and makes tractable the design of numeric function generators based on table lookup for high accuracy applications we show that an estimate of segment width based on local derivatives greatly reduces the search needed to determine the exact segment width we apply the new algorithm to a suite of 15 numeric functions and show that the estimates are sufficiently accurate to produce a minimum or near minimum number of computational steps

power and area efficient unified computation of vector and elementary functions for handheld 3d graphics systems a unified computation method of vector and elementary functions is proposed for handheld 3d graphics systems it unifies vector operations like vector multiply multiply and add divide divide by square root and dot product and elementary functions like trigonometric inverse trigonometric hyperbolic inverse hyperbolic power xy with two variables and logarithm to an arbitrary base into a single four way arithmetic platform a number system called the fixed point hybrid number system fxp hns which combines the fixed point number system fxp and the logarithmic number system lns is proposed for the power and area efficient unification power and area efficient logarithmic and antilogarithmic conversion schemes are also proposed for the data conversions between fixed point and logarithmic numbers in the fxp hns and achieve 0 41 percent and 0 08 percent maximum conversion errors respectively the unified arithmetic unit based on the proposed schemes is presented with less than 6 3 percent operation error its fully pipelined architecture achieves single cycle throughput with maximum four cycle latency for all of the supported operations comparison results show that the proposed arithmetic unit achieves 30 percent power and 10 9 percent area reductions and runs two times faster than the previous approach

radix 4 square rot without initial pla a systematic derivation of a radix 4 square root algorithm using redundant residual and result is presented unlike other similar schemes it does not use a table lookup or pla for the initial step resulting in a simpler implementation without any time penalty the scheme can be integrated with division and incorporates an on the fly conversion and rounding of the result thus eliminating a carry propagate step to obtain the final result the result digit selection uses 3 bits of the result and 7 bits of the estimate of the residual

unified mixed radix 2 4 redundant cordic processor we present a unified mixed radix cordic algorithm with carry save arithmetic with a constant scale factor the pipelined architecture of the processor is determined by a unique sequence of microrotations for the two modes of operation rotation and vectoring in circular and hyperbolic coordinates the combination of radix 2 and radix 4 microrotations allows us to reduce the latency and size of the pipeline significantly the unified algorithm is based on the correcting microrotation method which we have extended to the vectoring mode in hyperbolic coordinates we have also generalized the use of radix 4 microrotations to the two operation modes and coordinate systems

measuring the accuracy of rom reciprocal tables we prove that a convenient rom reciprocal table construction algorithm generates tables that minimize the relative error the worst case relative errors realized for such optimally computed k bits in m bits out rom reciprocal tables are then determined for all table sizes 3 spl les k m spl les 12 we next prove the table construction algorithm always generates a k bits in k bits out table with relative errors never any greater than 3 4 2 sup k and more generally with g guard bits that for k g bits out the relative error is never any greater than 2 k 1 1 1 2g 1 to provide for determining extreme case test data and to compute the precision of a reciprocal table without prior construction of the full rom reciprocal table we describe a procedure that requires generation and inspection of only a small portion of such a table to identify input values guaranteed to include the worst case relative errors in the table

copositivity and constrained fractional quadratic problems we provide completely positive and copositive optimization formulations for the constrained fractional quadratic problem cfqp and standard fractional quadratic problem stfqp based on these formulations semidefinite programming relaxations are derived for finding good lower bounds to these fractional programs which can be used in a global optimization branch and bound approach applications of the cfqp and stfqp related with the correction of infeasible linear systems and eigenvalue complementarity problems are also discussed

very high radix circular cordic vectoring and unified rotation vectoring a very high radix algorithm and implementation for circular cordic is presented we first present in depth the algorithm for the vectoring mode in which the selection of the digits is performed by rounding of the control variable to assure convergence with this kind of selection the operands are prescaled however in the cordic algorithm the coordinate x varies during the execution so several scalings might be needed we show that two scalings are sufficient moreover the compensation of the variable scale factor including the cordic scale factor and the prescaling factors is done by computing the logarithm of the scale factor and performing the compensation by an exponential then we combine in a unified unit the proposed vectoring algorithm and the very high radix rotation algorithm which was previously proposed by the authors we compare with low radix implementations in terms of latency and hardware complexity estimations of the delay for 32 bit precision show a speedup of about two with respect to the radix 4 case with redundant addition this speedup is obtained at the cost of an increase in the hardware complexity which is moderate for the pipelined implementation we also compare at the algorithmic level with other very high radix proposals demonstrating the advantages of our algorithms

long term memory in stock market prices a test for long term memory that is robust to short range dependence is developed it is a modification of the r s statistic and the relevant asymptotic sampling theory is derived via functional central limit theory contrary to previous findings when applied to daily and monthly stock returns indexes over several time periods this test yields no evidence of long range dependence once short range dependence is accounted for monte carlo experiments show that the modified r s test has power against at least two specific models of long term memory suggesting that models with short range dependence may adequately capture the behavior of historical stock returns copyright 1991 by the econometric society

fractionally integrated process for transition economics we analyze the european transition economics and show that many time series of major indices exhibit i power law correlations in their values ii power law correlations in their magnitudes and iii an asymmetric probability distribution applying the phase randomization procedure to these time series we show that magnitude correlations completely vanish we propose a stochastic model that can generate time series with features i ii and iii and we show by means of numerical simulations that this model is capable of reproducing these three features found in the empirical data

choices of operand truncation in the srt division algorithm the paper presents an analysis of the number of partial remainder digits and divisor bits that must be examined in the srt division algorithm the number of examined digits is found to be the same for both signed digit and 2s complement partial remainder representations and appears to increase as 3log sub 2 r approximately where r is the radix of the divider in some cases it proves advantageous to examine a fractional number of remainder digits by inspecting more positive than negative bits

fast hardware based algorithms for elementary function computations using rectangular multipliers as the name suggests elementary functions play a vital role in scientific computations yet due to their inherent nature they are a considerable computing task by themselves not surprisingly since the dawn of computing the goal of speeding up elementary function computation has been pursued this paper describes new hardware based algorithms for the computation of the common elementary functions namely division logarithm reciprocal square root arc tangent sine and cosine these algorithms exploit microscopic parallelism using specialized hardware with heavy use of truncation based on detailed accuracy analysis the contribution of this work lies in the fact that these algorithms are very fast and yet are accurate if we let the time to perform an ieee standard 754 double precision floating point multiplication be spl tau sub spl times our algorithms to achieve roughly 3 68 spl tau sub spl times 4 56 spl tau sub spl times 5 25 spl tau sub spl times 3 69 spl tau sub spl times 7 06 spl tau sub spl times and 6 5 spl tau sub spl times for division logarithm square root exponential are tangent and complex exponential sine and cosine respectively the trade off is the need for tables and some specialized hardware the total amount of tables required however is less than 128 kbytes we discuss the hardware algorithmic and accuracy aspects of these algorithms

simple radix 4 division with operands scaling a radix 4 division algorithm with operands scaling is proposed the algorithm uses a recurrence with redundant addition carry save or signed digit and combines simple scaling with a quotient selection function that depends only on the estimate of the partial remainder and is independent of the divisor the scheme results in a significant speedup with respect to both the radix 2 and radix 4 without scaling

design of a hih speed square root multiply and divide unit in this paper radix 4 algorithms for square root and division are developed the division algorithm evaluates the more useful function xz y these algorithms are shown to be suitable for implementing as a unified hardware unit which evaluates square root division and multiplication cost reductions in the hardware are obtained by use of gate arrays a design based on the motorola mca2500 series of macrocell gate array mca is presented at a cost of 9 mca s and 16 commercial ecl 100 k parts a 64 bit square root can be evaluated in 750 us using worst case delays division takes 710 ns and multiplication 325 ns redundancy in the digit set together with carry save adders are used to achieve this high performance

a systematic method for division with high average bit skipping it is shown that if a division is described by aq c where a is the divisor q is the quotient and c is the dividend then the bit variables involved in a set of equations each of which determines a leading bit of c gives an approximation for q that an be used in a srt division scheme the results of an exhaustive statistical simulation using all possible combinations of two pairs of integers 12 b in length in normalized form representing a and c are presented to validate the method

parallel high radix nonrestoring division an algorithm for high radix nonrestoring division is proposed which combines a cost efficient quotient estimation technique with collapsing of the division into one operation each iteration the quotient estimation technique is a direct combinatorial algorithm which allows a more generalized partial remainder than similar studies in addition the successor partial remainder is calculated directly from the previous partial remainder the intermediate steps of calculating the next quotient estimate multiplying it by the divisor and then subtracting the result from the previous remainder are telescoped into one step this is possible due to the use of simple direct combinatorial equations for the quotient estimate thus one operation is used to generate the next remainder from the previous remainder this operation is similar to a multiplication with a reduced carry propagate adder this algorithm reduces the latency of each iteration to less than the delay of one multiplication thus high radix nonrestoring division is possible with a low latency and no need for an off chip rom to hold a quotient estimate

redundant cordic methods with a constant scale factor for sine and cosine computation proposes two redundant cordic coordinate rotation digital computer methods with a constant scale factor for sine and cosine computation called the double rotation method and the correcting rotation method in both methods the cordic is accelerated by the use of a redundant binary number representation as in the previously proposed redundant cordic in the proposed methods since the number of rotation extensions performed for each angle is a constant the scale factor is a constant independent of the operand hence one does not need to calculate the scale factor during the computation and can make a more efficient sine and cosine generator than that based on the previous redundant cordic

tight upper bounds on the minimum precision required of the divisor and the partial remainder in high radix division digit recurrence binary dividers are sped up via two complementary methods keeping the partial remainder in redundant form and selecting the quotient digits in a radix higher than 2 use of a redundant partial remainder replaces the standard addition in each cycle by a carry free addition thus making the cycles shorter deriving the quotient in high radix reduces the number of cycles by a factor of about h for radix 2 sup h to make the redundant partial remainder scheme work quotient digits must be chosen from a redundant set such as 2 2 in radix 4 the redundancy provides some tolerance to imprecision so that the quotient digits can be selected based on examining truncated versions of the partial remainder and divisor no closed form formula for the required precision in the partial remainder and divisor as a function of the quotient digit set and the range of the partial remainder is known we establish tight upper bounds on the required precision for the partial remainder and divisor the bounds are tight in the sense that each is only one bit over a well known simple lower bound we also discuss the implications of these bounds for the quotient digit selection process

signed digit addition and related operations with threshold logic assuming signed digit number representations we investigate the implementation of some addition related operations assuming linear threshold networks we measure the depth and size of the networks in terms of linear threshold gates we show first that a depth 2 network with o n size weight and fan in complexities can perform signed digit symmetric functions consequently assuming radix 2 signed digit representation we show that the two operand addition can be performed by a threshold network of depth 2 having o n size complexity and o 1 weight and fan in complexities furthermore we show that assuming radix 2n 1 signed digit representations the multioperand addition can be computed by a depth 2 network with o n sup 3 size with the weight and fan in complexities being polynomially bounded finally we show that multiplication can be performed by a linear threshold network of depth 3 with the size of o n sup 3 requiring o n sup 3 weights and o n sup 2 log n fan in

fast evaluation of the elementary functions in single precision in this paper we introduce a new method for the fast evaluation of the elementary functions in single precision based on the evaluation of truncated taylor series using a difference method we assume the availability of large and fast at least for read purposes memory we call this method the ata add table lookup add method as the name implies the hardware required for the method are adders both two and multi operand adders and fast tables for ieee single precision numbers our initial estimates indicate that we can calculate the basic elementary functions namely reciprocal square root logarithm exponential trigonometric and inverse trigonometric functions within the latency of two to four floating point multiplies

hardware starting approximation method and its application to the square root operation quadratically converging algorithms for high order arithmetic operations typically are accelerated by a starting approximation the higher the precision of the starting approximation the less number of iterations required for convergence traditional methods have used look up tables or polynomial approximations or a combination of the two called piecewise linear approximations this paper provides a revision and major extension to our study 1993 proposing a nontraditional method for reusing the hardware of a multiplier an approximation is described in the form of partial product array ppa composed of boolean elements the boolean elements are chosen such that their sum is a high precision approximation to a high order arithmetic operation such as square root reciprocal division logarithm exponential and trigonometric functions this paper derives a ppa that produces in the worst case a 16 bit approximation to the square root operation the implementation of the ppa utilizes an existing 53 bit multiplier design requiring approximately 1 000 dedicated logic gates of function additional repowering circuits and has a latency of one multiplication

higher radix square rooting a general discussion on nonrestoring square root algorithms is presented showing bounds and constraints delimiting the space of feasible algorithms for all the choices of radix digit set and representation of the partial remainder two classes of algorithms are then derived from the general discussion and it is shown how it is possible to determine two parameters with a relevant impact on the implementation the number of radicand bits to be inspected in order to obtain a starting value and the number of partial remainder bits to be examined for digit selection the algorithms for the specific case of radix 4 digit set 2 1 0 1 2 and partial remainder represented in carry save form are derived in order to show that the algorithms introduced can lead to better results than those obtained with algorithms previously presented

over redundant digit sets and the design of digit by digit division units over redundant digit sets are defined as those ranging from spl minus s to s with s spl ges b b being the radix this paper presents new techniques for the direct computation of division that use an over redundant digit set for representing the quotient instead of simply redundant ones used previously in particular general criteria for synthesizing the digit selection rules and remainder updating are given for any radix and index of redundancy a methodology combining the use of over redundant digit sets with the prescaling of the divisor is also studied in order to achieve radix b division units with trivial digit selection functions it is also shown for the specific case of radix 4 that using a prescaling slightly wider than in a radix 4 unit by m d ercegovac and t lang 1990 possible to avoid the digit selection table the paper also presents a modified algorithm for on the fly conversion of the result into the irredundant form the proposed methodology can be considered as an alternative to existing division techniques

on the fly rounding computing arithmetic in implementations of operations based on digit recurrence algorithms such as division left to right multiplication and square root the result is obtained in digit serial form from most significant digit to least significant to reduce the complexity of the result digit selection and allow the use of redundant addition the result digit has values from a signed digit set as a consequence the result has to be converted to conventional representation which can be done on the fly as the digits are produced without the use of a carry propagate adder the authors describe three ways to modify this conversion process so that the result is rounded the resulting operation is fast because no carry propagate addition is needed the schemes described apply also to online arithmetic operations

high speed vlsi multiplication algorithm with a redundant binary addition tree a high speed vlsi multiplication algorithm internally using redundant binary representation is proposed in n bit binary integer multiplication n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders since parallel addition of two n digit redundant binary numbers can be performed in a constant time independent of n without carry propagation n bit multiplication can be performed in a time proportional to log2 n the computation time is almost the same as that by a multiplier with a wallace tree in which three partial products will be converted into two in contrast to our two to one conversion and is much shorter than that by an array multiplier for longer operands the number of computation elements of an n bit multiplier based on the algorithm is proportional to n2 it is almost the same as those of conventional ones furthermore since the multiplier has a regular cellular array structure similar to an array multiplier it is suitable for vlsi implementation thus the multiplier is excellent in both computation speed and regularity in layout it can be implemented on a vlsi chip with an area proportional to n2 log2 n the algorithm can be directly applied to both unsigned and 2 s complement binary integer multiplication

cones of matrices and set functions and 0 1 optimization it has been recognized recently that to represent a polyhedron as the projection of a higher dimensional but simpler polyhedron is a powerful tool in polyhedral combinatorics a general method is developed to construct higher dimensional polyhedra or in some cases convex sets whose projection approximates the convex hull of 0 1 valued solutions of a system of linear inequalities an important feature of these approximations is that one can optimize any linear objective function over them in polynomial time in the special case of the vertex packing polytope a sequence of systems of inequalities is obtained such that the first system already includes clique odd hole odd antihole wheel and orthogonality constraints in particular for perfect and many other graphs this first system gives the vertex packing polytope for various classes of graphs including t perfect graphs it follows that the stable set polytope is the projection of a polytope with a polynomial number of facets an extension o

multiplicative division employing independent factors we introduce a division procedure where a normalized quotient approximation is derived as a product of four independent closed form factors specific derivations of the method for ieee 754 standard binary single and double precision division are developed in detail theoretical error bounds are derived to prove correctness for obtaining properly rounded single precision quotients by rounding the product of these four factors the proofs include exhaustive verification for the single precision extremal cases for double precision quotient approximations the error bounds verify suitable accuracy so that further determination of the remainder sign is sufficient to obtain precisely rounded double precision quotients selected experimental results are provided to illustrate the double precision level quotient approximations a prescaling process is introduced to reduce the table size requirements for these double precision approximations to less than 5 kbytes

a low latency pipelined 2d and 3d cordic processors the unfolded and pipelined cordic is a high performance hardware element that produces a wide variety of one and two argument functions with high throughput the reduction in delay power and area cost are of significant interest regarding this module due to its high demand for resources the linear approximation to rotation has been proposed to achieve such reductions however the schemes for rotation multiplication and vectoring division complicate the implementation in a single unit in this work we improve the linear approximation scheme leading to a unified implementation for rotation and vectoring where fully parallel tree multipliers are used instead of the second half of cordic iterations we also combine the linear approximation to rotation with the scale factor compensation so that the compensation is concurrently performed with the rotation process we then extend the method to 3d cordic such an extension is not straightforward due to the lack of existing analytical expressions for the convergence of the algorithm a comparison using a rough area time model and synthesis results shows that our proposals may achieve significant reductions in delay with no increase in area in actual implementations

fractionally integrated generalized autoregressive conditional heteroskedasticity abstract the new class of fractionally integrated generalized autoregressive conditionally heteroskedastic figarch processes is introduced the conditional variance of the process implies a slow hyperbolic rate of decay for the influence of lagged squared innovations unlike i d processes for the mean maximum likelihood estimates mle of the figarch parameters are argued to be t 1 2 consistent the small sample behavior of an approximate mle procedure is assessed through a simulation study which also documents how the estimation of a standard garch model tends to produce integrated or igarch like estimates an empirical example with daily deutschmark u s dollar exchange rates illustrates the practical relevance of the new figarch specification

higher radix square root with prescaling a scheme for performing higher radix square root based on prescaling of the radicand is presented to reduce the complexity of the result digit selection the scheme requires several steps namely multiplication for prescaling the radicand square root multiplication for prescaling for the division and division online algorithms are used to reduce the overall time and pipelining to reuse the different modules an estimate of the execution time for a radix 256 unit for double precision square root and a comparison with other implementations indicate that the proposed approach is an alternative to consider when designing a square root unit

a unified architecture for the accurate and high throughput implementation of six key elementary functions this paper presents a unified architecture for the compact implementation of several key elementary functions including reciprocal square root and logarithm in single precision floating point arithmetic the proposed high throughput design is based on uniform domain segmentation and curve fitting techniques numerically accurate least squares regression is utilized to calculate the polynomial coefficients the architecture is optimized by analyzing the trade off between the size of the required memory and the precision of intermediate variables to achieve the minimum 23 bit accuracy required for single precision floating point representation the efficiency of the proposed unified data path is demonstrated on a common field programmable gate array

toward correctly rounded transcendentals the table maker s dilemma is the problem of always getting correctly rounded results when computing the elementary functions after a brief presentation of this problem we present new developments that have helped us to solve this problem for the double precision exponential function in a small domain these new results show that this problem can be solved at least for the double precision format for the most usual functions

modeling persistence in hydrological time series using fractional differencing the class of autoregressive integrated moving average arima time series models may be generalized by permitting the degree of differencing d to take fractional values models including fractional differencing are capable of representing persistent series d 0 or short memory series d 0 the class of fractionally differenced arima processes provides a more flexible way than has hitherto been available of simultaneously modeling the long term and short term behavior of a time series in this paper some fundamental properties of fractionally differenced arima processes are presented methods of simulating these processes are described estimation of the parameters of fractionally differenced arima models is discussed and an approximate maximum likelihood method is proposed the methodology is illustrated by fitting fractionally differenced models to time series of streamflows and annual temperatures

on the fly conversion of redundant into conventional representations an algorithm to convert redundant number representations into conventional representations is presented the algorithm is performed concurrently with the digit by digit generation of redundant forms by schemes such as srt division it has a step delay roughly equivalent to the delay of a carry save adder and simple implementation the conversion scheme is applicable in arithmetic algorithms such as nonrestoring division square root and on line operations in which redundantly represented results are generated in a digit by digit manner from most significant to least significant

radix 4 reciprocal square root and its combination with division and square root in this work we present a reciprocal square root algorithm by digit recurrence and selection by a staircase function and the radix 4 implementation as in similar algorithms for division and square root the results are obtained correctly rounded in a straightforward manner in contrast to existing methods to compute the reciprocal square root although apparently a single selection function can only be used for j spl ges 2 the selection constants are different for j 0 j 1 and j spl ges 2 we show that it is possible to use a single selection function for all iterations we perform a rough comparison with existing methods and we conclude that our implementation is a low hardware complexity solution with moderate latency especially for exactly rounded results we also extend the unit to support division and square root with the same selection function and with slight modifications in the initialization of the reciprocal square root unit

generalized autoregressive conditional heteroskedasticity a natural generalization of the arch autoregressive conditional heteroskedastic process introduced in engle 1982 to allow for past conditional variances in the current conditional variance equation is proposed stationarity conditions and autocorrelation structure for this new class of parametric models are derived maximum likelihood estimation and testing are also considered finally an empirical example relating to the uncertainty of the inflation rate is presented

digit recurrence dividers with reduced logical depth in this paper we propose a class of division algorithms with the aim of reducing the delay of the selection of the quotient digit by introducing more concurrency and flexibility in its computation from the proposed class of algorithms we select one that moves part of the selection function out of the critical path with a corresponding reduction in the critical path compared with existing alternatives we present the algorithm and describe the architectures for radix 4 and for radix 16 for radix 16 we use the scheme of overlapping two radix 4 stages in both cases radix 4 and radix 16 we show that our algorithms allow the design of units with well balanced critical paths with consequent decreases of the cycle times moreover in the radix 16 case we include some additional speculation techniques to estimate the speedup we used a rough timing model based on logical effort for both radices we estimate a speedup of about 25 percent with respect to previous implementations in the radix 4 case this is achieved by using roughly the same area while in the radix 16 case the area is increased by about 30 percent we verified our estimations by performing a synthesis of the radix 4 units

weak linear bilevel programming problems existence of solutions via a penalty method we are concerned with a class of weak linear bilevel programs with nonunique lower level solutions for such problems we give via an exact penalty method an existence theorem of solutions then we propose an algorithm

an exact penalty on bilevel programs with linear vector optimization lower level we are interested in a class of linear bilevel programs where the upper level is a linear scalar optimization problem and the lower level is a linear multi objective optimization problem we approach this problem via an exact penalty method then we propose an algorithm illustrated by numerical examples

hard wired multipliers with encoded partial products a multibit overlapped scanning multiplication algorithm for sign magnitude and two s complement hard wired multipliers is presented the theorems necessary to construct the multiplication matrix for sign magnitude representations are emphasized consequently the algorithm for sign magnitude multiplication and its variation to include two s complement numbers are presented the proposed algorithm is compared to previous algorithms that generate a sign extended partial product matrix with an implementation and with a study of the number of elements in the partial product matrix the proposed algorithm is shown to yield significant savings over well known algorithms for the generation and the reduction of the partial product matrix of a multiplier designed with multibit overlapped scanning

fast division using accurate quotient approximations to reduce the number of iterations a class of iterative integer division algorithms is presented based on look up table and taylor series approximations to the reciprocal the algorithm iterates by using the reciprocal to find an approximate quotient and then subtracting the quotient multiplied by the divisor from the dividend to find a remaining dividend fast implementations can produce an average of either 14 or 27 b per iteration depending on whether the basic or advanced version of this method is implemented detailed analyses are presented to support the claimed accuracy per iteration speed estimates using state of the art ecl components show that this method is faster than the newton raphson technique and can produce 53 b quotients of 53 b numbers in about 25 ns using the basic method and 21 ns using the advanced method in addition these methods naturally produce an exact remainder which is very useful for implementing precise rounding specifications

radix 2 division with over redundant quotient selection in this paper we present a new radix 2 division algorithm that uses a recurrence employing simple 3 to 2 digit carry free adders to perform carry free addition subtraction for computing the partial remainders in radix 2 signed digit form the quotient digit during any iteration of the division recursion is generated from the two most significant radix 2 digits of the partial remainder and independent of the divisor in over redundant radix 2 digit form i e with digits which belong to the digit set 2 1 0 1 2 the over redundant quotient digits are then converted to the conventional radix 2 digits belonging to the set 1 0 1 by using a reduction technique this division algorithm is well suited for ieee 754 standard operands belonging to the range 1 2 and is slightly faster than previously proposed radix 2 designs such as the radix 2 srt which do not employ input scaling since the quotient selection for such algorithms is a function of more than two most significant radix 2 digits of the partial remainder in comparison with the designs that employ input scaling the proposed design although slightly slower saves hardware required for scaling purposes

variable neighborhood search principles and applications abstract systematic change of neighborhood within a possibly randomized local search algorithm yields a simple and effective metaheuristic for combinatorial and global optimization called variable neighborhood search vns we present a basic scheme for this purpose which can easily be implemented using any local search algorithm as a subroutine its effectiveness is illustrated by solving several classical combinatorial or global optimization problems moreover several extensions are proposed for solving large problem instances using vns within the successive approximation method yields a two level vns called variable neighborhood decomposition search vnds modifying the basic scheme to explore easily valleys far from the incumbent solution yields an efficient skewed vns svns heuristic finally we show how to stabilize column generation algorithms with help of vns and discuss various ways to use vns in graph theory i e to suggest disprove or give hints on how to prove conjectures an area where metaheuristics do not appear to have been applied before

quantifying and modeling long range cross correlations in multiple time series with applications to world stock indices we propose a modified time lag random matrix theory in order to study time lag cross correlations in multiple time series we apply the method to 48 world indices one for each of 48 different countries we find long range power law cross correlations in the absolute values of returns that quantify risk and find that they decay much more slowly than cross correlations between the returns the magnitude of the cross correlations constitutes bad news for international investment managers who may believe that risk is reduced by diversifying across countries we find that when a market shock is transmitted around the world the risk decays very slowly we explain these time lag cross correlations by introducing a global factor model gfm in which all index returns fluctuate in response to a single global factor for each pair of individual time series of returns the cross correlations between returns or magnitudes can be modeled with the autocorrelations of the global factor returns or magnitudes we estimate the global factor using principal component analysis which minimizes the variance of the residuals after removing the global trend using random matrix theory a significant fraction of the world index cross correlations can be explained by the global factor which supports the utility of the gfm we demonstrate applications of the gfm in forecasting risks at the world level and infinding uncorrelated individual indices we find ten indices that are practically uncorrelated with the global factor and with the remainder of the world indices which is relevant information for world managers in reducing their portfolio risk finally we argue that this general method can be applied to a wide range of phenomena in which time series are measured ranging from seismology and physiology to atmospheric geophysics

improved decimal floating point logarithmic converter based on selection by rounding this paper presents the algorithm and architecture of the decimal floating point dfp logarithmic converter based on the digit recurrence algorithm with selection by rounding the proposed approach can compute faithful dfp logarithm results for any one of the three dfp formats specified in the ieee 754 2008 standard in order to optimize the latency for the proposed design we mainly integrate the following novel features 1 using the redundant carry save representation of the data path 2 reducing the number of iterations by determining the number of initial iteration and 3 retiming and balancing the delay of the proposed architecture the proposed architecture is synthesized with stm 90 nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed decimal64 logarithmic converter are 1 55 ns 34 4 fo4 and 19 respectively and the total hardware complexity is 43 572 nand2 gates the delay estimation results of the proposed architecture show that its latency is close to that of the binary radix 16 logarithmic converter and that it has a significant decrease on latency compared with a recently published high performance cordic implementation

high speed function approximation using a minimax quadratic interpolator a table based method for high speed function approximation in single precision floating point format is presented in this paper our focus is the approximation of reciprocal square root square root reciprocal exponentials logarithms trigonometric functions powering with a fixed exponent p or special functions the algorithm presented here combines table look up an enhanced minimax quadratic approximation and an efficient evaluation of the second degree polynomial using a specialized squaring unit redundant arithmetic and multioperand addition the execution times and area costs of an architecture implementing our method are estimated showing the achievement of the fast execution times of linear approximation methods and the reduced area requirements of other second degree interpolation algorithms moreover the use of an enhanced minimax approximation which through an iterative process takes into account the effect of rounding the polynomial coefficients to a finite size allows for a further reduction in the size of the look up tables to be used making our method very suitable for the implementation of an elementary function generator in state of the art dsps or graphics processing units gpus

a remark on reducing iteration time when result digit is zero for radix 2 srt division and square root with redundant remainders in a previous paper by p montuschi and l ciminiera ibid vol 42 no 2 p239 246 feb 1993 an architecture for shared radix 2 division and square root has been presented whose main characteristic is the ability to avoid any addition subtraction when the digit 0 has been selected here we emphasize the characteristics of the digit selection mechanism used by montuschi and ciminiera by presenting a small modification of the digit selection hardware which has the benefit to further reduce the computation delay with respect to the time estimated in that work

new svoboda tung division the paper presents a general theory for developing new svoboda tung or simply nst division algorithms not suffering the drawbacks of the classical svoboda tung or simply st method nst avoids the drawbacks of st by proper recoding of the two most significant digits of the residual before selecting the most significant digit of this recoded residual as the quotient digit nst relies on the divisor being in the range 1 1 spl delta where spl delta is a positive fraction depending upon 1 the radix 2 the signed digit set used to represent the residual and 3 the recoding conditions of the two most significant digits of the residual if the operands belong to the ieee std range 1 2 they have to be conveniently prescaled in that case nst produces the correct quotient but the final residual is scaled by the same factor as the operands therefore nst is not useful in applications where the unsealed residual is necessary an analysis of nst shows that previously published algorithms can be derived from the general theory proposed in the paper moreover nst reveals a spectrum of new possibilities for the design of alternative division units for a given radix b the number of different algorithms of this kind is b sup 2 4

on the copositive representation of binary and continuous nonconvex quadratic programs in this paper we model any nonconvex quadratic program having a mix of binary and continuous variables as a linear program over the dual of the cone of copositive matrices this result can be viewed as an extension of earlier separate results which have established the copositive representation of a small collection of np hard problems a simplification which reduces the dimension of the linear conic program and an extension to complementarity constraints are established and computational issues are discussed

algorithm architecture and floating point unit codesign of a matrix factorization accelerator this paper examines the mapping of algorithms encountered when solving dense linear systems and linear least squares problems to a custom linear algebra processor specifically the focus is on cholesky lu with partial pivoting and qr factorizations and their blocked algorithms as part of the study we expose the benefits of redesigning floating point units and their surrounding data paths to support these complicated operations we show how adding moderate complexity to the architecture greatly alleviates complexities in the algorithm we study design tradeoffs and the effectiveness of architectural modifications to demonstrate that we can improve power and performance efficiency to a level that can otherwise only be expected of full custom asic designs a feasibility study of inner kernels is extended to blocked level and shows that at block level the linear algebra core lac can achieve high efficiencies with up to 45 gflops w for both cholesky and lu factorization and over 35 gflops w for qr factorization while maintaining such efficiencies our extensions to the mac units can achieve up to 10 12 and 20 percent speedup for the blocked algorithms of cholesky lu and qr factorization respectively

a new approach for solving linear bilevel problems using genetic algorithms bilevel programming involves two optimization problems where the constraint region of the first level problem is implicitly determined by another optimization problem this paper develops a genetic algorithm for the linear bilevel problem in which both objective functions are linear and the common constraint region is a polyhedron taking into account the existence of an extreme point of the polyhedron which solves the problem the algorithm aims to combine classical extreme point enumeration techniques with genetic search methods by associating chromosomes with extreme points of the polyhedron the numerical results show the efficiency of the proposed algorithm in addition this genetic algorithm can also be used for solving quasiconcave bilevel problems provided that the second level objective function is linear

very high radix square root with prescaling and rounding and a combined division square root unit an algorithm for square root with prescaling and selection by rounding is developed and combined with a similar scheme for division since division is usually more frequent than square root the main concern of the combined implementation is to maintain the low execution time of division while accepting a somewhat larger execution time for square root the algorithm is presented in detail including the mathematical development of bounds for the first square root digit and for the scaling factor the proposed implementation is described evaluated and compared with other combined div sqrt units the comparisons show that the proposed scheme potentially produces a significant speed up for division whereas for square root the speed up is small

a cost effective pipelined divider with a small lookup table current pipelinable dividers require very large lookup tables we propose a cost effective pipelinable divider that uses a modified taylor series expansion and has a smaller lookup table than other pipelinable dividers the proposed divider requires about 27 percent less area than the pipelinable divider based on normal taylor series expansion in single precision

approximating elementary functions with symmetric bipartite tables this paper presents a high speed method for function approximation that employs symmetric bipartite tables this method performs two parallel table lookups to obtain a carry save borrow save function approximation which is either converted to a two s complement number or is booth encoded compared to previous methods for bipartite table approximations this method uses less memory by taking advantage of symmetry and leading zeros in one of the two tables it also has a closed form solution for the table entries provides tight bounds on the maximum absolute error and can be applied to a wide range of functions a variation of this method provides accurate initial approximations that are useful in multiplicative divide and square root algorithms

digit serial methods with applications to division and square root we present a generic digit serial method dsm to compute the digits of a real number v bounds on these digits and on the errors in the associated estimates of v formed from these digits are derived to illustrate our results we derive such bounds for a parameterized family of high radix algorithms for division and square root these bounds enable a dsm designer to determine for example whether a given choice of parameters allows rapid formation and rounding of its approximation to v