FR 3135825 A1 20231124 FR 2204715 A 20220518 A method of making a semiconductor structure, the method comprises: - providing a silicon on insulator (SOI) substrate comprising a first epitaxial layer and a bulk silicon substrate separated by a buried oxide layer; - performing a local oxidation of silicon (LOCOS) process in a region of said SOI substrate to at least partially oxidise said first epitaxial silicon layer in said region; - locally etching the SOI substrate in said region to create a trench through said buried oxide layer and to said bulk silicon substrate; - forming a second epitaxial layer on said bulk silicon substrate in said trench; and - forming one or more semiconductor devices in said first and second epitaxial layers. Refer to: Fig. 1 Semiconductor Fabrication Process The present disclosure relates to a semiconductor fabrication process, and in particular a process comprising a silicon on insulator (SOI) substrate. Background Silicon on insulator (SOI) technology can provide many advantages compared to bulk silicon technology due to the improved device isolation provided by the buried oxide (BOX) layer. Complementary metal oxide semiconductor (CMOS) technology such as field effect transistors (FETs) can be used to form radio frequency (RF) devices such as low noise amplifiers (LNA). Preferably such devices are formed on a silicon on insulator (SOI) substrate for improved isolation. RF-SOI is the dominant technology for RF-front-end applications in RF mobile, where the application frequencies are However, for high frequency (e.g. > 6 GHz) applications, a bipolar junction transistor (BJT) such as an NPN transistor may be preferable to the equivalent NFET. For example, a SiGe hetero bipolar transistor (HBT) outperforms Si N-MOS transistors with respect to the maximum transit frequency (Ft) and the minimum noise figure (NFmin). A BJT may be implemented together with CMOS technology on bulk Si, which is referred to as BiCMOS. The BiCMOS technology has had modest success in niche applications and is still developing. Summary In accordance with a first aspect of the invention, there is provided a method of making a semiconductor structure, the method comprising: - providing a silicon on insulator (SOI) substrate comprising a first epitaxial layer and a bulk silicon substrate separated by a buried oxide layer; - performing a local oxidation of silicon (LOCOS) process in a region of said SOI substrate to at least partially oxidise said first epitaxial silicon layer in said region; - locally etching the SOI substrate in said region to create a trench through said buried oxide layer and to said bulk silicon substrate; - forming a second epitaxial layer on said bulk silicon substrate in said trench; and - forming one or more semiconductor devices in said first and second epitaxial layers. In a development of the first aspect, said step of forming one or more semiconductor devices comprises forming a SiGe device in said second epitaxial layer. In a development of the first aspect, said step of forming one or more semiconductor devices comprises forming a bipolar junction transistor (BJT) in said second epitaxial layer. In a development of the first aspect, said step of forming one or more semiconductor devices comprises forming one or more CMOS devices in said first epitaxial layer located over said buried oxide layer. In a development of the first aspect, said method further comprises performing a second local oxidation of silicon process to fully oxidise said first epitaxial silicon layer in said region. In a development of the first aspect, the or each local oxidation of silicon process comprises one or more of the following steps in the following order: - depositing a nitride hard mask layer on said substrate; - depositing an oxide layer on said substrate; - depositing a photoresist on said substrate, and patterning said photoresist to define said region. In a development of the first aspect, said local oxidation of silicon process partially oxidises said first epitaxial layer in said region and thereby forms an oxide layer on said first epitaxial layer in said region. The method further comprises etching said region to remove said oxide layer on said first epitaxial layer to expose said first epitaxial layer in said region. In a development of the first aspect, said method further comprises after the or each local oxidation of silicon process, depositing a nitride hard mask layer and a photoresist on said substrate, and patterning said nitride hard mask and said photoresist to define a trench region in said region. In a development of the first aspect, said step of locally etching comprises performing a dry etch in said trench region to etch through a part but not through the whole of said buried oxide layer. In a development of the first aspect, said step of locally etching comprises a wet etch to etch through a remaining part of said buried oxide layer in said trench region to expose said bulk silicon substrate. In a development of the first aspect, said step of forming a second epitaxial layer comprises forming said second epitaxial layer to have a thickness greater than a combined thickness of said buried oxide layer and said first epitaxial layer. In a development of the first aspect, said method further comprises after forming said second epitaxial layer, performing chemical mechanical planarization (CMP) to level an upper surface of said second epitaxial layer. In a development of the first aspect, said method further comprises providing shallow trench isolation (STI) to provide lateral isolation at least between said first and second epitaxial layers. In a development of the first aspect, said step of forming one or more semiconductor devices comprises selectively doping said first and second epitaxial layers. In accordance with a second aspect of the invention, there is provided a semiconductor structure formed by the method according to any development of the first aspect of the invention. Specific embodiments of the method will now be described with reference to the accompanying drawings. Brief description of the drawings shows a schematic diagram of a cross section of a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a first step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a second step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a third step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a fourth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a fifth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a sixth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a seventh step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in an eighth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a ninth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a tenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in an eleventh step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a twelfth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a thirteenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a fourteenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a fifteenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a sixteenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a seventeenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a seventeenth step of forming a semiconductor structure according to an embodiment; shows a schematic diagram of a cross section of a substrate in a nineteenth step of forming a semiconductor structure according to an embodiment; and shows a flow diagram illustrating the steps of a method of forming a semiconductor structure according to an embodiment. A method of making a semiconductor structure, the method comprising: - providing a silicon on insulator (SOI) substrate (4) comprising a first epitaxial layer (10) and a bulk silicon substrate (6) separated by a buried oxide layer (8); - performing a local oxidation of silicon (LOCOS) process in a region (30) of said silicon on insulator substrate (4) to at least partially oxidise said first epitaxial silicon layer (10) in said region (30); - locally etching the silicon on insulator substrate (4) in said region (30) to create a trench (16) through said buried oxide layer (8) and to said bulk silicon substrate (6); - forming a second epitaxial layer (40) on said bulk silicon substrate (6) in said trench (16); and - forming one or more semiconductor devices in said first and second epitaxial layers. A method according to claim 1, wherein said step of forming one or more semiconductor devices comprises forming a SiGe device in said second epitaxial layer (40). A method according to claim 1 or 2, wherein said step of forming one or more semiconductor devices comprises forming a bipolar junction transistor BJT in said second epitaxial layer (40). A method according to claim 1, 2 or 3, wherein said step of forming one or more semiconductor devices comprises forming one or more CMOS devices in said first epitaxial layer (10) located over said buried oxide layer (8). A method according to any one of the preceding claims, further comprising performing a second local oxidation of silicon process to fully oxidise said first epitaxial silicon layer (10) in said region. A method according to any one of the preceding claims, wherein the or each local oxidation of silicon process comprises one or more of the following steps in the following order: - depositing a nitride hard mask layer on said substrate; - depositing an oxide layer on said substrate; - depositing a photoresist on said substrate, and patterning said photoresist to define said region. A method according to any one of the preceding claims, wherein said local oxidation of silicon process partially oxidises said first epitaxial layer (10) in said region and thereby forms an oxide layer on said first epitaxial layer (10) in said region, the method further comprising etching said region to remove said oxide layer on said first epitaxial layer to expose said first epitaxial layer in said region. A method according to any one of the preceding claims, further comprising, after the or each local oxidation of silicon process, depositing a nitride hard mask layer and a photoresist on said substrate, and patterning said nitride hard mask and said photoresist to define a trench region in said region. A method according to claim 8, wherein said step of locally etching comprises performing a dry etch in said trench region (30) to etch through a part but not through the whole of said buried oxide layer (8). A method according to claim 9, wherein said step of locally etching comprises a wet etch to etch through a remaining part of said buried oxide layer in said trench region to expose said bulk silicon substrate (6). A method according to any one of the preceding claims, wherein said step of forming a second epitaxial layer (40) comprises forming said second epitaxial layer (40) to have a thickness greater than a combined thickness of said buried oxide layer (8) and said first epitaxial layer (10). A method according to any one of the preceding claims, further comprising, after forming said second epitaxial layer (40), performing chemical mechanical planarization CMP to level an upper surface of said second epitaxial layer. A method according to any one of the preceding claims, further comprising providing shallow trench isolation STI (50, 52) to provide lateral isolation at least between said first (10) and second (40) epitaxial layers. A method according to any one of the preceding claims, wherein said step of forming one or more semiconductor devices comprises selectively doping said first (10) and second (40) epitaxial layers. A semiconductor structure (2) formed by the method of any one of the preceding claims.